1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 #define ICE_RXQ_CTX_SIZE_DWORDS 8 16 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) 17 18 typedef struct __packed { u8 buf[ICE_RXQ_CTX_SZ]; } ice_rxq_ctx_buf_t; 19 20 /* The Tx queue context is 40 bytes, and includes some internal state. The 21 * Admin Queue buffers don't include the internal state, so only include the 22 * first 22 bytes of the context. 23 */ 24 #define ICE_TXQ_CTX_SZ 22 25 26 typedef struct __packed { u8 buf[ICE_TXQ_CTX_SZ]; } ice_txq_ctx_buf_t; 27 28 #define ICE_TXQ_CTX_FULL_SIZE_DWORDS 10 29 #define ICE_TXQ_CTX_FULL_SZ \ 30 (ICE_TXQ_CTX_FULL_SIZE_DWORDS * sizeof(u32)) 31 32 typedef struct __packed { u8 buf[ICE_TXQ_CTX_FULL_SZ]; } ice_txq_ctx_buf_full_t; 33 34 struct ice_aqc_generic { 35 __le32 param0; 36 __le32 param1; 37 __le32 addr_high; 38 __le32 addr_low; 39 }; 40 41 /* Get version (direct 0x0001) */ 42 struct ice_aqc_get_ver { 43 __le32 rom_ver; 44 __le32 fw_build; 45 u8 fw_branch; 46 u8 fw_major; 47 u8 fw_minor; 48 u8 fw_patch; 49 u8 api_branch; 50 u8 api_major; 51 u8 api_minor; 52 u8 api_patch; 53 }; 54 55 /* Send driver version (indirect 0x0002) */ 56 struct ice_aqc_driver_ver { 57 u8 major_ver; 58 u8 minor_ver; 59 u8 build_ver; 60 u8 subbuild_ver; 61 u8 reserved[4]; 62 __le32 addr_high; 63 __le32 addr_low; 64 }; 65 66 /* Queue Shutdown (direct 0x0003) */ 67 struct ice_aqc_q_shutdown { 68 u8 driver_unloading; 69 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 70 u8 reserved[15]; 71 }; 72 73 /* Request resource ownership (direct 0x0008) 74 * Release resource ownership (direct 0x0009) 75 */ 76 struct ice_aqc_req_res { 77 __le16 res_id; 78 #define ICE_AQC_RES_ID_NVM 1 79 #define ICE_AQC_RES_ID_SDP 2 80 #define ICE_AQC_RES_ID_CHNG_LOCK 3 81 #define ICE_AQC_RES_ID_GLBL_LOCK 4 82 __le16 access_type; 83 #define ICE_AQC_RES_ACCESS_READ 1 84 #define ICE_AQC_RES_ACCESS_WRITE 2 85 86 /* Upon successful completion, FW writes this value and driver is 87 * expected to release resource before timeout. This value is provided 88 * in milliseconds. 89 */ 90 __le32 timeout; 91 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 92 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 93 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 94 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 95 /* For SDP: pin ID of the SDP */ 96 __le32 res_number; 97 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 98 __le16 status; 99 #define ICE_AQ_RES_GLBL_SUCCESS 0 100 #define ICE_AQ_RES_GLBL_IN_PROG 1 101 #define ICE_AQ_RES_GLBL_DONE 2 102 u8 reserved[2]; 103 }; 104 105 /* Get function capabilities (indirect 0x000A) 106 * Get device capabilities (indirect 0x000B) 107 */ 108 struct ice_aqc_list_caps { 109 u8 cmd_flags; 110 u8 pf_index; 111 u8 reserved[2]; 112 __le32 count; 113 __le32 addr_high; 114 __le32 addr_low; 115 }; 116 117 /* Device/Function buffer entry, repeated per reported capability */ 118 struct ice_aqc_list_caps_elem { 119 __le16 cap; 120 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 121 #define ICE_AQC_CAPS_SRIOV 0x0012 122 #define ICE_AQC_CAPS_VF 0x0013 123 #define ICE_AQC_CAPS_VSI 0x0017 124 #define ICE_AQC_CAPS_DCB 0x0018 125 #define ICE_AQC_CAPS_RSS 0x0040 126 #define ICE_AQC_CAPS_RXQS 0x0041 127 #define ICE_AQC_CAPS_TXQS 0x0042 128 #define ICE_AQC_CAPS_MSIX 0x0043 129 #define ICE_AQC_CAPS_FD 0x0045 130 #define ICE_AQC_CAPS_1588 0x0046 131 #define ICE_AQC_CAPS_MAX_MTU 0x0047 132 #define ICE_AQC_CAPS_NVM_VER 0x0048 133 #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049 134 #define ICE_AQC_CAPS_OROM_VER 0x004A 135 #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B 136 #define ICE_AQC_CAPS_NET_VER 0x004C 137 #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D 138 #define ICE_AQC_CAPS_RDMA 0x0051 139 #define ICE_AQC_CAPS_SENSOR_READING 0x0067 140 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 141 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 142 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 143 #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085 144 #define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087 145 #define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092 146 #define ICE_AQC_BIT_ROCEV2_LAG 0x01 147 #define ICE_AQC_BIT_SRIOV_LAG 0x02 148 149 u8 major_ver; 150 u8 minor_ver; 151 /* Number of resources described by this capability */ 152 __le32 number; 153 /* Only meaningful for some types of resources */ 154 __le32 logical_id; 155 /* Only meaningful for some types of resources */ 156 __le32 phys_id; 157 __le64 rsvd1; 158 __le64 rsvd2; 159 }; 160 161 /* Manage MAC address, read command - indirect (0x0107) 162 * This struct is also used for the response 163 */ 164 struct ice_aqc_manage_mac_read { 165 __le16 flags; /* Zeroed by device driver */ 166 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 167 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 168 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 169 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 170 #define ICE_AQC_MAN_MAC_READ_S 4 171 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 172 u8 rsvd[2]; 173 u8 num_addr; /* Used in response */ 174 u8 rsvd1[3]; 175 __le32 addr_high; 176 __le32 addr_low; 177 }; 178 179 /* Response buffer format for manage MAC read command */ 180 struct ice_aqc_manage_mac_read_resp { 181 u8 lport_num; 182 u8 addr_type; 183 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 184 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 185 u8 mac_addr[ETH_ALEN]; 186 }; 187 188 /* Manage MAC address, write command - direct (0x0108) */ 189 struct ice_aqc_manage_mac_write { 190 u8 rsvd; 191 u8 flags; 192 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 193 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 194 #define ICE_AQC_MAN_MAC_WR_S 6 195 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 196 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 197 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 198 /* byte stream in network order */ 199 u8 mac_addr[ETH_ALEN]; 200 __le32 addr_high; 201 __le32 addr_low; 202 }; 203 204 /* Clear PXE Command and response (direct 0x0110) */ 205 struct ice_aqc_clear_pxe { 206 u8 rx_cnt; 207 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 208 u8 reserved[15]; 209 }; 210 211 /* Get switch configuration (0x0200) */ 212 struct ice_aqc_get_sw_cfg { 213 /* Reserved for command and copy of request flags for response */ 214 __le16 flags; 215 /* First desc in case of command and next_elem in case of response 216 * In case of response, if it is not zero, means all the configuration 217 * was not returned and new command shall be sent with this value in 218 * the 'first desc' field 219 */ 220 __le16 element; 221 /* Reserved for command, only used for response */ 222 __le16 num_elems; 223 __le16 rsvd; 224 __le32 addr_high; 225 __le32 addr_low; 226 }; 227 228 /* Each entry in the response buffer is of the following type: */ 229 struct ice_aqc_get_sw_cfg_resp_elem { 230 /* VSI/Port Number */ 231 __le16 vsi_port_num; 232 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 233 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 234 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 235 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 236 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 237 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 238 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 239 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 240 241 /* SWID VSI/Port belongs to */ 242 __le16 swid; 243 244 /* Bit 14..0 : PF/VF number VSI belongs to 245 * Bit 15 : VF indication bit 246 */ 247 __le16 pf_vf_num; 248 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 249 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 250 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 251 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 252 }; 253 254 /* Loopback port parameter mode values. */ 255 enum ice_local_fwd_mode { 256 ICE_LOCAL_FWD_MODE_ENABLED = 0, 257 ICE_LOCAL_FWD_MODE_DISABLED = 1, 258 ICE_LOCAL_FWD_MODE_PRIORITIZED = 2, 259 }; 260 261 /* Set Port parameters, (direct, 0x0203) */ 262 struct ice_aqc_set_port_params { 263 __le16 cmd_flags; 264 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 265 __le16 bad_frame_vsi; 266 __le16 swid; 267 #define ICE_AQC_PORT_SWID_VALID BIT(15) 268 #define ICE_AQC_PORT_SWID_M 0xFF 269 u8 local_fwd_mode; 270 #define ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID BIT(2) 271 u8 reserved[9]; 272 }; 273 274 /* These resource type defines are used for all switch resource 275 * commands where a resource type is required, such as: 276 * Get Resource Allocation command (indirect 0x0204) 277 * Allocate Resources command (indirect 0x0208) 278 * Free Resources command (indirect 0x0209) 279 * Get Allocated Resource Descriptors Command (indirect 0x020A) 280 * Share Resource command (indirect 0x020B) 281 */ 282 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 283 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 284 #define ICE_AQC_RES_TYPE_RECIPE 0x05 285 #define ICE_AQC_RES_TYPE_SWID 0x07 286 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 287 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 288 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 289 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 290 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 291 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 292 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 293 294 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 295 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 296 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 297 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14) 298 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15) 299 300 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 301 302 #define ICE_AQC_RES_TYPE_S 0 303 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 304 305 /* Allocate Resources command (indirect 0x0208) 306 * Free Resources command (indirect 0x0209) 307 * Share Resource command (indirect 0x020B) 308 */ 309 struct ice_aqc_alloc_free_res_cmd { 310 __le16 num_entries; /* Number of Resource entries */ 311 u8 reserved[6]; 312 __le32 addr_high; 313 __le32 addr_low; 314 }; 315 316 /* Resource descriptor */ 317 struct ice_aqc_res_elem { 318 union { 319 __le16 sw_resp; 320 __le16 flu_resp; 321 } e; 322 }; 323 324 /* Buffer for Allocate/Free Resources commands */ 325 struct ice_aqc_alloc_free_res_elem { 326 __le16 res_type; /* Types defined above cmd 0x0204 */ 327 #define ICE_AQC_RES_TYPE_SHARED_S 7 328 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 329 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 330 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 331 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 332 __le16 num_elems; 333 struct ice_aqc_res_elem elem[]; 334 }; 335 336 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 337 struct ice_aqc_set_vlan_mode { 338 u8 reserved; 339 u8 l2tag_prio_tagging; 340 #define ICE_AQ_VLAN_PRIO_TAG_S 0 341 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 342 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 343 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 344 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 345 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 346 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 347 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 348 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 349 u8 l2tag_reserved[64]; 350 u8 rdma_packet; 351 #define ICE_AQ_VLAN_RDMA_TAG_S 0 352 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 353 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 354 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 355 u8 rdma_reserved[2]; 356 u8 mng_vlan_prot_id; 357 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 358 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 359 u8 prot_id_reserved[30]; 360 }; 361 362 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 363 struct ice_aqc_get_vlan_mode { 364 u8 vlan_mode; 365 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 366 u8 l2tag_prio_tagging; 367 u8 reserved[98]; 368 }; 369 370 /* Add VSI (indirect 0x0210) 371 * Update VSI (indirect 0x0211) 372 * Get VSI (indirect 0x0212) 373 * Free VSI (indirect 0x0213) 374 */ 375 struct ice_aqc_add_get_update_free_vsi { 376 __le16 vsi_num; 377 #define ICE_AQ_VSI_NUM_S 0 378 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 379 #define ICE_AQ_VSI_IS_VALID BIT(15) 380 __le16 cmd_flags; 381 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 382 u8 vf_id; 383 u8 reserved; 384 __le16 vsi_flags; 385 #define ICE_AQ_VSI_TYPE_S 0 386 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 387 #define ICE_AQ_VSI_TYPE_VF 0x0 388 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 389 #define ICE_AQ_VSI_TYPE_PF 0x2 390 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 391 __le32 addr_high; 392 __le32 addr_low; 393 }; 394 395 /* Response descriptor for: 396 * Add VSI (indirect 0x0210) 397 * Update VSI (indirect 0x0211) 398 * Free VSI (indirect 0x0213) 399 */ 400 struct ice_aqc_add_update_free_vsi_resp { 401 __le16 vsi_num; 402 __le16 ext_status; 403 __le16 vsi_used; 404 __le16 vsi_free; 405 __le32 addr_high; 406 __le32 addr_low; 407 }; 408 409 struct ice_aqc_vsi_props { 410 __le16 valid_sections; 411 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 412 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 413 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 414 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 415 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 416 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 417 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 418 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 419 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 420 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 421 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 422 /* switch section */ 423 u8 sw_id; 424 u8 sw_flags; 425 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 426 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 427 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 428 u8 sw_flags2; 429 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 430 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 431 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 432 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 433 u8 veb_stat_id; 434 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 435 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 436 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 437 /* security section */ 438 u8 sec_flags; 439 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 440 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 441 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 442 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 443 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 444 u8 sec_reserved; 445 /* VLAN section */ 446 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 447 u8 inner_vlan_reserved[2]; 448 u8 inner_vlan_flags; 449 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 450 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 451 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 452 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 453 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 454 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 455 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 456 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 457 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH 0x0U 458 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP 0x1U 459 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR 0x2U 460 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING 0x3U 461 u8 inner_vlan_reserved2[3]; 462 /* ingress egress up sections */ 463 __le32 ingress_table; /* bitmap, 3 bits per up */ 464 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 465 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 466 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 467 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 468 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 469 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 470 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 471 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 472 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 473 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 474 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 475 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 476 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 477 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 478 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 479 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 480 __le32 egress_table; /* same defines as for ingress table */ 481 /* outer tags section */ 482 __le16 port_based_outer_vlan; 483 u8 outer_vlan_flags; 484 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 485 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 486 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 487 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 488 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 489 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 490 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 491 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 492 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 493 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 494 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 495 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 496 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 497 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 498 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 499 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 500 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 501 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 502 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 503 u8 outer_vlan_reserved; 504 /* queue mapping section */ 505 __le16 mapping_flags; 506 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 507 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 508 __le16 q_mapping[16]; 509 #define ICE_AQ_VSI_Q_S 0 510 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 511 __le16 tc_mapping[8]; 512 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 513 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 514 #define ICE_AQ_VSI_TC_Q_NUM_S 11 515 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 516 /* queueing option section */ 517 u8 q_opt_rss; 518 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 519 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 520 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 521 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 522 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 523 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 524 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 525 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 526 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6) 527 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ 0x0U 528 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ 0x1U 529 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR 0x2U 530 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH 0x3U 531 u8 q_opt_tc; 532 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 533 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 534 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 535 u8 q_opt_flags; 536 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 537 u8 q_opt_reserved[3]; 538 /* outer up section */ 539 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 540 /* section 10 */ 541 __le16 sect_10_reserved; 542 /* flow director section */ 543 __le16 fd_options; 544 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 545 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 546 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 547 __le16 max_fd_fltr_dedicated; 548 __le16 max_fd_fltr_shared; 549 __le16 fd_def_q; 550 #define ICE_AQ_VSI_FD_DEF_Q_S 0 551 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 552 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 553 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 554 __le16 fd_report_opt; 555 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 556 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 557 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 558 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 559 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 560 /* PASID section */ 561 __le32 pasid_id; 562 #define ICE_AQ_VSI_PASID_ID_S 0 563 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 564 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 565 u8 reserved[24]; 566 }; 567 568 #define ICE_MAX_NUM_RECIPES 64 569 570 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 571 struct ice_aqc_add_get_recipe { 572 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 573 __le16 return_index; /* Input, used for Get cmd only */ 574 u8 reserved[4]; 575 __le32 addr_high; 576 __le32 addr_low; 577 }; 578 579 struct ice_aqc_recipe_content { 580 u8 rid; 581 #define ICE_AQ_RECIPE_ID_S 0 582 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 583 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 584 #define ICE_AQ_SW_ID_LKUP_IDX 0 585 u8 lkup_indx[5]; 586 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 587 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 588 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 589 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 590 __le16 mask[5]; 591 u8 result_indx; 592 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 593 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 594 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 595 u8 rsvd0[3]; 596 u8 act_ctrl_join_priority; 597 u8 act_ctrl_fwd_priority; 598 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 599 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 600 u8 act_ctrl; 601 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 602 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 603 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 604 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 605 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 606 u8 rsvd1; 607 __le32 dflt_act; 608 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 609 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 610 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 611 }; 612 613 struct ice_aqc_recipe_data_elem { 614 u8 recipe_indx; 615 u8 resp_bits; 616 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 617 u8 rsvd0[2]; 618 u8 recipe_bitmap[8]; 619 u8 rsvd1[4]; 620 struct ice_aqc_recipe_content content; 621 u8 rsvd2[20]; 622 }; 623 624 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 625 struct ice_aqc_recipe_to_profile { 626 __le16 profile_id; 627 u8 rsvd[6]; 628 __le64 recipe_assoc; 629 }; 630 static_assert(sizeof(struct ice_aqc_recipe_to_profile) == 16); 631 632 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 633 */ 634 struct ice_aqc_sw_rules { 635 /* ops: add switch rules, referring the number of rules. 636 * ops: update switch rules, referring the number of filters 637 * ops: remove switch rules, referring the entry index. 638 * ops: get switch rules, referring to the number of filters. 639 */ 640 __le16 num_rules_fltr_entry_index; 641 u8 reserved[6]; 642 __le32 addr_high; 643 __le32 addr_low; 644 }; 645 646 /* Add switch rule response: 647 * Content of return buffer is same as the input buffer. The status field and 648 * LUT index are updated as part of the response 649 */ 650 struct ice_aqc_sw_rules_elem_hdr { 651 __le16 type; /* Switch rule type, one of T_... */ 652 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 653 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 654 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 655 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 656 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 657 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 658 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 659 __le16 status; 660 } __packed __aligned(sizeof(__le16)); 661 662 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 663 * This structures describes the lookup rules and associated actions. "index" 664 * is returned as part of a response to a successful Add command, and can be 665 * used to identify the rule for Update/Get/Remove commands. 666 */ 667 struct ice_sw_rule_lkup_rx_tx { 668 struct ice_aqc_sw_rules_elem_hdr hdr; 669 670 __le16 recipe_id; 671 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 672 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 673 __le16 src; 674 __le32 act; 675 676 /* Bit 0:1 - Action type */ 677 #define ICE_SINGLE_ACT_TYPE_S 0x00 678 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 679 680 /* Bit 2 - Loop back enable 681 * Bit 3 - LAN enable 682 */ 683 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 684 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 685 686 /* Action type = 0 - Forward to VSI or VSI list */ 687 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 688 689 #define ICE_SINGLE_ACT_VSI_ID_S 4 690 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 691 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 692 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 693 /* This bit needs to be set if action is forward to VSI list */ 694 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 695 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 696 #define ICE_SINGLE_ACT_DROP BIT(18) 697 698 /* Action type = 1 - Forward to Queue of Queue group */ 699 #define ICE_SINGLE_ACT_TO_Q 0x1 700 #define ICE_SINGLE_ACT_Q_INDEX_S 4 701 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 702 #define ICE_SINGLE_ACT_Q_REGION_S 15 703 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 704 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 705 706 /* Action type = 2 - Prune */ 707 #define ICE_SINGLE_ACT_PRUNE 0x2 708 #define ICE_SINGLE_ACT_EGRESS BIT(15) 709 #define ICE_SINGLE_ACT_INGRESS BIT(16) 710 #define ICE_SINGLE_ACT_PRUNET BIT(17) 711 /* Bit 18 should be set to 0 for this action */ 712 713 /* Action type = 2 - Pointer */ 714 #define ICE_SINGLE_ACT_PTR 0x2 715 #define ICE_SINGLE_ACT_PTR_VAL_S 4 716 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 717 /* Bit 18 should be set to 1 */ 718 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 719 720 /* Action type = 3 - Other actions. Last two bits 721 * are other action identifier 722 */ 723 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 724 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 725 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 726 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 727 728 /* Bit 17:18 - Defines other actions */ 729 /* Other action = 0 - Mirror VSI */ 730 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 731 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 732 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 733 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 734 735 /* Other action = 3 - Set Stat count */ 736 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 737 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 738 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 739 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 740 741 __le16 index; /* The index of the rule in the lookup table */ 742 /* Length and values of the header to be matched per recipe or 743 * lookup-type 744 */ 745 __le16 hdr_len; 746 u8 hdr_data[]; 747 } __packed __aligned(sizeof(__le16)); 748 749 /* Add/Update/Remove large action command/response entry 750 * "index" is returned as part of a response to a successful Add command, and 751 * can be used to identify the action for Update/Get/Remove commands. 752 */ 753 struct ice_sw_rule_lg_act { 754 struct ice_aqc_sw_rules_elem_hdr hdr; 755 756 __le16 index; /* Index in large action table */ 757 __le16 size; 758 /* Max number of large actions */ 759 #define ICE_MAX_LG_ACT 4 760 /* Bit 0:1 - Action type */ 761 #define ICE_LG_ACT_TYPE_S 0 762 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 763 764 /* Action type = 0 - Forward to VSI or VSI list */ 765 #define ICE_LG_ACT_VSI_FORWARDING 0 766 #define ICE_LG_ACT_VSI_ID_S 3 767 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 768 #define ICE_LG_ACT_VSI_LIST_ID_S 3 769 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 770 /* This bit needs to be set if action is forward to VSI list */ 771 #define ICE_LG_ACT_VSI_LIST BIT(13) 772 773 #define ICE_LG_ACT_VALID_BIT BIT(16) 774 775 /* Action type = 1 - Forward to Queue of Queue group */ 776 #define ICE_LG_ACT_TO_Q 0x1 777 #define ICE_LG_ACT_Q_INDEX_S 3 778 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 779 #define ICE_LG_ACT_Q_REGION_S 14 780 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 781 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 782 783 /* Action type = 2 - Prune */ 784 #define ICE_LG_ACT_PRUNE 0x2 785 #define ICE_LG_ACT_EGRESS BIT(14) 786 #define ICE_LG_ACT_INGRESS BIT(15) 787 #define ICE_LG_ACT_PRUNET BIT(16) 788 789 /* Action type = 3 - Mirror VSI */ 790 #define ICE_LG_OTHER_ACT_MIRROR 0x3 791 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 792 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 793 794 /* Action type = 5 - Generic Value */ 795 #define ICE_LG_ACT_GENERIC 0x5 796 #define ICE_LG_ACT_GENERIC_VALUE_S 3 797 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 798 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 799 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 800 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 801 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 802 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 803 804 /* Action = 7 - Set Stat count */ 805 #define ICE_LG_ACT_STAT_COUNT 0x7 806 #define ICE_LG_ACT_STAT_COUNT_S 3 807 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 808 __le32 act[]; /* array of size for actions */ 809 } __packed __aligned(sizeof(__le16)); 810 811 /* Add/Update/Remove VSI list command/response entry 812 * "index" is returned as part of a response to a successful Add command, and 813 * can be used to identify the VSI list for Update/Get/Remove commands. 814 */ 815 struct ice_sw_rule_vsi_list { 816 struct ice_aqc_sw_rules_elem_hdr hdr; 817 818 __le16 index; /* Index of VSI/Prune list */ 819 __le16 number_vsi; 820 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 821 } __packed __aligned(sizeof(__le16)); 822 823 /* Query PFC Mode (direct 0x0302) 824 * Set PFC Mode (direct 0x0303) 825 */ 826 struct ice_aqc_set_query_pfc_mode { 827 u8 pfc_mode; 828 /* For Query Command response, reserved in all other cases */ 829 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 830 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 831 u8 rsvd[15]; 832 }; 833 /* Get Default Topology (indirect 0x0400) */ 834 struct ice_aqc_get_topo { 835 u8 port_num; 836 u8 num_branches; 837 __le16 reserved1; 838 __le32 reserved2; 839 __le32 addr_high; 840 __le32 addr_low; 841 }; 842 843 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */ 844 struct ice_aqc_get_set_tx_topo { 845 u8 set_flags; 846 #define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0) 847 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1) 848 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4) 849 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5) 850 851 u8 get_flags; 852 #define ICE_AQC_TX_TOPO_GET_RAM 2 853 854 __le16 reserved1; 855 __le32 reserved2; 856 __le32 addr_high; 857 __le32 addr_low; 858 }; 859 860 /* Update TSE (indirect 0x0403) 861 * Get TSE (indirect 0x0404) 862 * Add TSE (indirect 0x0401) 863 * Delete TSE (indirect 0x040F) 864 * Move TSE (indirect 0x0408) 865 * Suspend Nodes (indirect 0x0409) 866 * Resume Nodes (indirect 0x040A) 867 */ 868 struct ice_aqc_sched_elem_cmd { 869 __le16 num_elem_req; /* Used by commands */ 870 __le16 num_elem_resp; /* Used by responses */ 871 __le32 reserved; 872 __le32 addr_high; 873 __le32 addr_low; 874 }; 875 876 struct ice_aqc_txsched_move_grp_info_hdr { 877 __le32 src_parent_teid; 878 __le32 dest_parent_teid; 879 __le16 num_elems; 880 u8 mode; 881 #define ICE_AQC_MOVE_ELEM_MODE_SAME_PF 0x0 882 #define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN 0x1 883 #define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN 0x2 884 u8 reserved; 885 }; 886 887 struct ice_aqc_move_elem { 888 struct ice_aqc_txsched_move_grp_info_hdr hdr; 889 __le32 teid[]; 890 }; 891 892 struct ice_aqc_elem_info_bw { 893 __le16 bw_profile_idx; 894 __le16 bw_alloc; 895 }; 896 897 struct ice_aqc_txsched_elem { 898 u8 elem_type; /* Special field, reserved for some aq calls */ 899 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 900 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 901 #define ICE_AQC_ELEM_TYPE_TC 0x2 902 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 903 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 904 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 905 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 906 u8 valid_sections; 907 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 908 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 909 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 910 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 911 u8 generic; 912 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 913 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 914 #define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1) 915 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 916 #define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4) 917 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 918 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 919 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 920 u8 flags; /* Special field, reserved for some aq calls */ 921 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 922 struct ice_aqc_elem_info_bw cir_bw; 923 struct ice_aqc_elem_info_bw eir_bw; 924 __le16 srl_id; 925 __le16 reserved2; 926 }; 927 928 struct ice_aqc_txsched_elem_data { 929 __le32 parent_teid; 930 __le32 node_teid; 931 struct ice_aqc_txsched_elem data; 932 }; 933 934 struct ice_aqc_txsched_topo_grp_info_hdr { 935 __le32 parent_teid; 936 __le16 num_elems; 937 __le16 reserved2; 938 }; 939 940 struct ice_aqc_add_elem { 941 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 942 struct ice_aqc_txsched_elem_data generic[]; 943 }; 944 945 struct ice_aqc_get_topo_elem { 946 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 947 struct ice_aqc_txsched_elem_data 948 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 949 }; 950 951 struct ice_aqc_delete_elem { 952 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 953 __le32 teid[]; 954 }; 955 956 /* Query Port ETS (indirect 0x040E) 957 * 958 * This indirect command is used to query port TC node configuration. 959 */ 960 struct ice_aqc_query_port_ets { 961 __le32 port_teid; 962 __le32 reserved; 963 __le32 addr_high; 964 __le32 addr_low; 965 }; 966 967 struct ice_aqc_port_ets_elem { 968 u8 tc_valid_bits; 969 u8 reserved[3]; 970 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 971 __le32 up2tc; 972 u8 tc_bw_share[8]; 973 __le32 port_eir_prof_id; 974 __le32 port_cir_prof_id; 975 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 976 __le32 tc_node_prio; 977 #define ICE_TC_NODE_PRIO_S 0x4 978 u8 reserved1[4]; 979 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 980 }; 981 982 /* Rate limiting profile for 983 * Add RL profile (indirect 0x0410) 984 * Query RL profile (indirect 0x0411) 985 * Remove RL profile (indirect 0x0415) 986 * These indirect commands acts on single or multiple 987 * RL profiles with specified data. 988 */ 989 struct ice_aqc_rl_profile { 990 __le16 num_profiles; 991 __le16 num_processed; /* Only for response. Reserved in Command. */ 992 u8 reserved[4]; 993 __le32 addr_high; 994 __le32 addr_low; 995 }; 996 997 struct ice_aqc_rl_profile_elem { 998 u8 level; 999 u8 flags; 1000 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1001 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1002 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1003 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1004 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1005 /* The following flag is used for Query RL Profile Data */ 1006 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1007 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1008 1009 __le16 profile_id; 1010 __le16 max_burst_size; 1011 __le16 rl_multiply; 1012 __le16 wake_up_calc; 1013 __le16 rl_encode; 1014 }; 1015 1016 /* Query Scheduler Resource Allocation (indirect 0x0412) 1017 * This indirect command retrieves the scheduler resources allocated by 1018 * EMP Firmware to the given PF. 1019 */ 1020 struct ice_aqc_query_txsched_res { 1021 u8 reserved[8]; 1022 __le32 addr_high; 1023 __le32 addr_low; 1024 }; 1025 1026 struct ice_aqc_generic_sched_props { 1027 __le16 phys_levels; 1028 __le16 logical_levels; 1029 u8 flattening_bitmap; 1030 u8 max_device_cgds; 1031 u8 max_pf_cgds; 1032 u8 rsvd0; 1033 __le16 rdma_qsets; 1034 u8 rsvd1[22]; 1035 }; 1036 1037 struct ice_aqc_layer_props { 1038 u8 logical_layer; 1039 u8 chunk_size; 1040 __le16 max_device_nodes; 1041 __le16 max_pf_nodes; 1042 u8 rsvd0[4]; 1043 __le16 max_sibl_grp_sz; 1044 __le16 max_cir_rl_profiles; 1045 __le16 max_eir_rl_profiles; 1046 __le16 max_srl_profiles; 1047 u8 rsvd1[14]; 1048 }; 1049 1050 struct ice_aqc_query_txsched_res_resp { 1051 struct ice_aqc_generic_sched_props sched_props; 1052 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1053 }; 1054 1055 /* Get PHY capabilities (indirect 0x0600) */ 1056 struct ice_aqc_get_phy_caps { 1057 u8 lport_num; 1058 u8 reserved; 1059 __le16 param0; 1060 /* 18.0 - Report qualified modules */ 1061 #define ICE_AQC_GET_PHY_RQM BIT(0) 1062 /* 18.1 - 18.3 : Report mode 1063 * 000b - Report NVM capabilities 1064 * 001b - Report topology capabilities 1065 * 010b - Report SW configured 1066 * 100b - Report default capabilities 1067 */ 1068 #define ICE_AQC_REPORT_MODE_S 1 1069 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1070 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1071 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1072 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1073 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1074 __le32 reserved1; 1075 __le32 addr_high; 1076 __le32 addr_low; 1077 }; 1078 1079 /* This is #define of PHY type (Extended): 1080 * The first set of defines is for phy_type_low. 1081 */ 1082 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1083 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1084 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1085 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1086 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1087 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1088 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1089 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1090 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1091 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1092 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1093 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1094 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1095 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1096 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1097 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1098 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1099 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1100 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1101 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1102 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1103 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1104 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1105 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1106 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1107 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1108 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1109 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1110 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1111 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1112 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1113 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1114 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1115 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1116 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1117 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1118 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1119 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1120 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1121 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1122 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1123 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1124 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1125 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1126 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1127 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1128 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1129 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1130 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1131 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1132 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1133 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1134 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1135 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1136 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1137 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1138 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1139 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1140 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1141 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1142 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1143 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1144 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1145 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1146 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1147 /* The second set of defines is for phy_type_high. */ 1148 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1149 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1150 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1151 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1152 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1153 #define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) 1154 #define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) 1155 #define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) 1156 #define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) 1157 #define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) 1158 #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) 1159 #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) 1160 #define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) 1161 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 12 1162 1163 struct ice_aqc_get_phy_caps_data { 1164 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1165 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1166 u8 caps; 1167 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1168 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1169 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1170 #define ICE_AQC_PHY_EN_LINK BIT(3) 1171 #define ICE_AQC_PHY_AN_MODE BIT(4) 1172 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 1173 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1174 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 1175 u8 low_power_ctrl_an; 1176 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1177 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1178 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1179 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1180 __le16 eee_cap; 1181 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1182 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1183 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1184 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1185 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1186 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1187 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1188 __le16 eeer_value; 1189 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1190 u8 phy_fw_ver[8]; 1191 u8 link_fec_options; 1192 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1193 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1194 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1195 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1196 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1197 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1198 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1199 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1200 u8 module_compliance_enforcement; 1201 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1202 u8 extended_compliance_code; 1203 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1204 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1205 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1206 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1207 #define ICE_AQC_MOD_TYPE_IDENT 1 1208 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1209 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1210 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1211 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1212 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1213 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1214 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1215 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1216 u8 qualified_module_count; 1217 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1218 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1219 struct { 1220 u8 v_oui[3]; 1221 u8 rsvd3; 1222 u8 v_part[16]; 1223 __le32 v_rev; 1224 __le64 rsvd4; 1225 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1226 }; 1227 1228 /* Set PHY capabilities (direct 0x0601) 1229 * NOTE: This command must be followed by setup link and restart auto-neg 1230 */ 1231 struct ice_aqc_set_phy_cfg { 1232 u8 lport_num; 1233 u8 reserved[7]; 1234 __le32 addr_high; 1235 __le32 addr_low; 1236 }; 1237 1238 /* Set PHY config command data structure */ 1239 struct ice_aqc_set_phy_cfg_data { 1240 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1241 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1242 u8 caps; 1243 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1244 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1245 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1246 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1247 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1248 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1249 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1250 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1251 u8 low_power_ctrl_an; 1252 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1253 __le16 eeer_value; 1254 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1255 u8 module_compliance_enforcement; 1256 }; 1257 1258 /* Set MAC Config command data structure (direct 0x0603) */ 1259 struct ice_aqc_set_mac_cfg { 1260 __le16 max_frame_size; 1261 u8 params; 1262 #define ICE_AQ_SET_MAC_PACE_S 3 1263 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1264 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1265 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1266 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1267 u8 tx_tmr_priority; 1268 __le16 tx_tmr_value; 1269 __le16 fc_refresh_threshold; 1270 u8 drop_opts; 1271 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1272 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1273 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1274 u8 reserved[7]; 1275 }; 1276 1277 /* Restart AN command data structure (direct 0x0605) 1278 * Also used for response, with only the lport_num field present. 1279 */ 1280 struct ice_aqc_restart_an { 1281 u8 lport_num; 1282 u8 reserved; 1283 u8 cmd_flags; 1284 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1285 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1286 u8 reserved2[13]; 1287 }; 1288 1289 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1290 struct ice_aqc_get_link_status { 1291 u8 lport_num; 1292 u8 reserved; 1293 __le16 cmd_flags; 1294 #define ICE_AQ_LSE_M 0x3 1295 #define ICE_AQ_LSE_NOP 0x0 1296 #define ICE_AQ_LSE_DIS 0x2 1297 #define ICE_AQ_LSE_ENA 0x3 1298 /* only response uses this flag */ 1299 #define ICE_AQ_LSE_IS_ENABLED 0x1 1300 __le32 reserved2; 1301 __le32 addr_high; 1302 __le32 addr_low; 1303 }; 1304 1305 /* Get link status response data structure, also used for Link Status Event */ 1306 struct ice_aqc_get_link_status_data { 1307 u8 topo_media_conflict; 1308 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1309 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1310 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1311 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1312 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1313 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1314 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1315 u8 link_cfg_err; 1316 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1317 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1318 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1319 u8 link_info; 1320 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1321 #define ICE_AQ_LINK_FAULT BIT(1) 1322 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1323 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1324 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1325 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1326 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1327 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1328 u8 an_info; 1329 #define ICE_AQ_AN_COMPLETED BIT(0) 1330 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1331 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1332 #define ICE_AQ_FEC_EN BIT(3) 1333 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1334 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1335 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1336 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1337 u8 ext_info; 1338 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1339 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1340 /* Port Tx Suspended */ 1341 #define ICE_AQ_LINK_TX_S 2 1342 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1343 #define ICE_AQ_LINK_TX_ACTIVE 0 1344 #define ICE_AQ_LINK_TX_DRAINED 1 1345 #define ICE_AQ_LINK_TX_FLUSHED 3 1346 u8 reserved2; 1347 __le16 max_frame_size; 1348 u8 cfg; 1349 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1350 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1351 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1352 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1353 /* Pacing Config */ 1354 #define ICE_AQ_CFG_PACING_S 3 1355 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1356 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1357 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1358 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1359 /* External Device Power Ability */ 1360 u8 power_desc; 1361 #define ICE_AQ_PWR_CLASS_M 0x3F 1362 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1363 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1364 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1365 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1366 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1367 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1368 __le16 link_speed; 1369 #define ICE_AQ_LINK_SPEED_M 0x7FF 1370 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1371 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1372 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1373 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1374 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1375 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1376 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1377 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1378 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1379 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1380 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1381 #define ICE_AQ_LINK_SPEED_200GB BIT(11) 1382 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1383 /* Aligns next field to 8-byte boundary */ 1384 __le16 reserved3; 1385 u8 ext_fec_status; 1386 /* RS 272 FEC enabled */ 1387 #define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) 1388 u8 reserved4; 1389 /* Use values from ICE_PHY_TYPE_LOW_* */ 1390 __le64 phy_type_low; 1391 /* Use values from ICE_PHY_TYPE_HIGH_* */ 1392 __le64 phy_type_high; 1393 #define ICE_AQC_LS_DATA_SIZE_V1 \ 1394 offsetofend(struct ice_aqc_get_link_status_data, phy_type_high) 1395 /* Get link status v2 link partner data */ 1396 __le64 lp_phy_type_low; 1397 __le64 lp_phy_type_high; 1398 u8 lp_fec_adv; 1399 #define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0) 1400 #define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1) 1401 #define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2) 1402 #define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 1403 #define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 1404 #define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 1405 u8 lp_fec_req; 1406 #define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0) 1407 #define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1) 1408 #define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2) 1409 #define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3) 1410 u8 lp_flowcontrol; 1411 #define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0) 1412 #define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1) 1413 u8 reserved5[5]; 1414 #define ICE_AQC_LS_DATA_SIZE_V2 \ 1415 offsetofend(struct ice_aqc_get_link_status_data, reserved5) 1416 } __packed; 1417 1418 /* Set event mask command (direct 0x0613) */ 1419 struct ice_aqc_set_event_mask { 1420 u8 lport_num; 1421 u8 reserved[7]; 1422 __le16 event_mask; 1423 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1424 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1425 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1426 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1427 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1428 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1429 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1430 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1431 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1432 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1433 u8 reserved1[6]; 1434 }; 1435 1436 /* Set MAC Loopback command (direct 0x0620) */ 1437 struct ice_aqc_set_mac_lb { 1438 u8 lb_mode; 1439 #define ICE_AQ_MAC_LB_EN BIT(0) 1440 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1441 u8 reserved[15]; 1442 }; 1443 1444 /* Set PHY recovered clock output (direct 0x0630) */ 1445 struct ice_aqc_set_phy_rec_clk_out { 1446 u8 phy_output; 1447 u8 port_num; 1448 #define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1449 u8 flags; 1450 #define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1451 u8 rsvd; 1452 __le32 freq; 1453 u8 rsvd2[6]; 1454 __le16 node_handle; 1455 }; 1456 1457 /* Get PHY recovered clock output (direct 0x0631) */ 1458 struct ice_aqc_get_phy_rec_clk_out { 1459 u8 phy_output; 1460 u8 port_num; 1461 #define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1462 u8 flags; 1463 #define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1464 u8 rsvd[11]; 1465 __le16 node_handle; 1466 }; 1467 1468 /* Get sensor reading (direct 0x0632) */ 1469 struct ice_aqc_get_sensor_reading { 1470 u8 sensor; 1471 u8 format; 1472 u8 reserved[6]; 1473 __le32 addr_high; 1474 __le32 addr_low; 1475 }; 1476 1477 /* Get sensor reading response (direct 0x0632) */ 1478 struct ice_aqc_get_sensor_reading_resp { 1479 union { 1480 u8 raw[8]; 1481 /* Output data for sensor 0x00, format 0x00 */ 1482 struct _packed { 1483 s8 temp; 1484 u8 temp_warning_threshold; 1485 u8 temp_critical_threshold; 1486 u8 temp_fatal_threshold; 1487 u8 reserved[4]; 1488 } s0f0; 1489 } data; 1490 }; 1491 1492 /* DNL call command (indirect 0x0682) 1493 * Struct is used for both command and response 1494 */ 1495 struct ice_aqc_dnl_call_command { 1496 u8 ctx; /* Used in command, reserved in response */ 1497 u8 reserved; 1498 __le16 activity_id; 1499 #define ICE_AQC_ACT_ID_DNL 0x1129 1500 __le32 reserved1; 1501 __le32 addr_high; 1502 __le32 addr_low; 1503 }; 1504 1505 struct ice_aqc_dnl_equa_param { 1506 __le16 data_in; 1507 #define ICE_AQC_RX_EQU_SHIFT 8 1508 #define ICE_AQC_RX_EQU_PRE2 (0x10 << ICE_AQC_RX_EQU_SHIFT) 1509 #define ICE_AQC_RX_EQU_PRE1 (0x11 << ICE_AQC_RX_EQU_SHIFT) 1510 #define ICE_AQC_RX_EQU_POST1 (0x12 << ICE_AQC_RX_EQU_SHIFT) 1511 #define ICE_AQC_RX_EQU_BFLF (0x13 << ICE_AQC_RX_EQU_SHIFT) 1512 #define ICE_AQC_RX_EQU_BFHF (0x14 << ICE_AQC_RX_EQU_SHIFT) 1513 #define ICE_AQC_RX_EQU_CTLE_GAINHF (0x20 << ICE_AQC_RX_EQU_SHIFT) 1514 #define ICE_AQC_RX_EQU_CTLE_GAINLF (0x21 << ICE_AQC_RX_EQU_SHIFT) 1515 #define ICE_AQC_RX_EQU_CTLE_GAINDC (0x22 << ICE_AQC_RX_EQU_SHIFT) 1516 #define ICE_AQC_RX_EQU_CTLE_BW (0x23 << ICE_AQC_RX_EQU_SHIFT) 1517 #define ICE_AQC_RX_EQU_DFE_GAIN (0x30 << ICE_AQC_RX_EQU_SHIFT) 1518 #define ICE_AQC_RX_EQU_DFE_GAIN2 (0x31 << ICE_AQC_RX_EQU_SHIFT) 1519 #define ICE_AQC_RX_EQU_DFE_2 (0x32 << ICE_AQC_RX_EQU_SHIFT) 1520 #define ICE_AQC_RX_EQU_DFE_3 (0x33 << ICE_AQC_RX_EQU_SHIFT) 1521 #define ICE_AQC_RX_EQU_DFE_4 (0x34 << ICE_AQC_RX_EQU_SHIFT) 1522 #define ICE_AQC_RX_EQU_DFE_5 (0x35 << ICE_AQC_RX_EQU_SHIFT) 1523 #define ICE_AQC_RX_EQU_DFE_6 (0x36 << ICE_AQC_RX_EQU_SHIFT) 1524 #define ICE_AQC_RX_EQU_DFE_7 (0x37 << ICE_AQC_RX_EQU_SHIFT) 1525 #define ICE_AQC_RX_EQU_DFE_8 (0x38 << ICE_AQC_RX_EQU_SHIFT) 1526 #define ICE_AQC_RX_EQU_DFE_9 (0x39 << ICE_AQC_RX_EQU_SHIFT) 1527 #define ICE_AQC_RX_EQU_DFE_10 (0x3A << ICE_AQC_RX_EQU_SHIFT) 1528 #define ICE_AQC_RX_EQU_DFE_11 (0x3B << ICE_AQC_RX_EQU_SHIFT) 1529 #define ICE_AQC_RX_EQU_DFE_12 (0x3C << ICE_AQC_RX_EQU_SHIFT) 1530 #define ICE_AQC_TX_EQU_PRE1 0x0 1531 #define ICE_AQC_TX_EQU_PRE3 0x3 1532 #define ICE_AQC_TX_EQU_ATTEN 0x4 1533 #define ICE_AQC_TX_EQU_POST1 0x8 1534 #define ICE_AQC_TX_EQU_PRE2 0xC 1535 __le16 op_code_serdes_sel; 1536 #define ICE_AQC_OP_CODE_SHIFT 4 1537 #define ICE_AQC_OP_CODE_RX_EQU (0x9 << ICE_AQC_OP_CODE_SHIFT) 1538 #define ICE_AQC_OP_CODE_TX_EQU (0x10 << ICE_AQC_OP_CODE_SHIFT) 1539 __le32 reserved[3]; 1540 }; 1541 1542 struct ice_aqc_dnl_equa_respon { 1543 /* Equalization value can be negative */ 1544 int val; 1545 __le32 reserved[3]; 1546 }; 1547 1548 /* DNL call command/response buffer (indirect 0x0682) */ 1549 struct ice_aqc_dnl_call { 1550 union { 1551 struct ice_aqc_dnl_equa_param txrx_equa_reqs; 1552 __le32 stores[4]; 1553 struct ice_aqc_dnl_equa_respon txrx_equa_resp; 1554 } sto; 1555 }; 1556 1557 struct ice_aqc_link_topo_params { 1558 u8 lport_num; 1559 u8 lport_num_valid; 1560 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1561 u8 node_type_ctx; 1562 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1563 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1564 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1565 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1566 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1567 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1568 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1569 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1570 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1571 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1572 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1573 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 9 1574 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 10 1575 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS 11 1576 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1577 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1578 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1579 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1580 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1581 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1582 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1583 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1584 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1585 u8 index; 1586 }; 1587 1588 struct ice_aqc_link_topo_addr { 1589 struct ice_aqc_link_topo_params topo_params; 1590 __le16 handle; 1591 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1592 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1593 /* Used to decode the handle field */ 1594 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1595 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1596 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1597 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1598 /* In case of a Mezzanine type */ 1599 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1600 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1601 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1602 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1603 /* In case of a LOM type */ 1604 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1605 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1606 }; 1607 1608 /* Get Link Topology Handle (direct, 0x06E0) */ 1609 struct ice_aqc_get_link_topo { 1610 struct ice_aqc_link_topo_addr addr; 1611 u8 node_part_num; 1612 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1613 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 1614 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25 1615 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30 1616 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31 1617 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 1618 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 1619 u8 rsvd[9]; 1620 }; 1621 1622 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1623 struct ice_aqc_i2c { 1624 struct ice_aqc_link_topo_addr topo_addr; 1625 __le16 i2c_addr; 1626 u8 i2c_params; 1627 #define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0) 1628 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1629 1630 u8 rsvd; 1631 __le16 i2c_bus_addr; 1632 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1633 }; 1634 1635 /* Read I2C Response (direct, 0x06E2) */ 1636 struct ice_aqc_read_i2c_resp { 1637 u8 i2c_data[16]; 1638 }; 1639 1640 /* Set Port Identification LED (direct, 0x06E9) */ 1641 struct ice_aqc_set_port_id_led { 1642 u8 lport_num; 1643 u8 lport_num_valid; 1644 u8 ident_mode; 1645 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1646 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1647 u8 rsvd[13]; 1648 }; 1649 1650 /* Get Port Options (indirect, 0x06EA) */ 1651 struct ice_aqc_get_port_options { 1652 u8 lport_num; 1653 u8 lport_num_valid; 1654 u8 port_options_count; 1655 #define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0) 1656 #define ICE_AQC_PORT_OPT_MAX 16 1657 1658 u8 innermost_phy_index; 1659 u8 port_options; 1660 #define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0) 1661 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1662 1663 u8 pending_port_option_status; 1664 #define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0) 1665 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 1666 1667 u8 rsvd[2]; 1668 __le32 addr_high; 1669 __le32 addr_low; 1670 }; 1671 1672 struct ice_aqc_get_port_options_elem { 1673 u8 pmd; 1674 #define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0) 1675 1676 u8 max_lane_speed; 1677 #define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0) 1678 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1679 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1680 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1681 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1682 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1683 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1684 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1685 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1686 #define ICE_AQC_PORT_OPT_MAX_LANE_200G 8 1687 1688 u8 global_scid[2]; 1689 u8 phy_scid[2]; 1690 u8 pf2port_cid[2]; 1691 }; 1692 1693 /* Set Port Option (direct, 0x06EB) */ 1694 struct ice_aqc_set_port_option { 1695 u8 lport_num; 1696 u8 lport_num_valid; 1697 u8 selected_port_option; 1698 u8 rsvd[13]; 1699 }; 1700 1701 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1702 struct ice_aqc_gpio { 1703 __le16 gpio_ctrl_handle; 1704 #define ICE_AQC_GPIO_HANDLE_S 0 1705 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1706 u8 gpio_num; 1707 u8 gpio_val; 1708 u8 rsvd[12]; 1709 }; 1710 1711 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1712 struct ice_aqc_sff_eeprom { 1713 u8 lport_num; 1714 u8 lport_num_valid; 1715 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1716 __le16 i2c_bus_addr; 1717 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1718 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1719 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1720 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1721 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1722 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1723 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1724 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1725 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1726 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1727 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1728 __le16 i2c_mem_addr; 1729 __le16 eeprom_page; 1730 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1731 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1732 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1733 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1734 __le32 addr_high; 1735 __le32 addr_low; 1736 }; 1737 1738 /* NVM Read command (indirect 0x0701) 1739 * NVM Erase commands (direct 0x0702) 1740 * NVM Update commands (indirect 0x0703) 1741 */ 1742 struct ice_aqc_nvm { 1743 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1744 __le16 offset_low; 1745 u8 offset_high; 1746 u8 cmd_flags; 1747 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1748 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1749 #define ICE_AQC_NVM_PRESERVATION_S 1 1750 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1751 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1752 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1753 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1754 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1755 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1756 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1757 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1758 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1759 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1760 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1761 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1762 #define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */ 1763 #define ICE_AQC_NVM_POR_FLAG 0 1764 #define ICE_AQC_NVM_PERST_FLAG 1 1765 #define ICE_AQC_NVM_EMPR_FLAG 2 1766 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 1767 /* For Write Activate, several flags are sent as part of a separate 1768 * flags2 field using a separate byte. For simplicity of the software 1769 * interface, we pass the flags as a 16 bit value so these flags are 1770 * all offset by 8 bits 1771 */ 1772 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 1773 __le16 module_typeid; 1774 __le16 length; 1775 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1776 __le32 addr_high; 1777 __le32 addr_low; 1778 }; 1779 1780 #define ICE_AQC_NVM_START_POINT 0 1781 #define ICE_AQC_NVM_SECTOR_UNIT 4096 1782 #define ICE_AQC_NVM_SDP_AC_PTR_OFFSET 0xD8 1783 #define ICE_AQC_NVM_SDP_AC_PTR_M GENMASK(14, 0) 1784 #define ICE_AQC_NVM_SDP_AC_PTR_INVAL 0x7FFF 1785 #define ICE_AQC_NVM_SDP_AC_PTR_TYPE_M BIT(15) 1786 #define ICE_AQC_NVM_SDP_AC_SDP_NUM_M GENMASK(2, 0) 1787 #define ICE_AQC_NVM_SDP_AC_DIR_M BIT(3) 1788 #define ICE_AQC_NVM_SDP_AC_PIN_M GENMASK(15, 6) 1789 #define ICE_AQC_NVM_SDP_AC_MAX_SIZE 7 1790 1791 #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B 1792 1793 struct ice_aqc_nvm_tx_topo_user_sel { 1794 __le16 length; 1795 u8 data; 1796 #define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4) 1797 u8 reserved; 1798 }; 1799 1800 /* NVM Checksum Command (direct, 0x0706) */ 1801 struct ice_aqc_nvm_checksum { 1802 u8 flags; 1803 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1804 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1805 u8 rsvd; 1806 __le16 checksum; /* Used only by response */ 1807 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1808 u8 rsvd2[12]; 1809 }; 1810 1811 /* Used for NVM Set Package Data command - 0x070A */ 1812 struct ice_aqc_nvm_pkg_data { 1813 u8 reserved[3]; 1814 u8 cmd_flags; 1815 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1816 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1817 1818 u32 reserved1; 1819 __le32 addr_high; 1820 __le32 addr_low; 1821 }; 1822 1823 /* Used for Pass Component Table command - 0x070B */ 1824 struct ice_aqc_nvm_pass_comp_tbl { 1825 u8 component_response; /* Response only */ 1826 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1827 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1828 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1829 #define ICE_AQ_NVM_PASS_COMP_PARTIAL_CHECK 0x3 1830 u8 component_response_code; /* Response only */ 1831 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1832 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1833 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1834 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1835 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1836 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1837 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1838 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1839 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1840 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1841 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1842 u8 reserved; 1843 u8 transfer_flag; 1844 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1845 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1846 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1847 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1848 __le32 reserved1; 1849 __le32 addr_high; 1850 __le32 addr_low; 1851 }; 1852 1853 struct ice_aqc_nvm_comp_tbl { 1854 __le16 comp_class; 1855 #define NVM_COMP_CLASS_ALL_FW 0x000A 1856 1857 __le16 comp_id; 1858 #define NVM_COMP_ID_OROM 0x5 1859 #define NVM_COMP_ID_NVM 0x6 1860 #define NVM_COMP_ID_NETLIST 0x8 1861 1862 u8 comp_class_idx; 1863 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1864 1865 __le32 comp_cmp_stamp; 1866 u8 cvs_type; 1867 #define NVM_CVS_TYPE_ASCII 0x1 1868 1869 u8 cvs_len; 1870 u8 cvs[]; /* Component Version String */ 1871 } __packed; 1872 1873 /* Send to PF command (indirect 0x0801) ID is only used by PF 1874 * 1875 * Send to VF command (indirect 0x0802) ID is only used by PF 1876 * 1877 */ 1878 struct ice_aqc_pf_vf_msg { 1879 __le32 id; 1880 u32 reserved; 1881 __le32 addr_high; 1882 __le32 addr_low; 1883 }; 1884 1885 /* Get LLDP MIB (indirect 0x0A00) 1886 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1887 * as the format is the same. 1888 */ 1889 struct ice_aqc_lldp_get_mib { 1890 u8 type; 1891 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1892 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1893 #define ICE_AQ_LLDP_MIB_LOCAL 0 1894 #define ICE_AQ_LLDP_MIB_REMOTE 1 1895 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1896 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1897 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1898 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1899 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1900 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1901 #define ICE_AQ_LLDP_TX_S 0x4 1902 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1903 #define ICE_AQ_LLDP_TX_ACTIVE 0 1904 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1905 #define ICE_AQ_LLDP_TX_FLUSHED 3 1906 /* DCBX mode */ 1907 #define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6) 1908 #define ICE_AQ_LLDP_DCBX_NA 0 1909 #define ICE_AQ_LLDP_DCBX_CEE 1 1910 #define ICE_AQ_LLDP_DCBX_IEEE 2 1911 1912 u8 state; 1913 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M BIT(0) 1914 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 1915 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 1916 1917 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1918 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1919 * Get LLDP MIB (0x0A00) response only. 1920 */ 1921 __le16 local_len; 1922 __le16 remote_len; 1923 u8 reserved[2]; 1924 __le32 addr_high; 1925 __le32 addr_low; 1926 }; 1927 1928 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1929 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1930 struct ice_aqc_lldp_set_mib_change { 1931 u8 command; 1932 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1933 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1934 #define ICE_AQ_LLDP_MIB_PENDING_M BIT(1) 1935 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 1936 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 1937 u8 reserved[15]; 1938 }; 1939 1940 /* Stop LLDP (direct 0x0A05) */ 1941 struct ice_aqc_lldp_stop { 1942 u8 command; 1943 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1944 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1945 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1946 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1947 u8 reserved[15]; 1948 }; 1949 1950 /* Start LLDP (direct 0x0A06) */ 1951 struct ice_aqc_lldp_start { 1952 u8 command; 1953 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1954 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1955 u8 reserved[15]; 1956 }; 1957 1958 /* Get CEE DCBX Oper Config (0x0A07) 1959 * The command uses the generic descriptor struct and 1960 * returns the struct below as an indirect response. 1961 */ 1962 struct ice_aqc_get_cee_dcb_cfg_resp { 1963 u8 oper_num_tc; 1964 u8 oper_prio_tc[4]; 1965 u8 oper_tc_bw[8]; 1966 u8 oper_pfc_en; 1967 __le16 oper_app_prio; 1968 #define ICE_AQC_CEE_APP_FCOE_S 0 1969 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1970 #define ICE_AQC_CEE_APP_ISCSI_S 3 1971 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1972 #define ICE_AQC_CEE_APP_FIP_S 8 1973 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1974 __le32 tlv_status; 1975 #define ICE_AQC_CEE_PG_STATUS_S 0 1976 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1977 #define ICE_AQC_CEE_PFC_STATUS_S 3 1978 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1979 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1980 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1981 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1982 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1983 #define ICE_AQC_CEE_FIP_STATUS_S 16 1984 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1985 u8 reserved[12]; 1986 }; 1987 1988 /* Set Local LLDP MIB (indirect 0x0A08) 1989 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1990 */ 1991 struct ice_aqc_lldp_set_local_mib { 1992 u8 type; 1993 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1994 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1995 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1996 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1997 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1998 u8 reserved0; 1999 __le16 length; 2000 u8 reserved1[4]; 2001 __le32 addr_high; 2002 __le32 addr_low; 2003 }; 2004 2005 /* Stop/Start LLDP Agent (direct 0x0A09) 2006 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 2007 * The same structure is used for the response, with the command field 2008 * being used as the status field. 2009 */ 2010 struct ice_aqc_lldp_stop_start_specific_agent { 2011 u8 command; 2012 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 2013 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 2014 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 2015 u8 reserved[15]; 2016 }; 2017 2018 /* LLDP Filter Control (direct 0x0A0A) */ 2019 struct ice_aqc_lldp_filter_ctrl { 2020 u8 cmd_flags; 2021 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 2022 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 2023 u8 reserved1; 2024 __le16 vsi_num; 2025 u8 reserved2[12]; 2026 }; 2027 2028 #define ICE_AQC_RSS_VSI_VALID BIT(15) 2029 2030 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 2031 struct ice_aqc_get_set_rss_key { 2032 __le16 vsi_id; 2033 u8 reserved[6]; 2034 __le32 addr_high; 2035 __le32 addr_low; 2036 }; 2037 2038 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2039 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2040 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2041 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2042 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2043 2044 struct ice_aqc_get_set_rss_keys { 2045 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2046 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2047 }; 2048 2049 enum ice_lut_type { 2050 ICE_LUT_VSI = 0, 2051 ICE_LUT_PF = 1, 2052 ICE_LUT_GLOBAL = 2, 2053 }; 2054 2055 enum ice_lut_size { 2056 ICE_LUT_VSI_SIZE = 64, 2057 ICE_LUT_GLOBAL_SIZE = 512, 2058 ICE_LUT_PF_SIZE = 2048, 2059 }; 2060 2061 /* enum ice_aqc_lut_flags combines constants used to fill 2062 * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID, 2063 * LUT size and LUT type, last of which does not need neither shift nor mask. 2064 */ 2065 enum ice_aqc_lut_flags { 2066 ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */ 2067 ICE_AQC_LUT_SIZE_512 = BIT(2), 2068 ICE_AQC_LUT_SIZE_2K = BIT(3), 2069 2070 ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4), 2071 }; 2072 2073 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2074 struct ice_aqc_get_set_rss_lut { 2075 __le16 vsi_id; 2076 __le16 flags; 2077 __le32 reserved; 2078 __le32 addr_high; 2079 __le32 addr_low; 2080 }; 2081 2082 /* Sideband Control Interface Commands */ 2083 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 2084 struct ice_aqc_neigh_dev_req { 2085 __le16 sb_data_len; 2086 u8 reserved[6]; 2087 __le32 addr_high; 2088 __le32 addr_low; 2089 }; 2090 2091 /* Add Tx LAN Queues (indirect 0x0C30) */ 2092 struct ice_aqc_add_txqs { 2093 u8 num_qgrps; 2094 u8 reserved[3]; 2095 __le32 reserved1; 2096 __le32 addr_high; 2097 __le32 addr_low; 2098 }; 2099 2100 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2101 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2102 */ 2103 struct ice_aqc_add_txqs_perq { 2104 __le16 txq_id; 2105 u8 rsvd[2]; 2106 __le32 q_teid; 2107 ice_txq_ctx_buf_t txq_ctx; 2108 u8 rsvd2[2]; 2109 struct ice_aqc_txsched_elem info; 2110 } __packed; 2111 2112 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2113 * is an array of the following structs. Please note that the length of 2114 * each struct ice_aqc_add_tx_qgrp is variable due 2115 * to the variable number of queues in each group! 2116 */ 2117 struct ice_aqc_add_tx_qgrp { 2118 __le32 parent_teid; 2119 u8 num_txqs; 2120 u8 rsvd[3]; 2121 struct ice_aqc_add_txqs_perq txqs[]; 2122 }; 2123 2124 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2125 struct ice_aqc_dis_txqs { 2126 u8 cmd_type; 2127 #define ICE_AQC_Q_DIS_CMD_S 0 2128 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2129 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2130 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2131 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2132 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2133 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2134 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2135 u8 num_entries; 2136 __le16 vmvf_and_timeout; 2137 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2138 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2139 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2140 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2141 __le32 blocked_cgds; 2142 __le32 addr_high; 2143 __le32 addr_low; 2144 }; 2145 2146 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2147 * contains the following structures, arrayed one after the 2148 * other. 2149 * Note: Since the q_id is 16 bits wide, if the 2150 * number of queues is even, then 2 bytes of alignment MUST be 2151 * added before the start of the next group, to allow correct 2152 * alignment of the parent_teid field. 2153 */ 2154 struct ice_aqc_dis_txq_item { 2155 __le32 parent_teid; 2156 u8 num_qs; 2157 u8 rsvd; 2158 /* The length of the q_id array varies according to num_qs */ 2159 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2160 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2161 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2162 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2163 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2164 __le16 q_id[]; 2165 } __packed; 2166 2167 /* Move/Reconfigure Tx queue (indirect 0x0C32) */ 2168 struct ice_aqc_cfg_txqs { 2169 u8 cmd_type; 2170 #define ICE_AQC_Q_CFG_MOVE_NODE 0x1 2171 #define ICE_AQC_Q_CFG_TC_CHNG 0x2 2172 #define ICE_AQC_Q_CFG_MOVE_TC_CHNG 0x3 2173 #define ICE_AQC_Q_CFG_SUBSEQ_CALL BIT(2) 2174 #define ICE_AQC_Q_CFG_FLUSH BIT(3) 2175 u8 num_qs; 2176 u8 port_num_chng; 2177 #define ICE_AQC_Q_CFG_SRC_PRT_M 0x7 2178 #define ICE_AQC_Q_CFG_DST_PRT_S 3 2179 #define ICE_AQC_Q_CFG_DST_PRT_M (0x7 << ICE_AQC_Q_CFG_DST_PRT_S) 2180 u8 time_out; 2181 #define ICE_AQC_Q_CFG_TIMEOUT_S 2 2182 #define ICE_AQC_Q_CFG_TIMEOUT_M (0x1F << ICE_AQC_Q_CFG_TIMEOUT_S) 2183 __le32 blocked_cgds; 2184 __le32 addr_high; 2185 __le32 addr_low; 2186 }; 2187 2188 /* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2189 struct ice_aqc_cfg_txq_perq { 2190 __le16 q_handle; 2191 u8 tc; 2192 u8 rsvd; 2193 __le32 q_teid; 2194 }; 2195 2196 /* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2197 struct ice_aqc_cfg_txqs_buf { 2198 __le32 src_parent_teid; 2199 __le32 dst_parent_teid; 2200 struct ice_aqc_cfg_txq_perq queue_info[]; 2201 }; 2202 2203 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 2204 struct ice_aqc_add_rdma_qset { 2205 u8 num_qset_grps; 2206 u8 reserved[7]; 2207 __le32 addr_high; 2208 __le32 addr_low; 2209 }; 2210 2211 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 2212 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 2213 */ 2214 struct ice_aqc_add_tx_rdma_qset_entry { 2215 __le16 tx_qset_id; 2216 u8 rsvd[2]; 2217 __le32 qset_teid; 2218 struct ice_aqc_txsched_elem info; 2219 }; 2220 2221 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 2222 * is an array of the following structs. Please note that the length of 2223 * each struct ice_aqc_add_rdma_qset is variable due to the variable 2224 * number of queues in each group! 2225 */ 2226 struct ice_aqc_add_rdma_qset_data { 2227 __le32 parent_teid; 2228 __le16 num_qsets; 2229 u8 rsvd[2]; 2230 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 2231 }; 2232 2233 /* Download Package (indirect 0x0C40) */ 2234 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ 2235 struct ice_aqc_download_pkg { 2236 u8 flags; 2237 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2238 u8 reserved[3]; 2239 __le32 reserved1; 2240 __le32 addr_high; 2241 __le32 addr_low; 2242 }; 2243 2244 struct ice_aqc_download_pkg_resp { 2245 __le32 error_offset; 2246 __le32 error_info; 2247 __le32 addr_high; 2248 __le32 addr_low; 2249 }; 2250 2251 /* Get Package Info List (indirect 0x0C43) */ 2252 struct ice_aqc_get_pkg_info_list { 2253 __le32 reserved1; 2254 __le32 reserved2; 2255 __le32 addr_high; 2256 __le32 addr_low; 2257 }; 2258 2259 /* Version format for packages */ 2260 struct ice_pkg_ver { 2261 u8 major; 2262 u8 minor; 2263 u8 update; 2264 u8 draft; 2265 }; 2266 2267 #define ICE_PKG_NAME_SIZE 32 2268 #define ICE_SEG_ID_SIZE 28 2269 #define ICE_SEG_NAME_SIZE 28 2270 2271 struct ice_aqc_get_pkg_info { 2272 struct ice_pkg_ver ver; 2273 char name[ICE_SEG_NAME_SIZE]; 2274 __le32 track_id; 2275 u8 is_in_nvm; 2276 u8 is_active; 2277 u8 is_active_at_boot; 2278 u8 is_modified; 2279 }; 2280 2281 /* Get Package Info List response buffer format (0x0C43) */ 2282 struct ice_aqc_get_pkg_info_resp { 2283 __le32 count; 2284 struct ice_aqc_get_pkg_info pkg_info[]; 2285 }; 2286 2287 #define ICE_CGU_INPUT_PHASE_OFFSET_BYTES 6 2288 2289 struct ice_cgu_input_measure { 2290 u8 phase_offset[ICE_CGU_INPUT_PHASE_OFFSET_BYTES]; 2291 __le32 freq; 2292 } __packed __aligned(sizeof(__le16)); 2293 2294 #define ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M ICE_M(0xf, 0) 2295 2296 /* Get CGU input measure command response data structure (indirect 0x0C59) */ 2297 struct ice_aqc_get_cgu_input_measure { 2298 u8 dpll_idx_opt; 2299 u8 length; 2300 u8 rsvd[6]; 2301 }; 2302 2303 #define ICE_AQC_GET_CGU_MAX_PHASE_ADJ GENMASK(30, 0) 2304 2305 /* Get CGU abilities command response data structure (indirect 0x0C61) */ 2306 struct ice_aqc_get_cgu_abilities { 2307 u8 num_inputs; 2308 u8 num_outputs; 2309 u8 pps_dpll_idx; 2310 u8 eec_dpll_idx; 2311 __le32 max_in_freq; 2312 __le32 max_in_phase_adj; 2313 __le32 max_out_freq; 2314 __le32 max_out_phase_adj; 2315 u8 cgu_part_num; 2316 u8 rsvd[3]; 2317 }; 2318 2319 #define ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN BIT(7) 2320 2321 /* Set CGU input config (direct 0x0C62) */ 2322 struct ice_aqc_set_cgu_input_config { 2323 u8 input_idx; 2324 u8 flags1; 2325 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6) 2326 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7) 2327 u8 flags2; 2328 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2329 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2330 u8 rsvd; 2331 __le32 freq; 2332 __le32 phase_delay; 2333 u8 rsvd2[2]; 2334 __le16 node_handle; 2335 }; 2336 2337 /* Get CGU input config response descriptor structure (direct 0x0C63) */ 2338 struct ice_aqc_get_cgu_input_config { 2339 u8 input_idx; 2340 u8 status; 2341 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS BIT(0) 2342 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1) 2343 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2) 2344 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3) 2345 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4) 2346 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6) 2347 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7) 2348 u8 type; 2349 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0) 2350 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS BIT(4) 2351 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5) 2352 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY BIT(6) 2353 u8 flags1; 2354 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0) 2355 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2) 2356 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3) 2357 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7) 2358 __le32 freq; 2359 __le32 phase_delay; 2360 u8 flags2; 2361 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2362 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2363 u8 rsvd[1]; 2364 __le16 node_handle; 2365 }; 2366 2367 /* Set CGU output config (direct 0x0C64) */ 2368 struct ice_aqc_set_cgu_output_config { 2369 u8 output_idx; 2370 u8 flags; 2371 #define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN BIT(0) 2372 #define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2373 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2) 2374 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3) 2375 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4) 2376 u8 src_sel; 2377 #define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0) 2378 u8 rsvd; 2379 __le32 freq; 2380 __le32 phase_delay; 2381 u8 rsvd2[2]; 2382 __le16 node_handle; 2383 }; 2384 2385 /* Get CGU output config (direct 0x0C65) */ 2386 struct ice_aqc_get_cgu_output_config { 2387 u8 output_idx; 2388 u8 flags; 2389 #define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN BIT(0) 2390 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2391 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2) 2392 u8 src_sel; 2393 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0 2394 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \ 2395 ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT) 2396 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5 2397 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \ 2398 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT) 2399 u8 rsvd; 2400 __le32 freq; 2401 __le32 src_freq; 2402 u8 rsvd2[2]; 2403 __le16 node_handle; 2404 }; 2405 2406 /* Get CGU DPLL status (direct 0x0C66) */ 2407 struct ice_aqc_get_cgu_dpll_status { 2408 u8 dpll_num; 2409 u8 ref_state; 2410 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0) 2411 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1) 2412 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2) 2413 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3) 2414 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4) 2415 #define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5) 2416 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6) 2417 u8 dpll_state; 2418 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0) 2419 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO BIT(1) 2420 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2) 2421 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5) 2422 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7) 2423 u8 config; 2424 #define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2425 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2426 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE \ 2427 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2428 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2429 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2430 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2431 __le32 phase_offset_h; 2432 __le32 phase_offset_l; 2433 u8 eec_mode; 2434 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA 2435 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB 2436 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF 2437 u8 rsvd[1]; 2438 __le16 node_handle; 2439 }; 2440 2441 /* Set CGU DPLL config (direct 0x0C67) */ 2442 struct ice_aqc_set_cgu_dpll_config { 2443 u8 dpll_num; 2444 u8 ref_state; 2445 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0) 2446 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1) 2447 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2) 2448 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3) 2449 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4) 2450 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5) 2451 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6) 2452 u8 rsvd; 2453 u8 config; 2454 #define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2455 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2456 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE \ 2457 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2458 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2459 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2460 ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2461 u8 rsvd2[8]; 2462 u8 eec_mode; 2463 u8 rsvd3[1]; 2464 __le16 node_handle; 2465 }; 2466 2467 /* Set CGU reference priority (direct 0x0C68) */ 2468 struct ice_aqc_set_cgu_ref_prio { 2469 u8 dpll_num; 2470 u8 ref_idx; 2471 u8 ref_priority; 2472 u8 rsvd[11]; 2473 __le16 node_handle; 2474 }; 2475 2476 /* Get CGU reference priority (direct 0x0C69) */ 2477 struct ice_aqc_get_cgu_ref_prio { 2478 u8 dpll_num; 2479 u8 ref_idx; 2480 u8 ref_priority; /* Valid only in response */ 2481 u8 rsvd[13]; 2482 }; 2483 2484 /* Get CGU info (direct 0x0C6A) */ 2485 struct ice_aqc_get_cgu_info { 2486 __le32 cgu_id; 2487 __le32 cgu_cfg_ver; 2488 __le32 cgu_fw_ver; 2489 u8 node_part_num; 2490 u8 dev_rev; 2491 __le16 node_handle; 2492 }; 2493 2494 /* Driver Shared Parameters (direct, 0x0C90) */ 2495 struct ice_aqc_driver_shared_params { 2496 u8 set_or_get_op; 2497 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2498 #define ICE_AQC_DRIVER_PARAM_SET 0 2499 #define ICE_AQC_DRIVER_PARAM_GET 1 2500 u8 param_indx; 2501 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2502 u8 rsvd[2]; 2503 __le32 param_val; 2504 __le32 addr_high; 2505 __le32 addr_low; 2506 }; 2507 2508 /* Lan Queue Overflow Event (direct, 0x1001) */ 2509 struct ice_aqc_event_lan_overflow { 2510 __le32 prtdcb_ruptq; 2511 __le32 qtx_ctl; 2512 u8 reserved[8]; 2513 }; 2514 2515 enum ice_aqc_fw_logging_mod { 2516 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2517 ICE_AQC_FW_LOG_ID_CTRL, 2518 ICE_AQC_FW_LOG_ID_LINK, 2519 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2520 ICE_AQC_FW_LOG_ID_DNL, 2521 ICE_AQC_FW_LOG_ID_I2C, 2522 ICE_AQC_FW_LOG_ID_SDP, 2523 ICE_AQC_FW_LOG_ID_MDIO, 2524 ICE_AQC_FW_LOG_ID_ADMINQ, 2525 ICE_AQC_FW_LOG_ID_HDMA, 2526 ICE_AQC_FW_LOG_ID_LLDP, 2527 ICE_AQC_FW_LOG_ID_DCBX, 2528 ICE_AQC_FW_LOG_ID_DCB, 2529 ICE_AQC_FW_LOG_ID_XLR, 2530 ICE_AQC_FW_LOG_ID_NVM, 2531 ICE_AQC_FW_LOG_ID_AUTH, 2532 ICE_AQC_FW_LOG_ID_VPD, 2533 ICE_AQC_FW_LOG_ID_IOSF, 2534 ICE_AQC_FW_LOG_ID_PARSER, 2535 ICE_AQC_FW_LOG_ID_SW, 2536 ICE_AQC_FW_LOG_ID_SCHEDULER, 2537 ICE_AQC_FW_LOG_ID_TXQ, 2538 ICE_AQC_FW_LOG_ID_RSVD, 2539 ICE_AQC_FW_LOG_ID_POST, 2540 ICE_AQC_FW_LOG_ID_WATCHDOG, 2541 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 2542 ICE_AQC_FW_LOG_ID_MNG, 2543 ICE_AQC_FW_LOG_ID_SYNCE, 2544 ICE_AQC_FW_LOG_ID_HEALTH, 2545 ICE_AQC_FW_LOG_ID_TSDRV, 2546 ICE_AQC_FW_LOG_ID_PFREG, 2547 ICE_AQC_FW_LOG_ID_MDLVER, 2548 ICE_AQC_FW_LOG_ID_MAX, 2549 }; 2550 2551 enum ice_aqc_health_status_mask { 2552 ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK = BIT(0), 2553 ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK = BIT(1), 2554 ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK = BIT(2), 2555 }; 2556 2557 /* Set Health Status (direct 0xFF20) */ 2558 struct ice_aqc_set_health_status_cfg { 2559 u8 event_source; 2560 u8 reserved[15]; 2561 }; 2562 2563 enum ice_aqc_health_status { 2564 ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT = 0x101, 2565 ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE = 0x102, 2566 ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL = 0x103, 2567 ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM = 0x104, 2568 ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT = 0x105, 2569 ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT = 0x106, 2570 ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED = 0x107, 2571 ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT = 0x108, 2572 ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE = 0x109, 2573 ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG = 0x10B, 2574 ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS = 0x10C, 2575 ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE = 0x10D, 2576 ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED = 0x10F, 2577 ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT = 0x110, 2578 ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED = 0x111, 2579 ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO = 0x112, 2580 ICE_AQC_HEALTH_STATUS_ERR_NETLIST = 0x113, 2581 ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT = 0x114, 2582 ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS = 0x115, 2583 ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME = 0x116, 2584 ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT = 0x117, 2585 ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG = 0x120, 2586 ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD = 0x121, 2587 ICE_AQC_HEALTH_STATUS_INFO_RECOVERY = 0x500, 2588 ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS = 0x501, 2589 ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH = 0x502, 2590 ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH = 0x503, 2591 ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH = 0x504, 2592 ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT = 0x505, 2593 ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT = 0x506, 2594 ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION = 0x507, 2595 ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION = 0x508, 2596 ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB = 0x509, 2597 ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT = 0x50A, 2598 ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET = 0x50B, 2599 ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL = 0x50C, 2600 ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL = 0x50D, 2601 ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP = 0x1000, 2602 ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL = 0x1001, 2603 ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ = 0x1002, 2604 }; 2605 2606 /* Get Health Status (indirect 0xFF22) */ 2607 struct ice_aqc_get_health_status { 2608 __le16 health_status_count; 2609 u8 reserved[6]; 2610 __le32 addr_high; 2611 __le32 addr_low; 2612 }; 2613 2614 enum ice_aqc_health_status_scope { 2615 ICE_AQC_HEALTH_STATUS_PF = 0x1, 2616 ICE_AQC_HEALTH_STATUS_PORT = 0x2, 2617 ICE_AQC_HEALTH_STATUS_GLOBAL = 0x3, 2618 }; 2619 2620 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA 0xDEADBEEF 2621 2622 /* Get Health Status event buffer entry (0xFF22), 2623 * repeated per reported health status. 2624 */ 2625 struct ice_aqc_health_status_elem { 2626 __le16 health_status_code; 2627 __le16 event_source; 2628 __le32 internal_data1; 2629 __le32 internal_data2; 2630 }; 2631 2632 /* Set FW Logging configuration (indirect 0xFF30) 2633 * Register for FW Logging (indirect 0xFF31) 2634 * Query FW Logging (indirect 0xFF32) 2635 * FW Log Event (indirect 0xFF33) 2636 */ 2637 struct ice_aqc_fw_log { 2638 u8 cmd_flags; 2639 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 2640 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 2641 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2) 2642 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 2643 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 2644 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 2645 2646 u8 rsp_flag; 2647 __le16 fw_rt_msb; 2648 union { 2649 struct { 2650 __le32 fw_rt_lsb; 2651 } sync; 2652 struct { 2653 __le16 log_resolution; 2654 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 2655 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 2656 2657 __le16 mdl_cnt; 2658 } cfg; 2659 } ops; 2660 __le32 addr_high; 2661 __le32 addr_low; 2662 }; 2663 2664 /* Response Buffer for: 2665 * Set Firmware Logging Configuration (0xFF30) 2666 * Query FW Logging (0xFF32) 2667 */ 2668 struct ice_aqc_fw_log_cfg_resp { 2669 __le16 module_identifier; 2670 u8 log_level; 2671 u8 rsvd0; 2672 }; 2673 2674 /** 2675 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2676 * @flags: ICE_AQ_FLAG_* flags 2677 * @opcode: AQ command opcode 2678 * @datalen: length in bytes of indirect/external data buffer 2679 * @retval: return value from firmware 2680 * @cookie_high: opaque data high-half 2681 * @cookie_low: opaque data low-half 2682 * @params: command-specific parameters 2683 * 2684 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2685 * (ATQ). The firmware writes back onto the command descriptor and returns 2686 * the result of the command. Asynchronous events that are not an immediate 2687 * result of the command are written to the Admin Receive Queue (ARQ) using 2688 * the same descriptor format. Descriptors are in little-endian notation with 2689 * 32-bit words. 2690 */ 2691 struct ice_aq_desc { 2692 __le16 flags; 2693 __le16 opcode; 2694 __le16 datalen; 2695 __le16 retval; 2696 __le32 cookie_high; 2697 __le32 cookie_low; 2698 union { 2699 u8 raw[16]; 2700 struct ice_aqc_generic generic; 2701 struct ice_aqc_get_ver get_ver; 2702 struct ice_aqc_driver_ver driver_ver; 2703 struct ice_aqc_q_shutdown q_shutdown; 2704 struct ice_aqc_req_res res_owner; 2705 struct ice_aqc_manage_mac_read mac_read; 2706 struct ice_aqc_manage_mac_write mac_write; 2707 struct ice_aqc_clear_pxe clear_pxe; 2708 struct ice_aqc_list_caps get_cap; 2709 struct ice_aqc_get_phy_caps get_phy; 2710 struct ice_aqc_set_phy_cfg set_phy; 2711 struct ice_aqc_restart_an restart_an; 2712 struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out; 2713 struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out; 2714 struct ice_aqc_get_sensor_reading get_sensor_reading; 2715 struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp; 2716 struct ice_aqc_gpio read_write_gpio; 2717 struct ice_aqc_sff_eeprom read_write_sff_param; 2718 struct ice_aqc_set_port_id_led set_port_id_led; 2719 struct ice_aqc_get_port_options get_port_options; 2720 struct ice_aqc_set_port_option set_port_option; 2721 struct ice_aqc_get_sw_cfg get_sw_conf; 2722 struct ice_aqc_set_port_params set_port_params; 2723 struct ice_aqc_sw_rules sw_rules; 2724 struct ice_aqc_add_get_recipe add_get_recipe; 2725 struct ice_aqc_recipe_to_profile recipe_to_profile; 2726 struct ice_aqc_get_topo get_topo; 2727 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2728 struct ice_aqc_query_txsched_res query_sched_res; 2729 struct ice_aqc_query_port_ets port_ets; 2730 struct ice_aqc_rl_profile rl_profile; 2731 struct ice_aqc_nvm nvm; 2732 struct ice_aqc_nvm_checksum nvm_checksum; 2733 struct ice_aqc_nvm_pkg_data pkg_data; 2734 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl; 2735 struct ice_aqc_pf_vf_msg virt; 2736 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2737 struct ice_aqc_lldp_get_mib lldp_get_mib; 2738 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2739 struct ice_aqc_lldp_stop lldp_stop; 2740 struct ice_aqc_lldp_start lldp_start; 2741 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2742 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2743 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2744 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2745 struct ice_aqc_get_set_rss_key get_set_rss_key; 2746 struct ice_aqc_neigh_dev_req neigh_dev; 2747 struct ice_aqc_add_txqs add_txqs; 2748 struct ice_aqc_dis_txqs dis_txqs; 2749 struct ice_aqc_cfg_txqs cfg_txqs; 2750 struct ice_aqc_add_rdma_qset add_rdma_qset; 2751 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2752 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2753 struct ice_aqc_download_pkg download_pkg; 2754 struct ice_aqc_get_cgu_input_measure get_cgu_input_measure; 2755 struct ice_aqc_set_cgu_input_config set_cgu_input_config; 2756 struct ice_aqc_get_cgu_input_config get_cgu_input_config; 2757 struct ice_aqc_set_cgu_output_config set_cgu_output_config; 2758 struct ice_aqc_get_cgu_output_config get_cgu_output_config; 2759 struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status; 2760 struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config; 2761 struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio; 2762 struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio; 2763 struct ice_aqc_get_cgu_info get_cgu_info; 2764 struct ice_aqc_driver_shared_params drv_shared_params; 2765 struct ice_aqc_fw_log fw_log; 2766 struct ice_aqc_set_mac_lb set_mac_lb; 2767 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2768 struct ice_aqc_set_mac_cfg set_mac_cfg; 2769 struct ice_aqc_set_event_mask set_event_mask; 2770 struct ice_aqc_get_link_status get_link_status; 2771 struct ice_aqc_event_lan_overflow lan_overflow; 2772 struct ice_aqc_get_link_topo get_link_topo; 2773 struct ice_aqc_set_health_status_cfg set_health_status_cfg; 2774 struct ice_aqc_get_health_status get_health_status; 2775 struct ice_aqc_dnl_call_command dnl_call; 2776 struct ice_aqc_i2c read_write_i2c; 2777 struct ice_aqc_read_i2c_resp read_i2c_resp; 2778 struct ice_aqc_get_set_tx_topo get_set_tx_topo; 2779 } params; 2780 }; 2781 2782 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2783 #define ICE_AQ_LG_BUF 512 2784 2785 #define ICE_AQ_FLAG_DD_S 0 2786 #define ICE_AQ_FLAG_CMP_S 1 2787 #define ICE_AQ_FLAG_ERR_S 2 2788 #define ICE_AQ_FLAG_LB_S 9 2789 #define ICE_AQ_FLAG_RD_S 10 2790 #define ICE_AQ_FLAG_BUF_S 12 2791 #define ICE_AQ_FLAG_SI_S 13 2792 2793 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2794 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2795 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2796 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2797 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2798 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2799 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2800 2801 /* error codes */ 2802 enum ice_aq_err { 2803 ICE_AQ_RC_OK = 0, /* Success */ 2804 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2805 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2806 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2807 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2808 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2809 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2810 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2811 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2812 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2813 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2814 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2815 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2816 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2817 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2818 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2819 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2820 }; 2821 2822 /* Admin Queue command opcodes */ 2823 enum ice_adminq_opc { 2824 /* AQ commands */ 2825 ice_aqc_opc_get_ver = 0x0001, 2826 ice_aqc_opc_driver_ver = 0x0002, 2827 ice_aqc_opc_q_shutdown = 0x0003, 2828 2829 /* resource ownership */ 2830 ice_aqc_opc_req_res = 0x0008, 2831 ice_aqc_opc_release_res = 0x0009, 2832 2833 /* device/function capabilities */ 2834 ice_aqc_opc_list_func_caps = 0x000A, 2835 ice_aqc_opc_list_dev_caps = 0x000B, 2836 2837 /* manage MAC address */ 2838 ice_aqc_opc_manage_mac_read = 0x0107, 2839 ice_aqc_opc_manage_mac_write = 0x0108, 2840 2841 /* PXE */ 2842 ice_aqc_opc_clear_pxe_mode = 0x0110, 2843 2844 /* internal switch commands */ 2845 ice_aqc_opc_get_sw_cfg = 0x0200, 2846 ice_aqc_opc_set_port_params = 0x0203, 2847 2848 /* Alloc/Free/Get Resources */ 2849 ice_aqc_opc_alloc_res = 0x0208, 2850 ice_aqc_opc_free_res = 0x0209, 2851 ice_aqc_opc_share_res = 0x020B, 2852 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 2853 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 2854 2855 /* VSI commands */ 2856 ice_aqc_opc_add_vsi = 0x0210, 2857 ice_aqc_opc_update_vsi = 0x0211, 2858 ice_aqc_opc_free_vsi = 0x0213, 2859 2860 /* recipe commands */ 2861 ice_aqc_opc_add_recipe = 0x0290, 2862 ice_aqc_opc_recipe_to_profile = 0x0291, 2863 ice_aqc_opc_get_recipe = 0x0292, 2864 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2865 2866 /* switch rules population commands */ 2867 ice_aqc_opc_add_sw_rules = 0x02A0, 2868 ice_aqc_opc_update_sw_rules = 0x02A1, 2869 ice_aqc_opc_remove_sw_rules = 0x02A2, 2870 2871 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2872 2873 /* DCB commands */ 2874 ice_aqc_opc_query_pfc_mode = 0x0302, 2875 ice_aqc_opc_set_pfc_mode = 0x0303, 2876 2877 /* transmit scheduler commands */ 2878 ice_aqc_opc_get_dflt_topo = 0x0400, 2879 ice_aqc_opc_add_sched_elems = 0x0401, 2880 ice_aqc_opc_cfg_sched_elems = 0x0403, 2881 ice_aqc_opc_get_sched_elems = 0x0404, 2882 ice_aqc_opc_move_sched_elems = 0x0408, 2883 ice_aqc_opc_suspend_sched_elems = 0x0409, 2884 ice_aqc_opc_resume_sched_elems = 0x040A, 2885 ice_aqc_opc_query_port_ets = 0x040E, 2886 ice_aqc_opc_delete_sched_elems = 0x040F, 2887 ice_aqc_opc_add_rl_profiles = 0x0410, 2888 ice_aqc_opc_query_sched_res = 0x0412, 2889 ice_aqc_opc_remove_rl_profiles = 0x0415, 2890 2891 /* tx topology commands */ 2892 ice_aqc_opc_set_tx_topo = 0x0417, 2893 ice_aqc_opc_get_tx_topo = 0x0418, 2894 2895 /* PHY commands */ 2896 ice_aqc_opc_get_phy_caps = 0x0600, 2897 ice_aqc_opc_set_phy_cfg = 0x0601, 2898 ice_aqc_opc_set_mac_cfg = 0x0603, 2899 ice_aqc_opc_restart_an = 0x0605, 2900 ice_aqc_opc_get_link_status = 0x0607, 2901 ice_aqc_opc_set_event_mask = 0x0613, 2902 ice_aqc_opc_set_mac_lb = 0x0620, 2903 ice_aqc_opc_set_phy_rec_clk_out = 0x0630, 2904 ice_aqc_opc_get_phy_rec_clk_out = 0x0631, 2905 ice_aqc_opc_get_sensor_reading = 0x0632, 2906 ice_aqc_opc_dnl_call = 0x0682, 2907 ice_aqc_opc_get_link_topo = 0x06E0, 2908 ice_aqc_opc_read_i2c = 0x06E2, 2909 ice_aqc_opc_write_i2c = 0x06E3, 2910 ice_aqc_opc_set_port_id_led = 0x06E9, 2911 ice_aqc_opc_get_port_options = 0x06EA, 2912 ice_aqc_opc_set_port_option = 0x06EB, 2913 ice_aqc_opc_set_gpio = 0x06EC, 2914 ice_aqc_opc_get_gpio = 0x06ED, 2915 ice_aqc_opc_sff_eeprom = 0x06EE, 2916 2917 /* NVM commands */ 2918 ice_aqc_opc_nvm_read = 0x0701, 2919 ice_aqc_opc_nvm_erase = 0x0702, 2920 ice_aqc_opc_nvm_write = 0x0703, 2921 ice_aqc_opc_nvm_checksum = 0x0706, 2922 ice_aqc_opc_nvm_write_activate = 0x0707, 2923 ice_aqc_opc_nvm_update_empr = 0x0709, 2924 ice_aqc_opc_nvm_pkg_data = 0x070A, 2925 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2926 2927 /* PF/VF mailbox commands */ 2928 ice_mbx_opc_send_msg_to_pf = 0x0801, 2929 ice_mbx_opc_send_msg_to_vf = 0x0802, 2930 /* LLDP commands */ 2931 ice_aqc_opc_lldp_get_mib = 0x0A00, 2932 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2933 ice_aqc_opc_lldp_stop = 0x0A05, 2934 ice_aqc_opc_lldp_start = 0x0A06, 2935 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2936 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2937 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2938 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2939 ice_aqc_opc_lldp_execute_pending_mib = 0x0A0B, 2940 2941 /* RSS commands */ 2942 ice_aqc_opc_set_rss_key = 0x0B02, 2943 ice_aqc_opc_set_rss_lut = 0x0B03, 2944 ice_aqc_opc_get_rss_key = 0x0B04, 2945 ice_aqc_opc_get_rss_lut = 0x0B05, 2946 2947 /* Sideband Control Interface commands */ 2948 ice_aqc_opc_neighbour_device_request = 0x0C00, 2949 2950 /* Tx queue handling commands/events */ 2951 ice_aqc_opc_add_txqs = 0x0C30, 2952 ice_aqc_opc_dis_txqs = 0x0C31, 2953 ice_aqc_opc_cfg_txqs = 0x0C32, 2954 ice_aqc_opc_add_rdma_qset = 0x0C33, 2955 2956 /* package commands */ 2957 ice_aqc_opc_download_pkg = 0x0C40, 2958 ice_aqc_opc_upload_section = 0x0C41, 2959 ice_aqc_opc_update_pkg = 0x0C42, 2960 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2961 2962 /* 1588/SyncE commands/events */ 2963 ice_aqc_opc_get_cgu_input_measure = 0x0C59, 2964 ice_aqc_opc_get_cgu_abilities = 0x0C61, 2965 ice_aqc_opc_set_cgu_input_config = 0x0C62, 2966 ice_aqc_opc_get_cgu_input_config = 0x0C63, 2967 ice_aqc_opc_set_cgu_output_config = 0x0C64, 2968 ice_aqc_opc_get_cgu_output_config = 0x0C65, 2969 ice_aqc_opc_get_cgu_dpll_status = 0x0C66, 2970 ice_aqc_opc_set_cgu_dpll_config = 0x0C67, 2971 ice_aqc_opc_set_cgu_ref_prio = 0x0C68, 2972 ice_aqc_opc_get_cgu_ref_prio = 0x0C69, 2973 ice_aqc_opc_get_cgu_info = 0x0C6A, 2974 2975 ice_aqc_opc_driver_shared_params = 0x0C90, 2976 2977 /* Standalone Commands/Events */ 2978 ice_aqc_opc_event_lan_overflow = 0x1001, 2979 2980 /* System Diagnostic commands */ 2981 ice_aqc_opc_set_health_status_cfg = 0xFF20, 2982 ice_aqc_opc_get_health_status = 0xFF22, 2983 2984 /* FW Logging Commands */ 2985 ice_aqc_opc_fw_logs_config = 0xFF30, 2986 ice_aqc_opc_fw_logs_register = 0xFF31, 2987 ice_aqc_opc_fw_logs_query = 0xFF32, 2988 ice_aqc_opc_fw_logs_event = 0xFF33, 2989 }; 2990 2991 #endif /* _ICE_ADMINQ_CMD_H_ */ 2992