1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Send driver version (indirect 0x0002) */ 37 struct ice_aqc_driver_ver { 38 u8 major_ver; 39 u8 minor_ver; 40 u8 build_ver; 41 u8 subbuild_ver; 42 u8 reserved[4]; 43 __le32 addr_high; 44 __le32 addr_low; 45 }; 46 47 /* Queue Shutdown (direct 0x0003) */ 48 struct ice_aqc_q_shutdown { 49 u8 driver_unloading; 50 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 51 u8 reserved[15]; 52 }; 53 54 /* Request resource ownership (direct 0x0008) 55 * Release resource ownership (direct 0x0009) 56 */ 57 struct ice_aqc_req_res { 58 __le16 res_id; 59 #define ICE_AQC_RES_ID_NVM 1 60 #define ICE_AQC_RES_ID_SDP 2 61 #define ICE_AQC_RES_ID_CHNG_LOCK 3 62 #define ICE_AQC_RES_ID_GLBL_LOCK 4 63 __le16 access_type; 64 #define ICE_AQC_RES_ACCESS_READ 1 65 #define ICE_AQC_RES_ACCESS_WRITE 2 66 67 /* Upon successful completion, FW writes this value and driver is 68 * expected to release resource before timeout. This value is provided 69 * in milliseconds. 70 */ 71 __le32 timeout; 72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76 /* For SDP: pin ID of the SDP */ 77 __le32 res_number; 78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79 __le16 status; 80 #define ICE_AQ_RES_GLBL_SUCCESS 0 81 #define ICE_AQ_RES_GLBL_IN_PROG 1 82 #define ICE_AQ_RES_GLBL_DONE 2 83 u8 reserved[2]; 84 }; 85 86 /* Get function capabilities (indirect 0x000A) 87 * Get device capabilities (indirect 0x000B) 88 */ 89 struct ice_aqc_list_caps { 90 u8 cmd_flags; 91 u8 pf_index; 92 u8 reserved[2]; 93 __le32 count; 94 __le32 addr_high; 95 __le32 addr_low; 96 }; 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_SRIOV 0x0012 103 #define ICE_AQC_CAPS_VF 0x0013 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_1588 0x0046 112 #define ICE_AQC_CAPS_MAX_MTU 0x0047 113 #define ICE_AQC_CAPS_NVM_VER 0x0048 114 #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049 115 #define ICE_AQC_CAPS_OROM_VER 0x004A 116 #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B 117 #define ICE_AQC_CAPS_NET_VER 0x004C 118 #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D 119 #define ICE_AQC_CAPS_RDMA 0x0051 120 #define ICE_AQC_CAPS_SENSOR_READING 0x0067 121 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 122 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 123 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 124 #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085 125 #define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087 126 #define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092 127 #define ICE_AQC_BIT_ROCEV2_LAG 0x01 128 #define ICE_AQC_BIT_SRIOV_LAG 0x02 129 130 u8 major_ver; 131 u8 minor_ver; 132 /* Number of resources described by this capability */ 133 __le32 number; 134 /* Only meaningful for some types of resources */ 135 __le32 logical_id; 136 /* Only meaningful for some types of resources */ 137 __le32 phys_id; 138 __le64 rsvd1; 139 __le64 rsvd2; 140 }; 141 142 /* Manage MAC address, read command - indirect (0x0107) 143 * This struct is also used for the response 144 */ 145 struct ice_aqc_manage_mac_read { 146 __le16 flags; /* Zeroed by device driver */ 147 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 148 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 149 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 150 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 151 #define ICE_AQC_MAN_MAC_READ_S 4 152 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 153 u8 rsvd[2]; 154 u8 num_addr; /* Used in response */ 155 u8 rsvd1[3]; 156 __le32 addr_high; 157 __le32 addr_low; 158 }; 159 160 /* Response buffer format for manage MAC read command */ 161 struct ice_aqc_manage_mac_read_resp { 162 u8 lport_num; 163 u8 addr_type; 164 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 165 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 166 u8 mac_addr[ETH_ALEN]; 167 }; 168 169 /* Manage MAC address, write command - direct (0x0108) */ 170 struct ice_aqc_manage_mac_write { 171 u8 rsvd; 172 u8 flags; 173 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 174 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 175 #define ICE_AQC_MAN_MAC_WR_S 6 176 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 177 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 178 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 179 /* byte stream in network order */ 180 u8 mac_addr[ETH_ALEN]; 181 __le32 addr_high; 182 __le32 addr_low; 183 }; 184 185 /* Clear PXE Command and response (direct 0x0110) */ 186 struct ice_aqc_clear_pxe { 187 u8 rx_cnt; 188 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 189 u8 reserved[15]; 190 }; 191 192 /* Get switch configuration (0x0200) */ 193 struct ice_aqc_get_sw_cfg { 194 /* Reserved for command and copy of request flags for response */ 195 __le16 flags; 196 /* First desc in case of command and next_elem in case of response 197 * In case of response, if it is not zero, means all the configuration 198 * was not returned and new command shall be sent with this value in 199 * the 'first desc' field 200 */ 201 __le16 element; 202 /* Reserved for command, only used for response */ 203 __le16 num_elems; 204 __le16 rsvd; 205 __le32 addr_high; 206 __le32 addr_low; 207 }; 208 209 /* Each entry in the response buffer is of the following type: */ 210 struct ice_aqc_get_sw_cfg_resp_elem { 211 /* VSI/Port Number */ 212 __le16 vsi_port_num; 213 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 214 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 215 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 216 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 217 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 218 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 219 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 220 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 221 222 /* SWID VSI/Port belongs to */ 223 __le16 swid; 224 225 /* Bit 14..0 : PF/VF number VSI belongs to 226 * Bit 15 : VF indication bit 227 */ 228 __le16 pf_vf_num; 229 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 230 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 231 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 232 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 233 }; 234 235 /* Set Port parameters, (direct, 0x0203) */ 236 struct ice_aqc_set_port_params { 237 __le16 cmd_flags; 238 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 239 __le16 bad_frame_vsi; 240 __le16 swid; 241 #define ICE_AQC_PORT_SWID_VALID BIT(15) 242 #define ICE_AQC_PORT_SWID_M 0xFF 243 u8 reserved[10]; 244 }; 245 246 /* These resource type defines are used for all switch resource 247 * commands where a resource type is required, such as: 248 * Get Resource Allocation command (indirect 0x0204) 249 * Allocate Resources command (indirect 0x0208) 250 * Free Resources command (indirect 0x0209) 251 * Get Allocated Resource Descriptors Command (indirect 0x020A) 252 * Share Resource command (indirect 0x020B) 253 */ 254 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 255 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 256 #define ICE_AQC_RES_TYPE_RECIPE 0x05 257 #define ICE_AQC_RES_TYPE_SWID 0x07 258 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 259 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 260 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 261 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 262 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 263 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 264 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 265 266 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 267 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 268 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 269 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14) 270 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15) 271 272 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 273 274 #define ICE_AQC_RES_TYPE_S 0 275 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 276 277 /* Allocate Resources command (indirect 0x0208) 278 * Free Resources command (indirect 0x0209) 279 * Share Resource command (indirect 0x020B) 280 */ 281 struct ice_aqc_alloc_free_res_cmd { 282 __le16 num_entries; /* Number of Resource entries */ 283 u8 reserved[6]; 284 __le32 addr_high; 285 __le32 addr_low; 286 }; 287 288 /* Resource descriptor */ 289 struct ice_aqc_res_elem { 290 union { 291 __le16 sw_resp; 292 __le16 flu_resp; 293 } e; 294 }; 295 296 /* Buffer for Allocate/Free Resources commands */ 297 struct ice_aqc_alloc_free_res_elem { 298 __le16 res_type; /* Types defined above cmd 0x0204 */ 299 #define ICE_AQC_RES_TYPE_SHARED_S 7 300 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 301 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 302 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 303 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 304 __le16 num_elems; 305 struct ice_aqc_res_elem elem[]; 306 }; 307 308 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 309 struct ice_aqc_set_vlan_mode { 310 u8 reserved; 311 u8 l2tag_prio_tagging; 312 #define ICE_AQ_VLAN_PRIO_TAG_S 0 313 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 314 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 315 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 316 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 317 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 318 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 319 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 320 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 321 u8 l2tag_reserved[64]; 322 u8 rdma_packet; 323 #define ICE_AQ_VLAN_RDMA_TAG_S 0 324 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 325 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 326 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 327 u8 rdma_reserved[2]; 328 u8 mng_vlan_prot_id; 329 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 330 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 331 u8 prot_id_reserved[30]; 332 }; 333 334 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 335 struct ice_aqc_get_vlan_mode { 336 u8 vlan_mode; 337 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 338 u8 l2tag_prio_tagging; 339 u8 reserved[98]; 340 }; 341 342 /* Add VSI (indirect 0x0210) 343 * Update VSI (indirect 0x0211) 344 * Get VSI (indirect 0x0212) 345 * Free VSI (indirect 0x0213) 346 */ 347 struct ice_aqc_add_get_update_free_vsi { 348 __le16 vsi_num; 349 #define ICE_AQ_VSI_NUM_S 0 350 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 351 #define ICE_AQ_VSI_IS_VALID BIT(15) 352 __le16 cmd_flags; 353 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 354 u8 vf_id; 355 u8 reserved; 356 __le16 vsi_flags; 357 #define ICE_AQ_VSI_TYPE_S 0 358 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 359 #define ICE_AQ_VSI_TYPE_VF 0x0 360 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 361 #define ICE_AQ_VSI_TYPE_PF 0x2 362 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 363 __le32 addr_high; 364 __le32 addr_low; 365 }; 366 367 /* Response descriptor for: 368 * Add VSI (indirect 0x0210) 369 * Update VSI (indirect 0x0211) 370 * Free VSI (indirect 0x0213) 371 */ 372 struct ice_aqc_add_update_free_vsi_resp { 373 __le16 vsi_num; 374 __le16 ext_status; 375 __le16 vsi_used; 376 __le16 vsi_free; 377 __le32 addr_high; 378 __le32 addr_low; 379 }; 380 381 struct ice_aqc_vsi_props { 382 __le16 valid_sections; 383 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 384 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 385 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 386 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 387 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 388 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 389 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 390 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 391 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 392 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 393 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 394 /* switch section */ 395 u8 sw_id; 396 u8 sw_flags; 397 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 398 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 399 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 400 u8 sw_flags2; 401 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 402 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 403 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 404 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 405 u8 veb_stat_id; 406 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 407 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 408 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 409 /* security section */ 410 u8 sec_flags; 411 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 412 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 413 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 414 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 415 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 416 u8 sec_reserved; 417 /* VLAN section */ 418 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 419 u8 inner_vlan_reserved[2]; 420 u8 inner_vlan_flags; 421 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 422 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 423 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 424 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 425 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 426 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 427 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 428 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 429 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH 0x0U 430 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP 0x1U 431 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR 0x2U 432 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING 0x3U 433 u8 inner_vlan_reserved2[3]; 434 /* ingress egress up sections */ 435 __le32 ingress_table; /* bitmap, 3 bits per up */ 436 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 437 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 438 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 439 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 440 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 441 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 442 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 443 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 444 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 445 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 446 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 447 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 448 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 449 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 450 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 451 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 452 __le32 egress_table; /* same defines as for ingress table */ 453 /* outer tags section */ 454 __le16 port_based_outer_vlan; 455 u8 outer_vlan_flags; 456 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 457 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 458 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 459 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 460 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 461 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 462 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 463 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 464 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 465 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 466 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 467 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 468 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 469 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 470 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 471 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 472 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 473 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 474 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 475 u8 outer_vlan_reserved; 476 /* queue mapping section */ 477 __le16 mapping_flags; 478 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 479 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 480 __le16 q_mapping[16]; 481 #define ICE_AQ_VSI_Q_S 0 482 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 483 __le16 tc_mapping[8]; 484 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 485 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 486 #define ICE_AQ_VSI_TC_Q_NUM_S 11 487 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 488 /* queueing option section */ 489 u8 q_opt_rss; 490 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 491 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 492 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 493 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 494 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 495 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 496 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 497 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 498 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6) 499 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ 0x0U 500 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ 0x1U 501 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR 0x2U 502 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH 0x3U 503 u8 q_opt_tc; 504 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 505 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 506 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 507 u8 q_opt_flags; 508 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 509 u8 q_opt_reserved[3]; 510 /* outer up section */ 511 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 512 /* section 10 */ 513 __le16 sect_10_reserved; 514 /* flow director section */ 515 __le16 fd_options; 516 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 517 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 518 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 519 __le16 max_fd_fltr_dedicated; 520 __le16 max_fd_fltr_shared; 521 __le16 fd_def_q; 522 #define ICE_AQ_VSI_FD_DEF_Q_S 0 523 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 524 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 525 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 526 __le16 fd_report_opt; 527 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 528 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 529 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 530 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 531 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 532 /* PASID section */ 533 __le32 pasid_id; 534 #define ICE_AQ_VSI_PASID_ID_S 0 535 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 536 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 537 u8 reserved[24]; 538 }; 539 540 #define ICE_MAX_NUM_RECIPES 64 541 542 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 543 struct ice_aqc_add_get_recipe { 544 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 545 __le16 return_index; /* Input, used for Get cmd only */ 546 u8 reserved[4]; 547 __le32 addr_high; 548 __le32 addr_low; 549 }; 550 551 struct ice_aqc_recipe_content { 552 u8 rid; 553 #define ICE_AQ_RECIPE_ID_S 0 554 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 555 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 556 #define ICE_AQ_SW_ID_LKUP_IDX 0 557 u8 lkup_indx[5]; 558 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 559 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 560 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 561 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 562 __le16 mask[5]; 563 u8 result_indx; 564 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 565 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 566 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 567 u8 rsvd0[3]; 568 u8 act_ctrl_join_priority; 569 u8 act_ctrl_fwd_priority; 570 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 571 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 572 u8 act_ctrl; 573 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 574 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 575 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 576 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 577 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 578 u8 rsvd1; 579 __le32 dflt_act; 580 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 581 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 582 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 583 }; 584 585 struct ice_aqc_recipe_data_elem { 586 u8 recipe_indx; 587 u8 resp_bits; 588 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 589 u8 rsvd0[2]; 590 u8 recipe_bitmap[8]; 591 u8 rsvd1[4]; 592 struct ice_aqc_recipe_content content; 593 u8 rsvd2[20]; 594 }; 595 596 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 597 struct ice_aqc_recipe_to_profile { 598 __le16 profile_id; 599 u8 rsvd[6]; 600 __le64 recipe_assoc; 601 }; 602 static_assert(sizeof(struct ice_aqc_recipe_to_profile) == 16); 603 604 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 605 */ 606 struct ice_aqc_sw_rules { 607 /* ops: add switch rules, referring the number of rules. 608 * ops: update switch rules, referring the number of filters 609 * ops: remove switch rules, referring the entry index. 610 * ops: get switch rules, referring to the number of filters. 611 */ 612 __le16 num_rules_fltr_entry_index; 613 u8 reserved[6]; 614 __le32 addr_high; 615 __le32 addr_low; 616 }; 617 618 /* Add switch rule response: 619 * Content of return buffer is same as the input buffer. The status field and 620 * LUT index are updated as part of the response 621 */ 622 struct ice_aqc_sw_rules_elem_hdr { 623 __le16 type; /* Switch rule type, one of T_... */ 624 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 625 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 626 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 627 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 628 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 629 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 630 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 631 __le16 status; 632 } __packed __aligned(sizeof(__le16)); 633 634 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 635 * This structures describes the lookup rules and associated actions. "index" 636 * is returned as part of a response to a successful Add command, and can be 637 * used to identify the rule for Update/Get/Remove commands. 638 */ 639 struct ice_sw_rule_lkup_rx_tx { 640 struct ice_aqc_sw_rules_elem_hdr hdr; 641 642 __le16 recipe_id; 643 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 644 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 645 __le16 src; 646 __le32 act; 647 648 /* Bit 0:1 - Action type */ 649 #define ICE_SINGLE_ACT_TYPE_S 0x00 650 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 651 652 /* Bit 2 - Loop back enable 653 * Bit 3 - LAN enable 654 */ 655 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 656 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 657 658 /* Action type = 0 - Forward to VSI or VSI list */ 659 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 660 661 #define ICE_SINGLE_ACT_VSI_ID_S 4 662 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 663 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 664 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 665 /* This bit needs to be set if action is forward to VSI list */ 666 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 667 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 668 #define ICE_SINGLE_ACT_DROP BIT(18) 669 670 /* Action type = 1 - Forward to Queue of Queue group */ 671 #define ICE_SINGLE_ACT_TO_Q 0x1 672 #define ICE_SINGLE_ACT_Q_INDEX_S 4 673 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 674 #define ICE_SINGLE_ACT_Q_REGION_S 15 675 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 676 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 677 678 /* Action type = 2 - Prune */ 679 #define ICE_SINGLE_ACT_PRUNE 0x2 680 #define ICE_SINGLE_ACT_EGRESS BIT(15) 681 #define ICE_SINGLE_ACT_INGRESS BIT(16) 682 #define ICE_SINGLE_ACT_PRUNET BIT(17) 683 /* Bit 18 should be set to 0 for this action */ 684 685 /* Action type = 2 - Pointer */ 686 #define ICE_SINGLE_ACT_PTR 0x2 687 #define ICE_SINGLE_ACT_PTR_VAL_S 4 688 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 689 /* Bit 18 should be set to 1 */ 690 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 691 692 /* Action type = 3 - Other actions. Last two bits 693 * are other action identifier 694 */ 695 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 696 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 697 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 698 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 699 700 /* Bit 17:18 - Defines other actions */ 701 /* Other action = 0 - Mirror VSI */ 702 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 703 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 704 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 705 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 706 707 /* Other action = 3 - Set Stat count */ 708 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 709 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 710 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 711 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 712 713 __le16 index; /* The index of the rule in the lookup table */ 714 /* Length and values of the header to be matched per recipe or 715 * lookup-type 716 */ 717 __le16 hdr_len; 718 u8 hdr_data[]; 719 } __packed __aligned(sizeof(__le16)); 720 721 /* Add/Update/Remove large action command/response entry 722 * "index" is returned as part of a response to a successful Add command, and 723 * can be used to identify the action for Update/Get/Remove commands. 724 */ 725 struct ice_sw_rule_lg_act { 726 struct ice_aqc_sw_rules_elem_hdr hdr; 727 728 __le16 index; /* Index in large action table */ 729 __le16 size; 730 /* Max number of large actions */ 731 #define ICE_MAX_LG_ACT 4 732 /* Bit 0:1 - Action type */ 733 #define ICE_LG_ACT_TYPE_S 0 734 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 735 736 /* Action type = 0 - Forward to VSI or VSI list */ 737 #define ICE_LG_ACT_VSI_FORWARDING 0 738 #define ICE_LG_ACT_VSI_ID_S 3 739 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 740 #define ICE_LG_ACT_VSI_LIST_ID_S 3 741 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 742 /* This bit needs to be set if action is forward to VSI list */ 743 #define ICE_LG_ACT_VSI_LIST BIT(13) 744 745 #define ICE_LG_ACT_VALID_BIT BIT(16) 746 747 /* Action type = 1 - Forward to Queue of Queue group */ 748 #define ICE_LG_ACT_TO_Q 0x1 749 #define ICE_LG_ACT_Q_INDEX_S 3 750 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 751 #define ICE_LG_ACT_Q_REGION_S 14 752 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 753 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 754 755 /* Action type = 2 - Prune */ 756 #define ICE_LG_ACT_PRUNE 0x2 757 #define ICE_LG_ACT_EGRESS BIT(14) 758 #define ICE_LG_ACT_INGRESS BIT(15) 759 #define ICE_LG_ACT_PRUNET BIT(16) 760 761 /* Action type = 3 - Mirror VSI */ 762 #define ICE_LG_OTHER_ACT_MIRROR 0x3 763 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 764 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 765 766 /* Action type = 5 - Generic Value */ 767 #define ICE_LG_ACT_GENERIC 0x5 768 #define ICE_LG_ACT_GENERIC_VALUE_S 3 769 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 770 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 771 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 772 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 773 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 774 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 775 776 /* Action = 7 - Set Stat count */ 777 #define ICE_LG_ACT_STAT_COUNT 0x7 778 #define ICE_LG_ACT_STAT_COUNT_S 3 779 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 780 __le32 act[]; /* array of size for actions */ 781 } __packed __aligned(sizeof(__le16)); 782 783 /* Add/Update/Remove VSI list command/response entry 784 * "index" is returned as part of a response to a successful Add command, and 785 * can be used to identify the VSI list for Update/Get/Remove commands. 786 */ 787 struct ice_sw_rule_vsi_list { 788 struct ice_aqc_sw_rules_elem_hdr hdr; 789 790 __le16 index; /* Index of VSI/Prune list */ 791 __le16 number_vsi; 792 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 793 } __packed __aligned(sizeof(__le16)); 794 795 /* Query PFC Mode (direct 0x0302) 796 * Set PFC Mode (direct 0x0303) 797 */ 798 struct ice_aqc_set_query_pfc_mode { 799 u8 pfc_mode; 800 /* For Query Command response, reserved in all other cases */ 801 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 802 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 803 u8 rsvd[15]; 804 }; 805 /* Get Default Topology (indirect 0x0400) */ 806 struct ice_aqc_get_topo { 807 u8 port_num; 808 u8 num_branches; 809 __le16 reserved1; 810 __le32 reserved2; 811 __le32 addr_high; 812 __le32 addr_low; 813 }; 814 815 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */ 816 struct ice_aqc_get_set_tx_topo { 817 u8 set_flags; 818 #define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0) 819 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1) 820 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4) 821 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5) 822 823 u8 get_flags; 824 #define ICE_AQC_TX_TOPO_GET_RAM 2 825 826 __le16 reserved1; 827 __le32 reserved2; 828 __le32 addr_high; 829 __le32 addr_low; 830 }; 831 832 /* Update TSE (indirect 0x0403) 833 * Get TSE (indirect 0x0404) 834 * Add TSE (indirect 0x0401) 835 * Delete TSE (indirect 0x040F) 836 * Move TSE (indirect 0x0408) 837 * Suspend Nodes (indirect 0x0409) 838 * Resume Nodes (indirect 0x040A) 839 */ 840 struct ice_aqc_sched_elem_cmd { 841 __le16 num_elem_req; /* Used by commands */ 842 __le16 num_elem_resp; /* Used by responses */ 843 __le32 reserved; 844 __le32 addr_high; 845 __le32 addr_low; 846 }; 847 848 struct ice_aqc_txsched_move_grp_info_hdr { 849 __le32 src_parent_teid; 850 __le32 dest_parent_teid; 851 __le16 num_elems; 852 u8 mode; 853 #define ICE_AQC_MOVE_ELEM_MODE_SAME_PF 0x0 854 #define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN 0x1 855 #define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN 0x2 856 u8 reserved; 857 }; 858 859 struct ice_aqc_move_elem { 860 struct ice_aqc_txsched_move_grp_info_hdr hdr; 861 __le32 teid[]; 862 }; 863 864 struct ice_aqc_elem_info_bw { 865 __le16 bw_profile_idx; 866 __le16 bw_alloc; 867 }; 868 869 struct ice_aqc_txsched_elem { 870 u8 elem_type; /* Special field, reserved for some aq calls */ 871 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 872 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 873 #define ICE_AQC_ELEM_TYPE_TC 0x2 874 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 875 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 876 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 877 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 878 u8 valid_sections; 879 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 880 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 881 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 882 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 883 u8 generic; 884 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 885 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 886 #define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1) 887 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 888 #define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4) 889 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 890 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 891 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 892 u8 flags; /* Special field, reserved for some aq calls */ 893 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 894 struct ice_aqc_elem_info_bw cir_bw; 895 struct ice_aqc_elem_info_bw eir_bw; 896 __le16 srl_id; 897 __le16 reserved2; 898 }; 899 900 struct ice_aqc_txsched_elem_data { 901 __le32 parent_teid; 902 __le32 node_teid; 903 struct ice_aqc_txsched_elem data; 904 }; 905 906 struct ice_aqc_txsched_topo_grp_info_hdr { 907 __le32 parent_teid; 908 __le16 num_elems; 909 __le16 reserved2; 910 }; 911 912 struct ice_aqc_add_elem { 913 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 914 struct ice_aqc_txsched_elem_data generic[]; 915 }; 916 917 struct ice_aqc_get_topo_elem { 918 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 919 struct ice_aqc_txsched_elem_data 920 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 921 }; 922 923 struct ice_aqc_delete_elem { 924 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 925 __le32 teid[]; 926 }; 927 928 /* Query Port ETS (indirect 0x040E) 929 * 930 * This indirect command is used to query port TC node configuration. 931 */ 932 struct ice_aqc_query_port_ets { 933 __le32 port_teid; 934 __le32 reserved; 935 __le32 addr_high; 936 __le32 addr_low; 937 }; 938 939 struct ice_aqc_port_ets_elem { 940 u8 tc_valid_bits; 941 u8 reserved[3]; 942 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 943 __le32 up2tc; 944 u8 tc_bw_share[8]; 945 __le32 port_eir_prof_id; 946 __le32 port_cir_prof_id; 947 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 948 __le32 tc_node_prio; 949 #define ICE_TC_NODE_PRIO_S 0x4 950 u8 reserved1[4]; 951 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 952 }; 953 954 /* Rate limiting profile for 955 * Add RL profile (indirect 0x0410) 956 * Query RL profile (indirect 0x0411) 957 * Remove RL profile (indirect 0x0415) 958 * These indirect commands acts on single or multiple 959 * RL profiles with specified data. 960 */ 961 struct ice_aqc_rl_profile { 962 __le16 num_profiles; 963 __le16 num_processed; /* Only for response. Reserved in Command. */ 964 u8 reserved[4]; 965 __le32 addr_high; 966 __le32 addr_low; 967 }; 968 969 struct ice_aqc_rl_profile_elem { 970 u8 level; 971 u8 flags; 972 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 973 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 974 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 975 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 976 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 977 /* The following flag is used for Query RL Profile Data */ 978 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 979 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 980 981 __le16 profile_id; 982 __le16 max_burst_size; 983 __le16 rl_multiply; 984 __le16 wake_up_calc; 985 __le16 rl_encode; 986 }; 987 988 /* Query Scheduler Resource Allocation (indirect 0x0412) 989 * This indirect command retrieves the scheduler resources allocated by 990 * EMP Firmware to the given PF. 991 */ 992 struct ice_aqc_query_txsched_res { 993 u8 reserved[8]; 994 __le32 addr_high; 995 __le32 addr_low; 996 }; 997 998 struct ice_aqc_generic_sched_props { 999 __le16 phys_levels; 1000 __le16 logical_levels; 1001 u8 flattening_bitmap; 1002 u8 max_device_cgds; 1003 u8 max_pf_cgds; 1004 u8 rsvd0; 1005 __le16 rdma_qsets; 1006 u8 rsvd1[22]; 1007 }; 1008 1009 struct ice_aqc_layer_props { 1010 u8 logical_layer; 1011 u8 chunk_size; 1012 __le16 max_device_nodes; 1013 __le16 max_pf_nodes; 1014 u8 rsvd0[4]; 1015 __le16 max_sibl_grp_sz; 1016 __le16 max_cir_rl_profiles; 1017 __le16 max_eir_rl_profiles; 1018 __le16 max_srl_profiles; 1019 u8 rsvd1[14]; 1020 }; 1021 1022 struct ice_aqc_query_txsched_res_resp { 1023 struct ice_aqc_generic_sched_props sched_props; 1024 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1025 }; 1026 1027 /* Get PHY capabilities (indirect 0x0600) */ 1028 struct ice_aqc_get_phy_caps { 1029 u8 lport_num; 1030 u8 reserved; 1031 __le16 param0; 1032 /* 18.0 - Report qualified modules */ 1033 #define ICE_AQC_GET_PHY_RQM BIT(0) 1034 /* 18.1 - 18.3 : Report mode 1035 * 000b - Report NVM capabilities 1036 * 001b - Report topology capabilities 1037 * 010b - Report SW configured 1038 * 100b - Report default capabilities 1039 */ 1040 #define ICE_AQC_REPORT_MODE_S 1 1041 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1042 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1043 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1044 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1045 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1046 __le32 reserved1; 1047 __le32 addr_high; 1048 __le32 addr_low; 1049 }; 1050 1051 /* This is #define of PHY type (Extended): 1052 * The first set of defines is for phy_type_low. 1053 */ 1054 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1055 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1056 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1057 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1058 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1059 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1060 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1061 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1062 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1063 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1064 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1065 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1066 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1067 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1068 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1069 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1070 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1071 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1072 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1073 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1074 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1075 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1076 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1077 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1078 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1079 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1080 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1081 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1082 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1083 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1084 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1085 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1086 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1087 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1088 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1089 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1090 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1091 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1092 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1093 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1094 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1095 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1096 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1097 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1098 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1099 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1100 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1101 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1102 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1103 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1104 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1105 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1106 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1107 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1108 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1109 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1110 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1111 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1112 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1113 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1114 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1115 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1116 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1117 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1118 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1119 /* The second set of defines is for phy_type_high. */ 1120 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1121 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1122 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1123 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1124 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1125 #define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) 1126 #define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) 1127 #define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) 1128 #define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) 1129 #define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) 1130 #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) 1131 #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) 1132 #define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) 1133 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 12 1134 1135 struct ice_aqc_get_phy_caps_data { 1136 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1137 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1138 u8 caps; 1139 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1140 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1141 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1142 #define ICE_AQC_PHY_EN_LINK BIT(3) 1143 #define ICE_AQC_PHY_AN_MODE BIT(4) 1144 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 1145 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1146 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 1147 u8 low_power_ctrl_an; 1148 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1149 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1150 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1151 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1152 __le16 eee_cap; 1153 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1154 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1155 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1156 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1157 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1158 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1159 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1160 __le16 eeer_value; 1161 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1162 u8 phy_fw_ver[8]; 1163 u8 link_fec_options; 1164 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1165 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1166 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1167 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1168 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1169 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1170 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1171 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1172 u8 module_compliance_enforcement; 1173 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1174 u8 extended_compliance_code; 1175 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1176 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1177 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1178 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1179 #define ICE_AQC_MOD_TYPE_IDENT 1 1180 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1181 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1182 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1183 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1184 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1185 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1186 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1187 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1188 u8 qualified_module_count; 1189 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1190 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1191 struct { 1192 u8 v_oui[3]; 1193 u8 rsvd3; 1194 u8 v_part[16]; 1195 __le32 v_rev; 1196 __le64 rsvd4; 1197 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1198 }; 1199 1200 /* Set PHY capabilities (direct 0x0601) 1201 * NOTE: This command must be followed by setup link and restart auto-neg 1202 */ 1203 struct ice_aqc_set_phy_cfg { 1204 u8 lport_num; 1205 u8 reserved[7]; 1206 __le32 addr_high; 1207 __le32 addr_low; 1208 }; 1209 1210 /* Set PHY config command data structure */ 1211 struct ice_aqc_set_phy_cfg_data { 1212 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1213 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1214 u8 caps; 1215 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1216 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1217 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1218 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1219 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1220 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1221 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1222 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1223 u8 low_power_ctrl_an; 1224 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1225 __le16 eeer_value; 1226 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1227 u8 module_compliance_enforcement; 1228 }; 1229 1230 /* Set MAC Config command data structure (direct 0x0603) */ 1231 struct ice_aqc_set_mac_cfg { 1232 __le16 max_frame_size; 1233 u8 params; 1234 #define ICE_AQ_SET_MAC_PACE_S 3 1235 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1236 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1237 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1238 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1239 u8 tx_tmr_priority; 1240 __le16 tx_tmr_value; 1241 __le16 fc_refresh_threshold; 1242 u8 drop_opts; 1243 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1244 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1245 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1246 u8 reserved[7]; 1247 }; 1248 1249 /* Restart AN command data structure (direct 0x0605) 1250 * Also used for response, with only the lport_num field present. 1251 */ 1252 struct ice_aqc_restart_an { 1253 u8 lport_num; 1254 u8 reserved; 1255 u8 cmd_flags; 1256 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1257 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1258 u8 reserved2[13]; 1259 }; 1260 1261 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1262 struct ice_aqc_get_link_status { 1263 u8 lport_num; 1264 u8 reserved; 1265 __le16 cmd_flags; 1266 #define ICE_AQ_LSE_M 0x3 1267 #define ICE_AQ_LSE_NOP 0x0 1268 #define ICE_AQ_LSE_DIS 0x2 1269 #define ICE_AQ_LSE_ENA 0x3 1270 /* only response uses this flag */ 1271 #define ICE_AQ_LSE_IS_ENABLED 0x1 1272 __le32 reserved2; 1273 __le32 addr_high; 1274 __le32 addr_low; 1275 }; 1276 1277 /* Get link status response data structure, also used for Link Status Event */ 1278 struct ice_aqc_get_link_status_data { 1279 u8 topo_media_conflict; 1280 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1281 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1282 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1283 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1284 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1285 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1286 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1287 u8 link_cfg_err; 1288 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1289 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1290 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1291 u8 link_info; 1292 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1293 #define ICE_AQ_LINK_FAULT BIT(1) 1294 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1295 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1296 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1297 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1298 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1299 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1300 u8 an_info; 1301 #define ICE_AQ_AN_COMPLETED BIT(0) 1302 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1303 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1304 #define ICE_AQ_FEC_EN BIT(3) 1305 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1306 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1307 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1308 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1309 u8 ext_info; 1310 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1311 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1312 /* Port Tx Suspended */ 1313 #define ICE_AQ_LINK_TX_S 2 1314 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1315 #define ICE_AQ_LINK_TX_ACTIVE 0 1316 #define ICE_AQ_LINK_TX_DRAINED 1 1317 #define ICE_AQ_LINK_TX_FLUSHED 3 1318 u8 reserved2; 1319 __le16 max_frame_size; 1320 u8 cfg; 1321 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1322 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1323 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1324 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1325 /* Pacing Config */ 1326 #define ICE_AQ_CFG_PACING_S 3 1327 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1328 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1329 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1330 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1331 /* External Device Power Ability */ 1332 u8 power_desc; 1333 #define ICE_AQ_PWR_CLASS_M 0x3F 1334 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1335 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1336 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1337 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1338 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1339 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1340 __le16 link_speed; 1341 #define ICE_AQ_LINK_SPEED_M 0x7FF 1342 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1343 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1344 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1345 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1346 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1347 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1348 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1349 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1350 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1351 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1352 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1353 #define ICE_AQ_LINK_SPEED_200GB BIT(11) 1354 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1355 /* Aligns next field to 8-byte boundary */ 1356 __le16 reserved3; 1357 u8 ext_fec_status; 1358 /* RS 272 FEC enabled */ 1359 #define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) 1360 u8 reserved4; 1361 /* Use values from ICE_PHY_TYPE_LOW_* */ 1362 __le64 phy_type_low; 1363 /* Use values from ICE_PHY_TYPE_HIGH_* */ 1364 __le64 phy_type_high; 1365 #define ICE_AQC_LS_DATA_SIZE_V1 \ 1366 offsetofend(struct ice_aqc_get_link_status_data, phy_type_high) 1367 /* Get link status v2 link partner data */ 1368 __le64 lp_phy_type_low; 1369 __le64 lp_phy_type_high; 1370 u8 lp_fec_adv; 1371 #define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0) 1372 #define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1) 1373 #define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2) 1374 #define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 1375 #define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 1376 #define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 1377 u8 lp_fec_req; 1378 #define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0) 1379 #define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1) 1380 #define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2) 1381 #define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3) 1382 u8 lp_flowcontrol; 1383 #define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0) 1384 #define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1) 1385 u8 reserved5[5]; 1386 #define ICE_AQC_LS_DATA_SIZE_V2 \ 1387 offsetofend(struct ice_aqc_get_link_status_data, reserved5) 1388 } __packed; 1389 1390 /* Set event mask command (direct 0x0613) */ 1391 struct ice_aqc_set_event_mask { 1392 u8 lport_num; 1393 u8 reserved[7]; 1394 __le16 event_mask; 1395 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1396 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1397 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1398 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1399 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1400 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1401 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1402 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1403 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1404 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1405 u8 reserved1[6]; 1406 }; 1407 1408 /* Set MAC Loopback command (direct 0x0620) */ 1409 struct ice_aqc_set_mac_lb { 1410 u8 lb_mode; 1411 #define ICE_AQ_MAC_LB_EN BIT(0) 1412 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1413 u8 reserved[15]; 1414 }; 1415 1416 /* Set PHY recovered clock output (direct 0x0630) */ 1417 struct ice_aqc_set_phy_rec_clk_out { 1418 u8 phy_output; 1419 u8 port_num; 1420 #define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1421 u8 flags; 1422 #define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1423 u8 rsvd; 1424 __le32 freq; 1425 u8 rsvd2[6]; 1426 __le16 node_handle; 1427 }; 1428 1429 /* Get PHY recovered clock output (direct 0x0631) */ 1430 struct ice_aqc_get_phy_rec_clk_out { 1431 u8 phy_output; 1432 u8 port_num; 1433 #define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1434 u8 flags; 1435 #define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1436 u8 rsvd[11]; 1437 __le16 node_handle; 1438 }; 1439 1440 /* Get sensor reading (direct 0x0632) */ 1441 struct ice_aqc_get_sensor_reading { 1442 u8 sensor; 1443 u8 format; 1444 u8 reserved[6]; 1445 __le32 addr_high; 1446 __le32 addr_low; 1447 }; 1448 1449 /* Get sensor reading response (direct 0x0632) */ 1450 struct ice_aqc_get_sensor_reading_resp { 1451 union { 1452 u8 raw[8]; 1453 /* Output data for sensor 0x00, format 0x00 */ 1454 struct _packed { 1455 s8 temp; 1456 u8 temp_warning_threshold; 1457 u8 temp_critical_threshold; 1458 u8 temp_fatal_threshold; 1459 u8 reserved[4]; 1460 } s0f0; 1461 } data; 1462 }; 1463 1464 struct ice_aqc_link_topo_params { 1465 u8 lport_num; 1466 u8 lport_num_valid; 1467 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1468 u8 node_type_ctx; 1469 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1470 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1471 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1472 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1473 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1474 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1475 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1476 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1477 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1478 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1479 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1480 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 9 1481 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 10 1482 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS 11 1483 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1484 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1485 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1486 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1487 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1488 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1489 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1490 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1491 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1492 u8 index; 1493 }; 1494 1495 struct ice_aqc_link_topo_addr { 1496 struct ice_aqc_link_topo_params topo_params; 1497 __le16 handle; 1498 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1499 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1500 /* Used to decode the handle field */ 1501 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1502 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1503 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1504 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1505 /* In case of a Mezzanine type */ 1506 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1507 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1508 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1509 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1510 /* In case of a LOM type */ 1511 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1512 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1513 }; 1514 1515 /* Get Link Topology Handle (direct, 0x06E0) */ 1516 struct ice_aqc_get_link_topo { 1517 struct ice_aqc_link_topo_addr addr; 1518 u8 node_part_num; 1519 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1520 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 1521 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25 1522 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30 1523 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31 1524 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 1525 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 1526 u8 rsvd[9]; 1527 }; 1528 1529 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1530 struct ice_aqc_i2c { 1531 struct ice_aqc_link_topo_addr topo_addr; 1532 __le16 i2c_addr; 1533 u8 i2c_params; 1534 #define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0) 1535 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1536 1537 u8 rsvd; 1538 __le16 i2c_bus_addr; 1539 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1540 }; 1541 1542 /* Read I2C Response (direct, 0x06E2) */ 1543 struct ice_aqc_read_i2c_resp { 1544 u8 i2c_data[16]; 1545 }; 1546 1547 /* Set Port Identification LED (direct, 0x06E9) */ 1548 struct ice_aqc_set_port_id_led { 1549 u8 lport_num; 1550 u8 lport_num_valid; 1551 u8 ident_mode; 1552 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1553 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1554 u8 rsvd[13]; 1555 }; 1556 1557 /* Get Port Options (indirect, 0x06EA) */ 1558 struct ice_aqc_get_port_options { 1559 u8 lport_num; 1560 u8 lport_num_valid; 1561 u8 port_options_count; 1562 #define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0) 1563 #define ICE_AQC_PORT_OPT_MAX 16 1564 1565 u8 innermost_phy_index; 1566 u8 port_options; 1567 #define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0) 1568 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1569 1570 u8 pending_port_option_status; 1571 #define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0) 1572 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 1573 1574 u8 rsvd[2]; 1575 __le32 addr_high; 1576 __le32 addr_low; 1577 }; 1578 1579 struct ice_aqc_get_port_options_elem { 1580 u8 pmd; 1581 #define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0) 1582 1583 u8 max_lane_speed; 1584 #define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0) 1585 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1586 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1587 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1588 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1589 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1590 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1591 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1592 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1593 1594 u8 global_scid[2]; 1595 u8 phy_scid[2]; 1596 u8 pf2port_cid[2]; 1597 }; 1598 1599 /* Set Port Option (direct, 0x06EB) */ 1600 struct ice_aqc_set_port_option { 1601 u8 lport_num; 1602 u8 lport_num_valid; 1603 u8 selected_port_option; 1604 u8 rsvd[13]; 1605 }; 1606 1607 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1608 struct ice_aqc_gpio { 1609 __le16 gpio_ctrl_handle; 1610 #define ICE_AQC_GPIO_HANDLE_S 0 1611 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1612 u8 gpio_num; 1613 u8 gpio_val; 1614 u8 rsvd[12]; 1615 }; 1616 1617 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1618 struct ice_aqc_sff_eeprom { 1619 u8 lport_num; 1620 u8 lport_num_valid; 1621 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1622 __le16 i2c_bus_addr; 1623 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1624 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1625 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1626 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1627 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1628 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1629 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1630 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1631 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1632 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1633 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1634 __le16 i2c_mem_addr; 1635 __le16 eeprom_page; 1636 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1637 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1638 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1639 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1640 __le32 addr_high; 1641 __le32 addr_low; 1642 }; 1643 1644 /* NVM Read command (indirect 0x0701) 1645 * NVM Erase commands (direct 0x0702) 1646 * NVM Update commands (indirect 0x0703) 1647 */ 1648 struct ice_aqc_nvm { 1649 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1650 __le16 offset_low; 1651 u8 offset_high; 1652 u8 cmd_flags; 1653 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1654 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1655 #define ICE_AQC_NVM_PRESERVATION_S 1 1656 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1657 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1658 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1659 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1660 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1661 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1662 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1663 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1664 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1665 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1666 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1667 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1668 #define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */ 1669 #define ICE_AQC_NVM_POR_FLAG 0 1670 #define ICE_AQC_NVM_PERST_FLAG 1 1671 #define ICE_AQC_NVM_EMPR_FLAG 2 1672 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 1673 /* For Write Activate, several flags are sent as part of a separate 1674 * flags2 field using a separate byte. For simplicity of the software 1675 * interface, we pass the flags as a 16 bit value so these flags are 1676 * all offset by 8 bits 1677 */ 1678 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 1679 __le16 module_typeid; 1680 __le16 length; 1681 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1682 __le32 addr_high; 1683 __le32 addr_low; 1684 }; 1685 1686 #define ICE_AQC_NVM_START_POINT 0 1687 1688 #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B 1689 1690 struct ice_aqc_nvm_tx_topo_user_sel { 1691 __le16 length; 1692 u8 data; 1693 #define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4) 1694 u8 reserved; 1695 }; 1696 1697 /* NVM Checksum Command (direct, 0x0706) */ 1698 struct ice_aqc_nvm_checksum { 1699 u8 flags; 1700 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1701 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1702 u8 rsvd; 1703 __le16 checksum; /* Used only by response */ 1704 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1705 u8 rsvd2[12]; 1706 }; 1707 1708 /* Used for NVM Set Package Data command - 0x070A */ 1709 struct ice_aqc_nvm_pkg_data { 1710 u8 reserved[3]; 1711 u8 cmd_flags; 1712 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1713 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1714 1715 u32 reserved1; 1716 __le32 addr_high; 1717 __le32 addr_low; 1718 }; 1719 1720 /* Used for Pass Component Table command - 0x070B */ 1721 struct ice_aqc_nvm_pass_comp_tbl { 1722 u8 component_response; /* Response only */ 1723 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1724 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1725 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1726 u8 component_response_code; /* Response only */ 1727 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1728 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1729 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1730 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1731 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1732 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1733 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1734 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1735 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1736 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1737 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1738 u8 reserved; 1739 u8 transfer_flag; 1740 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1741 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1742 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1743 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1744 __le32 reserved1; 1745 __le32 addr_high; 1746 __le32 addr_low; 1747 }; 1748 1749 struct ice_aqc_nvm_comp_tbl { 1750 __le16 comp_class; 1751 #define NVM_COMP_CLASS_ALL_FW 0x000A 1752 1753 __le16 comp_id; 1754 #define NVM_COMP_ID_OROM 0x5 1755 #define NVM_COMP_ID_NVM 0x6 1756 #define NVM_COMP_ID_NETLIST 0x8 1757 1758 u8 comp_class_idx; 1759 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1760 1761 __le32 comp_cmp_stamp; 1762 u8 cvs_type; 1763 #define NVM_CVS_TYPE_ASCII 0x1 1764 1765 u8 cvs_len; 1766 u8 cvs[]; /* Component Version String */ 1767 } __packed; 1768 1769 /* Send to PF command (indirect 0x0801) ID is only used by PF 1770 * 1771 * Send to VF command (indirect 0x0802) ID is only used by PF 1772 * 1773 */ 1774 struct ice_aqc_pf_vf_msg { 1775 __le32 id; 1776 u32 reserved; 1777 __le32 addr_high; 1778 __le32 addr_low; 1779 }; 1780 1781 /* Get LLDP MIB (indirect 0x0A00) 1782 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1783 * as the format is the same. 1784 */ 1785 struct ice_aqc_lldp_get_mib { 1786 u8 type; 1787 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1788 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1789 #define ICE_AQ_LLDP_MIB_LOCAL 0 1790 #define ICE_AQ_LLDP_MIB_REMOTE 1 1791 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1792 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1793 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1794 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1795 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1796 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1797 #define ICE_AQ_LLDP_TX_S 0x4 1798 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1799 #define ICE_AQ_LLDP_TX_ACTIVE 0 1800 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1801 #define ICE_AQ_LLDP_TX_FLUSHED 3 1802 /* DCBX mode */ 1803 #define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6) 1804 #define ICE_AQ_LLDP_DCBX_NA 0 1805 #define ICE_AQ_LLDP_DCBX_CEE 1 1806 #define ICE_AQ_LLDP_DCBX_IEEE 2 1807 1808 u8 state; 1809 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M BIT(0) 1810 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 1811 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 1812 1813 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1814 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1815 * Get LLDP MIB (0x0A00) response only. 1816 */ 1817 __le16 local_len; 1818 __le16 remote_len; 1819 u8 reserved[2]; 1820 __le32 addr_high; 1821 __le32 addr_low; 1822 }; 1823 1824 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1825 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1826 struct ice_aqc_lldp_set_mib_change { 1827 u8 command; 1828 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1829 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1830 #define ICE_AQ_LLDP_MIB_PENDING_M BIT(1) 1831 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 1832 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 1833 u8 reserved[15]; 1834 }; 1835 1836 /* Stop LLDP (direct 0x0A05) */ 1837 struct ice_aqc_lldp_stop { 1838 u8 command; 1839 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1840 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1841 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1842 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1843 u8 reserved[15]; 1844 }; 1845 1846 /* Start LLDP (direct 0x0A06) */ 1847 struct ice_aqc_lldp_start { 1848 u8 command; 1849 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1850 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1851 u8 reserved[15]; 1852 }; 1853 1854 /* Get CEE DCBX Oper Config (0x0A07) 1855 * The command uses the generic descriptor struct and 1856 * returns the struct below as an indirect response. 1857 */ 1858 struct ice_aqc_get_cee_dcb_cfg_resp { 1859 u8 oper_num_tc; 1860 u8 oper_prio_tc[4]; 1861 u8 oper_tc_bw[8]; 1862 u8 oper_pfc_en; 1863 __le16 oper_app_prio; 1864 #define ICE_AQC_CEE_APP_FCOE_S 0 1865 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1866 #define ICE_AQC_CEE_APP_ISCSI_S 3 1867 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1868 #define ICE_AQC_CEE_APP_FIP_S 8 1869 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1870 __le32 tlv_status; 1871 #define ICE_AQC_CEE_PG_STATUS_S 0 1872 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1873 #define ICE_AQC_CEE_PFC_STATUS_S 3 1874 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1875 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1876 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1877 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1878 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1879 #define ICE_AQC_CEE_FIP_STATUS_S 16 1880 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1881 u8 reserved[12]; 1882 }; 1883 1884 /* Set Local LLDP MIB (indirect 0x0A08) 1885 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1886 */ 1887 struct ice_aqc_lldp_set_local_mib { 1888 u8 type; 1889 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1890 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1891 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1892 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1893 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1894 u8 reserved0; 1895 __le16 length; 1896 u8 reserved1[4]; 1897 __le32 addr_high; 1898 __le32 addr_low; 1899 }; 1900 1901 /* Stop/Start LLDP Agent (direct 0x0A09) 1902 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1903 * The same structure is used for the response, with the command field 1904 * being used as the status field. 1905 */ 1906 struct ice_aqc_lldp_stop_start_specific_agent { 1907 u8 command; 1908 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1909 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1910 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1911 u8 reserved[15]; 1912 }; 1913 1914 /* LLDP Filter Control (direct 0x0A0A) */ 1915 struct ice_aqc_lldp_filter_ctrl { 1916 u8 cmd_flags; 1917 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1918 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1919 u8 reserved1; 1920 __le16 vsi_num; 1921 u8 reserved2[12]; 1922 }; 1923 1924 #define ICE_AQC_RSS_VSI_VALID BIT(15) 1925 1926 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1927 struct ice_aqc_get_set_rss_key { 1928 __le16 vsi_id; 1929 u8 reserved[6]; 1930 __le32 addr_high; 1931 __le32 addr_low; 1932 }; 1933 1934 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1935 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1936 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1937 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1938 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1939 1940 struct ice_aqc_get_set_rss_keys { 1941 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1942 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1943 }; 1944 1945 enum ice_lut_type { 1946 ICE_LUT_VSI = 0, 1947 ICE_LUT_PF = 1, 1948 ICE_LUT_GLOBAL = 2, 1949 }; 1950 1951 enum ice_lut_size { 1952 ICE_LUT_VSI_SIZE = 64, 1953 ICE_LUT_GLOBAL_SIZE = 512, 1954 ICE_LUT_PF_SIZE = 2048, 1955 }; 1956 1957 /* enum ice_aqc_lut_flags combines constants used to fill 1958 * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID, 1959 * LUT size and LUT type, last of which does not need neither shift nor mask. 1960 */ 1961 enum ice_aqc_lut_flags { 1962 ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */ 1963 ICE_AQC_LUT_SIZE_512 = BIT(2), 1964 ICE_AQC_LUT_SIZE_2K = BIT(3), 1965 1966 ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4), 1967 }; 1968 1969 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1970 struct ice_aqc_get_set_rss_lut { 1971 __le16 vsi_id; 1972 __le16 flags; 1973 __le32 reserved; 1974 __le32 addr_high; 1975 __le32 addr_low; 1976 }; 1977 1978 /* Sideband Control Interface Commands */ 1979 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 1980 struct ice_aqc_neigh_dev_req { 1981 __le16 sb_data_len; 1982 u8 reserved[6]; 1983 __le32 addr_high; 1984 __le32 addr_low; 1985 }; 1986 1987 /* Add Tx LAN Queues (indirect 0x0C30) */ 1988 struct ice_aqc_add_txqs { 1989 u8 num_qgrps; 1990 u8 reserved[3]; 1991 __le32 reserved1; 1992 __le32 addr_high; 1993 __le32 addr_low; 1994 }; 1995 1996 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1997 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1998 */ 1999 struct ice_aqc_add_txqs_perq { 2000 __le16 txq_id; 2001 u8 rsvd[2]; 2002 __le32 q_teid; 2003 u8 txq_ctx[22]; 2004 u8 rsvd2[2]; 2005 struct ice_aqc_txsched_elem info; 2006 }; 2007 2008 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2009 * is an array of the following structs. Please note that the length of 2010 * each struct ice_aqc_add_tx_qgrp is variable due 2011 * to the variable number of queues in each group! 2012 */ 2013 struct ice_aqc_add_tx_qgrp { 2014 __le32 parent_teid; 2015 u8 num_txqs; 2016 u8 rsvd[3]; 2017 struct ice_aqc_add_txqs_perq txqs[]; 2018 }; 2019 2020 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2021 struct ice_aqc_dis_txqs { 2022 u8 cmd_type; 2023 #define ICE_AQC_Q_DIS_CMD_S 0 2024 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2025 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2026 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2027 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2028 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2029 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2030 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2031 u8 num_entries; 2032 __le16 vmvf_and_timeout; 2033 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2034 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2035 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2036 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2037 __le32 blocked_cgds; 2038 __le32 addr_high; 2039 __le32 addr_low; 2040 }; 2041 2042 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2043 * contains the following structures, arrayed one after the 2044 * other. 2045 * Note: Since the q_id is 16 bits wide, if the 2046 * number of queues is even, then 2 bytes of alignment MUST be 2047 * added before the start of the next group, to allow correct 2048 * alignment of the parent_teid field. 2049 */ 2050 struct ice_aqc_dis_txq_item { 2051 __le32 parent_teid; 2052 u8 num_qs; 2053 u8 rsvd; 2054 /* The length of the q_id array varies according to num_qs */ 2055 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2056 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2057 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2058 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2059 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2060 __le16 q_id[]; 2061 } __packed; 2062 2063 /* Move/Reconfigure Tx queue (indirect 0x0C32) */ 2064 struct ice_aqc_cfg_txqs { 2065 u8 cmd_type; 2066 #define ICE_AQC_Q_CFG_MOVE_NODE 0x1 2067 #define ICE_AQC_Q_CFG_TC_CHNG 0x2 2068 #define ICE_AQC_Q_CFG_MOVE_TC_CHNG 0x3 2069 #define ICE_AQC_Q_CFG_SUBSEQ_CALL BIT(2) 2070 #define ICE_AQC_Q_CFG_FLUSH BIT(3) 2071 u8 num_qs; 2072 u8 port_num_chng; 2073 #define ICE_AQC_Q_CFG_SRC_PRT_M 0x7 2074 #define ICE_AQC_Q_CFG_DST_PRT_S 3 2075 #define ICE_AQC_Q_CFG_DST_PRT_M (0x7 << ICE_AQC_Q_CFG_DST_PRT_S) 2076 u8 time_out; 2077 #define ICE_AQC_Q_CFG_TIMEOUT_S 2 2078 #define ICE_AQC_Q_CFG_TIMEOUT_M (0x1F << ICE_AQC_Q_CFG_TIMEOUT_S) 2079 __le32 blocked_cgds; 2080 __le32 addr_high; 2081 __le32 addr_low; 2082 }; 2083 2084 /* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2085 struct ice_aqc_cfg_txq_perq { 2086 __le16 q_handle; 2087 u8 tc; 2088 u8 rsvd; 2089 __le32 q_teid; 2090 }; 2091 2092 /* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2093 struct ice_aqc_cfg_txqs_buf { 2094 __le32 src_parent_teid; 2095 __le32 dst_parent_teid; 2096 struct ice_aqc_cfg_txq_perq queue_info[]; 2097 }; 2098 2099 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 2100 struct ice_aqc_add_rdma_qset { 2101 u8 num_qset_grps; 2102 u8 reserved[7]; 2103 __le32 addr_high; 2104 __le32 addr_low; 2105 }; 2106 2107 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 2108 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 2109 */ 2110 struct ice_aqc_add_tx_rdma_qset_entry { 2111 __le16 tx_qset_id; 2112 u8 rsvd[2]; 2113 __le32 qset_teid; 2114 struct ice_aqc_txsched_elem info; 2115 }; 2116 2117 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 2118 * is an array of the following structs. Please note that the length of 2119 * each struct ice_aqc_add_rdma_qset is variable due to the variable 2120 * number of queues in each group! 2121 */ 2122 struct ice_aqc_add_rdma_qset_data { 2123 __le32 parent_teid; 2124 __le16 num_qsets; 2125 u8 rsvd[2]; 2126 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 2127 }; 2128 2129 /* Download Package (indirect 0x0C40) */ 2130 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ 2131 struct ice_aqc_download_pkg { 2132 u8 flags; 2133 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2134 u8 reserved[3]; 2135 __le32 reserved1; 2136 __le32 addr_high; 2137 __le32 addr_low; 2138 }; 2139 2140 struct ice_aqc_download_pkg_resp { 2141 __le32 error_offset; 2142 __le32 error_info; 2143 __le32 addr_high; 2144 __le32 addr_low; 2145 }; 2146 2147 /* Get Package Info List (indirect 0x0C43) */ 2148 struct ice_aqc_get_pkg_info_list { 2149 __le32 reserved1; 2150 __le32 reserved2; 2151 __le32 addr_high; 2152 __le32 addr_low; 2153 }; 2154 2155 /* Version format for packages */ 2156 struct ice_pkg_ver { 2157 u8 major; 2158 u8 minor; 2159 u8 update; 2160 u8 draft; 2161 }; 2162 2163 #define ICE_PKG_NAME_SIZE 32 2164 #define ICE_SEG_ID_SIZE 28 2165 #define ICE_SEG_NAME_SIZE 28 2166 2167 struct ice_aqc_get_pkg_info { 2168 struct ice_pkg_ver ver; 2169 char name[ICE_SEG_NAME_SIZE]; 2170 __le32 track_id; 2171 u8 is_in_nvm; 2172 u8 is_active; 2173 u8 is_active_at_boot; 2174 u8 is_modified; 2175 }; 2176 2177 /* Get Package Info List response buffer format (0x0C43) */ 2178 struct ice_aqc_get_pkg_info_resp { 2179 __le32 count; 2180 struct ice_aqc_get_pkg_info pkg_info[]; 2181 }; 2182 2183 /* Get CGU abilities command response data structure (indirect 0x0C61) */ 2184 struct ice_aqc_get_cgu_abilities { 2185 u8 num_inputs; 2186 u8 num_outputs; 2187 u8 pps_dpll_idx; 2188 u8 eec_dpll_idx; 2189 __le32 max_in_freq; 2190 __le32 max_in_phase_adj; 2191 __le32 max_out_freq; 2192 __le32 max_out_phase_adj; 2193 u8 cgu_part_num; 2194 u8 rsvd[3]; 2195 }; 2196 2197 /* Set CGU input config (direct 0x0C62) */ 2198 struct ice_aqc_set_cgu_input_config { 2199 u8 input_idx; 2200 u8 flags1; 2201 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6) 2202 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7) 2203 u8 flags2; 2204 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2205 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2206 u8 rsvd; 2207 __le32 freq; 2208 __le32 phase_delay; 2209 u8 rsvd2[2]; 2210 __le16 node_handle; 2211 }; 2212 2213 /* Get CGU input config response descriptor structure (direct 0x0C63) */ 2214 struct ice_aqc_get_cgu_input_config { 2215 u8 input_idx; 2216 u8 status; 2217 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS BIT(0) 2218 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1) 2219 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2) 2220 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3) 2221 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4) 2222 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6) 2223 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7) 2224 u8 type; 2225 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0) 2226 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS BIT(4) 2227 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5) 2228 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY BIT(6) 2229 u8 flags1; 2230 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0) 2231 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2) 2232 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3) 2233 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7) 2234 __le32 freq; 2235 __le32 phase_delay; 2236 u8 flags2; 2237 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2238 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2239 u8 rsvd[1]; 2240 __le16 node_handle; 2241 }; 2242 2243 /* Set CGU output config (direct 0x0C64) */ 2244 struct ice_aqc_set_cgu_output_config { 2245 u8 output_idx; 2246 u8 flags; 2247 #define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN BIT(0) 2248 #define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2249 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2) 2250 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3) 2251 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4) 2252 u8 src_sel; 2253 #define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0) 2254 u8 rsvd; 2255 __le32 freq; 2256 __le32 phase_delay; 2257 u8 rsvd2[2]; 2258 __le16 node_handle; 2259 }; 2260 2261 /* Get CGU output config (direct 0x0C65) */ 2262 struct ice_aqc_get_cgu_output_config { 2263 u8 output_idx; 2264 u8 flags; 2265 #define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN BIT(0) 2266 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2267 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2) 2268 u8 src_sel; 2269 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0 2270 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \ 2271 ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT) 2272 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5 2273 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \ 2274 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT) 2275 u8 rsvd; 2276 __le32 freq; 2277 __le32 src_freq; 2278 u8 rsvd2[2]; 2279 __le16 node_handle; 2280 }; 2281 2282 /* Get CGU DPLL status (direct 0x0C66) */ 2283 struct ice_aqc_get_cgu_dpll_status { 2284 u8 dpll_num; 2285 u8 ref_state; 2286 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0) 2287 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1) 2288 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2) 2289 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3) 2290 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4) 2291 #define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5) 2292 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6) 2293 u8 dpll_state; 2294 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0) 2295 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO BIT(1) 2296 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2) 2297 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5) 2298 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7) 2299 u8 config; 2300 #define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2301 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2302 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE \ 2303 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2304 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2305 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2306 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2307 __le32 phase_offset_h; 2308 __le32 phase_offset_l; 2309 u8 eec_mode; 2310 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA 2311 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB 2312 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF 2313 u8 rsvd[1]; 2314 __le16 node_handle; 2315 }; 2316 2317 /* Set CGU DPLL config (direct 0x0C67) */ 2318 struct ice_aqc_set_cgu_dpll_config { 2319 u8 dpll_num; 2320 u8 ref_state; 2321 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0) 2322 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1) 2323 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2) 2324 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3) 2325 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4) 2326 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5) 2327 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6) 2328 u8 rsvd; 2329 u8 config; 2330 #define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2331 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2332 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE \ 2333 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2334 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2335 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2336 ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2337 u8 rsvd2[8]; 2338 u8 eec_mode; 2339 u8 rsvd3[1]; 2340 __le16 node_handle; 2341 }; 2342 2343 /* Set CGU reference priority (direct 0x0C68) */ 2344 struct ice_aqc_set_cgu_ref_prio { 2345 u8 dpll_num; 2346 u8 ref_idx; 2347 u8 ref_priority; 2348 u8 rsvd[11]; 2349 __le16 node_handle; 2350 }; 2351 2352 /* Get CGU reference priority (direct 0x0C69) */ 2353 struct ice_aqc_get_cgu_ref_prio { 2354 u8 dpll_num; 2355 u8 ref_idx; 2356 u8 ref_priority; /* Valid only in response */ 2357 u8 rsvd[13]; 2358 }; 2359 2360 /* Get CGU info (direct 0x0C6A) */ 2361 struct ice_aqc_get_cgu_info { 2362 __le32 cgu_id; 2363 __le32 cgu_cfg_ver; 2364 __le32 cgu_fw_ver; 2365 u8 node_part_num; 2366 u8 dev_rev; 2367 __le16 node_handle; 2368 }; 2369 2370 /* Driver Shared Parameters (direct, 0x0C90) */ 2371 struct ice_aqc_driver_shared_params { 2372 u8 set_or_get_op; 2373 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2374 #define ICE_AQC_DRIVER_PARAM_SET 0 2375 #define ICE_AQC_DRIVER_PARAM_GET 1 2376 u8 param_indx; 2377 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2378 u8 rsvd[2]; 2379 __le32 param_val; 2380 __le32 addr_high; 2381 __le32 addr_low; 2382 }; 2383 2384 /* Lan Queue Overflow Event (direct, 0x1001) */ 2385 struct ice_aqc_event_lan_overflow { 2386 __le32 prtdcb_ruptq; 2387 __le32 qtx_ctl; 2388 u8 reserved[8]; 2389 }; 2390 2391 enum ice_aqc_fw_logging_mod { 2392 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2393 ICE_AQC_FW_LOG_ID_CTRL, 2394 ICE_AQC_FW_LOG_ID_LINK, 2395 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2396 ICE_AQC_FW_LOG_ID_DNL, 2397 ICE_AQC_FW_LOG_ID_I2C, 2398 ICE_AQC_FW_LOG_ID_SDP, 2399 ICE_AQC_FW_LOG_ID_MDIO, 2400 ICE_AQC_FW_LOG_ID_ADMINQ, 2401 ICE_AQC_FW_LOG_ID_HDMA, 2402 ICE_AQC_FW_LOG_ID_LLDP, 2403 ICE_AQC_FW_LOG_ID_DCBX, 2404 ICE_AQC_FW_LOG_ID_DCB, 2405 ICE_AQC_FW_LOG_ID_XLR, 2406 ICE_AQC_FW_LOG_ID_NVM, 2407 ICE_AQC_FW_LOG_ID_AUTH, 2408 ICE_AQC_FW_LOG_ID_VPD, 2409 ICE_AQC_FW_LOG_ID_IOSF, 2410 ICE_AQC_FW_LOG_ID_PARSER, 2411 ICE_AQC_FW_LOG_ID_SW, 2412 ICE_AQC_FW_LOG_ID_SCHEDULER, 2413 ICE_AQC_FW_LOG_ID_TXQ, 2414 ICE_AQC_FW_LOG_ID_RSVD, 2415 ICE_AQC_FW_LOG_ID_POST, 2416 ICE_AQC_FW_LOG_ID_WATCHDOG, 2417 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 2418 ICE_AQC_FW_LOG_ID_MNG, 2419 ICE_AQC_FW_LOG_ID_SYNCE, 2420 ICE_AQC_FW_LOG_ID_HEALTH, 2421 ICE_AQC_FW_LOG_ID_TSDRV, 2422 ICE_AQC_FW_LOG_ID_PFREG, 2423 ICE_AQC_FW_LOG_ID_MDLVER, 2424 ICE_AQC_FW_LOG_ID_MAX, 2425 }; 2426 2427 /* Set FW Logging configuration (indirect 0xFF30) 2428 * Register for FW Logging (indirect 0xFF31) 2429 * Query FW Logging (indirect 0xFF32) 2430 * FW Log Event (indirect 0xFF33) 2431 */ 2432 struct ice_aqc_fw_log { 2433 u8 cmd_flags; 2434 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 2435 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 2436 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2) 2437 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 2438 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 2439 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 2440 2441 u8 rsp_flag; 2442 __le16 fw_rt_msb; 2443 union { 2444 struct { 2445 __le32 fw_rt_lsb; 2446 } sync; 2447 struct { 2448 __le16 log_resolution; 2449 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 2450 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 2451 2452 __le16 mdl_cnt; 2453 } cfg; 2454 } ops; 2455 __le32 addr_high; 2456 __le32 addr_low; 2457 }; 2458 2459 /* Response Buffer for: 2460 * Set Firmware Logging Configuration (0xFF30) 2461 * Query FW Logging (0xFF32) 2462 */ 2463 struct ice_aqc_fw_log_cfg_resp { 2464 __le16 module_identifier; 2465 u8 log_level; 2466 u8 rsvd0; 2467 }; 2468 2469 /** 2470 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2471 * @flags: ICE_AQ_FLAG_* flags 2472 * @opcode: AQ command opcode 2473 * @datalen: length in bytes of indirect/external data buffer 2474 * @retval: return value from firmware 2475 * @cookie_high: opaque data high-half 2476 * @cookie_low: opaque data low-half 2477 * @params: command-specific parameters 2478 * 2479 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2480 * (ATQ). The firmware writes back onto the command descriptor and returns 2481 * the result of the command. Asynchronous events that are not an immediate 2482 * result of the command are written to the Admin Receive Queue (ARQ) using 2483 * the same descriptor format. Descriptors are in little-endian notation with 2484 * 32-bit words. 2485 */ 2486 struct ice_aq_desc { 2487 __le16 flags; 2488 __le16 opcode; 2489 __le16 datalen; 2490 __le16 retval; 2491 __le32 cookie_high; 2492 __le32 cookie_low; 2493 union { 2494 u8 raw[16]; 2495 struct ice_aqc_generic generic; 2496 struct ice_aqc_get_ver get_ver; 2497 struct ice_aqc_driver_ver driver_ver; 2498 struct ice_aqc_q_shutdown q_shutdown; 2499 struct ice_aqc_req_res res_owner; 2500 struct ice_aqc_manage_mac_read mac_read; 2501 struct ice_aqc_manage_mac_write mac_write; 2502 struct ice_aqc_clear_pxe clear_pxe; 2503 struct ice_aqc_list_caps get_cap; 2504 struct ice_aqc_get_phy_caps get_phy; 2505 struct ice_aqc_set_phy_cfg set_phy; 2506 struct ice_aqc_restart_an restart_an; 2507 struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out; 2508 struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out; 2509 struct ice_aqc_get_sensor_reading get_sensor_reading; 2510 struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp; 2511 struct ice_aqc_gpio read_write_gpio; 2512 struct ice_aqc_sff_eeprom read_write_sff_param; 2513 struct ice_aqc_set_port_id_led set_port_id_led; 2514 struct ice_aqc_get_port_options get_port_options; 2515 struct ice_aqc_set_port_option set_port_option; 2516 struct ice_aqc_get_sw_cfg get_sw_conf; 2517 struct ice_aqc_set_port_params set_port_params; 2518 struct ice_aqc_sw_rules sw_rules; 2519 struct ice_aqc_add_get_recipe add_get_recipe; 2520 struct ice_aqc_recipe_to_profile recipe_to_profile; 2521 struct ice_aqc_get_topo get_topo; 2522 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2523 struct ice_aqc_query_txsched_res query_sched_res; 2524 struct ice_aqc_query_port_ets port_ets; 2525 struct ice_aqc_rl_profile rl_profile; 2526 struct ice_aqc_nvm nvm; 2527 struct ice_aqc_nvm_checksum nvm_checksum; 2528 struct ice_aqc_nvm_pkg_data pkg_data; 2529 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl; 2530 struct ice_aqc_pf_vf_msg virt; 2531 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2532 struct ice_aqc_lldp_get_mib lldp_get_mib; 2533 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2534 struct ice_aqc_lldp_stop lldp_stop; 2535 struct ice_aqc_lldp_start lldp_start; 2536 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2537 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2538 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2539 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2540 struct ice_aqc_get_set_rss_key get_set_rss_key; 2541 struct ice_aqc_neigh_dev_req neigh_dev; 2542 struct ice_aqc_add_txqs add_txqs; 2543 struct ice_aqc_dis_txqs dis_txqs; 2544 struct ice_aqc_cfg_txqs cfg_txqs; 2545 struct ice_aqc_add_rdma_qset add_rdma_qset; 2546 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2547 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2548 struct ice_aqc_download_pkg download_pkg; 2549 struct ice_aqc_set_cgu_input_config set_cgu_input_config; 2550 struct ice_aqc_get_cgu_input_config get_cgu_input_config; 2551 struct ice_aqc_set_cgu_output_config set_cgu_output_config; 2552 struct ice_aqc_get_cgu_output_config get_cgu_output_config; 2553 struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status; 2554 struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config; 2555 struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio; 2556 struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio; 2557 struct ice_aqc_get_cgu_info get_cgu_info; 2558 struct ice_aqc_driver_shared_params drv_shared_params; 2559 struct ice_aqc_fw_log fw_log; 2560 struct ice_aqc_set_mac_lb set_mac_lb; 2561 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2562 struct ice_aqc_set_mac_cfg set_mac_cfg; 2563 struct ice_aqc_set_event_mask set_event_mask; 2564 struct ice_aqc_get_link_status get_link_status; 2565 struct ice_aqc_event_lan_overflow lan_overflow; 2566 struct ice_aqc_get_link_topo get_link_topo; 2567 struct ice_aqc_i2c read_write_i2c; 2568 struct ice_aqc_read_i2c_resp read_i2c_resp; 2569 struct ice_aqc_get_set_tx_topo get_set_tx_topo; 2570 } params; 2571 }; 2572 2573 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2574 #define ICE_AQ_LG_BUF 512 2575 2576 #define ICE_AQ_FLAG_ERR_S 2 2577 #define ICE_AQ_FLAG_LB_S 9 2578 #define ICE_AQ_FLAG_RD_S 10 2579 #define ICE_AQ_FLAG_BUF_S 12 2580 #define ICE_AQ_FLAG_SI_S 13 2581 2582 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2583 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2584 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2585 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2586 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2587 2588 /* error codes */ 2589 enum ice_aq_err { 2590 ICE_AQ_RC_OK = 0, /* Success */ 2591 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2592 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2593 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2594 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2595 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2596 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2597 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2598 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2599 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2600 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2601 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2602 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2603 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2604 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2605 }; 2606 2607 /* Admin Queue command opcodes */ 2608 enum ice_adminq_opc { 2609 /* AQ commands */ 2610 ice_aqc_opc_get_ver = 0x0001, 2611 ice_aqc_opc_driver_ver = 0x0002, 2612 ice_aqc_opc_q_shutdown = 0x0003, 2613 2614 /* resource ownership */ 2615 ice_aqc_opc_req_res = 0x0008, 2616 ice_aqc_opc_release_res = 0x0009, 2617 2618 /* device/function capabilities */ 2619 ice_aqc_opc_list_func_caps = 0x000A, 2620 ice_aqc_opc_list_dev_caps = 0x000B, 2621 2622 /* manage MAC address */ 2623 ice_aqc_opc_manage_mac_read = 0x0107, 2624 ice_aqc_opc_manage_mac_write = 0x0108, 2625 2626 /* PXE */ 2627 ice_aqc_opc_clear_pxe_mode = 0x0110, 2628 2629 /* internal switch commands */ 2630 ice_aqc_opc_get_sw_cfg = 0x0200, 2631 ice_aqc_opc_set_port_params = 0x0203, 2632 2633 /* Alloc/Free/Get Resources */ 2634 ice_aqc_opc_alloc_res = 0x0208, 2635 ice_aqc_opc_free_res = 0x0209, 2636 ice_aqc_opc_share_res = 0x020B, 2637 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 2638 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 2639 2640 /* VSI commands */ 2641 ice_aqc_opc_add_vsi = 0x0210, 2642 ice_aqc_opc_update_vsi = 0x0211, 2643 ice_aqc_opc_free_vsi = 0x0213, 2644 2645 /* recipe commands */ 2646 ice_aqc_opc_add_recipe = 0x0290, 2647 ice_aqc_opc_recipe_to_profile = 0x0291, 2648 ice_aqc_opc_get_recipe = 0x0292, 2649 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2650 2651 /* switch rules population commands */ 2652 ice_aqc_opc_add_sw_rules = 0x02A0, 2653 ice_aqc_opc_update_sw_rules = 0x02A1, 2654 ice_aqc_opc_remove_sw_rules = 0x02A2, 2655 2656 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2657 2658 /* DCB commands */ 2659 ice_aqc_opc_query_pfc_mode = 0x0302, 2660 ice_aqc_opc_set_pfc_mode = 0x0303, 2661 2662 /* transmit scheduler commands */ 2663 ice_aqc_opc_get_dflt_topo = 0x0400, 2664 ice_aqc_opc_add_sched_elems = 0x0401, 2665 ice_aqc_opc_cfg_sched_elems = 0x0403, 2666 ice_aqc_opc_get_sched_elems = 0x0404, 2667 ice_aqc_opc_move_sched_elems = 0x0408, 2668 ice_aqc_opc_suspend_sched_elems = 0x0409, 2669 ice_aqc_opc_resume_sched_elems = 0x040A, 2670 ice_aqc_opc_query_port_ets = 0x040E, 2671 ice_aqc_opc_delete_sched_elems = 0x040F, 2672 ice_aqc_opc_add_rl_profiles = 0x0410, 2673 ice_aqc_opc_query_sched_res = 0x0412, 2674 ice_aqc_opc_remove_rl_profiles = 0x0415, 2675 2676 /* tx topology commands */ 2677 ice_aqc_opc_set_tx_topo = 0x0417, 2678 ice_aqc_opc_get_tx_topo = 0x0418, 2679 2680 /* PHY commands */ 2681 ice_aqc_opc_get_phy_caps = 0x0600, 2682 ice_aqc_opc_set_phy_cfg = 0x0601, 2683 ice_aqc_opc_set_mac_cfg = 0x0603, 2684 ice_aqc_opc_restart_an = 0x0605, 2685 ice_aqc_opc_get_link_status = 0x0607, 2686 ice_aqc_opc_set_event_mask = 0x0613, 2687 ice_aqc_opc_set_mac_lb = 0x0620, 2688 ice_aqc_opc_set_phy_rec_clk_out = 0x0630, 2689 ice_aqc_opc_get_phy_rec_clk_out = 0x0631, 2690 ice_aqc_opc_get_sensor_reading = 0x0632, 2691 ice_aqc_opc_get_link_topo = 0x06E0, 2692 ice_aqc_opc_read_i2c = 0x06E2, 2693 ice_aqc_opc_write_i2c = 0x06E3, 2694 ice_aqc_opc_set_port_id_led = 0x06E9, 2695 ice_aqc_opc_get_port_options = 0x06EA, 2696 ice_aqc_opc_set_port_option = 0x06EB, 2697 ice_aqc_opc_set_gpio = 0x06EC, 2698 ice_aqc_opc_get_gpio = 0x06ED, 2699 ice_aqc_opc_sff_eeprom = 0x06EE, 2700 2701 /* NVM commands */ 2702 ice_aqc_opc_nvm_read = 0x0701, 2703 ice_aqc_opc_nvm_erase = 0x0702, 2704 ice_aqc_opc_nvm_write = 0x0703, 2705 ice_aqc_opc_nvm_checksum = 0x0706, 2706 ice_aqc_opc_nvm_write_activate = 0x0707, 2707 ice_aqc_opc_nvm_update_empr = 0x0709, 2708 ice_aqc_opc_nvm_pkg_data = 0x070A, 2709 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2710 2711 /* PF/VF mailbox commands */ 2712 ice_mbx_opc_send_msg_to_pf = 0x0801, 2713 ice_mbx_opc_send_msg_to_vf = 0x0802, 2714 /* LLDP commands */ 2715 ice_aqc_opc_lldp_get_mib = 0x0A00, 2716 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2717 ice_aqc_opc_lldp_stop = 0x0A05, 2718 ice_aqc_opc_lldp_start = 0x0A06, 2719 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2720 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2721 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2722 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2723 ice_aqc_opc_lldp_execute_pending_mib = 0x0A0B, 2724 2725 /* RSS commands */ 2726 ice_aqc_opc_set_rss_key = 0x0B02, 2727 ice_aqc_opc_set_rss_lut = 0x0B03, 2728 ice_aqc_opc_get_rss_key = 0x0B04, 2729 ice_aqc_opc_get_rss_lut = 0x0B05, 2730 2731 /* Sideband Control Interface commands */ 2732 ice_aqc_opc_neighbour_device_request = 0x0C00, 2733 2734 /* Tx queue handling commands/events */ 2735 ice_aqc_opc_add_txqs = 0x0C30, 2736 ice_aqc_opc_dis_txqs = 0x0C31, 2737 ice_aqc_opc_cfg_txqs = 0x0C32, 2738 ice_aqc_opc_add_rdma_qset = 0x0C33, 2739 2740 /* package commands */ 2741 ice_aqc_opc_download_pkg = 0x0C40, 2742 ice_aqc_opc_upload_section = 0x0C41, 2743 ice_aqc_opc_update_pkg = 0x0C42, 2744 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2745 2746 /* 1588/SyncE commands/events */ 2747 ice_aqc_opc_get_cgu_abilities = 0x0C61, 2748 ice_aqc_opc_set_cgu_input_config = 0x0C62, 2749 ice_aqc_opc_get_cgu_input_config = 0x0C63, 2750 ice_aqc_opc_set_cgu_output_config = 0x0C64, 2751 ice_aqc_opc_get_cgu_output_config = 0x0C65, 2752 ice_aqc_opc_get_cgu_dpll_status = 0x0C66, 2753 ice_aqc_opc_set_cgu_dpll_config = 0x0C67, 2754 ice_aqc_opc_set_cgu_ref_prio = 0x0C68, 2755 ice_aqc_opc_get_cgu_ref_prio = 0x0C69, 2756 ice_aqc_opc_get_cgu_info = 0x0C6A, 2757 2758 ice_aqc_opc_driver_shared_params = 0x0C90, 2759 2760 /* Standalone Commands/Events */ 2761 ice_aqc_opc_event_lan_overflow = 0x1001, 2762 2763 /* FW Logging Commands */ 2764 ice_aqc_opc_fw_logs_config = 0xFF30, 2765 ice_aqc_opc_fw_logs_register = 0xFF31, 2766 ice_aqc_opc_fw_logs_query = 0xFF32, 2767 ice_aqc_opc_fw_logs_event = 0xFF33, 2768 }; 2769 2770 #endif /* _ICE_ADMINQ_CMD_H_ */ 2771