1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Send driver version (indirect 0x0002) */ 37 struct ice_aqc_driver_ver { 38 u8 major_ver; 39 u8 minor_ver; 40 u8 build_ver; 41 u8 subbuild_ver; 42 u8 reserved[4]; 43 __le32 addr_high; 44 __le32 addr_low; 45 }; 46 47 /* Queue Shutdown (direct 0x0003) */ 48 struct ice_aqc_q_shutdown { 49 u8 driver_unloading; 50 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 51 u8 reserved[15]; 52 }; 53 54 /* Request resource ownership (direct 0x0008) 55 * Release resource ownership (direct 0x0009) 56 */ 57 struct ice_aqc_req_res { 58 __le16 res_id; 59 #define ICE_AQC_RES_ID_NVM 1 60 #define ICE_AQC_RES_ID_SDP 2 61 #define ICE_AQC_RES_ID_CHNG_LOCK 3 62 #define ICE_AQC_RES_ID_GLBL_LOCK 4 63 __le16 access_type; 64 #define ICE_AQC_RES_ACCESS_READ 1 65 #define ICE_AQC_RES_ACCESS_WRITE 2 66 67 /* Upon successful completion, FW writes this value and driver is 68 * expected to release resource before timeout. This value is provided 69 * in milliseconds. 70 */ 71 __le32 timeout; 72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76 /* For SDP: pin ID of the SDP */ 77 __le32 res_number; 78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79 __le16 status; 80 #define ICE_AQ_RES_GLBL_SUCCESS 0 81 #define ICE_AQ_RES_GLBL_IN_PROG 1 82 #define ICE_AQ_RES_GLBL_DONE 2 83 u8 reserved[2]; 84 }; 85 86 /* Get function capabilities (indirect 0x000A) 87 * Get device capabilities (indirect 0x000B) 88 */ 89 struct ice_aqc_list_caps { 90 u8 cmd_flags; 91 u8 pf_index; 92 u8 reserved[2]; 93 __le32 count; 94 __le32 addr_high; 95 __le32 addr_low; 96 }; 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_SRIOV 0x0012 103 #define ICE_AQC_CAPS_VF 0x0013 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_1588 0x0046 112 #define ICE_AQC_CAPS_MAX_MTU 0x0047 113 #define ICE_AQC_CAPS_NVM_VER 0x0048 114 #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049 115 #define ICE_AQC_CAPS_OROM_VER 0x004A 116 #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B 117 #define ICE_AQC_CAPS_NET_VER 0x004C 118 #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D 119 #define ICE_AQC_CAPS_RDMA 0x0051 120 #define ICE_AQC_CAPS_SENSOR_READING 0x0067 121 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 122 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 123 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 124 #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085 125 #define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092 126 #define ICE_AQC_BIT_ROCEV2_LAG 0x01 127 #define ICE_AQC_BIT_SRIOV_LAG 0x02 128 129 u8 major_ver; 130 u8 minor_ver; 131 /* Number of resources described by this capability */ 132 __le32 number; 133 /* Only meaningful for some types of resources */ 134 __le32 logical_id; 135 /* Only meaningful for some types of resources */ 136 __le32 phys_id; 137 __le64 rsvd1; 138 __le64 rsvd2; 139 }; 140 141 /* Manage MAC address, read command - indirect (0x0107) 142 * This struct is also used for the response 143 */ 144 struct ice_aqc_manage_mac_read { 145 __le16 flags; /* Zeroed by device driver */ 146 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 147 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 148 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 149 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 150 #define ICE_AQC_MAN_MAC_READ_S 4 151 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 152 u8 rsvd[2]; 153 u8 num_addr; /* Used in response */ 154 u8 rsvd1[3]; 155 __le32 addr_high; 156 __le32 addr_low; 157 }; 158 159 /* Response buffer format for manage MAC read command */ 160 struct ice_aqc_manage_mac_read_resp { 161 u8 lport_num; 162 u8 addr_type; 163 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 164 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 165 u8 mac_addr[ETH_ALEN]; 166 }; 167 168 /* Manage MAC address, write command - direct (0x0108) */ 169 struct ice_aqc_manage_mac_write { 170 u8 rsvd; 171 u8 flags; 172 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 173 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 174 #define ICE_AQC_MAN_MAC_WR_S 6 175 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 176 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 177 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 178 /* byte stream in network order */ 179 u8 mac_addr[ETH_ALEN]; 180 __le32 addr_high; 181 __le32 addr_low; 182 }; 183 184 /* Clear PXE Command and response (direct 0x0110) */ 185 struct ice_aqc_clear_pxe { 186 u8 rx_cnt; 187 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 188 u8 reserved[15]; 189 }; 190 191 /* Get switch configuration (0x0200) */ 192 struct ice_aqc_get_sw_cfg { 193 /* Reserved for command and copy of request flags for response */ 194 __le16 flags; 195 /* First desc in case of command and next_elem in case of response 196 * In case of response, if it is not zero, means all the configuration 197 * was not returned and new command shall be sent with this value in 198 * the 'first desc' field 199 */ 200 __le16 element; 201 /* Reserved for command, only used for response */ 202 __le16 num_elems; 203 __le16 rsvd; 204 __le32 addr_high; 205 __le32 addr_low; 206 }; 207 208 /* Each entry in the response buffer is of the following type: */ 209 struct ice_aqc_get_sw_cfg_resp_elem { 210 /* VSI/Port Number */ 211 __le16 vsi_port_num; 212 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 213 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 214 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 215 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 216 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 217 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 218 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 219 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 220 221 /* SWID VSI/Port belongs to */ 222 __le16 swid; 223 224 /* Bit 14..0 : PF/VF number VSI belongs to 225 * Bit 15 : VF indication bit 226 */ 227 __le16 pf_vf_num; 228 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 229 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 230 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 231 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 232 }; 233 234 /* Set Port parameters, (direct, 0x0203) */ 235 struct ice_aqc_set_port_params { 236 __le16 cmd_flags; 237 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 238 __le16 bad_frame_vsi; 239 __le16 swid; 240 #define ICE_AQC_PORT_SWID_VALID BIT(15) 241 #define ICE_AQC_PORT_SWID_M 0xFF 242 u8 reserved[10]; 243 }; 244 245 /* These resource type defines are used for all switch resource 246 * commands where a resource type is required, such as: 247 * Get Resource Allocation command (indirect 0x0204) 248 * Allocate Resources command (indirect 0x0208) 249 * Free Resources command (indirect 0x0209) 250 * Get Allocated Resource Descriptors Command (indirect 0x020A) 251 * Share Resource command (indirect 0x020B) 252 */ 253 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 254 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 255 #define ICE_AQC_RES_TYPE_RECIPE 0x05 256 #define ICE_AQC_RES_TYPE_SWID 0x07 257 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 258 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 259 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 260 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 261 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 262 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 263 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 264 265 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 266 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 267 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 268 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14) 269 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15) 270 271 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 272 273 #define ICE_AQC_RES_TYPE_S 0 274 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 275 276 /* Allocate Resources command (indirect 0x0208) 277 * Free Resources command (indirect 0x0209) 278 * Share Resource command (indirect 0x020B) 279 */ 280 struct ice_aqc_alloc_free_res_cmd { 281 __le16 num_entries; /* Number of Resource entries */ 282 u8 reserved[6]; 283 __le32 addr_high; 284 __le32 addr_low; 285 }; 286 287 /* Resource descriptor */ 288 struct ice_aqc_res_elem { 289 union { 290 __le16 sw_resp; 291 __le16 flu_resp; 292 } e; 293 }; 294 295 /* Buffer for Allocate/Free Resources commands */ 296 struct ice_aqc_alloc_free_res_elem { 297 __le16 res_type; /* Types defined above cmd 0x0204 */ 298 #define ICE_AQC_RES_TYPE_SHARED_S 7 299 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 300 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 301 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 302 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 303 __le16 num_elems; 304 struct ice_aqc_res_elem elem[]; 305 }; 306 307 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 308 struct ice_aqc_set_vlan_mode { 309 u8 reserved; 310 u8 l2tag_prio_tagging; 311 #define ICE_AQ_VLAN_PRIO_TAG_S 0 312 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 313 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 314 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 315 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 316 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 317 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 318 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 319 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 320 u8 l2tag_reserved[64]; 321 u8 rdma_packet; 322 #define ICE_AQ_VLAN_RDMA_TAG_S 0 323 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 324 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 325 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 326 u8 rdma_reserved[2]; 327 u8 mng_vlan_prot_id; 328 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 329 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 330 u8 prot_id_reserved[30]; 331 }; 332 333 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 334 struct ice_aqc_get_vlan_mode { 335 u8 vlan_mode; 336 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 337 u8 l2tag_prio_tagging; 338 u8 reserved[98]; 339 }; 340 341 /* Add VSI (indirect 0x0210) 342 * Update VSI (indirect 0x0211) 343 * Get VSI (indirect 0x0212) 344 * Free VSI (indirect 0x0213) 345 */ 346 struct ice_aqc_add_get_update_free_vsi { 347 __le16 vsi_num; 348 #define ICE_AQ_VSI_NUM_S 0 349 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 350 #define ICE_AQ_VSI_IS_VALID BIT(15) 351 __le16 cmd_flags; 352 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 353 u8 vf_id; 354 u8 reserved; 355 __le16 vsi_flags; 356 #define ICE_AQ_VSI_TYPE_S 0 357 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 358 #define ICE_AQ_VSI_TYPE_VF 0x0 359 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 360 #define ICE_AQ_VSI_TYPE_PF 0x2 361 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 362 __le32 addr_high; 363 __le32 addr_low; 364 }; 365 366 /* Response descriptor for: 367 * Add VSI (indirect 0x0210) 368 * Update VSI (indirect 0x0211) 369 * Free VSI (indirect 0x0213) 370 */ 371 struct ice_aqc_add_update_free_vsi_resp { 372 __le16 vsi_num; 373 __le16 ext_status; 374 __le16 vsi_used; 375 __le16 vsi_free; 376 __le32 addr_high; 377 __le32 addr_low; 378 }; 379 380 struct ice_aqc_vsi_props { 381 __le16 valid_sections; 382 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 383 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 384 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 385 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 386 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 387 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 388 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 389 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 390 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 391 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 392 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 393 /* switch section */ 394 u8 sw_id; 395 u8 sw_flags; 396 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 397 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 398 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 399 u8 sw_flags2; 400 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 401 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 402 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 403 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 404 u8 veb_stat_id; 405 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 406 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 407 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 408 /* security section */ 409 u8 sec_flags; 410 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 411 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 412 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 413 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 414 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 415 u8 sec_reserved; 416 /* VLAN section */ 417 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 418 u8 inner_vlan_reserved[2]; 419 u8 inner_vlan_flags; 420 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 421 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 422 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 423 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 424 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 425 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 426 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 427 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 428 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH 0x0U 429 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP 0x1U 430 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR 0x2U 431 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING 0x3U 432 u8 inner_vlan_reserved2[3]; 433 /* ingress egress up sections */ 434 __le32 ingress_table; /* bitmap, 3 bits per up */ 435 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 436 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 437 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 438 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 439 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 440 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 441 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 442 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 443 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 444 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 445 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 446 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 447 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 448 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 449 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 450 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 451 __le32 egress_table; /* same defines as for ingress table */ 452 /* outer tags section */ 453 __le16 port_based_outer_vlan; 454 u8 outer_vlan_flags; 455 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 456 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 457 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 458 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 459 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 460 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 461 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 462 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 463 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 464 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 465 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 466 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 467 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 468 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 469 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 470 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 471 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 472 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 473 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 474 u8 outer_vlan_reserved; 475 /* queue mapping section */ 476 __le16 mapping_flags; 477 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 478 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 479 __le16 q_mapping[16]; 480 #define ICE_AQ_VSI_Q_S 0 481 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 482 __le16 tc_mapping[8]; 483 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 484 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 485 #define ICE_AQ_VSI_TC_Q_NUM_S 11 486 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 487 /* queueing option section */ 488 u8 q_opt_rss; 489 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 490 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 491 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 492 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 493 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 494 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 495 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 496 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 497 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6) 498 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ 0x0U 499 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ 0x1U 500 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR 0x2U 501 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH 0x3U 502 u8 q_opt_tc; 503 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 504 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 505 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 506 u8 q_opt_flags; 507 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 508 u8 q_opt_reserved[3]; 509 /* outer up section */ 510 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 511 /* section 10 */ 512 __le16 sect_10_reserved; 513 /* flow director section */ 514 __le16 fd_options; 515 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 516 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 517 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 518 __le16 max_fd_fltr_dedicated; 519 __le16 max_fd_fltr_shared; 520 __le16 fd_def_q; 521 #define ICE_AQ_VSI_FD_DEF_Q_S 0 522 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 523 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 524 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 525 __le16 fd_report_opt; 526 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 527 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 528 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 529 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 530 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 531 /* PASID section */ 532 __le32 pasid_id; 533 #define ICE_AQ_VSI_PASID_ID_S 0 534 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 535 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 536 u8 reserved[24]; 537 }; 538 539 #define ICE_MAX_NUM_RECIPES 64 540 541 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 542 struct ice_aqc_add_get_recipe { 543 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 544 __le16 return_index; /* Input, used for Get cmd only */ 545 u8 reserved[4]; 546 __le32 addr_high; 547 __le32 addr_low; 548 }; 549 550 struct ice_aqc_recipe_content { 551 u8 rid; 552 #define ICE_AQ_RECIPE_ID_S 0 553 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 554 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 555 #define ICE_AQ_SW_ID_LKUP_IDX 0 556 u8 lkup_indx[5]; 557 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 558 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 559 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 560 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 561 __le16 mask[5]; 562 u8 result_indx; 563 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 564 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 565 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 566 u8 rsvd0[3]; 567 u8 act_ctrl_join_priority; 568 u8 act_ctrl_fwd_priority; 569 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 570 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 571 u8 act_ctrl; 572 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 573 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 574 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 575 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 576 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 577 u8 rsvd1; 578 __le32 dflt_act; 579 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 580 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 581 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 582 }; 583 584 struct ice_aqc_recipe_data_elem { 585 u8 recipe_indx; 586 u8 resp_bits; 587 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 588 u8 rsvd0[2]; 589 u8 recipe_bitmap[8]; 590 u8 rsvd1[4]; 591 struct ice_aqc_recipe_content content; 592 u8 rsvd2[20]; 593 }; 594 595 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 596 struct ice_aqc_recipe_to_profile { 597 __le16 profile_id; 598 u8 rsvd[6]; 599 __le64 recipe_assoc; 600 }; 601 static_assert(sizeof(struct ice_aqc_recipe_to_profile) == 16); 602 603 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 604 */ 605 struct ice_aqc_sw_rules { 606 /* ops: add switch rules, referring the number of rules. 607 * ops: update switch rules, referring the number of filters 608 * ops: remove switch rules, referring the entry index. 609 * ops: get switch rules, referring to the number of filters. 610 */ 611 __le16 num_rules_fltr_entry_index; 612 u8 reserved[6]; 613 __le32 addr_high; 614 __le32 addr_low; 615 }; 616 617 /* Add switch rule response: 618 * Content of return buffer is same as the input buffer. The status field and 619 * LUT index are updated as part of the response 620 */ 621 struct ice_aqc_sw_rules_elem_hdr { 622 __le16 type; /* Switch rule type, one of T_... */ 623 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 624 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 625 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 626 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 627 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 628 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 629 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 630 __le16 status; 631 } __packed __aligned(sizeof(__le16)); 632 633 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 634 * This structures describes the lookup rules and associated actions. "index" 635 * is returned as part of a response to a successful Add command, and can be 636 * used to identify the rule for Update/Get/Remove commands. 637 */ 638 struct ice_sw_rule_lkup_rx_tx { 639 struct ice_aqc_sw_rules_elem_hdr hdr; 640 641 __le16 recipe_id; 642 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 643 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 644 __le16 src; 645 __le32 act; 646 647 /* Bit 0:1 - Action type */ 648 #define ICE_SINGLE_ACT_TYPE_S 0x00 649 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 650 651 /* Bit 2 - Loop back enable 652 * Bit 3 - LAN enable 653 */ 654 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 655 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 656 657 /* Action type = 0 - Forward to VSI or VSI list */ 658 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 659 660 #define ICE_SINGLE_ACT_VSI_ID_S 4 661 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 662 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 663 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 664 /* This bit needs to be set if action is forward to VSI list */ 665 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 666 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 667 #define ICE_SINGLE_ACT_DROP BIT(18) 668 669 /* Action type = 1 - Forward to Queue of Queue group */ 670 #define ICE_SINGLE_ACT_TO_Q 0x1 671 #define ICE_SINGLE_ACT_Q_INDEX_S 4 672 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 673 #define ICE_SINGLE_ACT_Q_REGION_S 15 674 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 675 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 676 677 /* Action type = 2 - Prune */ 678 #define ICE_SINGLE_ACT_PRUNE 0x2 679 #define ICE_SINGLE_ACT_EGRESS BIT(15) 680 #define ICE_SINGLE_ACT_INGRESS BIT(16) 681 #define ICE_SINGLE_ACT_PRUNET BIT(17) 682 /* Bit 18 should be set to 0 for this action */ 683 684 /* Action type = 2 - Pointer */ 685 #define ICE_SINGLE_ACT_PTR 0x2 686 #define ICE_SINGLE_ACT_PTR_VAL_S 4 687 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 688 /* Bit 18 should be set to 1 */ 689 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 690 691 /* Action type = 3 - Other actions. Last two bits 692 * are other action identifier 693 */ 694 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 695 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 696 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 697 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 698 699 /* Bit 17:18 - Defines other actions */ 700 /* Other action = 0 - Mirror VSI */ 701 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 702 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 703 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 704 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 705 706 /* Other action = 3 - Set Stat count */ 707 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 708 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 709 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 710 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 711 712 __le16 index; /* The index of the rule in the lookup table */ 713 /* Length and values of the header to be matched per recipe or 714 * lookup-type 715 */ 716 __le16 hdr_len; 717 u8 hdr_data[]; 718 } __packed __aligned(sizeof(__le16)); 719 720 /* Add/Update/Remove large action command/response entry 721 * "index" is returned as part of a response to a successful Add command, and 722 * can be used to identify the action for Update/Get/Remove commands. 723 */ 724 struct ice_sw_rule_lg_act { 725 struct ice_aqc_sw_rules_elem_hdr hdr; 726 727 __le16 index; /* Index in large action table */ 728 __le16 size; 729 /* Max number of large actions */ 730 #define ICE_MAX_LG_ACT 4 731 /* Bit 0:1 - Action type */ 732 #define ICE_LG_ACT_TYPE_S 0 733 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 734 735 /* Action type = 0 - Forward to VSI or VSI list */ 736 #define ICE_LG_ACT_VSI_FORWARDING 0 737 #define ICE_LG_ACT_VSI_ID_S 3 738 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 739 #define ICE_LG_ACT_VSI_LIST_ID_S 3 740 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 741 /* This bit needs to be set if action is forward to VSI list */ 742 #define ICE_LG_ACT_VSI_LIST BIT(13) 743 744 #define ICE_LG_ACT_VALID_BIT BIT(16) 745 746 /* Action type = 1 - Forward to Queue of Queue group */ 747 #define ICE_LG_ACT_TO_Q 0x1 748 #define ICE_LG_ACT_Q_INDEX_S 3 749 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 750 #define ICE_LG_ACT_Q_REGION_S 14 751 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 752 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 753 754 /* Action type = 2 - Prune */ 755 #define ICE_LG_ACT_PRUNE 0x2 756 #define ICE_LG_ACT_EGRESS BIT(14) 757 #define ICE_LG_ACT_INGRESS BIT(15) 758 #define ICE_LG_ACT_PRUNET BIT(16) 759 760 /* Action type = 3 - Mirror VSI */ 761 #define ICE_LG_OTHER_ACT_MIRROR 0x3 762 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 763 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 764 765 /* Action type = 5 - Generic Value */ 766 #define ICE_LG_ACT_GENERIC 0x5 767 #define ICE_LG_ACT_GENERIC_VALUE_S 3 768 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 769 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 770 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 771 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 772 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 773 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 774 775 /* Action = 7 - Set Stat count */ 776 #define ICE_LG_ACT_STAT_COUNT 0x7 777 #define ICE_LG_ACT_STAT_COUNT_S 3 778 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 779 __le32 act[]; /* array of size for actions */ 780 } __packed __aligned(sizeof(__le16)); 781 782 /* Add/Update/Remove VSI list command/response entry 783 * "index" is returned as part of a response to a successful Add command, and 784 * can be used to identify the VSI list for Update/Get/Remove commands. 785 */ 786 struct ice_sw_rule_vsi_list { 787 struct ice_aqc_sw_rules_elem_hdr hdr; 788 789 __le16 index; /* Index of VSI/Prune list */ 790 __le16 number_vsi; 791 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 792 } __packed __aligned(sizeof(__le16)); 793 794 /* Query PFC Mode (direct 0x0302) 795 * Set PFC Mode (direct 0x0303) 796 */ 797 struct ice_aqc_set_query_pfc_mode { 798 u8 pfc_mode; 799 /* For Query Command response, reserved in all other cases */ 800 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 801 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 802 u8 rsvd[15]; 803 }; 804 /* Get Default Topology (indirect 0x0400) */ 805 struct ice_aqc_get_topo { 806 u8 port_num; 807 u8 num_branches; 808 __le16 reserved1; 809 __le32 reserved2; 810 __le32 addr_high; 811 __le32 addr_low; 812 }; 813 814 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */ 815 struct ice_aqc_get_set_tx_topo { 816 u8 set_flags; 817 #define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0) 818 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1) 819 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4) 820 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5) 821 822 u8 get_flags; 823 #define ICE_AQC_TX_TOPO_GET_RAM 2 824 825 __le16 reserved1; 826 __le32 reserved2; 827 __le32 addr_high; 828 __le32 addr_low; 829 }; 830 831 /* Update TSE (indirect 0x0403) 832 * Get TSE (indirect 0x0404) 833 * Add TSE (indirect 0x0401) 834 * Delete TSE (indirect 0x040F) 835 * Move TSE (indirect 0x0408) 836 * Suspend Nodes (indirect 0x0409) 837 * Resume Nodes (indirect 0x040A) 838 */ 839 struct ice_aqc_sched_elem_cmd { 840 __le16 num_elem_req; /* Used by commands */ 841 __le16 num_elem_resp; /* Used by responses */ 842 __le32 reserved; 843 __le32 addr_high; 844 __le32 addr_low; 845 }; 846 847 struct ice_aqc_txsched_move_grp_info_hdr { 848 __le32 src_parent_teid; 849 __le32 dest_parent_teid; 850 __le16 num_elems; 851 u8 mode; 852 #define ICE_AQC_MOVE_ELEM_MODE_SAME_PF 0x0 853 #define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN 0x1 854 #define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN 0x2 855 u8 reserved; 856 }; 857 858 struct ice_aqc_move_elem { 859 struct ice_aqc_txsched_move_grp_info_hdr hdr; 860 __le32 teid[]; 861 }; 862 863 struct ice_aqc_elem_info_bw { 864 __le16 bw_profile_idx; 865 __le16 bw_alloc; 866 }; 867 868 struct ice_aqc_txsched_elem { 869 u8 elem_type; /* Special field, reserved for some aq calls */ 870 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 871 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 872 #define ICE_AQC_ELEM_TYPE_TC 0x2 873 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 874 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 875 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 876 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 877 u8 valid_sections; 878 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 879 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 880 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 881 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 882 u8 generic; 883 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 884 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 885 #define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1) 886 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 887 #define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4) 888 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 889 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 890 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 891 u8 flags; /* Special field, reserved for some aq calls */ 892 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 893 struct ice_aqc_elem_info_bw cir_bw; 894 struct ice_aqc_elem_info_bw eir_bw; 895 __le16 srl_id; 896 __le16 reserved2; 897 }; 898 899 struct ice_aqc_txsched_elem_data { 900 __le32 parent_teid; 901 __le32 node_teid; 902 struct ice_aqc_txsched_elem data; 903 }; 904 905 struct ice_aqc_txsched_topo_grp_info_hdr { 906 __le32 parent_teid; 907 __le16 num_elems; 908 __le16 reserved2; 909 }; 910 911 struct ice_aqc_add_elem { 912 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 913 struct ice_aqc_txsched_elem_data generic[]; 914 }; 915 916 struct ice_aqc_get_topo_elem { 917 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 918 struct ice_aqc_txsched_elem_data 919 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 920 }; 921 922 struct ice_aqc_delete_elem { 923 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 924 __le32 teid[]; 925 }; 926 927 /* Query Port ETS (indirect 0x040E) 928 * 929 * This indirect command is used to query port TC node configuration. 930 */ 931 struct ice_aqc_query_port_ets { 932 __le32 port_teid; 933 __le32 reserved; 934 __le32 addr_high; 935 __le32 addr_low; 936 }; 937 938 struct ice_aqc_port_ets_elem { 939 u8 tc_valid_bits; 940 u8 reserved[3]; 941 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 942 __le32 up2tc; 943 u8 tc_bw_share[8]; 944 __le32 port_eir_prof_id; 945 __le32 port_cir_prof_id; 946 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 947 __le32 tc_node_prio; 948 #define ICE_TC_NODE_PRIO_S 0x4 949 u8 reserved1[4]; 950 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 951 }; 952 953 /* Rate limiting profile for 954 * Add RL profile (indirect 0x0410) 955 * Query RL profile (indirect 0x0411) 956 * Remove RL profile (indirect 0x0415) 957 * These indirect commands acts on single or multiple 958 * RL profiles with specified data. 959 */ 960 struct ice_aqc_rl_profile { 961 __le16 num_profiles; 962 __le16 num_processed; /* Only for response. Reserved in Command. */ 963 u8 reserved[4]; 964 __le32 addr_high; 965 __le32 addr_low; 966 }; 967 968 struct ice_aqc_rl_profile_elem { 969 u8 level; 970 u8 flags; 971 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 972 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 973 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 974 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 975 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 976 /* The following flag is used for Query RL Profile Data */ 977 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 978 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 979 980 __le16 profile_id; 981 __le16 max_burst_size; 982 __le16 rl_multiply; 983 __le16 wake_up_calc; 984 __le16 rl_encode; 985 }; 986 987 /* Query Scheduler Resource Allocation (indirect 0x0412) 988 * This indirect command retrieves the scheduler resources allocated by 989 * EMP Firmware to the given PF. 990 */ 991 struct ice_aqc_query_txsched_res { 992 u8 reserved[8]; 993 __le32 addr_high; 994 __le32 addr_low; 995 }; 996 997 struct ice_aqc_generic_sched_props { 998 __le16 phys_levels; 999 __le16 logical_levels; 1000 u8 flattening_bitmap; 1001 u8 max_device_cgds; 1002 u8 max_pf_cgds; 1003 u8 rsvd0; 1004 __le16 rdma_qsets; 1005 u8 rsvd1[22]; 1006 }; 1007 1008 struct ice_aqc_layer_props { 1009 u8 logical_layer; 1010 u8 chunk_size; 1011 __le16 max_device_nodes; 1012 __le16 max_pf_nodes; 1013 u8 rsvd0[4]; 1014 __le16 max_sibl_grp_sz; 1015 __le16 max_cir_rl_profiles; 1016 __le16 max_eir_rl_profiles; 1017 __le16 max_srl_profiles; 1018 u8 rsvd1[14]; 1019 }; 1020 1021 struct ice_aqc_query_txsched_res_resp { 1022 struct ice_aqc_generic_sched_props sched_props; 1023 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1024 }; 1025 1026 /* Get PHY capabilities (indirect 0x0600) */ 1027 struct ice_aqc_get_phy_caps { 1028 u8 lport_num; 1029 u8 reserved; 1030 __le16 param0; 1031 /* 18.0 - Report qualified modules */ 1032 #define ICE_AQC_GET_PHY_RQM BIT(0) 1033 /* 18.1 - 18.3 : Report mode 1034 * 000b - Report NVM capabilities 1035 * 001b - Report topology capabilities 1036 * 010b - Report SW configured 1037 * 100b - Report default capabilities 1038 */ 1039 #define ICE_AQC_REPORT_MODE_S 1 1040 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1041 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1042 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1043 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1044 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1045 __le32 reserved1; 1046 __le32 addr_high; 1047 __le32 addr_low; 1048 }; 1049 1050 /* This is #define of PHY type (Extended): 1051 * The first set of defines is for phy_type_low. 1052 */ 1053 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1054 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1055 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1056 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1057 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1058 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1059 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1060 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1061 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1062 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1063 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1064 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1065 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1066 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1067 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1068 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1069 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1070 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1071 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1072 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1073 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1074 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1075 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1076 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1077 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1078 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1079 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1080 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1081 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1082 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1083 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1084 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1085 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1086 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1087 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1088 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1089 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1090 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1091 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1092 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1093 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1094 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1095 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1096 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1097 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1098 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1099 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1100 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1101 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1102 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1103 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1104 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1105 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1106 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1107 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1108 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1109 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1110 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1111 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1112 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1113 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1114 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1115 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1116 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1117 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1118 /* The second set of defines is for phy_type_high. */ 1119 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1120 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1121 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1122 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1123 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1124 #define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) 1125 #define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) 1126 #define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) 1127 #define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) 1128 #define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) 1129 #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) 1130 #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) 1131 #define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) 1132 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 12 1133 1134 struct ice_aqc_get_phy_caps_data { 1135 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1136 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1137 u8 caps; 1138 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1139 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1140 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1141 #define ICE_AQC_PHY_EN_LINK BIT(3) 1142 #define ICE_AQC_PHY_AN_MODE BIT(4) 1143 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 1144 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1145 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 1146 u8 low_power_ctrl_an; 1147 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1148 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1149 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1150 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1151 __le16 eee_cap; 1152 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1153 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1154 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1155 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1156 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1157 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1158 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1159 __le16 eeer_value; 1160 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1161 u8 phy_fw_ver[8]; 1162 u8 link_fec_options; 1163 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1164 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1165 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1166 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1167 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1168 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1169 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1170 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1171 u8 module_compliance_enforcement; 1172 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1173 u8 extended_compliance_code; 1174 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1175 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1176 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1177 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1178 #define ICE_AQC_MOD_TYPE_IDENT 1 1179 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1180 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1181 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1182 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1183 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1184 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1185 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1186 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1187 u8 qualified_module_count; 1188 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1189 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1190 struct { 1191 u8 v_oui[3]; 1192 u8 rsvd3; 1193 u8 v_part[16]; 1194 __le32 v_rev; 1195 __le64 rsvd4; 1196 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1197 }; 1198 1199 /* Set PHY capabilities (direct 0x0601) 1200 * NOTE: This command must be followed by setup link and restart auto-neg 1201 */ 1202 struct ice_aqc_set_phy_cfg { 1203 u8 lport_num; 1204 u8 reserved[7]; 1205 __le32 addr_high; 1206 __le32 addr_low; 1207 }; 1208 1209 /* Set PHY config command data structure */ 1210 struct ice_aqc_set_phy_cfg_data { 1211 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1212 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1213 u8 caps; 1214 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1215 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1216 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1217 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1218 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1219 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1220 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1221 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1222 u8 low_power_ctrl_an; 1223 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1224 __le16 eeer_value; 1225 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1226 u8 module_compliance_enforcement; 1227 }; 1228 1229 /* Set MAC Config command data structure (direct 0x0603) */ 1230 struct ice_aqc_set_mac_cfg { 1231 __le16 max_frame_size; 1232 u8 params; 1233 #define ICE_AQ_SET_MAC_PACE_S 3 1234 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1235 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1236 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1237 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1238 u8 tx_tmr_priority; 1239 __le16 tx_tmr_value; 1240 __le16 fc_refresh_threshold; 1241 u8 drop_opts; 1242 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1243 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1244 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1245 u8 reserved[7]; 1246 }; 1247 1248 /* Restart AN command data structure (direct 0x0605) 1249 * Also used for response, with only the lport_num field present. 1250 */ 1251 struct ice_aqc_restart_an { 1252 u8 lport_num; 1253 u8 reserved; 1254 u8 cmd_flags; 1255 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1256 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1257 u8 reserved2[13]; 1258 }; 1259 1260 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1261 struct ice_aqc_get_link_status { 1262 u8 lport_num; 1263 u8 reserved; 1264 __le16 cmd_flags; 1265 #define ICE_AQ_LSE_M 0x3 1266 #define ICE_AQ_LSE_NOP 0x0 1267 #define ICE_AQ_LSE_DIS 0x2 1268 #define ICE_AQ_LSE_ENA 0x3 1269 /* only response uses this flag */ 1270 #define ICE_AQ_LSE_IS_ENABLED 0x1 1271 __le32 reserved2; 1272 __le32 addr_high; 1273 __le32 addr_low; 1274 }; 1275 1276 /* Get link status response data structure, also used for Link Status Event */ 1277 struct ice_aqc_get_link_status_data { 1278 u8 topo_media_conflict; 1279 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1280 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1281 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1282 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1283 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1284 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1285 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1286 u8 link_cfg_err; 1287 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1288 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1289 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1290 u8 link_info; 1291 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1292 #define ICE_AQ_LINK_FAULT BIT(1) 1293 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1294 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1295 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1296 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1297 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1298 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1299 u8 an_info; 1300 #define ICE_AQ_AN_COMPLETED BIT(0) 1301 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1302 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1303 #define ICE_AQ_FEC_EN BIT(3) 1304 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1305 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1306 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1307 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1308 u8 ext_info; 1309 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1310 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1311 /* Port Tx Suspended */ 1312 #define ICE_AQ_LINK_TX_S 2 1313 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1314 #define ICE_AQ_LINK_TX_ACTIVE 0 1315 #define ICE_AQ_LINK_TX_DRAINED 1 1316 #define ICE_AQ_LINK_TX_FLUSHED 3 1317 u8 reserved2; 1318 __le16 max_frame_size; 1319 u8 cfg; 1320 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1321 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1322 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1323 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1324 /* Pacing Config */ 1325 #define ICE_AQ_CFG_PACING_S 3 1326 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1327 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1328 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1329 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1330 /* External Device Power Ability */ 1331 u8 power_desc; 1332 #define ICE_AQ_PWR_CLASS_M 0x3F 1333 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1334 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1335 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1336 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1337 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1338 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1339 __le16 link_speed; 1340 #define ICE_AQ_LINK_SPEED_M 0x7FF 1341 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1342 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1343 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1344 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1345 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1346 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1347 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1348 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1349 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1350 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1351 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1352 #define ICE_AQ_LINK_SPEED_200GB BIT(11) 1353 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1354 /* Aligns next field to 8-byte boundary */ 1355 __le16 reserved3; 1356 u8 ext_fec_status; 1357 /* RS 272 FEC enabled */ 1358 #define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) 1359 u8 reserved4; 1360 /* Use values from ICE_PHY_TYPE_LOW_* */ 1361 __le64 phy_type_low; 1362 /* Use values from ICE_PHY_TYPE_HIGH_* */ 1363 __le64 phy_type_high; 1364 #define ICE_AQC_LS_DATA_SIZE_V1 \ 1365 offsetofend(struct ice_aqc_get_link_status_data, phy_type_high) 1366 /* Get link status v2 link partner data */ 1367 __le64 lp_phy_type_low; 1368 __le64 lp_phy_type_high; 1369 u8 lp_fec_adv; 1370 #define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0) 1371 #define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1) 1372 #define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2) 1373 #define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 1374 #define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 1375 #define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 1376 u8 lp_fec_req; 1377 #define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0) 1378 #define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1) 1379 #define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2) 1380 #define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3) 1381 u8 lp_flowcontrol; 1382 #define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0) 1383 #define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1) 1384 u8 reserved5[5]; 1385 #define ICE_AQC_LS_DATA_SIZE_V2 \ 1386 offsetofend(struct ice_aqc_get_link_status_data, reserved5) 1387 } __packed; 1388 1389 /* Set event mask command (direct 0x0613) */ 1390 struct ice_aqc_set_event_mask { 1391 u8 lport_num; 1392 u8 reserved[7]; 1393 __le16 event_mask; 1394 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1395 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1396 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1397 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1398 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1399 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1400 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1401 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1402 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1403 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1404 u8 reserved1[6]; 1405 }; 1406 1407 /* Set MAC Loopback command (direct 0x0620) */ 1408 struct ice_aqc_set_mac_lb { 1409 u8 lb_mode; 1410 #define ICE_AQ_MAC_LB_EN BIT(0) 1411 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1412 u8 reserved[15]; 1413 }; 1414 1415 /* Set PHY recovered clock output (direct 0x0630) */ 1416 struct ice_aqc_set_phy_rec_clk_out { 1417 u8 phy_output; 1418 u8 port_num; 1419 #define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1420 u8 flags; 1421 #define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1422 u8 rsvd; 1423 __le32 freq; 1424 u8 rsvd2[6]; 1425 __le16 node_handle; 1426 }; 1427 1428 /* Get PHY recovered clock output (direct 0x0631) */ 1429 struct ice_aqc_get_phy_rec_clk_out { 1430 u8 phy_output; 1431 u8 port_num; 1432 #define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1433 u8 flags; 1434 #define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1435 u8 rsvd[11]; 1436 __le16 node_handle; 1437 }; 1438 1439 /* Get sensor reading (direct 0x0632) */ 1440 struct ice_aqc_get_sensor_reading { 1441 u8 sensor; 1442 u8 format; 1443 u8 reserved[6]; 1444 __le32 addr_high; 1445 __le32 addr_low; 1446 }; 1447 1448 /* Get sensor reading response (direct 0x0632) */ 1449 struct ice_aqc_get_sensor_reading_resp { 1450 union { 1451 u8 raw[8]; 1452 /* Output data for sensor 0x00, format 0x00 */ 1453 struct _packed { 1454 s8 temp; 1455 u8 temp_warning_threshold; 1456 u8 temp_critical_threshold; 1457 u8 temp_fatal_threshold; 1458 u8 reserved[4]; 1459 } s0f0; 1460 } data; 1461 }; 1462 1463 struct ice_aqc_link_topo_params { 1464 u8 lport_num; 1465 u8 lport_num_valid; 1466 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1467 u8 node_type_ctx; 1468 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1469 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1470 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1471 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1472 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1473 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1474 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1475 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1476 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1477 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1478 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1479 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 9 1480 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 10 1481 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS 11 1482 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1483 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1484 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1485 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1486 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1487 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1488 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1489 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1490 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1491 u8 index; 1492 }; 1493 1494 struct ice_aqc_link_topo_addr { 1495 struct ice_aqc_link_topo_params topo_params; 1496 __le16 handle; 1497 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1498 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1499 /* Used to decode the handle field */ 1500 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1501 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1502 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1503 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1504 /* In case of a Mezzanine type */ 1505 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1506 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1507 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1508 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1509 /* In case of a LOM type */ 1510 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1511 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1512 }; 1513 1514 /* Get Link Topology Handle (direct, 0x06E0) */ 1515 struct ice_aqc_get_link_topo { 1516 struct ice_aqc_link_topo_addr addr; 1517 u8 node_part_num; 1518 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1519 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 1520 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25 1521 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30 1522 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31 1523 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 1524 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 1525 u8 rsvd[9]; 1526 }; 1527 1528 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1529 struct ice_aqc_i2c { 1530 struct ice_aqc_link_topo_addr topo_addr; 1531 __le16 i2c_addr; 1532 u8 i2c_params; 1533 #define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0) 1534 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1535 1536 u8 rsvd; 1537 __le16 i2c_bus_addr; 1538 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1539 }; 1540 1541 /* Read I2C Response (direct, 0x06E2) */ 1542 struct ice_aqc_read_i2c_resp { 1543 u8 i2c_data[16]; 1544 }; 1545 1546 /* Set Port Identification LED (direct, 0x06E9) */ 1547 struct ice_aqc_set_port_id_led { 1548 u8 lport_num; 1549 u8 lport_num_valid; 1550 u8 ident_mode; 1551 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1552 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1553 u8 rsvd[13]; 1554 }; 1555 1556 /* Get Port Options (indirect, 0x06EA) */ 1557 struct ice_aqc_get_port_options { 1558 u8 lport_num; 1559 u8 lport_num_valid; 1560 u8 port_options_count; 1561 #define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0) 1562 #define ICE_AQC_PORT_OPT_MAX 16 1563 1564 u8 innermost_phy_index; 1565 u8 port_options; 1566 #define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0) 1567 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1568 1569 u8 pending_port_option_status; 1570 #define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0) 1571 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 1572 1573 u8 rsvd[2]; 1574 __le32 addr_high; 1575 __le32 addr_low; 1576 }; 1577 1578 struct ice_aqc_get_port_options_elem { 1579 u8 pmd; 1580 #define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0) 1581 1582 u8 max_lane_speed; 1583 #define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0) 1584 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1585 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1586 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1587 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1588 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1589 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1590 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1591 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1592 1593 u8 global_scid[2]; 1594 u8 phy_scid[2]; 1595 u8 pf2port_cid[2]; 1596 }; 1597 1598 /* Set Port Option (direct, 0x06EB) */ 1599 struct ice_aqc_set_port_option { 1600 u8 lport_num; 1601 u8 lport_num_valid; 1602 u8 selected_port_option; 1603 u8 rsvd[13]; 1604 }; 1605 1606 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1607 struct ice_aqc_gpio { 1608 __le16 gpio_ctrl_handle; 1609 #define ICE_AQC_GPIO_HANDLE_S 0 1610 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1611 u8 gpio_num; 1612 u8 gpio_val; 1613 u8 rsvd[12]; 1614 }; 1615 1616 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1617 struct ice_aqc_sff_eeprom { 1618 u8 lport_num; 1619 u8 lport_num_valid; 1620 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1621 __le16 i2c_bus_addr; 1622 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1623 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1624 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1625 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1626 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1627 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1628 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1629 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1630 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1631 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1632 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1633 __le16 i2c_mem_addr; 1634 __le16 eeprom_page; 1635 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1636 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1637 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1638 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1639 __le32 addr_high; 1640 __le32 addr_low; 1641 }; 1642 1643 /* NVM Read command (indirect 0x0701) 1644 * NVM Erase commands (direct 0x0702) 1645 * NVM Update commands (indirect 0x0703) 1646 */ 1647 struct ice_aqc_nvm { 1648 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1649 __le16 offset_low; 1650 u8 offset_high; 1651 u8 cmd_flags; 1652 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1653 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1654 #define ICE_AQC_NVM_PRESERVATION_S 1 1655 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1656 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1657 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1658 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1659 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1660 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1661 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1662 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1663 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1664 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1665 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1666 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1667 #define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */ 1668 #define ICE_AQC_NVM_POR_FLAG 0 1669 #define ICE_AQC_NVM_PERST_FLAG 1 1670 #define ICE_AQC_NVM_EMPR_FLAG 2 1671 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 1672 /* For Write Activate, several flags are sent as part of a separate 1673 * flags2 field using a separate byte. For simplicity of the software 1674 * interface, we pass the flags as a 16 bit value so these flags are 1675 * all offset by 8 bits 1676 */ 1677 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 1678 __le16 module_typeid; 1679 __le16 length; 1680 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1681 __le32 addr_high; 1682 __le32 addr_low; 1683 }; 1684 1685 #define ICE_AQC_NVM_START_POINT 0 1686 1687 #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B 1688 1689 struct ice_aqc_nvm_tx_topo_user_sel { 1690 __le16 length; 1691 u8 data; 1692 #define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4) 1693 u8 reserved; 1694 }; 1695 1696 /* NVM Checksum Command (direct, 0x0706) */ 1697 struct ice_aqc_nvm_checksum { 1698 u8 flags; 1699 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1700 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1701 u8 rsvd; 1702 __le16 checksum; /* Used only by response */ 1703 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1704 u8 rsvd2[12]; 1705 }; 1706 1707 /* Used for NVM Set Package Data command - 0x070A */ 1708 struct ice_aqc_nvm_pkg_data { 1709 u8 reserved[3]; 1710 u8 cmd_flags; 1711 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1712 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1713 1714 u32 reserved1; 1715 __le32 addr_high; 1716 __le32 addr_low; 1717 }; 1718 1719 /* Used for Pass Component Table command - 0x070B */ 1720 struct ice_aqc_nvm_pass_comp_tbl { 1721 u8 component_response; /* Response only */ 1722 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1723 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1724 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1725 u8 component_response_code; /* Response only */ 1726 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1727 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1728 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1729 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1730 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1731 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1732 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1733 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1734 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1735 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1736 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1737 u8 reserved; 1738 u8 transfer_flag; 1739 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1740 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1741 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1742 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1743 __le32 reserved1; 1744 __le32 addr_high; 1745 __le32 addr_low; 1746 }; 1747 1748 struct ice_aqc_nvm_comp_tbl { 1749 __le16 comp_class; 1750 #define NVM_COMP_CLASS_ALL_FW 0x000A 1751 1752 __le16 comp_id; 1753 #define NVM_COMP_ID_OROM 0x5 1754 #define NVM_COMP_ID_NVM 0x6 1755 #define NVM_COMP_ID_NETLIST 0x8 1756 1757 u8 comp_class_idx; 1758 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1759 1760 __le32 comp_cmp_stamp; 1761 u8 cvs_type; 1762 #define NVM_CVS_TYPE_ASCII 0x1 1763 1764 u8 cvs_len; 1765 u8 cvs[]; /* Component Version String */ 1766 } __packed; 1767 1768 /* Send to PF command (indirect 0x0801) ID is only used by PF 1769 * 1770 * Send to VF command (indirect 0x0802) ID is only used by PF 1771 * 1772 */ 1773 struct ice_aqc_pf_vf_msg { 1774 __le32 id; 1775 u32 reserved; 1776 __le32 addr_high; 1777 __le32 addr_low; 1778 }; 1779 1780 /* Get LLDP MIB (indirect 0x0A00) 1781 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1782 * as the format is the same. 1783 */ 1784 struct ice_aqc_lldp_get_mib { 1785 u8 type; 1786 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1787 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1788 #define ICE_AQ_LLDP_MIB_LOCAL 0 1789 #define ICE_AQ_LLDP_MIB_REMOTE 1 1790 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1791 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1792 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1793 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1794 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1795 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1796 #define ICE_AQ_LLDP_TX_S 0x4 1797 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1798 #define ICE_AQ_LLDP_TX_ACTIVE 0 1799 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1800 #define ICE_AQ_LLDP_TX_FLUSHED 3 1801 /* DCBX mode */ 1802 #define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6) 1803 #define ICE_AQ_LLDP_DCBX_NA 0 1804 #define ICE_AQ_LLDP_DCBX_CEE 1 1805 #define ICE_AQ_LLDP_DCBX_IEEE 2 1806 1807 u8 state; 1808 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M BIT(0) 1809 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 1810 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 1811 1812 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1813 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1814 * Get LLDP MIB (0x0A00) response only. 1815 */ 1816 __le16 local_len; 1817 __le16 remote_len; 1818 u8 reserved[2]; 1819 __le32 addr_high; 1820 __le32 addr_low; 1821 }; 1822 1823 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1824 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1825 struct ice_aqc_lldp_set_mib_change { 1826 u8 command; 1827 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1828 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1829 #define ICE_AQ_LLDP_MIB_PENDING_M BIT(1) 1830 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 1831 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 1832 u8 reserved[15]; 1833 }; 1834 1835 /* Stop LLDP (direct 0x0A05) */ 1836 struct ice_aqc_lldp_stop { 1837 u8 command; 1838 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1839 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1840 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1841 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1842 u8 reserved[15]; 1843 }; 1844 1845 /* Start LLDP (direct 0x0A06) */ 1846 struct ice_aqc_lldp_start { 1847 u8 command; 1848 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1849 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1850 u8 reserved[15]; 1851 }; 1852 1853 /* Get CEE DCBX Oper Config (0x0A07) 1854 * The command uses the generic descriptor struct and 1855 * returns the struct below as an indirect response. 1856 */ 1857 struct ice_aqc_get_cee_dcb_cfg_resp { 1858 u8 oper_num_tc; 1859 u8 oper_prio_tc[4]; 1860 u8 oper_tc_bw[8]; 1861 u8 oper_pfc_en; 1862 __le16 oper_app_prio; 1863 #define ICE_AQC_CEE_APP_FCOE_S 0 1864 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1865 #define ICE_AQC_CEE_APP_ISCSI_S 3 1866 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1867 #define ICE_AQC_CEE_APP_FIP_S 8 1868 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1869 __le32 tlv_status; 1870 #define ICE_AQC_CEE_PG_STATUS_S 0 1871 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1872 #define ICE_AQC_CEE_PFC_STATUS_S 3 1873 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1874 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1875 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1876 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1877 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1878 #define ICE_AQC_CEE_FIP_STATUS_S 16 1879 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1880 u8 reserved[12]; 1881 }; 1882 1883 /* Set Local LLDP MIB (indirect 0x0A08) 1884 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1885 */ 1886 struct ice_aqc_lldp_set_local_mib { 1887 u8 type; 1888 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1889 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1890 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1891 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1892 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1893 u8 reserved0; 1894 __le16 length; 1895 u8 reserved1[4]; 1896 __le32 addr_high; 1897 __le32 addr_low; 1898 }; 1899 1900 /* Stop/Start LLDP Agent (direct 0x0A09) 1901 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1902 * The same structure is used for the response, with the command field 1903 * being used as the status field. 1904 */ 1905 struct ice_aqc_lldp_stop_start_specific_agent { 1906 u8 command; 1907 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1908 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1909 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1910 u8 reserved[15]; 1911 }; 1912 1913 /* LLDP Filter Control (direct 0x0A0A) */ 1914 struct ice_aqc_lldp_filter_ctrl { 1915 u8 cmd_flags; 1916 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1917 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1918 u8 reserved1; 1919 __le16 vsi_num; 1920 u8 reserved2[12]; 1921 }; 1922 1923 #define ICE_AQC_RSS_VSI_VALID BIT(15) 1924 1925 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1926 struct ice_aqc_get_set_rss_key { 1927 __le16 vsi_id; 1928 u8 reserved[6]; 1929 __le32 addr_high; 1930 __le32 addr_low; 1931 }; 1932 1933 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1934 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1935 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1936 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1937 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1938 1939 struct ice_aqc_get_set_rss_keys { 1940 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1941 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1942 }; 1943 1944 enum ice_lut_type { 1945 ICE_LUT_VSI = 0, 1946 ICE_LUT_PF = 1, 1947 ICE_LUT_GLOBAL = 2, 1948 }; 1949 1950 enum ice_lut_size { 1951 ICE_LUT_VSI_SIZE = 64, 1952 ICE_LUT_GLOBAL_SIZE = 512, 1953 ICE_LUT_PF_SIZE = 2048, 1954 }; 1955 1956 /* enum ice_aqc_lut_flags combines constants used to fill 1957 * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID, 1958 * LUT size and LUT type, last of which does not need neither shift nor mask. 1959 */ 1960 enum ice_aqc_lut_flags { 1961 ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */ 1962 ICE_AQC_LUT_SIZE_512 = BIT(2), 1963 ICE_AQC_LUT_SIZE_2K = BIT(3), 1964 1965 ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4), 1966 }; 1967 1968 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1969 struct ice_aqc_get_set_rss_lut { 1970 __le16 vsi_id; 1971 __le16 flags; 1972 __le32 reserved; 1973 __le32 addr_high; 1974 __le32 addr_low; 1975 }; 1976 1977 /* Sideband Control Interface Commands */ 1978 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 1979 struct ice_aqc_neigh_dev_req { 1980 __le16 sb_data_len; 1981 u8 reserved[6]; 1982 __le32 addr_high; 1983 __le32 addr_low; 1984 }; 1985 1986 /* Add Tx LAN Queues (indirect 0x0C30) */ 1987 struct ice_aqc_add_txqs { 1988 u8 num_qgrps; 1989 u8 reserved[3]; 1990 __le32 reserved1; 1991 __le32 addr_high; 1992 __le32 addr_low; 1993 }; 1994 1995 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1996 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1997 */ 1998 struct ice_aqc_add_txqs_perq { 1999 __le16 txq_id; 2000 u8 rsvd[2]; 2001 __le32 q_teid; 2002 u8 txq_ctx[22]; 2003 u8 rsvd2[2]; 2004 struct ice_aqc_txsched_elem info; 2005 }; 2006 2007 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2008 * is an array of the following structs. Please note that the length of 2009 * each struct ice_aqc_add_tx_qgrp is variable due 2010 * to the variable number of queues in each group! 2011 */ 2012 struct ice_aqc_add_tx_qgrp { 2013 __le32 parent_teid; 2014 u8 num_txqs; 2015 u8 rsvd[3]; 2016 struct ice_aqc_add_txqs_perq txqs[]; 2017 }; 2018 2019 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2020 struct ice_aqc_dis_txqs { 2021 u8 cmd_type; 2022 #define ICE_AQC_Q_DIS_CMD_S 0 2023 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2024 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2025 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2026 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2027 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2028 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2029 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2030 u8 num_entries; 2031 __le16 vmvf_and_timeout; 2032 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2033 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2034 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2035 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2036 __le32 blocked_cgds; 2037 __le32 addr_high; 2038 __le32 addr_low; 2039 }; 2040 2041 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2042 * contains the following structures, arrayed one after the 2043 * other. 2044 * Note: Since the q_id is 16 bits wide, if the 2045 * number of queues is even, then 2 bytes of alignment MUST be 2046 * added before the start of the next group, to allow correct 2047 * alignment of the parent_teid field. 2048 */ 2049 struct ice_aqc_dis_txq_item { 2050 __le32 parent_teid; 2051 u8 num_qs; 2052 u8 rsvd; 2053 /* The length of the q_id array varies according to num_qs */ 2054 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2055 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2056 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2057 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2058 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2059 __le16 q_id[]; 2060 } __packed; 2061 2062 /* Move/Reconfigure Tx queue (indirect 0x0C32) */ 2063 struct ice_aqc_cfg_txqs { 2064 u8 cmd_type; 2065 #define ICE_AQC_Q_CFG_MOVE_NODE 0x1 2066 #define ICE_AQC_Q_CFG_TC_CHNG 0x2 2067 #define ICE_AQC_Q_CFG_MOVE_TC_CHNG 0x3 2068 #define ICE_AQC_Q_CFG_SUBSEQ_CALL BIT(2) 2069 #define ICE_AQC_Q_CFG_FLUSH BIT(3) 2070 u8 num_qs; 2071 u8 port_num_chng; 2072 #define ICE_AQC_Q_CFG_SRC_PRT_M 0x7 2073 #define ICE_AQC_Q_CFG_DST_PRT_S 3 2074 #define ICE_AQC_Q_CFG_DST_PRT_M (0x7 << ICE_AQC_Q_CFG_DST_PRT_S) 2075 u8 time_out; 2076 #define ICE_AQC_Q_CFG_TIMEOUT_S 2 2077 #define ICE_AQC_Q_CFG_TIMEOUT_M (0x1F << ICE_AQC_Q_CFG_TIMEOUT_S) 2078 __le32 blocked_cgds; 2079 __le32 addr_high; 2080 __le32 addr_low; 2081 }; 2082 2083 /* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2084 struct ice_aqc_cfg_txq_perq { 2085 __le16 q_handle; 2086 u8 tc; 2087 u8 rsvd; 2088 __le32 q_teid; 2089 }; 2090 2091 /* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2092 struct ice_aqc_cfg_txqs_buf { 2093 __le32 src_parent_teid; 2094 __le32 dst_parent_teid; 2095 struct ice_aqc_cfg_txq_perq queue_info[]; 2096 }; 2097 2098 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 2099 struct ice_aqc_add_rdma_qset { 2100 u8 num_qset_grps; 2101 u8 reserved[7]; 2102 __le32 addr_high; 2103 __le32 addr_low; 2104 }; 2105 2106 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 2107 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 2108 */ 2109 struct ice_aqc_add_tx_rdma_qset_entry { 2110 __le16 tx_qset_id; 2111 u8 rsvd[2]; 2112 __le32 qset_teid; 2113 struct ice_aqc_txsched_elem info; 2114 }; 2115 2116 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 2117 * is an array of the following structs. Please note that the length of 2118 * each struct ice_aqc_add_rdma_qset is variable due to the variable 2119 * number of queues in each group! 2120 */ 2121 struct ice_aqc_add_rdma_qset_data { 2122 __le32 parent_teid; 2123 __le16 num_qsets; 2124 u8 rsvd[2]; 2125 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 2126 }; 2127 2128 /* Download Package (indirect 0x0C40) */ 2129 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ 2130 struct ice_aqc_download_pkg { 2131 u8 flags; 2132 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2133 u8 reserved[3]; 2134 __le32 reserved1; 2135 __le32 addr_high; 2136 __le32 addr_low; 2137 }; 2138 2139 struct ice_aqc_download_pkg_resp { 2140 __le32 error_offset; 2141 __le32 error_info; 2142 __le32 addr_high; 2143 __le32 addr_low; 2144 }; 2145 2146 /* Get Package Info List (indirect 0x0C43) */ 2147 struct ice_aqc_get_pkg_info_list { 2148 __le32 reserved1; 2149 __le32 reserved2; 2150 __le32 addr_high; 2151 __le32 addr_low; 2152 }; 2153 2154 /* Version format for packages */ 2155 struct ice_pkg_ver { 2156 u8 major; 2157 u8 minor; 2158 u8 update; 2159 u8 draft; 2160 }; 2161 2162 #define ICE_PKG_NAME_SIZE 32 2163 #define ICE_SEG_ID_SIZE 28 2164 #define ICE_SEG_NAME_SIZE 28 2165 2166 struct ice_aqc_get_pkg_info { 2167 struct ice_pkg_ver ver; 2168 char name[ICE_SEG_NAME_SIZE]; 2169 __le32 track_id; 2170 u8 is_in_nvm; 2171 u8 is_active; 2172 u8 is_active_at_boot; 2173 u8 is_modified; 2174 }; 2175 2176 /* Get Package Info List response buffer format (0x0C43) */ 2177 struct ice_aqc_get_pkg_info_resp { 2178 __le32 count; 2179 struct ice_aqc_get_pkg_info pkg_info[]; 2180 }; 2181 2182 /* Get CGU abilities command response data structure (indirect 0x0C61) */ 2183 struct ice_aqc_get_cgu_abilities { 2184 u8 num_inputs; 2185 u8 num_outputs; 2186 u8 pps_dpll_idx; 2187 u8 eec_dpll_idx; 2188 __le32 max_in_freq; 2189 __le32 max_in_phase_adj; 2190 __le32 max_out_freq; 2191 __le32 max_out_phase_adj; 2192 u8 cgu_part_num; 2193 u8 rsvd[3]; 2194 }; 2195 2196 /* Set CGU input config (direct 0x0C62) */ 2197 struct ice_aqc_set_cgu_input_config { 2198 u8 input_idx; 2199 u8 flags1; 2200 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6) 2201 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7) 2202 u8 flags2; 2203 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2204 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2205 u8 rsvd; 2206 __le32 freq; 2207 __le32 phase_delay; 2208 u8 rsvd2[2]; 2209 __le16 node_handle; 2210 }; 2211 2212 /* Get CGU input config response descriptor structure (direct 0x0C63) */ 2213 struct ice_aqc_get_cgu_input_config { 2214 u8 input_idx; 2215 u8 status; 2216 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS BIT(0) 2217 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1) 2218 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2) 2219 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3) 2220 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4) 2221 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6) 2222 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7) 2223 u8 type; 2224 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0) 2225 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS BIT(4) 2226 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5) 2227 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY BIT(6) 2228 u8 flags1; 2229 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0) 2230 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2) 2231 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3) 2232 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7) 2233 __le32 freq; 2234 __le32 phase_delay; 2235 u8 flags2; 2236 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2237 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2238 u8 rsvd[1]; 2239 __le16 node_handle; 2240 }; 2241 2242 /* Set CGU output config (direct 0x0C64) */ 2243 struct ice_aqc_set_cgu_output_config { 2244 u8 output_idx; 2245 u8 flags; 2246 #define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN BIT(0) 2247 #define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2248 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2) 2249 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3) 2250 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4) 2251 u8 src_sel; 2252 #define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0) 2253 u8 rsvd; 2254 __le32 freq; 2255 __le32 phase_delay; 2256 u8 rsvd2[2]; 2257 __le16 node_handle; 2258 }; 2259 2260 /* Get CGU output config (direct 0x0C65) */ 2261 struct ice_aqc_get_cgu_output_config { 2262 u8 output_idx; 2263 u8 flags; 2264 #define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN BIT(0) 2265 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2266 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2) 2267 u8 src_sel; 2268 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0 2269 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \ 2270 ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT) 2271 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5 2272 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \ 2273 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT) 2274 u8 rsvd; 2275 __le32 freq; 2276 __le32 src_freq; 2277 u8 rsvd2[2]; 2278 __le16 node_handle; 2279 }; 2280 2281 /* Get CGU DPLL status (direct 0x0C66) */ 2282 struct ice_aqc_get_cgu_dpll_status { 2283 u8 dpll_num; 2284 u8 ref_state; 2285 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0) 2286 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1) 2287 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2) 2288 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3) 2289 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4) 2290 #define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5) 2291 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6) 2292 u8 dpll_state; 2293 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0) 2294 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO BIT(1) 2295 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2) 2296 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5) 2297 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7) 2298 u8 config; 2299 #define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2300 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2301 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE \ 2302 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2303 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2304 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2305 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2306 __le32 phase_offset_h; 2307 __le32 phase_offset_l; 2308 u8 eec_mode; 2309 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA 2310 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB 2311 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF 2312 u8 rsvd[1]; 2313 __le16 node_handle; 2314 }; 2315 2316 /* Set CGU DPLL config (direct 0x0C67) */ 2317 struct ice_aqc_set_cgu_dpll_config { 2318 u8 dpll_num; 2319 u8 ref_state; 2320 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0) 2321 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1) 2322 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2) 2323 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3) 2324 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4) 2325 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5) 2326 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6) 2327 u8 rsvd; 2328 u8 config; 2329 #define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2330 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2331 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE \ 2332 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2333 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2334 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2335 ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2336 u8 rsvd2[8]; 2337 u8 eec_mode; 2338 u8 rsvd3[1]; 2339 __le16 node_handle; 2340 }; 2341 2342 /* Set CGU reference priority (direct 0x0C68) */ 2343 struct ice_aqc_set_cgu_ref_prio { 2344 u8 dpll_num; 2345 u8 ref_idx; 2346 u8 ref_priority; 2347 u8 rsvd[11]; 2348 __le16 node_handle; 2349 }; 2350 2351 /* Get CGU reference priority (direct 0x0C69) */ 2352 struct ice_aqc_get_cgu_ref_prio { 2353 u8 dpll_num; 2354 u8 ref_idx; 2355 u8 ref_priority; /* Valid only in response */ 2356 u8 rsvd[13]; 2357 }; 2358 2359 /* Get CGU info (direct 0x0C6A) */ 2360 struct ice_aqc_get_cgu_info { 2361 __le32 cgu_id; 2362 __le32 cgu_cfg_ver; 2363 __le32 cgu_fw_ver; 2364 u8 node_part_num; 2365 u8 dev_rev; 2366 __le16 node_handle; 2367 }; 2368 2369 /* Driver Shared Parameters (direct, 0x0C90) */ 2370 struct ice_aqc_driver_shared_params { 2371 u8 set_or_get_op; 2372 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2373 #define ICE_AQC_DRIVER_PARAM_SET 0 2374 #define ICE_AQC_DRIVER_PARAM_GET 1 2375 u8 param_indx; 2376 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2377 u8 rsvd[2]; 2378 __le32 param_val; 2379 __le32 addr_high; 2380 __le32 addr_low; 2381 }; 2382 2383 /* Lan Queue Overflow Event (direct, 0x1001) */ 2384 struct ice_aqc_event_lan_overflow { 2385 __le32 prtdcb_ruptq; 2386 __le32 qtx_ctl; 2387 u8 reserved[8]; 2388 }; 2389 2390 enum ice_aqc_fw_logging_mod { 2391 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2392 ICE_AQC_FW_LOG_ID_CTRL, 2393 ICE_AQC_FW_LOG_ID_LINK, 2394 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2395 ICE_AQC_FW_LOG_ID_DNL, 2396 ICE_AQC_FW_LOG_ID_I2C, 2397 ICE_AQC_FW_LOG_ID_SDP, 2398 ICE_AQC_FW_LOG_ID_MDIO, 2399 ICE_AQC_FW_LOG_ID_ADMINQ, 2400 ICE_AQC_FW_LOG_ID_HDMA, 2401 ICE_AQC_FW_LOG_ID_LLDP, 2402 ICE_AQC_FW_LOG_ID_DCBX, 2403 ICE_AQC_FW_LOG_ID_DCB, 2404 ICE_AQC_FW_LOG_ID_XLR, 2405 ICE_AQC_FW_LOG_ID_NVM, 2406 ICE_AQC_FW_LOG_ID_AUTH, 2407 ICE_AQC_FW_LOG_ID_VPD, 2408 ICE_AQC_FW_LOG_ID_IOSF, 2409 ICE_AQC_FW_LOG_ID_PARSER, 2410 ICE_AQC_FW_LOG_ID_SW, 2411 ICE_AQC_FW_LOG_ID_SCHEDULER, 2412 ICE_AQC_FW_LOG_ID_TXQ, 2413 ICE_AQC_FW_LOG_ID_RSVD, 2414 ICE_AQC_FW_LOG_ID_POST, 2415 ICE_AQC_FW_LOG_ID_WATCHDOG, 2416 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 2417 ICE_AQC_FW_LOG_ID_MNG, 2418 ICE_AQC_FW_LOG_ID_SYNCE, 2419 ICE_AQC_FW_LOG_ID_HEALTH, 2420 ICE_AQC_FW_LOG_ID_TSDRV, 2421 ICE_AQC_FW_LOG_ID_PFREG, 2422 ICE_AQC_FW_LOG_ID_MDLVER, 2423 ICE_AQC_FW_LOG_ID_MAX, 2424 }; 2425 2426 /* Set FW Logging configuration (indirect 0xFF30) 2427 * Register for FW Logging (indirect 0xFF31) 2428 * Query FW Logging (indirect 0xFF32) 2429 * FW Log Event (indirect 0xFF33) 2430 */ 2431 struct ice_aqc_fw_log { 2432 u8 cmd_flags; 2433 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 2434 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 2435 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2) 2436 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 2437 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 2438 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 2439 2440 u8 rsp_flag; 2441 __le16 fw_rt_msb; 2442 union { 2443 struct { 2444 __le32 fw_rt_lsb; 2445 } sync; 2446 struct { 2447 __le16 log_resolution; 2448 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 2449 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 2450 2451 __le16 mdl_cnt; 2452 } cfg; 2453 } ops; 2454 __le32 addr_high; 2455 __le32 addr_low; 2456 }; 2457 2458 /* Response Buffer for: 2459 * Set Firmware Logging Configuration (0xFF30) 2460 * Query FW Logging (0xFF32) 2461 */ 2462 struct ice_aqc_fw_log_cfg_resp { 2463 __le16 module_identifier; 2464 u8 log_level; 2465 u8 rsvd0; 2466 }; 2467 2468 /** 2469 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2470 * @flags: ICE_AQ_FLAG_* flags 2471 * @opcode: AQ command opcode 2472 * @datalen: length in bytes of indirect/external data buffer 2473 * @retval: return value from firmware 2474 * @cookie_high: opaque data high-half 2475 * @cookie_low: opaque data low-half 2476 * @params: command-specific parameters 2477 * 2478 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2479 * (ATQ). The firmware writes back onto the command descriptor and returns 2480 * the result of the command. Asynchronous events that are not an immediate 2481 * result of the command are written to the Admin Receive Queue (ARQ) using 2482 * the same descriptor format. Descriptors are in little-endian notation with 2483 * 32-bit words. 2484 */ 2485 struct ice_aq_desc { 2486 __le16 flags; 2487 __le16 opcode; 2488 __le16 datalen; 2489 __le16 retval; 2490 __le32 cookie_high; 2491 __le32 cookie_low; 2492 union { 2493 u8 raw[16]; 2494 struct ice_aqc_generic generic; 2495 struct ice_aqc_get_ver get_ver; 2496 struct ice_aqc_driver_ver driver_ver; 2497 struct ice_aqc_q_shutdown q_shutdown; 2498 struct ice_aqc_req_res res_owner; 2499 struct ice_aqc_manage_mac_read mac_read; 2500 struct ice_aqc_manage_mac_write mac_write; 2501 struct ice_aqc_clear_pxe clear_pxe; 2502 struct ice_aqc_list_caps get_cap; 2503 struct ice_aqc_get_phy_caps get_phy; 2504 struct ice_aqc_set_phy_cfg set_phy; 2505 struct ice_aqc_restart_an restart_an; 2506 struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out; 2507 struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out; 2508 struct ice_aqc_get_sensor_reading get_sensor_reading; 2509 struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp; 2510 struct ice_aqc_gpio read_write_gpio; 2511 struct ice_aqc_sff_eeprom read_write_sff_param; 2512 struct ice_aqc_set_port_id_led set_port_id_led; 2513 struct ice_aqc_get_port_options get_port_options; 2514 struct ice_aqc_set_port_option set_port_option; 2515 struct ice_aqc_get_sw_cfg get_sw_conf; 2516 struct ice_aqc_set_port_params set_port_params; 2517 struct ice_aqc_sw_rules sw_rules; 2518 struct ice_aqc_add_get_recipe add_get_recipe; 2519 struct ice_aqc_recipe_to_profile recipe_to_profile; 2520 struct ice_aqc_get_topo get_topo; 2521 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2522 struct ice_aqc_query_txsched_res query_sched_res; 2523 struct ice_aqc_query_port_ets port_ets; 2524 struct ice_aqc_rl_profile rl_profile; 2525 struct ice_aqc_nvm nvm; 2526 struct ice_aqc_nvm_checksum nvm_checksum; 2527 struct ice_aqc_nvm_pkg_data pkg_data; 2528 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl; 2529 struct ice_aqc_pf_vf_msg virt; 2530 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2531 struct ice_aqc_lldp_get_mib lldp_get_mib; 2532 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2533 struct ice_aqc_lldp_stop lldp_stop; 2534 struct ice_aqc_lldp_start lldp_start; 2535 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2536 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2537 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2538 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2539 struct ice_aqc_get_set_rss_key get_set_rss_key; 2540 struct ice_aqc_neigh_dev_req neigh_dev; 2541 struct ice_aqc_add_txqs add_txqs; 2542 struct ice_aqc_dis_txqs dis_txqs; 2543 struct ice_aqc_cfg_txqs cfg_txqs; 2544 struct ice_aqc_add_rdma_qset add_rdma_qset; 2545 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2546 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2547 struct ice_aqc_download_pkg download_pkg; 2548 struct ice_aqc_set_cgu_input_config set_cgu_input_config; 2549 struct ice_aqc_get_cgu_input_config get_cgu_input_config; 2550 struct ice_aqc_set_cgu_output_config set_cgu_output_config; 2551 struct ice_aqc_get_cgu_output_config get_cgu_output_config; 2552 struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status; 2553 struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config; 2554 struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio; 2555 struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio; 2556 struct ice_aqc_get_cgu_info get_cgu_info; 2557 struct ice_aqc_driver_shared_params drv_shared_params; 2558 struct ice_aqc_fw_log fw_log; 2559 struct ice_aqc_set_mac_lb set_mac_lb; 2560 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2561 struct ice_aqc_set_mac_cfg set_mac_cfg; 2562 struct ice_aqc_set_event_mask set_event_mask; 2563 struct ice_aqc_get_link_status get_link_status; 2564 struct ice_aqc_event_lan_overflow lan_overflow; 2565 struct ice_aqc_get_link_topo get_link_topo; 2566 struct ice_aqc_i2c read_write_i2c; 2567 struct ice_aqc_read_i2c_resp read_i2c_resp; 2568 struct ice_aqc_get_set_tx_topo get_set_tx_topo; 2569 } params; 2570 }; 2571 2572 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2573 #define ICE_AQ_LG_BUF 512 2574 2575 #define ICE_AQ_FLAG_ERR_S 2 2576 #define ICE_AQ_FLAG_LB_S 9 2577 #define ICE_AQ_FLAG_RD_S 10 2578 #define ICE_AQ_FLAG_BUF_S 12 2579 #define ICE_AQ_FLAG_SI_S 13 2580 2581 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2582 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2583 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2584 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2585 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2586 2587 /* error codes */ 2588 enum ice_aq_err { 2589 ICE_AQ_RC_OK = 0, /* Success */ 2590 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2591 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2592 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2593 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2594 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2595 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2596 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2597 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2598 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2599 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2600 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2601 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2602 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2603 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2604 }; 2605 2606 /* Admin Queue command opcodes */ 2607 enum ice_adminq_opc { 2608 /* AQ commands */ 2609 ice_aqc_opc_get_ver = 0x0001, 2610 ice_aqc_opc_driver_ver = 0x0002, 2611 ice_aqc_opc_q_shutdown = 0x0003, 2612 2613 /* resource ownership */ 2614 ice_aqc_opc_req_res = 0x0008, 2615 ice_aqc_opc_release_res = 0x0009, 2616 2617 /* device/function capabilities */ 2618 ice_aqc_opc_list_func_caps = 0x000A, 2619 ice_aqc_opc_list_dev_caps = 0x000B, 2620 2621 /* manage MAC address */ 2622 ice_aqc_opc_manage_mac_read = 0x0107, 2623 ice_aqc_opc_manage_mac_write = 0x0108, 2624 2625 /* PXE */ 2626 ice_aqc_opc_clear_pxe_mode = 0x0110, 2627 2628 /* internal switch commands */ 2629 ice_aqc_opc_get_sw_cfg = 0x0200, 2630 ice_aqc_opc_set_port_params = 0x0203, 2631 2632 /* Alloc/Free/Get Resources */ 2633 ice_aqc_opc_alloc_res = 0x0208, 2634 ice_aqc_opc_free_res = 0x0209, 2635 ice_aqc_opc_share_res = 0x020B, 2636 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 2637 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 2638 2639 /* VSI commands */ 2640 ice_aqc_opc_add_vsi = 0x0210, 2641 ice_aqc_opc_update_vsi = 0x0211, 2642 ice_aqc_opc_free_vsi = 0x0213, 2643 2644 /* recipe commands */ 2645 ice_aqc_opc_add_recipe = 0x0290, 2646 ice_aqc_opc_recipe_to_profile = 0x0291, 2647 ice_aqc_opc_get_recipe = 0x0292, 2648 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2649 2650 /* switch rules population commands */ 2651 ice_aqc_opc_add_sw_rules = 0x02A0, 2652 ice_aqc_opc_update_sw_rules = 0x02A1, 2653 ice_aqc_opc_remove_sw_rules = 0x02A2, 2654 2655 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2656 2657 /* DCB commands */ 2658 ice_aqc_opc_query_pfc_mode = 0x0302, 2659 ice_aqc_opc_set_pfc_mode = 0x0303, 2660 2661 /* transmit scheduler commands */ 2662 ice_aqc_opc_get_dflt_topo = 0x0400, 2663 ice_aqc_opc_add_sched_elems = 0x0401, 2664 ice_aqc_opc_cfg_sched_elems = 0x0403, 2665 ice_aqc_opc_get_sched_elems = 0x0404, 2666 ice_aqc_opc_move_sched_elems = 0x0408, 2667 ice_aqc_opc_suspend_sched_elems = 0x0409, 2668 ice_aqc_opc_resume_sched_elems = 0x040A, 2669 ice_aqc_opc_query_port_ets = 0x040E, 2670 ice_aqc_opc_delete_sched_elems = 0x040F, 2671 ice_aqc_opc_add_rl_profiles = 0x0410, 2672 ice_aqc_opc_query_sched_res = 0x0412, 2673 ice_aqc_opc_remove_rl_profiles = 0x0415, 2674 2675 /* tx topology commands */ 2676 ice_aqc_opc_set_tx_topo = 0x0417, 2677 ice_aqc_opc_get_tx_topo = 0x0418, 2678 2679 /* PHY commands */ 2680 ice_aqc_opc_get_phy_caps = 0x0600, 2681 ice_aqc_opc_set_phy_cfg = 0x0601, 2682 ice_aqc_opc_set_mac_cfg = 0x0603, 2683 ice_aqc_opc_restart_an = 0x0605, 2684 ice_aqc_opc_get_link_status = 0x0607, 2685 ice_aqc_opc_set_event_mask = 0x0613, 2686 ice_aqc_opc_set_mac_lb = 0x0620, 2687 ice_aqc_opc_set_phy_rec_clk_out = 0x0630, 2688 ice_aqc_opc_get_phy_rec_clk_out = 0x0631, 2689 ice_aqc_opc_get_sensor_reading = 0x0632, 2690 ice_aqc_opc_get_link_topo = 0x06E0, 2691 ice_aqc_opc_read_i2c = 0x06E2, 2692 ice_aqc_opc_write_i2c = 0x06E3, 2693 ice_aqc_opc_set_port_id_led = 0x06E9, 2694 ice_aqc_opc_get_port_options = 0x06EA, 2695 ice_aqc_opc_set_port_option = 0x06EB, 2696 ice_aqc_opc_set_gpio = 0x06EC, 2697 ice_aqc_opc_get_gpio = 0x06ED, 2698 ice_aqc_opc_sff_eeprom = 0x06EE, 2699 2700 /* NVM commands */ 2701 ice_aqc_opc_nvm_read = 0x0701, 2702 ice_aqc_opc_nvm_erase = 0x0702, 2703 ice_aqc_opc_nvm_write = 0x0703, 2704 ice_aqc_opc_nvm_checksum = 0x0706, 2705 ice_aqc_opc_nvm_write_activate = 0x0707, 2706 ice_aqc_opc_nvm_update_empr = 0x0709, 2707 ice_aqc_opc_nvm_pkg_data = 0x070A, 2708 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2709 2710 /* PF/VF mailbox commands */ 2711 ice_mbx_opc_send_msg_to_pf = 0x0801, 2712 ice_mbx_opc_send_msg_to_vf = 0x0802, 2713 /* LLDP commands */ 2714 ice_aqc_opc_lldp_get_mib = 0x0A00, 2715 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2716 ice_aqc_opc_lldp_stop = 0x0A05, 2717 ice_aqc_opc_lldp_start = 0x0A06, 2718 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2719 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2720 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2721 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2722 ice_aqc_opc_lldp_execute_pending_mib = 0x0A0B, 2723 2724 /* RSS commands */ 2725 ice_aqc_opc_set_rss_key = 0x0B02, 2726 ice_aqc_opc_set_rss_lut = 0x0B03, 2727 ice_aqc_opc_get_rss_key = 0x0B04, 2728 ice_aqc_opc_get_rss_lut = 0x0B05, 2729 2730 /* Sideband Control Interface commands */ 2731 ice_aqc_opc_neighbour_device_request = 0x0C00, 2732 2733 /* Tx queue handling commands/events */ 2734 ice_aqc_opc_add_txqs = 0x0C30, 2735 ice_aqc_opc_dis_txqs = 0x0C31, 2736 ice_aqc_opc_cfg_txqs = 0x0C32, 2737 ice_aqc_opc_add_rdma_qset = 0x0C33, 2738 2739 /* package commands */ 2740 ice_aqc_opc_download_pkg = 0x0C40, 2741 ice_aqc_opc_upload_section = 0x0C41, 2742 ice_aqc_opc_update_pkg = 0x0C42, 2743 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2744 2745 /* 1588/SyncE commands/events */ 2746 ice_aqc_opc_get_cgu_abilities = 0x0C61, 2747 ice_aqc_opc_set_cgu_input_config = 0x0C62, 2748 ice_aqc_opc_get_cgu_input_config = 0x0C63, 2749 ice_aqc_opc_set_cgu_output_config = 0x0C64, 2750 ice_aqc_opc_get_cgu_output_config = 0x0C65, 2751 ice_aqc_opc_get_cgu_dpll_status = 0x0C66, 2752 ice_aqc_opc_set_cgu_dpll_config = 0x0C67, 2753 ice_aqc_opc_set_cgu_ref_prio = 0x0C68, 2754 ice_aqc_opc_get_cgu_ref_prio = 0x0C69, 2755 ice_aqc_opc_get_cgu_info = 0x0C6A, 2756 2757 ice_aqc_opc_driver_shared_params = 0x0C90, 2758 2759 /* Standalone Commands/Events */ 2760 ice_aqc_opc_event_lan_overflow = 0x1001, 2761 2762 /* FW Logging Commands */ 2763 ice_aqc_opc_fw_logs_config = 0xFF30, 2764 ice_aqc_opc_fw_logs_register = 0xFF31, 2765 ice_aqc_opc_fw_logs_query = 0xFF32, 2766 ice_aqc_opc_fw_logs_event = 0xFF33, 2767 }; 2768 2769 #endif /* _ICE_ADMINQ_CMD_H_ */ 2770