1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Send driver version (indirect 0x0002) */ 37 struct ice_aqc_driver_ver { 38 u8 major_ver; 39 u8 minor_ver; 40 u8 build_ver; 41 u8 subbuild_ver; 42 u8 reserved[4]; 43 __le32 addr_high; 44 __le32 addr_low; 45 }; 46 47 /* Queue Shutdown (direct 0x0003) */ 48 struct ice_aqc_q_shutdown { 49 u8 driver_unloading; 50 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 51 u8 reserved[15]; 52 }; 53 54 /* Request resource ownership (direct 0x0008) 55 * Release resource ownership (direct 0x0009) 56 */ 57 struct ice_aqc_req_res { 58 __le16 res_id; 59 #define ICE_AQC_RES_ID_NVM 1 60 #define ICE_AQC_RES_ID_SDP 2 61 #define ICE_AQC_RES_ID_CHNG_LOCK 3 62 #define ICE_AQC_RES_ID_GLBL_LOCK 4 63 __le16 access_type; 64 #define ICE_AQC_RES_ACCESS_READ 1 65 #define ICE_AQC_RES_ACCESS_WRITE 2 66 67 /* Upon successful completion, FW writes this value and driver is 68 * expected to release resource before timeout. This value is provided 69 * in milliseconds. 70 */ 71 __le32 timeout; 72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76 /* For SDP: pin ID of the SDP */ 77 __le32 res_number; 78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79 __le16 status; 80 #define ICE_AQ_RES_GLBL_SUCCESS 0 81 #define ICE_AQ_RES_GLBL_IN_PROG 1 82 #define ICE_AQ_RES_GLBL_DONE 2 83 u8 reserved[2]; 84 }; 85 86 /* Get function capabilities (indirect 0x000A) 87 * Get device capabilities (indirect 0x000B) 88 */ 89 struct ice_aqc_list_caps { 90 u8 cmd_flags; 91 u8 pf_index; 92 u8 reserved[2]; 93 __le32 count; 94 __le32 addr_high; 95 __le32 addr_low; 96 }; 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_SRIOV 0x0012 103 #define ICE_AQC_CAPS_VF 0x0013 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_1588 0x0046 112 #define ICE_AQC_CAPS_MAX_MTU 0x0047 113 #define ICE_AQC_CAPS_NVM_VER 0x0048 114 #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049 115 #define ICE_AQC_CAPS_OROM_VER 0x004A 116 #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B 117 #define ICE_AQC_CAPS_NET_VER 0x004C 118 #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D 119 #define ICE_AQC_CAPS_RDMA 0x0051 120 #define ICE_AQC_CAPS_SENSOR_READING 0x0067 121 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 122 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 123 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 124 #define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092 125 #define ICE_AQC_BIT_ROCEV2_LAG 0x01 126 #define ICE_AQC_BIT_SRIOV_LAG 0x02 127 128 u8 major_ver; 129 u8 minor_ver; 130 /* Number of resources described by this capability */ 131 __le32 number; 132 /* Only meaningful for some types of resources */ 133 __le32 logical_id; 134 /* Only meaningful for some types of resources */ 135 __le32 phys_id; 136 __le64 rsvd1; 137 __le64 rsvd2; 138 }; 139 140 /* Manage MAC address, read command - indirect (0x0107) 141 * This struct is also used for the response 142 */ 143 struct ice_aqc_manage_mac_read { 144 __le16 flags; /* Zeroed by device driver */ 145 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 146 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 147 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 148 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 149 #define ICE_AQC_MAN_MAC_READ_S 4 150 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 151 u8 rsvd[2]; 152 u8 num_addr; /* Used in response */ 153 u8 rsvd1[3]; 154 __le32 addr_high; 155 __le32 addr_low; 156 }; 157 158 /* Response buffer format for manage MAC read command */ 159 struct ice_aqc_manage_mac_read_resp { 160 u8 lport_num; 161 u8 addr_type; 162 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 163 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 164 u8 mac_addr[ETH_ALEN]; 165 }; 166 167 /* Manage MAC address, write command - direct (0x0108) */ 168 struct ice_aqc_manage_mac_write { 169 u8 rsvd; 170 u8 flags; 171 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 172 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 173 #define ICE_AQC_MAN_MAC_WR_S 6 174 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 175 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 176 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 177 /* byte stream in network order */ 178 u8 mac_addr[ETH_ALEN]; 179 __le32 addr_high; 180 __le32 addr_low; 181 }; 182 183 /* Clear PXE Command and response (direct 0x0110) */ 184 struct ice_aqc_clear_pxe { 185 u8 rx_cnt; 186 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 187 u8 reserved[15]; 188 }; 189 190 /* Get switch configuration (0x0200) */ 191 struct ice_aqc_get_sw_cfg { 192 /* Reserved for command and copy of request flags for response */ 193 __le16 flags; 194 /* First desc in case of command and next_elem in case of response 195 * In case of response, if it is not zero, means all the configuration 196 * was not returned and new command shall be sent with this value in 197 * the 'first desc' field 198 */ 199 __le16 element; 200 /* Reserved for command, only used for response */ 201 __le16 num_elems; 202 __le16 rsvd; 203 __le32 addr_high; 204 __le32 addr_low; 205 }; 206 207 /* Each entry in the response buffer is of the following type: */ 208 struct ice_aqc_get_sw_cfg_resp_elem { 209 /* VSI/Port Number */ 210 __le16 vsi_port_num; 211 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 212 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 213 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 214 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 215 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 216 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 217 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 218 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 219 220 /* SWID VSI/Port belongs to */ 221 __le16 swid; 222 223 /* Bit 14..0 : PF/VF number VSI belongs to 224 * Bit 15 : VF indication bit 225 */ 226 __le16 pf_vf_num; 227 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 228 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 229 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 230 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 231 }; 232 233 /* Set Port parameters, (direct, 0x0203) */ 234 struct ice_aqc_set_port_params { 235 __le16 cmd_flags; 236 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 237 __le16 bad_frame_vsi; 238 __le16 swid; 239 #define ICE_AQC_PORT_SWID_VALID BIT(15) 240 #define ICE_AQC_PORT_SWID_M 0xFF 241 u8 reserved[10]; 242 }; 243 244 /* These resource type defines are used for all switch resource 245 * commands where a resource type is required, such as: 246 * Get Resource Allocation command (indirect 0x0204) 247 * Allocate Resources command (indirect 0x0208) 248 * Free Resources command (indirect 0x0209) 249 * Get Allocated Resource Descriptors Command (indirect 0x020A) 250 * Share Resource command (indirect 0x020B) 251 */ 252 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 253 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 254 #define ICE_AQC_RES_TYPE_RECIPE 0x05 255 #define ICE_AQC_RES_TYPE_SWID 0x07 256 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 257 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 258 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 259 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 260 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 261 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 262 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 263 264 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 265 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 266 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 267 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14) 268 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15) 269 270 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 271 272 #define ICE_AQC_RES_TYPE_S 0 273 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 274 275 /* Allocate Resources command (indirect 0x0208) 276 * Free Resources command (indirect 0x0209) 277 * Share Resource command (indirect 0x020B) 278 */ 279 struct ice_aqc_alloc_free_res_cmd { 280 __le16 num_entries; /* Number of Resource entries */ 281 u8 reserved[6]; 282 __le32 addr_high; 283 __le32 addr_low; 284 }; 285 286 /* Resource descriptor */ 287 struct ice_aqc_res_elem { 288 union { 289 __le16 sw_resp; 290 __le16 flu_resp; 291 } e; 292 }; 293 294 /* Buffer for Allocate/Free Resources commands */ 295 struct ice_aqc_alloc_free_res_elem { 296 __le16 res_type; /* Types defined above cmd 0x0204 */ 297 #define ICE_AQC_RES_TYPE_SHARED_S 7 298 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 299 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 300 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 301 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 302 __le16 num_elems; 303 struct ice_aqc_res_elem elem[]; 304 }; 305 306 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 307 struct ice_aqc_set_vlan_mode { 308 u8 reserved; 309 u8 l2tag_prio_tagging; 310 #define ICE_AQ_VLAN_PRIO_TAG_S 0 311 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 312 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 313 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 314 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 315 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 316 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 317 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 318 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 319 u8 l2tag_reserved[64]; 320 u8 rdma_packet; 321 #define ICE_AQ_VLAN_RDMA_TAG_S 0 322 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 323 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 324 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 325 u8 rdma_reserved[2]; 326 u8 mng_vlan_prot_id; 327 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 328 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 329 u8 prot_id_reserved[30]; 330 }; 331 332 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 333 struct ice_aqc_get_vlan_mode { 334 u8 vlan_mode; 335 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 336 u8 l2tag_prio_tagging; 337 u8 reserved[98]; 338 }; 339 340 /* Add VSI (indirect 0x0210) 341 * Update VSI (indirect 0x0211) 342 * Get VSI (indirect 0x0212) 343 * Free VSI (indirect 0x0213) 344 */ 345 struct ice_aqc_add_get_update_free_vsi { 346 __le16 vsi_num; 347 #define ICE_AQ_VSI_NUM_S 0 348 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 349 #define ICE_AQ_VSI_IS_VALID BIT(15) 350 __le16 cmd_flags; 351 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 352 u8 vf_id; 353 u8 reserved; 354 __le16 vsi_flags; 355 #define ICE_AQ_VSI_TYPE_S 0 356 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 357 #define ICE_AQ_VSI_TYPE_VF 0x0 358 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 359 #define ICE_AQ_VSI_TYPE_PF 0x2 360 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 361 __le32 addr_high; 362 __le32 addr_low; 363 }; 364 365 /* Response descriptor for: 366 * Add VSI (indirect 0x0210) 367 * Update VSI (indirect 0x0211) 368 * Free VSI (indirect 0x0213) 369 */ 370 struct ice_aqc_add_update_free_vsi_resp { 371 __le16 vsi_num; 372 __le16 ext_status; 373 __le16 vsi_used; 374 __le16 vsi_free; 375 __le32 addr_high; 376 __le32 addr_low; 377 }; 378 379 struct ice_aqc_vsi_props { 380 __le16 valid_sections; 381 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 382 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 383 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 384 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 385 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 386 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 387 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 388 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 389 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 390 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 391 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 392 /* switch section */ 393 u8 sw_id; 394 u8 sw_flags; 395 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 396 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 397 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 398 u8 sw_flags2; 399 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 400 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 401 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 402 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 403 u8 veb_stat_id; 404 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 405 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 406 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 407 /* security section */ 408 u8 sec_flags; 409 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 410 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 411 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 412 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 413 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 414 u8 sec_reserved; 415 /* VLAN section */ 416 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 417 u8 inner_vlan_reserved[2]; 418 u8 inner_vlan_flags; 419 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 420 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 421 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 422 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 423 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 424 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 425 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 426 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 427 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH 0x0U 428 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP 0x1U 429 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR 0x2U 430 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING 0x3U 431 u8 inner_vlan_reserved2[3]; 432 /* ingress egress up sections */ 433 __le32 ingress_table; /* bitmap, 3 bits per up */ 434 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 435 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 436 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 437 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 438 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 439 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 440 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 441 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 442 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 443 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 444 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 445 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 446 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 447 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 448 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 449 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 450 __le32 egress_table; /* same defines as for ingress table */ 451 /* outer tags section */ 452 __le16 port_based_outer_vlan; 453 u8 outer_vlan_flags; 454 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 455 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 456 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 457 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 458 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 459 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 460 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 461 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 462 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 463 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 464 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 465 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 466 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 467 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 468 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 469 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 470 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 471 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 472 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 473 u8 outer_vlan_reserved; 474 /* queue mapping section */ 475 __le16 mapping_flags; 476 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 477 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 478 __le16 q_mapping[16]; 479 #define ICE_AQ_VSI_Q_S 0 480 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 481 __le16 tc_mapping[8]; 482 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 483 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 484 #define ICE_AQ_VSI_TC_Q_NUM_S 11 485 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 486 /* queueing option section */ 487 u8 q_opt_rss; 488 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 489 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 490 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 491 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 492 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 493 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 494 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 495 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 496 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6) 497 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ 0x0U 498 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ 0x1U 499 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR 0x2U 500 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH 0x3U 501 u8 q_opt_tc; 502 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 503 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 504 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 505 u8 q_opt_flags; 506 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 507 u8 q_opt_reserved[3]; 508 /* outer up section */ 509 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 510 /* section 10 */ 511 __le16 sect_10_reserved; 512 /* flow director section */ 513 __le16 fd_options; 514 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 515 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 516 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 517 __le16 max_fd_fltr_dedicated; 518 __le16 max_fd_fltr_shared; 519 __le16 fd_def_q; 520 #define ICE_AQ_VSI_FD_DEF_Q_S 0 521 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 522 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 523 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 524 __le16 fd_report_opt; 525 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 526 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 527 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 528 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 529 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 530 /* PASID section */ 531 __le32 pasid_id; 532 #define ICE_AQ_VSI_PASID_ID_S 0 533 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 534 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 535 u8 reserved[24]; 536 }; 537 538 #define ICE_MAX_NUM_RECIPES 64 539 540 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 541 struct ice_aqc_add_get_recipe { 542 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 543 __le16 return_index; /* Input, used for Get cmd only */ 544 u8 reserved[4]; 545 __le32 addr_high; 546 __le32 addr_low; 547 }; 548 549 struct ice_aqc_recipe_content { 550 u8 rid; 551 #define ICE_AQ_RECIPE_ID_S 0 552 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 553 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 554 #define ICE_AQ_SW_ID_LKUP_IDX 0 555 u8 lkup_indx[5]; 556 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 557 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 558 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 559 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 560 __le16 mask[5]; 561 u8 result_indx; 562 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 563 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 564 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 565 u8 rsvd0[3]; 566 u8 act_ctrl_join_priority; 567 u8 act_ctrl_fwd_priority; 568 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 569 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 570 u8 act_ctrl; 571 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 572 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 573 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 574 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 575 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 576 u8 rsvd1; 577 __le32 dflt_act; 578 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 579 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 580 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 581 }; 582 583 struct ice_aqc_recipe_data_elem { 584 u8 recipe_indx; 585 u8 resp_bits; 586 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 587 u8 rsvd0[2]; 588 u8 recipe_bitmap[8]; 589 u8 rsvd1[4]; 590 struct ice_aqc_recipe_content content; 591 u8 rsvd2[20]; 592 }; 593 594 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 595 struct ice_aqc_recipe_to_profile { 596 __le16 profile_id; 597 u8 rsvd[6]; 598 __le64 recipe_assoc; 599 }; 600 static_assert(sizeof(struct ice_aqc_recipe_to_profile) == 16); 601 602 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 603 */ 604 struct ice_aqc_sw_rules { 605 /* ops: add switch rules, referring the number of rules. 606 * ops: update switch rules, referring the number of filters 607 * ops: remove switch rules, referring the entry index. 608 * ops: get switch rules, referring to the number of filters. 609 */ 610 __le16 num_rules_fltr_entry_index; 611 u8 reserved[6]; 612 __le32 addr_high; 613 __le32 addr_low; 614 }; 615 616 /* Add switch rule response: 617 * Content of return buffer is same as the input buffer. The status field and 618 * LUT index are updated as part of the response 619 */ 620 struct ice_aqc_sw_rules_elem_hdr { 621 __le16 type; /* Switch rule type, one of T_... */ 622 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 623 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 624 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 625 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 626 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 627 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 628 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 629 __le16 status; 630 } __packed __aligned(sizeof(__le16)); 631 632 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 633 * This structures describes the lookup rules and associated actions. "index" 634 * is returned as part of a response to a successful Add command, and can be 635 * used to identify the rule for Update/Get/Remove commands. 636 */ 637 struct ice_sw_rule_lkup_rx_tx { 638 struct ice_aqc_sw_rules_elem_hdr hdr; 639 640 __le16 recipe_id; 641 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 642 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 643 __le16 src; 644 __le32 act; 645 646 /* Bit 0:1 - Action type */ 647 #define ICE_SINGLE_ACT_TYPE_S 0x00 648 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 649 650 /* Bit 2 - Loop back enable 651 * Bit 3 - LAN enable 652 */ 653 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 654 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 655 656 /* Action type = 0 - Forward to VSI or VSI list */ 657 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 658 659 #define ICE_SINGLE_ACT_VSI_ID_S 4 660 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 661 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 662 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 663 /* This bit needs to be set if action is forward to VSI list */ 664 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 665 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 666 #define ICE_SINGLE_ACT_DROP BIT(18) 667 668 /* Action type = 1 - Forward to Queue of Queue group */ 669 #define ICE_SINGLE_ACT_TO_Q 0x1 670 #define ICE_SINGLE_ACT_Q_INDEX_S 4 671 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 672 #define ICE_SINGLE_ACT_Q_REGION_S 15 673 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 674 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 675 676 /* Action type = 2 - Prune */ 677 #define ICE_SINGLE_ACT_PRUNE 0x2 678 #define ICE_SINGLE_ACT_EGRESS BIT(15) 679 #define ICE_SINGLE_ACT_INGRESS BIT(16) 680 #define ICE_SINGLE_ACT_PRUNET BIT(17) 681 /* Bit 18 should be set to 0 for this action */ 682 683 /* Action type = 2 - Pointer */ 684 #define ICE_SINGLE_ACT_PTR 0x2 685 #define ICE_SINGLE_ACT_PTR_VAL_S 4 686 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 687 /* Bit 18 should be set to 1 */ 688 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 689 690 /* Action type = 3 - Other actions. Last two bits 691 * are other action identifier 692 */ 693 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 694 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 695 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 696 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 697 698 /* Bit 17:18 - Defines other actions */ 699 /* Other action = 0 - Mirror VSI */ 700 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 701 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 702 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 703 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 704 705 /* Other action = 3 - Set Stat count */ 706 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 707 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 708 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 709 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 710 711 __le16 index; /* The index of the rule in the lookup table */ 712 /* Length and values of the header to be matched per recipe or 713 * lookup-type 714 */ 715 __le16 hdr_len; 716 u8 hdr_data[]; 717 } __packed __aligned(sizeof(__le16)); 718 719 /* Add/Update/Remove large action command/response entry 720 * "index" is returned as part of a response to a successful Add command, and 721 * can be used to identify the action for Update/Get/Remove commands. 722 */ 723 struct ice_sw_rule_lg_act { 724 struct ice_aqc_sw_rules_elem_hdr hdr; 725 726 __le16 index; /* Index in large action table */ 727 __le16 size; 728 /* Max number of large actions */ 729 #define ICE_MAX_LG_ACT 4 730 /* Bit 0:1 - Action type */ 731 #define ICE_LG_ACT_TYPE_S 0 732 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 733 734 /* Action type = 0 - Forward to VSI or VSI list */ 735 #define ICE_LG_ACT_VSI_FORWARDING 0 736 #define ICE_LG_ACT_VSI_ID_S 3 737 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 738 #define ICE_LG_ACT_VSI_LIST_ID_S 3 739 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 740 /* This bit needs to be set if action is forward to VSI list */ 741 #define ICE_LG_ACT_VSI_LIST BIT(13) 742 743 #define ICE_LG_ACT_VALID_BIT BIT(16) 744 745 /* Action type = 1 - Forward to Queue of Queue group */ 746 #define ICE_LG_ACT_TO_Q 0x1 747 #define ICE_LG_ACT_Q_INDEX_S 3 748 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 749 #define ICE_LG_ACT_Q_REGION_S 14 750 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 751 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 752 753 /* Action type = 2 - Prune */ 754 #define ICE_LG_ACT_PRUNE 0x2 755 #define ICE_LG_ACT_EGRESS BIT(14) 756 #define ICE_LG_ACT_INGRESS BIT(15) 757 #define ICE_LG_ACT_PRUNET BIT(16) 758 759 /* Action type = 3 - Mirror VSI */ 760 #define ICE_LG_OTHER_ACT_MIRROR 0x3 761 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 762 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 763 764 /* Action type = 5 - Generic Value */ 765 #define ICE_LG_ACT_GENERIC 0x5 766 #define ICE_LG_ACT_GENERIC_VALUE_S 3 767 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 768 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 769 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 770 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 771 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 772 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 773 774 /* Action = 7 - Set Stat count */ 775 #define ICE_LG_ACT_STAT_COUNT 0x7 776 #define ICE_LG_ACT_STAT_COUNT_S 3 777 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 778 __le32 act[]; /* array of size for actions */ 779 } __packed __aligned(sizeof(__le16)); 780 781 /* Add/Update/Remove VSI list command/response entry 782 * "index" is returned as part of a response to a successful Add command, and 783 * can be used to identify the VSI list for Update/Get/Remove commands. 784 */ 785 struct ice_sw_rule_vsi_list { 786 struct ice_aqc_sw_rules_elem_hdr hdr; 787 788 __le16 index; /* Index of VSI/Prune list */ 789 __le16 number_vsi; 790 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 791 } __packed __aligned(sizeof(__le16)); 792 793 /* Query PFC Mode (direct 0x0302) 794 * Set PFC Mode (direct 0x0303) 795 */ 796 struct ice_aqc_set_query_pfc_mode { 797 u8 pfc_mode; 798 /* For Query Command response, reserved in all other cases */ 799 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 800 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 801 u8 rsvd[15]; 802 }; 803 /* Get Default Topology (indirect 0x0400) */ 804 struct ice_aqc_get_topo { 805 u8 port_num; 806 u8 num_branches; 807 __le16 reserved1; 808 __le32 reserved2; 809 __le32 addr_high; 810 __le32 addr_low; 811 }; 812 813 /* Update TSE (indirect 0x0403) 814 * Get TSE (indirect 0x0404) 815 * Add TSE (indirect 0x0401) 816 * Delete TSE (indirect 0x040F) 817 * Move TSE (indirect 0x0408) 818 * Suspend Nodes (indirect 0x0409) 819 * Resume Nodes (indirect 0x040A) 820 */ 821 struct ice_aqc_sched_elem_cmd { 822 __le16 num_elem_req; /* Used by commands */ 823 __le16 num_elem_resp; /* Used by responses */ 824 __le32 reserved; 825 __le32 addr_high; 826 __le32 addr_low; 827 }; 828 829 struct ice_aqc_txsched_move_grp_info_hdr { 830 __le32 src_parent_teid; 831 __le32 dest_parent_teid; 832 __le16 num_elems; 833 u8 mode; 834 #define ICE_AQC_MOVE_ELEM_MODE_SAME_PF 0x0 835 #define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN 0x1 836 #define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN 0x2 837 u8 reserved; 838 }; 839 840 struct ice_aqc_move_elem { 841 struct ice_aqc_txsched_move_grp_info_hdr hdr; 842 __le32 teid[]; 843 }; 844 845 struct ice_aqc_elem_info_bw { 846 __le16 bw_profile_idx; 847 __le16 bw_alloc; 848 }; 849 850 struct ice_aqc_txsched_elem { 851 u8 elem_type; /* Special field, reserved for some aq calls */ 852 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 853 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 854 #define ICE_AQC_ELEM_TYPE_TC 0x2 855 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 856 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 857 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 858 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 859 u8 valid_sections; 860 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 861 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 862 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 863 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 864 u8 generic; 865 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 866 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 867 #define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1) 868 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 869 #define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4) 870 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 871 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 872 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 873 u8 flags; /* Special field, reserved for some aq calls */ 874 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 875 struct ice_aqc_elem_info_bw cir_bw; 876 struct ice_aqc_elem_info_bw eir_bw; 877 __le16 srl_id; 878 __le16 reserved2; 879 }; 880 881 struct ice_aqc_txsched_elem_data { 882 __le32 parent_teid; 883 __le32 node_teid; 884 struct ice_aqc_txsched_elem data; 885 }; 886 887 struct ice_aqc_txsched_topo_grp_info_hdr { 888 __le32 parent_teid; 889 __le16 num_elems; 890 __le16 reserved2; 891 }; 892 893 struct ice_aqc_add_elem { 894 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 895 struct ice_aqc_txsched_elem_data generic[]; 896 }; 897 898 struct ice_aqc_get_topo_elem { 899 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 900 struct ice_aqc_txsched_elem_data 901 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 902 }; 903 904 struct ice_aqc_delete_elem { 905 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 906 __le32 teid[]; 907 }; 908 909 /* Query Port ETS (indirect 0x040E) 910 * 911 * This indirect command is used to query port TC node configuration. 912 */ 913 struct ice_aqc_query_port_ets { 914 __le32 port_teid; 915 __le32 reserved; 916 __le32 addr_high; 917 __le32 addr_low; 918 }; 919 920 struct ice_aqc_port_ets_elem { 921 u8 tc_valid_bits; 922 u8 reserved[3]; 923 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 924 __le32 up2tc; 925 u8 tc_bw_share[8]; 926 __le32 port_eir_prof_id; 927 __le32 port_cir_prof_id; 928 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 929 __le32 tc_node_prio; 930 #define ICE_TC_NODE_PRIO_S 0x4 931 u8 reserved1[4]; 932 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 933 }; 934 935 /* Rate limiting profile for 936 * Add RL profile (indirect 0x0410) 937 * Query RL profile (indirect 0x0411) 938 * Remove RL profile (indirect 0x0415) 939 * These indirect commands acts on single or multiple 940 * RL profiles with specified data. 941 */ 942 struct ice_aqc_rl_profile { 943 __le16 num_profiles; 944 __le16 num_processed; /* Only for response. Reserved in Command. */ 945 u8 reserved[4]; 946 __le32 addr_high; 947 __le32 addr_low; 948 }; 949 950 struct ice_aqc_rl_profile_elem { 951 u8 level; 952 u8 flags; 953 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 954 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 955 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 956 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 957 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 958 /* The following flag is used for Query RL Profile Data */ 959 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 960 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 961 962 __le16 profile_id; 963 __le16 max_burst_size; 964 __le16 rl_multiply; 965 __le16 wake_up_calc; 966 __le16 rl_encode; 967 }; 968 969 /* Query Scheduler Resource Allocation (indirect 0x0412) 970 * This indirect command retrieves the scheduler resources allocated by 971 * EMP Firmware to the given PF. 972 */ 973 struct ice_aqc_query_txsched_res { 974 u8 reserved[8]; 975 __le32 addr_high; 976 __le32 addr_low; 977 }; 978 979 struct ice_aqc_generic_sched_props { 980 __le16 phys_levels; 981 __le16 logical_levels; 982 u8 flattening_bitmap; 983 u8 max_device_cgds; 984 u8 max_pf_cgds; 985 u8 rsvd0; 986 __le16 rdma_qsets; 987 u8 rsvd1[22]; 988 }; 989 990 struct ice_aqc_layer_props { 991 u8 logical_layer; 992 u8 chunk_size; 993 __le16 max_device_nodes; 994 __le16 max_pf_nodes; 995 u8 rsvd0[4]; 996 __le16 max_sibl_grp_sz; 997 __le16 max_cir_rl_profiles; 998 __le16 max_eir_rl_profiles; 999 __le16 max_srl_profiles; 1000 u8 rsvd1[14]; 1001 }; 1002 1003 struct ice_aqc_query_txsched_res_resp { 1004 struct ice_aqc_generic_sched_props sched_props; 1005 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1006 }; 1007 1008 /* Get PHY capabilities (indirect 0x0600) */ 1009 struct ice_aqc_get_phy_caps { 1010 u8 lport_num; 1011 u8 reserved; 1012 __le16 param0; 1013 /* 18.0 - Report qualified modules */ 1014 #define ICE_AQC_GET_PHY_RQM BIT(0) 1015 /* 18.1 - 18.3 : Report mode 1016 * 000b - Report NVM capabilities 1017 * 001b - Report topology capabilities 1018 * 010b - Report SW configured 1019 * 100b - Report default capabilities 1020 */ 1021 #define ICE_AQC_REPORT_MODE_S 1 1022 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1023 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1024 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1025 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1026 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1027 __le32 reserved1; 1028 __le32 addr_high; 1029 __le32 addr_low; 1030 }; 1031 1032 /* This is #define of PHY type (Extended): 1033 * The first set of defines is for phy_type_low. 1034 */ 1035 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1036 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1037 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1038 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1039 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1040 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1041 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1042 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1043 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1044 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1045 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1046 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1047 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1048 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1049 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1050 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1051 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1052 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1053 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1054 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1055 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1056 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1057 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1058 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1059 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1060 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1061 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1062 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1063 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1064 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1065 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1066 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1067 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1068 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1069 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1070 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1071 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1072 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1073 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1074 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1075 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1076 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1077 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1078 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1079 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1080 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1081 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1082 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1083 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1084 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1085 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1086 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1087 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1088 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1089 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1090 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1091 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1092 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1093 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1094 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1095 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1096 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1097 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1098 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1099 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1100 /* The second set of defines is for phy_type_high. */ 1101 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1102 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1103 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1104 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1105 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1106 #define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) 1107 #define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) 1108 #define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) 1109 #define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) 1110 #define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) 1111 #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) 1112 #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) 1113 #define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) 1114 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 12 1115 1116 struct ice_aqc_get_phy_caps_data { 1117 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1118 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1119 u8 caps; 1120 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1121 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1122 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1123 #define ICE_AQC_PHY_EN_LINK BIT(3) 1124 #define ICE_AQC_PHY_AN_MODE BIT(4) 1125 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 1126 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1127 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 1128 u8 low_power_ctrl_an; 1129 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1130 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1131 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1132 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1133 __le16 eee_cap; 1134 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1135 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1136 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1137 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1138 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1139 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1140 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1141 __le16 eeer_value; 1142 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1143 u8 phy_fw_ver[8]; 1144 u8 link_fec_options; 1145 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1146 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1147 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1148 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1149 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1150 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1151 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1152 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1153 u8 module_compliance_enforcement; 1154 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1155 u8 extended_compliance_code; 1156 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1157 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1158 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1159 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1160 #define ICE_AQC_MOD_TYPE_IDENT 1 1161 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1162 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1163 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1164 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1165 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1166 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1167 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1168 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1169 u8 qualified_module_count; 1170 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1171 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1172 struct { 1173 u8 v_oui[3]; 1174 u8 rsvd3; 1175 u8 v_part[16]; 1176 __le32 v_rev; 1177 __le64 rsvd4; 1178 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1179 }; 1180 1181 /* Set PHY capabilities (direct 0x0601) 1182 * NOTE: This command must be followed by setup link and restart auto-neg 1183 */ 1184 struct ice_aqc_set_phy_cfg { 1185 u8 lport_num; 1186 u8 reserved[7]; 1187 __le32 addr_high; 1188 __le32 addr_low; 1189 }; 1190 1191 /* Set PHY config command data structure */ 1192 struct ice_aqc_set_phy_cfg_data { 1193 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1194 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1195 u8 caps; 1196 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1197 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1198 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1199 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1200 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1201 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1202 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1203 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1204 u8 low_power_ctrl_an; 1205 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1206 __le16 eeer_value; 1207 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1208 u8 module_compliance_enforcement; 1209 }; 1210 1211 /* Set MAC Config command data structure (direct 0x0603) */ 1212 struct ice_aqc_set_mac_cfg { 1213 __le16 max_frame_size; 1214 u8 params; 1215 #define ICE_AQ_SET_MAC_PACE_S 3 1216 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1217 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1218 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1219 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1220 u8 tx_tmr_priority; 1221 __le16 tx_tmr_value; 1222 __le16 fc_refresh_threshold; 1223 u8 drop_opts; 1224 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1225 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1226 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1227 u8 reserved[7]; 1228 }; 1229 1230 /* Restart AN command data structure (direct 0x0605) 1231 * Also used for response, with only the lport_num field present. 1232 */ 1233 struct ice_aqc_restart_an { 1234 u8 lport_num; 1235 u8 reserved; 1236 u8 cmd_flags; 1237 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1238 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1239 u8 reserved2[13]; 1240 }; 1241 1242 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1243 struct ice_aqc_get_link_status { 1244 u8 lport_num; 1245 u8 reserved; 1246 __le16 cmd_flags; 1247 #define ICE_AQ_LSE_M 0x3 1248 #define ICE_AQ_LSE_NOP 0x0 1249 #define ICE_AQ_LSE_DIS 0x2 1250 #define ICE_AQ_LSE_ENA 0x3 1251 /* only response uses this flag */ 1252 #define ICE_AQ_LSE_IS_ENABLED 0x1 1253 __le32 reserved2; 1254 __le32 addr_high; 1255 __le32 addr_low; 1256 }; 1257 1258 /* Get link status response data structure, also used for Link Status Event */ 1259 struct ice_aqc_get_link_status_data { 1260 u8 topo_media_conflict; 1261 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1262 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1263 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1264 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1265 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1266 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1267 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1268 u8 link_cfg_err; 1269 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1270 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1271 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1272 u8 link_info; 1273 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1274 #define ICE_AQ_LINK_FAULT BIT(1) 1275 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1276 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1277 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1278 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1279 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1280 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1281 u8 an_info; 1282 #define ICE_AQ_AN_COMPLETED BIT(0) 1283 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1284 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1285 #define ICE_AQ_FEC_EN BIT(3) 1286 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1287 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1288 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1289 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1290 u8 ext_info; 1291 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1292 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1293 /* Port Tx Suspended */ 1294 #define ICE_AQ_LINK_TX_S 2 1295 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1296 #define ICE_AQ_LINK_TX_ACTIVE 0 1297 #define ICE_AQ_LINK_TX_DRAINED 1 1298 #define ICE_AQ_LINK_TX_FLUSHED 3 1299 u8 reserved2; 1300 __le16 max_frame_size; 1301 u8 cfg; 1302 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1303 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1304 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1305 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1306 /* Pacing Config */ 1307 #define ICE_AQ_CFG_PACING_S 3 1308 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1309 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1310 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1311 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1312 /* External Device Power Ability */ 1313 u8 power_desc; 1314 #define ICE_AQ_PWR_CLASS_M 0x3F 1315 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1316 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1317 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1318 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1319 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1320 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1321 __le16 link_speed; 1322 #define ICE_AQ_LINK_SPEED_M 0x7FF 1323 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1324 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1325 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1326 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1327 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1328 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1329 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1330 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1331 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1332 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1333 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1334 #define ICE_AQ_LINK_SPEED_200GB BIT(11) 1335 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1336 /* Aligns next field to 8-byte boundary */ 1337 __le16 reserved3; 1338 u8 ext_fec_status; 1339 /* RS 272 FEC enabled */ 1340 #define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) 1341 u8 reserved4; 1342 /* Use values from ICE_PHY_TYPE_LOW_* */ 1343 __le64 phy_type_low; 1344 /* Use values from ICE_PHY_TYPE_HIGH_* */ 1345 __le64 phy_type_high; 1346 #define ICE_AQC_LS_DATA_SIZE_V1 \ 1347 offsetofend(struct ice_aqc_get_link_status_data, phy_type_high) 1348 /* Get link status v2 link partner data */ 1349 __le64 lp_phy_type_low; 1350 __le64 lp_phy_type_high; 1351 u8 lp_fec_adv; 1352 #define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0) 1353 #define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1) 1354 #define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2) 1355 #define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 1356 #define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 1357 #define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 1358 u8 lp_fec_req; 1359 #define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0) 1360 #define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1) 1361 #define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2) 1362 #define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3) 1363 u8 lp_flowcontrol; 1364 #define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0) 1365 #define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1) 1366 u8 reserved5[5]; 1367 #define ICE_AQC_LS_DATA_SIZE_V2 \ 1368 offsetofend(struct ice_aqc_get_link_status_data, reserved5) 1369 } __packed; 1370 1371 /* Set event mask command (direct 0x0613) */ 1372 struct ice_aqc_set_event_mask { 1373 u8 lport_num; 1374 u8 reserved[7]; 1375 __le16 event_mask; 1376 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1377 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1378 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1379 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1380 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1381 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1382 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1383 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1384 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1385 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1386 u8 reserved1[6]; 1387 }; 1388 1389 /* Set MAC Loopback command (direct 0x0620) */ 1390 struct ice_aqc_set_mac_lb { 1391 u8 lb_mode; 1392 #define ICE_AQ_MAC_LB_EN BIT(0) 1393 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1394 u8 reserved[15]; 1395 }; 1396 1397 /* Set PHY recovered clock output (direct 0x0630) */ 1398 struct ice_aqc_set_phy_rec_clk_out { 1399 u8 phy_output; 1400 u8 port_num; 1401 #define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1402 u8 flags; 1403 #define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1404 u8 rsvd; 1405 __le32 freq; 1406 u8 rsvd2[6]; 1407 __le16 node_handle; 1408 }; 1409 1410 /* Get PHY recovered clock output (direct 0x0631) */ 1411 struct ice_aqc_get_phy_rec_clk_out { 1412 u8 phy_output; 1413 u8 port_num; 1414 #define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1415 u8 flags; 1416 #define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1417 u8 rsvd[11]; 1418 __le16 node_handle; 1419 }; 1420 1421 /* Get sensor reading (direct 0x0632) */ 1422 struct ice_aqc_get_sensor_reading { 1423 u8 sensor; 1424 u8 format; 1425 u8 reserved[6]; 1426 __le32 addr_high; 1427 __le32 addr_low; 1428 }; 1429 1430 /* Get sensor reading response (direct 0x0632) */ 1431 struct ice_aqc_get_sensor_reading_resp { 1432 union { 1433 u8 raw[8]; 1434 /* Output data for sensor 0x00, format 0x00 */ 1435 struct _packed { 1436 s8 temp; 1437 u8 temp_warning_threshold; 1438 u8 temp_critical_threshold; 1439 u8 temp_fatal_threshold; 1440 u8 reserved[4]; 1441 } s0f0; 1442 } data; 1443 }; 1444 1445 struct ice_aqc_link_topo_params { 1446 u8 lport_num; 1447 u8 lport_num_valid; 1448 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1449 u8 node_type_ctx; 1450 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1451 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1452 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1453 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1454 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1455 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1456 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1457 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1458 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1459 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1460 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1461 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 9 1462 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 10 1463 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS 11 1464 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1465 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1466 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1467 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1468 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1469 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1470 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1471 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1472 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1473 u8 index; 1474 }; 1475 1476 struct ice_aqc_link_topo_addr { 1477 struct ice_aqc_link_topo_params topo_params; 1478 __le16 handle; 1479 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1480 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1481 /* Used to decode the handle field */ 1482 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1483 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1484 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1485 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1486 /* In case of a Mezzanine type */ 1487 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1488 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1489 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1490 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1491 /* In case of a LOM type */ 1492 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1493 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1494 }; 1495 1496 /* Get Link Topology Handle (direct, 0x06E0) */ 1497 struct ice_aqc_get_link_topo { 1498 struct ice_aqc_link_topo_addr addr; 1499 u8 node_part_num; 1500 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1501 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 1502 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25 1503 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30 1504 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31 1505 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 1506 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 1507 u8 rsvd[9]; 1508 }; 1509 1510 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1511 struct ice_aqc_i2c { 1512 struct ice_aqc_link_topo_addr topo_addr; 1513 __le16 i2c_addr; 1514 u8 i2c_params; 1515 #define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0) 1516 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1517 1518 u8 rsvd; 1519 __le16 i2c_bus_addr; 1520 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1521 }; 1522 1523 /* Read I2C Response (direct, 0x06E2) */ 1524 struct ice_aqc_read_i2c_resp { 1525 u8 i2c_data[16]; 1526 }; 1527 1528 /* Set Port Identification LED (direct, 0x06E9) */ 1529 struct ice_aqc_set_port_id_led { 1530 u8 lport_num; 1531 u8 lport_num_valid; 1532 u8 ident_mode; 1533 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1534 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1535 u8 rsvd[13]; 1536 }; 1537 1538 /* Get Port Options (indirect, 0x06EA) */ 1539 struct ice_aqc_get_port_options { 1540 u8 lport_num; 1541 u8 lport_num_valid; 1542 u8 port_options_count; 1543 #define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0) 1544 #define ICE_AQC_PORT_OPT_MAX 16 1545 1546 u8 innermost_phy_index; 1547 u8 port_options; 1548 #define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0) 1549 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1550 1551 u8 pending_port_option_status; 1552 #define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0) 1553 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 1554 1555 u8 rsvd[2]; 1556 __le32 addr_high; 1557 __le32 addr_low; 1558 }; 1559 1560 struct ice_aqc_get_port_options_elem { 1561 u8 pmd; 1562 #define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0) 1563 1564 u8 max_lane_speed; 1565 #define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0) 1566 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1567 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1568 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1569 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1570 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1571 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1572 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1573 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1574 1575 u8 global_scid[2]; 1576 u8 phy_scid[2]; 1577 u8 pf2port_cid[2]; 1578 }; 1579 1580 /* Set Port Option (direct, 0x06EB) */ 1581 struct ice_aqc_set_port_option { 1582 u8 lport_num; 1583 u8 lport_num_valid; 1584 u8 selected_port_option; 1585 u8 rsvd[13]; 1586 }; 1587 1588 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1589 struct ice_aqc_gpio { 1590 __le16 gpio_ctrl_handle; 1591 #define ICE_AQC_GPIO_HANDLE_S 0 1592 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1593 u8 gpio_num; 1594 u8 gpio_val; 1595 u8 rsvd[12]; 1596 }; 1597 1598 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1599 struct ice_aqc_sff_eeprom { 1600 u8 lport_num; 1601 u8 lport_num_valid; 1602 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1603 __le16 i2c_bus_addr; 1604 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1605 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1606 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1607 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1608 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1609 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1610 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1611 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1612 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1613 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1614 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1615 __le16 i2c_mem_addr; 1616 __le16 eeprom_page; 1617 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1618 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1619 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1620 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1621 __le32 addr_high; 1622 __le32 addr_low; 1623 }; 1624 1625 /* NVM Read command (indirect 0x0701) 1626 * NVM Erase commands (direct 0x0702) 1627 * NVM Update commands (indirect 0x0703) 1628 */ 1629 struct ice_aqc_nvm { 1630 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1631 __le16 offset_low; 1632 u8 offset_high; 1633 u8 cmd_flags; 1634 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1635 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1636 #define ICE_AQC_NVM_PRESERVATION_S 1 1637 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1638 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1639 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1640 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1641 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1642 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1643 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1644 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1645 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1646 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1647 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1648 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1649 #define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */ 1650 #define ICE_AQC_NVM_POR_FLAG 0 1651 #define ICE_AQC_NVM_PERST_FLAG 1 1652 #define ICE_AQC_NVM_EMPR_FLAG 2 1653 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 1654 /* For Write Activate, several flags are sent as part of a separate 1655 * flags2 field using a separate byte. For simplicity of the software 1656 * interface, we pass the flags as a 16 bit value so these flags are 1657 * all offset by 8 bits 1658 */ 1659 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 1660 __le16 module_typeid; 1661 __le16 length; 1662 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1663 __le32 addr_high; 1664 __le32 addr_low; 1665 }; 1666 1667 #define ICE_AQC_NVM_START_POINT 0 1668 1669 /* NVM Checksum Command (direct, 0x0706) */ 1670 struct ice_aqc_nvm_checksum { 1671 u8 flags; 1672 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1673 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1674 u8 rsvd; 1675 __le16 checksum; /* Used only by response */ 1676 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1677 u8 rsvd2[12]; 1678 }; 1679 1680 /* Used for NVM Set Package Data command - 0x070A */ 1681 struct ice_aqc_nvm_pkg_data { 1682 u8 reserved[3]; 1683 u8 cmd_flags; 1684 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1685 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1686 1687 u32 reserved1; 1688 __le32 addr_high; 1689 __le32 addr_low; 1690 }; 1691 1692 /* Used for Pass Component Table command - 0x070B */ 1693 struct ice_aqc_nvm_pass_comp_tbl { 1694 u8 component_response; /* Response only */ 1695 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1696 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1697 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1698 u8 component_response_code; /* Response only */ 1699 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1700 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1701 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1702 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1703 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1704 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1705 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1706 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1707 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1708 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1709 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1710 u8 reserved; 1711 u8 transfer_flag; 1712 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1713 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1714 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1715 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1716 __le32 reserved1; 1717 __le32 addr_high; 1718 __le32 addr_low; 1719 }; 1720 1721 struct ice_aqc_nvm_comp_tbl { 1722 __le16 comp_class; 1723 #define NVM_COMP_CLASS_ALL_FW 0x000A 1724 1725 __le16 comp_id; 1726 #define NVM_COMP_ID_OROM 0x5 1727 #define NVM_COMP_ID_NVM 0x6 1728 #define NVM_COMP_ID_NETLIST 0x8 1729 1730 u8 comp_class_idx; 1731 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1732 1733 __le32 comp_cmp_stamp; 1734 u8 cvs_type; 1735 #define NVM_CVS_TYPE_ASCII 0x1 1736 1737 u8 cvs_len; 1738 u8 cvs[]; /* Component Version String */ 1739 } __packed; 1740 1741 /* Send to PF command (indirect 0x0801) ID is only used by PF 1742 * 1743 * Send to VF command (indirect 0x0802) ID is only used by PF 1744 * 1745 */ 1746 struct ice_aqc_pf_vf_msg { 1747 __le32 id; 1748 u32 reserved; 1749 __le32 addr_high; 1750 __le32 addr_low; 1751 }; 1752 1753 /* Get LLDP MIB (indirect 0x0A00) 1754 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1755 * as the format is the same. 1756 */ 1757 struct ice_aqc_lldp_get_mib { 1758 u8 type; 1759 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1760 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1761 #define ICE_AQ_LLDP_MIB_LOCAL 0 1762 #define ICE_AQ_LLDP_MIB_REMOTE 1 1763 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1764 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1765 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1766 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1767 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1768 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1769 #define ICE_AQ_LLDP_TX_S 0x4 1770 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1771 #define ICE_AQ_LLDP_TX_ACTIVE 0 1772 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1773 #define ICE_AQ_LLDP_TX_FLUSHED 3 1774 /* DCBX mode */ 1775 #define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6) 1776 #define ICE_AQ_LLDP_DCBX_NA 0 1777 #define ICE_AQ_LLDP_DCBX_CEE 1 1778 #define ICE_AQ_LLDP_DCBX_IEEE 2 1779 1780 u8 state; 1781 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M BIT(0) 1782 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 1783 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 1784 1785 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1786 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1787 * Get LLDP MIB (0x0A00) response only. 1788 */ 1789 __le16 local_len; 1790 __le16 remote_len; 1791 u8 reserved[2]; 1792 __le32 addr_high; 1793 __le32 addr_low; 1794 }; 1795 1796 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1797 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1798 struct ice_aqc_lldp_set_mib_change { 1799 u8 command; 1800 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1801 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1802 #define ICE_AQ_LLDP_MIB_PENDING_M BIT(1) 1803 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 1804 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 1805 u8 reserved[15]; 1806 }; 1807 1808 /* Stop LLDP (direct 0x0A05) */ 1809 struct ice_aqc_lldp_stop { 1810 u8 command; 1811 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1812 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1813 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1814 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1815 u8 reserved[15]; 1816 }; 1817 1818 /* Start LLDP (direct 0x0A06) */ 1819 struct ice_aqc_lldp_start { 1820 u8 command; 1821 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1822 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1823 u8 reserved[15]; 1824 }; 1825 1826 /* Get CEE DCBX Oper Config (0x0A07) 1827 * The command uses the generic descriptor struct and 1828 * returns the struct below as an indirect response. 1829 */ 1830 struct ice_aqc_get_cee_dcb_cfg_resp { 1831 u8 oper_num_tc; 1832 u8 oper_prio_tc[4]; 1833 u8 oper_tc_bw[8]; 1834 u8 oper_pfc_en; 1835 __le16 oper_app_prio; 1836 #define ICE_AQC_CEE_APP_FCOE_S 0 1837 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1838 #define ICE_AQC_CEE_APP_ISCSI_S 3 1839 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1840 #define ICE_AQC_CEE_APP_FIP_S 8 1841 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1842 __le32 tlv_status; 1843 #define ICE_AQC_CEE_PG_STATUS_S 0 1844 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1845 #define ICE_AQC_CEE_PFC_STATUS_S 3 1846 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1847 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1848 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1849 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1850 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1851 #define ICE_AQC_CEE_FIP_STATUS_S 16 1852 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1853 u8 reserved[12]; 1854 }; 1855 1856 /* Set Local LLDP MIB (indirect 0x0A08) 1857 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1858 */ 1859 struct ice_aqc_lldp_set_local_mib { 1860 u8 type; 1861 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1862 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1863 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1864 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1865 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1866 u8 reserved0; 1867 __le16 length; 1868 u8 reserved1[4]; 1869 __le32 addr_high; 1870 __le32 addr_low; 1871 }; 1872 1873 /* Stop/Start LLDP Agent (direct 0x0A09) 1874 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1875 * The same structure is used for the response, with the command field 1876 * being used as the status field. 1877 */ 1878 struct ice_aqc_lldp_stop_start_specific_agent { 1879 u8 command; 1880 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1881 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1882 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1883 u8 reserved[15]; 1884 }; 1885 1886 /* LLDP Filter Control (direct 0x0A0A) */ 1887 struct ice_aqc_lldp_filter_ctrl { 1888 u8 cmd_flags; 1889 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1890 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1891 u8 reserved1; 1892 __le16 vsi_num; 1893 u8 reserved2[12]; 1894 }; 1895 1896 #define ICE_AQC_RSS_VSI_VALID BIT(15) 1897 1898 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1899 struct ice_aqc_get_set_rss_key { 1900 __le16 vsi_id; 1901 u8 reserved[6]; 1902 __le32 addr_high; 1903 __le32 addr_low; 1904 }; 1905 1906 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1907 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1908 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1909 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1910 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1911 1912 struct ice_aqc_get_set_rss_keys { 1913 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1914 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1915 }; 1916 1917 enum ice_lut_type { 1918 ICE_LUT_VSI = 0, 1919 ICE_LUT_PF = 1, 1920 ICE_LUT_GLOBAL = 2, 1921 }; 1922 1923 enum ice_lut_size { 1924 ICE_LUT_VSI_SIZE = 64, 1925 ICE_LUT_GLOBAL_SIZE = 512, 1926 ICE_LUT_PF_SIZE = 2048, 1927 }; 1928 1929 /* enum ice_aqc_lut_flags combines constants used to fill 1930 * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID, 1931 * LUT size and LUT type, last of which does not need neither shift nor mask. 1932 */ 1933 enum ice_aqc_lut_flags { 1934 ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */ 1935 ICE_AQC_LUT_SIZE_512 = BIT(2), 1936 ICE_AQC_LUT_SIZE_2K = BIT(3), 1937 1938 ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4), 1939 }; 1940 1941 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1942 struct ice_aqc_get_set_rss_lut { 1943 __le16 vsi_id; 1944 __le16 flags; 1945 __le32 reserved; 1946 __le32 addr_high; 1947 __le32 addr_low; 1948 }; 1949 1950 /* Sideband Control Interface Commands */ 1951 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 1952 struct ice_aqc_neigh_dev_req { 1953 __le16 sb_data_len; 1954 u8 reserved[6]; 1955 __le32 addr_high; 1956 __le32 addr_low; 1957 }; 1958 1959 /* Add Tx LAN Queues (indirect 0x0C30) */ 1960 struct ice_aqc_add_txqs { 1961 u8 num_qgrps; 1962 u8 reserved[3]; 1963 __le32 reserved1; 1964 __le32 addr_high; 1965 __le32 addr_low; 1966 }; 1967 1968 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1969 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1970 */ 1971 struct ice_aqc_add_txqs_perq { 1972 __le16 txq_id; 1973 u8 rsvd[2]; 1974 __le32 q_teid; 1975 u8 txq_ctx[22]; 1976 u8 rsvd2[2]; 1977 struct ice_aqc_txsched_elem info; 1978 }; 1979 1980 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1981 * is an array of the following structs. Please note that the length of 1982 * each struct ice_aqc_add_tx_qgrp is variable due 1983 * to the variable number of queues in each group! 1984 */ 1985 struct ice_aqc_add_tx_qgrp { 1986 __le32 parent_teid; 1987 u8 num_txqs; 1988 u8 rsvd[3]; 1989 struct ice_aqc_add_txqs_perq txqs[]; 1990 }; 1991 1992 /* Disable Tx LAN Queues (indirect 0x0C31) */ 1993 struct ice_aqc_dis_txqs { 1994 u8 cmd_type; 1995 #define ICE_AQC_Q_DIS_CMD_S 0 1996 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1997 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1998 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1999 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2000 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2001 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2002 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2003 u8 num_entries; 2004 __le16 vmvf_and_timeout; 2005 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2006 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2007 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2008 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2009 __le32 blocked_cgds; 2010 __le32 addr_high; 2011 __le32 addr_low; 2012 }; 2013 2014 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2015 * contains the following structures, arrayed one after the 2016 * other. 2017 * Note: Since the q_id is 16 bits wide, if the 2018 * number of queues is even, then 2 bytes of alignment MUST be 2019 * added before the start of the next group, to allow correct 2020 * alignment of the parent_teid field. 2021 */ 2022 struct ice_aqc_dis_txq_item { 2023 __le32 parent_teid; 2024 u8 num_qs; 2025 u8 rsvd; 2026 /* The length of the q_id array varies according to num_qs */ 2027 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2028 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2029 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2030 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2031 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2032 __le16 q_id[]; 2033 } __packed; 2034 2035 /* Move/Reconfigure Tx queue (indirect 0x0C32) */ 2036 struct ice_aqc_cfg_txqs { 2037 u8 cmd_type; 2038 #define ICE_AQC_Q_CFG_MOVE_NODE 0x1 2039 #define ICE_AQC_Q_CFG_TC_CHNG 0x2 2040 #define ICE_AQC_Q_CFG_MOVE_TC_CHNG 0x3 2041 #define ICE_AQC_Q_CFG_SUBSEQ_CALL BIT(2) 2042 #define ICE_AQC_Q_CFG_FLUSH BIT(3) 2043 u8 num_qs; 2044 u8 port_num_chng; 2045 #define ICE_AQC_Q_CFG_SRC_PRT_M 0x7 2046 #define ICE_AQC_Q_CFG_DST_PRT_S 3 2047 #define ICE_AQC_Q_CFG_DST_PRT_M (0x7 << ICE_AQC_Q_CFG_DST_PRT_S) 2048 u8 time_out; 2049 #define ICE_AQC_Q_CFG_TIMEOUT_S 2 2050 #define ICE_AQC_Q_CFG_TIMEOUT_M (0x1F << ICE_AQC_Q_CFG_TIMEOUT_S) 2051 __le32 blocked_cgds; 2052 __le32 addr_high; 2053 __le32 addr_low; 2054 }; 2055 2056 /* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2057 struct ice_aqc_cfg_txq_perq { 2058 __le16 q_handle; 2059 u8 tc; 2060 u8 rsvd; 2061 __le32 q_teid; 2062 }; 2063 2064 /* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2065 struct ice_aqc_cfg_txqs_buf { 2066 __le32 src_parent_teid; 2067 __le32 dst_parent_teid; 2068 struct ice_aqc_cfg_txq_perq queue_info[]; 2069 }; 2070 2071 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 2072 struct ice_aqc_add_rdma_qset { 2073 u8 num_qset_grps; 2074 u8 reserved[7]; 2075 __le32 addr_high; 2076 __le32 addr_low; 2077 }; 2078 2079 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 2080 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 2081 */ 2082 struct ice_aqc_add_tx_rdma_qset_entry { 2083 __le16 tx_qset_id; 2084 u8 rsvd[2]; 2085 __le32 qset_teid; 2086 struct ice_aqc_txsched_elem info; 2087 }; 2088 2089 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 2090 * is an array of the following structs. Please note that the length of 2091 * each struct ice_aqc_add_rdma_qset is variable due to the variable 2092 * number of queues in each group! 2093 */ 2094 struct ice_aqc_add_rdma_qset_data { 2095 __le32 parent_teid; 2096 __le16 num_qsets; 2097 u8 rsvd[2]; 2098 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 2099 }; 2100 2101 /* Download Package (indirect 0x0C40) */ 2102 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ 2103 struct ice_aqc_download_pkg { 2104 u8 flags; 2105 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2106 u8 reserved[3]; 2107 __le32 reserved1; 2108 __le32 addr_high; 2109 __le32 addr_low; 2110 }; 2111 2112 struct ice_aqc_download_pkg_resp { 2113 __le32 error_offset; 2114 __le32 error_info; 2115 __le32 addr_high; 2116 __le32 addr_low; 2117 }; 2118 2119 /* Get Package Info List (indirect 0x0C43) */ 2120 struct ice_aqc_get_pkg_info_list { 2121 __le32 reserved1; 2122 __le32 reserved2; 2123 __le32 addr_high; 2124 __le32 addr_low; 2125 }; 2126 2127 /* Version format for packages */ 2128 struct ice_pkg_ver { 2129 u8 major; 2130 u8 minor; 2131 u8 update; 2132 u8 draft; 2133 }; 2134 2135 #define ICE_PKG_NAME_SIZE 32 2136 #define ICE_SEG_ID_SIZE 28 2137 #define ICE_SEG_NAME_SIZE 28 2138 2139 struct ice_aqc_get_pkg_info { 2140 struct ice_pkg_ver ver; 2141 char name[ICE_SEG_NAME_SIZE]; 2142 __le32 track_id; 2143 u8 is_in_nvm; 2144 u8 is_active; 2145 u8 is_active_at_boot; 2146 u8 is_modified; 2147 }; 2148 2149 /* Get Package Info List response buffer format (0x0C43) */ 2150 struct ice_aqc_get_pkg_info_resp { 2151 __le32 count; 2152 struct ice_aqc_get_pkg_info pkg_info[]; 2153 }; 2154 2155 /* Get CGU abilities command response data structure (indirect 0x0C61) */ 2156 struct ice_aqc_get_cgu_abilities { 2157 u8 num_inputs; 2158 u8 num_outputs; 2159 u8 pps_dpll_idx; 2160 u8 eec_dpll_idx; 2161 __le32 max_in_freq; 2162 __le32 max_in_phase_adj; 2163 __le32 max_out_freq; 2164 __le32 max_out_phase_adj; 2165 u8 cgu_part_num; 2166 u8 rsvd[3]; 2167 }; 2168 2169 /* Set CGU input config (direct 0x0C62) */ 2170 struct ice_aqc_set_cgu_input_config { 2171 u8 input_idx; 2172 u8 flags1; 2173 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6) 2174 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7) 2175 u8 flags2; 2176 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2177 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2178 u8 rsvd; 2179 __le32 freq; 2180 __le32 phase_delay; 2181 u8 rsvd2[2]; 2182 __le16 node_handle; 2183 }; 2184 2185 /* Get CGU input config response descriptor structure (direct 0x0C63) */ 2186 struct ice_aqc_get_cgu_input_config { 2187 u8 input_idx; 2188 u8 status; 2189 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS BIT(0) 2190 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1) 2191 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2) 2192 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3) 2193 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4) 2194 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6) 2195 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7) 2196 u8 type; 2197 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0) 2198 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS BIT(4) 2199 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5) 2200 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY BIT(6) 2201 u8 flags1; 2202 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0) 2203 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2) 2204 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3) 2205 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7) 2206 __le32 freq; 2207 __le32 phase_delay; 2208 u8 flags2; 2209 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2210 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2211 u8 rsvd[1]; 2212 __le16 node_handle; 2213 }; 2214 2215 /* Set CGU output config (direct 0x0C64) */ 2216 struct ice_aqc_set_cgu_output_config { 2217 u8 output_idx; 2218 u8 flags; 2219 #define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN BIT(0) 2220 #define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2221 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2) 2222 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3) 2223 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4) 2224 u8 src_sel; 2225 #define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0) 2226 u8 rsvd; 2227 __le32 freq; 2228 __le32 phase_delay; 2229 u8 rsvd2[2]; 2230 __le16 node_handle; 2231 }; 2232 2233 /* Get CGU output config (direct 0x0C65) */ 2234 struct ice_aqc_get_cgu_output_config { 2235 u8 output_idx; 2236 u8 flags; 2237 #define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN BIT(0) 2238 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2239 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2) 2240 u8 src_sel; 2241 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0 2242 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \ 2243 ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT) 2244 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5 2245 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \ 2246 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT) 2247 u8 rsvd; 2248 __le32 freq; 2249 __le32 src_freq; 2250 u8 rsvd2[2]; 2251 __le16 node_handle; 2252 }; 2253 2254 /* Get CGU DPLL status (direct 0x0C66) */ 2255 struct ice_aqc_get_cgu_dpll_status { 2256 u8 dpll_num; 2257 u8 ref_state; 2258 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0) 2259 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1) 2260 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2) 2261 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3) 2262 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4) 2263 #define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5) 2264 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6) 2265 u8 dpll_state; 2266 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0) 2267 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO BIT(1) 2268 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2) 2269 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5) 2270 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7) 2271 u8 config; 2272 #define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2273 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2274 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE \ 2275 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2276 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2277 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2278 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2279 __le32 phase_offset_h; 2280 __le32 phase_offset_l; 2281 u8 eec_mode; 2282 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA 2283 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB 2284 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF 2285 u8 rsvd[1]; 2286 __le16 node_handle; 2287 }; 2288 2289 /* Set CGU DPLL config (direct 0x0C67) */ 2290 struct ice_aqc_set_cgu_dpll_config { 2291 u8 dpll_num; 2292 u8 ref_state; 2293 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0) 2294 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1) 2295 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2) 2296 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3) 2297 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4) 2298 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5) 2299 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6) 2300 u8 rsvd; 2301 u8 config; 2302 #define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2303 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2304 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE \ 2305 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2306 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2307 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2308 ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2309 u8 rsvd2[8]; 2310 u8 eec_mode; 2311 u8 rsvd3[1]; 2312 __le16 node_handle; 2313 }; 2314 2315 /* Set CGU reference priority (direct 0x0C68) */ 2316 struct ice_aqc_set_cgu_ref_prio { 2317 u8 dpll_num; 2318 u8 ref_idx; 2319 u8 ref_priority; 2320 u8 rsvd[11]; 2321 __le16 node_handle; 2322 }; 2323 2324 /* Get CGU reference priority (direct 0x0C69) */ 2325 struct ice_aqc_get_cgu_ref_prio { 2326 u8 dpll_num; 2327 u8 ref_idx; 2328 u8 ref_priority; /* Valid only in response */ 2329 u8 rsvd[13]; 2330 }; 2331 2332 /* Get CGU info (direct 0x0C6A) */ 2333 struct ice_aqc_get_cgu_info { 2334 __le32 cgu_id; 2335 __le32 cgu_cfg_ver; 2336 __le32 cgu_fw_ver; 2337 u8 node_part_num; 2338 u8 dev_rev; 2339 __le16 node_handle; 2340 }; 2341 2342 /* Driver Shared Parameters (direct, 0x0C90) */ 2343 struct ice_aqc_driver_shared_params { 2344 u8 set_or_get_op; 2345 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2346 #define ICE_AQC_DRIVER_PARAM_SET 0 2347 #define ICE_AQC_DRIVER_PARAM_GET 1 2348 u8 param_indx; 2349 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2350 u8 rsvd[2]; 2351 __le32 param_val; 2352 __le32 addr_high; 2353 __le32 addr_low; 2354 }; 2355 2356 /* Lan Queue Overflow Event (direct, 0x1001) */ 2357 struct ice_aqc_event_lan_overflow { 2358 __le32 prtdcb_ruptq; 2359 __le32 qtx_ctl; 2360 u8 reserved[8]; 2361 }; 2362 2363 enum ice_aqc_fw_logging_mod { 2364 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2365 ICE_AQC_FW_LOG_ID_CTRL, 2366 ICE_AQC_FW_LOG_ID_LINK, 2367 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2368 ICE_AQC_FW_LOG_ID_DNL, 2369 ICE_AQC_FW_LOG_ID_I2C, 2370 ICE_AQC_FW_LOG_ID_SDP, 2371 ICE_AQC_FW_LOG_ID_MDIO, 2372 ICE_AQC_FW_LOG_ID_ADMINQ, 2373 ICE_AQC_FW_LOG_ID_HDMA, 2374 ICE_AQC_FW_LOG_ID_LLDP, 2375 ICE_AQC_FW_LOG_ID_DCBX, 2376 ICE_AQC_FW_LOG_ID_DCB, 2377 ICE_AQC_FW_LOG_ID_XLR, 2378 ICE_AQC_FW_LOG_ID_NVM, 2379 ICE_AQC_FW_LOG_ID_AUTH, 2380 ICE_AQC_FW_LOG_ID_VPD, 2381 ICE_AQC_FW_LOG_ID_IOSF, 2382 ICE_AQC_FW_LOG_ID_PARSER, 2383 ICE_AQC_FW_LOG_ID_SW, 2384 ICE_AQC_FW_LOG_ID_SCHEDULER, 2385 ICE_AQC_FW_LOG_ID_TXQ, 2386 ICE_AQC_FW_LOG_ID_RSVD, 2387 ICE_AQC_FW_LOG_ID_POST, 2388 ICE_AQC_FW_LOG_ID_WATCHDOG, 2389 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 2390 ICE_AQC_FW_LOG_ID_MNG, 2391 ICE_AQC_FW_LOG_ID_SYNCE, 2392 ICE_AQC_FW_LOG_ID_HEALTH, 2393 ICE_AQC_FW_LOG_ID_TSDRV, 2394 ICE_AQC_FW_LOG_ID_PFREG, 2395 ICE_AQC_FW_LOG_ID_MDLVER, 2396 ICE_AQC_FW_LOG_ID_MAX, 2397 }; 2398 2399 /* Set FW Logging configuration (indirect 0xFF30) 2400 * Register for FW Logging (indirect 0xFF31) 2401 * Query FW Logging (indirect 0xFF32) 2402 * FW Log Event (indirect 0xFF33) 2403 */ 2404 struct ice_aqc_fw_log { 2405 u8 cmd_flags; 2406 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 2407 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 2408 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2) 2409 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 2410 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 2411 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 2412 2413 u8 rsp_flag; 2414 __le16 fw_rt_msb; 2415 union { 2416 struct { 2417 __le32 fw_rt_lsb; 2418 } sync; 2419 struct { 2420 __le16 log_resolution; 2421 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 2422 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 2423 2424 __le16 mdl_cnt; 2425 } cfg; 2426 } ops; 2427 __le32 addr_high; 2428 __le32 addr_low; 2429 }; 2430 2431 /* Response Buffer for: 2432 * Set Firmware Logging Configuration (0xFF30) 2433 * Query FW Logging (0xFF32) 2434 */ 2435 struct ice_aqc_fw_log_cfg_resp { 2436 __le16 module_identifier; 2437 u8 log_level; 2438 u8 rsvd0; 2439 }; 2440 2441 /** 2442 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2443 * @flags: ICE_AQ_FLAG_* flags 2444 * @opcode: AQ command opcode 2445 * @datalen: length in bytes of indirect/external data buffer 2446 * @retval: return value from firmware 2447 * @cookie_high: opaque data high-half 2448 * @cookie_low: opaque data low-half 2449 * @params: command-specific parameters 2450 * 2451 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2452 * (ATQ). The firmware writes back onto the command descriptor and returns 2453 * the result of the command. Asynchronous events that are not an immediate 2454 * result of the command are written to the Admin Receive Queue (ARQ) using 2455 * the same descriptor format. Descriptors are in little-endian notation with 2456 * 32-bit words. 2457 */ 2458 struct ice_aq_desc { 2459 __le16 flags; 2460 __le16 opcode; 2461 __le16 datalen; 2462 __le16 retval; 2463 __le32 cookie_high; 2464 __le32 cookie_low; 2465 union { 2466 u8 raw[16]; 2467 struct ice_aqc_generic generic; 2468 struct ice_aqc_get_ver get_ver; 2469 struct ice_aqc_driver_ver driver_ver; 2470 struct ice_aqc_q_shutdown q_shutdown; 2471 struct ice_aqc_req_res res_owner; 2472 struct ice_aqc_manage_mac_read mac_read; 2473 struct ice_aqc_manage_mac_write mac_write; 2474 struct ice_aqc_clear_pxe clear_pxe; 2475 struct ice_aqc_list_caps get_cap; 2476 struct ice_aqc_get_phy_caps get_phy; 2477 struct ice_aqc_set_phy_cfg set_phy; 2478 struct ice_aqc_restart_an restart_an; 2479 struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out; 2480 struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out; 2481 struct ice_aqc_get_sensor_reading get_sensor_reading; 2482 struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp; 2483 struct ice_aqc_gpio read_write_gpio; 2484 struct ice_aqc_sff_eeprom read_write_sff_param; 2485 struct ice_aqc_set_port_id_led set_port_id_led; 2486 struct ice_aqc_get_port_options get_port_options; 2487 struct ice_aqc_set_port_option set_port_option; 2488 struct ice_aqc_get_sw_cfg get_sw_conf; 2489 struct ice_aqc_set_port_params set_port_params; 2490 struct ice_aqc_sw_rules sw_rules; 2491 struct ice_aqc_add_get_recipe add_get_recipe; 2492 struct ice_aqc_recipe_to_profile recipe_to_profile; 2493 struct ice_aqc_get_topo get_topo; 2494 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2495 struct ice_aqc_query_txsched_res query_sched_res; 2496 struct ice_aqc_query_port_ets port_ets; 2497 struct ice_aqc_rl_profile rl_profile; 2498 struct ice_aqc_nvm nvm; 2499 struct ice_aqc_nvm_checksum nvm_checksum; 2500 struct ice_aqc_nvm_pkg_data pkg_data; 2501 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl; 2502 struct ice_aqc_pf_vf_msg virt; 2503 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2504 struct ice_aqc_lldp_get_mib lldp_get_mib; 2505 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2506 struct ice_aqc_lldp_stop lldp_stop; 2507 struct ice_aqc_lldp_start lldp_start; 2508 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2509 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2510 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2511 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2512 struct ice_aqc_get_set_rss_key get_set_rss_key; 2513 struct ice_aqc_neigh_dev_req neigh_dev; 2514 struct ice_aqc_add_txqs add_txqs; 2515 struct ice_aqc_dis_txqs dis_txqs; 2516 struct ice_aqc_cfg_txqs cfg_txqs; 2517 struct ice_aqc_add_rdma_qset add_rdma_qset; 2518 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2519 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2520 struct ice_aqc_download_pkg download_pkg; 2521 struct ice_aqc_set_cgu_input_config set_cgu_input_config; 2522 struct ice_aqc_get_cgu_input_config get_cgu_input_config; 2523 struct ice_aqc_set_cgu_output_config set_cgu_output_config; 2524 struct ice_aqc_get_cgu_output_config get_cgu_output_config; 2525 struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status; 2526 struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config; 2527 struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio; 2528 struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio; 2529 struct ice_aqc_get_cgu_info get_cgu_info; 2530 struct ice_aqc_driver_shared_params drv_shared_params; 2531 struct ice_aqc_fw_log fw_log; 2532 struct ice_aqc_set_mac_lb set_mac_lb; 2533 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2534 struct ice_aqc_set_mac_cfg set_mac_cfg; 2535 struct ice_aqc_set_event_mask set_event_mask; 2536 struct ice_aqc_get_link_status get_link_status; 2537 struct ice_aqc_event_lan_overflow lan_overflow; 2538 struct ice_aqc_get_link_topo get_link_topo; 2539 struct ice_aqc_i2c read_write_i2c; 2540 struct ice_aqc_read_i2c_resp read_i2c_resp; 2541 } params; 2542 }; 2543 2544 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2545 #define ICE_AQ_LG_BUF 512 2546 2547 #define ICE_AQ_FLAG_ERR_S 2 2548 #define ICE_AQ_FLAG_LB_S 9 2549 #define ICE_AQ_FLAG_RD_S 10 2550 #define ICE_AQ_FLAG_BUF_S 12 2551 #define ICE_AQ_FLAG_SI_S 13 2552 2553 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2554 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2555 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2556 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2557 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2558 2559 /* error codes */ 2560 enum ice_aq_err { 2561 ICE_AQ_RC_OK = 0, /* Success */ 2562 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2563 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2564 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2565 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2566 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2567 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2568 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2569 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2570 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2571 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2572 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2573 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2574 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2575 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2576 }; 2577 2578 /* Admin Queue command opcodes */ 2579 enum ice_adminq_opc { 2580 /* AQ commands */ 2581 ice_aqc_opc_get_ver = 0x0001, 2582 ice_aqc_opc_driver_ver = 0x0002, 2583 ice_aqc_opc_q_shutdown = 0x0003, 2584 2585 /* resource ownership */ 2586 ice_aqc_opc_req_res = 0x0008, 2587 ice_aqc_opc_release_res = 0x0009, 2588 2589 /* device/function capabilities */ 2590 ice_aqc_opc_list_func_caps = 0x000A, 2591 ice_aqc_opc_list_dev_caps = 0x000B, 2592 2593 /* manage MAC address */ 2594 ice_aqc_opc_manage_mac_read = 0x0107, 2595 ice_aqc_opc_manage_mac_write = 0x0108, 2596 2597 /* PXE */ 2598 ice_aqc_opc_clear_pxe_mode = 0x0110, 2599 2600 /* internal switch commands */ 2601 ice_aqc_opc_get_sw_cfg = 0x0200, 2602 ice_aqc_opc_set_port_params = 0x0203, 2603 2604 /* Alloc/Free/Get Resources */ 2605 ice_aqc_opc_alloc_res = 0x0208, 2606 ice_aqc_opc_free_res = 0x0209, 2607 ice_aqc_opc_share_res = 0x020B, 2608 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 2609 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 2610 2611 /* VSI commands */ 2612 ice_aqc_opc_add_vsi = 0x0210, 2613 ice_aqc_opc_update_vsi = 0x0211, 2614 ice_aqc_opc_free_vsi = 0x0213, 2615 2616 /* recipe commands */ 2617 ice_aqc_opc_add_recipe = 0x0290, 2618 ice_aqc_opc_recipe_to_profile = 0x0291, 2619 ice_aqc_opc_get_recipe = 0x0292, 2620 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2621 2622 /* switch rules population commands */ 2623 ice_aqc_opc_add_sw_rules = 0x02A0, 2624 ice_aqc_opc_update_sw_rules = 0x02A1, 2625 ice_aqc_opc_remove_sw_rules = 0x02A2, 2626 2627 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2628 2629 /* DCB commands */ 2630 ice_aqc_opc_query_pfc_mode = 0x0302, 2631 ice_aqc_opc_set_pfc_mode = 0x0303, 2632 2633 /* transmit scheduler commands */ 2634 ice_aqc_opc_get_dflt_topo = 0x0400, 2635 ice_aqc_opc_add_sched_elems = 0x0401, 2636 ice_aqc_opc_cfg_sched_elems = 0x0403, 2637 ice_aqc_opc_get_sched_elems = 0x0404, 2638 ice_aqc_opc_move_sched_elems = 0x0408, 2639 ice_aqc_opc_suspend_sched_elems = 0x0409, 2640 ice_aqc_opc_resume_sched_elems = 0x040A, 2641 ice_aqc_opc_query_port_ets = 0x040E, 2642 ice_aqc_opc_delete_sched_elems = 0x040F, 2643 ice_aqc_opc_add_rl_profiles = 0x0410, 2644 ice_aqc_opc_query_sched_res = 0x0412, 2645 ice_aqc_opc_remove_rl_profiles = 0x0415, 2646 2647 /* PHY commands */ 2648 ice_aqc_opc_get_phy_caps = 0x0600, 2649 ice_aqc_opc_set_phy_cfg = 0x0601, 2650 ice_aqc_opc_set_mac_cfg = 0x0603, 2651 ice_aqc_opc_restart_an = 0x0605, 2652 ice_aqc_opc_get_link_status = 0x0607, 2653 ice_aqc_opc_set_event_mask = 0x0613, 2654 ice_aqc_opc_set_mac_lb = 0x0620, 2655 ice_aqc_opc_set_phy_rec_clk_out = 0x0630, 2656 ice_aqc_opc_get_phy_rec_clk_out = 0x0631, 2657 ice_aqc_opc_get_sensor_reading = 0x0632, 2658 ice_aqc_opc_get_link_topo = 0x06E0, 2659 ice_aqc_opc_read_i2c = 0x06E2, 2660 ice_aqc_opc_write_i2c = 0x06E3, 2661 ice_aqc_opc_set_port_id_led = 0x06E9, 2662 ice_aqc_opc_get_port_options = 0x06EA, 2663 ice_aqc_opc_set_port_option = 0x06EB, 2664 ice_aqc_opc_set_gpio = 0x06EC, 2665 ice_aqc_opc_get_gpio = 0x06ED, 2666 ice_aqc_opc_sff_eeprom = 0x06EE, 2667 2668 /* NVM commands */ 2669 ice_aqc_opc_nvm_read = 0x0701, 2670 ice_aqc_opc_nvm_erase = 0x0702, 2671 ice_aqc_opc_nvm_write = 0x0703, 2672 ice_aqc_opc_nvm_checksum = 0x0706, 2673 ice_aqc_opc_nvm_write_activate = 0x0707, 2674 ice_aqc_opc_nvm_update_empr = 0x0709, 2675 ice_aqc_opc_nvm_pkg_data = 0x070A, 2676 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2677 2678 /* PF/VF mailbox commands */ 2679 ice_mbx_opc_send_msg_to_pf = 0x0801, 2680 ice_mbx_opc_send_msg_to_vf = 0x0802, 2681 /* LLDP commands */ 2682 ice_aqc_opc_lldp_get_mib = 0x0A00, 2683 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2684 ice_aqc_opc_lldp_stop = 0x0A05, 2685 ice_aqc_opc_lldp_start = 0x0A06, 2686 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2687 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2688 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2689 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2690 ice_aqc_opc_lldp_execute_pending_mib = 0x0A0B, 2691 2692 /* RSS commands */ 2693 ice_aqc_opc_set_rss_key = 0x0B02, 2694 ice_aqc_opc_set_rss_lut = 0x0B03, 2695 ice_aqc_opc_get_rss_key = 0x0B04, 2696 ice_aqc_opc_get_rss_lut = 0x0B05, 2697 2698 /* Sideband Control Interface commands */ 2699 ice_aqc_opc_neighbour_device_request = 0x0C00, 2700 2701 /* Tx queue handling commands/events */ 2702 ice_aqc_opc_add_txqs = 0x0C30, 2703 ice_aqc_opc_dis_txqs = 0x0C31, 2704 ice_aqc_opc_cfg_txqs = 0x0C32, 2705 ice_aqc_opc_add_rdma_qset = 0x0C33, 2706 2707 /* package commands */ 2708 ice_aqc_opc_download_pkg = 0x0C40, 2709 ice_aqc_opc_upload_section = 0x0C41, 2710 ice_aqc_opc_update_pkg = 0x0C42, 2711 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2712 2713 /* 1588/SyncE commands/events */ 2714 ice_aqc_opc_get_cgu_abilities = 0x0C61, 2715 ice_aqc_opc_set_cgu_input_config = 0x0C62, 2716 ice_aqc_opc_get_cgu_input_config = 0x0C63, 2717 ice_aqc_opc_set_cgu_output_config = 0x0C64, 2718 ice_aqc_opc_get_cgu_output_config = 0x0C65, 2719 ice_aqc_opc_get_cgu_dpll_status = 0x0C66, 2720 ice_aqc_opc_set_cgu_dpll_config = 0x0C67, 2721 ice_aqc_opc_set_cgu_ref_prio = 0x0C68, 2722 ice_aqc_opc_get_cgu_ref_prio = 0x0C69, 2723 ice_aqc_opc_get_cgu_info = 0x0C6A, 2724 2725 ice_aqc_opc_driver_shared_params = 0x0C90, 2726 2727 /* Standalone Commands/Events */ 2728 ice_aqc_opc_event_lan_overflow = 0x1001, 2729 2730 /* FW Logging Commands */ 2731 ice_aqc_opc_fw_logs_config = 0xFF30, 2732 ice_aqc_opc_fw_logs_register = 0xFF31, 2733 ice_aqc_opc_fw_logs_query = 0xFF32, 2734 ice_aqc_opc_fw_logs_event = 0xFF33, 2735 }; 2736 2737 #endif /* _ICE_ADMINQ_CMD_H_ */ 2738