1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _IAVF_TXRX_H_ 5 #define _IAVF_TXRX_H_ 6 7 /* Interrupt Throttling and Rate Limiting Goodies */ 8 #define IAVF_DEFAULT_IRQ_WORK 256 9 10 /* The datasheet for the X710 and XL710 indicate that the maximum value for 11 * the ITR is 8160usec which is then called out as 0xFF0 with a 2usec 12 * resolution. 8160 is 0x1FE0 when written out in hex. So instead of storing 13 * the register value which is divided by 2 lets use the actual values and 14 * avoid an excessive amount of translation. 15 */ 16 #define IAVF_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 17 #define IAVF_ITR_MASK 0x1FFE /* mask for ITR register value */ 18 #define IAVF_ITR_100K 10 /* all values below must be even */ 19 #define IAVF_ITR_50K 20 20 #define IAVF_ITR_20K 50 21 #define IAVF_ITR_18K 60 22 #define IAVF_ITR_8K 122 23 #define IAVF_MAX_ITR 8160 /* maximum value as per datasheet */ 24 #define ITR_TO_REG(setting) ((setting) & ~IAVF_ITR_DYNAMIC) 25 #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~IAVF_ITR_MASK) 26 #define ITR_IS_DYNAMIC(setting) (!!((setting) & IAVF_ITR_DYNAMIC)) 27 28 #define IAVF_ITR_RX_DEF (IAVF_ITR_20K | IAVF_ITR_DYNAMIC) 29 #define IAVF_ITR_TX_DEF (IAVF_ITR_20K | IAVF_ITR_DYNAMIC) 30 31 /* 0x40 is the enable bit for interrupt rate limiting, and must be set if 32 * the value of the rate limit is non-zero 33 */ 34 #define INTRL_ENA BIT(6) 35 #define IAVF_MAX_INTRL 0x3B /* reg uses 4 usec resolution */ 36 #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2) 37 #define INTRL_USEC_TO_REG(set) ((set) ? ((set) >> 2) | INTRL_ENA : 0) 38 #define IAVF_INTRL_8K 125 /* 8000 ints/sec */ 39 #define IAVF_INTRL_62K 16 /* 62500 ints/sec */ 40 #define IAVF_INTRL_83K 12 /* 83333 ints/sec */ 41 42 #define IAVF_QUEUE_END_OF_LIST 0x7FF 43 44 /* this enum matches hardware bits and is meant to be used by DYN_CTLN 45 * registers and QINT registers or more generally anywhere in the manual 46 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 47 * register but instead is a special value meaning "don't update" ITR0/1/2. 48 */ 49 enum iavf_dyn_idx_t { 50 IAVF_IDX_ITR0 = 0, 51 IAVF_IDX_ITR1 = 1, 52 IAVF_IDX_ITR2 = 2, 53 IAVF_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 54 }; 55 56 /* these are indexes into ITRN registers */ 57 #define IAVF_RX_ITR IAVF_IDX_ITR0 58 #define IAVF_TX_ITR IAVF_IDX_ITR1 59 #define IAVF_PE_ITR IAVF_IDX_ITR2 60 61 /* Supported RSS offloads */ 62 #define IAVF_DEFAULT_RSS_HENA ( \ 63 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 64 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 65 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 66 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 67 BIT_ULL(IAVF_FILTER_PCTYPE_FRAG_IPV4) | \ 68 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 69 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 70 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 71 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 72 BIT_ULL(IAVF_FILTER_PCTYPE_FRAG_IPV6) | \ 73 BIT_ULL(IAVF_FILTER_PCTYPE_L2_PAYLOAD)) 74 75 #define IAVF_DEFAULT_RSS_HENA_EXPANDED (IAVF_DEFAULT_RSS_HENA | \ 76 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 77 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 78 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 79 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 80 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 81 BIT_ULL(IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP)) 82 83 /* Supported Rx Buffer Sizes (a multiple of 128) */ 84 #define IAVF_RXBUFFER_3072 3072 /* Used for large frames w/ padding */ 85 #define IAVF_MAX_RXBUFFER 9728 /* largest size for single descriptor */ 86 87 #define IAVF_PACKET_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) 88 #define iavf_rx_desc iavf_32byte_rx_desc 89 90 #define IAVF_RX_DMA_ATTR \ 91 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 92 93 #define IAVF_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 94 95 /** 96 * iavf_test_staterr - tests bits in Rx descriptor status and error fields 97 * @rx_desc: pointer to receive descriptor (in le64 format) 98 * @stat_err_bits: value to mask 99 * 100 * This function does some fast chicanery in order to return the 101 * value of the mask which is really only used for boolean tests. 102 * The status_error_len doesn't need to be shifted because it begins 103 * at offset zero. 104 */ 105 static inline bool iavf_test_staterr(union iavf_rx_desc *rx_desc, 106 const u64 stat_err_bits) 107 { 108 return !!(rx_desc->wb.qword1.status_error_len & 109 cpu_to_le64(stat_err_bits)); 110 } 111 112 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 113 #define IAVF_RX_INCREMENT(r, i) \ 114 do { \ 115 (i)++; \ 116 if ((i) == (r)->count) \ 117 i = 0; \ 118 r->next_to_clean = i; \ 119 } while (0) 120 121 #define IAVF_RX_NEXT_DESC(r, i, n) \ 122 do { \ 123 (i)++; \ 124 if ((i) == (r)->count) \ 125 i = 0; \ 126 (n) = IAVF_RX_DESC((r), (i)); \ 127 } while (0) 128 129 #define IAVF_RX_NEXT_DESC_PREFETCH(r, i, n) \ 130 do { \ 131 IAVF_RX_NEXT_DESC((r), (i), (n)); \ 132 prefetch((n)); \ 133 } while (0) 134 135 #define IAVF_MAX_BUFFER_TXD 8 136 #define IAVF_MIN_TX_LEN 17 137 138 /* The size limit for a transmit buffer in a descriptor is (16K - 1). 139 * In order to align with the read requests we will align the value to 140 * the nearest 4K which represents our maximum read request size. 141 */ 142 #define IAVF_MAX_READ_REQ_SIZE 4096 143 #define IAVF_MAX_DATA_PER_TXD (16 * 1024 - 1) 144 #define IAVF_MAX_DATA_PER_TXD_ALIGNED \ 145 (IAVF_MAX_DATA_PER_TXD & ~(IAVF_MAX_READ_REQ_SIZE - 1)) 146 147 /** 148 * iavf_txd_use_count - estimate the number of descriptors needed for Tx 149 * @size: transmit request size in bytes 150 * 151 * Due to hardware alignment restrictions (4K alignment), we need to 152 * assume that we can have no more than 12K of data per descriptor, even 153 * though each descriptor can take up to 16K - 1 bytes of aligned memory. 154 * Thus, we need to divide by 12K. But division is slow! Instead, 155 * we decompose the operation into shifts and one relatively cheap 156 * multiply operation. 157 * 158 * To divide by 12K, we first divide by 4K, then divide by 3: 159 * To divide by 4K, shift right by 12 bits 160 * To divide by 3, multiply by 85, then divide by 256 161 * (Divide by 256 is done by shifting right by 8 bits) 162 * Finally, we add one to round up. Because 256 isn't an exact multiple of 163 * 3, we'll underestimate near each multiple of 12K. This is actually more 164 * accurate as we have 4K - 1 of wiggle room that we can fit into the last 165 * segment. For our purposes this is accurate out to 1M which is orders of 166 * magnitude greater than our largest possible GSO size. 167 * 168 * This would then be implemented as: 169 * return (((size >> 12) * 85) >> 8) + 1; 170 * 171 * Since multiplication and division are commutative, we can reorder 172 * operations into: 173 * return ((size * 85) >> 20) + 1; 174 */ 175 static inline unsigned int iavf_txd_use_count(unsigned int size) 176 { 177 return ((size * 85) >> 20) + 1; 178 } 179 180 /* Tx Descriptors needed, worst case */ 181 #define DESC_NEEDED (MAX_SKB_FRAGS + 6) 182 #define IAVF_MIN_DESC_PENDING 4 183 184 #define IAVF_TX_FLAGS_HW_VLAN BIT(1) 185 #define IAVF_TX_FLAGS_SW_VLAN BIT(2) 186 #define IAVF_TX_FLAGS_TSO BIT(3) 187 #define IAVF_TX_FLAGS_IPV4 BIT(4) 188 #define IAVF_TX_FLAGS_IPV6 BIT(5) 189 #define IAVF_TX_FLAGS_FCCRC BIT(6) 190 #define IAVF_TX_FLAGS_FSO BIT(7) 191 #define IAVF_TX_FLAGS_FD_SB BIT(9) 192 #define IAVF_TX_FLAGS_VXLAN_TUNNEL BIT(10) 193 #define IAVF_TX_FLAGS_HW_OUTER_SINGLE_VLAN BIT(11) 194 #define IAVF_TX_FLAGS_VLAN_MASK 0xffff0000 195 #define IAVF_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 196 #define IAVF_TX_FLAGS_VLAN_PRIO_SHIFT 29 197 #define IAVF_TX_FLAGS_VLAN_SHIFT 16 198 199 struct iavf_tx_buffer { 200 struct iavf_tx_desc *next_to_watch; 201 union { 202 struct sk_buff *skb; 203 void *raw_buf; 204 }; 205 unsigned int bytecount; 206 unsigned short gso_segs; 207 208 DEFINE_DMA_UNMAP_ADDR(dma); 209 DEFINE_DMA_UNMAP_LEN(len); 210 u32 tx_flags; 211 }; 212 213 struct iavf_rx_buffer { 214 dma_addr_t dma; 215 struct page *page; 216 __u32 page_offset; 217 }; 218 219 struct iavf_queue_stats { 220 u64 packets; 221 u64 bytes; 222 }; 223 224 struct iavf_tx_queue_stats { 225 u64 restart_queue; 226 u64 tx_busy; 227 u64 tx_done_old; 228 u64 tx_linearize; 229 u64 tx_force_wb; 230 u64 tx_lost_interrupt; 231 }; 232 233 struct iavf_rx_queue_stats { 234 u64 non_eop_descs; 235 u64 alloc_page_failed; 236 u64 alloc_buff_failed; 237 }; 238 239 /* some useful defines for virtchannel interface, which 240 * is the only remaining user of header split 241 */ 242 #define IAVF_RX_DTYPE_NO_SPLIT 0 243 #define IAVF_RX_DTYPE_HEADER_SPLIT 1 244 #define IAVF_RX_DTYPE_SPLIT_ALWAYS 2 245 #define IAVF_RX_SPLIT_L2 0x1 246 #define IAVF_RX_SPLIT_IP 0x2 247 #define IAVF_RX_SPLIT_TCP_UDP 0x4 248 #define IAVF_RX_SPLIT_SCTP 0x8 249 250 /* struct that defines a descriptor ring, associated with a VSI */ 251 struct iavf_ring { 252 struct iavf_ring *next; /* pointer to next ring in q_vector */ 253 void *desc; /* Descriptor ring memory */ 254 struct device *dev; /* Used for DMA mapping */ 255 struct net_device *netdev; /* netdev ring maps to */ 256 union { 257 struct iavf_tx_buffer *tx_bi; 258 struct iavf_rx_buffer *rx_bi; 259 }; 260 u8 __iomem *tail; 261 u16 queue_index; /* Queue number of ring */ 262 263 /* high bit set means dynamic, use accessors routines to read/write. 264 * hardware only supports 2us resolution for the ITR registers. 265 * these values always store the USER setting, and must be converted 266 * before programming to a register. 267 */ 268 u16 itr_setting; 269 270 u16 count; /* Number of descriptors */ 271 272 /* used in interrupt processing */ 273 u16 next_to_use; 274 u16 next_to_clean; 275 276 u16 flags; 277 #define IAVF_TXR_FLAGS_WB_ON_ITR BIT(0) 278 #define IAVF_TXR_FLAGS_ARM_WB BIT(1) 279 /* BIT(2) is free */ 280 #define IAVF_TXRX_FLAGS_VLAN_TAG_LOC_L2TAG1 BIT(3) 281 #define IAVF_TXR_FLAGS_VLAN_TAG_LOC_L2TAG2 BIT(4) 282 #define IAVF_RXR_FLAGS_VLAN_TAG_LOC_L2TAG2_2 BIT(5) 283 284 /* stats structs */ 285 struct iavf_queue_stats stats; 286 struct u64_stats_sync syncp; 287 union { 288 struct iavf_tx_queue_stats tx_stats; 289 struct iavf_rx_queue_stats rx_stats; 290 }; 291 292 int prev_pkt_ctr; /* For Tx stall detection */ 293 unsigned int size; /* length of descriptor ring in bytes */ 294 dma_addr_t dma; /* physical address of ring */ 295 296 struct iavf_vsi *vsi; /* Backreference to associated VSI */ 297 struct iavf_q_vector *q_vector; /* Backreference to associated vector */ 298 299 struct rcu_head rcu; /* to avoid race on free */ 300 struct sk_buff *skb; /* When iavf_clean_rx_ring_irq() must 301 * return before it sees the EOP for 302 * the current packet, we save that skb 303 * here and resume receiving this 304 * packet the next time 305 * iavf_clean_rx_ring_irq() is called 306 * for this ring. 307 */ 308 } ____cacheline_internodealigned_in_smp; 309 310 #define IAVF_ITR_ADAPTIVE_MIN_INC 0x0002 311 #define IAVF_ITR_ADAPTIVE_MIN_USECS 0x0002 312 #define IAVF_ITR_ADAPTIVE_MAX_USECS 0x007e 313 #define IAVF_ITR_ADAPTIVE_LATENCY 0x8000 314 #define IAVF_ITR_ADAPTIVE_BULK 0x0000 315 #define ITR_IS_BULK(x) (!((x) & IAVF_ITR_ADAPTIVE_LATENCY)) 316 317 struct iavf_ring_container { 318 struct iavf_ring *ring; /* pointer to linked list of ring(s) */ 319 unsigned long next_update; /* jiffies value of next update */ 320 unsigned int total_bytes; /* total bytes processed this int */ 321 unsigned int total_packets; /* total packets processed this int */ 322 u16 count; 323 u16 target_itr; /* target ITR setting for ring(s) */ 324 u16 current_itr; /* current ITR setting for ring(s) */ 325 }; 326 327 /* iterator for handling rings in ring container */ 328 #define iavf_for_each_ring(pos, head) \ 329 for (pos = (head).ring; pos != NULL; pos = pos->next) 330 331 static inline unsigned int iavf_rx_pg_order(struct iavf_ring *ring) 332 { 333 return 0; 334 } 335 336 #define iavf_rx_pg_size(_ring) (PAGE_SIZE << iavf_rx_pg_order(_ring)) 337 338 bool iavf_alloc_rx_buffers(struct iavf_ring *rxr, u16 cleaned_count); 339 netdev_tx_t iavf_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 340 int iavf_setup_tx_descriptors(struct iavf_ring *tx_ring); 341 int iavf_setup_rx_descriptors(struct iavf_ring *rx_ring); 342 void iavf_free_tx_resources(struct iavf_ring *tx_ring); 343 void iavf_free_rx_resources(struct iavf_ring *rx_ring); 344 int iavf_napi_poll(struct napi_struct *napi, int budget); 345 void iavf_detect_recover_hung(struct iavf_vsi *vsi); 346 int __iavf_maybe_stop_tx(struct iavf_ring *tx_ring, int size); 347 bool __iavf_chk_linearize(struct sk_buff *skb); 348 349 /** 350 * iavf_xmit_descriptor_count - calculate number of Tx descriptors needed 351 * @skb: send buffer 352 * 353 * Returns number of data descriptors needed for this skb. Returns 0 to indicate 354 * there is not enough descriptors available in this ring since we need at least 355 * one descriptor. 356 **/ 357 static inline int iavf_xmit_descriptor_count(struct sk_buff *skb) 358 { 359 const skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 360 unsigned int nr_frags = skb_shinfo(skb)->nr_frags; 361 int count = 0, size = skb_headlen(skb); 362 363 for (;;) { 364 count += iavf_txd_use_count(size); 365 366 if (!nr_frags--) 367 break; 368 369 size = skb_frag_size(frag++); 370 } 371 372 return count; 373 } 374 375 /** 376 * iavf_maybe_stop_tx - 1st level check for Tx stop conditions 377 * @tx_ring: the ring to be checked 378 * @size: the size buffer we want to assure is available 379 * 380 * Returns 0 if stop is not needed 381 **/ 382 static inline int iavf_maybe_stop_tx(struct iavf_ring *tx_ring, int size) 383 { 384 if (likely(IAVF_DESC_UNUSED(tx_ring) >= size)) 385 return 0; 386 return __iavf_maybe_stop_tx(tx_ring, size); 387 } 388 389 /** 390 * iavf_chk_linearize - Check if there are more than 8 fragments per packet 391 * @skb: send buffer 392 * @count: number of buffers used 393 * 394 * Note: Our HW can't scatter-gather more than 8 fragments to build 395 * a packet on the wire and so we need to figure out the cases where we 396 * need to linearize the skb. 397 **/ 398 static inline bool iavf_chk_linearize(struct sk_buff *skb, int count) 399 { 400 /* Both TSO and single send will work if count is less than 8 */ 401 if (likely(count < IAVF_MAX_BUFFER_TXD)) 402 return false; 403 404 if (skb_is_gso(skb)) 405 return __iavf_chk_linearize(skb); 406 407 /* we can support up to 8 data buffers for a single send */ 408 return count != IAVF_MAX_BUFFER_TXD; 409 } 410 /** 411 * txring_txq - helper to convert from a ring to a queue 412 * @ring: Tx ring to find the netdev equivalent of 413 **/ 414 static inline struct netdev_queue *txring_txq(const struct iavf_ring *ring) 415 { 416 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 417 } 418 #endif /* _IAVF_TXRX_H_ */ 419