1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _IAVF_TXRX_H_ 5 #define _IAVF_TXRX_H_ 6 7 #include <linux/net/intel/libie/pctype.h> 8 9 /* Interrupt Throttling and Rate Limiting Goodies */ 10 #define IAVF_DEFAULT_IRQ_WORK 256 11 12 /* The datasheet for the X710 and XL710 indicate that the maximum value for 13 * the ITR is 8160usec which is then called out as 0xFF0 with a 2usec 14 * resolution. 8160 is 0x1FE0 when written out in hex. So instead of storing 15 * the register value which is divided by 2 lets use the actual values and 16 * avoid an excessive amount of translation. 17 */ 18 #define IAVF_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 19 #define IAVF_ITR_MASK 0x1FFE /* mask for ITR register value */ 20 #define IAVF_ITR_100K 10 /* all values below must be even */ 21 #define IAVF_ITR_50K 20 22 #define IAVF_ITR_20K 50 23 #define IAVF_ITR_18K 60 24 #define IAVF_ITR_8K 122 25 #define IAVF_MAX_ITR 8160 /* maximum value as per datasheet */ 26 #define ITR_TO_REG(setting) ((setting) & ~IAVF_ITR_DYNAMIC) 27 #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~IAVF_ITR_MASK) 28 #define ITR_IS_DYNAMIC(setting) (!!((setting) & IAVF_ITR_DYNAMIC)) 29 30 #define IAVF_ITR_RX_DEF (IAVF_ITR_20K | IAVF_ITR_DYNAMIC) 31 #define IAVF_ITR_TX_DEF (IAVF_ITR_20K | IAVF_ITR_DYNAMIC) 32 33 /* 0x40 is the enable bit for interrupt rate limiting, and must be set if 34 * the value of the rate limit is non-zero 35 */ 36 #define INTRL_ENA BIT(6) 37 #define IAVF_MAX_INTRL 0x3B /* reg uses 4 usec resolution */ 38 #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2) 39 #define INTRL_USEC_TO_REG(set) ((set) ? ((set) >> 2) | INTRL_ENA : 0) 40 #define IAVF_INTRL_8K 125 /* 8000 ints/sec */ 41 #define IAVF_INTRL_62K 16 /* 62500 ints/sec */ 42 #define IAVF_INTRL_83K 12 /* 83333 ints/sec */ 43 44 #define IAVF_QUEUE_END_OF_LIST 0x7FF 45 46 /* this enum matches hardware bits and is meant to be used by DYN_CTLN 47 * registers and QINT registers or more generally anywhere in the manual 48 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 49 * register but instead is a special value meaning "don't update" ITR0/1/2. 50 */ 51 enum iavf_dyn_idx_t { 52 IAVF_IDX_ITR0 = 0, 53 IAVF_IDX_ITR1 = 1, 54 IAVF_IDX_ITR2 = 2, 55 IAVF_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 56 }; 57 58 /* these are indexes into ITRN registers */ 59 #define IAVF_RX_ITR IAVF_IDX_ITR0 60 #define IAVF_TX_ITR IAVF_IDX_ITR1 61 #define IAVF_PE_ITR IAVF_IDX_ITR2 62 63 /* Supported RSS offloads */ 64 #define IAVF_DEFAULT_RSS_HASHCFG ( \ 65 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 66 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 67 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 68 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 69 BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV4) | \ 70 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 71 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 72 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 73 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 74 BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV6) | \ 75 BIT_ULL(LIBIE_FILTER_PCTYPE_L2_PAYLOAD)) 76 77 #define IAVF_DEFAULT_RSS_HASHCFG_EXPANDED (IAVF_DEFAULT_RSS_HASHCFG | \ 78 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 79 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 80 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 81 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 82 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 83 BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP)) 84 85 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 86 #define IAVF_RX_INCREMENT(r, i) \ 87 do { \ 88 (i)++; \ 89 if ((i) == (r)->count) \ 90 i = 0; \ 91 r->next_to_clean = i; \ 92 } while (0) 93 94 #define IAVF_RX_NEXT_DESC(r, i, n) \ 95 do { \ 96 (i)++; \ 97 if ((i) == (r)->count) \ 98 i = 0; \ 99 (n) = IAVF_RX_DESC((r), (i)); \ 100 } while (0) 101 102 #define IAVF_RX_NEXT_DESC_PREFETCH(r, i, n) \ 103 do { \ 104 IAVF_RX_NEXT_DESC((r), (i), (n)); \ 105 prefetch((n)); \ 106 } while (0) 107 108 #define IAVF_MAX_BUFFER_TXD 8 109 #define IAVF_MIN_TX_LEN 17 110 111 /* The size limit for a transmit buffer in a descriptor is (16K - 1). 112 * In order to align with the read requests we will align the value to 113 * the nearest 4K which represents our maximum read request size. 114 */ 115 #define IAVF_MAX_READ_REQ_SIZE 4096 116 #define IAVF_MAX_DATA_PER_TXD (16 * 1024 - 1) 117 #define IAVF_MAX_DATA_PER_TXD_ALIGNED \ 118 (IAVF_MAX_DATA_PER_TXD & ~(IAVF_MAX_READ_REQ_SIZE - 1)) 119 120 /** 121 * iavf_txd_use_count - estimate the number of descriptors needed for Tx 122 * @size: transmit request size in bytes 123 * 124 * Due to hardware alignment restrictions (4K alignment), we need to 125 * assume that we can have no more than 12K of data per descriptor, even 126 * though each descriptor can take up to 16K - 1 bytes of aligned memory. 127 * Thus, we need to divide by 12K. But division is slow! Instead, 128 * we decompose the operation into shifts and one relatively cheap 129 * multiply operation. 130 * 131 * To divide by 12K, we first divide by 4K, then divide by 3: 132 * To divide by 4K, shift right by 12 bits 133 * To divide by 3, multiply by 85, then divide by 256 134 * (Divide by 256 is done by shifting right by 8 bits) 135 * Finally, we add one to round up. Because 256 isn't an exact multiple of 136 * 3, we'll underestimate near each multiple of 12K. This is actually more 137 * accurate as we have 4K - 1 of wiggle room that we can fit into the last 138 * segment. For our purposes this is accurate out to 1M which is orders of 139 * magnitude greater than our largest possible GSO size. 140 * 141 * This would then be implemented as: 142 * return (((size >> 12) * 85) >> 8) + 1; 143 * 144 * Since multiplication and division are commutative, we can reorder 145 * operations into: 146 * return ((size * 85) >> 20) + 1; 147 */ 148 static inline unsigned int iavf_txd_use_count(unsigned int size) 149 { 150 return ((size * 85) >> 20) + 1; 151 } 152 153 /* Tx Descriptors needed, worst case */ 154 #define DESC_NEEDED (MAX_SKB_FRAGS + 6) 155 #define IAVF_MIN_DESC_PENDING 4 156 157 #define IAVF_TX_FLAGS_HW_VLAN BIT(1) 158 #define IAVF_TX_FLAGS_SW_VLAN BIT(2) 159 #define IAVF_TX_FLAGS_TSO BIT(3) 160 #define IAVF_TX_FLAGS_IPV4 BIT(4) 161 #define IAVF_TX_FLAGS_IPV6 BIT(5) 162 #define IAVF_TX_FLAGS_FCCRC BIT(6) 163 #define IAVF_TX_FLAGS_FSO BIT(7) 164 #define IAVF_TX_FLAGS_FD_SB BIT(9) 165 #define IAVF_TX_FLAGS_VXLAN_TUNNEL BIT(10) 166 #define IAVF_TX_FLAGS_HW_OUTER_SINGLE_VLAN BIT(11) 167 #define IAVF_TX_FLAGS_VLAN_MASK 0xffff0000 168 #define IAVF_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 169 #define IAVF_TX_FLAGS_VLAN_PRIO_SHIFT 29 170 #define IAVF_TX_FLAGS_VLAN_SHIFT 16 171 172 struct iavf_tx_buffer { 173 struct iavf_tx_desc *next_to_watch; 174 union { 175 struct sk_buff *skb; 176 void *raw_buf; 177 }; 178 unsigned int bytecount; 179 unsigned short gso_segs; 180 181 DEFINE_DMA_UNMAP_ADDR(dma); 182 DEFINE_DMA_UNMAP_LEN(len); 183 u32 tx_flags; 184 }; 185 186 struct iavf_queue_stats { 187 u64 packets; 188 u64 bytes; 189 }; 190 191 struct iavf_tx_queue_stats { 192 u64 restart_queue; 193 u64 tx_busy; 194 u64 tx_done_old; 195 u64 tx_linearize; 196 u64 tx_force_wb; 197 u64 tx_lost_interrupt; 198 }; 199 200 struct iavf_rx_queue_stats { 201 u64 non_eop_descs; 202 u64 alloc_page_failed; 203 u64 alloc_buff_failed; 204 }; 205 206 /* some useful defines for virtchannel interface, which 207 * is the only remaining user of header split 208 */ 209 #define IAVF_RX_DTYPE_NO_SPLIT 0 210 #define IAVF_RX_DTYPE_HEADER_SPLIT 1 211 #define IAVF_RX_DTYPE_SPLIT_ALWAYS 2 212 #define IAVF_RX_SPLIT_L2 0x1 213 #define IAVF_RX_SPLIT_IP 0x2 214 #define IAVF_RX_SPLIT_TCP_UDP 0x4 215 #define IAVF_RX_SPLIT_SCTP 0x8 216 217 /* struct that defines a descriptor ring, associated with a VSI */ 218 struct iavf_ring { 219 struct iavf_ring *next; /* pointer to next ring in q_vector */ 220 void *desc; /* Descriptor ring memory */ 221 union { 222 struct page_pool *pp; /* Used on Rx for buffer management */ 223 struct device *dev; /* Used on Tx for DMA mapping */ 224 }; 225 struct net_device *netdev; /* netdev ring maps to */ 226 union { 227 struct libeth_fqe *rx_fqes; 228 struct iavf_tx_buffer *tx_bi; 229 }; 230 u8 __iomem *tail; 231 u32 truesize; 232 233 u16 queue_index; /* Queue number of ring */ 234 235 /* high bit set means dynamic, use accessors routines to read/write. 236 * hardware only supports 2us resolution for the ITR registers. 237 * these values always store the USER setting, and must be converted 238 * before programming to a register. 239 */ 240 u16 itr_setting; 241 242 u16 count; /* Number of descriptors */ 243 244 /* used in interrupt processing */ 245 u16 next_to_use; 246 u16 next_to_clean; 247 248 u16 rxdid; /* Rx descriptor format */ 249 250 u16 flags; 251 #define IAVF_TXR_FLAGS_WB_ON_ITR BIT(0) 252 #define IAVF_TXR_FLAGS_ARM_WB BIT(1) 253 /* BIT(2) is free */ 254 #define IAVF_TXRX_FLAGS_VLAN_TAG_LOC_L2TAG1 BIT(3) 255 #define IAVF_TXR_FLAGS_VLAN_TAG_LOC_L2TAG2 BIT(4) 256 #define IAVF_RXR_FLAGS_VLAN_TAG_LOC_L2TAG2_2 BIT(5) 257 #define IAVF_TXRX_FLAGS_HW_TSTAMP BIT(6) 258 259 /* stats structs */ 260 struct iavf_queue_stats stats; 261 struct u64_stats_sync syncp; 262 union { 263 struct iavf_tx_queue_stats tx_stats; 264 struct iavf_rx_queue_stats rx_stats; 265 }; 266 267 int prev_pkt_ctr; /* For Tx stall detection */ 268 unsigned int size; /* length of descriptor ring in bytes */ 269 dma_addr_t dma; /* physical address of ring */ 270 271 struct iavf_vsi *vsi; /* Backreference to associated VSI */ 272 struct iavf_q_vector *q_vector; /* Backreference to associated vector */ 273 274 struct rcu_head rcu; /* to avoid race on free */ 275 struct sk_buff *skb; /* When iavf_clean_rx_ring_irq() must 276 * return before it sees the EOP for 277 * the current packet, we save that skb 278 * here and resume receiving this 279 * packet the next time 280 * iavf_clean_rx_ring_irq() is called 281 * for this ring. 282 */ 283 284 struct iavf_ptp *ptp; 285 286 u32 rx_buf_len; 287 struct net_shaper q_shaper; 288 bool q_shaper_update; 289 } ____cacheline_internodealigned_in_smp; 290 291 #define IAVF_ITR_ADAPTIVE_MIN_INC 0x0002 292 #define IAVF_ITR_ADAPTIVE_MIN_USECS 0x0002 293 #define IAVF_ITR_ADAPTIVE_MAX_USECS 0x007e 294 #define IAVF_ITR_ADAPTIVE_LATENCY 0x8000 295 #define IAVF_ITR_ADAPTIVE_BULK 0x0000 296 #define ITR_IS_BULK(x) (!((x) & IAVF_ITR_ADAPTIVE_LATENCY)) 297 298 struct iavf_ring_container { 299 struct iavf_ring *ring; /* pointer to linked list of ring(s) */ 300 unsigned long next_update; /* jiffies value of next update */ 301 unsigned int total_bytes; /* total bytes processed this int */ 302 unsigned int total_packets; /* total packets processed this int */ 303 u16 count; 304 u16 target_itr; /* target ITR setting for ring(s) */ 305 u16 current_itr; /* current ITR setting for ring(s) */ 306 }; 307 308 /* iterator for handling rings in ring container */ 309 #define iavf_for_each_ring(pos, head) \ 310 for (pos = (head).ring; pos != NULL; pos = pos->next) 311 312 bool iavf_alloc_rx_buffers(struct iavf_ring *rxr, u16 cleaned_count); 313 netdev_tx_t iavf_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 314 int iavf_setup_tx_descriptors(struct iavf_ring *tx_ring); 315 int iavf_setup_rx_descriptors(struct iavf_ring *rx_ring); 316 void iavf_free_tx_resources(struct iavf_ring *tx_ring); 317 void iavf_free_rx_resources(struct iavf_ring *rx_ring); 318 int iavf_napi_poll(struct napi_struct *napi, int budget); 319 void iavf_detect_recover_hung(struct iavf_vsi *vsi); 320 int __iavf_maybe_stop_tx(struct iavf_ring *tx_ring, int size); 321 bool __iavf_chk_linearize(struct sk_buff *skb); 322 323 /** 324 * iavf_xmit_descriptor_count - calculate number of Tx descriptors needed 325 * @skb: send buffer 326 * 327 * Returns number of data descriptors needed for this skb. Returns 0 to indicate 328 * there is not enough descriptors available in this ring since we need at least 329 * one descriptor. 330 **/ 331 static inline int iavf_xmit_descriptor_count(struct sk_buff *skb) 332 { 333 const skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 334 unsigned int nr_frags = skb_shinfo(skb)->nr_frags; 335 int count = 0, size = skb_headlen(skb); 336 337 for (;;) { 338 count += iavf_txd_use_count(size); 339 340 if (!nr_frags--) 341 break; 342 343 size = skb_frag_size(frag++); 344 } 345 346 return count; 347 } 348 349 /** 350 * iavf_maybe_stop_tx - 1st level check for Tx stop conditions 351 * @tx_ring: the ring to be checked 352 * @size: the size buffer we want to assure is available 353 * 354 * Returns 0 if stop is not needed 355 **/ 356 static inline int iavf_maybe_stop_tx(struct iavf_ring *tx_ring, int size) 357 { 358 if (likely(IAVF_DESC_UNUSED(tx_ring) >= size)) 359 return 0; 360 return __iavf_maybe_stop_tx(tx_ring, size); 361 } 362 363 /** 364 * iavf_chk_linearize - Check if there are more than 8 fragments per packet 365 * @skb: send buffer 366 * @count: number of buffers used 367 * 368 * Note: Our HW can't scatter-gather more than 8 fragments to build 369 * a packet on the wire and so we need to figure out the cases where we 370 * need to linearize the skb. 371 **/ 372 static inline bool iavf_chk_linearize(struct sk_buff *skb, int count) 373 { 374 /* Both TSO and single send will work if count is less than 8 */ 375 if (likely(count < IAVF_MAX_BUFFER_TXD)) 376 return false; 377 378 if (skb_is_gso(skb)) 379 return __iavf_chk_linearize(skb); 380 381 /* we can support up to 8 data buffers for a single send */ 382 return count != IAVF_MAX_BUFFER_TXD; 383 } 384 /** 385 * txring_txq - helper to convert from a ring to a queue 386 * @ring: Tx ring to find the netdev equivalent of 387 **/ 388 static inline struct netdev_queue *txring_txq(const struct iavf_ring *ring) 389 { 390 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 391 } 392 #endif /* _IAVF_TXRX_H_ */ 393