xref: /linux/drivers/net/ethernet/intel/iavf/iavf_adminq.c (revision 5322c68e588dd018365fe59f9a9930ef11813337)
18be454c9SAlice Michael // SPDX-License-Identifier: GPL-2.0
28be454c9SAlice Michael /* Copyright(c) 2013 - 2018 Intel Corporation. */
38be454c9SAlice Michael 
48be454c9SAlice Michael #include "iavf_status.h"
58be454c9SAlice Michael #include "iavf_type.h"
68be454c9SAlice Michael #include "iavf_register.h"
78be454c9SAlice Michael #include "iavf_adminq.h"
88be454c9SAlice Michael #include "iavf_prototype.h"
98be454c9SAlice Michael 
108be454c9SAlice Michael /**
11d650fb40SAlice Michael  *  iavf_adminq_init_regs - Initialize AdminQ registers
128be454c9SAlice Michael  *  @hw: pointer to the hardware structure
138be454c9SAlice Michael  *
148be454c9SAlice Michael  *  This assumes the alloc_asq and alloc_arq functions have already been called
158be454c9SAlice Michael  **/
16d650fb40SAlice Michael static void iavf_adminq_init_regs(struct iavf_hw *hw)
178be454c9SAlice Michael {
188be454c9SAlice Michael 	/* set head and tail registers in our local struct */
198be454c9SAlice Michael 	hw->aq.asq.tail = IAVF_VF_ATQT1;
208be454c9SAlice Michael 	hw->aq.asq.head = IAVF_VF_ATQH1;
218be454c9SAlice Michael 	hw->aq.asq.len  = IAVF_VF_ATQLEN1;
228be454c9SAlice Michael 	hw->aq.asq.bal  = IAVF_VF_ATQBAL1;
238be454c9SAlice Michael 	hw->aq.asq.bah  = IAVF_VF_ATQBAH1;
248be454c9SAlice Michael 	hw->aq.arq.tail = IAVF_VF_ARQT1;
258be454c9SAlice Michael 	hw->aq.arq.head = IAVF_VF_ARQH1;
268be454c9SAlice Michael 	hw->aq.arq.len  = IAVF_VF_ARQLEN1;
278be454c9SAlice Michael 	hw->aq.arq.bal  = IAVF_VF_ARQBAL1;
288be454c9SAlice Michael 	hw->aq.arq.bah  = IAVF_VF_ARQBAH1;
298be454c9SAlice Michael }
308be454c9SAlice Michael 
318be454c9SAlice Michael /**
32db950599SAlice Michael  *  iavf_alloc_adminq_asq_ring - Allocate Admin Queue send rings
338be454c9SAlice Michael  *  @hw: pointer to the hardware structure
348be454c9SAlice Michael  **/
35db950599SAlice Michael static enum iavf_status iavf_alloc_adminq_asq_ring(struct iavf_hw *hw)
368be454c9SAlice Michael {
3780754bbcSSergey Nemov 	enum iavf_status ret_code;
388be454c9SAlice Michael 
398be454c9SAlice Michael 	ret_code = iavf_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
407af36e32SAlice Michael 					 iavf_mem_atq_ring,
418be454c9SAlice Michael 					 (hw->aq.num_asq_entries *
427af36e32SAlice Michael 					 sizeof(struct iavf_aq_desc)),
438be454c9SAlice Michael 					 IAVF_ADMINQ_DESC_ALIGNMENT);
448be454c9SAlice Michael 	if (ret_code)
458be454c9SAlice Michael 		return ret_code;
468be454c9SAlice Michael 
478be454c9SAlice Michael 	ret_code = iavf_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
488be454c9SAlice Michael 					  (hw->aq.num_asq_entries *
497af36e32SAlice Michael 					  sizeof(struct iavf_asq_cmd_details)));
508be454c9SAlice Michael 	if (ret_code) {
518be454c9SAlice Michael 		iavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);
528be454c9SAlice Michael 		return ret_code;
538be454c9SAlice Michael 	}
548be454c9SAlice Michael 
558be454c9SAlice Michael 	return ret_code;
568be454c9SAlice Michael }
578be454c9SAlice Michael 
588be454c9SAlice Michael /**
59db950599SAlice Michael  *  iavf_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
608be454c9SAlice Michael  *  @hw: pointer to the hardware structure
618be454c9SAlice Michael  **/
62db950599SAlice Michael static enum iavf_status iavf_alloc_adminq_arq_ring(struct iavf_hw *hw)
638be454c9SAlice Michael {
6480754bbcSSergey Nemov 	enum iavf_status ret_code;
658be454c9SAlice Michael 
668be454c9SAlice Michael 	ret_code = iavf_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
677af36e32SAlice Michael 					 iavf_mem_arq_ring,
688be454c9SAlice Michael 					 (hw->aq.num_arq_entries *
697af36e32SAlice Michael 					 sizeof(struct iavf_aq_desc)),
708be454c9SAlice Michael 					 IAVF_ADMINQ_DESC_ALIGNMENT);
718be454c9SAlice Michael 
728be454c9SAlice Michael 	return ret_code;
738be454c9SAlice Michael }
748be454c9SAlice Michael 
758be454c9SAlice Michael /**
76db950599SAlice Michael  *  iavf_free_adminq_asq - Free Admin Queue send rings
778be454c9SAlice Michael  *  @hw: pointer to the hardware structure
788be454c9SAlice Michael  *
798be454c9SAlice Michael  *  This assumes the posted send buffers have already been cleaned
808be454c9SAlice Michael  *  and de-allocated
818be454c9SAlice Michael  **/
82db950599SAlice Michael static void iavf_free_adminq_asq(struct iavf_hw *hw)
838be454c9SAlice Michael {
848be454c9SAlice Michael 	iavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);
858be454c9SAlice Michael }
868be454c9SAlice Michael 
878be454c9SAlice Michael /**
88db950599SAlice Michael  *  iavf_free_adminq_arq - Free Admin Queue receive rings
898be454c9SAlice Michael  *  @hw: pointer to the hardware structure
908be454c9SAlice Michael  *
918be454c9SAlice Michael  *  This assumes the posted receive buffers have already been cleaned
928be454c9SAlice Michael  *  and de-allocated
938be454c9SAlice Michael  **/
94db950599SAlice Michael static void iavf_free_adminq_arq(struct iavf_hw *hw)
958be454c9SAlice Michael {
968be454c9SAlice Michael 	iavf_free_dma_mem(hw, &hw->aq.arq.desc_buf);
978be454c9SAlice Michael }
988be454c9SAlice Michael 
998be454c9SAlice Michael /**
100db950599SAlice Michael  *  iavf_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
1018be454c9SAlice Michael  *  @hw: pointer to the hardware structure
1028be454c9SAlice Michael  **/
103db950599SAlice Michael static enum iavf_status iavf_alloc_arq_bufs(struct iavf_hw *hw)
1048be454c9SAlice Michael {
1057af36e32SAlice Michael 	struct iavf_aq_desc *desc;
1068be454c9SAlice Michael 	struct iavf_dma_mem *bi;
10780754bbcSSergey Nemov 	enum iavf_status ret_code;
1088be454c9SAlice Michael 	int i;
1098be454c9SAlice Michael 
1108be454c9SAlice Michael 	/* We'll be allocating the buffer info memory first, then we can
1118be454c9SAlice Michael 	 * allocate the mapped buffers for the event processing
1128be454c9SAlice Michael 	 */
1138be454c9SAlice Michael 
1148be454c9SAlice Michael 	/* buffer_info structures do not need alignment */
1158be454c9SAlice Michael 	ret_code = iavf_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
1168be454c9SAlice Michael 					  (hw->aq.num_arq_entries *
1178be454c9SAlice Michael 					   sizeof(struct iavf_dma_mem)));
1188be454c9SAlice Michael 	if (ret_code)
1198be454c9SAlice Michael 		goto alloc_arq_bufs;
1208be454c9SAlice Michael 	hw->aq.arq.r.arq_bi = (struct iavf_dma_mem *)hw->aq.arq.dma_head.va;
1218be454c9SAlice Michael 
1228be454c9SAlice Michael 	/* allocate the mapped buffers */
1238be454c9SAlice Michael 	for (i = 0; i < hw->aq.num_arq_entries; i++) {
1248be454c9SAlice Michael 		bi = &hw->aq.arq.r.arq_bi[i];
1258be454c9SAlice Michael 		ret_code = iavf_allocate_dma_mem(hw, bi,
1267af36e32SAlice Michael 						 iavf_mem_arq_buf,
1278be454c9SAlice Michael 						 hw->aq.arq_buf_size,
1288be454c9SAlice Michael 						 IAVF_ADMINQ_DESC_ALIGNMENT);
1298be454c9SAlice Michael 		if (ret_code)
1308be454c9SAlice Michael 			goto unwind_alloc_arq_bufs;
1318be454c9SAlice Michael 
1328be454c9SAlice Michael 		/* now configure the descriptors for use */
1338be454c9SAlice Michael 		desc = IAVF_ADMINQ_DESC(hw->aq.arq, i);
1348be454c9SAlice Michael 
1357af36e32SAlice Michael 		desc->flags = cpu_to_le16(IAVF_AQ_FLAG_BUF);
1367af36e32SAlice Michael 		if (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF)
1377af36e32SAlice Michael 			desc->flags |= cpu_to_le16(IAVF_AQ_FLAG_LB);
1388be454c9SAlice Michael 		desc->opcode = 0;
1398be454c9SAlice Michael 		/* This is in accordance with Admin queue design, there is no
1408be454c9SAlice Michael 		 * register for buffer size configuration
1418be454c9SAlice Michael 		 */
1428be454c9SAlice Michael 		desc->datalen = cpu_to_le16((u16)bi->size);
1438be454c9SAlice Michael 		desc->retval = 0;
1448be454c9SAlice Michael 		desc->cookie_high = 0;
1458be454c9SAlice Michael 		desc->cookie_low = 0;
1468be454c9SAlice Michael 		desc->params.external.addr_high =
1478be454c9SAlice Michael 			cpu_to_le32(upper_32_bits(bi->pa));
1488be454c9SAlice Michael 		desc->params.external.addr_low =
1498be454c9SAlice Michael 			cpu_to_le32(lower_32_bits(bi->pa));
1508be454c9SAlice Michael 		desc->params.external.param0 = 0;
1518be454c9SAlice Michael 		desc->params.external.param1 = 0;
1528be454c9SAlice Michael 	}
1538be454c9SAlice Michael 
1548be454c9SAlice Michael alloc_arq_bufs:
1558be454c9SAlice Michael 	return ret_code;
1568be454c9SAlice Michael 
1578be454c9SAlice Michael unwind_alloc_arq_bufs:
1588be454c9SAlice Michael 	/* don't try to free the one that failed... */
1598be454c9SAlice Michael 	i--;
1608be454c9SAlice Michael 	for (; i >= 0; i--)
1618be454c9SAlice Michael 		iavf_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
1628be454c9SAlice Michael 	iavf_free_virt_mem(hw, &hw->aq.arq.dma_head);
1638be454c9SAlice Michael 
1648be454c9SAlice Michael 	return ret_code;
1658be454c9SAlice Michael }
1668be454c9SAlice Michael 
1678be454c9SAlice Michael /**
168db950599SAlice Michael  *  iavf_alloc_asq_bufs - Allocate empty buffer structs for the send queue
1698be454c9SAlice Michael  *  @hw: pointer to the hardware structure
1708be454c9SAlice Michael  **/
171db950599SAlice Michael static enum iavf_status iavf_alloc_asq_bufs(struct iavf_hw *hw)
1728be454c9SAlice Michael {
1738be454c9SAlice Michael 	struct iavf_dma_mem *bi;
17480754bbcSSergey Nemov 	enum iavf_status ret_code;
1758be454c9SAlice Michael 	int i;
1768be454c9SAlice Michael 
1778be454c9SAlice Michael 	/* No mapped memory needed yet, just the buffer info structures */
1788be454c9SAlice Michael 	ret_code = iavf_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
1798be454c9SAlice Michael 					  (hw->aq.num_asq_entries *
1808be454c9SAlice Michael 					   sizeof(struct iavf_dma_mem)));
1818be454c9SAlice Michael 	if (ret_code)
1828be454c9SAlice Michael 		goto alloc_asq_bufs;
1838be454c9SAlice Michael 	hw->aq.asq.r.asq_bi = (struct iavf_dma_mem *)hw->aq.asq.dma_head.va;
1848be454c9SAlice Michael 
1858be454c9SAlice Michael 	/* allocate the mapped buffers */
1868be454c9SAlice Michael 	for (i = 0; i < hw->aq.num_asq_entries; i++) {
1878be454c9SAlice Michael 		bi = &hw->aq.asq.r.asq_bi[i];
1888be454c9SAlice Michael 		ret_code = iavf_allocate_dma_mem(hw, bi,
1897af36e32SAlice Michael 						 iavf_mem_asq_buf,
1908be454c9SAlice Michael 						 hw->aq.asq_buf_size,
1918be454c9SAlice Michael 						 IAVF_ADMINQ_DESC_ALIGNMENT);
1928be454c9SAlice Michael 		if (ret_code)
1938be454c9SAlice Michael 			goto unwind_alloc_asq_bufs;
1948be454c9SAlice Michael 	}
1958be454c9SAlice Michael alloc_asq_bufs:
1968be454c9SAlice Michael 	return ret_code;
1978be454c9SAlice Michael 
1988be454c9SAlice Michael unwind_alloc_asq_bufs:
1998be454c9SAlice Michael 	/* don't try to free the one that failed... */
2008be454c9SAlice Michael 	i--;
2018be454c9SAlice Michael 	for (; i >= 0; i--)
2028be454c9SAlice Michael 		iavf_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
2038be454c9SAlice Michael 	iavf_free_virt_mem(hw, &hw->aq.asq.dma_head);
2048be454c9SAlice Michael 
2058be454c9SAlice Michael 	return ret_code;
2068be454c9SAlice Michael }
2078be454c9SAlice Michael 
2088be454c9SAlice Michael /**
209db950599SAlice Michael  *  iavf_free_arq_bufs - Free receive queue buffer info elements
2108be454c9SAlice Michael  *  @hw: pointer to the hardware structure
2118be454c9SAlice Michael  **/
212db950599SAlice Michael static void iavf_free_arq_bufs(struct iavf_hw *hw)
2138be454c9SAlice Michael {
2148be454c9SAlice Michael 	int i;
2158be454c9SAlice Michael 
2168be454c9SAlice Michael 	/* free descriptors */
2178be454c9SAlice Michael 	for (i = 0; i < hw->aq.num_arq_entries; i++)
2188be454c9SAlice Michael 		iavf_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
2198be454c9SAlice Michael 
2208be454c9SAlice Michael 	/* free the descriptor memory */
2218be454c9SAlice Michael 	iavf_free_dma_mem(hw, &hw->aq.arq.desc_buf);
2228be454c9SAlice Michael 
2238be454c9SAlice Michael 	/* free the dma header */
2248be454c9SAlice Michael 	iavf_free_virt_mem(hw, &hw->aq.arq.dma_head);
2258be454c9SAlice Michael }
2268be454c9SAlice Michael 
2278be454c9SAlice Michael /**
228db950599SAlice Michael  *  iavf_free_asq_bufs - Free send queue buffer info elements
2298be454c9SAlice Michael  *  @hw: pointer to the hardware structure
2308be454c9SAlice Michael  **/
231db950599SAlice Michael static void iavf_free_asq_bufs(struct iavf_hw *hw)
2328be454c9SAlice Michael {
2338be454c9SAlice Michael 	int i;
2348be454c9SAlice Michael 
2358be454c9SAlice Michael 	/* only unmap if the address is non-NULL */
2368be454c9SAlice Michael 	for (i = 0; i < hw->aq.num_asq_entries; i++)
2378be454c9SAlice Michael 		if (hw->aq.asq.r.asq_bi[i].pa)
2388be454c9SAlice Michael 			iavf_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
2398be454c9SAlice Michael 
2408be454c9SAlice Michael 	/* free the buffer info list */
2418be454c9SAlice Michael 	iavf_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
2428be454c9SAlice Michael 
2438be454c9SAlice Michael 	/* free the descriptor memory */
2448be454c9SAlice Michael 	iavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);
2458be454c9SAlice Michael 
2468be454c9SAlice Michael 	/* free the dma header */
2478be454c9SAlice Michael 	iavf_free_virt_mem(hw, &hw->aq.asq.dma_head);
2488be454c9SAlice Michael }
2498be454c9SAlice Michael 
2508be454c9SAlice Michael /**
251db950599SAlice Michael  *  iavf_config_asq_regs - configure ASQ registers
2528be454c9SAlice Michael  *  @hw: pointer to the hardware structure
2538be454c9SAlice Michael  *
2548be454c9SAlice Michael  *  Configure base address and length registers for the transmit queue
2558be454c9SAlice Michael  **/
256db950599SAlice Michael static enum iavf_status iavf_config_asq_regs(struct iavf_hw *hw)
2578be454c9SAlice Michael {
25880754bbcSSergey Nemov 	enum iavf_status ret_code = 0;
2598be454c9SAlice Michael 	u32 reg = 0;
2608be454c9SAlice Michael 
2618be454c9SAlice Michael 	/* Clear Head and Tail */
2628be454c9SAlice Michael 	wr32(hw, hw->aq.asq.head, 0);
2638be454c9SAlice Michael 	wr32(hw, hw->aq.asq.tail, 0);
2648be454c9SAlice Michael 
2658be454c9SAlice Michael 	/* set starting point */
2668be454c9SAlice Michael 	wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
2678be454c9SAlice Michael 				  IAVF_VF_ATQLEN1_ATQENABLE_MASK));
2688be454c9SAlice Michael 	wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
2698be454c9SAlice Michael 	wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
2708be454c9SAlice Michael 
2718be454c9SAlice Michael 	/* Check one register to verify that config was applied */
2728be454c9SAlice Michael 	reg = rd32(hw, hw->aq.asq.bal);
2738be454c9SAlice Michael 	if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
2748821b3faSAlice Michael 		ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
2758be454c9SAlice Michael 
2768be454c9SAlice Michael 	return ret_code;
2778be454c9SAlice Michael }
2788be454c9SAlice Michael 
2798be454c9SAlice Michael /**
280db950599SAlice Michael  *  iavf_config_arq_regs - ARQ register configuration
2818be454c9SAlice Michael  *  @hw: pointer to the hardware structure
2828be454c9SAlice Michael  *
2838be454c9SAlice Michael  * Configure base address and length registers for the receive (event queue)
2848be454c9SAlice Michael  **/
285db950599SAlice Michael static enum iavf_status iavf_config_arq_regs(struct iavf_hw *hw)
2868be454c9SAlice Michael {
28780754bbcSSergey Nemov 	enum iavf_status ret_code = 0;
2888be454c9SAlice Michael 	u32 reg = 0;
2898be454c9SAlice Michael 
2908be454c9SAlice Michael 	/* Clear Head and Tail */
2918be454c9SAlice Michael 	wr32(hw, hw->aq.arq.head, 0);
2928be454c9SAlice Michael 	wr32(hw, hw->aq.arq.tail, 0);
2938be454c9SAlice Michael 
2948be454c9SAlice Michael 	/* set starting point */
2958be454c9SAlice Michael 	wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
2968be454c9SAlice Michael 				  IAVF_VF_ARQLEN1_ARQENABLE_MASK));
2978be454c9SAlice Michael 	wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
2988be454c9SAlice Michael 	wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
2998be454c9SAlice Michael 
3008be454c9SAlice Michael 	/* Update tail in the HW to post pre-allocated buffers */
3018be454c9SAlice Michael 	wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
3028be454c9SAlice Michael 
3038be454c9SAlice Michael 	/* Check one register to verify that config was applied */
3048be454c9SAlice Michael 	reg = rd32(hw, hw->aq.arq.bal);
3058be454c9SAlice Michael 	if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
3068821b3faSAlice Michael 		ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
3078be454c9SAlice Michael 
3088be454c9SAlice Michael 	return ret_code;
3098be454c9SAlice Michael }
3108be454c9SAlice Michael 
3118be454c9SAlice Michael /**
312db950599SAlice Michael  *  iavf_init_asq - main initialization routine for ASQ
3138be454c9SAlice Michael  *  @hw: pointer to the hardware structure
3148be454c9SAlice Michael  *
3158be454c9SAlice Michael  *  This is the main initialization routine for the Admin Send Queue
3168be454c9SAlice Michael  *  Prior to calling this function, drivers *MUST* set the following fields
3178be454c9SAlice Michael  *  in the hw->aq structure:
3188be454c9SAlice Michael  *     - hw->aq.num_asq_entries
3198be454c9SAlice Michael  *     - hw->aq.arq_buf_size
3208be454c9SAlice Michael  *
3218be454c9SAlice Michael  *  Do *NOT* hold the lock when calling this as the memory allocation routines
3228be454c9SAlice Michael  *  called are not going to be atomic context safe
3238be454c9SAlice Michael  **/
324db950599SAlice Michael static enum iavf_status iavf_init_asq(struct iavf_hw *hw)
3258be454c9SAlice Michael {
32680754bbcSSergey Nemov 	enum iavf_status ret_code = 0;
3278be454c9SAlice Michael 
3288be454c9SAlice Michael 	if (hw->aq.asq.count > 0) {
3298be454c9SAlice Michael 		/* queue already initialized */
3308821b3faSAlice Michael 		ret_code = IAVF_ERR_NOT_READY;
3318be454c9SAlice Michael 		goto init_adminq_exit;
3328be454c9SAlice Michael 	}
3338be454c9SAlice Michael 
3348be454c9SAlice Michael 	/* verify input for valid configuration */
3358be454c9SAlice Michael 	if ((hw->aq.num_asq_entries == 0) ||
3368be454c9SAlice Michael 	    (hw->aq.asq_buf_size == 0)) {
3378821b3faSAlice Michael 		ret_code = IAVF_ERR_CONFIG;
3388be454c9SAlice Michael 		goto init_adminq_exit;
3398be454c9SAlice Michael 	}
3408be454c9SAlice Michael 
3418be454c9SAlice Michael 	hw->aq.asq.next_to_use = 0;
3428be454c9SAlice Michael 	hw->aq.asq.next_to_clean = 0;
3438be454c9SAlice Michael 
3448be454c9SAlice Michael 	/* allocate the ring memory */
345db950599SAlice Michael 	ret_code = iavf_alloc_adminq_asq_ring(hw);
3468be454c9SAlice Michael 	if (ret_code)
3478be454c9SAlice Michael 		goto init_adminq_exit;
3488be454c9SAlice Michael 
3498be454c9SAlice Michael 	/* allocate buffers in the rings */
350db950599SAlice Michael 	ret_code = iavf_alloc_asq_bufs(hw);
3518be454c9SAlice Michael 	if (ret_code)
3528be454c9SAlice Michael 		goto init_adminq_free_rings;
3538be454c9SAlice Michael 
3548be454c9SAlice Michael 	/* initialize base registers */
355db950599SAlice Michael 	ret_code = iavf_config_asq_regs(hw);
3568be454c9SAlice Michael 	if (ret_code)
3578be454c9SAlice Michael 		goto init_adminq_free_rings;
3588be454c9SAlice Michael 
3598be454c9SAlice Michael 	/* success! */
3608be454c9SAlice Michael 	hw->aq.asq.count = hw->aq.num_asq_entries;
3618be454c9SAlice Michael 	goto init_adminq_exit;
3628be454c9SAlice Michael 
3638be454c9SAlice Michael init_adminq_free_rings:
364db950599SAlice Michael 	iavf_free_adminq_asq(hw);
3658be454c9SAlice Michael 
3668be454c9SAlice Michael init_adminq_exit:
3678be454c9SAlice Michael 	return ret_code;
3688be454c9SAlice Michael }
3698be454c9SAlice Michael 
3708be454c9SAlice Michael /**
371db950599SAlice Michael  *  iavf_init_arq - initialize ARQ
3728be454c9SAlice Michael  *  @hw: pointer to the hardware structure
3738be454c9SAlice Michael  *
3748be454c9SAlice Michael  *  The main initialization routine for the Admin Receive (Event) Queue.
3758be454c9SAlice Michael  *  Prior to calling this function, drivers *MUST* set the following fields
3768be454c9SAlice Michael  *  in the hw->aq structure:
3778be454c9SAlice Michael  *     - hw->aq.num_asq_entries
3788be454c9SAlice Michael  *     - hw->aq.arq_buf_size
3798be454c9SAlice Michael  *
3808be454c9SAlice Michael  *  Do *NOT* hold the lock when calling this as the memory allocation routines
3818be454c9SAlice Michael  *  called are not going to be atomic context safe
3828be454c9SAlice Michael  **/
383db950599SAlice Michael static enum iavf_status iavf_init_arq(struct iavf_hw *hw)
3848be454c9SAlice Michael {
38580754bbcSSergey Nemov 	enum iavf_status ret_code = 0;
3868be454c9SAlice Michael 
3878be454c9SAlice Michael 	if (hw->aq.arq.count > 0) {
3888be454c9SAlice Michael 		/* queue already initialized */
3898821b3faSAlice Michael 		ret_code = IAVF_ERR_NOT_READY;
3908be454c9SAlice Michael 		goto init_adminq_exit;
3918be454c9SAlice Michael 	}
3928be454c9SAlice Michael 
3938be454c9SAlice Michael 	/* verify input for valid configuration */
3948be454c9SAlice Michael 	if ((hw->aq.num_arq_entries == 0) ||
3958be454c9SAlice Michael 	    (hw->aq.arq_buf_size == 0)) {
3968821b3faSAlice Michael 		ret_code = IAVF_ERR_CONFIG;
3978be454c9SAlice Michael 		goto init_adminq_exit;
3988be454c9SAlice Michael 	}
3998be454c9SAlice Michael 
4008be454c9SAlice Michael 	hw->aq.arq.next_to_use = 0;
4018be454c9SAlice Michael 	hw->aq.arq.next_to_clean = 0;
4028be454c9SAlice Michael 
4038be454c9SAlice Michael 	/* allocate the ring memory */
404db950599SAlice Michael 	ret_code = iavf_alloc_adminq_arq_ring(hw);
4058be454c9SAlice Michael 	if (ret_code)
4068be454c9SAlice Michael 		goto init_adminq_exit;
4078be454c9SAlice Michael 
4088be454c9SAlice Michael 	/* allocate buffers in the rings */
409db950599SAlice Michael 	ret_code = iavf_alloc_arq_bufs(hw);
4108be454c9SAlice Michael 	if (ret_code)
4118be454c9SAlice Michael 		goto init_adminq_free_rings;
4128be454c9SAlice Michael 
4138be454c9SAlice Michael 	/* initialize base registers */
414db950599SAlice Michael 	ret_code = iavf_config_arq_regs(hw);
4158be454c9SAlice Michael 	if (ret_code)
4168be454c9SAlice Michael 		goto init_adminq_free_rings;
4178be454c9SAlice Michael 
4188be454c9SAlice Michael 	/* success! */
4198be454c9SAlice Michael 	hw->aq.arq.count = hw->aq.num_arq_entries;
4208be454c9SAlice Michael 	goto init_adminq_exit;
4218be454c9SAlice Michael 
4228be454c9SAlice Michael init_adminq_free_rings:
423db950599SAlice Michael 	iavf_free_adminq_arq(hw);
4248be454c9SAlice Michael 
4258be454c9SAlice Michael init_adminq_exit:
4268be454c9SAlice Michael 	return ret_code;
4278be454c9SAlice Michael }
4288be454c9SAlice Michael 
4298be454c9SAlice Michael /**
430db950599SAlice Michael  *  iavf_shutdown_asq - shutdown the ASQ
4318be454c9SAlice Michael  *  @hw: pointer to the hardware structure
4328be454c9SAlice Michael  *
4338be454c9SAlice Michael  *  The main shutdown routine for the Admin Send Queue
4348be454c9SAlice Michael  **/
435db950599SAlice Michael static enum iavf_status iavf_shutdown_asq(struct iavf_hw *hw)
4368be454c9SAlice Michael {
43780754bbcSSergey Nemov 	enum iavf_status ret_code = 0;
4388be454c9SAlice Michael 
4398be454c9SAlice Michael 	mutex_lock(&hw->aq.asq_mutex);
4408be454c9SAlice Michael 
4418be454c9SAlice Michael 	if (hw->aq.asq.count == 0) {
4428821b3faSAlice Michael 		ret_code = IAVF_ERR_NOT_READY;
4438be454c9SAlice Michael 		goto shutdown_asq_out;
4448be454c9SAlice Michael 	}
4458be454c9SAlice Michael 
4468be454c9SAlice Michael 	/* Stop firmware AdminQ processing */
4478be454c9SAlice Michael 	wr32(hw, hw->aq.asq.head, 0);
4488be454c9SAlice Michael 	wr32(hw, hw->aq.asq.tail, 0);
4498be454c9SAlice Michael 	wr32(hw, hw->aq.asq.len, 0);
4508be454c9SAlice Michael 	wr32(hw, hw->aq.asq.bal, 0);
4518be454c9SAlice Michael 	wr32(hw, hw->aq.asq.bah, 0);
4528be454c9SAlice Michael 
4538be454c9SAlice Michael 	hw->aq.asq.count = 0; /* to indicate uninitialized queue */
4548be454c9SAlice Michael 
4558be454c9SAlice Michael 	/* free ring buffers */
456db950599SAlice Michael 	iavf_free_asq_bufs(hw);
4578be454c9SAlice Michael 
4588be454c9SAlice Michael shutdown_asq_out:
4598be454c9SAlice Michael 	mutex_unlock(&hw->aq.asq_mutex);
4608be454c9SAlice Michael 	return ret_code;
4618be454c9SAlice Michael }
4628be454c9SAlice Michael 
4638be454c9SAlice Michael /**
464db950599SAlice Michael  *  iavf_shutdown_arq - shutdown ARQ
4658be454c9SAlice Michael  *  @hw: pointer to the hardware structure
4668be454c9SAlice Michael  *
4678be454c9SAlice Michael  *  The main shutdown routine for the Admin Receive Queue
4688be454c9SAlice Michael  **/
469db950599SAlice Michael static enum iavf_status iavf_shutdown_arq(struct iavf_hw *hw)
4708be454c9SAlice Michael {
47180754bbcSSergey Nemov 	enum iavf_status ret_code = 0;
4728be454c9SAlice Michael 
4738be454c9SAlice Michael 	mutex_lock(&hw->aq.arq_mutex);
4748be454c9SAlice Michael 
4758be454c9SAlice Michael 	if (hw->aq.arq.count == 0) {
4768821b3faSAlice Michael 		ret_code = IAVF_ERR_NOT_READY;
4778be454c9SAlice Michael 		goto shutdown_arq_out;
4788be454c9SAlice Michael 	}
4798be454c9SAlice Michael 
4808be454c9SAlice Michael 	/* Stop firmware AdminQ processing */
4818be454c9SAlice Michael 	wr32(hw, hw->aq.arq.head, 0);
4828be454c9SAlice Michael 	wr32(hw, hw->aq.arq.tail, 0);
4838be454c9SAlice Michael 	wr32(hw, hw->aq.arq.len, 0);
4848be454c9SAlice Michael 	wr32(hw, hw->aq.arq.bal, 0);
4858be454c9SAlice Michael 	wr32(hw, hw->aq.arq.bah, 0);
4868be454c9SAlice Michael 
4878be454c9SAlice Michael 	hw->aq.arq.count = 0; /* to indicate uninitialized queue */
4888be454c9SAlice Michael 
4898be454c9SAlice Michael 	/* free ring buffers */
490db950599SAlice Michael 	iavf_free_arq_bufs(hw);
4918be454c9SAlice Michael 
4928be454c9SAlice Michael shutdown_arq_out:
4938be454c9SAlice Michael 	mutex_unlock(&hw->aq.arq_mutex);
4948be454c9SAlice Michael 	return ret_code;
4958be454c9SAlice Michael }
4968be454c9SAlice Michael 
4978be454c9SAlice Michael /**
4988be454c9SAlice Michael  *  iavf_init_adminq - main initialization routine for Admin Queue
4998be454c9SAlice Michael  *  @hw: pointer to the hardware structure
5008be454c9SAlice Michael  *
5018be454c9SAlice Michael  *  Prior to calling this function, drivers *MUST* set the following fields
5028be454c9SAlice Michael  *  in the hw->aq structure:
5038be454c9SAlice Michael  *     - hw->aq.num_asq_entries
5048be454c9SAlice Michael  *     - hw->aq.num_arq_entries
5058be454c9SAlice Michael  *     - hw->aq.arq_buf_size
5068be454c9SAlice Michael  *     - hw->aq.asq_buf_size
5078be454c9SAlice Michael  **/
50880754bbcSSergey Nemov enum iavf_status iavf_init_adminq(struct iavf_hw *hw)
5098be454c9SAlice Michael {
51080754bbcSSergey Nemov 	enum iavf_status ret_code;
5118be454c9SAlice Michael 
5128be454c9SAlice Michael 	/* verify input for valid configuration */
5138be454c9SAlice Michael 	if ((hw->aq.num_arq_entries == 0) ||
5148be454c9SAlice Michael 	    (hw->aq.num_asq_entries == 0) ||
5158be454c9SAlice Michael 	    (hw->aq.arq_buf_size == 0) ||
5168be454c9SAlice Michael 	    (hw->aq.asq_buf_size == 0)) {
5178821b3faSAlice Michael 		ret_code = IAVF_ERR_CONFIG;
5188be454c9SAlice Michael 		goto init_adminq_exit;
5198be454c9SAlice Michael 	}
5208be454c9SAlice Michael 
5218be454c9SAlice Michael 	/* Set up register offsets */
522d650fb40SAlice Michael 	iavf_adminq_init_regs(hw);
5238be454c9SAlice Michael 
5248be454c9SAlice Michael 	/* setup ASQ command write back timeout */
5257af36e32SAlice Michael 	hw->aq.asq_cmd_timeout = IAVF_ASQ_CMD_TIMEOUT;
5268be454c9SAlice Michael 
5278be454c9SAlice Michael 	/* allocate the ASQ */
528db950599SAlice Michael 	ret_code = iavf_init_asq(hw);
5298be454c9SAlice Michael 	if (ret_code)
5308be454c9SAlice Michael 		goto init_adminq_destroy_locks;
5318be454c9SAlice Michael 
5328be454c9SAlice Michael 	/* allocate the ARQ */
533db950599SAlice Michael 	ret_code = iavf_init_arq(hw);
5348be454c9SAlice Michael 	if (ret_code)
5358be454c9SAlice Michael 		goto init_adminq_free_asq;
5368be454c9SAlice Michael 
5378be454c9SAlice Michael 	/* success! */
5388be454c9SAlice Michael 	goto init_adminq_exit;
5398be454c9SAlice Michael 
5408be454c9SAlice Michael init_adminq_free_asq:
541db950599SAlice Michael 	iavf_shutdown_asq(hw);
5428be454c9SAlice Michael init_adminq_destroy_locks:
5438be454c9SAlice Michael 
5448be454c9SAlice Michael init_adminq_exit:
5458be454c9SAlice Michael 	return ret_code;
5468be454c9SAlice Michael }
5478be454c9SAlice Michael 
5488be454c9SAlice Michael /**
5498be454c9SAlice Michael  *  iavf_shutdown_adminq - shutdown routine for the Admin Queue
5508be454c9SAlice Michael  *  @hw: pointer to the hardware structure
5518be454c9SAlice Michael  **/
55280754bbcSSergey Nemov enum iavf_status iavf_shutdown_adminq(struct iavf_hw *hw)
5538be454c9SAlice Michael {
5548be454c9SAlice Michael 	if (iavf_check_asq_alive(hw))
5558be454c9SAlice Michael 		iavf_aq_queue_shutdown(hw, true);
5568be454c9SAlice Michael 
557db950599SAlice Michael 	iavf_shutdown_asq(hw);
558db950599SAlice Michael 	iavf_shutdown_arq(hw);
5598be454c9SAlice Michael 
560*5322c68eSJason Wang 	return 0;
5618be454c9SAlice Michael }
5628be454c9SAlice Michael 
5638be454c9SAlice Michael /**
564db950599SAlice Michael  *  iavf_clean_asq - cleans Admin send queue
5658be454c9SAlice Michael  *  @hw: pointer to the hardware structure
5668be454c9SAlice Michael  *
5678be454c9SAlice Michael  *  returns the number of free desc
5688be454c9SAlice Michael  **/
569db950599SAlice Michael static u16 iavf_clean_asq(struct iavf_hw *hw)
5708be454c9SAlice Michael {
5718be454c9SAlice Michael 	struct iavf_adminq_ring *asq = &hw->aq.asq;
5727af36e32SAlice Michael 	struct iavf_asq_cmd_details *details;
5738be454c9SAlice Michael 	u16 ntc = asq->next_to_clean;
5747af36e32SAlice Michael 	struct iavf_aq_desc desc_cb;
5757af36e32SAlice Michael 	struct iavf_aq_desc *desc;
5768be454c9SAlice Michael 
5778be454c9SAlice Michael 	desc = IAVF_ADMINQ_DESC(*asq, ntc);
5787af36e32SAlice Michael 	details = IAVF_ADMINQ_DETAILS(*asq, ntc);
5798be454c9SAlice Michael 	while (rd32(hw, hw->aq.asq.head) != ntc) {
5808be454c9SAlice Michael 		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
5818be454c9SAlice Michael 			   "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
5828be454c9SAlice Michael 
5838be454c9SAlice Michael 		if (details->callback) {
584db950599SAlice Michael 			IAVF_ADMINQ_CALLBACK cb_func =
585db950599SAlice Michael 					(IAVF_ADMINQ_CALLBACK)details->callback;
5868be454c9SAlice Michael 			desc_cb = *desc;
5878be454c9SAlice Michael 			cb_func(hw, &desc_cb);
5888be454c9SAlice Michael 		}
5897af36e32SAlice Michael 		memset((void *)desc, 0, sizeof(struct iavf_aq_desc));
5908be454c9SAlice Michael 		memset((void *)details, 0,
5917af36e32SAlice Michael 		       sizeof(struct iavf_asq_cmd_details));
5928be454c9SAlice Michael 		ntc++;
5938be454c9SAlice Michael 		if (ntc == asq->count)
5948be454c9SAlice Michael 			ntc = 0;
5958be454c9SAlice Michael 		desc = IAVF_ADMINQ_DESC(*asq, ntc);
5967af36e32SAlice Michael 		details = IAVF_ADMINQ_DETAILS(*asq, ntc);
5978be454c9SAlice Michael 	}
5988be454c9SAlice Michael 
5998be454c9SAlice Michael 	asq->next_to_clean = ntc;
6008be454c9SAlice Michael 
6018be454c9SAlice Michael 	return IAVF_DESC_UNUSED(asq);
6028be454c9SAlice Michael }
6038be454c9SAlice Michael 
6048be454c9SAlice Michael /**
6058be454c9SAlice Michael  *  iavf_asq_done - check if FW has processed the Admin Send Queue
6068be454c9SAlice Michael  *  @hw: pointer to the hw struct
6078be454c9SAlice Michael  *
6088be454c9SAlice Michael  *  Returns true if the firmware has processed all descriptors on the
6098be454c9SAlice Michael  *  admin send queue. Returns false if there are still requests pending.
6108be454c9SAlice Michael  **/
6118be454c9SAlice Michael bool iavf_asq_done(struct iavf_hw *hw)
6128be454c9SAlice Michael {
6138be454c9SAlice Michael 	/* AQ designers suggest use of head for better
6148be454c9SAlice Michael 	 * timing reliability than DD bit
6158be454c9SAlice Michael 	 */
6168be454c9SAlice Michael 	return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
6178be454c9SAlice Michael }
6188be454c9SAlice Michael 
6198be454c9SAlice Michael /**
6208be454c9SAlice Michael  *  iavf_asq_send_command - send command to Admin Queue
6218be454c9SAlice Michael  *  @hw: pointer to the hw struct
6228be454c9SAlice Michael  *  @desc: prefilled descriptor describing the command (non DMA mem)
6238be454c9SAlice Michael  *  @buff: buffer to use for indirect commands
6248be454c9SAlice Michael  *  @buff_size: size of buffer for indirect commands
6258be454c9SAlice Michael  *  @cmd_details: pointer to command details structure
6268be454c9SAlice Michael  *
6278be454c9SAlice Michael  *  This is the main send command driver routine for the Admin Queue send
6288be454c9SAlice Michael  *  queue.  It runs the queue, cleans the queue, etc
6298be454c9SAlice Michael  **/
63080754bbcSSergey Nemov enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
6317af36e32SAlice Michael 				       struct iavf_aq_desc *desc,
6328be454c9SAlice Michael 				       void *buff, /* can be NULL */
6338be454c9SAlice Michael 				       u16  buff_size,
6347af36e32SAlice Michael 				       struct iavf_asq_cmd_details *cmd_details)
6358be454c9SAlice Michael {
6368be454c9SAlice Michael 	struct iavf_dma_mem *dma_buff = NULL;
6377af36e32SAlice Michael 	struct iavf_asq_cmd_details *details;
6387af36e32SAlice Michael 	struct iavf_aq_desc *desc_on_ring;
6398be454c9SAlice Michael 	bool cmd_completed = false;
64080754bbcSSergey Nemov 	enum iavf_status status = 0;
6418be454c9SAlice Michael 	u16  retval = 0;
6428be454c9SAlice Michael 	u32  val = 0;
6438be454c9SAlice Michael 
6448be454c9SAlice Michael 	mutex_lock(&hw->aq.asq_mutex);
6458be454c9SAlice Michael 
6468be454c9SAlice Michael 	if (hw->aq.asq.count == 0) {
6478be454c9SAlice Michael 		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
6488be454c9SAlice Michael 			   "AQTX: Admin queue not initialized.\n");
6498821b3faSAlice Michael 		status = IAVF_ERR_QUEUE_EMPTY;
6508be454c9SAlice Michael 		goto asq_send_command_error;
6518be454c9SAlice Michael 	}
6528be454c9SAlice Michael 
6537af36e32SAlice Michael 	hw->aq.asq_last_status = IAVF_AQ_RC_OK;
6548be454c9SAlice Michael 
6558be454c9SAlice Michael 	val = rd32(hw, hw->aq.asq.head);
6568be454c9SAlice Michael 	if (val >= hw->aq.num_asq_entries) {
6578be454c9SAlice Michael 		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
6588be454c9SAlice Michael 			   "AQTX: head overrun at %d\n", val);
6598821b3faSAlice Michael 		status = IAVF_ERR_QUEUE_EMPTY;
6608be454c9SAlice Michael 		goto asq_send_command_error;
6618be454c9SAlice Michael 	}
6628be454c9SAlice Michael 
6637af36e32SAlice Michael 	details = IAVF_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
6648be454c9SAlice Michael 	if (cmd_details) {
6658be454c9SAlice Michael 		*details = *cmd_details;
6668be454c9SAlice Michael 
6678be454c9SAlice Michael 		/* If the cmd_details are defined copy the cookie.  The
6688be454c9SAlice Michael 		 * cpu_to_le32 is not needed here because the data is ignored
6698be454c9SAlice Michael 		 * by the FW, only used by the driver
6708be454c9SAlice Michael 		 */
6718be454c9SAlice Michael 		if (details->cookie) {
6728be454c9SAlice Michael 			desc->cookie_high =
6738be454c9SAlice Michael 				cpu_to_le32(upper_32_bits(details->cookie));
6748be454c9SAlice Michael 			desc->cookie_low =
6758be454c9SAlice Michael 				cpu_to_le32(lower_32_bits(details->cookie));
6768be454c9SAlice Michael 		}
6778be454c9SAlice Michael 	} else {
6787af36e32SAlice Michael 		memset(details, 0, sizeof(struct iavf_asq_cmd_details));
6798be454c9SAlice Michael 	}
6808be454c9SAlice Michael 
6818be454c9SAlice Michael 	/* clear requested flags and then set additional flags if defined */
6828be454c9SAlice Michael 	desc->flags &= ~cpu_to_le16(details->flags_dis);
6838be454c9SAlice Michael 	desc->flags |= cpu_to_le16(details->flags_ena);
6848be454c9SAlice Michael 
6858be454c9SAlice Michael 	if (buff_size > hw->aq.asq_buf_size) {
6868be454c9SAlice Michael 		iavf_debug(hw,
6878be454c9SAlice Michael 			   IAVF_DEBUG_AQ_MESSAGE,
6888be454c9SAlice Michael 			   "AQTX: Invalid buffer size: %d.\n",
6898be454c9SAlice Michael 			   buff_size);
6908821b3faSAlice Michael 		status = IAVF_ERR_INVALID_SIZE;
6918be454c9SAlice Michael 		goto asq_send_command_error;
6928be454c9SAlice Michael 	}
6938be454c9SAlice Michael 
6948be454c9SAlice Michael 	if (details->postpone && !details->async) {
6958be454c9SAlice Michael 		iavf_debug(hw,
6968be454c9SAlice Michael 			   IAVF_DEBUG_AQ_MESSAGE,
6978be454c9SAlice Michael 			   "AQTX: Async flag not set along with postpone flag");
6988821b3faSAlice Michael 		status = IAVF_ERR_PARAM;
6998be454c9SAlice Michael 		goto asq_send_command_error;
7008be454c9SAlice Michael 	}
7018be454c9SAlice Michael 
7028be454c9SAlice Michael 	/* call clean and check queue available function to reclaim the
7038be454c9SAlice Michael 	 * descriptors that were processed by FW, the function returns the
7048be454c9SAlice Michael 	 * number of desc available
7058be454c9SAlice Michael 	 */
7068be454c9SAlice Michael 	/* the clean function called here could be called in a separate thread
7078be454c9SAlice Michael 	 * in case of asynchronous completions
7088be454c9SAlice Michael 	 */
709db950599SAlice Michael 	if (iavf_clean_asq(hw) == 0) {
7108be454c9SAlice Michael 		iavf_debug(hw,
7118be454c9SAlice Michael 			   IAVF_DEBUG_AQ_MESSAGE,
7128be454c9SAlice Michael 			   "AQTX: Error queue is full.\n");
7138821b3faSAlice Michael 		status = IAVF_ERR_ADMIN_QUEUE_FULL;
7148be454c9SAlice Michael 		goto asq_send_command_error;
7158be454c9SAlice Michael 	}
7168be454c9SAlice Michael 
7178be454c9SAlice Michael 	/* initialize the temp desc pointer with the right desc */
7188be454c9SAlice Michael 	desc_on_ring = IAVF_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
7198be454c9SAlice Michael 
7208be454c9SAlice Michael 	/* if the desc is available copy the temp desc to the right place */
7218be454c9SAlice Michael 	*desc_on_ring = *desc;
7228be454c9SAlice Michael 
7238be454c9SAlice Michael 	/* if buff is not NULL assume indirect command */
7248be454c9SAlice Michael 	if (buff) {
7258be454c9SAlice Michael 		dma_buff = &hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use];
7268be454c9SAlice Michael 		/* copy the user buff into the respective DMA buff */
7278be454c9SAlice Michael 		memcpy(dma_buff->va, buff, buff_size);
7288be454c9SAlice Michael 		desc_on_ring->datalen = cpu_to_le16(buff_size);
7298be454c9SAlice Michael 
7308be454c9SAlice Michael 		/* Update the address values in the desc with the pa value
7318be454c9SAlice Michael 		 * for respective buffer
7328be454c9SAlice Michael 		 */
7338be454c9SAlice Michael 		desc_on_ring->params.external.addr_high =
7348be454c9SAlice Michael 				cpu_to_le32(upper_32_bits(dma_buff->pa));
7358be454c9SAlice Michael 		desc_on_ring->params.external.addr_low =
7368be454c9SAlice Michael 				cpu_to_le32(lower_32_bits(dma_buff->pa));
7378be454c9SAlice Michael 	}
7388be454c9SAlice Michael 
7398be454c9SAlice Michael 	/* bump the tail */
7408be454c9SAlice Michael 	iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
7418be454c9SAlice Michael 	iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
7428be454c9SAlice Michael 		      buff, buff_size);
7438be454c9SAlice Michael 	(hw->aq.asq.next_to_use)++;
7448be454c9SAlice Michael 	if (hw->aq.asq.next_to_use == hw->aq.asq.count)
7458be454c9SAlice Michael 		hw->aq.asq.next_to_use = 0;
7468be454c9SAlice Michael 	if (!details->postpone)
7478be454c9SAlice Michael 		wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
7488be454c9SAlice Michael 
7498be454c9SAlice Michael 	/* if cmd_details are not defined or async flag is not set,
7508be454c9SAlice Michael 	 * we need to wait for desc write back
7518be454c9SAlice Michael 	 */
7528be454c9SAlice Michael 	if (!details->async && !details->postpone) {
7538be454c9SAlice Michael 		u32 total_delay = 0;
7548be454c9SAlice Michael 
7558be454c9SAlice Michael 		do {
7568be454c9SAlice Michael 			/* AQ designers suggest use of head for better
7578be454c9SAlice Michael 			 * timing reliability than DD bit
7588be454c9SAlice Michael 			 */
7598be454c9SAlice Michael 			if (iavf_asq_done(hw))
7608be454c9SAlice Michael 				break;
7618be454c9SAlice Michael 			udelay(50);
7628be454c9SAlice Michael 			total_delay += 50;
7638be454c9SAlice Michael 		} while (total_delay < hw->aq.asq_cmd_timeout);
7648be454c9SAlice Michael 	}
7658be454c9SAlice Michael 
7668be454c9SAlice Michael 	/* if ready, copy the desc back to temp */
7678be454c9SAlice Michael 	if (iavf_asq_done(hw)) {
7688be454c9SAlice Michael 		*desc = *desc_on_ring;
7698be454c9SAlice Michael 		if (buff)
7708be454c9SAlice Michael 			memcpy(buff, dma_buff->va, buff_size);
7718be454c9SAlice Michael 		retval = le16_to_cpu(desc->retval);
7728be454c9SAlice Michael 		if (retval != 0) {
7738be454c9SAlice Michael 			iavf_debug(hw,
7748be454c9SAlice Michael 				   IAVF_DEBUG_AQ_MESSAGE,
7758be454c9SAlice Michael 				   "AQTX: Command completed with error 0x%X.\n",
7768be454c9SAlice Michael 				   retval);
7778be454c9SAlice Michael 
7788be454c9SAlice Michael 			/* strip off FW internal code */
7798be454c9SAlice Michael 			retval &= 0xff;
7808be454c9SAlice Michael 		}
7818be454c9SAlice Michael 		cmd_completed = true;
7827af36e32SAlice Michael 		if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_OK)
7838be454c9SAlice Michael 			status = 0;
7847af36e32SAlice Michael 		else if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_EBUSY)
7858821b3faSAlice Michael 			status = IAVF_ERR_NOT_READY;
7868be454c9SAlice Michael 		else
7878821b3faSAlice Michael 			status = IAVF_ERR_ADMIN_QUEUE_ERROR;
7887af36e32SAlice Michael 		hw->aq.asq_last_status = (enum iavf_admin_queue_err)retval;
7898be454c9SAlice Michael 	}
7908be454c9SAlice Michael 
7918be454c9SAlice Michael 	iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
7928be454c9SAlice Michael 		   "AQTX: desc and buffer writeback:\n");
7938be454c9SAlice Michael 	iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
7948be454c9SAlice Michael 
7958be454c9SAlice Michael 	/* save writeback aq if requested */
7968be454c9SAlice Michael 	if (details->wb_desc)
7978be454c9SAlice Michael 		*details->wb_desc = *desc_on_ring;
7988be454c9SAlice Michael 
7998be454c9SAlice Michael 	/* update the error if time out occurred */
8008be454c9SAlice Michael 	if ((!cmd_completed) &&
8018be454c9SAlice Michael 	    (!details->async && !details->postpone)) {
8028be454c9SAlice Michael 		if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {
8038be454c9SAlice Michael 			iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
8048be454c9SAlice Michael 				   "AQTX: AQ Critical error.\n");
8058821b3faSAlice Michael 			status = IAVF_ERR_ADMIN_QUEUE_CRITICAL_ERROR;
8068be454c9SAlice Michael 		} else {
8078be454c9SAlice Michael 			iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
8088be454c9SAlice Michael 				   "AQTX: Writeback timeout.\n");
8098821b3faSAlice Michael 			status = IAVF_ERR_ADMIN_QUEUE_TIMEOUT;
8108be454c9SAlice Michael 		}
8118be454c9SAlice Michael 	}
8128be454c9SAlice Michael 
8138be454c9SAlice Michael asq_send_command_error:
8148be454c9SAlice Michael 	mutex_unlock(&hw->aq.asq_mutex);
8158be454c9SAlice Michael 	return status;
8168be454c9SAlice Michael }
8178be454c9SAlice Michael 
8188be454c9SAlice Michael /**
8198be454c9SAlice Michael  *  iavf_fill_default_direct_cmd_desc - AQ descriptor helper function
8208be454c9SAlice Michael  *  @desc:     pointer to the temp descriptor (non DMA mem)
8218be454c9SAlice Michael  *  @opcode:   the opcode can be used to decide which flags to turn off or on
8228be454c9SAlice Michael  *
8238be454c9SAlice Michael  *  Fill the desc with default values
8248be454c9SAlice Michael  **/
8257af36e32SAlice Michael void iavf_fill_default_direct_cmd_desc(struct iavf_aq_desc *desc, u16 opcode)
8268be454c9SAlice Michael {
8278be454c9SAlice Michael 	/* zero out the desc */
8287af36e32SAlice Michael 	memset((void *)desc, 0, sizeof(struct iavf_aq_desc));
8298be454c9SAlice Michael 	desc->opcode = cpu_to_le16(opcode);
8307af36e32SAlice Michael 	desc->flags = cpu_to_le16(IAVF_AQ_FLAG_SI);
8318be454c9SAlice Michael }
8328be454c9SAlice Michael 
8338be454c9SAlice Michael /**
8348be454c9SAlice Michael  *  iavf_clean_arq_element
8358be454c9SAlice Michael  *  @hw: pointer to the hw struct
8368be454c9SAlice Michael  *  @e: event info from the receive descriptor, includes any buffers
8378be454c9SAlice Michael  *  @pending: number of events that could be left to process
8388be454c9SAlice Michael  *
8398be454c9SAlice Michael  *  This function cleans one Admin Receive Queue element and returns
8408be454c9SAlice Michael  *  the contents through e.  It can also return how many events are
8418be454c9SAlice Michael  *  left to process through 'pending'
8428be454c9SAlice Michael  **/
84380754bbcSSergey Nemov enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
8447af36e32SAlice Michael 					struct iavf_arq_event_info *e,
8458be454c9SAlice Michael 					u16 *pending)
8468be454c9SAlice Michael {
8478be454c9SAlice Michael 	u16 ntc = hw->aq.arq.next_to_clean;
8487af36e32SAlice Michael 	struct iavf_aq_desc *desc;
84980754bbcSSergey Nemov 	enum iavf_status ret_code = 0;
8508be454c9SAlice Michael 	struct iavf_dma_mem *bi;
8518be454c9SAlice Michael 	u16 desc_idx;
8528be454c9SAlice Michael 	u16 datalen;
8538be454c9SAlice Michael 	u16 flags;
8548be454c9SAlice Michael 	u16 ntu;
8558be454c9SAlice Michael 
8568be454c9SAlice Michael 	/* pre-clean the event info */
8578be454c9SAlice Michael 	memset(&e->desc, 0, sizeof(e->desc));
8588be454c9SAlice Michael 
8598be454c9SAlice Michael 	/* take the lock before we start messing with the ring */
8608be454c9SAlice Michael 	mutex_lock(&hw->aq.arq_mutex);
8618be454c9SAlice Michael 
8628be454c9SAlice Michael 	if (hw->aq.arq.count == 0) {
8638be454c9SAlice Michael 		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
8648be454c9SAlice Michael 			   "AQRX: Admin queue not initialized.\n");
8658821b3faSAlice Michael 		ret_code = IAVF_ERR_QUEUE_EMPTY;
8668be454c9SAlice Michael 		goto clean_arq_element_err;
8678be454c9SAlice Michael 	}
8688be454c9SAlice Michael 
8698be454c9SAlice Michael 	/* set next_to_use to head */
8708be454c9SAlice Michael 	ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;
8718be454c9SAlice Michael 	if (ntu == ntc) {
8728be454c9SAlice Michael 		/* nothing to do - shouldn't need to update ring's values */
8738821b3faSAlice Michael 		ret_code = IAVF_ERR_ADMIN_QUEUE_NO_WORK;
8748be454c9SAlice Michael 		goto clean_arq_element_out;
8758be454c9SAlice Michael 	}
8768be454c9SAlice Michael 
8778be454c9SAlice Michael 	/* now clean the next descriptor */
8788be454c9SAlice Michael 	desc = IAVF_ADMINQ_DESC(hw->aq.arq, ntc);
8798be454c9SAlice Michael 	desc_idx = ntc;
8808be454c9SAlice Michael 
8818be454c9SAlice Michael 	hw->aq.arq_last_status =
8827af36e32SAlice Michael 		(enum iavf_admin_queue_err)le16_to_cpu(desc->retval);
8838be454c9SAlice Michael 	flags = le16_to_cpu(desc->flags);
8847af36e32SAlice Michael 	if (flags & IAVF_AQ_FLAG_ERR) {
8858821b3faSAlice Michael 		ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
8868be454c9SAlice Michael 		iavf_debug(hw,
8878be454c9SAlice Michael 			   IAVF_DEBUG_AQ_MESSAGE,
8888be454c9SAlice Michael 			   "AQRX: Event received with error 0x%X.\n",
8898be454c9SAlice Michael 			   hw->aq.arq_last_status);
8908be454c9SAlice Michael 	}
8918be454c9SAlice Michael 
8928be454c9SAlice Michael 	e->desc = *desc;
8938be454c9SAlice Michael 	datalen = le16_to_cpu(desc->datalen);
8948be454c9SAlice Michael 	e->msg_len = min(datalen, e->buf_len);
8958be454c9SAlice Michael 	if (e->msg_buf && (e->msg_len != 0))
8968be454c9SAlice Michael 		memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
8978be454c9SAlice Michael 		       e->msg_len);
8988be454c9SAlice Michael 
8998be454c9SAlice Michael 	iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
9008be454c9SAlice Michael 	iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
9018be454c9SAlice Michael 		      hw->aq.arq_buf_size);
9028be454c9SAlice Michael 
9038be454c9SAlice Michael 	/* Restore the original datalen and buffer address in the desc,
9048be454c9SAlice Michael 	 * FW updates datalen to indicate the event message
9058be454c9SAlice Michael 	 * size
9068be454c9SAlice Michael 	 */
9078be454c9SAlice Michael 	bi = &hw->aq.arq.r.arq_bi[ntc];
9087af36e32SAlice Michael 	memset((void *)desc, 0, sizeof(struct iavf_aq_desc));
9098be454c9SAlice Michael 
9107af36e32SAlice Michael 	desc->flags = cpu_to_le16(IAVF_AQ_FLAG_BUF);
9117af36e32SAlice Michael 	if (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF)
9127af36e32SAlice Michael 		desc->flags |= cpu_to_le16(IAVF_AQ_FLAG_LB);
9138be454c9SAlice Michael 	desc->datalen = cpu_to_le16((u16)bi->size);
9148be454c9SAlice Michael 	desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
9158be454c9SAlice Michael 	desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
9168be454c9SAlice Michael 
9178be454c9SAlice Michael 	/* set tail = the last cleaned desc index. */
9188be454c9SAlice Michael 	wr32(hw, hw->aq.arq.tail, ntc);
9198be454c9SAlice Michael 	/* ntc is updated to tail + 1 */
9208be454c9SAlice Michael 	ntc++;
9218be454c9SAlice Michael 	if (ntc == hw->aq.num_arq_entries)
9228be454c9SAlice Michael 		ntc = 0;
9238be454c9SAlice Michael 	hw->aq.arq.next_to_clean = ntc;
9248be454c9SAlice Michael 	hw->aq.arq.next_to_use = ntu;
9258be454c9SAlice Michael 
9268be454c9SAlice Michael clean_arq_element_out:
9278be454c9SAlice Michael 	/* Set pending if needed, unlock and return */
9288be454c9SAlice Michael 	if (pending)
9298be454c9SAlice Michael 		*pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
9308be454c9SAlice Michael 
9318be454c9SAlice Michael clean_arq_element_err:
9328be454c9SAlice Michael 	mutex_unlock(&hw->aq.arq_mutex);
9338be454c9SAlice Michael 
9348be454c9SAlice Michael 	return ret_code;
9358be454c9SAlice Michael }
936