1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include <linux/bpf_trace.h> 5 #include <linux/net/intel/libie/pctype.h> 6 #include <linux/net/intel/libie/rx.h> 7 #include <linux/prefetch.h> 8 #include <linux/sctp.h> 9 #include <net/mpls.h> 10 #include <net/xdp.h> 11 #include "i40e_txrx_common.h" 12 #include "i40e_trace.h" 13 #include "i40e_xsk.h" 14 15 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) 16 /** 17 * i40e_fdir - Generate a Flow Director descriptor based on fdata 18 * @tx_ring: Tx ring to send buffer on 19 * @fdata: Flow director filter data 20 * @add: Indicate if we are adding a rule or deleting one 21 * 22 **/ 23 static void i40e_fdir(struct i40e_ring *tx_ring, 24 struct i40e_fdir_filter *fdata, bool add) 25 { 26 struct i40e_filter_program_desc *fdir_desc; 27 struct i40e_pf *pf = tx_ring->vsi->back; 28 u32 flex_ptype, dtype_cmd, vsi_id; 29 u16 i; 30 31 /* grab the next descriptor */ 32 i = tx_ring->next_to_use; 33 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 34 35 i++; 36 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 37 38 flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK, fdata->q_index); 39 40 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_FLEXOFF_MASK, 41 fdata->flex_off); 42 43 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_PCTYPE_MASK, fdata->pctype); 44 45 /* Use LAN VSI Id if not programmed by user */ 46 vsi_id = fdata->dest_vsi ? : i40e_pf_get_main_vsi(pf)->id; 47 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_DEST_VSI_MASK, vsi_id); 48 49 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 50 51 dtype_cmd |= add ? 52 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 53 I40E_TXD_FLTR_QW1_PCMD_SHIFT : 54 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 55 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 56 57 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_DEST_MASK, fdata->dest_ctl); 58 59 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_FD_STATUS_MASK, 60 fdata->fd_status); 61 62 if (fdata->cnt_index) { 63 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 64 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK, 65 fdata->cnt_index); 66 } 67 68 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 69 fdir_desc->rsvd = cpu_to_le32(0); 70 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 71 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id); 72 } 73 74 #define I40E_FD_CLEAN_DELAY 10 75 /** 76 * i40e_program_fdir_filter - Program a Flow Director filter 77 * @fdir_data: Packet data that will be filter parameters 78 * @raw_packet: the pre-allocated packet buffer for FDir 79 * @pf: The PF pointer 80 * @add: True for add/update, False for remove 81 **/ 82 static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, 83 u8 *raw_packet, struct i40e_pf *pf, 84 bool add) 85 { 86 struct i40e_tx_buffer *tx_buf, *first; 87 struct i40e_tx_desc *tx_desc; 88 struct i40e_ring *tx_ring; 89 struct i40e_vsi *vsi; 90 struct device *dev; 91 dma_addr_t dma; 92 u32 td_cmd = 0; 93 u16 i; 94 95 /* find existing FDIR VSI */ 96 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); 97 if (!vsi) 98 return -ENOENT; 99 100 tx_ring = vsi->tx_rings[0]; 101 dev = tx_ring->dev; 102 103 /* we need two descriptors to add/del a filter and we can wait */ 104 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) { 105 if (!i) 106 return -EAGAIN; 107 msleep_interruptible(1); 108 } 109 110 dma = dma_map_single(dev, raw_packet, 111 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); 112 if (dma_mapping_error(dev, dma)) 113 goto dma_fail; 114 115 /* grab the next descriptor */ 116 i = tx_ring->next_to_use; 117 first = &tx_ring->tx_bi[i]; 118 i40e_fdir(tx_ring, fdir_data, add); 119 120 /* Now program a dummy descriptor */ 121 i = tx_ring->next_to_use; 122 tx_desc = I40E_TX_DESC(tx_ring, i); 123 tx_buf = &tx_ring->tx_bi[i]; 124 125 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 126 127 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); 128 129 /* record length, and DMA address */ 130 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); 131 dma_unmap_addr_set(tx_buf, dma, dma); 132 133 tx_desc->buffer_addr = cpu_to_le64(dma); 134 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; 135 136 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; 137 tx_buf->raw_buf = (void *)raw_packet; 138 139 tx_desc->cmd_type_offset_bsz = 140 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); 141 142 /* Force memory writes to complete before letting h/w 143 * know there are new descriptors to fetch. 144 */ 145 wmb(); 146 147 /* Mark the data descriptor to be watched */ 148 first->next_to_watch = tx_desc; 149 150 writel(tx_ring->next_to_use, tx_ring->tail); 151 return 0; 152 153 dma_fail: 154 return -1; 155 } 156 157 /** 158 * i40e_create_dummy_packet - Constructs dummy packet for HW 159 * @dummy_packet: preallocated space for dummy packet 160 * @ipv4: is layer 3 packet of version 4 or 6 161 * @l4proto: next level protocol used in data portion of l3 162 * @data: filter data 163 * 164 * Returns address of layer 4 protocol dummy packet. 165 **/ 166 static char *i40e_create_dummy_packet(u8 *dummy_packet, bool ipv4, u8 l4proto, 167 struct i40e_fdir_filter *data) 168 { 169 bool is_vlan = !!data->vlan_tag; 170 struct vlan_hdr vlan = {}; 171 struct ipv6hdr ipv6 = {}; 172 struct ethhdr eth = {}; 173 struct iphdr ip = {}; 174 u8 *tmp; 175 176 if (ipv4) { 177 eth.h_proto = cpu_to_be16(ETH_P_IP); 178 ip.protocol = l4proto; 179 ip.version = 0x4; 180 ip.ihl = 0x5; 181 182 ip.daddr = data->dst_ip; 183 ip.saddr = data->src_ip; 184 } else { 185 eth.h_proto = cpu_to_be16(ETH_P_IPV6); 186 ipv6.nexthdr = l4proto; 187 ipv6.version = 0x6; 188 189 memcpy(&ipv6.saddr.in6_u.u6_addr32, data->src_ip6, 190 sizeof(__be32) * 4); 191 memcpy(&ipv6.daddr.in6_u.u6_addr32, data->dst_ip6, 192 sizeof(__be32) * 4); 193 } 194 195 if (is_vlan) { 196 vlan.h_vlan_TCI = data->vlan_tag; 197 vlan.h_vlan_encapsulated_proto = eth.h_proto; 198 eth.h_proto = data->vlan_etype; 199 } 200 201 tmp = dummy_packet; 202 memcpy(tmp, ð, sizeof(eth)); 203 tmp += sizeof(eth); 204 205 if (is_vlan) { 206 memcpy(tmp, &vlan, sizeof(vlan)); 207 tmp += sizeof(vlan); 208 } 209 210 if (ipv4) { 211 memcpy(tmp, &ip, sizeof(ip)); 212 tmp += sizeof(ip); 213 } else { 214 memcpy(tmp, &ipv6, sizeof(ipv6)); 215 tmp += sizeof(ipv6); 216 } 217 218 return tmp; 219 } 220 221 /** 222 * i40e_create_dummy_udp_packet - helper function to create UDP packet 223 * @raw_packet: preallocated space for dummy packet 224 * @ipv4: is layer 3 packet of version 4 or 6 225 * @l4proto: next level protocol used in data portion of l3 226 * @data: filter data 227 * 228 * Helper function to populate udp fields. 229 **/ 230 static void i40e_create_dummy_udp_packet(u8 *raw_packet, bool ipv4, u8 l4proto, 231 struct i40e_fdir_filter *data) 232 { 233 struct udphdr *udp; 234 u8 *tmp; 235 236 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_UDP, data); 237 udp = (struct udphdr *)(tmp); 238 udp->dest = data->dst_port; 239 udp->source = data->src_port; 240 } 241 242 /** 243 * i40e_create_dummy_tcp_packet - helper function to create TCP packet 244 * @raw_packet: preallocated space for dummy packet 245 * @ipv4: is layer 3 packet of version 4 or 6 246 * @l4proto: next level protocol used in data portion of l3 247 * @data: filter data 248 * 249 * Helper function to populate tcp fields. 250 **/ 251 static void i40e_create_dummy_tcp_packet(u8 *raw_packet, bool ipv4, u8 l4proto, 252 struct i40e_fdir_filter *data) 253 { 254 struct tcphdr *tcp; 255 u8 *tmp; 256 /* Dummy tcp packet */ 257 static const char tcp_packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 258 0x50, 0x11, 0x0, 0x72, 0, 0, 0, 0}; 259 260 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_TCP, data); 261 262 tcp = (struct tcphdr *)tmp; 263 memcpy(tcp, tcp_packet, sizeof(tcp_packet)); 264 tcp->dest = data->dst_port; 265 tcp->source = data->src_port; 266 } 267 268 /** 269 * i40e_create_dummy_sctp_packet - helper function to create SCTP packet 270 * @raw_packet: preallocated space for dummy packet 271 * @ipv4: is layer 3 packet of version 4 or 6 272 * @l4proto: next level protocol used in data portion of l3 273 * @data: filter data 274 * 275 * Helper function to populate sctp fields. 276 **/ 277 static void i40e_create_dummy_sctp_packet(u8 *raw_packet, bool ipv4, 278 u8 l4proto, 279 struct i40e_fdir_filter *data) 280 { 281 struct sctphdr *sctp; 282 u8 *tmp; 283 284 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_SCTP, data); 285 286 sctp = (struct sctphdr *)tmp; 287 sctp->dest = data->dst_port; 288 sctp->source = data->src_port; 289 } 290 291 /** 292 * i40e_prepare_fdir_filter - Prepare and program fdir filter 293 * @pf: physical function to attach filter to 294 * @fd_data: filter data 295 * @add: add or delete filter 296 * @packet_addr: address of dummy packet, used in filtering 297 * @payload_offset: offset from dummy packet address to user defined data 298 * @pctype: Packet type for which filter is used 299 * 300 * Helper function to offset data of dummy packet, program it and 301 * handle errors. 302 **/ 303 static int i40e_prepare_fdir_filter(struct i40e_pf *pf, 304 struct i40e_fdir_filter *fd_data, 305 bool add, char *packet_addr, 306 int payload_offset, u8 pctype) 307 { 308 int ret; 309 310 if (fd_data->flex_filter) { 311 u8 *payload; 312 __be16 pattern = fd_data->flex_word; 313 u16 off = fd_data->flex_offset; 314 315 payload = packet_addr + payload_offset; 316 317 /* If user provided vlan, offset payload by vlan header length */ 318 if (!!fd_data->vlan_tag) 319 payload += VLAN_HLEN; 320 321 *((__force __be16 *)(payload + off)) = pattern; 322 } 323 324 fd_data->pctype = pctype; 325 ret = i40e_program_fdir_filter(fd_data, packet_addr, pf, add); 326 if (ret) { 327 dev_info(&pf->pdev->dev, 328 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 329 fd_data->pctype, fd_data->fd_id, ret); 330 /* Free the packet buffer since it wasn't added to the ring */ 331 return -EOPNOTSUPP; 332 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 333 if (add) 334 dev_info(&pf->pdev->dev, 335 "Filter OK for PCTYPE %d loc = %d\n", 336 fd_data->pctype, fd_data->fd_id); 337 else 338 dev_info(&pf->pdev->dev, 339 "Filter deleted for PCTYPE %d loc = %d\n", 340 fd_data->pctype, fd_data->fd_id); 341 } 342 343 return ret; 344 } 345 346 /** 347 * i40e_change_filter_num - Prepare and program fdir filter 348 * @ipv4: is layer 3 packet of version 4 or 6 349 * @add: add or delete filter 350 * @ipv4_filter_num: field to update 351 * @ipv6_filter_num: field to update 352 * 353 * Update filter number field for pf. 354 **/ 355 static void i40e_change_filter_num(bool ipv4, bool add, u16 *ipv4_filter_num, 356 u16 *ipv6_filter_num) 357 { 358 if (add) { 359 if (ipv4) 360 (*ipv4_filter_num)++; 361 else 362 (*ipv6_filter_num)++; 363 } else { 364 if (ipv4) 365 (*ipv4_filter_num)--; 366 else 367 (*ipv6_filter_num)--; 368 } 369 } 370 371 #define I40E_UDPIP_DUMMY_PACKET_LEN 42 372 #define I40E_UDPIP6_DUMMY_PACKET_LEN 62 373 /** 374 * i40e_add_del_fdir_udp - Add/Remove UDP filters 375 * @vsi: pointer to the targeted VSI 376 * @fd_data: the flow director data required for the FDir descriptor 377 * @add: true adds a filter, false removes it 378 * @ipv4: true is v4, false is v6 379 * 380 * Returns 0 if the filters were successfully added or removed 381 **/ 382 static int i40e_add_del_fdir_udp(struct i40e_vsi *vsi, 383 struct i40e_fdir_filter *fd_data, 384 bool add, 385 bool ipv4) 386 { 387 struct i40e_pf *pf = vsi->back; 388 u8 *raw_packet; 389 int ret; 390 391 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 392 if (!raw_packet) 393 return -ENOMEM; 394 395 i40e_create_dummy_udp_packet(raw_packet, ipv4, IPPROTO_UDP, fd_data); 396 397 if (ipv4) 398 ret = i40e_prepare_fdir_filter 399 (pf, fd_data, add, raw_packet, 400 I40E_UDPIP_DUMMY_PACKET_LEN, 401 LIBIE_FILTER_PCTYPE_NONF_IPV4_UDP); 402 else 403 ret = i40e_prepare_fdir_filter 404 (pf, fd_data, add, raw_packet, 405 I40E_UDPIP6_DUMMY_PACKET_LEN, 406 LIBIE_FILTER_PCTYPE_NONF_IPV6_UDP); 407 408 if (ret) { 409 kfree(raw_packet); 410 return ret; 411 } 412 413 i40e_change_filter_num(ipv4, add, &pf->fd_udp4_filter_cnt, 414 &pf->fd_udp6_filter_cnt); 415 416 return 0; 417 } 418 419 #define I40E_TCPIP_DUMMY_PACKET_LEN 54 420 #define I40E_TCPIP6_DUMMY_PACKET_LEN 74 421 /** 422 * i40e_add_del_fdir_tcp - Add/Remove TCPv4 filters 423 * @vsi: pointer to the targeted VSI 424 * @fd_data: the flow director data required for the FDir descriptor 425 * @add: true adds a filter, false removes it 426 * @ipv4: true is v4, false is v6 427 * 428 * Returns 0 if the filters were successfully added or removed 429 **/ 430 static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi, 431 struct i40e_fdir_filter *fd_data, 432 bool add, 433 bool ipv4) 434 { 435 struct i40e_pf *pf = vsi->back; 436 u8 *raw_packet; 437 int ret; 438 439 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 440 if (!raw_packet) 441 return -ENOMEM; 442 443 i40e_create_dummy_tcp_packet(raw_packet, ipv4, IPPROTO_TCP, fd_data); 444 if (ipv4) 445 ret = i40e_prepare_fdir_filter 446 (pf, fd_data, add, raw_packet, 447 I40E_TCPIP_DUMMY_PACKET_LEN, 448 LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP); 449 else 450 ret = i40e_prepare_fdir_filter 451 (pf, fd_data, add, raw_packet, 452 I40E_TCPIP6_DUMMY_PACKET_LEN, 453 LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP); 454 455 if (ret) { 456 kfree(raw_packet); 457 return ret; 458 } 459 460 i40e_change_filter_num(ipv4, add, &pf->fd_tcp4_filter_cnt, 461 &pf->fd_tcp6_filter_cnt); 462 463 if (add) { 464 if (test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags) && 465 I40E_DEBUG_FD & pf->hw.debug_mask) 466 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); 467 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); 468 } 469 return 0; 470 } 471 472 #define I40E_SCTPIP_DUMMY_PACKET_LEN 46 473 #define I40E_SCTPIP6_DUMMY_PACKET_LEN 66 474 /** 475 * i40e_add_del_fdir_sctp - Add/Remove SCTPv4 Flow Director filters for 476 * a specific flow spec 477 * @vsi: pointer to the targeted VSI 478 * @fd_data: the flow director data required for the FDir descriptor 479 * @add: true adds a filter, false removes it 480 * @ipv4: true is v4, false is v6 481 * 482 * Returns 0 if the filters were successfully added or removed 483 **/ 484 static int i40e_add_del_fdir_sctp(struct i40e_vsi *vsi, 485 struct i40e_fdir_filter *fd_data, 486 bool add, 487 bool ipv4) 488 { 489 struct i40e_pf *pf = vsi->back; 490 u8 *raw_packet; 491 int ret; 492 493 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 494 if (!raw_packet) 495 return -ENOMEM; 496 497 i40e_create_dummy_sctp_packet(raw_packet, ipv4, IPPROTO_SCTP, fd_data); 498 499 if (ipv4) 500 ret = i40e_prepare_fdir_filter 501 (pf, fd_data, add, raw_packet, 502 I40E_SCTPIP_DUMMY_PACKET_LEN, 503 LIBIE_FILTER_PCTYPE_NONF_IPV4_SCTP); 504 else 505 ret = i40e_prepare_fdir_filter 506 (pf, fd_data, add, raw_packet, 507 I40E_SCTPIP6_DUMMY_PACKET_LEN, 508 LIBIE_FILTER_PCTYPE_NONF_IPV6_SCTP); 509 510 if (ret) { 511 kfree(raw_packet); 512 return ret; 513 } 514 515 i40e_change_filter_num(ipv4, add, &pf->fd_sctp4_filter_cnt, 516 &pf->fd_sctp6_filter_cnt); 517 518 return 0; 519 } 520 521 #define I40E_IP_DUMMY_PACKET_LEN 34 522 #define I40E_IP6_DUMMY_PACKET_LEN 54 523 /** 524 * i40e_add_del_fdir_ip - Add/Remove IPv4 Flow Director filters for 525 * a specific flow spec 526 * @vsi: pointer to the targeted VSI 527 * @fd_data: the flow director data required for the FDir descriptor 528 * @add: true adds a filter, false removes it 529 * @ipv4: true is v4, false is v6 530 * 531 * Returns 0 if the filters were successfully added or removed 532 **/ 533 static int i40e_add_del_fdir_ip(struct i40e_vsi *vsi, 534 struct i40e_fdir_filter *fd_data, 535 bool add, 536 bool ipv4) 537 { 538 struct i40e_pf *pf = vsi->back; 539 int payload_offset; 540 u8 *raw_packet; 541 int iter_start; 542 int iter_end; 543 int ret; 544 int i; 545 546 if (ipv4) { 547 iter_start = LIBIE_FILTER_PCTYPE_NONF_IPV4_OTHER; 548 iter_end = LIBIE_FILTER_PCTYPE_FRAG_IPV4; 549 } else { 550 iter_start = LIBIE_FILTER_PCTYPE_NONF_IPV6_OTHER; 551 iter_end = LIBIE_FILTER_PCTYPE_FRAG_IPV6; 552 } 553 554 for (i = iter_start; i <= iter_end; i++) { 555 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 556 if (!raw_packet) 557 return -ENOMEM; 558 559 /* IPv6 no header option differs from IPv4 */ 560 (void)i40e_create_dummy_packet 561 (raw_packet, ipv4, (ipv4) ? IPPROTO_IP : IPPROTO_NONE, 562 fd_data); 563 564 payload_offset = (ipv4) ? I40E_IP_DUMMY_PACKET_LEN : 565 I40E_IP6_DUMMY_PACKET_LEN; 566 ret = i40e_prepare_fdir_filter(pf, fd_data, add, raw_packet, 567 payload_offset, i); 568 if (ret) 569 goto err; 570 } 571 572 i40e_change_filter_num(ipv4, add, &pf->fd_ip4_filter_cnt, 573 &pf->fd_ip6_filter_cnt); 574 575 return 0; 576 err: 577 kfree(raw_packet); 578 return ret; 579 } 580 581 /** 582 * i40e_add_del_fdir - Build raw packets to add/del fdir filter 583 * @vsi: pointer to the targeted VSI 584 * @input: filter to add or delete 585 * @add: true adds a filter, false removes it 586 * 587 **/ 588 int i40e_add_del_fdir(struct i40e_vsi *vsi, 589 struct i40e_fdir_filter *input, bool add) 590 { 591 enum ip_ver { ipv6 = 0, ipv4 = 1 }; 592 struct i40e_pf *pf = vsi->back; 593 int ret; 594 595 switch (input->flow_type & ~FLOW_EXT) { 596 case TCP_V4_FLOW: 597 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4); 598 break; 599 case UDP_V4_FLOW: 600 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4); 601 break; 602 case SCTP_V4_FLOW: 603 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4); 604 break; 605 case TCP_V6_FLOW: 606 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6); 607 break; 608 case UDP_V6_FLOW: 609 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6); 610 break; 611 case SCTP_V6_FLOW: 612 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6); 613 break; 614 case IP_USER_FLOW: 615 switch (input->ipl4_proto) { 616 case IPPROTO_TCP: 617 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4); 618 break; 619 case IPPROTO_UDP: 620 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4); 621 break; 622 case IPPROTO_SCTP: 623 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4); 624 break; 625 case IPPROTO_IP: 626 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv4); 627 break; 628 default: 629 /* We cannot support masking based on protocol */ 630 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n", 631 input->ipl4_proto); 632 return -EINVAL; 633 } 634 break; 635 case IPV6_USER_FLOW: 636 switch (input->ipl4_proto) { 637 case IPPROTO_TCP: 638 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6); 639 break; 640 case IPPROTO_UDP: 641 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6); 642 break; 643 case IPPROTO_SCTP: 644 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6); 645 break; 646 case IPPROTO_IP: 647 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv6); 648 break; 649 default: 650 /* We cannot support masking based on protocol */ 651 dev_info(&pf->pdev->dev, "Unsupported IPv6 protocol 0x%02x\n", 652 input->ipl4_proto); 653 return -EINVAL; 654 } 655 break; 656 default: 657 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n", 658 input->flow_type); 659 return -EINVAL; 660 } 661 662 /* The buffer allocated here will be normally be freed by 663 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit 664 * completion. In the event of an error adding the buffer to the FDIR 665 * ring, it will immediately be freed. It may also be freed by 666 * i40e_clean_tx_ring() when closing the VSI. 667 */ 668 return ret; 669 } 670 671 /** 672 * i40e_fd_handle_status - check the Programming Status for FD 673 * @rx_ring: the Rx ring for this descriptor 674 * @qword0_raw: qword0 675 * @qword1: qword1 after le_to_cpu 676 * @prog_id: the id originally used for programming 677 * 678 * This is used to verify if the FD programming or invalidation 679 * requested by SW to the HW is successful or not and take actions accordingly. 680 **/ 681 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw, 682 u64 qword1, u8 prog_id) 683 { 684 struct i40e_pf *pf = rx_ring->vsi->back; 685 struct pci_dev *pdev = pf->pdev; 686 struct i40e_16b_rx_wb_qw0 *qw0; 687 u32 fcnt_prog, fcnt_avail; 688 u32 error; 689 690 qw0 = (struct i40e_16b_rx_wb_qw0 *)&qword0_raw; 691 error = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK, qword1); 692 693 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { 694 pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id); 695 if (qw0->hi_dword.fd_id != 0 || 696 (I40E_DEBUG_FD & pf->hw.debug_mask)) 697 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", 698 pf->fd_inv); 699 700 /* Check if the programming error is for ATR. 701 * If so, auto disable ATR and set a state for 702 * flush in progress. Next time we come here if flush is in 703 * progress do nothing, once flush is complete the state will 704 * be cleared. 705 */ 706 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) 707 return; 708 709 pf->fd_add_err++; 710 /* store the current atr filter count */ 711 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); 712 713 if (qw0->hi_dword.fd_id == 0 && 714 test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) { 715 /* These set_bit() calls aren't atomic with the 716 * test_bit() here, but worse case we potentially 717 * disable ATR and queue a flush right after SB 718 * support is re-enabled. That shouldn't cause an 719 * issue in practice 720 */ 721 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); 722 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); 723 } 724 725 /* filter programming failed most likely due to table full */ 726 fcnt_prog = i40e_get_global_fd_count(pf); 727 fcnt_avail = pf->fdir_pf_filter_count; 728 /* If ATR is running fcnt_prog can quickly change, 729 * if we are very close to full, it makes sense to disable 730 * FD ATR/SB and then re-enable it when there is room. 731 */ 732 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { 733 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags) && 734 !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED, 735 pf->state)) 736 if (I40E_DEBUG_FD & pf->hw.debug_mask) 737 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); 738 } 739 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { 740 if (I40E_DEBUG_FD & pf->hw.debug_mask) 741 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", 742 qw0->hi_dword.fd_id); 743 } 744 } 745 746 /** 747 * i40e_unmap_and_free_tx_resource - Release a Tx buffer 748 * @ring: the ring that owns the buffer 749 * @tx_buffer: the buffer to free 750 **/ 751 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, 752 struct i40e_tx_buffer *tx_buffer) 753 { 754 if (tx_buffer->skb) { 755 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) 756 kfree(tx_buffer->raw_buf); 757 else if (ring_is_xdp(ring)) 758 xdp_return_frame(tx_buffer->xdpf); 759 else 760 dev_kfree_skb_any(tx_buffer->skb); 761 if (dma_unmap_len(tx_buffer, len)) 762 dma_unmap_single(ring->dev, 763 dma_unmap_addr(tx_buffer, dma), 764 dma_unmap_len(tx_buffer, len), 765 DMA_TO_DEVICE); 766 } else if (dma_unmap_len(tx_buffer, len)) { 767 dma_unmap_page(ring->dev, 768 dma_unmap_addr(tx_buffer, dma), 769 dma_unmap_len(tx_buffer, len), 770 DMA_TO_DEVICE); 771 } 772 773 tx_buffer->next_to_watch = NULL; 774 tx_buffer->skb = NULL; 775 dma_unmap_len_set(tx_buffer, len, 0); 776 /* tx_buffer must be completely set up in the transmit path */ 777 } 778 779 /** 780 * i40e_clean_tx_ring - Free any empty Tx buffers 781 * @tx_ring: ring to be cleaned 782 **/ 783 void i40e_clean_tx_ring(struct i40e_ring *tx_ring) 784 { 785 unsigned long bi_size; 786 u16 i; 787 788 if (ring_is_xdp(tx_ring) && tx_ring->xsk_pool) { 789 i40e_xsk_clean_tx_ring(tx_ring); 790 } else { 791 /* ring already cleared, nothing to do */ 792 if (!tx_ring->tx_bi) 793 return; 794 795 /* Free all the Tx ring sk_buffs */ 796 for (i = 0; i < tx_ring->count; i++) 797 i40e_unmap_and_free_tx_resource(tx_ring, 798 &tx_ring->tx_bi[i]); 799 } 800 801 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 802 memset(tx_ring->tx_bi, 0, bi_size); 803 804 /* Zero out the descriptor ring */ 805 memset(tx_ring->desc, 0, tx_ring->size); 806 807 tx_ring->next_to_use = 0; 808 tx_ring->next_to_clean = 0; 809 810 if (!tx_ring->netdev) 811 return; 812 813 /* cleanup Tx queue statistics */ 814 netdev_tx_reset_queue(txring_txq(tx_ring)); 815 } 816 817 /** 818 * i40e_free_tx_resources - Free Tx resources per queue 819 * @tx_ring: Tx descriptor ring for a specific queue 820 * 821 * Free all transmit software resources 822 **/ 823 void i40e_free_tx_resources(struct i40e_ring *tx_ring) 824 { 825 i40e_clean_tx_ring(tx_ring); 826 kfree(tx_ring->tx_bi); 827 tx_ring->tx_bi = NULL; 828 829 if (tx_ring->desc) { 830 dma_free_coherent(tx_ring->dev, tx_ring->size, 831 tx_ring->desc, tx_ring->dma); 832 tx_ring->desc = NULL; 833 } 834 } 835 836 /** 837 * i40e_get_tx_pending - how many tx descriptors not processed 838 * @ring: the ring of descriptors 839 * @in_sw: use SW variables 840 * 841 * Since there is no access to the ring head register 842 * in XL710, we need to use our local copies 843 **/ 844 u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw) 845 { 846 u32 head, tail; 847 848 if (!in_sw) { 849 head = i40e_get_head(ring); 850 tail = readl(ring->tail); 851 } else { 852 head = ring->next_to_clean; 853 tail = ring->next_to_use; 854 } 855 856 if (head != tail) 857 return (head < tail) ? 858 tail - head : (tail + ring->count - head); 859 860 return 0; 861 } 862 863 /** 864 * i40e_detect_recover_hung - Function to detect and recover hung_queues 865 * @pf: pointer to PF struct 866 * 867 * LAN VSI has netdev and netdev has TX queues. This function is to check 868 * each of those TX queues if they are hung, trigger recovery by issuing 869 * SW interrupt. 870 **/ 871 void i40e_detect_recover_hung(struct i40e_pf *pf) 872 { 873 struct i40e_vsi *vsi = i40e_pf_get_main_vsi(pf); 874 struct i40e_ring *tx_ring = NULL; 875 struct net_device *netdev; 876 unsigned int i; 877 int packets; 878 879 if (!vsi) 880 return; 881 882 if (test_bit(__I40E_VSI_DOWN, vsi->state)) 883 return; 884 885 netdev = vsi->netdev; 886 if (!netdev) 887 return; 888 889 if (!netif_carrier_ok(netdev)) 890 return; 891 892 for (i = 0; i < vsi->num_queue_pairs; i++) { 893 tx_ring = vsi->tx_rings[i]; 894 if (tx_ring && tx_ring->desc) { 895 /* If packet counter has not changed the queue is 896 * likely stalled, so force an interrupt for this 897 * queue. 898 * 899 * prev_pkt_ctr would be negative if there was no 900 * pending work. 901 */ 902 packets = tx_ring->stats.packets & INT_MAX; 903 if (tx_ring->tx_stats.prev_pkt_ctr == packets) { 904 i40e_force_wb(vsi, tx_ring->q_vector); 905 continue; 906 } 907 908 /* Memory barrier between read of packet count and call 909 * to i40e_get_tx_pending() 910 */ 911 smp_rmb(); 912 tx_ring->tx_stats.prev_pkt_ctr = 913 i40e_get_tx_pending(tx_ring, true) ? packets : -1; 914 } 915 } 916 } 917 918 /** 919 * i40e_clean_tx_irq - Reclaim resources after transmit completes 920 * @vsi: the VSI we care about 921 * @tx_ring: Tx ring to clean 922 * @napi_budget: Used to determine if we are in netpoll 923 * @tx_cleaned: Out parameter set to the number of TXes cleaned 924 * 925 * Returns true if there's any budget left (e.g. the clean is finished) 926 **/ 927 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, 928 struct i40e_ring *tx_ring, int napi_budget, 929 unsigned int *tx_cleaned) 930 { 931 int i = tx_ring->next_to_clean; 932 struct i40e_tx_buffer *tx_buf; 933 struct i40e_tx_desc *tx_head; 934 struct i40e_tx_desc *tx_desc; 935 unsigned int total_bytes = 0, total_packets = 0; 936 unsigned int budget = vsi->work_limit; 937 938 tx_buf = &tx_ring->tx_bi[i]; 939 tx_desc = I40E_TX_DESC(tx_ring, i); 940 i -= tx_ring->count; 941 942 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); 943 944 do { 945 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; 946 947 /* if next_to_watch is not set then there is no work pending */ 948 if (!eop_desc) 949 break; 950 951 /* prevent any other reads prior to eop_desc */ 952 smp_rmb(); 953 954 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); 955 /* we have caught up to head, no work left to do */ 956 if (tx_head == tx_desc) 957 break; 958 959 /* clear next_to_watch to prevent false hangs */ 960 tx_buf->next_to_watch = NULL; 961 962 /* update the statistics for this packet */ 963 total_bytes += tx_buf->bytecount; 964 total_packets += tx_buf->gso_segs; 965 966 /* free the skb/XDP data */ 967 if (ring_is_xdp(tx_ring)) 968 xdp_return_frame(tx_buf->xdpf); 969 else 970 napi_consume_skb(tx_buf->skb, napi_budget); 971 972 /* unmap skb header data */ 973 dma_unmap_single(tx_ring->dev, 974 dma_unmap_addr(tx_buf, dma), 975 dma_unmap_len(tx_buf, len), 976 DMA_TO_DEVICE); 977 978 /* clear tx_buffer data */ 979 tx_buf->skb = NULL; 980 dma_unmap_len_set(tx_buf, len, 0); 981 982 /* unmap remaining buffers */ 983 while (tx_desc != eop_desc) { 984 i40e_trace(clean_tx_irq_unmap, 985 tx_ring, tx_desc, tx_buf); 986 987 tx_buf++; 988 tx_desc++; 989 i++; 990 if (unlikely(!i)) { 991 i -= tx_ring->count; 992 tx_buf = tx_ring->tx_bi; 993 tx_desc = I40E_TX_DESC(tx_ring, 0); 994 } 995 996 /* unmap any remaining paged data */ 997 if (dma_unmap_len(tx_buf, len)) { 998 dma_unmap_page(tx_ring->dev, 999 dma_unmap_addr(tx_buf, dma), 1000 dma_unmap_len(tx_buf, len), 1001 DMA_TO_DEVICE); 1002 dma_unmap_len_set(tx_buf, len, 0); 1003 } 1004 } 1005 1006 /* move us one more past the eop_desc for start of next pkt */ 1007 tx_buf++; 1008 tx_desc++; 1009 i++; 1010 if (unlikely(!i)) { 1011 i -= tx_ring->count; 1012 tx_buf = tx_ring->tx_bi; 1013 tx_desc = I40E_TX_DESC(tx_ring, 0); 1014 } 1015 1016 prefetch(tx_desc); 1017 1018 /* update budget accounting */ 1019 budget--; 1020 } while (likely(budget)); 1021 1022 i += tx_ring->count; 1023 tx_ring->next_to_clean = i; 1024 i40e_update_tx_stats(tx_ring, total_packets, total_bytes); 1025 i40e_arm_wb(tx_ring, vsi, budget); 1026 1027 if (ring_is_xdp(tx_ring)) 1028 return !!budget; 1029 1030 /* notify netdev of completed buffers */ 1031 netdev_tx_completed_queue(txring_txq(tx_ring), 1032 total_packets, total_bytes); 1033 1034 #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2)) 1035 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1036 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 1037 /* Make sure that anybody stopping the queue after this 1038 * sees the new next_to_clean. 1039 */ 1040 smp_mb(); 1041 if (__netif_subqueue_stopped(tx_ring->netdev, 1042 tx_ring->queue_index) && 1043 !test_bit(__I40E_VSI_DOWN, vsi->state)) { 1044 netif_wake_subqueue(tx_ring->netdev, 1045 tx_ring->queue_index); 1046 ++tx_ring->tx_stats.restart_queue; 1047 } 1048 } 1049 1050 *tx_cleaned = total_packets; 1051 return !!budget; 1052 } 1053 1054 /** 1055 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled 1056 * @vsi: the VSI we care about 1057 * @q_vector: the vector on which to enable writeback 1058 * 1059 **/ 1060 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, 1061 struct i40e_q_vector *q_vector) 1062 { 1063 u16 flags = q_vector->tx.ring[0].flags; 1064 u32 val; 1065 1066 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) 1067 return; 1068 1069 if (q_vector->arm_wb_state) 1070 return; 1071 1072 if (test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) { 1073 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | 1074 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ 1075 1076 wr32(&vsi->back->hw, 1077 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), 1078 val); 1079 } else { 1080 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | 1081 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ 1082 1083 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 1084 } 1085 q_vector->arm_wb_state = true; 1086 } 1087 1088 /** 1089 * i40e_force_wb - Issue SW Interrupt so HW does a wb 1090 * @vsi: the VSI we care about 1091 * @q_vector: the vector on which to force writeback 1092 * 1093 **/ 1094 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) 1095 { 1096 if (test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) { 1097 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1098 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ 1099 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 1100 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; 1101 /* allow 00 to be written to the index */ 1102 1103 wr32(&vsi->back->hw, 1104 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val); 1105 } else { 1106 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | 1107 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ 1108 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | 1109 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; 1110 /* allow 00 to be written to the index */ 1111 1112 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 1113 } 1114 } 1115 1116 static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector, 1117 struct i40e_ring_container *rc) 1118 { 1119 return &q_vector->rx == rc; 1120 } 1121 1122 static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector) 1123 { 1124 unsigned int divisor; 1125 1126 switch (q_vector->vsi->back->hw.phy.link_info.link_speed) { 1127 case I40E_LINK_SPEED_40GB: 1128 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024; 1129 break; 1130 case I40E_LINK_SPEED_25GB: 1131 case I40E_LINK_SPEED_20GB: 1132 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512; 1133 break; 1134 default: 1135 case I40E_LINK_SPEED_10GB: 1136 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256; 1137 break; 1138 case I40E_LINK_SPEED_1GB: 1139 case I40E_LINK_SPEED_100MB: 1140 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32; 1141 break; 1142 } 1143 1144 return divisor; 1145 } 1146 1147 /** 1148 * i40e_update_itr - update the dynamic ITR value based on statistics 1149 * @q_vector: structure containing interrupt and ring information 1150 * @rc: structure containing ring performance data 1151 * 1152 * Stores a new ITR value based on packets and byte 1153 * counts during the last interrupt. The advantage of per interrupt 1154 * computation is faster updates and more accurate ITR for the current 1155 * traffic pattern. Constants in this function were computed 1156 * based on theoretical maximum wire speed and thresholds were set based 1157 * on testing data as well as attempting to minimize response time 1158 * while increasing bulk throughput. 1159 **/ 1160 static void i40e_update_itr(struct i40e_q_vector *q_vector, 1161 struct i40e_ring_container *rc) 1162 { 1163 unsigned int avg_wire_size, packets, bytes, itr; 1164 unsigned long next_update = jiffies; 1165 1166 /* If we don't have any rings just leave ourselves set for maximum 1167 * possible latency so we take ourselves out of the equation. 1168 */ 1169 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting)) 1170 return; 1171 1172 /* For Rx we want to push the delay up and default to low latency. 1173 * for Tx we want to pull the delay down and default to high latency. 1174 */ 1175 itr = i40e_container_is_rx(q_vector, rc) ? 1176 I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY : 1177 I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY; 1178 1179 /* If we didn't update within up to 1 - 2 jiffies we can assume 1180 * that either packets are coming in so slow there hasn't been 1181 * any work, or that there is so much work that NAPI is dealing 1182 * with interrupt moderation and we don't need to do anything. 1183 */ 1184 if (time_after(next_update, rc->next_update)) 1185 goto clear_counts; 1186 1187 /* If itr_countdown is set it means we programmed an ITR within 1188 * the last 4 interrupt cycles. This has a side effect of us 1189 * potentially firing an early interrupt. In order to work around 1190 * this we need to throw out any data received for a few 1191 * interrupts following the update. 1192 */ 1193 if (q_vector->itr_countdown) { 1194 itr = rc->target_itr; 1195 goto clear_counts; 1196 } 1197 1198 packets = rc->total_packets; 1199 bytes = rc->total_bytes; 1200 1201 if (i40e_container_is_rx(q_vector, rc)) { 1202 /* If Rx there are 1 to 4 packets and bytes are less than 1203 * 9000 assume insufficient data to use bulk rate limiting 1204 * approach unless Tx is already in bulk rate limiting. We 1205 * are likely latency driven. 1206 */ 1207 if (packets && packets < 4 && bytes < 9000 && 1208 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) { 1209 itr = I40E_ITR_ADAPTIVE_LATENCY; 1210 goto adjust_by_size; 1211 } 1212 } else if (packets < 4) { 1213 /* If we have Tx and Rx ITR maxed and Tx ITR is running in 1214 * bulk mode and we are receiving 4 or fewer packets just 1215 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so 1216 * that the Rx can relax. 1217 */ 1218 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS && 1219 (q_vector->rx.target_itr & I40E_ITR_MASK) == 1220 I40E_ITR_ADAPTIVE_MAX_USECS) 1221 goto clear_counts; 1222 } else if (packets > 32) { 1223 /* If we have processed over 32 packets in a single interrupt 1224 * for Tx assume we need to switch over to "bulk" mode. 1225 */ 1226 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY; 1227 } 1228 1229 /* We have no packets to actually measure against. This means 1230 * either one of the other queues on this vector is active or 1231 * we are a Tx queue doing TSO with too high of an interrupt rate. 1232 * 1233 * Between 4 and 56 we can assume that our current interrupt delay 1234 * is only slightly too low. As such we should increase it by a small 1235 * fixed amount. 1236 */ 1237 if (packets < 56) { 1238 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC; 1239 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { 1240 itr &= I40E_ITR_ADAPTIVE_LATENCY; 1241 itr += I40E_ITR_ADAPTIVE_MAX_USECS; 1242 } 1243 goto clear_counts; 1244 } 1245 1246 if (packets <= 256) { 1247 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr); 1248 itr &= I40E_ITR_MASK; 1249 1250 /* Between 56 and 112 is our "goldilocks" zone where we are 1251 * working out "just right". Just report that our current 1252 * ITR is good for us. 1253 */ 1254 if (packets <= 112) 1255 goto clear_counts; 1256 1257 /* If packet count is 128 or greater we are likely looking 1258 * at a slight overrun of the delay we want. Try halving 1259 * our delay to see if that will cut the number of packets 1260 * in half per interrupt. 1261 */ 1262 itr /= 2; 1263 itr &= I40E_ITR_MASK; 1264 if (itr < I40E_ITR_ADAPTIVE_MIN_USECS) 1265 itr = I40E_ITR_ADAPTIVE_MIN_USECS; 1266 1267 goto clear_counts; 1268 } 1269 1270 /* The paths below assume we are dealing with a bulk ITR since 1271 * number of packets is greater than 256. We are just going to have 1272 * to compute a value and try to bring the count under control, 1273 * though for smaller packet sizes there isn't much we can do as 1274 * NAPI polling will likely be kicking in sooner rather than later. 1275 */ 1276 itr = I40E_ITR_ADAPTIVE_BULK; 1277 1278 adjust_by_size: 1279 /* If packet counts are 256 or greater we can assume we have a gross 1280 * overestimation of what the rate should be. Instead of trying to fine 1281 * tune it just use the formula below to try and dial in an exact value 1282 * give the current packet size of the frame. 1283 */ 1284 avg_wire_size = bytes / packets; 1285 1286 /* The following is a crude approximation of: 1287 * wmem_default / (size + overhead) = desired_pkts_per_int 1288 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 1289 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 1290 * 1291 * Assuming wmem_default is 212992 and overhead is 640 bytes per 1292 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 1293 * formula down to 1294 * 1295 * (170 * (size + 24)) / (size + 640) = ITR 1296 * 1297 * We first do some math on the packet size and then finally bitshift 1298 * by 8 after rounding up. We also have to account for PCIe link speed 1299 * difference as ITR scales based on this. 1300 */ 1301 if (avg_wire_size <= 60) { 1302 /* Start at 250k ints/sec */ 1303 avg_wire_size = 4096; 1304 } else if (avg_wire_size <= 380) { 1305 /* 250K ints/sec to 60K ints/sec */ 1306 avg_wire_size *= 40; 1307 avg_wire_size += 1696; 1308 } else if (avg_wire_size <= 1084) { 1309 /* 60K ints/sec to 36K ints/sec */ 1310 avg_wire_size *= 15; 1311 avg_wire_size += 11452; 1312 } else if (avg_wire_size <= 1980) { 1313 /* 36K ints/sec to 30K ints/sec */ 1314 avg_wire_size *= 5; 1315 avg_wire_size += 22420; 1316 } else { 1317 /* plateau at a limit of 30K ints/sec */ 1318 avg_wire_size = 32256; 1319 } 1320 1321 /* If we are in low latency mode halve our delay which doubles the 1322 * rate to somewhere between 100K to 16K ints/sec 1323 */ 1324 if (itr & I40E_ITR_ADAPTIVE_LATENCY) 1325 avg_wire_size /= 2; 1326 1327 /* Resultant value is 256 times larger than it needs to be. This 1328 * gives us room to adjust the value as needed to either increase 1329 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 1330 * 1331 * Use addition as we have already recorded the new latency flag 1332 * for the ITR value. 1333 */ 1334 itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) * 1335 I40E_ITR_ADAPTIVE_MIN_INC; 1336 1337 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { 1338 itr &= I40E_ITR_ADAPTIVE_LATENCY; 1339 itr += I40E_ITR_ADAPTIVE_MAX_USECS; 1340 } 1341 1342 clear_counts: 1343 /* write back value */ 1344 rc->target_itr = itr; 1345 1346 /* next update should occur within next jiffy */ 1347 rc->next_update = next_update + 1; 1348 1349 rc->total_bytes = 0; 1350 rc->total_packets = 0; 1351 } 1352 1353 static struct i40e_rx_buffer *i40e_rx_bi(struct i40e_ring *rx_ring, u32 idx) 1354 { 1355 return &rx_ring->rx_bi[idx]; 1356 } 1357 1358 /** 1359 * i40e_reuse_rx_page - page flip buffer and store it back on the ring 1360 * @rx_ring: rx descriptor ring to store buffers on 1361 * @old_buff: donor buffer to have page reused 1362 * 1363 * Synchronizes page for reuse by the adapter 1364 **/ 1365 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, 1366 struct i40e_rx_buffer *old_buff) 1367 { 1368 struct i40e_rx_buffer *new_buff; 1369 u16 nta = rx_ring->next_to_alloc; 1370 1371 new_buff = i40e_rx_bi(rx_ring, nta); 1372 1373 /* update, and store next to alloc */ 1374 nta++; 1375 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1376 1377 /* transfer page from old buffer to new buffer */ 1378 new_buff->dma = old_buff->dma; 1379 new_buff->page = old_buff->page; 1380 new_buff->page_offset = old_buff->page_offset; 1381 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1382 1383 /* clear contents of buffer_info */ 1384 old_buff->page = NULL; 1385 } 1386 1387 /** 1388 * i40e_clean_programming_status - clean the programming status descriptor 1389 * @rx_ring: the rx ring that has this descriptor 1390 * @qword0_raw: qword0 1391 * @qword1: qword1 representing status_error_len in CPU ordering 1392 * 1393 * Flow director should handle FD_FILTER_STATUS to check its filter programming 1394 * status being successful or not and take actions accordingly. FCoE should 1395 * handle its context/filter programming/invalidation status and take actions. 1396 * 1397 * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL. 1398 **/ 1399 void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw, 1400 u64 qword1) 1401 { 1402 u8 id; 1403 1404 id = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK, qword1); 1405 1406 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) 1407 i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id); 1408 } 1409 1410 /** 1411 * i40e_setup_tx_descriptors - Allocate the Tx descriptors 1412 * @tx_ring: the tx ring to set up 1413 * 1414 * Return 0 on success, negative on error 1415 **/ 1416 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) 1417 { 1418 struct device *dev = tx_ring->dev; 1419 int bi_size; 1420 1421 if (!dev) 1422 return -ENOMEM; 1423 1424 /* warn if we are about to overwrite the pointer */ 1425 WARN_ON(tx_ring->tx_bi); 1426 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 1427 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); 1428 if (!tx_ring->tx_bi) 1429 goto err; 1430 1431 u64_stats_init(&tx_ring->syncp); 1432 1433 /* round up to nearest 4K */ 1434 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); 1435 /* add u32 for head writeback, align after this takes care of 1436 * guaranteeing this is at least one cache line in size 1437 */ 1438 tx_ring->size += sizeof(u32); 1439 tx_ring->size = ALIGN(tx_ring->size, 4096); 1440 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 1441 &tx_ring->dma, GFP_KERNEL); 1442 if (!tx_ring->desc) { 1443 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 1444 tx_ring->size); 1445 goto err; 1446 } 1447 1448 tx_ring->next_to_use = 0; 1449 tx_ring->next_to_clean = 0; 1450 tx_ring->tx_stats.prev_pkt_ctr = -1; 1451 return 0; 1452 1453 err: 1454 kfree(tx_ring->tx_bi); 1455 tx_ring->tx_bi = NULL; 1456 return -ENOMEM; 1457 } 1458 1459 static void i40e_clear_rx_bi(struct i40e_ring *rx_ring) 1460 { 1461 memset(rx_ring->rx_bi, 0, sizeof(*rx_ring->rx_bi) * rx_ring->count); 1462 } 1463 1464 /** 1465 * i40e_clean_rx_ring - Free Rx buffers 1466 * @rx_ring: ring to be cleaned 1467 **/ 1468 void i40e_clean_rx_ring(struct i40e_ring *rx_ring) 1469 { 1470 u16 i; 1471 1472 /* ring already cleared, nothing to do */ 1473 if (!rx_ring->rx_bi) 1474 return; 1475 1476 if (rx_ring->xsk_pool) { 1477 i40e_xsk_clean_rx_ring(rx_ring); 1478 goto skip_free; 1479 } 1480 1481 /* Free all the Rx ring sk_buffs */ 1482 for (i = 0; i < rx_ring->count; i++) { 1483 struct i40e_rx_buffer *rx_bi = i40e_rx_bi(rx_ring, i); 1484 1485 if (!rx_bi->page) 1486 continue; 1487 1488 /* Invalidate cache lines that may have been written to by 1489 * device so that we avoid corrupting memory. 1490 */ 1491 dma_sync_single_range_for_cpu(rx_ring->dev, 1492 rx_bi->dma, 1493 rx_bi->page_offset, 1494 rx_ring->rx_buf_len, 1495 DMA_FROM_DEVICE); 1496 1497 /* free resources associated with mapping */ 1498 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, 1499 i40e_rx_pg_size(rx_ring), 1500 DMA_FROM_DEVICE, 1501 I40E_RX_DMA_ATTR); 1502 1503 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); 1504 1505 rx_bi->page = NULL; 1506 rx_bi->page_offset = 0; 1507 } 1508 1509 skip_free: 1510 if (rx_ring->xsk_pool) 1511 i40e_clear_rx_bi_zc(rx_ring); 1512 else 1513 i40e_clear_rx_bi(rx_ring); 1514 1515 /* Zero out the descriptor ring */ 1516 memset(rx_ring->desc, 0, rx_ring->size); 1517 1518 rx_ring->next_to_alloc = 0; 1519 rx_ring->next_to_clean = 0; 1520 rx_ring->next_to_process = 0; 1521 rx_ring->next_to_use = 0; 1522 } 1523 1524 /** 1525 * i40e_free_rx_resources - Free Rx resources 1526 * @rx_ring: ring to clean the resources from 1527 * 1528 * Free all receive software resources 1529 **/ 1530 void i40e_free_rx_resources(struct i40e_ring *rx_ring) 1531 { 1532 i40e_clean_rx_ring(rx_ring); 1533 if (rx_ring->vsi->type == I40E_VSI_MAIN) 1534 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 1535 rx_ring->xdp_prog = NULL; 1536 kfree(rx_ring->rx_bi); 1537 rx_ring->rx_bi = NULL; 1538 1539 if (rx_ring->desc) { 1540 dma_free_coherent(rx_ring->dev, rx_ring->size, 1541 rx_ring->desc, rx_ring->dma); 1542 rx_ring->desc = NULL; 1543 } 1544 } 1545 1546 /** 1547 * i40e_setup_rx_descriptors - Allocate Rx descriptors 1548 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1549 * 1550 * Returns 0 on success, negative on failure 1551 **/ 1552 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) 1553 { 1554 struct device *dev = rx_ring->dev; 1555 1556 u64_stats_init(&rx_ring->syncp); 1557 1558 /* Round up to nearest 4K */ 1559 rx_ring->size = rx_ring->count * sizeof(union i40e_rx_desc); 1560 rx_ring->size = ALIGN(rx_ring->size, 4096); 1561 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 1562 &rx_ring->dma, GFP_KERNEL); 1563 1564 if (!rx_ring->desc) { 1565 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 1566 rx_ring->size); 1567 return -ENOMEM; 1568 } 1569 1570 rx_ring->next_to_alloc = 0; 1571 rx_ring->next_to_clean = 0; 1572 rx_ring->next_to_process = 0; 1573 rx_ring->next_to_use = 0; 1574 1575 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog; 1576 1577 rx_ring->rx_bi = 1578 kcalloc(rx_ring->count, sizeof(*rx_ring->rx_bi), GFP_KERNEL); 1579 if (!rx_ring->rx_bi) 1580 return -ENOMEM; 1581 1582 return 0; 1583 } 1584 1585 /** 1586 * i40e_release_rx_desc - Store the new tail and head values 1587 * @rx_ring: ring to bump 1588 * @val: new head index 1589 **/ 1590 void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) 1591 { 1592 rx_ring->next_to_use = val; 1593 1594 /* update next to alloc since we have filled the ring */ 1595 rx_ring->next_to_alloc = val; 1596 1597 /* Force memory writes to complete before letting h/w 1598 * know there are new descriptors to fetch. (Only 1599 * applicable for weak-ordered memory model archs, 1600 * such as IA-64). 1601 */ 1602 wmb(); 1603 writel(val, rx_ring->tail); 1604 } 1605 1606 #if (PAGE_SIZE >= 8192) 1607 static unsigned int i40e_rx_frame_truesize(struct i40e_ring *rx_ring, 1608 unsigned int size) 1609 { 1610 unsigned int truesize; 1611 1612 truesize = rx_ring->rx_offset ? 1613 SKB_DATA_ALIGN(size + rx_ring->rx_offset) + 1614 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 1615 SKB_DATA_ALIGN(size); 1616 return truesize; 1617 } 1618 #endif 1619 1620 /** 1621 * i40e_alloc_mapped_page - recycle or make a new page 1622 * @rx_ring: ring to use 1623 * @bi: rx_buffer struct to modify 1624 * 1625 * Returns true if the page was successfully allocated or 1626 * reused. 1627 **/ 1628 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, 1629 struct i40e_rx_buffer *bi) 1630 { 1631 struct page *page = bi->page; 1632 dma_addr_t dma; 1633 1634 /* since we are recycling buffers we should seldom need to alloc */ 1635 if (likely(page)) { 1636 rx_ring->rx_stats.page_reuse_count++; 1637 return true; 1638 } 1639 1640 /* alloc new page for storage */ 1641 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring)); 1642 if (unlikely(!page)) { 1643 rx_ring->rx_stats.alloc_page_failed++; 1644 return false; 1645 } 1646 1647 rx_ring->rx_stats.page_alloc_count++; 1648 1649 /* map page for use */ 1650 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1651 i40e_rx_pg_size(rx_ring), 1652 DMA_FROM_DEVICE, 1653 I40E_RX_DMA_ATTR); 1654 1655 /* if mapping failed free memory back to system since 1656 * there isn't much point in holding memory we can't use 1657 */ 1658 if (dma_mapping_error(rx_ring->dev, dma)) { 1659 __free_pages(page, i40e_rx_pg_order(rx_ring)); 1660 rx_ring->rx_stats.alloc_page_failed++; 1661 return false; 1662 } 1663 1664 bi->dma = dma; 1665 bi->page = page; 1666 bi->page_offset = rx_ring->rx_offset; 1667 page_ref_add(page, USHRT_MAX - 1); 1668 bi->pagecnt_bias = USHRT_MAX; 1669 1670 return true; 1671 } 1672 1673 /** 1674 * i40e_alloc_rx_buffers - Replace used receive buffers 1675 * @rx_ring: ring to place buffers on 1676 * @cleaned_count: number of buffers to replace 1677 * 1678 * Returns false if all allocations were successful, true if any fail 1679 **/ 1680 bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) 1681 { 1682 u16 ntu = rx_ring->next_to_use; 1683 union i40e_rx_desc *rx_desc; 1684 struct i40e_rx_buffer *bi; 1685 1686 /* do nothing if no valid netdev defined */ 1687 if (!rx_ring->netdev || !cleaned_count) 1688 return false; 1689 1690 rx_desc = I40E_RX_DESC(rx_ring, ntu); 1691 bi = i40e_rx_bi(rx_ring, ntu); 1692 1693 do { 1694 if (!i40e_alloc_mapped_page(rx_ring, bi)) 1695 goto no_buffers; 1696 1697 /* sync the buffer for use by the device */ 1698 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1699 bi->page_offset, 1700 rx_ring->rx_buf_len, 1701 DMA_FROM_DEVICE); 1702 1703 /* Refresh the desc even if buffer_addrs didn't change 1704 * because each write-back erases this info. 1705 */ 1706 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1707 1708 rx_desc++; 1709 bi++; 1710 ntu++; 1711 if (unlikely(ntu == rx_ring->count)) { 1712 rx_desc = I40E_RX_DESC(rx_ring, 0); 1713 bi = i40e_rx_bi(rx_ring, 0); 1714 ntu = 0; 1715 } 1716 1717 /* clear the status bits for the next_to_use descriptor */ 1718 rx_desc->wb.qword1.status_error_len = 0; 1719 1720 cleaned_count--; 1721 } while (cleaned_count); 1722 1723 if (rx_ring->next_to_use != ntu) 1724 i40e_release_rx_desc(rx_ring, ntu); 1725 1726 return false; 1727 1728 no_buffers: 1729 if (rx_ring->next_to_use != ntu) 1730 i40e_release_rx_desc(rx_ring, ntu); 1731 1732 /* make sure to come back via polling to try again after 1733 * allocation failure 1734 */ 1735 return true; 1736 } 1737 1738 /** 1739 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum 1740 * @vsi: the VSI we care about 1741 * @skb: skb currently being received and modified 1742 * @rx_desc: the receive descriptor 1743 **/ 1744 static inline void i40e_rx_checksum(struct i40e_vsi *vsi, 1745 struct sk_buff *skb, 1746 union i40e_rx_desc *rx_desc) 1747 { 1748 struct libeth_rx_pt decoded; 1749 u32 rx_error, rx_status; 1750 bool ipv4, ipv6; 1751 u8 ptype; 1752 u64 qword; 1753 1754 skb->ip_summed = CHECKSUM_NONE; 1755 1756 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1757 ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword); 1758 1759 decoded = libie_rx_pt_parse(ptype); 1760 if (!libeth_rx_pt_has_checksum(vsi->netdev, decoded)) 1761 return; 1762 1763 rx_error = FIELD_GET(I40E_RXD_QW1_ERROR_MASK, qword); 1764 rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword); 1765 1766 /* did the hardware decode the packet and checksum? */ 1767 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) 1768 return; 1769 1770 ipv4 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV4; 1771 ipv6 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV6; 1772 1773 if (ipv4 && 1774 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | 1775 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) 1776 goto checksum_fail; 1777 1778 /* likely incorrect csum if alternate IP extension headers found */ 1779 if (ipv6 && 1780 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) 1781 /* don't increment checksum err here, non-fatal err */ 1782 return; 1783 1784 /* there was some L4 error, count error and punt packet to the stack */ 1785 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) 1786 goto checksum_fail; 1787 1788 /* handle packets that were not able to be checksummed due 1789 * to arrival speed, in this case the stack can compute 1790 * the csum. 1791 */ 1792 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) 1793 return; 1794 1795 /* If there is an outer header present that might contain a checksum 1796 * we need to bump the checksum level by 1 to reflect the fact that 1797 * we are indicating we validated the inner checksum. 1798 */ 1799 if (decoded.tunnel_type >= LIBETH_RX_PT_TUNNEL_IP_GRENAT) 1800 skb->csum_level = 1; 1801 1802 skb->ip_summed = CHECKSUM_UNNECESSARY; 1803 return; 1804 1805 checksum_fail: 1806 vsi->back->hw_csum_rx_error++; 1807 } 1808 1809 /** 1810 * i40e_rx_hash - set the hash value in the skb 1811 * @ring: descriptor ring 1812 * @rx_desc: specific descriptor 1813 * @skb: skb currently being received and modified 1814 * @rx_ptype: Rx packet type 1815 **/ 1816 static inline void i40e_rx_hash(struct i40e_ring *ring, 1817 union i40e_rx_desc *rx_desc, 1818 struct sk_buff *skb, 1819 u8 rx_ptype) 1820 { 1821 struct libeth_rx_pt decoded; 1822 u32 hash; 1823 const __le64 rss_mask = 1824 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << 1825 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); 1826 1827 decoded = libie_rx_pt_parse(rx_ptype); 1828 if (!libeth_rx_pt_has_hash(ring->netdev, decoded)) 1829 return; 1830 1831 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { 1832 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); 1833 libeth_rx_pt_set_hash(skb, hash, decoded); 1834 } 1835 } 1836 1837 /** 1838 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor 1839 * @rx_ring: rx descriptor ring packet is being transacted on 1840 * @rx_desc: pointer to the EOP Rx descriptor 1841 * @skb: pointer to current skb being populated 1842 * 1843 * This function checks the ring, descriptor, and packet information in 1844 * order to populate the hash, checksum, VLAN, protocol, and 1845 * other fields within the skb. 1846 **/ 1847 void i40e_process_skb_fields(struct i40e_ring *rx_ring, 1848 union i40e_rx_desc *rx_desc, struct sk_buff *skb) 1849 { 1850 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1851 u32 rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword); 1852 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK; 1853 u32 tsyn = FIELD_GET(I40E_RXD_QW1_STATUS_TSYNINDX_MASK, rx_status); 1854 u8 rx_ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword); 1855 1856 if (unlikely(tsynvalid)) 1857 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn); 1858 1859 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); 1860 1861 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); 1862 1863 skb_record_rx_queue(skb, rx_ring->queue_index); 1864 1865 if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) { 1866 __le16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1; 1867 1868 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1869 le16_to_cpu(vlan_tag)); 1870 } 1871 1872 /* modifies the skb - consumes the enet header */ 1873 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1874 } 1875 1876 /** 1877 * i40e_cleanup_headers - Correct empty headers 1878 * @rx_ring: rx descriptor ring packet is being transacted on 1879 * @skb: pointer to current skb being fixed 1880 * @rx_desc: pointer to the EOP Rx descriptor 1881 * 1882 * In addition if skb is not at least 60 bytes we need to pad it so that 1883 * it is large enough to qualify as a valid Ethernet frame. 1884 * 1885 * Returns true if an error was encountered and skb was freed. 1886 **/ 1887 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb, 1888 union i40e_rx_desc *rx_desc) 1889 1890 { 1891 /* ERR_MASK will only have valid bits if EOP set, and 1892 * what we are doing here is actually checking 1893 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in 1894 * the error field 1895 */ 1896 if (unlikely(i40e_test_staterr(rx_desc, 1897 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { 1898 dev_kfree_skb_any(skb); 1899 return true; 1900 } 1901 1902 /* if eth_skb_pad returns an error the skb was freed */ 1903 if (eth_skb_pad(skb)) 1904 return true; 1905 1906 return false; 1907 } 1908 1909 /** 1910 * i40e_can_reuse_rx_page - Determine if page can be reused for another Rx 1911 * @rx_buffer: buffer containing the page 1912 * @rx_stats: rx stats structure for the rx ring 1913 * 1914 * If page is reusable, we have a green light for calling i40e_reuse_rx_page, 1915 * which will assign the current buffer to the buffer that next_to_alloc is 1916 * pointing to; otherwise, the DMA mapping needs to be destroyed and 1917 * page freed. 1918 * 1919 * rx_stats will be updated to indicate whether the page was waived 1920 * or busy if it could not be reused. 1921 */ 1922 static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer, 1923 struct i40e_rx_queue_stats *rx_stats) 1924 { 1925 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1926 struct page *page = rx_buffer->page; 1927 1928 /* Is any reuse possible? */ 1929 if (!dev_page_is_reusable(page)) { 1930 rx_stats->page_waive_count++; 1931 return false; 1932 } 1933 1934 #if (PAGE_SIZE < 8192) 1935 /* if we are only owner of page we can reuse it */ 1936 if (unlikely((rx_buffer->page_count - pagecnt_bias) > 1)) { 1937 rx_stats->page_busy_count++; 1938 return false; 1939 } 1940 #else 1941 #define I40E_LAST_OFFSET \ 1942 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048) 1943 if (rx_buffer->page_offset > I40E_LAST_OFFSET) { 1944 rx_stats->page_busy_count++; 1945 return false; 1946 } 1947 #endif 1948 1949 /* If we have drained the page fragment pool we need to update 1950 * the pagecnt_bias and page count so that we fully restock the 1951 * number of references the driver holds. 1952 */ 1953 if (unlikely(pagecnt_bias == 1)) { 1954 page_ref_add(page, USHRT_MAX - 1); 1955 rx_buffer->pagecnt_bias = USHRT_MAX; 1956 } 1957 1958 return true; 1959 } 1960 1961 /** 1962 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region 1963 * @rx_buffer: Rx buffer to adjust 1964 * @truesize: Size of adjustment 1965 **/ 1966 static void i40e_rx_buffer_flip(struct i40e_rx_buffer *rx_buffer, 1967 unsigned int truesize) 1968 { 1969 #if (PAGE_SIZE < 8192) 1970 rx_buffer->page_offset ^= truesize; 1971 #else 1972 rx_buffer->page_offset += truesize; 1973 #endif 1974 } 1975 1976 /** 1977 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use 1978 * @rx_ring: rx descriptor ring to transact packets on 1979 * @size: size of buffer to add to skb 1980 * 1981 * This function will pull an Rx buffer from the ring and synchronize it 1982 * for use by the CPU. 1983 */ 1984 static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring, 1985 const unsigned int size) 1986 { 1987 struct i40e_rx_buffer *rx_buffer; 1988 1989 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_process); 1990 rx_buffer->page_count = 1991 #if (PAGE_SIZE < 8192) 1992 page_count(rx_buffer->page); 1993 #else 1994 0; 1995 #endif 1996 prefetch_page_address(rx_buffer->page); 1997 1998 /* we are reusing so sync this buffer for CPU use */ 1999 dma_sync_single_range_for_cpu(rx_ring->dev, 2000 rx_buffer->dma, 2001 rx_buffer->page_offset, 2002 size, 2003 DMA_FROM_DEVICE); 2004 2005 /* We have pulled a buffer for use, so decrement pagecnt_bias */ 2006 rx_buffer->pagecnt_bias--; 2007 2008 return rx_buffer; 2009 } 2010 2011 /** 2012 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free 2013 * @rx_ring: rx descriptor ring to transact packets on 2014 * @rx_buffer: rx buffer to pull data from 2015 * 2016 * This function will clean up the contents of the rx_buffer. It will 2017 * either recycle the buffer or unmap it and free the associated resources. 2018 */ 2019 static void i40e_put_rx_buffer(struct i40e_ring *rx_ring, 2020 struct i40e_rx_buffer *rx_buffer) 2021 { 2022 if (i40e_can_reuse_rx_page(rx_buffer, &rx_ring->rx_stats)) { 2023 /* hand second half of page back to the ring */ 2024 i40e_reuse_rx_page(rx_ring, rx_buffer); 2025 } else { 2026 /* we are not reusing the buffer so unmap it */ 2027 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2028 i40e_rx_pg_size(rx_ring), 2029 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); 2030 __page_frag_cache_drain(rx_buffer->page, 2031 rx_buffer->pagecnt_bias); 2032 /* clear contents of buffer_info */ 2033 rx_buffer->page = NULL; 2034 } 2035 } 2036 2037 /** 2038 * i40e_process_rx_buffs- Processing of buffers post XDP prog or on error 2039 * @rx_ring: Rx descriptor ring to transact packets on 2040 * @xdp_res: Result of the XDP program 2041 * @xdp: xdp_buff pointing to the data 2042 **/ 2043 static void i40e_process_rx_buffs(struct i40e_ring *rx_ring, int xdp_res, 2044 struct xdp_buff *xdp) 2045 { 2046 u32 nr_frags = xdp_get_shared_info_from_buff(xdp)->nr_frags; 2047 u32 next = rx_ring->next_to_clean, i = 0; 2048 struct i40e_rx_buffer *rx_buffer; 2049 2050 xdp->flags = 0; 2051 2052 while (1) { 2053 rx_buffer = i40e_rx_bi(rx_ring, next); 2054 if (++next == rx_ring->count) 2055 next = 0; 2056 2057 if (!rx_buffer->page) 2058 continue; 2059 2060 if (xdp_res != I40E_XDP_CONSUMED) 2061 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2062 else if (i++ <= nr_frags) 2063 rx_buffer->pagecnt_bias++; 2064 2065 /* EOP buffer will be put in i40e_clean_rx_irq() */ 2066 if (next == rx_ring->next_to_process) 2067 return; 2068 2069 i40e_put_rx_buffer(rx_ring, rx_buffer); 2070 } 2071 } 2072 2073 /** 2074 * i40e_construct_skb - Allocate skb and populate it 2075 * @rx_ring: rx descriptor ring to transact packets on 2076 * @xdp: xdp_buff pointing to the data 2077 * 2078 * This function allocates an skb. It then populates it with the page 2079 * data from the current receive descriptor, taking care to set up the 2080 * skb correctly. 2081 */ 2082 static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring, 2083 struct xdp_buff *xdp) 2084 { 2085 unsigned int size = xdp->data_end - xdp->data; 2086 struct i40e_rx_buffer *rx_buffer; 2087 struct skb_shared_info *sinfo; 2088 unsigned int headlen; 2089 struct sk_buff *skb; 2090 u32 nr_frags = 0; 2091 2092 /* prefetch first cache line of first page */ 2093 net_prefetch(xdp->data); 2094 2095 /* Note, we get here by enabling legacy-rx via: 2096 * 2097 * ethtool --set-priv-flags <dev> legacy-rx on 2098 * 2099 * In this mode, we currently get 0 extra XDP headroom as 2100 * opposed to having legacy-rx off, where we process XDP 2101 * packets going to stack via i40e_build_skb(). The latter 2102 * provides us currently with 192 bytes of headroom. 2103 * 2104 * For i40e_construct_skb() mode it means that the 2105 * xdp->data_meta will always point to xdp->data, since 2106 * the helper cannot expand the head. Should this ever 2107 * change in future for legacy-rx mode on, then lets also 2108 * add xdp->data_meta handling here. 2109 */ 2110 2111 /* allocate a skb to store the frags */ 2112 skb = napi_alloc_skb(&rx_ring->q_vector->napi, I40E_RX_HDR_SIZE); 2113 if (unlikely(!skb)) 2114 return NULL; 2115 2116 /* Determine available headroom for copy */ 2117 headlen = size; 2118 if (headlen > I40E_RX_HDR_SIZE) 2119 headlen = eth_get_headlen(skb->dev, xdp->data, 2120 I40E_RX_HDR_SIZE); 2121 2122 /* align pull length to size of long to optimize memcpy performance */ 2123 memcpy(__skb_put(skb, headlen), xdp->data, 2124 ALIGN(headlen, sizeof(long))); 2125 2126 if (unlikely(xdp_buff_has_frags(xdp))) { 2127 sinfo = xdp_get_shared_info_from_buff(xdp); 2128 nr_frags = sinfo->nr_frags; 2129 } 2130 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean); 2131 /* update all of the pointers */ 2132 size -= headlen; 2133 if (size) { 2134 if (unlikely(nr_frags >= MAX_SKB_FRAGS)) { 2135 dev_kfree_skb(skb); 2136 return NULL; 2137 } 2138 skb_add_rx_frag(skb, 0, rx_buffer->page, 2139 rx_buffer->page_offset + headlen, 2140 size, xdp->frame_sz); 2141 /* buffer is used by skb, update page_offset */ 2142 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2143 } else { 2144 /* buffer is unused, reset bias back to rx_buffer */ 2145 rx_buffer->pagecnt_bias++; 2146 } 2147 2148 if (unlikely(xdp_buff_has_frags(xdp))) { 2149 struct skb_shared_info *skinfo = skb_shinfo(skb); 2150 2151 memcpy(&skinfo->frags[skinfo->nr_frags], &sinfo->frags[0], 2152 sizeof(skb_frag_t) * nr_frags); 2153 2154 xdp_update_skb_frags_info(skb, skinfo->nr_frags + nr_frags, 2155 sinfo->xdp_frags_size, 2156 nr_frags * xdp->frame_sz, 2157 xdp_buff_get_skb_flags(xdp)); 2158 2159 /* First buffer has already been processed, so bump ntc */ 2160 if (++rx_ring->next_to_clean == rx_ring->count) 2161 rx_ring->next_to_clean = 0; 2162 2163 i40e_process_rx_buffs(rx_ring, I40E_XDP_PASS, xdp); 2164 } 2165 2166 return skb; 2167 } 2168 2169 /** 2170 * i40e_build_skb - Build skb around an existing buffer 2171 * @rx_ring: Rx descriptor ring to transact packets on 2172 * @xdp: xdp_buff pointing to the data 2173 * 2174 * This function builds an skb around an existing Rx buffer, taking care 2175 * to set up the skb correctly and avoid any memcpy overhead. 2176 */ 2177 static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring, 2178 struct xdp_buff *xdp) 2179 { 2180 unsigned int metasize = xdp->data - xdp->data_meta; 2181 struct skb_shared_info *sinfo; 2182 struct sk_buff *skb; 2183 u32 nr_frags; 2184 2185 /* Prefetch first cache line of first page. If xdp->data_meta 2186 * is unused, this points exactly as xdp->data, otherwise we 2187 * likely have a consumer accessing first few bytes of meta 2188 * data, and then actual data. 2189 */ 2190 net_prefetch(xdp->data_meta); 2191 2192 if (unlikely(xdp_buff_has_frags(xdp))) { 2193 sinfo = xdp_get_shared_info_from_buff(xdp); 2194 nr_frags = sinfo->nr_frags; 2195 } 2196 2197 /* build an skb around the page buffer */ 2198 skb = napi_build_skb(xdp->data_hard_start, xdp->frame_sz); 2199 if (unlikely(!skb)) 2200 return NULL; 2201 2202 /* update pointers within the skb to store the data */ 2203 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2204 __skb_put(skb, xdp->data_end - xdp->data); 2205 if (metasize) 2206 skb_metadata_set(skb, metasize); 2207 2208 if (unlikely(xdp_buff_has_frags(xdp))) { 2209 xdp_update_skb_frags_info(skb, nr_frags, sinfo->xdp_frags_size, 2210 nr_frags * xdp->frame_sz, 2211 xdp_buff_get_skb_flags(xdp)); 2212 2213 i40e_process_rx_buffs(rx_ring, I40E_XDP_PASS, xdp); 2214 } else { 2215 struct i40e_rx_buffer *rx_buffer; 2216 2217 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean); 2218 /* buffer is used by skb, update page_offset */ 2219 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2220 } 2221 2222 return skb; 2223 } 2224 2225 /** 2226 * i40e_is_non_eop - process handling of non-EOP buffers 2227 * @rx_ring: Rx ring being processed 2228 * @rx_desc: Rx descriptor for current buffer 2229 * 2230 * If the buffer is an EOP buffer, this function exits returning false, 2231 * otherwise return true indicating that this is in fact a non-EOP buffer. 2232 */ 2233 bool i40e_is_non_eop(struct i40e_ring *rx_ring, 2234 union i40e_rx_desc *rx_desc) 2235 { 2236 /* if we are the last buffer then there is nothing else to do */ 2237 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) 2238 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) 2239 return false; 2240 2241 rx_ring->rx_stats.non_eop_descs++; 2242 2243 return true; 2244 } 2245 2246 static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf, 2247 struct i40e_ring *xdp_ring); 2248 2249 int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring) 2250 { 2251 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2252 2253 if (unlikely(!xdpf)) 2254 return I40E_XDP_CONSUMED; 2255 2256 return i40e_xmit_xdp_ring(xdpf, xdp_ring); 2257 } 2258 2259 /** 2260 * i40e_run_xdp - run an XDP program 2261 * @rx_ring: Rx ring being processed 2262 * @xdp: XDP buffer containing the frame 2263 * @xdp_prog: XDP program to run 2264 **/ 2265 static int i40e_run_xdp(struct i40e_ring *rx_ring, struct xdp_buff *xdp, struct bpf_prog *xdp_prog) 2266 { 2267 int err, result = I40E_XDP_PASS; 2268 struct i40e_ring *xdp_ring; 2269 u32 act; 2270 2271 if (!xdp_prog) 2272 goto xdp_out; 2273 2274 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2275 2276 act = bpf_prog_run_xdp(xdp_prog, xdp); 2277 switch (act) { 2278 case XDP_PASS: 2279 break; 2280 case XDP_TX: 2281 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index]; 2282 result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring); 2283 if (result == I40E_XDP_CONSUMED) 2284 goto out_failure; 2285 break; 2286 case XDP_REDIRECT: 2287 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog); 2288 if (err) 2289 goto out_failure; 2290 result = I40E_XDP_REDIR; 2291 break; 2292 default: 2293 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act); 2294 fallthrough; 2295 case XDP_ABORTED: 2296 out_failure: 2297 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2298 fallthrough; /* handle aborts by dropping packet */ 2299 case XDP_DROP: 2300 result = I40E_XDP_CONSUMED; 2301 break; 2302 } 2303 xdp_out: 2304 return result; 2305 } 2306 2307 /** 2308 * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register 2309 * @xdp_ring: XDP Tx ring 2310 * 2311 * This function updates the XDP Tx ring tail register. 2312 **/ 2313 void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring) 2314 { 2315 /* Force memory writes to complete before letting h/w 2316 * know there are new descriptors to fetch. 2317 */ 2318 wmb(); 2319 writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail); 2320 } 2321 2322 /** 2323 * i40e_update_rx_stats - Update Rx ring statistics 2324 * @rx_ring: rx descriptor ring 2325 * @total_rx_bytes: number of bytes received 2326 * @total_rx_packets: number of packets received 2327 * 2328 * This function updates the Rx ring statistics. 2329 **/ 2330 void i40e_update_rx_stats(struct i40e_ring *rx_ring, 2331 unsigned int total_rx_bytes, 2332 unsigned int total_rx_packets) 2333 { 2334 u64_stats_update_begin(&rx_ring->syncp); 2335 rx_ring->stats.packets += total_rx_packets; 2336 rx_ring->stats.bytes += total_rx_bytes; 2337 u64_stats_update_end(&rx_ring->syncp); 2338 rx_ring->q_vector->rx.total_packets += total_rx_packets; 2339 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 2340 } 2341 2342 /** 2343 * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map 2344 * @rx_ring: Rx ring 2345 * @xdp_res: Result of the receive batch 2346 * 2347 * This function bumps XDP Tx tail and/or flush redirect map, and 2348 * should be called when a batch of packets has been processed in the 2349 * napi loop. 2350 **/ 2351 void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res) 2352 { 2353 if (xdp_res & I40E_XDP_REDIR) 2354 xdp_do_flush(); 2355 2356 if (xdp_res & I40E_XDP_TX) { 2357 struct i40e_ring *xdp_ring = 2358 rx_ring->vsi->xdp_rings[rx_ring->queue_index]; 2359 2360 i40e_xdp_ring_update_tail(xdp_ring); 2361 } 2362 } 2363 2364 /** 2365 * i40e_inc_ntp: Advance the next_to_process index 2366 * @rx_ring: Rx ring 2367 **/ 2368 static void i40e_inc_ntp(struct i40e_ring *rx_ring) 2369 { 2370 u32 ntp = rx_ring->next_to_process + 1; 2371 2372 ntp = (ntp < rx_ring->count) ? ntp : 0; 2373 rx_ring->next_to_process = ntp; 2374 prefetch(I40E_RX_DESC(rx_ring, ntp)); 2375 } 2376 2377 /** 2378 * i40e_add_xdp_frag: Add a frag to xdp_buff 2379 * @xdp: xdp_buff pointing to the data 2380 * @nr_frags: return number of buffers for the packet 2381 * @rx_buffer: rx_buffer holding data of the current frag 2382 * @size: size of data of current frag 2383 */ 2384 static int i40e_add_xdp_frag(struct xdp_buff *xdp, u32 *nr_frags, 2385 struct i40e_rx_buffer *rx_buffer, u32 size) 2386 { 2387 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2388 2389 if (!xdp_buff_has_frags(xdp)) { 2390 sinfo->nr_frags = 0; 2391 sinfo->xdp_frags_size = 0; 2392 xdp_buff_set_frags_flag(xdp); 2393 } else if (unlikely(sinfo->nr_frags >= MAX_SKB_FRAGS)) { 2394 /* Overflowing packet: All frags need to be dropped */ 2395 return -ENOMEM; 2396 } 2397 2398 __skb_fill_page_desc_noacc(sinfo, sinfo->nr_frags++, rx_buffer->page, 2399 rx_buffer->page_offset, size); 2400 2401 sinfo->xdp_frags_size += size; 2402 2403 if (page_is_pfmemalloc(rx_buffer->page)) 2404 xdp_buff_set_frag_pfmemalloc(xdp); 2405 *nr_frags = sinfo->nr_frags; 2406 2407 return 0; 2408 } 2409 2410 /** 2411 * i40e_consume_xdp_buff - Consume all the buffers of the packet and update ntc 2412 * @rx_ring: rx descriptor ring to transact packets on 2413 * @xdp: xdp_buff pointing to the data 2414 * @rx_buffer: rx_buffer of eop desc 2415 */ 2416 static void i40e_consume_xdp_buff(struct i40e_ring *rx_ring, 2417 struct xdp_buff *xdp, 2418 struct i40e_rx_buffer *rx_buffer) 2419 { 2420 i40e_process_rx_buffs(rx_ring, I40E_XDP_CONSUMED, xdp); 2421 i40e_put_rx_buffer(rx_ring, rx_buffer); 2422 rx_ring->next_to_clean = rx_ring->next_to_process; 2423 xdp->data = NULL; 2424 } 2425 2426 /** 2427 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2428 * @rx_ring: rx descriptor ring to transact packets on 2429 * @budget: Total limit on number of packets to process 2430 * @rx_cleaned: Out parameter of the number of packets processed 2431 * 2432 * This function provides a "bounce buffer" approach to Rx interrupt 2433 * processing. The advantage to this is that on systems that have 2434 * expensive overhead for IOMMU access this provides a means of avoiding 2435 * it by maintaining the mapping of the page to the system. 2436 * 2437 * Returns amount of work completed 2438 **/ 2439 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget, 2440 unsigned int *rx_cleaned) 2441 { 2442 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2443 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); 2444 u16 clean_threshold = rx_ring->count / 2; 2445 unsigned int offset = rx_ring->rx_offset; 2446 struct xdp_buff *xdp = &rx_ring->xdp; 2447 unsigned int xdp_xmit = 0; 2448 struct bpf_prog *xdp_prog; 2449 bool failure = false; 2450 int xdp_res = 0; 2451 2452 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2453 2454 while (likely(total_rx_packets < (unsigned int)budget)) { 2455 u16 ntp = rx_ring->next_to_process; 2456 struct i40e_rx_buffer *rx_buffer; 2457 union i40e_rx_desc *rx_desc; 2458 struct sk_buff *skb; 2459 unsigned int size; 2460 u32 nfrags = 0; 2461 bool neop; 2462 u64 qword; 2463 2464 /* return some buffers to hardware, one at a time is too slow */ 2465 if (cleaned_count >= clean_threshold) { 2466 failure = failure || 2467 i40e_alloc_rx_buffers(rx_ring, cleaned_count); 2468 cleaned_count = 0; 2469 } 2470 2471 rx_desc = I40E_RX_DESC(rx_ring, ntp); 2472 2473 /* status_error_len will always be zero for unused descriptors 2474 * because it's cleared in cleanup, and overlaps with hdr_addr 2475 * which is always zero because packet split isn't used, if the 2476 * hardware wrote DD then the length will be non-zero 2477 */ 2478 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 2479 2480 /* This memory barrier is needed to keep us from reading 2481 * any other fields out of the rx_desc until we have 2482 * verified the descriptor has been written back. 2483 */ 2484 dma_rmb(); 2485 2486 if (i40e_rx_is_programming_status(qword)) { 2487 i40e_clean_programming_status(rx_ring, 2488 rx_desc->raw.qword[0], 2489 qword); 2490 rx_buffer = i40e_rx_bi(rx_ring, ntp); 2491 i40e_inc_ntp(rx_ring); 2492 i40e_reuse_rx_page(rx_ring, rx_buffer); 2493 /* Update ntc and bump cleaned count if not in the 2494 * middle of mb packet. 2495 */ 2496 if (rx_ring->next_to_clean == ntp) { 2497 rx_ring->next_to_clean = 2498 rx_ring->next_to_process; 2499 cleaned_count++; 2500 } 2501 continue; 2502 } 2503 2504 size = FIELD_GET(I40E_RXD_QW1_LENGTH_PBUF_MASK, qword); 2505 if (!size) 2506 break; 2507 2508 i40e_trace(clean_rx_irq, rx_ring, rx_desc, xdp); 2509 /* retrieve a buffer from the ring */ 2510 rx_buffer = i40e_get_rx_buffer(rx_ring, size); 2511 2512 neop = i40e_is_non_eop(rx_ring, rx_desc); 2513 i40e_inc_ntp(rx_ring); 2514 2515 if (!xdp->data) { 2516 unsigned char *hard_start; 2517 2518 hard_start = page_address(rx_buffer->page) + 2519 rx_buffer->page_offset - offset; 2520 xdp_prepare_buff(xdp, hard_start, offset, size, true); 2521 #if (PAGE_SIZE > 4096) 2522 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2523 xdp->frame_sz = i40e_rx_frame_truesize(rx_ring, size); 2524 #endif 2525 } else if (i40e_add_xdp_frag(xdp, &nfrags, rx_buffer, size) && 2526 !neop) { 2527 /* Overflowing packet: Drop all frags on EOP */ 2528 i40e_consume_xdp_buff(rx_ring, xdp, rx_buffer); 2529 break; 2530 } 2531 2532 if (neop) 2533 continue; 2534 2535 xdp_res = i40e_run_xdp(rx_ring, xdp, xdp_prog); 2536 2537 if (xdp_res) { 2538 xdp_xmit |= xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR); 2539 2540 if (unlikely(xdp_buff_has_frags(xdp))) { 2541 i40e_process_rx_buffs(rx_ring, xdp_res, xdp); 2542 size = xdp_get_buff_len(xdp); 2543 } else if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) { 2544 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2545 } else { 2546 rx_buffer->pagecnt_bias++; 2547 } 2548 total_rx_bytes += size; 2549 } else { 2550 if (ring_uses_build_skb(rx_ring)) 2551 skb = i40e_build_skb(rx_ring, xdp); 2552 else 2553 skb = i40e_construct_skb(rx_ring, xdp); 2554 2555 /* drop if we failed to retrieve a buffer */ 2556 if (!skb) { 2557 rx_ring->rx_stats.alloc_buff_failed++; 2558 i40e_consume_xdp_buff(rx_ring, xdp, rx_buffer); 2559 break; 2560 } 2561 2562 if (i40e_cleanup_headers(rx_ring, skb, rx_desc)) 2563 goto process_next; 2564 2565 /* probably a little skewed due to removing CRC */ 2566 total_rx_bytes += skb->len; 2567 2568 /* populate checksum, VLAN, and protocol */ 2569 i40e_process_skb_fields(rx_ring, rx_desc, skb); 2570 2571 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, xdp); 2572 napi_gro_receive(&rx_ring->q_vector->napi, skb); 2573 } 2574 2575 /* update budget accounting */ 2576 total_rx_packets++; 2577 process_next: 2578 cleaned_count += nfrags + 1; 2579 i40e_put_rx_buffer(rx_ring, rx_buffer); 2580 rx_ring->next_to_clean = rx_ring->next_to_process; 2581 2582 xdp->data = NULL; 2583 } 2584 2585 i40e_finalize_xdp_rx(rx_ring, xdp_xmit); 2586 2587 i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets); 2588 2589 *rx_cleaned = total_rx_packets; 2590 2591 /* guarantee a trip back through this routine if there was a failure */ 2592 return failure ? budget : (int)total_rx_packets; 2593 } 2594 2595 /** 2596 * i40e_buildreg_itr - build a value for writing to I40E_PFINT_DYN_CTLN register 2597 * @itr_idx: interrupt throttling index 2598 * @interval: interrupt throttling interval value in usecs 2599 * @force_swint: force software interrupt 2600 * 2601 * The function builds a value for I40E_PFINT_DYN_CTLN register that 2602 * is used to update interrupt throttling interval for specified ITR index 2603 * and optionally enforces a software interrupt. If the @itr_idx is equal 2604 * to I40E_ITR_NONE then no interval change is applied and only @force_swint 2605 * parameter is taken into account. If the interval change and enforced 2606 * software interrupt are not requested then the built value just enables 2607 * appropriate vector interrupt. 2608 **/ 2609 static u32 i40e_buildreg_itr(enum i40e_dyn_idx itr_idx, u16 interval, 2610 bool force_swint) 2611 { 2612 u32 val; 2613 2614 /* We don't bother with setting the CLEARPBA bit as the data sheet 2615 * points out doing so is "meaningless since it was already 2616 * auto-cleared". The auto-clearing happens when the interrupt is 2617 * asserted. 2618 * 2619 * Hardware errata 28 for also indicates that writing to a 2620 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear 2621 * an event in the PBA anyway so we need to rely on the automask 2622 * to hold pending events for us until the interrupt is re-enabled 2623 * 2624 * We have to shift the given value as it is reported in microseconds 2625 * and the register value is recorded in 2 microsecond units. 2626 */ 2627 interval >>= 1; 2628 2629 /* 1. Enable vector interrupt 2630 * 2. Update the interval for the specified ITR index 2631 * (I40E_ITR_NONE in the register is used to indicate that 2632 * no interval update is requested) 2633 */ 2634 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 2635 FIELD_PREP(I40E_PFINT_DYN_CTLN_ITR_INDX_MASK, itr_idx) | 2636 FIELD_PREP(I40E_PFINT_DYN_CTLN_INTERVAL_MASK, interval); 2637 2638 /* 3. Enforce software interrupt trigger if requested 2639 * (These software interrupts rate is limited by ITR2 that is 2640 * set to 20K interrupts per second) 2641 */ 2642 if (force_swint) 2643 val |= I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 2644 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK | 2645 FIELD_PREP(I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK, 2646 I40E_SW_ITR); 2647 2648 return val; 2649 } 2650 2651 /* The act of updating the ITR will cause it to immediately trigger. In order 2652 * to prevent this from throwing off adaptive update statistics we defer the 2653 * update so that it can only happen so often. So after either Tx or Rx are 2654 * updated we make the adaptive scheme wait until either the ITR completely 2655 * expires via the next_update expiration or we have been through at least 2656 * 3 interrupts. 2657 */ 2658 #define ITR_COUNTDOWN_START 3 2659 2660 /** 2661 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt 2662 * @vsi: the VSI we care about 2663 * @q_vector: q_vector for which itr is being updated and interrupt enabled 2664 * 2665 **/ 2666 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, 2667 struct i40e_q_vector *q_vector) 2668 { 2669 enum i40e_dyn_idx itr_idx = I40E_ITR_NONE; 2670 struct i40e_hw *hw = &vsi->back->hw; 2671 u16 interval = 0; 2672 u32 itr_val; 2673 2674 /* If we don't have MSIX, then we only need to re-enable icr0 */ 2675 if (!test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) { 2676 i40e_irq_dynamic_enable_icr0(vsi->back); 2677 return; 2678 } 2679 2680 /* These will do nothing if dynamic updates are not enabled */ 2681 i40e_update_itr(q_vector, &q_vector->tx); 2682 i40e_update_itr(q_vector, &q_vector->rx); 2683 2684 /* This block of logic allows us to get away with only updating 2685 * one ITR value with each interrupt. The idea is to perform a 2686 * pseudo-lazy update with the following criteria. 2687 * 2688 * 1. Rx is given higher priority than Tx if both are in same state 2689 * 2. If we must reduce an ITR that is given highest priority. 2690 * 3. We then give priority to increasing ITR based on amount. 2691 */ 2692 if (q_vector->rx.target_itr < q_vector->rx.current_itr) { 2693 /* Rx ITR needs to be reduced, this is highest priority */ 2694 itr_idx = I40E_RX_ITR; 2695 interval = q_vector->rx.target_itr; 2696 q_vector->rx.current_itr = q_vector->rx.target_itr; 2697 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2698 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) || 2699 ((q_vector->rx.target_itr - q_vector->rx.current_itr) < 2700 (q_vector->tx.target_itr - q_vector->tx.current_itr))) { 2701 /* Tx ITR needs to be reduced, this is second priority 2702 * Tx ITR needs to be increased more than Rx, fourth priority 2703 */ 2704 itr_idx = I40E_TX_ITR; 2705 interval = q_vector->tx.target_itr; 2706 q_vector->tx.current_itr = q_vector->tx.target_itr; 2707 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2708 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) { 2709 /* Rx ITR needs to be increased, third priority */ 2710 itr_idx = I40E_RX_ITR; 2711 interval = q_vector->rx.target_itr; 2712 q_vector->rx.current_itr = q_vector->rx.target_itr; 2713 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2714 } else { 2715 /* No ITR update, lowest priority */ 2716 if (q_vector->itr_countdown) 2717 q_vector->itr_countdown--; 2718 } 2719 2720 /* Do not update interrupt control register if VSI is down */ 2721 if (test_bit(__I40E_VSI_DOWN, vsi->state)) 2722 return; 2723 2724 /* Update ITR interval if necessary and enforce software interrupt 2725 * if we are exiting busy poll. 2726 */ 2727 if (q_vector->in_busy_poll) { 2728 itr_val = i40e_buildreg_itr(itr_idx, interval, true); 2729 q_vector->in_busy_poll = false; 2730 } else { 2731 itr_val = i40e_buildreg_itr(itr_idx, interval, false); 2732 } 2733 wr32(hw, I40E_PFINT_DYN_CTLN(q_vector->reg_idx), itr_val); 2734 } 2735 2736 /** 2737 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine 2738 * @napi: napi struct with our devices info in it 2739 * @budget: amount of work driver is allowed to do this pass, in packets 2740 * 2741 * This function will clean all queues associated with a q_vector. 2742 * 2743 * Returns the amount of work done 2744 **/ 2745 int i40e_napi_poll(struct napi_struct *napi, int budget) 2746 { 2747 struct i40e_q_vector *q_vector = 2748 container_of(napi, struct i40e_q_vector, napi); 2749 struct i40e_vsi *vsi = q_vector->vsi; 2750 struct i40e_ring *ring; 2751 bool tx_clean_complete = true; 2752 bool rx_clean_complete = true; 2753 unsigned int tx_cleaned = 0; 2754 unsigned int rx_cleaned = 0; 2755 bool clean_complete = true; 2756 bool arm_wb = false; 2757 int budget_per_ring; 2758 int work_done = 0; 2759 2760 if (test_bit(__I40E_VSI_DOWN, vsi->state)) { 2761 napi_complete(napi); 2762 return 0; 2763 } 2764 2765 /* Since the actual Tx work is minimal, we can give the Tx a larger 2766 * budget and be more aggressive about cleaning up the Tx descriptors. 2767 */ 2768 i40e_for_each_ring(ring, q_vector->tx) { 2769 bool wd = ring->xsk_pool ? 2770 i40e_clean_xdp_tx_irq(vsi, ring) : 2771 i40e_clean_tx_irq(vsi, ring, budget, &tx_cleaned); 2772 2773 if (!wd) { 2774 clean_complete = tx_clean_complete = false; 2775 continue; 2776 } 2777 arm_wb |= ring->arm_wb; 2778 ring->arm_wb = false; 2779 } 2780 2781 /* Handle case where we are called by netpoll with a budget of 0 */ 2782 if (budget <= 0) 2783 goto tx_only; 2784 2785 /* normally we have 1 Rx ring per q_vector */ 2786 if (unlikely(q_vector->num_ringpairs > 1)) 2787 /* We attempt to distribute budget to each Rx queue fairly, but 2788 * don't allow the budget to go below 1 because that would exit 2789 * polling early. 2790 */ 2791 budget_per_ring = max_t(int, budget / q_vector->num_ringpairs, 1); 2792 else 2793 /* Max of 1 Rx ring in this q_vector so give it the budget */ 2794 budget_per_ring = budget; 2795 2796 i40e_for_each_ring(ring, q_vector->rx) { 2797 int cleaned = ring->xsk_pool ? 2798 i40e_clean_rx_irq_zc(ring, budget_per_ring) : 2799 i40e_clean_rx_irq(ring, budget_per_ring, &rx_cleaned); 2800 2801 work_done += cleaned; 2802 /* if we clean as many as budgeted, we must not be done */ 2803 if (cleaned >= budget_per_ring) 2804 clean_complete = rx_clean_complete = false; 2805 } 2806 2807 if (!i40e_enabled_xdp_vsi(vsi)) 2808 trace_i40e_napi_poll(napi, q_vector, budget, budget_per_ring, rx_cleaned, 2809 tx_cleaned, rx_clean_complete, tx_clean_complete); 2810 2811 /* If work not completed, return budget and polling will return */ 2812 if (!clean_complete) { 2813 int cpu_id = smp_processor_id(); 2814 2815 /* It is possible that the interrupt affinity has changed but, 2816 * if the cpu is pegged at 100%, polling will never exit while 2817 * traffic continues and the interrupt will be stuck on this 2818 * cpu. We check to make sure affinity is correct before we 2819 * continue to poll, otherwise we must stop polling so the 2820 * interrupt can move to the correct cpu. 2821 */ 2822 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) { 2823 /* Tell napi that we are done polling */ 2824 napi_complete_done(napi, work_done); 2825 2826 /* Force an interrupt */ 2827 i40e_force_wb(vsi, q_vector); 2828 2829 /* Return budget-1 so that polling stops */ 2830 return budget - 1; 2831 } 2832 tx_only: 2833 if (arm_wb) { 2834 q_vector->tx.ring[0].tx_stats.tx_force_wb++; 2835 i40e_enable_wb_on_itr(vsi, q_vector); 2836 } 2837 return budget; 2838 } 2839 2840 if (q_vector->tx.ring[0].flags & I40E_TXR_FLAGS_WB_ON_ITR) 2841 q_vector->arm_wb_state = false; 2842 2843 /* Exit the polling mode, but don't re-enable interrupts if stack might 2844 * poll us due to busy-polling 2845 */ 2846 if (likely(napi_complete_done(napi, work_done))) 2847 i40e_update_enable_itr(vsi, q_vector); 2848 else 2849 q_vector->in_busy_poll = true; 2850 2851 return min(work_done, budget - 1); 2852 } 2853 2854 /** 2855 * i40e_atr - Add a Flow Director ATR filter 2856 * @tx_ring: ring to add programming descriptor to 2857 * @skb: send buffer 2858 * @tx_flags: send tx flags 2859 **/ 2860 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, 2861 u32 tx_flags) 2862 { 2863 struct i40e_filter_program_desc *fdir_desc; 2864 struct i40e_pf *pf = tx_ring->vsi->back; 2865 union { 2866 unsigned char *network; 2867 struct iphdr *ipv4; 2868 struct ipv6hdr *ipv6; 2869 } hdr; 2870 struct tcphdr *th; 2871 unsigned int hlen; 2872 u32 flex_ptype, dtype_cmd; 2873 int l4_proto; 2874 u16 i; 2875 2876 /* make sure ATR is enabled */ 2877 if (!test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags)) 2878 return; 2879 2880 if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) 2881 return; 2882 2883 /* if sampling is disabled do nothing */ 2884 if (!tx_ring->atr_sample_rate) 2885 return; 2886 2887 /* Currently only IPv4/IPv6 with TCP is supported */ 2888 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) 2889 return; 2890 2891 /* snag network header to get L4 type and address */ 2892 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? 2893 skb_inner_network_header(skb) : skb_network_header(skb); 2894 2895 /* Note: tx_flags gets modified to reflect inner protocols in 2896 * tx_enable_csum function if encap is enabled. 2897 */ 2898 if (tx_flags & I40E_TX_FLAGS_IPV4) { 2899 /* access ihl as u8 to avoid unaligned access on ia64 */ 2900 hlen = (hdr.network[0] & 0x0F) << 2; 2901 l4_proto = hdr.ipv4->protocol; 2902 } else { 2903 /* find the start of the innermost ipv6 header */ 2904 unsigned int inner_hlen = hdr.network - skb->data; 2905 unsigned int h_offset = inner_hlen; 2906 2907 /* this function updates h_offset to the end of the header */ 2908 l4_proto = 2909 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL); 2910 /* hlen will contain our best estimate of the tcp header */ 2911 hlen = h_offset - inner_hlen; 2912 } 2913 2914 if (l4_proto != IPPROTO_TCP) 2915 return; 2916 2917 th = (struct tcphdr *)(hdr.network + hlen); 2918 2919 /* Due to lack of space, no more new filters can be programmed */ 2920 if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) 2921 return; 2922 if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags)) { 2923 /* HW ATR eviction will take care of removing filters on FIN 2924 * and RST packets. 2925 */ 2926 if (th->fin || th->rst) 2927 return; 2928 } 2929 2930 tx_ring->atr_count++; 2931 2932 /* sample on all syn/fin/rst packets or once every atr sample rate */ 2933 if (!th->fin && 2934 !th->syn && 2935 !th->rst && 2936 (tx_ring->atr_count < tx_ring->atr_sample_rate)) 2937 return; 2938 2939 tx_ring->atr_count = 0; 2940 2941 /* grab the next descriptor */ 2942 i = tx_ring->next_to_use; 2943 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 2944 2945 i++; 2946 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2947 2948 flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK, 2949 tx_ring->queue_index); 2950 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? 2951 (LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP << 2952 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 2953 (LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP << 2954 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 2955 2956 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 2957 2958 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 2959 2960 dtype_cmd |= (th->fin || th->rst) ? 2961 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 2962 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 2963 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 2964 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 2965 2966 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 2967 I40E_TXD_FLTR_QW1_DEST_SHIFT; 2968 2969 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 2970 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 2971 2972 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 2973 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) 2974 dtype_cmd |= 2975 FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK, 2976 I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)); 2977 else 2978 dtype_cmd |= 2979 FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK, 2980 I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)); 2981 2982 if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags)) 2983 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; 2984 2985 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 2986 fdir_desc->rsvd = cpu_to_le32(0); 2987 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 2988 fdir_desc->fd_id = cpu_to_le32(0); 2989 } 2990 2991 /** 2992 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW 2993 * @skb: send buffer 2994 * @tx_ring: ring to send buffer on 2995 * @flags: the tx flags to be set 2996 * 2997 * Checks the skb and set up correspondingly several generic transmit flags 2998 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 2999 * 3000 * Returns error code indicate the frame should be dropped upon error and the 3001 * otherwise returns 0 to indicate the flags has been set properly. 3002 **/ 3003 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 3004 struct i40e_ring *tx_ring, 3005 u32 *flags) 3006 { 3007 __be16 protocol = skb->protocol; 3008 u32 tx_flags = 0; 3009 3010 if (protocol == htons(ETH_P_8021Q) && 3011 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 3012 /* When HW VLAN acceleration is turned off by the user the 3013 * stack sets the protocol to 8021q so that the driver 3014 * can take any steps required to support the SW only 3015 * VLAN handling. In our case the driver doesn't need 3016 * to take any further steps so just set the protocol 3017 * to the encapsulated ethertype. 3018 */ 3019 skb->protocol = vlan_get_protocol(skb); 3020 goto out; 3021 } 3022 3023 /* if we have a HW VLAN tag being added, default to the HW one */ 3024 if (skb_vlan_tag_present(skb)) { 3025 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; 3026 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 3027 /* else if it is a SW VLAN, check the next protocol and store the tag */ 3028 } else if (protocol == htons(ETH_P_8021Q)) { 3029 struct vlan_hdr *vhdr, _vhdr; 3030 3031 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 3032 if (!vhdr) 3033 return -EINVAL; 3034 3035 protocol = vhdr->h_vlan_encapsulated_proto; 3036 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; 3037 tx_flags |= I40E_TX_FLAGS_SW_VLAN; 3038 } 3039 3040 if (!test_bit(I40E_FLAG_DCB_ENA, tx_ring->vsi->back->flags)) 3041 goto out; 3042 3043 /* Insert 802.1p priority into VLAN header */ 3044 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || 3045 (skb->priority != TC_PRIO_CONTROL)) { 3046 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; 3047 tx_flags |= (skb->priority & 0x7) << 3048 I40E_TX_FLAGS_VLAN_PRIO_SHIFT; 3049 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { 3050 struct vlan_ethhdr *vhdr; 3051 int rc; 3052 3053 rc = skb_cow_head(skb, 0); 3054 if (rc < 0) 3055 return rc; 3056 vhdr = skb_vlan_eth_hdr(skb); 3057 vhdr->h_vlan_TCI = htons(tx_flags >> 3058 I40E_TX_FLAGS_VLAN_SHIFT); 3059 } else { 3060 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 3061 } 3062 } 3063 3064 out: 3065 *flags = tx_flags; 3066 return 0; 3067 } 3068 3069 /** 3070 * i40e_tso - set up the tso context descriptor 3071 * @first: pointer to first Tx buffer for xmit 3072 * @hdr_len: ptr to the size of the packet header 3073 * @cd_type_cmd_tso_mss: Quad Word 1 3074 * 3075 * Returns 0 if no TSO can happen, 1 if tso is going, or error 3076 **/ 3077 static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, 3078 u64 *cd_type_cmd_tso_mss) 3079 { 3080 struct sk_buff *skb = first->skb; 3081 u64 cd_cmd, cd_tso_len, cd_mss; 3082 __be16 protocol; 3083 union { 3084 struct iphdr *v4; 3085 struct ipv6hdr *v6; 3086 unsigned char *hdr; 3087 } ip; 3088 union { 3089 struct tcphdr *tcp; 3090 struct udphdr *udp; 3091 unsigned char *hdr; 3092 } l4; 3093 u32 paylen, l4_offset; 3094 u16 gso_size; 3095 int err; 3096 3097 if (skb->ip_summed != CHECKSUM_PARTIAL) 3098 return 0; 3099 3100 if (!skb_is_gso(skb)) 3101 return 0; 3102 3103 err = skb_cow_head(skb, 0); 3104 if (err < 0) 3105 return err; 3106 3107 protocol = vlan_get_protocol(skb); 3108 3109 if (eth_p_mpls(protocol)) 3110 ip.hdr = skb_inner_network_header(skb); 3111 else 3112 ip.hdr = skb_network_header(skb); 3113 l4.hdr = skb_checksum_start(skb); 3114 3115 /* initialize outer IP header fields */ 3116 if (ip.v4->version == 4) { 3117 ip.v4->tot_len = 0; 3118 ip.v4->check = 0; 3119 3120 first->tx_flags |= I40E_TX_FLAGS_TSO; 3121 } else { 3122 ip.v6->payload_len = 0; 3123 first->tx_flags |= I40E_TX_FLAGS_TSO; 3124 } 3125 3126 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 3127 SKB_GSO_GRE_CSUM | 3128 SKB_GSO_IPXIP4 | 3129 SKB_GSO_IPXIP6 | 3130 SKB_GSO_UDP_TUNNEL | 3131 SKB_GSO_UDP_TUNNEL_CSUM)) { 3132 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 3133 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { 3134 l4.udp->len = 0; 3135 3136 /* determine offset of outer transport header */ 3137 l4_offset = l4.hdr - skb->data; 3138 3139 /* remove payload length from outer checksum */ 3140 paylen = skb->len - l4_offset; 3141 csum_replace_by_diff(&l4.udp->check, 3142 (__force __wsum)htonl(paylen)); 3143 } 3144 3145 /* reset pointers to inner headers */ 3146 ip.hdr = skb_inner_network_header(skb); 3147 l4.hdr = skb_inner_transport_header(skb); 3148 3149 /* initialize inner IP header fields */ 3150 if (ip.v4->version == 4) { 3151 ip.v4->tot_len = 0; 3152 ip.v4->check = 0; 3153 } else { 3154 ip.v6->payload_len = 0; 3155 } 3156 } 3157 3158 /* determine offset of inner transport header */ 3159 l4_offset = l4.hdr - skb->data; 3160 3161 /* remove payload length from inner checksum */ 3162 paylen = skb->len - l4_offset; 3163 3164 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3165 csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen)); 3166 /* compute length of segmentation header */ 3167 *hdr_len = sizeof(*l4.udp) + l4_offset; 3168 } else { 3169 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); 3170 /* compute length of segmentation header */ 3171 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 3172 } 3173 3174 /* pull values out of skb_shinfo */ 3175 gso_size = skb_shinfo(skb)->gso_size; 3176 3177 /* update GSO size and bytecount with header size */ 3178 first->gso_segs = skb_shinfo(skb)->gso_segs; 3179 first->bytecount += (first->gso_segs - 1) * *hdr_len; 3180 3181 /* find the field values */ 3182 cd_cmd = I40E_TX_CTX_DESC_TSO; 3183 cd_tso_len = skb->len - *hdr_len; 3184 cd_mss = gso_size; 3185 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | 3186 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | 3187 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); 3188 return 1; 3189 } 3190 3191 /** 3192 * i40e_tsyn - set up the tsyn context descriptor 3193 * @tx_ring: ptr to the ring to send 3194 * @skb: ptr to the skb we're sending 3195 * @tx_flags: the collected send information 3196 * @cd_type_cmd_tso_mss: Quad Word 1 3197 * 3198 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen 3199 **/ 3200 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, 3201 u32 tx_flags, u64 *cd_type_cmd_tso_mss) 3202 { 3203 struct i40e_pf *pf; 3204 3205 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 3206 return 0; 3207 3208 /* Tx timestamps cannot be sampled when doing TSO */ 3209 if (tx_flags & I40E_TX_FLAGS_TSO) 3210 return 0; 3211 3212 /* only timestamp the outbound packet if the user has requested it and 3213 * we are not already transmitting a packet to be timestamped 3214 */ 3215 pf = i40e_netdev_to_pf(tx_ring->netdev); 3216 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags)) 3217 return 0; 3218 3219 if (pf->ptp_tx && 3220 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) { 3221 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3222 pf->ptp_tx_start = jiffies; 3223 pf->ptp_tx_skb = skb_get(skb); 3224 } else { 3225 pf->tx_hwtstamp_skipped++; 3226 return 0; 3227 } 3228 3229 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << 3230 I40E_TXD_CTX_QW1_CMD_SHIFT; 3231 3232 return 1; 3233 } 3234 3235 /** 3236 * i40e_tx_enable_csum - Enable Tx checksum offloads 3237 * @skb: send buffer 3238 * @tx_flags: pointer to Tx flags currently set 3239 * @td_cmd: Tx descriptor command bits to set 3240 * @td_offset: Tx descriptor header offsets to set 3241 * @tx_ring: Tx descriptor ring 3242 * @cd_tunneling: ptr to context desc bits 3243 **/ 3244 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, 3245 u32 *td_cmd, u32 *td_offset, 3246 struct i40e_ring *tx_ring, 3247 u32 *cd_tunneling) 3248 { 3249 union { 3250 struct iphdr *v4; 3251 struct ipv6hdr *v6; 3252 unsigned char *hdr; 3253 } ip; 3254 union { 3255 struct tcphdr *tcp; 3256 struct udphdr *udp; 3257 unsigned char *hdr; 3258 } l4; 3259 unsigned char *exthdr; 3260 u32 offset, cmd = 0; 3261 __be16 frag_off; 3262 __be16 protocol; 3263 u8 l4_proto = 0; 3264 3265 if (skb->ip_summed != CHECKSUM_PARTIAL) 3266 return 0; 3267 3268 protocol = vlan_get_protocol(skb); 3269 3270 if (eth_p_mpls(protocol)) { 3271 ip.hdr = skb_inner_network_header(skb); 3272 l4.hdr = skb_checksum_start(skb); 3273 } else { 3274 ip.hdr = skb_network_header(skb); 3275 l4.hdr = skb_transport_header(skb); 3276 } 3277 3278 /* set the tx_flags to indicate the IP protocol type. this is 3279 * required so that checksum header computation below is accurate. 3280 */ 3281 if (ip.v4->version == 4) 3282 *tx_flags |= I40E_TX_FLAGS_IPV4; 3283 else 3284 *tx_flags |= I40E_TX_FLAGS_IPV6; 3285 3286 /* compute outer L2 header size */ 3287 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; 3288 3289 if (skb->encapsulation) { 3290 u32 tunnel = 0; 3291 /* define outer network header type */ 3292 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 3293 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 3294 I40E_TX_CTX_EXT_IP_IPV4 : 3295 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; 3296 3297 l4_proto = ip.v4->protocol; 3298 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 3299 int ret; 3300 3301 tunnel |= I40E_TX_CTX_EXT_IP_IPV6; 3302 3303 exthdr = ip.hdr + sizeof(*ip.v6); 3304 l4_proto = ip.v6->nexthdr; 3305 ret = ipv6_skip_exthdr(skb, exthdr - skb->data, 3306 &l4_proto, &frag_off); 3307 if (ret < 0) 3308 return -1; 3309 } 3310 3311 /* define outer transport */ 3312 switch (l4_proto) { 3313 case IPPROTO_UDP: 3314 tunnel |= I40E_TXD_CTX_UDP_TUNNELING; 3315 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 3316 break; 3317 case IPPROTO_GRE: 3318 tunnel |= I40E_TXD_CTX_GRE_TUNNELING; 3319 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 3320 break; 3321 case IPPROTO_IPIP: 3322 case IPPROTO_IPV6: 3323 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 3324 l4.hdr = skb_inner_network_header(skb); 3325 break; 3326 default: 3327 if (*tx_flags & I40E_TX_FLAGS_TSO) 3328 return -1; 3329 3330 skb_checksum_help(skb); 3331 return 0; 3332 } 3333 3334 /* compute outer L3 header size */ 3335 tunnel |= ((l4.hdr - ip.hdr) / 4) << 3336 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; 3337 3338 /* switch IP header pointer from outer to inner header */ 3339 ip.hdr = skb_inner_network_header(skb); 3340 3341 /* compute tunnel header size */ 3342 tunnel |= ((ip.hdr - l4.hdr) / 2) << 3343 I40E_TXD_CTX_QW0_NATLEN_SHIFT; 3344 3345 /* indicate if we need to offload outer UDP header */ 3346 if ((*tx_flags & I40E_TX_FLAGS_TSO) && 3347 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 3348 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) 3349 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; 3350 3351 /* record tunnel offload values */ 3352 *cd_tunneling |= tunnel; 3353 3354 /* switch L4 header pointer from outer to inner */ 3355 l4.hdr = skb_inner_transport_header(skb); 3356 l4_proto = 0; 3357 3358 /* reset type as we transition from outer to inner headers */ 3359 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); 3360 if (ip.v4->version == 4) 3361 *tx_flags |= I40E_TX_FLAGS_IPV4; 3362 if (ip.v6->version == 6) 3363 *tx_flags |= I40E_TX_FLAGS_IPV6; 3364 } 3365 3366 /* Enable IP checksum offloads */ 3367 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 3368 l4_proto = ip.v4->protocol; 3369 /* the stack computes the IP header already, the only time we 3370 * need the hardware to recompute it is in the case of TSO. 3371 */ 3372 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 3373 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : 3374 I40E_TX_DESC_CMD_IIPT_IPV4; 3375 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 3376 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; 3377 3378 exthdr = ip.hdr + sizeof(*ip.v6); 3379 l4_proto = ip.v6->nexthdr; 3380 if (l4.hdr != exthdr) 3381 ipv6_skip_exthdr(skb, exthdr - skb->data, 3382 &l4_proto, &frag_off); 3383 } 3384 3385 /* compute inner L3 header size */ 3386 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 3387 3388 /* Enable L4 checksum offloads */ 3389 switch (l4_proto) { 3390 case IPPROTO_TCP: 3391 /* enable checksum offloads */ 3392 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; 3393 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 3394 break; 3395 case IPPROTO_SCTP: 3396 /* enable SCTP checksum offload */ 3397 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; 3398 offset |= (sizeof(struct sctphdr) >> 2) << 3399 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 3400 break; 3401 case IPPROTO_UDP: 3402 /* enable UDP checksum offload */ 3403 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; 3404 offset |= (sizeof(struct udphdr) >> 2) << 3405 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 3406 break; 3407 default: 3408 if (*tx_flags & I40E_TX_FLAGS_TSO) 3409 return -1; 3410 skb_checksum_help(skb); 3411 return 0; 3412 } 3413 3414 *td_cmd |= cmd; 3415 *td_offset |= offset; 3416 3417 return 1; 3418 } 3419 3420 /** 3421 * i40e_create_tx_ctx - Build the Tx context descriptor 3422 * @tx_ring: ring to create the descriptor on 3423 * @cd_type_cmd_tso_mss: Quad Word 1 3424 * @cd_tunneling: Quad Word 0 - bits 0-31 3425 * @cd_l2tag2: Quad Word 0 - bits 32-63 3426 **/ 3427 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, 3428 const u64 cd_type_cmd_tso_mss, 3429 const u32 cd_tunneling, const u32 cd_l2tag2) 3430 { 3431 struct i40e_tx_context_desc *context_desc; 3432 int i = tx_ring->next_to_use; 3433 3434 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && 3435 !cd_tunneling && !cd_l2tag2) 3436 return; 3437 3438 /* grab the next descriptor */ 3439 context_desc = I40E_TX_CTXTDESC(tx_ring, i); 3440 3441 i++; 3442 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 3443 3444 /* cpu_to_le32 and assign to struct fields */ 3445 context_desc->tunneling_params = cpu_to_le32(cd_tunneling); 3446 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); 3447 context_desc->rsvd = cpu_to_le16(0); 3448 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); 3449 } 3450 3451 /** 3452 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions 3453 * @tx_ring: the ring to be checked 3454 * @size: the size buffer we want to assure is available 3455 * 3456 * Returns -EBUSY if a stop is needed, else 0 3457 **/ 3458 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 3459 { 3460 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 3461 /* Memory barrier before checking head and tail */ 3462 smp_mb(); 3463 3464 ++tx_ring->tx_stats.tx_stopped; 3465 3466 /* Check again in a case another CPU has just made room available. */ 3467 if (likely(I40E_DESC_UNUSED(tx_ring) < size)) 3468 return -EBUSY; 3469 3470 /* A reprieve! - use start_queue because it doesn't call schedule */ 3471 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 3472 ++tx_ring->tx_stats.restart_queue; 3473 return 0; 3474 } 3475 3476 /** 3477 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet 3478 * @skb: send buffer 3479 * 3480 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire 3481 * and so we need to figure out the cases where we need to linearize the skb. 3482 * 3483 * For TSO we need to count the TSO header and segment payload separately. 3484 * As such we need to check cases where we have 7 fragments or more as we 3485 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for 3486 * the segment payload in the first descriptor, and another 7 for the 3487 * fragments. 3488 **/ 3489 bool __i40e_chk_linearize(struct sk_buff *skb) 3490 { 3491 const skb_frag_t *frag, *stale; 3492 int nr_frags, sum; 3493 3494 /* no need to check if number of frags is less than 7 */ 3495 nr_frags = skb_shinfo(skb)->nr_frags; 3496 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) 3497 return false; 3498 3499 /* We need to walk through the list and validate that each group 3500 * of 6 fragments totals at least gso_size. 3501 */ 3502 nr_frags -= I40E_MAX_BUFFER_TXD - 2; 3503 frag = &skb_shinfo(skb)->frags[0]; 3504 3505 /* Initialize size to the negative value of gso_size minus 1. We 3506 * use this as the worst case scenerio in which the frag ahead 3507 * of us only provides one byte which is why we are limited to 6 3508 * descriptors for a single transmit as the header and previous 3509 * fragment are already consuming 2 descriptors. 3510 */ 3511 sum = 1 - skb_shinfo(skb)->gso_size; 3512 3513 /* Add size of frags 0 through 4 to create our initial sum */ 3514 sum += skb_frag_size(frag++); 3515 sum += skb_frag_size(frag++); 3516 sum += skb_frag_size(frag++); 3517 sum += skb_frag_size(frag++); 3518 sum += skb_frag_size(frag++); 3519 3520 /* Walk through fragments adding latest fragment, testing it, and 3521 * then removing stale fragments from the sum. 3522 */ 3523 for (stale = &skb_shinfo(skb)->frags[0];; stale++) { 3524 int stale_size = skb_frag_size(stale); 3525 3526 sum += skb_frag_size(frag++); 3527 3528 /* The stale fragment may present us with a smaller 3529 * descriptor than the actual fragment size. To account 3530 * for that we need to remove all the data on the front and 3531 * figure out what the remainder would be in the last 3532 * descriptor associated with the fragment. 3533 */ 3534 if (stale_size > I40E_MAX_DATA_PER_TXD) { 3535 int align_pad = -(skb_frag_off(stale)) & 3536 (I40E_MAX_READ_REQ_SIZE - 1); 3537 3538 sum -= align_pad; 3539 stale_size -= align_pad; 3540 3541 do { 3542 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED; 3543 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED; 3544 } while (stale_size > I40E_MAX_DATA_PER_TXD); 3545 } 3546 3547 /* if sum is negative we failed to make sufficient progress */ 3548 if (sum < 0) 3549 return true; 3550 3551 if (!nr_frags--) 3552 break; 3553 3554 sum -= stale_size; 3555 } 3556 3557 return false; 3558 } 3559 3560 /** 3561 * i40e_tx_map - Build the Tx descriptor 3562 * @tx_ring: ring to send buffer on 3563 * @skb: send buffer 3564 * @first: first buffer info buffer to use 3565 * @tx_flags: collected send information 3566 * @hdr_len: size of the packet header 3567 * @td_cmd: the command field in the descriptor 3568 * @td_offset: offset for checksum or crc 3569 * 3570 * Returns 0 on success, -1 on failure to DMA 3571 **/ 3572 static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 3573 struct i40e_tx_buffer *first, u32 tx_flags, 3574 const u8 hdr_len, u32 td_cmd, u32 td_offset) 3575 { 3576 unsigned int data_len = skb->data_len; 3577 unsigned int size = skb_headlen(skb); 3578 skb_frag_t *frag; 3579 struct i40e_tx_buffer *tx_bi; 3580 struct i40e_tx_desc *tx_desc; 3581 u16 i = tx_ring->next_to_use; 3582 u32 td_tag = 0; 3583 dma_addr_t dma; 3584 u16 desc_count = 1; 3585 3586 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { 3587 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; 3588 td_tag = FIELD_GET(I40E_TX_FLAGS_VLAN_MASK, tx_flags); 3589 } 3590 3591 first->tx_flags = tx_flags; 3592 3593 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 3594 3595 tx_desc = I40E_TX_DESC(tx_ring, i); 3596 tx_bi = first; 3597 3598 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 3599 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 3600 3601 if (dma_mapping_error(tx_ring->dev, dma)) 3602 goto dma_error; 3603 3604 /* record length, and DMA address */ 3605 dma_unmap_len_set(tx_bi, len, size); 3606 dma_unmap_addr_set(tx_bi, dma, dma); 3607 3608 /* align size to end of page */ 3609 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); 3610 tx_desc->buffer_addr = cpu_to_le64(dma); 3611 3612 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { 3613 tx_desc->cmd_type_offset_bsz = 3614 build_ctob(td_cmd, td_offset, 3615 max_data, td_tag); 3616 3617 tx_desc++; 3618 i++; 3619 desc_count++; 3620 3621 if (i == tx_ring->count) { 3622 tx_desc = I40E_TX_DESC(tx_ring, 0); 3623 i = 0; 3624 } 3625 3626 dma += max_data; 3627 size -= max_data; 3628 3629 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 3630 tx_desc->buffer_addr = cpu_to_le64(dma); 3631 } 3632 3633 if (likely(!data_len)) 3634 break; 3635 3636 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, 3637 size, td_tag); 3638 3639 tx_desc++; 3640 i++; 3641 desc_count++; 3642 3643 if (i == tx_ring->count) { 3644 tx_desc = I40E_TX_DESC(tx_ring, 0); 3645 i = 0; 3646 } 3647 3648 size = skb_frag_size(frag); 3649 data_len -= size; 3650 3651 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 3652 DMA_TO_DEVICE); 3653 3654 tx_bi = &tx_ring->tx_bi[i]; 3655 } 3656 3657 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 3658 3659 i++; 3660 if (i == tx_ring->count) 3661 i = 0; 3662 3663 tx_ring->next_to_use = i; 3664 3665 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); 3666 3667 /* write last descriptor with EOP bit */ 3668 td_cmd |= I40E_TX_DESC_CMD_EOP; 3669 3670 /* We OR these values together to check both against 4 (WB_STRIDE) 3671 * below. This is safe since we don't re-use desc_count afterwards. 3672 */ 3673 desc_count |= ++tx_ring->packet_stride; 3674 3675 if (desc_count >= WB_STRIDE) { 3676 /* write last descriptor with RS bit set */ 3677 td_cmd |= I40E_TX_DESC_CMD_RS; 3678 tx_ring->packet_stride = 0; 3679 } 3680 3681 tx_desc->cmd_type_offset_bsz = 3682 build_ctob(td_cmd, td_offset, size, td_tag); 3683 3684 skb_tx_timestamp(skb); 3685 3686 /* Force memory writes to complete before letting h/w know there 3687 * are new descriptors to fetch. 3688 * 3689 * We also use this memory barrier to make certain all of the 3690 * status bits have been updated before next_to_watch is written. 3691 */ 3692 wmb(); 3693 3694 /* set next_to_watch value indicating a packet is present */ 3695 first->next_to_watch = tx_desc; 3696 3697 /* notify HW of packet */ 3698 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 3699 writel(i, tx_ring->tail); 3700 } 3701 3702 return 0; 3703 3704 dma_error: 3705 dev_info(tx_ring->dev, "TX DMA map failed\n"); 3706 3707 /* clear dma mappings for failed tx_bi map */ 3708 for (;;) { 3709 tx_bi = &tx_ring->tx_bi[i]; 3710 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); 3711 if (tx_bi == first) 3712 break; 3713 if (i == 0) 3714 i = tx_ring->count; 3715 i--; 3716 } 3717 3718 tx_ring->next_to_use = i; 3719 3720 return -1; 3721 } 3722 3723 static u16 i40e_swdcb_skb_tx_hash(struct net_device *dev, 3724 const struct sk_buff *skb, 3725 u16 num_tx_queues) 3726 { 3727 u32 jhash_initval_salt = 0xd631614b; 3728 u32 hash; 3729 3730 if (skb->sk && skb->sk->sk_hash) 3731 hash = skb->sk->sk_hash; 3732 else 3733 hash = (__force u16)skb->protocol ^ skb->hash; 3734 3735 hash = jhash_1word(hash, jhash_initval_salt); 3736 3737 return (u16)(((u64)hash * num_tx_queues) >> 32); 3738 } 3739 3740 u16 i40e_lan_select_queue(struct net_device *netdev, 3741 struct sk_buff *skb, 3742 struct net_device __always_unused *sb_dev) 3743 { 3744 struct i40e_netdev_priv *np = netdev_priv(netdev); 3745 struct i40e_vsi *vsi = np->vsi; 3746 struct i40e_hw *hw; 3747 u16 qoffset; 3748 u16 qcount; 3749 u8 tclass; 3750 u16 hash; 3751 u8 prio; 3752 3753 /* is DCB enabled at all? */ 3754 if (vsi->tc_config.numtc == 1 || 3755 i40e_is_tc_mqprio_enabled(vsi->back)) 3756 return netdev_pick_tx(netdev, skb, sb_dev); 3757 3758 prio = skb->priority; 3759 hw = &vsi->back->hw; 3760 tclass = hw->local_dcbx_config.etscfg.prioritytable[prio]; 3761 /* sanity check */ 3762 if (unlikely(!(vsi->tc_config.enabled_tc & BIT(tclass)))) 3763 tclass = 0; 3764 3765 /* select a queue assigned for the given TC */ 3766 qcount = vsi->tc_config.tc_info[tclass].qcount; 3767 hash = i40e_swdcb_skb_tx_hash(netdev, skb, qcount); 3768 3769 qoffset = vsi->tc_config.tc_info[tclass].qoffset; 3770 return qoffset + hash; 3771 } 3772 3773 /** 3774 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring 3775 * @xdpf: data to transmit 3776 * @xdp_ring: XDP Tx ring 3777 **/ 3778 static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf, 3779 struct i40e_ring *xdp_ring) 3780 { 3781 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 3782 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 3783 u16 i = 0, index = xdp_ring->next_to_use; 3784 struct i40e_tx_buffer *tx_head = &xdp_ring->tx_bi[index]; 3785 struct i40e_tx_buffer *tx_bi = tx_head; 3786 struct i40e_tx_desc *tx_desc = I40E_TX_DESC(xdp_ring, index); 3787 void *data = xdpf->data; 3788 u32 size = xdpf->len; 3789 3790 if (unlikely(I40E_DESC_UNUSED(xdp_ring) < 1 + nr_frags)) { 3791 xdp_ring->tx_stats.tx_busy++; 3792 return I40E_XDP_CONSUMED; 3793 } 3794 3795 tx_head->bytecount = xdp_get_frame_len(xdpf); 3796 tx_head->gso_segs = 1; 3797 tx_head->xdpf = xdpf; 3798 3799 for (;;) { 3800 dma_addr_t dma; 3801 3802 dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE); 3803 if (dma_mapping_error(xdp_ring->dev, dma)) 3804 goto unmap; 3805 3806 /* record length, and DMA address */ 3807 dma_unmap_len_set(tx_bi, len, size); 3808 dma_unmap_addr_set(tx_bi, dma, dma); 3809 3810 tx_desc->buffer_addr = cpu_to_le64(dma); 3811 tx_desc->cmd_type_offset_bsz = 3812 build_ctob(I40E_TX_DESC_CMD_ICRC, 0, size, 0); 3813 3814 if (++index == xdp_ring->count) 3815 index = 0; 3816 3817 if (i == nr_frags) 3818 break; 3819 3820 tx_bi = &xdp_ring->tx_bi[index]; 3821 tx_desc = I40E_TX_DESC(xdp_ring, index); 3822 3823 data = skb_frag_address(&sinfo->frags[i]); 3824 size = skb_frag_size(&sinfo->frags[i]); 3825 i++; 3826 } 3827 3828 tx_desc->cmd_type_offset_bsz |= 3829 cpu_to_le64(I40E_TXD_CMD << I40E_TXD_QW1_CMD_SHIFT); 3830 3831 /* Make certain all of the status bits have been updated 3832 * before next_to_watch is written. 3833 */ 3834 smp_wmb(); 3835 3836 xdp_ring->xdp_tx_active++; 3837 3838 tx_head->next_to_watch = tx_desc; 3839 xdp_ring->next_to_use = index; 3840 3841 return I40E_XDP_TX; 3842 3843 unmap: 3844 for (;;) { 3845 tx_bi = &xdp_ring->tx_bi[index]; 3846 if (dma_unmap_len(tx_bi, len)) 3847 dma_unmap_page(xdp_ring->dev, 3848 dma_unmap_addr(tx_bi, dma), 3849 dma_unmap_len(tx_bi, len), 3850 DMA_TO_DEVICE); 3851 dma_unmap_len_set(tx_bi, len, 0); 3852 if (tx_bi == tx_head) 3853 break; 3854 3855 if (!index) 3856 index += xdp_ring->count; 3857 index--; 3858 } 3859 3860 return I40E_XDP_CONSUMED; 3861 } 3862 3863 /** 3864 * i40e_xmit_frame_ring - Sends buffer on Tx ring 3865 * @skb: send buffer 3866 * @tx_ring: ring to send buffer on 3867 * 3868 * Returns NETDEV_TX_OK if sent, else an error code 3869 **/ 3870 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, 3871 struct i40e_ring *tx_ring) 3872 { 3873 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; 3874 u32 cd_tunneling = 0, cd_l2tag2 = 0; 3875 struct i40e_tx_buffer *first; 3876 u32 td_offset = 0; 3877 u32 tx_flags = 0; 3878 u32 td_cmd = 0; 3879 u8 hdr_len = 0; 3880 int tso, count; 3881 int tsyn; 3882 3883 /* prefetch the data, we'll need it later */ 3884 prefetch(skb->data); 3885 3886 i40e_trace(xmit_frame_ring, skb, tx_ring); 3887 3888 count = i40e_xmit_descriptor_count(skb); 3889 if (i40e_chk_linearize(skb, count)) { 3890 if (__skb_linearize(skb)) { 3891 dev_kfree_skb_any(skb); 3892 return NETDEV_TX_OK; 3893 } 3894 count = i40e_txd_use_count(skb->len); 3895 tx_ring->tx_stats.tx_linearize++; 3896 } 3897 3898 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, 3899 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, 3900 * + 4 desc gap to avoid the cache line where head is, 3901 * + 1 desc for context descriptor, 3902 * otherwise try next time 3903 */ 3904 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { 3905 tx_ring->tx_stats.tx_busy++; 3906 return NETDEV_TX_BUSY; 3907 } 3908 3909 /* record the location of the first descriptor for this packet */ 3910 first = &tx_ring->tx_bi[tx_ring->next_to_use]; 3911 first->skb = skb; 3912 first->bytecount = skb->len; 3913 first->gso_segs = 1; 3914 3915 /* prepare the xmit flags */ 3916 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) 3917 goto out_drop; 3918 3919 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); 3920 3921 if (tso < 0) 3922 goto out_drop; 3923 else if (tso) 3924 tx_flags |= I40E_TX_FLAGS_TSO; 3925 3926 /* Always offload the checksum, since it's in the data descriptor */ 3927 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, 3928 tx_ring, &cd_tunneling); 3929 if (tso < 0) 3930 goto out_drop; 3931 3932 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); 3933 3934 if (tsyn) 3935 tx_flags |= I40E_TX_FLAGS_TSYN; 3936 3937 /* always enable CRC insertion offload */ 3938 td_cmd |= I40E_TX_DESC_CMD_ICRC; 3939 3940 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, 3941 cd_tunneling, cd_l2tag2); 3942 3943 /* Add Flow Director ATR if it's enabled. 3944 * 3945 * NOTE: this must always be directly before the data descriptor. 3946 */ 3947 i40e_atr(tx_ring, skb, tx_flags); 3948 3949 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, 3950 td_cmd, td_offset)) 3951 goto cleanup_tx_tstamp; 3952 3953 return NETDEV_TX_OK; 3954 3955 out_drop: 3956 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring); 3957 dev_kfree_skb_any(first->skb); 3958 first->skb = NULL; 3959 cleanup_tx_tstamp: 3960 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) { 3961 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev); 3962 3963 dev_kfree_skb_any(pf->ptp_tx_skb); 3964 pf->ptp_tx_skb = NULL; 3965 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 3966 } 3967 3968 return NETDEV_TX_OK; 3969 } 3970 3971 /** 3972 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer 3973 * @skb: send buffer 3974 * @netdev: network interface device structure 3975 * 3976 * Returns NETDEV_TX_OK if sent, else an error code 3977 **/ 3978 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 3979 { 3980 struct i40e_netdev_priv *np = netdev_priv(netdev); 3981 struct i40e_vsi *vsi = np->vsi; 3982 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; 3983 3984 /* hardware can't handle really short frames, hardware padding works 3985 * beyond this point 3986 */ 3987 if (skb_put_padto(skb, I40E_MIN_TX_LEN)) 3988 return NETDEV_TX_OK; 3989 3990 return i40e_xmit_frame_ring(skb, tx_ring); 3991 } 3992 3993 /** 3994 * i40e_xdp_xmit - Implements ndo_xdp_xmit 3995 * @dev: netdev 3996 * @n: number of frames 3997 * @frames: array of XDP buffer pointers 3998 * @flags: XDP extra info 3999 * 4000 * Returns number of frames successfully sent. Failed frames 4001 * will be free'ed by XDP core. 4002 * 4003 * For error cases, a negative errno code is returned and no-frames 4004 * are transmitted (caller must handle freeing frames). 4005 **/ 4006 int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames, 4007 u32 flags) 4008 { 4009 struct i40e_netdev_priv *np = netdev_priv(dev); 4010 unsigned int queue_index = smp_processor_id(); 4011 struct i40e_vsi *vsi = np->vsi; 4012 struct i40e_pf *pf = vsi->back; 4013 struct i40e_ring *xdp_ring; 4014 int nxmit = 0; 4015 int i; 4016 4017 if (test_bit(__I40E_VSI_DOWN, vsi->state)) 4018 return -ENETDOWN; 4019 4020 if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs || 4021 test_bit(__I40E_CONFIG_BUSY, pf->state)) 4022 return -ENXIO; 4023 4024 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 4025 return -EINVAL; 4026 4027 xdp_ring = vsi->xdp_rings[queue_index]; 4028 4029 for (i = 0; i < n; i++) { 4030 struct xdp_frame *xdpf = frames[i]; 4031 int err; 4032 4033 err = i40e_xmit_xdp_ring(xdpf, xdp_ring); 4034 if (err != I40E_XDP_TX) 4035 break; 4036 nxmit++; 4037 } 4038 4039 if (unlikely(flags & XDP_XMIT_FLUSH)) 4040 i40e_xdp_ring_update_tail(xdp_ring); 4041 4042 return nxmit; 4043 } 4044