1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include <linux/prefetch.h> 28 #include <net/busy_poll.h> 29 #include <linux/bpf_trace.h> 30 #include "i40e.h" 31 #include "i40e_trace.h" 32 #include "i40e_prototype.h" 33 34 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, 35 u32 td_tag) 36 { 37 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | 38 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | 39 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | 40 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | 41 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); 42 } 43 44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) 45 /** 46 * i40e_fdir - Generate a Flow Director descriptor based on fdata 47 * @tx_ring: Tx ring to send buffer on 48 * @fdata: Flow director filter data 49 * @add: Indicate if we are adding a rule or deleting one 50 * 51 **/ 52 static void i40e_fdir(struct i40e_ring *tx_ring, 53 struct i40e_fdir_filter *fdata, bool add) 54 { 55 struct i40e_filter_program_desc *fdir_desc; 56 struct i40e_pf *pf = tx_ring->vsi->back; 57 u32 flex_ptype, dtype_cmd; 58 u16 i; 59 60 /* grab the next descriptor */ 61 i = tx_ring->next_to_use; 62 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 63 64 i++; 65 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 66 67 flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK & 68 (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT); 69 70 flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK & 71 (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); 72 73 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & 74 (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 75 76 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & 77 (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); 78 79 /* Use LAN VSI Id if not programmed by user */ 80 flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK & 81 ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) << 82 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT); 83 84 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 85 86 dtype_cmd |= add ? 87 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 88 I40E_TXD_FLTR_QW1_PCMD_SHIFT : 89 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 90 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 91 92 dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK & 93 (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT); 94 95 dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK & 96 (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT); 97 98 if (fdata->cnt_index) { 99 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 100 dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK & 101 ((u32)fdata->cnt_index << 102 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT); 103 } 104 105 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 106 fdir_desc->rsvd = cpu_to_le32(0); 107 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 108 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id); 109 } 110 111 #define I40E_FD_CLEAN_DELAY 10 112 /** 113 * i40e_program_fdir_filter - Program a Flow Director filter 114 * @fdir_data: Packet data that will be filter parameters 115 * @raw_packet: the pre-allocated packet buffer for FDir 116 * @pf: The PF pointer 117 * @add: True for add/update, False for remove 118 **/ 119 static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, 120 u8 *raw_packet, struct i40e_pf *pf, 121 bool add) 122 { 123 struct i40e_tx_buffer *tx_buf, *first; 124 struct i40e_tx_desc *tx_desc; 125 struct i40e_ring *tx_ring; 126 struct i40e_vsi *vsi; 127 struct device *dev; 128 dma_addr_t dma; 129 u32 td_cmd = 0; 130 u16 i; 131 132 /* find existing FDIR VSI */ 133 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); 134 if (!vsi) 135 return -ENOENT; 136 137 tx_ring = vsi->tx_rings[0]; 138 dev = tx_ring->dev; 139 140 /* we need two descriptors to add/del a filter and we can wait */ 141 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) { 142 if (!i) 143 return -EAGAIN; 144 msleep_interruptible(1); 145 } 146 147 dma = dma_map_single(dev, raw_packet, 148 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); 149 if (dma_mapping_error(dev, dma)) 150 goto dma_fail; 151 152 /* grab the next descriptor */ 153 i = tx_ring->next_to_use; 154 first = &tx_ring->tx_bi[i]; 155 i40e_fdir(tx_ring, fdir_data, add); 156 157 /* Now program a dummy descriptor */ 158 i = tx_ring->next_to_use; 159 tx_desc = I40E_TX_DESC(tx_ring, i); 160 tx_buf = &tx_ring->tx_bi[i]; 161 162 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 163 164 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); 165 166 /* record length, and DMA address */ 167 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); 168 dma_unmap_addr_set(tx_buf, dma, dma); 169 170 tx_desc->buffer_addr = cpu_to_le64(dma); 171 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; 172 173 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; 174 tx_buf->raw_buf = (void *)raw_packet; 175 176 tx_desc->cmd_type_offset_bsz = 177 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); 178 179 /* Force memory writes to complete before letting h/w 180 * know there are new descriptors to fetch. 181 */ 182 wmb(); 183 184 /* Mark the data descriptor to be watched */ 185 first->next_to_watch = tx_desc; 186 187 writel(tx_ring->next_to_use, tx_ring->tail); 188 return 0; 189 190 dma_fail: 191 return -1; 192 } 193 194 #define IP_HEADER_OFFSET 14 195 #define I40E_UDPIP_DUMMY_PACKET_LEN 42 196 /** 197 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters 198 * @vsi: pointer to the targeted VSI 199 * @fd_data: the flow director data required for the FDir descriptor 200 * @add: true adds a filter, false removes it 201 * 202 * Returns 0 if the filters were successfully added or removed 203 **/ 204 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, 205 struct i40e_fdir_filter *fd_data, 206 bool add) 207 { 208 struct i40e_pf *pf = vsi->back; 209 struct udphdr *udp; 210 struct iphdr *ip; 211 u8 *raw_packet; 212 int ret; 213 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 214 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, 215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 216 217 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 218 if (!raw_packet) 219 return -ENOMEM; 220 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); 221 222 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 223 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET 224 + sizeof(struct iphdr)); 225 226 ip->daddr = fd_data->dst_ip; 227 udp->dest = fd_data->dst_port; 228 ip->saddr = fd_data->src_ip; 229 udp->source = fd_data->src_port; 230 231 if (fd_data->flex_filter) { 232 u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN; 233 __be16 pattern = fd_data->flex_word; 234 u16 off = fd_data->flex_offset; 235 236 *((__force __be16 *)(payload + off)) = pattern; 237 } 238 239 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 240 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 241 if (ret) { 242 dev_info(&pf->pdev->dev, 243 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 244 fd_data->pctype, fd_data->fd_id, ret); 245 /* Free the packet buffer since it wasn't added to the ring */ 246 kfree(raw_packet); 247 return -EOPNOTSUPP; 248 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 249 if (add) 250 dev_info(&pf->pdev->dev, 251 "Filter OK for PCTYPE %d loc = %d\n", 252 fd_data->pctype, fd_data->fd_id); 253 else 254 dev_info(&pf->pdev->dev, 255 "Filter deleted for PCTYPE %d loc = %d\n", 256 fd_data->pctype, fd_data->fd_id); 257 } 258 259 if (add) 260 pf->fd_udp4_filter_cnt++; 261 else 262 pf->fd_udp4_filter_cnt--; 263 264 return 0; 265 } 266 267 #define I40E_TCPIP_DUMMY_PACKET_LEN 54 268 /** 269 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters 270 * @vsi: pointer to the targeted VSI 271 * @fd_data: the flow director data required for the FDir descriptor 272 * @add: true adds a filter, false removes it 273 * 274 * Returns 0 if the filters were successfully added or removed 275 **/ 276 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, 277 struct i40e_fdir_filter *fd_data, 278 bool add) 279 { 280 struct i40e_pf *pf = vsi->back; 281 struct tcphdr *tcp; 282 struct iphdr *ip; 283 u8 *raw_packet; 284 int ret; 285 /* Dummy packet */ 286 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 287 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, 288 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, 289 0x0, 0x72, 0, 0, 0, 0}; 290 291 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 292 if (!raw_packet) 293 return -ENOMEM; 294 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); 295 296 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 297 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET 298 + sizeof(struct iphdr)); 299 300 ip->daddr = fd_data->dst_ip; 301 tcp->dest = fd_data->dst_port; 302 ip->saddr = fd_data->src_ip; 303 tcp->source = fd_data->src_port; 304 305 if (fd_data->flex_filter) { 306 u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN; 307 __be16 pattern = fd_data->flex_word; 308 u16 off = fd_data->flex_offset; 309 310 *((__force __be16 *)(payload + off)) = pattern; 311 } 312 313 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; 314 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 315 if (ret) { 316 dev_info(&pf->pdev->dev, 317 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 318 fd_data->pctype, fd_data->fd_id, ret); 319 /* Free the packet buffer since it wasn't added to the ring */ 320 kfree(raw_packet); 321 return -EOPNOTSUPP; 322 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 323 if (add) 324 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", 325 fd_data->pctype, fd_data->fd_id); 326 else 327 dev_info(&pf->pdev->dev, 328 "Filter deleted for PCTYPE %d loc = %d\n", 329 fd_data->pctype, fd_data->fd_id); 330 } 331 332 if (add) { 333 pf->fd_tcp4_filter_cnt++; 334 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && 335 I40E_DEBUG_FD & pf->hw.debug_mask) 336 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); 337 pf->flags |= I40E_FLAG_FD_ATR_AUTO_DISABLED; 338 } else { 339 pf->fd_tcp4_filter_cnt--; 340 } 341 342 return 0; 343 } 344 345 #define I40E_SCTPIP_DUMMY_PACKET_LEN 46 346 /** 347 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for 348 * a specific flow spec 349 * @vsi: pointer to the targeted VSI 350 * @fd_data: the flow director data required for the FDir descriptor 351 * @add: true adds a filter, false removes it 352 * 353 * Returns 0 if the filters were successfully added or removed 354 **/ 355 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, 356 struct i40e_fdir_filter *fd_data, 357 bool add) 358 { 359 struct i40e_pf *pf = vsi->back; 360 struct sctphdr *sctp; 361 struct iphdr *ip; 362 u8 *raw_packet; 363 int ret; 364 /* Dummy packet */ 365 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 366 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0, 367 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 368 369 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 370 if (!raw_packet) 371 return -ENOMEM; 372 memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN); 373 374 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 375 sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET 376 + sizeof(struct iphdr)); 377 378 ip->daddr = fd_data->dst_ip; 379 sctp->dest = fd_data->dst_port; 380 ip->saddr = fd_data->src_ip; 381 sctp->source = fd_data->src_port; 382 383 if (fd_data->flex_filter) { 384 u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN; 385 __be16 pattern = fd_data->flex_word; 386 u16 off = fd_data->flex_offset; 387 388 *((__force __be16 *)(payload + off)) = pattern; 389 } 390 391 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP; 392 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 393 if (ret) { 394 dev_info(&pf->pdev->dev, 395 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 396 fd_data->pctype, fd_data->fd_id, ret); 397 /* Free the packet buffer since it wasn't added to the ring */ 398 kfree(raw_packet); 399 return -EOPNOTSUPP; 400 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 401 if (add) 402 dev_info(&pf->pdev->dev, 403 "Filter OK for PCTYPE %d loc = %d\n", 404 fd_data->pctype, fd_data->fd_id); 405 else 406 dev_info(&pf->pdev->dev, 407 "Filter deleted for PCTYPE %d loc = %d\n", 408 fd_data->pctype, fd_data->fd_id); 409 } 410 411 if (add) 412 pf->fd_sctp4_filter_cnt++; 413 else 414 pf->fd_sctp4_filter_cnt--; 415 416 return 0; 417 } 418 419 #define I40E_IP_DUMMY_PACKET_LEN 34 420 /** 421 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for 422 * a specific flow spec 423 * @vsi: pointer to the targeted VSI 424 * @fd_data: the flow director data required for the FDir descriptor 425 * @add: true adds a filter, false removes it 426 * 427 * Returns 0 if the filters were successfully added or removed 428 **/ 429 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, 430 struct i40e_fdir_filter *fd_data, 431 bool add) 432 { 433 struct i40e_pf *pf = vsi->back; 434 struct iphdr *ip; 435 u8 *raw_packet; 436 int ret; 437 int i; 438 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 439 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, 440 0, 0, 0, 0}; 441 442 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; 443 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { 444 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 445 if (!raw_packet) 446 return -ENOMEM; 447 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); 448 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 449 450 ip->saddr = fd_data->src_ip; 451 ip->daddr = fd_data->dst_ip; 452 ip->protocol = 0; 453 454 if (fd_data->flex_filter) { 455 u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN; 456 __be16 pattern = fd_data->flex_word; 457 u16 off = fd_data->flex_offset; 458 459 *((__force __be16 *)(payload + off)) = pattern; 460 } 461 462 fd_data->pctype = i; 463 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 464 if (ret) { 465 dev_info(&pf->pdev->dev, 466 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 467 fd_data->pctype, fd_data->fd_id, ret); 468 /* The packet buffer wasn't added to the ring so we 469 * need to free it now. 470 */ 471 kfree(raw_packet); 472 return -EOPNOTSUPP; 473 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 474 if (add) 475 dev_info(&pf->pdev->dev, 476 "Filter OK for PCTYPE %d loc = %d\n", 477 fd_data->pctype, fd_data->fd_id); 478 else 479 dev_info(&pf->pdev->dev, 480 "Filter deleted for PCTYPE %d loc = %d\n", 481 fd_data->pctype, fd_data->fd_id); 482 } 483 } 484 485 if (add) 486 pf->fd_ip4_filter_cnt++; 487 else 488 pf->fd_ip4_filter_cnt--; 489 490 return 0; 491 } 492 493 /** 494 * i40e_add_del_fdir - Build raw packets to add/del fdir filter 495 * @vsi: pointer to the targeted VSI 496 * @cmd: command to get or set RX flow classification rules 497 * @add: true adds a filter, false removes it 498 * 499 **/ 500 int i40e_add_del_fdir(struct i40e_vsi *vsi, 501 struct i40e_fdir_filter *input, bool add) 502 { 503 struct i40e_pf *pf = vsi->back; 504 int ret; 505 506 switch (input->flow_type & ~FLOW_EXT) { 507 case TCP_V4_FLOW: 508 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 509 break; 510 case UDP_V4_FLOW: 511 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 512 break; 513 case SCTP_V4_FLOW: 514 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 515 break; 516 case IP_USER_FLOW: 517 switch (input->ip4_proto) { 518 case IPPROTO_TCP: 519 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 520 break; 521 case IPPROTO_UDP: 522 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 523 break; 524 case IPPROTO_SCTP: 525 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 526 break; 527 case IPPROTO_IP: 528 ret = i40e_add_del_fdir_ipv4(vsi, input, add); 529 break; 530 default: 531 /* We cannot support masking based on protocol */ 532 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n", 533 input->ip4_proto); 534 return -EINVAL; 535 } 536 break; 537 default: 538 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n", 539 input->flow_type); 540 return -EINVAL; 541 } 542 543 /* The buffer allocated here will be normally be freed by 544 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit 545 * completion. In the event of an error adding the buffer to the FDIR 546 * ring, it will immediately be freed. It may also be freed by 547 * i40e_clean_tx_ring() when closing the VSI. 548 */ 549 return ret; 550 } 551 552 /** 553 * i40e_fd_handle_status - check the Programming Status for FD 554 * @rx_ring: the Rx ring for this descriptor 555 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. 556 * @prog_id: the id originally used for programming 557 * 558 * This is used to verify if the FD programming or invalidation 559 * requested by SW to the HW is successful or not and take actions accordingly. 560 **/ 561 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, 562 union i40e_rx_desc *rx_desc, u8 prog_id) 563 { 564 struct i40e_pf *pf = rx_ring->vsi->back; 565 struct pci_dev *pdev = pf->pdev; 566 u32 fcnt_prog, fcnt_avail; 567 u32 error; 568 u64 qw; 569 570 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 571 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> 572 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; 573 574 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { 575 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id); 576 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || 577 (I40E_DEBUG_FD & pf->hw.debug_mask)) 578 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", 579 pf->fd_inv); 580 581 /* Check if the programming error is for ATR. 582 * If so, auto disable ATR and set a state for 583 * flush in progress. Next time we come here if flush is in 584 * progress do nothing, once flush is complete the state will 585 * be cleared. 586 */ 587 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) 588 return; 589 590 pf->fd_add_err++; 591 /* store the current atr filter count */ 592 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); 593 594 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) && 595 pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED) { 596 pf->flags |= I40E_FLAG_FD_ATR_AUTO_DISABLED; 597 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); 598 } 599 600 /* filter programming failed most likely due to table full */ 601 fcnt_prog = i40e_get_global_fd_count(pf); 602 fcnt_avail = pf->fdir_pf_filter_count; 603 /* If ATR is running fcnt_prog can quickly change, 604 * if we are very close to full, it makes sense to disable 605 * FD ATR/SB and then re-enable it when there is room. 606 */ 607 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { 608 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && 609 !(pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED)) { 610 pf->flags |= I40E_FLAG_FD_SB_AUTO_DISABLED; 611 if (I40E_DEBUG_FD & pf->hw.debug_mask) 612 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); 613 } 614 } 615 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { 616 if (I40E_DEBUG_FD & pf->hw.debug_mask) 617 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", 618 rx_desc->wb.qword0.hi_dword.fd_id); 619 } 620 } 621 622 /** 623 * i40e_unmap_and_free_tx_resource - Release a Tx buffer 624 * @ring: the ring that owns the buffer 625 * @tx_buffer: the buffer to free 626 **/ 627 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, 628 struct i40e_tx_buffer *tx_buffer) 629 { 630 if (tx_buffer->skb) { 631 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) 632 kfree(tx_buffer->raw_buf); 633 else if (ring_is_xdp(ring)) 634 page_frag_free(tx_buffer->raw_buf); 635 else 636 dev_kfree_skb_any(tx_buffer->skb); 637 if (dma_unmap_len(tx_buffer, len)) 638 dma_unmap_single(ring->dev, 639 dma_unmap_addr(tx_buffer, dma), 640 dma_unmap_len(tx_buffer, len), 641 DMA_TO_DEVICE); 642 } else if (dma_unmap_len(tx_buffer, len)) { 643 dma_unmap_page(ring->dev, 644 dma_unmap_addr(tx_buffer, dma), 645 dma_unmap_len(tx_buffer, len), 646 DMA_TO_DEVICE); 647 } 648 649 tx_buffer->next_to_watch = NULL; 650 tx_buffer->skb = NULL; 651 dma_unmap_len_set(tx_buffer, len, 0); 652 /* tx_buffer must be completely set up in the transmit path */ 653 } 654 655 /** 656 * i40e_clean_tx_ring - Free any empty Tx buffers 657 * @tx_ring: ring to be cleaned 658 **/ 659 void i40e_clean_tx_ring(struct i40e_ring *tx_ring) 660 { 661 unsigned long bi_size; 662 u16 i; 663 664 /* ring already cleared, nothing to do */ 665 if (!tx_ring->tx_bi) 666 return; 667 668 /* Free all the Tx ring sk_buffs */ 669 for (i = 0; i < tx_ring->count; i++) 670 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); 671 672 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 673 memset(tx_ring->tx_bi, 0, bi_size); 674 675 /* Zero out the descriptor ring */ 676 memset(tx_ring->desc, 0, tx_ring->size); 677 678 tx_ring->next_to_use = 0; 679 tx_ring->next_to_clean = 0; 680 681 if (!tx_ring->netdev) 682 return; 683 684 /* cleanup Tx queue statistics */ 685 netdev_tx_reset_queue(txring_txq(tx_ring)); 686 } 687 688 /** 689 * i40e_free_tx_resources - Free Tx resources per queue 690 * @tx_ring: Tx descriptor ring for a specific queue 691 * 692 * Free all transmit software resources 693 **/ 694 void i40e_free_tx_resources(struct i40e_ring *tx_ring) 695 { 696 i40e_clean_tx_ring(tx_ring); 697 kfree(tx_ring->tx_bi); 698 tx_ring->tx_bi = NULL; 699 700 if (tx_ring->desc) { 701 dma_free_coherent(tx_ring->dev, tx_ring->size, 702 tx_ring->desc, tx_ring->dma); 703 tx_ring->desc = NULL; 704 } 705 } 706 707 /** 708 * i40e_get_tx_pending - how many tx descriptors not processed 709 * @tx_ring: the ring of descriptors 710 * 711 * Since there is no access to the ring head register 712 * in XL710, we need to use our local copies 713 **/ 714 u32 i40e_get_tx_pending(struct i40e_ring *ring) 715 { 716 u32 head, tail; 717 718 head = i40e_get_head(ring); 719 tail = readl(ring->tail); 720 721 if (head != tail) 722 return (head < tail) ? 723 tail - head : (tail + ring->count - head); 724 725 return 0; 726 } 727 728 #define WB_STRIDE 4 729 730 /** 731 * i40e_clean_tx_irq - Reclaim resources after transmit completes 732 * @vsi: the VSI we care about 733 * @tx_ring: Tx ring to clean 734 * @napi_budget: Used to determine if we are in netpoll 735 * 736 * Returns true if there's any budget left (e.g. the clean is finished) 737 **/ 738 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, 739 struct i40e_ring *tx_ring, int napi_budget) 740 { 741 u16 i = tx_ring->next_to_clean; 742 struct i40e_tx_buffer *tx_buf; 743 struct i40e_tx_desc *tx_head; 744 struct i40e_tx_desc *tx_desc; 745 unsigned int total_bytes = 0, total_packets = 0; 746 unsigned int budget = vsi->work_limit; 747 748 tx_buf = &tx_ring->tx_bi[i]; 749 tx_desc = I40E_TX_DESC(tx_ring, i); 750 i -= tx_ring->count; 751 752 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); 753 754 do { 755 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; 756 757 /* if next_to_watch is not set then there is no work pending */ 758 if (!eop_desc) 759 break; 760 761 /* prevent any other reads prior to eop_desc */ 762 read_barrier_depends(); 763 764 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); 765 /* we have caught up to head, no work left to do */ 766 if (tx_head == tx_desc) 767 break; 768 769 /* clear next_to_watch to prevent false hangs */ 770 tx_buf->next_to_watch = NULL; 771 772 /* update the statistics for this packet */ 773 total_bytes += tx_buf->bytecount; 774 total_packets += tx_buf->gso_segs; 775 776 /* free the skb/XDP data */ 777 if (ring_is_xdp(tx_ring)) 778 page_frag_free(tx_buf->raw_buf); 779 else 780 napi_consume_skb(tx_buf->skb, napi_budget); 781 782 /* unmap skb header data */ 783 dma_unmap_single(tx_ring->dev, 784 dma_unmap_addr(tx_buf, dma), 785 dma_unmap_len(tx_buf, len), 786 DMA_TO_DEVICE); 787 788 /* clear tx_buffer data */ 789 tx_buf->skb = NULL; 790 dma_unmap_len_set(tx_buf, len, 0); 791 792 /* unmap remaining buffers */ 793 while (tx_desc != eop_desc) { 794 i40e_trace(clean_tx_irq_unmap, 795 tx_ring, tx_desc, tx_buf); 796 797 tx_buf++; 798 tx_desc++; 799 i++; 800 if (unlikely(!i)) { 801 i -= tx_ring->count; 802 tx_buf = tx_ring->tx_bi; 803 tx_desc = I40E_TX_DESC(tx_ring, 0); 804 } 805 806 /* unmap any remaining paged data */ 807 if (dma_unmap_len(tx_buf, len)) { 808 dma_unmap_page(tx_ring->dev, 809 dma_unmap_addr(tx_buf, dma), 810 dma_unmap_len(tx_buf, len), 811 DMA_TO_DEVICE); 812 dma_unmap_len_set(tx_buf, len, 0); 813 } 814 } 815 816 /* move us one more past the eop_desc for start of next pkt */ 817 tx_buf++; 818 tx_desc++; 819 i++; 820 if (unlikely(!i)) { 821 i -= tx_ring->count; 822 tx_buf = tx_ring->tx_bi; 823 tx_desc = I40E_TX_DESC(tx_ring, 0); 824 } 825 826 prefetch(tx_desc); 827 828 /* update budget accounting */ 829 budget--; 830 } while (likely(budget)); 831 832 i += tx_ring->count; 833 tx_ring->next_to_clean = i; 834 u64_stats_update_begin(&tx_ring->syncp); 835 tx_ring->stats.bytes += total_bytes; 836 tx_ring->stats.packets += total_packets; 837 u64_stats_update_end(&tx_ring->syncp); 838 tx_ring->q_vector->tx.total_bytes += total_bytes; 839 tx_ring->q_vector->tx.total_packets += total_packets; 840 841 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { 842 /* check to see if there are < 4 descriptors 843 * waiting to be written back, then kick the hardware to force 844 * them to be written back in case we stay in NAPI. 845 * In this mode on X722 we do not enable Interrupt. 846 */ 847 unsigned int j = i40e_get_tx_pending(tx_ring); 848 849 if (budget && 850 ((j / WB_STRIDE) == 0) && (j > 0) && 851 !test_bit(__I40E_VSI_DOWN, vsi->state) && 852 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) 853 tx_ring->arm_wb = true; 854 } 855 856 if (ring_is_xdp(tx_ring)) 857 return !!budget; 858 859 /* notify netdev of completed buffers */ 860 netdev_tx_completed_queue(txring_txq(tx_ring), 861 total_packets, total_bytes); 862 863 #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2)) 864 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 865 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 866 /* Make sure that anybody stopping the queue after this 867 * sees the new next_to_clean. 868 */ 869 smp_mb(); 870 if (__netif_subqueue_stopped(tx_ring->netdev, 871 tx_ring->queue_index) && 872 !test_bit(__I40E_VSI_DOWN, vsi->state)) { 873 netif_wake_subqueue(tx_ring->netdev, 874 tx_ring->queue_index); 875 ++tx_ring->tx_stats.restart_queue; 876 } 877 } 878 879 return !!budget; 880 } 881 882 /** 883 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled 884 * @vsi: the VSI we care about 885 * @q_vector: the vector on which to enable writeback 886 * 887 **/ 888 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, 889 struct i40e_q_vector *q_vector) 890 { 891 u16 flags = q_vector->tx.ring[0].flags; 892 u32 val; 893 894 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) 895 return; 896 897 if (q_vector->arm_wb_state) 898 return; 899 900 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 901 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | 902 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ 903 904 wr32(&vsi->back->hw, 905 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), 906 val); 907 } else { 908 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | 909 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ 910 911 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 912 } 913 q_vector->arm_wb_state = true; 914 } 915 916 /** 917 * i40e_force_wb - Issue SW Interrupt so HW does a wb 918 * @vsi: the VSI we care about 919 * @q_vector: the vector on which to force writeback 920 * 921 **/ 922 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) 923 { 924 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 925 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 926 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ 927 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 928 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; 929 /* allow 00 to be written to the index */ 930 931 wr32(&vsi->back->hw, 932 I40E_PFINT_DYN_CTLN(q_vector->v_idx + 933 vsi->base_vector - 1), val); 934 } else { 935 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | 936 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ 937 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | 938 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; 939 /* allow 00 to be written to the index */ 940 941 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 942 } 943 } 944 945 /** 946 * i40e_set_new_dynamic_itr - Find new ITR level 947 * @rc: structure containing ring performance data 948 * 949 * Returns true if ITR changed, false if not 950 * 951 * Stores a new ITR value based on packets and byte counts during 952 * the last interrupt. The advantage of per interrupt computation 953 * is faster updates and more accurate ITR for the current traffic 954 * pattern. Constants in this function were computed based on 955 * theoretical maximum wire speed and thresholds were set based on 956 * testing data as well as attempting to minimize response time 957 * while increasing bulk throughput. 958 **/ 959 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) 960 { 961 enum i40e_latency_range new_latency_range = rc->latency_range; 962 u32 new_itr = rc->itr; 963 int bytes_per_usec; 964 unsigned int usecs, estimated_usecs; 965 966 if (rc->total_packets == 0 || !rc->itr) 967 return false; 968 969 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; 970 bytes_per_usec = rc->total_bytes / usecs; 971 972 /* The calculations in this algorithm depend on interrupts actually 973 * firing at the ITR rate. This may not happen if the packet rate is 974 * really low, or if we've been napi polling. Check to make sure 975 * that's not the case before we continue. 976 */ 977 estimated_usecs = jiffies_to_usecs(jiffies - rc->last_itr_update); 978 if (estimated_usecs > usecs) { 979 new_latency_range = I40E_LOW_LATENCY; 980 goto reset_latency; 981 } 982 983 /* simple throttlerate management 984 * 0-10MB/s lowest (50000 ints/s) 985 * 10-20MB/s low (20000 ints/s) 986 * 20-1249MB/s bulk (18000 ints/s) 987 * 988 * The math works out because the divisor is in 10^(-6) which 989 * turns the bytes/us input value into MB/s values, but 990 * make sure to use usecs, as the register values written 991 * are in 2 usec increments in the ITR registers, and make sure 992 * to use the smoothed values that the countdown timer gives us. 993 */ 994 switch (new_latency_range) { 995 case I40E_LOWEST_LATENCY: 996 if (bytes_per_usec > 10) 997 new_latency_range = I40E_LOW_LATENCY; 998 break; 999 case I40E_LOW_LATENCY: 1000 if (bytes_per_usec > 20) 1001 new_latency_range = I40E_BULK_LATENCY; 1002 else if (bytes_per_usec <= 10) 1003 new_latency_range = I40E_LOWEST_LATENCY; 1004 break; 1005 case I40E_BULK_LATENCY: 1006 default: 1007 if (bytes_per_usec <= 20) 1008 new_latency_range = I40E_LOW_LATENCY; 1009 break; 1010 } 1011 1012 reset_latency: 1013 rc->latency_range = new_latency_range; 1014 1015 switch (new_latency_range) { 1016 case I40E_LOWEST_LATENCY: 1017 new_itr = I40E_ITR_50K; 1018 break; 1019 case I40E_LOW_LATENCY: 1020 new_itr = I40E_ITR_20K; 1021 break; 1022 case I40E_BULK_LATENCY: 1023 new_itr = I40E_ITR_18K; 1024 break; 1025 default: 1026 break; 1027 } 1028 1029 rc->total_bytes = 0; 1030 rc->total_packets = 0; 1031 rc->last_itr_update = jiffies; 1032 1033 if (new_itr != rc->itr) { 1034 rc->itr = new_itr; 1035 return true; 1036 } 1037 return false; 1038 } 1039 1040 /** 1041 * i40e_reuse_rx_page - page flip buffer and store it back on the ring 1042 * @rx_ring: rx descriptor ring to store buffers on 1043 * @old_buff: donor buffer to have page reused 1044 * 1045 * Synchronizes page for reuse by the adapter 1046 **/ 1047 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, 1048 struct i40e_rx_buffer *old_buff) 1049 { 1050 struct i40e_rx_buffer *new_buff; 1051 u16 nta = rx_ring->next_to_alloc; 1052 1053 new_buff = &rx_ring->rx_bi[nta]; 1054 1055 /* update, and store next to alloc */ 1056 nta++; 1057 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1058 1059 /* transfer page from old buffer to new buffer */ 1060 new_buff->dma = old_buff->dma; 1061 new_buff->page = old_buff->page; 1062 new_buff->page_offset = old_buff->page_offset; 1063 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1064 } 1065 1066 /** 1067 * i40e_rx_is_programming_status - check for programming status descriptor 1068 * @qw: qword representing status_error_len in CPU ordering 1069 * 1070 * The value of in the descriptor length field indicate if this 1071 * is a programming status descriptor for flow director or FCoE 1072 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise 1073 * it is a packet descriptor. 1074 **/ 1075 static inline bool i40e_rx_is_programming_status(u64 qw) 1076 { 1077 /* The Rx filter programming status and SPH bit occupy the same 1078 * spot in the descriptor. Since we don't support packet split we 1079 * can just reuse the bit as an indication that this is a 1080 * programming status descriptor. 1081 */ 1082 return qw & I40E_RXD_QW1_LENGTH_SPH_MASK; 1083 } 1084 1085 /** 1086 * i40e_clean_programming_status - clean the programming status descriptor 1087 * @rx_ring: the rx ring that has this descriptor 1088 * @rx_desc: the rx descriptor written back by HW 1089 * @qw: qword representing status_error_len in CPU ordering 1090 * 1091 * Flow director should handle FD_FILTER_STATUS to check its filter programming 1092 * status being successful or not and take actions accordingly. FCoE should 1093 * handle its context/filter programming/invalidation status and take actions. 1094 * 1095 **/ 1096 static void i40e_clean_programming_status(struct i40e_ring *rx_ring, 1097 union i40e_rx_desc *rx_desc, 1098 u64 qw) 1099 { 1100 struct i40e_rx_buffer *rx_buffer; 1101 u32 ntc = rx_ring->next_to_clean; 1102 u8 id; 1103 1104 /* fetch, update, and store next to clean */ 1105 rx_buffer = &rx_ring->rx_bi[ntc++]; 1106 ntc = (ntc < rx_ring->count) ? ntc : 0; 1107 rx_ring->next_to_clean = ntc; 1108 1109 prefetch(I40E_RX_DESC(rx_ring, ntc)); 1110 1111 /* place unused page back on the ring */ 1112 i40e_reuse_rx_page(rx_ring, rx_buffer); 1113 rx_ring->rx_stats.page_reuse_count++; 1114 1115 /* clear contents of buffer_info */ 1116 rx_buffer->page = NULL; 1117 1118 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> 1119 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; 1120 1121 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) 1122 i40e_fd_handle_status(rx_ring, rx_desc, id); 1123 } 1124 1125 /** 1126 * i40e_setup_tx_descriptors - Allocate the Tx descriptors 1127 * @tx_ring: the tx ring to set up 1128 * 1129 * Return 0 on success, negative on error 1130 **/ 1131 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) 1132 { 1133 struct device *dev = tx_ring->dev; 1134 int bi_size; 1135 1136 if (!dev) 1137 return -ENOMEM; 1138 1139 /* warn if we are about to overwrite the pointer */ 1140 WARN_ON(tx_ring->tx_bi); 1141 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 1142 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); 1143 if (!tx_ring->tx_bi) 1144 goto err; 1145 1146 u64_stats_init(&tx_ring->syncp); 1147 1148 /* round up to nearest 4K */ 1149 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); 1150 /* add u32 for head writeback, align after this takes care of 1151 * guaranteeing this is at least one cache line in size 1152 */ 1153 tx_ring->size += sizeof(u32); 1154 tx_ring->size = ALIGN(tx_ring->size, 4096); 1155 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 1156 &tx_ring->dma, GFP_KERNEL); 1157 if (!tx_ring->desc) { 1158 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 1159 tx_ring->size); 1160 goto err; 1161 } 1162 1163 tx_ring->next_to_use = 0; 1164 tx_ring->next_to_clean = 0; 1165 return 0; 1166 1167 err: 1168 kfree(tx_ring->tx_bi); 1169 tx_ring->tx_bi = NULL; 1170 return -ENOMEM; 1171 } 1172 1173 /** 1174 * i40e_clean_rx_ring - Free Rx buffers 1175 * @rx_ring: ring to be cleaned 1176 **/ 1177 void i40e_clean_rx_ring(struct i40e_ring *rx_ring) 1178 { 1179 unsigned long bi_size; 1180 u16 i; 1181 1182 /* ring already cleared, nothing to do */ 1183 if (!rx_ring->rx_bi) 1184 return; 1185 1186 if (rx_ring->skb) { 1187 dev_kfree_skb(rx_ring->skb); 1188 rx_ring->skb = NULL; 1189 } 1190 1191 /* Free all the Rx ring sk_buffs */ 1192 for (i = 0; i < rx_ring->count; i++) { 1193 struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; 1194 1195 if (!rx_bi->page) 1196 continue; 1197 1198 /* Invalidate cache lines that may have been written to by 1199 * device so that we avoid corrupting memory. 1200 */ 1201 dma_sync_single_range_for_cpu(rx_ring->dev, 1202 rx_bi->dma, 1203 rx_bi->page_offset, 1204 rx_ring->rx_buf_len, 1205 DMA_FROM_DEVICE); 1206 1207 /* free resources associated with mapping */ 1208 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, 1209 i40e_rx_pg_size(rx_ring), 1210 DMA_FROM_DEVICE, 1211 I40E_RX_DMA_ATTR); 1212 1213 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); 1214 1215 rx_bi->page = NULL; 1216 rx_bi->page_offset = 0; 1217 } 1218 1219 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1220 memset(rx_ring->rx_bi, 0, bi_size); 1221 1222 /* Zero out the descriptor ring */ 1223 memset(rx_ring->desc, 0, rx_ring->size); 1224 1225 rx_ring->next_to_alloc = 0; 1226 rx_ring->next_to_clean = 0; 1227 rx_ring->next_to_use = 0; 1228 } 1229 1230 /** 1231 * i40e_free_rx_resources - Free Rx resources 1232 * @rx_ring: ring to clean the resources from 1233 * 1234 * Free all receive software resources 1235 **/ 1236 void i40e_free_rx_resources(struct i40e_ring *rx_ring) 1237 { 1238 i40e_clean_rx_ring(rx_ring); 1239 rx_ring->xdp_prog = NULL; 1240 kfree(rx_ring->rx_bi); 1241 rx_ring->rx_bi = NULL; 1242 1243 if (rx_ring->desc) { 1244 dma_free_coherent(rx_ring->dev, rx_ring->size, 1245 rx_ring->desc, rx_ring->dma); 1246 rx_ring->desc = NULL; 1247 } 1248 } 1249 1250 /** 1251 * i40e_setup_rx_descriptors - Allocate Rx descriptors 1252 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1253 * 1254 * Returns 0 on success, negative on failure 1255 **/ 1256 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) 1257 { 1258 struct device *dev = rx_ring->dev; 1259 int bi_size; 1260 1261 /* warn if we are about to overwrite the pointer */ 1262 WARN_ON(rx_ring->rx_bi); 1263 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1264 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); 1265 if (!rx_ring->rx_bi) 1266 goto err; 1267 1268 u64_stats_init(&rx_ring->syncp); 1269 1270 /* Round up to nearest 4K */ 1271 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); 1272 rx_ring->size = ALIGN(rx_ring->size, 4096); 1273 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 1274 &rx_ring->dma, GFP_KERNEL); 1275 1276 if (!rx_ring->desc) { 1277 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 1278 rx_ring->size); 1279 goto err; 1280 } 1281 1282 rx_ring->next_to_alloc = 0; 1283 rx_ring->next_to_clean = 0; 1284 rx_ring->next_to_use = 0; 1285 1286 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog; 1287 1288 return 0; 1289 err: 1290 kfree(rx_ring->rx_bi); 1291 rx_ring->rx_bi = NULL; 1292 return -ENOMEM; 1293 } 1294 1295 /** 1296 * i40e_release_rx_desc - Store the new tail and head values 1297 * @rx_ring: ring to bump 1298 * @val: new head index 1299 **/ 1300 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) 1301 { 1302 rx_ring->next_to_use = val; 1303 1304 /* update next to alloc since we have filled the ring */ 1305 rx_ring->next_to_alloc = val; 1306 1307 /* Force memory writes to complete before letting h/w 1308 * know there are new descriptors to fetch. (Only 1309 * applicable for weak-ordered memory model archs, 1310 * such as IA-64). 1311 */ 1312 wmb(); 1313 writel(val, rx_ring->tail); 1314 } 1315 1316 /** 1317 * i40e_rx_offset - Return expected offset into page to access data 1318 * @rx_ring: Ring we are requesting offset of 1319 * 1320 * Returns the offset value for ring into the data buffer. 1321 */ 1322 static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring) 1323 { 1324 return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0; 1325 } 1326 1327 /** 1328 * i40e_alloc_mapped_page - recycle or make a new page 1329 * @rx_ring: ring to use 1330 * @bi: rx_buffer struct to modify 1331 * 1332 * Returns true if the page was successfully allocated or 1333 * reused. 1334 **/ 1335 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, 1336 struct i40e_rx_buffer *bi) 1337 { 1338 struct page *page = bi->page; 1339 dma_addr_t dma; 1340 1341 /* since we are recycling buffers we should seldom need to alloc */ 1342 if (likely(page)) { 1343 rx_ring->rx_stats.page_reuse_count++; 1344 return true; 1345 } 1346 1347 /* alloc new page for storage */ 1348 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring)); 1349 if (unlikely(!page)) { 1350 rx_ring->rx_stats.alloc_page_failed++; 1351 return false; 1352 } 1353 1354 /* map page for use */ 1355 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1356 i40e_rx_pg_size(rx_ring), 1357 DMA_FROM_DEVICE, 1358 I40E_RX_DMA_ATTR); 1359 1360 /* if mapping failed free memory back to system since 1361 * there isn't much point in holding memory we can't use 1362 */ 1363 if (dma_mapping_error(rx_ring->dev, dma)) { 1364 __free_pages(page, i40e_rx_pg_order(rx_ring)); 1365 rx_ring->rx_stats.alloc_page_failed++; 1366 return false; 1367 } 1368 1369 bi->dma = dma; 1370 bi->page = page; 1371 bi->page_offset = i40e_rx_offset(rx_ring); 1372 1373 /* initialize pagecnt_bias to 1 representing we fully own page */ 1374 bi->pagecnt_bias = 1; 1375 1376 return true; 1377 } 1378 1379 /** 1380 * i40e_receive_skb - Send a completed packet up the stack 1381 * @rx_ring: rx ring in play 1382 * @skb: packet to send up 1383 * @vlan_tag: vlan tag for packet 1384 **/ 1385 static void i40e_receive_skb(struct i40e_ring *rx_ring, 1386 struct sk_buff *skb, u16 vlan_tag) 1387 { 1388 struct i40e_q_vector *q_vector = rx_ring->q_vector; 1389 1390 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1391 (vlan_tag & VLAN_VID_MASK)) 1392 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 1393 1394 napi_gro_receive(&q_vector->napi, skb); 1395 } 1396 1397 /** 1398 * i40e_alloc_rx_buffers - Replace used receive buffers 1399 * @rx_ring: ring to place buffers on 1400 * @cleaned_count: number of buffers to replace 1401 * 1402 * Returns false if all allocations were successful, true if any fail 1403 **/ 1404 bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) 1405 { 1406 u16 ntu = rx_ring->next_to_use; 1407 union i40e_rx_desc *rx_desc; 1408 struct i40e_rx_buffer *bi; 1409 1410 /* Hardware only fetches new descriptors in cache lines of 8, 1411 * essentially ignoring the lower 3 bits of the tail register. We want 1412 * to ensure our tail writes are aligned to avoid unnecessary work. We 1413 * can't simply round down the cleaned count, since we might fail to 1414 * allocate some buffers. What we really want is to ensure that 1415 * next_to_used + cleaned_count produces an aligned value. 1416 */ 1417 cleaned_count -= (ntu + cleaned_count) & 0x7; 1418 1419 /* do nothing if no valid netdev defined */ 1420 if (!rx_ring->netdev || !cleaned_count) 1421 return false; 1422 1423 rx_desc = I40E_RX_DESC(rx_ring, ntu); 1424 bi = &rx_ring->rx_bi[ntu]; 1425 1426 do { 1427 if (!i40e_alloc_mapped_page(rx_ring, bi)) 1428 goto no_buffers; 1429 1430 /* sync the buffer for use by the device */ 1431 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1432 bi->page_offset, 1433 rx_ring->rx_buf_len, 1434 DMA_FROM_DEVICE); 1435 1436 /* Refresh the desc even if buffer_addrs didn't change 1437 * because each write-back erases this info. 1438 */ 1439 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1440 1441 rx_desc++; 1442 bi++; 1443 ntu++; 1444 if (unlikely(ntu == rx_ring->count)) { 1445 rx_desc = I40E_RX_DESC(rx_ring, 0); 1446 bi = rx_ring->rx_bi; 1447 ntu = 0; 1448 } 1449 1450 /* clear the status bits for the next_to_use descriptor */ 1451 rx_desc->wb.qword1.status_error_len = 0; 1452 1453 cleaned_count--; 1454 } while (cleaned_count); 1455 1456 if (rx_ring->next_to_use != ntu) 1457 i40e_release_rx_desc(rx_ring, ntu); 1458 1459 return false; 1460 1461 no_buffers: 1462 if (rx_ring->next_to_use != ntu) 1463 i40e_release_rx_desc(rx_ring, ntu); 1464 1465 /* make sure to come back via polling to try again after 1466 * allocation failure 1467 */ 1468 return true; 1469 } 1470 1471 /** 1472 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum 1473 * @vsi: the VSI we care about 1474 * @skb: skb currently being received and modified 1475 * @rx_desc: the receive descriptor 1476 **/ 1477 static inline void i40e_rx_checksum(struct i40e_vsi *vsi, 1478 struct sk_buff *skb, 1479 union i40e_rx_desc *rx_desc) 1480 { 1481 struct i40e_rx_ptype_decoded decoded; 1482 u32 rx_error, rx_status; 1483 bool ipv4, ipv6; 1484 u8 ptype; 1485 u64 qword; 1486 1487 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1488 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; 1489 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> 1490 I40E_RXD_QW1_ERROR_SHIFT; 1491 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1492 I40E_RXD_QW1_STATUS_SHIFT; 1493 decoded = decode_rx_desc_ptype(ptype); 1494 1495 skb->ip_summed = CHECKSUM_NONE; 1496 1497 skb_checksum_none_assert(skb); 1498 1499 /* Rx csum enabled and ip headers found? */ 1500 if (!(vsi->netdev->features & NETIF_F_RXCSUM)) 1501 return; 1502 1503 /* did the hardware decode the packet and checksum? */ 1504 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) 1505 return; 1506 1507 /* both known and outer_ip must be set for the below code to work */ 1508 if (!(decoded.known && decoded.outer_ip)) 1509 return; 1510 1511 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && 1512 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); 1513 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && 1514 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); 1515 1516 if (ipv4 && 1517 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | 1518 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) 1519 goto checksum_fail; 1520 1521 /* likely incorrect csum if alternate IP extension headers found */ 1522 if (ipv6 && 1523 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) 1524 /* don't increment checksum err here, non-fatal err */ 1525 return; 1526 1527 /* there was some L4 error, count error and punt packet to the stack */ 1528 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) 1529 goto checksum_fail; 1530 1531 /* handle packets that were not able to be checksummed due 1532 * to arrival speed, in this case the stack can compute 1533 * the csum. 1534 */ 1535 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) 1536 return; 1537 1538 /* If there is an outer header present that might contain a checksum 1539 * we need to bump the checksum level by 1 to reflect the fact that 1540 * we are indicating we validated the inner checksum. 1541 */ 1542 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT) 1543 skb->csum_level = 1; 1544 1545 /* Only report checksum unnecessary for TCP, UDP, or SCTP */ 1546 switch (decoded.inner_prot) { 1547 case I40E_RX_PTYPE_INNER_PROT_TCP: 1548 case I40E_RX_PTYPE_INNER_PROT_UDP: 1549 case I40E_RX_PTYPE_INNER_PROT_SCTP: 1550 skb->ip_summed = CHECKSUM_UNNECESSARY; 1551 /* fall though */ 1552 default: 1553 break; 1554 } 1555 1556 return; 1557 1558 checksum_fail: 1559 vsi->back->hw_csum_rx_error++; 1560 } 1561 1562 /** 1563 * i40e_ptype_to_htype - get a hash type 1564 * @ptype: the ptype value from the descriptor 1565 * 1566 * Returns a hash type to be used by skb_set_hash 1567 **/ 1568 static inline int i40e_ptype_to_htype(u8 ptype) 1569 { 1570 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); 1571 1572 if (!decoded.known) 1573 return PKT_HASH_TYPE_NONE; 1574 1575 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1576 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) 1577 return PKT_HASH_TYPE_L4; 1578 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1579 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) 1580 return PKT_HASH_TYPE_L3; 1581 else 1582 return PKT_HASH_TYPE_L2; 1583 } 1584 1585 /** 1586 * i40e_rx_hash - set the hash value in the skb 1587 * @ring: descriptor ring 1588 * @rx_desc: specific descriptor 1589 **/ 1590 static inline void i40e_rx_hash(struct i40e_ring *ring, 1591 union i40e_rx_desc *rx_desc, 1592 struct sk_buff *skb, 1593 u8 rx_ptype) 1594 { 1595 u32 hash; 1596 const __le64 rss_mask = 1597 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << 1598 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); 1599 1600 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1601 return; 1602 1603 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { 1604 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); 1605 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); 1606 } 1607 } 1608 1609 /** 1610 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor 1611 * @rx_ring: rx descriptor ring packet is being transacted on 1612 * @rx_desc: pointer to the EOP Rx descriptor 1613 * @skb: pointer to current skb being populated 1614 * @rx_ptype: the packet type decoded by hardware 1615 * 1616 * This function checks the ring, descriptor, and packet information in 1617 * order to populate the hash, checksum, VLAN, protocol, and 1618 * other fields within the skb. 1619 **/ 1620 static inline 1621 void i40e_process_skb_fields(struct i40e_ring *rx_ring, 1622 union i40e_rx_desc *rx_desc, struct sk_buff *skb, 1623 u8 rx_ptype) 1624 { 1625 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1626 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1627 I40E_RXD_QW1_STATUS_SHIFT; 1628 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK; 1629 u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> 1630 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT; 1631 1632 if (unlikely(tsynvalid)) 1633 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn); 1634 1635 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); 1636 1637 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); 1638 1639 skb_record_rx_queue(skb, rx_ring->queue_index); 1640 1641 /* modifies the skb - consumes the enet header */ 1642 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1643 } 1644 1645 /** 1646 * i40e_cleanup_headers - Correct empty headers 1647 * @rx_ring: rx descriptor ring packet is being transacted on 1648 * @skb: pointer to current skb being fixed 1649 * @rx_desc: pointer to the EOP Rx descriptor 1650 * 1651 * Also address the case where we are pulling data in on pages only 1652 * and as such no data is present in the skb header. 1653 * 1654 * In addition if skb is not at least 60 bytes we need to pad it so that 1655 * it is large enough to qualify as a valid Ethernet frame. 1656 * 1657 * Returns true if an error was encountered and skb was freed. 1658 **/ 1659 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb, 1660 union i40e_rx_desc *rx_desc) 1661 1662 { 1663 /* XDP packets use error pointer so abort at this point */ 1664 if (IS_ERR(skb)) 1665 return true; 1666 1667 /* ERR_MASK will only have valid bits if EOP set, and 1668 * what we are doing here is actually checking 1669 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in 1670 * the error field 1671 */ 1672 if (unlikely(i40e_test_staterr(rx_desc, 1673 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { 1674 dev_kfree_skb_any(skb); 1675 return true; 1676 } 1677 1678 /* if eth_skb_pad returns an error the skb was freed */ 1679 if (eth_skb_pad(skb)) 1680 return true; 1681 1682 return false; 1683 } 1684 1685 /** 1686 * i40e_page_is_reusable - check if any reuse is possible 1687 * @page: page struct to check 1688 * 1689 * A page is not reusable if it was allocated under low memory 1690 * conditions, or it's not in the same NUMA node as this CPU. 1691 */ 1692 static inline bool i40e_page_is_reusable(struct page *page) 1693 { 1694 return (page_to_nid(page) == numa_mem_id()) && 1695 !page_is_pfmemalloc(page); 1696 } 1697 1698 /** 1699 * i40e_can_reuse_rx_page - Determine if this page can be reused by 1700 * the adapter for another receive 1701 * 1702 * @rx_buffer: buffer containing the page 1703 * 1704 * If page is reusable, rx_buffer->page_offset is adjusted to point to 1705 * an unused region in the page. 1706 * 1707 * For small pages, @truesize will be a constant value, half the size 1708 * of the memory at page. We'll attempt to alternate between high and 1709 * low halves of the page, with one half ready for use by the hardware 1710 * and the other half being consumed by the stack. We use the page 1711 * ref count to determine whether the stack has finished consuming the 1712 * portion of this page that was passed up with a previous packet. If 1713 * the page ref count is >1, we'll assume the "other" half page is 1714 * still busy, and this page cannot be reused. 1715 * 1716 * For larger pages, @truesize will be the actual space used by the 1717 * received packet (adjusted upward to an even multiple of the cache 1718 * line size). This will advance through the page by the amount 1719 * actually consumed by the received packets while there is still 1720 * space for a buffer. Each region of larger pages will be used at 1721 * most once, after which the page will not be reused. 1722 * 1723 * In either case, if the page is reusable its refcount is increased. 1724 **/ 1725 static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer) 1726 { 1727 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1728 struct page *page = rx_buffer->page; 1729 1730 /* Is any reuse possible? */ 1731 if (unlikely(!i40e_page_is_reusable(page))) 1732 return false; 1733 1734 #if (PAGE_SIZE < 8192) 1735 /* if we are only owner of page we can reuse it */ 1736 if (unlikely((page_count(page) - pagecnt_bias) > 1)) 1737 return false; 1738 #else 1739 #define I40E_LAST_OFFSET \ 1740 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048) 1741 if (rx_buffer->page_offset > I40E_LAST_OFFSET) 1742 return false; 1743 #endif 1744 1745 /* If we have drained the page fragment pool we need to update 1746 * the pagecnt_bias and page count so that we fully restock the 1747 * number of references the driver holds. 1748 */ 1749 if (unlikely(!pagecnt_bias)) { 1750 page_ref_add(page, USHRT_MAX); 1751 rx_buffer->pagecnt_bias = USHRT_MAX; 1752 } 1753 1754 return true; 1755 } 1756 1757 /** 1758 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff 1759 * @rx_ring: rx descriptor ring to transact packets on 1760 * @rx_buffer: buffer containing page to add 1761 * @skb: sk_buff to place the data into 1762 * @size: packet length from rx_desc 1763 * 1764 * This function will add the data contained in rx_buffer->page to the skb. 1765 * It will just attach the page as a frag to the skb. 1766 * 1767 * The function will then update the page offset. 1768 **/ 1769 static void i40e_add_rx_frag(struct i40e_ring *rx_ring, 1770 struct i40e_rx_buffer *rx_buffer, 1771 struct sk_buff *skb, 1772 unsigned int size) 1773 { 1774 #if (PAGE_SIZE < 8192) 1775 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; 1776 #else 1777 unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring)); 1778 #endif 1779 1780 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 1781 rx_buffer->page_offset, size, truesize); 1782 1783 /* page is being used so we must update the page offset */ 1784 #if (PAGE_SIZE < 8192) 1785 rx_buffer->page_offset ^= truesize; 1786 #else 1787 rx_buffer->page_offset += truesize; 1788 #endif 1789 } 1790 1791 /** 1792 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use 1793 * @rx_ring: rx descriptor ring to transact packets on 1794 * @size: size of buffer to add to skb 1795 * 1796 * This function will pull an Rx buffer from the ring and synchronize it 1797 * for use by the CPU. 1798 */ 1799 static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring, 1800 const unsigned int size) 1801 { 1802 struct i40e_rx_buffer *rx_buffer; 1803 1804 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; 1805 prefetchw(rx_buffer->page); 1806 1807 /* we are reusing so sync this buffer for CPU use */ 1808 dma_sync_single_range_for_cpu(rx_ring->dev, 1809 rx_buffer->dma, 1810 rx_buffer->page_offset, 1811 size, 1812 DMA_FROM_DEVICE); 1813 1814 /* We have pulled a buffer for use, so decrement pagecnt_bias */ 1815 rx_buffer->pagecnt_bias--; 1816 1817 return rx_buffer; 1818 } 1819 1820 /** 1821 * i40e_construct_skb - Allocate skb and populate it 1822 * @rx_ring: rx descriptor ring to transact packets on 1823 * @rx_buffer: rx buffer to pull data from 1824 * @xdp: xdp_buff pointing to the data 1825 * 1826 * This function allocates an skb. It then populates it with the page 1827 * data from the current receive descriptor, taking care to set up the 1828 * skb correctly. 1829 */ 1830 static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring, 1831 struct i40e_rx_buffer *rx_buffer, 1832 struct xdp_buff *xdp) 1833 { 1834 unsigned int size = xdp->data_end - xdp->data; 1835 #if (PAGE_SIZE < 8192) 1836 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; 1837 #else 1838 unsigned int truesize = SKB_DATA_ALIGN(size); 1839 #endif 1840 unsigned int headlen; 1841 struct sk_buff *skb; 1842 1843 /* prefetch first cache line of first page */ 1844 prefetch(xdp->data); 1845 #if L1_CACHE_BYTES < 128 1846 prefetch(xdp->data + L1_CACHE_BYTES); 1847 #endif 1848 1849 /* allocate a skb to store the frags */ 1850 skb = __napi_alloc_skb(&rx_ring->q_vector->napi, 1851 I40E_RX_HDR_SIZE, 1852 GFP_ATOMIC | __GFP_NOWARN); 1853 if (unlikely(!skb)) 1854 return NULL; 1855 1856 /* Determine available headroom for copy */ 1857 headlen = size; 1858 if (headlen > I40E_RX_HDR_SIZE) 1859 headlen = eth_get_headlen(xdp->data, I40E_RX_HDR_SIZE); 1860 1861 /* align pull length to size of long to optimize memcpy performance */ 1862 memcpy(__skb_put(skb, headlen), xdp->data, 1863 ALIGN(headlen, sizeof(long))); 1864 1865 /* update all of the pointers */ 1866 size -= headlen; 1867 if (size) { 1868 skb_add_rx_frag(skb, 0, rx_buffer->page, 1869 rx_buffer->page_offset + headlen, 1870 size, truesize); 1871 1872 /* buffer is used by skb, update page_offset */ 1873 #if (PAGE_SIZE < 8192) 1874 rx_buffer->page_offset ^= truesize; 1875 #else 1876 rx_buffer->page_offset += truesize; 1877 #endif 1878 } else { 1879 /* buffer is unused, reset bias back to rx_buffer */ 1880 rx_buffer->pagecnt_bias++; 1881 } 1882 1883 return skb; 1884 } 1885 1886 /** 1887 * i40e_build_skb - Build skb around an existing buffer 1888 * @rx_ring: Rx descriptor ring to transact packets on 1889 * @rx_buffer: Rx buffer to pull data from 1890 * @xdp: xdp_buff pointing to the data 1891 * 1892 * This function builds an skb around an existing Rx buffer, taking care 1893 * to set up the skb correctly and avoid any memcpy overhead. 1894 */ 1895 static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring, 1896 struct i40e_rx_buffer *rx_buffer, 1897 struct xdp_buff *xdp) 1898 { 1899 unsigned int size = xdp->data_end - xdp->data; 1900 #if (PAGE_SIZE < 8192) 1901 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; 1902 #else 1903 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1904 SKB_DATA_ALIGN(I40E_SKB_PAD + size); 1905 #endif 1906 struct sk_buff *skb; 1907 1908 /* prefetch first cache line of first page */ 1909 prefetch(xdp->data); 1910 #if L1_CACHE_BYTES < 128 1911 prefetch(xdp->data + L1_CACHE_BYTES); 1912 #endif 1913 /* build an skb around the page buffer */ 1914 skb = build_skb(xdp->data_hard_start, truesize); 1915 if (unlikely(!skb)) 1916 return NULL; 1917 1918 /* update pointers within the skb to store the data */ 1919 skb_reserve(skb, I40E_SKB_PAD); 1920 __skb_put(skb, size); 1921 1922 /* buffer is used by skb, update page_offset */ 1923 #if (PAGE_SIZE < 8192) 1924 rx_buffer->page_offset ^= truesize; 1925 #else 1926 rx_buffer->page_offset += truesize; 1927 #endif 1928 1929 return skb; 1930 } 1931 1932 /** 1933 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free 1934 * @rx_ring: rx descriptor ring to transact packets on 1935 * @rx_buffer: rx buffer to pull data from 1936 * 1937 * This function will clean up the contents of the rx_buffer. It will 1938 * either recycle the bufer or unmap it and free the associated resources. 1939 */ 1940 static void i40e_put_rx_buffer(struct i40e_ring *rx_ring, 1941 struct i40e_rx_buffer *rx_buffer) 1942 { 1943 if (i40e_can_reuse_rx_page(rx_buffer)) { 1944 /* hand second half of page back to the ring */ 1945 i40e_reuse_rx_page(rx_ring, rx_buffer); 1946 rx_ring->rx_stats.page_reuse_count++; 1947 } else { 1948 /* we are not reusing the buffer so unmap it */ 1949 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 1950 i40e_rx_pg_size(rx_ring), 1951 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); 1952 __page_frag_cache_drain(rx_buffer->page, 1953 rx_buffer->pagecnt_bias); 1954 } 1955 1956 /* clear contents of buffer_info */ 1957 rx_buffer->page = NULL; 1958 } 1959 1960 /** 1961 * i40e_is_non_eop - process handling of non-EOP buffers 1962 * @rx_ring: Rx ring being processed 1963 * @rx_desc: Rx descriptor for current buffer 1964 * @skb: Current socket buffer containing buffer in progress 1965 * 1966 * This function updates next to clean. If the buffer is an EOP buffer 1967 * this function exits returning false, otherwise it will place the 1968 * sk_buff in the next buffer to be chained and return true indicating 1969 * that this is in fact a non-EOP buffer. 1970 **/ 1971 static bool i40e_is_non_eop(struct i40e_ring *rx_ring, 1972 union i40e_rx_desc *rx_desc, 1973 struct sk_buff *skb) 1974 { 1975 u32 ntc = rx_ring->next_to_clean + 1; 1976 1977 /* fetch, update, and store next to clean */ 1978 ntc = (ntc < rx_ring->count) ? ntc : 0; 1979 rx_ring->next_to_clean = ntc; 1980 1981 prefetch(I40E_RX_DESC(rx_ring, ntc)); 1982 1983 /* if we are the last buffer then there is nothing else to do */ 1984 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) 1985 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) 1986 return false; 1987 1988 rx_ring->rx_stats.non_eop_descs++; 1989 1990 return true; 1991 } 1992 1993 #define I40E_XDP_PASS 0 1994 #define I40E_XDP_CONSUMED 1 1995 #define I40E_XDP_TX 2 1996 1997 static int i40e_xmit_xdp_ring(struct xdp_buff *xdp, 1998 struct i40e_ring *xdp_ring); 1999 2000 /** 2001 * i40e_run_xdp - run an XDP program 2002 * @rx_ring: Rx ring being processed 2003 * @xdp: XDP buffer containing the frame 2004 **/ 2005 static struct sk_buff *i40e_run_xdp(struct i40e_ring *rx_ring, 2006 struct xdp_buff *xdp) 2007 { 2008 int result = I40E_XDP_PASS; 2009 struct i40e_ring *xdp_ring; 2010 struct bpf_prog *xdp_prog; 2011 u32 act; 2012 2013 rcu_read_lock(); 2014 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2015 2016 if (!xdp_prog) 2017 goto xdp_out; 2018 2019 act = bpf_prog_run_xdp(xdp_prog, xdp); 2020 switch (act) { 2021 case XDP_PASS: 2022 break; 2023 case XDP_TX: 2024 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index]; 2025 result = i40e_xmit_xdp_ring(xdp, xdp_ring); 2026 break; 2027 default: 2028 bpf_warn_invalid_xdp_action(act); 2029 case XDP_ABORTED: 2030 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2031 /* fallthrough -- handle aborts by dropping packet */ 2032 case XDP_DROP: 2033 result = I40E_XDP_CONSUMED; 2034 break; 2035 } 2036 xdp_out: 2037 rcu_read_unlock(); 2038 return ERR_PTR(-result); 2039 } 2040 2041 /** 2042 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region 2043 * @rx_ring: Rx ring 2044 * @rx_buffer: Rx buffer to adjust 2045 * @size: Size of adjustment 2046 **/ 2047 static void i40e_rx_buffer_flip(struct i40e_ring *rx_ring, 2048 struct i40e_rx_buffer *rx_buffer, 2049 unsigned int size) 2050 { 2051 #if (PAGE_SIZE < 8192) 2052 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; 2053 2054 rx_buffer->page_offset ^= truesize; 2055 #else 2056 unsigned int truesize = SKB_DATA_ALIGN(i40e_rx_offset(rx_ring) + size); 2057 2058 rx_buffer->page_offset += truesize; 2059 #endif 2060 } 2061 2062 /** 2063 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2064 * @rx_ring: rx descriptor ring to transact packets on 2065 * @budget: Total limit on number of packets to process 2066 * 2067 * This function provides a "bounce buffer" approach to Rx interrupt 2068 * processing. The advantage to this is that on systems that have 2069 * expensive overhead for IOMMU access this provides a means of avoiding 2070 * it by maintaining the mapping of the page to the system. 2071 * 2072 * Returns amount of work completed 2073 **/ 2074 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) 2075 { 2076 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2077 struct sk_buff *skb = rx_ring->skb; 2078 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); 2079 bool failure = false, xdp_xmit = false; 2080 2081 while (likely(total_rx_packets < (unsigned int)budget)) { 2082 struct i40e_rx_buffer *rx_buffer; 2083 union i40e_rx_desc *rx_desc; 2084 struct xdp_buff xdp; 2085 unsigned int size; 2086 u16 vlan_tag; 2087 u8 rx_ptype; 2088 u64 qword; 2089 2090 /* return some buffers to hardware, one at a time is too slow */ 2091 if (cleaned_count >= I40E_RX_BUFFER_WRITE) { 2092 failure = failure || 2093 i40e_alloc_rx_buffers(rx_ring, cleaned_count); 2094 cleaned_count = 0; 2095 } 2096 2097 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); 2098 2099 /* status_error_len will always be zero for unused descriptors 2100 * because it's cleared in cleanup, and overlaps with hdr_addr 2101 * which is always zero because packet split isn't used, if the 2102 * hardware wrote DD then the length will be non-zero 2103 */ 2104 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 2105 2106 /* This memory barrier is needed to keep us from reading 2107 * any other fields out of the rx_desc until we have 2108 * verified the descriptor has been written back. 2109 */ 2110 dma_rmb(); 2111 2112 if (unlikely(i40e_rx_is_programming_status(qword))) { 2113 i40e_clean_programming_status(rx_ring, rx_desc, qword); 2114 continue; 2115 } 2116 size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> 2117 I40E_RXD_QW1_LENGTH_PBUF_SHIFT; 2118 if (!size) 2119 break; 2120 2121 i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb); 2122 rx_buffer = i40e_get_rx_buffer(rx_ring, size); 2123 2124 /* retrieve a buffer from the ring */ 2125 if (!skb) { 2126 xdp.data = page_address(rx_buffer->page) + 2127 rx_buffer->page_offset; 2128 xdp_set_data_meta_invalid(&xdp); 2129 xdp.data_hard_start = xdp.data - 2130 i40e_rx_offset(rx_ring); 2131 xdp.data_end = xdp.data + size; 2132 2133 skb = i40e_run_xdp(rx_ring, &xdp); 2134 } 2135 2136 if (IS_ERR(skb)) { 2137 if (PTR_ERR(skb) == -I40E_XDP_TX) { 2138 xdp_xmit = true; 2139 i40e_rx_buffer_flip(rx_ring, rx_buffer, size); 2140 } else { 2141 rx_buffer->pagecnt_bias++; 2142 } 2143 total_rx_bytes += size; 2144 total_rx_packets++; 2145 } else if (skb) { 2146 i40e_add_rx_frag(rx_ring, rx_buffer, skb, size); 2147 } else if (ring_uses_build_skb(rx_ring)) { 2148 skb = i40e_build_skb(rx_ring, rx_buffer, &xdp); 2149 } else { 2150 skb = i40e_construct_skb(rx_ring, rx_buffer, &xdp); 2151 } 2152 2153 /* exit if we failed to retrieve a buffer */ 2154 if (!skb) { 2155 rx_ring->rx_stats.alloc_buff_failed++; 2156 rx_buffer->pagecnt_bias++; 2157 break; 2158 } 2159 2160 i40e_put_rx_buffer(rx_ring, rx_buffer); 2161 cleaned_count++; 2162 2163 if (i40e_is_non_eop(rx_ring, rx_desc, skb)) 2164 continue; 2165 2166 if (i40e_cleanup_headers(rx_ring, skb, rx_desc)) { 2167 skb = NULL; 2168 continue; 2169 } 2170 2171 /* probably a little skewed due to removing CRC */ 2172 total_rx_bytes += skb->len; 2173 2174 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 2175 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> 2176 I40E_RXD_QW1_PTYPE_SHIFT; 2177 2178 /* populate checksum, VLAN, and protocol */ 2179 i40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); 2180 2181 vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? 2182 le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; 2183 2184 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb); 2185 i40e_receive_skb(rx_ring, skb, vlan_tag); 2186 skb = NULL; 2187 2188 /* update budget accounting */ 2189 total_rx_packets++; 2190 } 2191 2192 if (xdp_xmit) { 2193 struct i40e_ring *xdp_ring; 2194 2195 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index]; 2196 2197 /* Force memory writes to complete before letting h/w 2198 * know there are new descriptors to fetch. 2199 */ 2200 wmb(); 2201 2202 writel(xdp_ring->next_to_use, xdp_ring->tail); 2203 } 2204 2205 rx_ring->skb = skb; 2206 2207 u64_stats_update_begin(&rx_ring->syncp); 2208 rx_ring->stats.packets += total_rx_packets; 2209 rx_ring->stats.bytes += total_rx_bytes; 2210 u64_stats_update_end(&rx_ring->syncp); 2211 rx_ring->q_vector->rx.total_packets += total_rx_packets; 2212 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 2213 2214 /* guarantee a trip back through this routine if there was a failure */ 2215 return failure ? budget : (int)total_rx_packets; 2216 } 2217 2218 static u32 i40e_buildreg_itr(const int type, const u16 itr) 2219 { 2220 u32 val; 2221 2222 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 2223 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 2224 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | 2225 (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); 2226 2227 return val; 2228 } 2229 2230 /* a small macro to shorten up some long lines */ 2231 #define INTREG I40E_PFINT_DYN_CTLN 2232 static inline int get_rx_itr(struct i40e_vsi *vsi, int idx) 2233 { 2234 return vsi->rx_rings[idx]->rx_itr_setting; 2235 } 2236 2237 static inline int get_tx_itr(struct i40e_vsi *vsi, int idx) 2238 { 2239 return vsi->tx_rings[idx]->tx_itr_setting; 2240 } 2241 2242 /** 2243 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt 2244 * @vsi: the VSI we care about 2245 * @q_vector: q_vector for which itr is being updated and interrupt enabled 2246 * 2247 **/ 2248 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, 2249 struct i40e_q_vector *q_vector) 2250 { 2251 struct i40e_hw *hw = &vsi->back->hw; 2252 bool rx = false, tx = false; 2253 u32 rxval, txval; 2254 int vector; 2255 int idx = q_vector->v_idx; 2256 int rx_itr_setting, tx_itr_setting; 2257 2258 /* If we don't have MSIX, then we only need to re-enable icr0 */ 2259 if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) { 2260 i40e_irq_dynamic_enable_icr0(vsi->back); 2261 return; 2262 } 2263 2264 vector = (q_vector->v_idx + vsi->base_vector); 2265 2266 /* avoid dynamic calculation if in countdown mode OR if 2267 * all dynamic is disabled 2268 */ 2269 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); 2270 2271 rx_itr_setting = get_rx_itr(vsi, idx); 2272 tx_itr_setting = get_tx_itr(vsi, idx); 2273 2274 if (q_vector->itr_countdown > 0 || 2275 (!ITR_IS_DYNAMIC(rx_itr_setting) && 2276 !ITR_IS_DYNAMIC(tx_itr_setting))) { 2277 goto enable_int; 2278 } 2279 2280 if (ITR_IS_DYNAMIC(tx_itr_setting)) { 2281 rx = i40e_set_new_dynamic_itr(&q_vector->rx); 2282 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); 2283 } 2284 2285 if (ITR_IS_DYNAMIC(tx_itr_setting)) { 2286 tx = i40e_set_new_dynamic_itr(&q_vector->tx); 2287 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); 2288 } 2289 2290 if (rx || tx) { 2291 /* get the higher of the two ITR adjustments and 2292 * use the same value for both ITR registers 2293 * when in adaptive mode (Rx and/or Tx) 2294 */ 2295 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); 2296 2297 q_vector->tx.itr = q_vector->rx.itr = itr; 2298 txval = i40e_buildreg_itr(I40E_TX_ITR, itr); 2299 tx = true; 2300 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); 2301 rx = true; 2302 } 2303 2304 /* only need to enable the interrupt once, but need 2305 * to possibly update both ITR values 2306 */ 2307 if (rx) { 2308 /* set the INTENA_MSK_MASK so that this first write 2309 * won't actually enable the interrupt, instead just 2310 * updating the ITR (it's bit 31 PF and VF) 2311 */ 2312 rxval |= BIT(31); 2313 /* don't check _DOWN because interrupt isn't being enabled */ 2314 wr32(hw, INTREG(vector - 1), rxval); 2315 } 2316 2317 enable_int: 2318 if (!test_bit(__I40E_VSI_DOWN, vsi->state)) 2319 wr32(hw, INTREG(vector - 1), txval); 2320 2321 if (q_vector->itr_countdown) 2322 q_vector->itr_countdown--; 2323 else 2324 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2325 } 2326 2327 /** 2328 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine 2329 * @napi: napi struct with our devices info in it 2330 * @budget: amount of work driver is allowed to do this pass, in packets 2331 * 2332 * This function will clean all queues associated with a q_vector. 2333 * 2334 * Returns the amount of work done 2335 **/ 2336 int i40e_napi_poll(struct napi_struct *napi, int budget) 2337 { 2338 struct i40e_q_vector *q_vector = 2339 container_of(napi, struct i40e_q_vector, napi); 2340 struct i40e_vsi *vsi = q_vector->vsi; 2341 struct i40e_ring *ring; 2342 bool clean_complete = true; 2343 bool arm_wb = false; 2344 int budget_per_ring; 2345 int work_done = 0; 2346 2347 if (test_bit(__I40E_VSI_DOWN, vsi->state)) { 2348 napi_complete(napi); 2349 return 0; 2350 } 2351 2352 /* Since the actual Tx work is minimal, we can give the Tx a larger 2353 * budget and be more aggressive about cleaning up the Tx descriptors. 2354 */ 2355 i40e_for_each_ring(ring, q_vector->tx) { 2356 if (!i40e_clean_tx_irq(vsi, ring, budget)) { 2357 clean_complete = false; 2358 continue; 2359 } 2360 arm_wb |= ring->arm_wb; 2361 ring->arm_wb = false; 2362 } 2363 2364 /* Handle case where we are called by netpoll with a budget of 0 */ 2365 if (budget <= 0) 2366 goto tx_only; 2367 2368 /* We attempt to distribute budget to each Rx queue fairly, but don't 2369 * allow the budget to go below 1 because that would exit polling early. 2370 */ 2371 budget_per_ring = max(budget/q_vector->num_ringpairs, 1); 2372 2373 i40e_for_each_ring(ring, q_vector->rx) { 2374 int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); 2375 2376 work_done += cleaned; 2377 /* if we clean as many as budgeted, we must not be done */ 2378 if (cleaned >= budget_per_ring) 2379 clean_complete = false; 2380 } 2381 2382 /* If work not completed, return budget and polling will return */ 2383 if (!clean_complete) { 2384 int cpu_id = smp_processor_id(); 2385 2386 /* It is possible that the interrupt affinity has changed but, 2387 * if the cpu is pegged at 100%, polling will never exit while 2388 * traffic continues and the interrupt will be stuck on this 2389 * cpu. We check to make sure affinity is correct before we 2390 * continue to poll, otherwise we must stop polling so the 2391 * interrupt can move to the correct cpu. 2392 */ 2393 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) { 2394 /* Tell napi that we are done polling */ 2395 napi_complete_done(napi, work_done); 2396 2397 /* Force an interrupt */ 2398 i40e_force_wb(vsi, q_vector); 2399 2400 /* Return budget-1 so that polling stops */ 2401 return budget - 1; 2402 } 2403 tx_only: 2404 if (arm_wb) { 2405 q_vector->tx.ring[0].tx_stats.tx_force_wb++; 2406 i40e_enable_wb_on_itr(vsi, q_vector); 2407 } 2408 return budget; 2409 } 2410 2411 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) 2412 q_vector->arm_wb_state = false; 2413 2414 /* Work is done so exit the polling mode and re-enable the interrupt */ 2415 napi_complete_done(napi, work_done); 2416 2417 i40e_update_enable_itr(vsi, q_vector); 2418 2419 return min(work_done, budget - 1); 2420 } 2421 2422 /** 2423 * i40e_atr - Add a Flow Director ATR filter 2424 * @tx_ring: ring to add programming descriptor to 2425 * @skb: send buffer 2426 * @tx_flags: send tx flags 2427 **/ 2428 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, 2429 u32 tx_flags) 2430 { 2431 struct i40e_filter_program_desc *fdir_desc; 2432 struct i40e_pf *pf = tx_ring->vsi->back; 2433 union { 2434 unsigned char *network; 2435 struct iphdr *ipv4; 2436 struct ipv6hdr *ipv6; 2437 } hdr; 2438 struct tcphdr *th; 2439 unsigned int hlen; 2440 u32 flex_ptype, dtype_cmd; 2441 int l4_proto; 2442 u16 i; 2443 2444 /* make sure ATR is enabled */ 2445 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) 2446 return; 2447 2448 if (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED) 2449 return; 2450 2451 /* if sampling is disabled do nothing */ 2452 if (!tx_ring->atr_sample_rate) 2453 return; 2454 2455 /* Currently only IPv4/IPv6 with TCP is supported */ 2456 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) 2457 return; 2458 2459 /* snag network header to get L4 type and address */ 2460 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? 2461 skb_inner_network_header(skb) : skb_network_header(skb); 2462 2463 /* Note: tx_flags gets modified to reflect inner protocols in 2464 * tx_enable_csum function if encap is enabled. 2465 */ 2466 if (tx_flags & I40E_TX_FLAGS_IPV4) { 2467 /* access ihl as u8 to avoid unaligned access on ia64 */ 2468 hlen = (hdr.network[0] & 0x0F) << 2; 2469 l4_proto = hdr.ipv4->protocol; 2470 } else { 2471 /* find the start of the innermost ipv6 header */ 2472 unsigned int inner_hlen = hdr.network - skb->data; 2473 unsigned int h_offset = inner_hlen; 2474 2475 /* this function updates h_offset to the end of the header */ 2476 l4_proto = 2477 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL); 2478 /* hlen will contain our best estimate of the tcp header */ 2479 hlen = h_offset - inner_hlen; 2480 } 2481 2482 if (l4_proto != IPPROTO_TCP) 2483 return; 2484 2485 th = (struct tcphdr *)(hdr.network + hlen); 2486 2487 /* Due to lack of space, no more new filters can be programmed */ 2488 if (th->syn && (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED)) 2489 return; 2490 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) { 2491 /* HW ATR eviction will take care of removing filters on FIN 2492 * and RST packets. 2493 */ 2494 if (th->fin || th->rst) 2495 return; 2496 } 2497 2498 tx_ring->atr_count++; 2499 2500 /* sample on all syn/fin/rst packets or once every atr sample rate */ 2501 if (!th->fin && 2502 !th->syn && 2503 !th->rst && 2504 (tx_ring->atr_count < tx_ring->atr_sample_rate)) 2505 return; 2506 2507 tx_ring->atr_count = 0; 2508 2509 /* grab the next descriptor */ 2510 i = tx_ring->next_to_use; 2511 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 2512 2513 i++; 2514 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2515 2516 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 2517 I40E_TXD_FLTR_QW0_QINDEX_MASK; 2518 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? 2519 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 2520 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 2521 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 2522 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 2523 2524 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 2525 2526 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 2527 2528 dtype_cmd |= (th->fin || th->rst) ? 2529 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 2530 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 2531 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 2532 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 2533 2534 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 2535 I40E_TXD_FLTR_QW1_DEST_SHIFT; 2536 2537 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 2538 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 2539 2540 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 2541 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) 2542 dtype_cmd |= 2543 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << 2544 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2545 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2546 else 2547 dtype_cmd |= 2548 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << 2549 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2550 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2551 2552 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) 2553 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; 2554 2555 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 2556 fdir_desc->rsvd = cpu_to_le32(0); 2557 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 2558 fdir_desc->fd_id = cpu_to_le32(0); 2559 } 2560 2561 /** 2562 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW 2563 * @skb: send buffer 2564 * @tx_ring: ring to send buffer on 2565 * @flags: the tx flags to be set 2566 * 2567 * Checks the skb and set up correspondingly several generic transmit flags 2568 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 2569 * 2570 * Returns error code indicate the frame should be dropped upon error and the 2571 * otherwise returns 0 to indicate the flags has been set properly. 2572 **/ 2573 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 2574 struct i40e_ring *tx_ring, 2575 u32 *flags) 2576 { 2577 __be16 protocol = skb->protocol; 2578 u32 tx_flags = 0; 2579 2580 if (protocol == htons(ETH_P_8021Q) && 2581 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 2582 /* When HW VLAN acceleration is turned off by the user the 2583 * stack sets the protocol to 8021q so that the driver 2584 * can take any steps required to support the SW only 2585 * VLAN handling. In our case the driver doesn't need 2586 * to take any further steps so just set the protocol 2587 * to the encapsulated ethertype. 2588 */ 2589 skb->protocol = vlan_get_protocol(skb); 2590 goto out; 2591 } 2592 2593 /* if we have a HW VLAN tag being added, default to the HW one */ 2594 if (skb_vlan_tag_present(skb)) { 2595 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; 2596 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 2597 /* else if it is a SW VLAN, check the next protocol and store the tag */ 2598 } else if (protocol == htons(ETH_P_8021Q)) { 2599 struct vlan_hdr *vhdr, _vhdr; 2600 2601 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 2602 if (!vhdr) 2603 return -EINVAL; 2604 2605 protocol = vhdr->h_vlan_encapsulated_proto; 2606 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; 2607 tx_flags |= I40E_TX_FLAGS_SW_VLAN; 2608 } 2609 2610 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) 2611 goto out; 2612 2613 /* Insert 802.1p priority into VLAN header */ 2614 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || 2615 (skb->priority != TC_PRIO_CONTROL)) { 2616 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; 2617 tx_flags |= (skb->priority & 0x7) << 2618 I40E_TX_FLAGS_VLAN_PRIO_SHIFT; 2619 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { 2620 struct vlan_ethhdr *vhdr; 2621 int rc; 2622 2623 rc = skb_cow_head(skb, 0); 2624 if (rc < 0) 2625 return rc; 2626 vhdr = (struct vlan_ethhdr *)skb->data; 2627 vhdr->h_vlan_TCI = htons(tx_flags >> 2628 I40E_TX_FLAGS_VLAN_SHIFT); 2629 } else { 2630 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 2631 } 2632 } 2633 2634 out: 2635 *flags = tx_flags; 2636 return 0; 2637 } 2638 2639 /** 2640 * i40e_tso - set up the tso context descriptor 2641 * @first: pointer to first Tx buffer for xmit 2642 * @hdr_len: ptr to the size of the packet header 2643 * @cd_type_cmd_tso_mss: Quad Word 1 2644 * 2645 * Returns 0 if no TSO can happen, 1 if tso is going, or error 2646 **/ 2647 static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, 2648 u64 *cd_type_cmd_tso_mss) 2649 { 2650 struct sk_buff *skb = first->skb; 2651 u64 cd_cmd, cd_tso_len, cd_mss; 2652 union { 2653 struct iphdr *v4; 2654 struct ipv6hdr *v6; 2655 unsigned char *hdr; 2656 } ip; 2657 union { 2658 struct tcphdr *tcp; 2659 struct udphdr *udp; 2660 unsigned char *hdr; 2661 } l4; 2662 u32 paylen, l4_offset; 2663 u16 gso_segs, gso_size; 2664 int err; 2665 2666 if (skb->ip_summed != CHECKSUM_PARTIAL) 2667 return 0; 2668 2669 if (!skb_is_gso(skb)) 2670 return 0; 2671 2672 err = skb_cow_head(skb, 0); 2673 if (err < 0) 2674 return err; 2675 2676 ip.hdr = skb_network_header(skb); 2677 l4.hdr = skb_transport_header(skb); 2678 2679 /* initialize outer IP header fields */ 2680 if (ip.v4->version == 4) { 2681 ip.v4->tot_len = 0; 2682 ip.v4->check = 0; 2683 } else { 2684 ip.v6->payload_len = 0; 2685 } 2686 2687 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 2688 SKB_GSO_GRE_CSUM | 2689 SKB_GSO_IPXIP4 | 2690 SKB_GSO_IPXIP6 | 2691 SKB_GSO_UDP_TUNNEL | 2692 SKB_GSO_UDP_TUNNEL_CSUM)) { 2693 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 2694 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { 2695 l4.udp->len = 0; 2696 2697 /* determine offset of outer transport header */ 2698 l4_offset = l4.hdr - skb->data; 2699 2700 /* remove payload length from outer checksum */ 2701 paylen = skb->len - l4_offset; 2702 csum_replace_by_diff(&l4.udp->check, 2703 (__force __wsum)htonl(paylen)); 2704 } 2705 2706 /* reset pointers to inner headers */ 2707 ip.hdr = skb_inner_network_header(skb); 2708 l4.hdr = skb_inner_transport_header(skb); 2709 2710 /* initialize inner IP header fields */ 2711 if (ip.v4->version == 4) { 2712 ip.v4->tot_len = 0; 2713 ip.v4->check = 0; 2714 } else { 2715 ip.v6->payload_len = 0; 2716 } 2717 } 2718 2719 /* determine offset of inner transport header */ 2720 l4_offset = l4.hdr - skb->data; 2721 2722 /* remove payload length from inner checksum */ 2723 paylen = skb->len - l4_offset; 2724 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); 2725 2726 /* compute length of segmentation header */ 2727 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 2728 2729 /* pull values out of skb_shinfo */ 2730 gso_size = skb_shinfo(skb)->gso_size; 2731 gso_segs = skb_shinfo(skb)->gso_segs; 2732 2733 /* update GSO size and bytecount with header size */ 2734 first->gso_segs = gso_segs; 2735 first->bytecount += (first->gso_segs - 1) * *hdr_len; 2736 2737 /* find the field values */ 2738 cd_cmd = I40E_TX_CTX_DESC_TSO; 2739 cd_tso_len = skb->len - *hdr_len; 2740 cd_mss = gso_size; 2741 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | 2742 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | 2743 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); 2744 return 1; 2745 } 2746 2747 /** 2748 * i40e_tsyn - set up the tsyn context descriptor 2749 * @tx_ring: ptr to the ring to send 2750 * @skb: ptr to the skb we're sending 2751 * @tx_flags: the collected send information 2752 * @cd_type_cmd_tso_mss: Quad Word 1 2753 * 2754 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen 2755 **/ 2756 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, 2757 u32 tx_flags, u64 *cd_type_cmd_tso_mss) 2758 { 2759 struct i40e_pf *pf; 2760 2761 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 2762 return 0; 2763 2764 /* Tx timestamps cannot be sampled when doing TSO */ 2765 if (tx_flags & I40E_TX_FLAGS_TSO) 2766 return 0; 2767 2768 /* only timestamp the outbound packet if the user has requested it and 2769 * we are not already transmitting a packet to be timestamped 2770 */ 2771 pf = i40e_netdev_to_pf(tx_ring->netdev); 2772 if (!(pf->flags & I40E_FLAG_PTP)) 2773 return 0; 2774 2775 if (pf->ptp_tx && 2776 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) { 2777 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2778 pf->ptp_tx_start = jiffies; 2779 pf->ptp_tx_skb = skb_get(skb); 2780 } else { 2781 pf->tx_hwtstamp_skipped++; 2782 return 0; 2783 } 2784 2785 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << 2786 I40E_TXD_CTX_QW1_CMD_SHIFT; 2787 2788 return 1; 2789 } 2790 2791 /** 2792 * i40e_tx_enable_csum - Enable Tx checksum offloads 2793 * @skb: send buffer 2794 * @tx_flags: pointer to Tx flags currently set 2795 * @td_cmd: Tx descriptor command bits to set 2796 * @td_offset: Tx descriptor header offsets to set 2797 * @tx_ring: Tx descriptor ring 2798 * @cd_tunneling: ptr to context desc bits 2799 **/ 2800 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, 2801 u32 *td_cmd, u32 *td_offset, 2802 struct i40e_ring *tx_ring, 2803 u32 *cd_tunneling) 2804 { 2805 union { 2806 struct iphdr *v4; 2807 struct ipv6hdr *v6; 2808 unsigned char *hdr; 2809 } ip; 2810 union { 2811 struct tcphdr *tcp; 2812 struct udphdr *udp; 2813 unsigned char *hdr; 2814 } l4; 2815 unsigned char *exthdr; 2816 u32 offset, cmd = 0; 2817 __be16 frag_off; 2818 u8 l4_proto = 0; 2819 2820 if (skb->ip_summed != CHECKSUM_PARTIAL) 2821 return 0; 2822 2823 ip.hdr = skb_network_header(skb); 2824 l4.hdr = skb_transport_header(skb); 2825 2826 /* compute outer L2 header size */ 2827 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; 2828 2829 if (skb->encapsulation) { 2830 u32 tunnel = 0; 2831 /* define outer network header type */ 2832 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 2833 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 2834 I40E_TX_CTX_EXT_IP_IPV4 : 2835 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; 2836 2837 l4_proto = ip.v4->protocol; 2838 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 2839 tunnel |= I40E_TX_CTX_EXT_IP_IPV6; 2840 2841 exthdr = ip.hdr + sizeof(*ip.v6); 2842 l4_proto = ip.v6->nexthdr; 2843 if (l4.hdr != exthdr) 2844 ipv6_skip_exthdr(skb, exthdr - skb->data, 2845 &l4_proto, &frag_off); 2846 } 2847 2848 /* define outer transport */ 2849 switch (l4_proto) { 2850 case IPPROTO_UDP: 2851 tunnel |= I40E_TXD_CTX_UDP_TUNNELING; 2852 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2853 break; 2854 case IPPROTO_GRE: 2855 tunnel |= I40E_TXD_CTX_GRE_TUNNELING; 2856 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2857 break; 2858 case IPPROTO_IPIP: 2859 case IPPROTO_IPV6: 2860 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2861 l4.hdr = skb_inner_network_header(skb); 2862 break; 2863 default: 2864 if (*tx_flags & I40E_TX_FLAGS_TSO) 2865 return -1; 2866 2867 skb_checksum_help(skb); 2868 return 0; 2869 } 2870 2871 /* compute outer L3 header size */ 2872 tunnel |= ((l4.hdr - ip.hdr) / 4) << 2873 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; 2874 2875 /* switch IP header pointer from outer to inner header */ 2876 ip.hdr = skb_inner_network_header(skb); 2877 2878 /* compute tunnel header size */ 2879 tunnel |= ((ip.hdr - l4.hdr) / 2) << 2880 I40E_TXD_CTX_QW0_NATLEN_SHIFT; 2881 2882 /* indicate if we need to offload outer UDP header */ 2883 if ((*tx_flags & I40E_TX_FLAGS_TSO) && 2884 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 2885 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) 2886 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; 2887 2888 /* record tunnel offload values */ 2889 *cd_tunneling |= tunnel; 2890 2891 /* switch L4 header pointer from outer to inner */ 2892 l4.hdr = skb_inner_transport_header(skb); 2893 l4_proto = 0; 2894 2895 /* reset type as we transition from outer to inner headers */ 2896 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); 2897 if (ip.v4->version == 4) 2898 *tx_flags |= I40E_TX_FLAGS_IPV4; 2899 if (ip.v6->version == 6) 2900 *tx_flags |= I40E_TX_FLAGS_IPV6; 2901 } 2902 2903 /* Enable IP checksum offloads */ 2904 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 2905 l4_proto = ip.v4->protocol; 2906 /* the stack computes the IP header already, the only time we 2907 * need the hardware to recompute it is in the case of TSO. 2908 */ 2909 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 2910 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : 2911 I40E_TX_DESC_CMD_IIPT_IPV4; 2912 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 2913 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; 2914 2915 exthdr = ip.hdr + sizeof(*ip.v6); 2916 l4_proto = ip.v6->nexthdr; 2917 if (l4.hdr != exthdr) 2918 ipv6_skip_exthdr(skb, exthdr - skb->data, 2919 &l4_proto, &frag_off); 2920 } 2921 2922 /* compute inner L3 header size */ 2923 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 2924 2925 /* Enable L4 checksum offloads */ 2926 switch (l4_proto) { 2927 case IPPROTO_TCP: 2928 /* enable checksum offloads */ 2929 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; 2930 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2931 break; 2932 case IPPROTO_SCTP: 2933 /* enable SCTP checksum offload */ 2934 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; 2935 offset |= (sizeof(struct sctphdr) >> 2) << 2936 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2937 break; 2938 case IPPROTO_UDP: 2939 /* enable UDP checksum offload */ 2940 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; 2941 offset |= (sizeof(struct udphdr) >> 2) << 2942 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2943 break; 2944 default: 2945 if (*tx_flags & I40E_TX_FLAGS_TSO) 2946 return -1; 2947 skb_checksum_help(skb); 2948 return 0; 2949 } 2950 2951 *td_cmd |= cmd; 2952 *td_offset |= offset; 2953 2954 return 1; 2955 } 2956 2957 /** 2958 * i40e_create_tx_ctx Build the Tx context descriptor 2959 * @tx_ring: ring to create the descriptor on 2960 * @cd_type_cmd_tso_mss: Quad Word 1 2961 * @cd_tunneling: Quad Word 0 - bits 0-31 2962 * @cd_l2tag2: Quad Word 0 - bits 32-63 2963 **/ 2964 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, 2965 const u64 cd_type_cmd_tso_mss, 2966 const u32 cd_tunneling, const u32 cd_l2tag2) 2967 { 2968 struct i40e_tx_context_desc *context_desc; 2969 int i = tx_ring->next_to_use; 2970 2971 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && 2972 !cd_tunneling && !cd_l2tag2) 2973 return; 2974 2975 /* grab the next descriptor */ 2976 context_desc = I40E_TX_CTXTDESC(tx_ring, i); 2977 2978 i++; 2979 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2980 2981 /* cpu_to_le32 and assign to struct fields */ 2982 context_desc->tunneling_params = cpu_to_le32(cd_tunneling); 2983 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); 2984 context_desc->rsvd = cpu_to_le16(0); 2985 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); 2986 } 2987 2988 /** 2989 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions 2990 * @tx_ring: the ring to be checked 2991 * @size: the size buffer we want to assure is available 2992 * 2993 * Returns -EBUSY if a stop is needed, else 0 2994 **/ 2995 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 2996 { 2997 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 2998 /* Memory barrier before checking head and tail */ 2999 smp_mb(); 3000 3001 /* Check again in a case another CPU has just made room available. */ 3002 if (likely(I40E_DESC_UNUSED(tx_ring) < size)) 3003 return -EBUSY; 3004 3005 /* A reprieve! - use start_queue because it doesn't call schedule */ 3006 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 3007 ++tx_ring->tx_stats.restart_queue; 3008 return 0; 3009 } 3010 3011 /** 3012 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet 3013 * @skb: send buffer 3014 * 3015 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire 3016 * and so we need to figure out the cases where we need to linearize the skb. 3017 * 3018 * For TSO we need to count the TSO header and segment payload separately. 3019 * As such we need to check cases where we have 7 fragments or more as we 3020 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for 3021 * the segment payload in the first descriptor, and another 7 for the 3022 * fragments. 3023 **/ 3024 bool __i40e_chk_linearize(struct sk_buff *skb) 3025 { 3026 const struct skb_frag_struct *frag, *stale; 3027 int nr_frags, sum; 3028 3029 /* no need to check if number of frags is less than 7 */ 3030 nr_frags = skb_shinfo(skb)->nr_frags; 3031 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) 3032 return false; 3033 3034 /* We need to walk through the list and validate that each group 3035 * of 6 fragments totals at least gso_size. 3036 */ 3037 nr_frags -= I40E_MAX_BUFFER_TXD - 2; 3038 frag = &skb_shinfo(skb)->frags[0]; 3039 3040 /* Initialize size to the negative value of gso_size minus 1. We 3041 * use this as the worst case scenerio in which the frag ahead 3042 * of us only provides one byte which is why we are limited to 6 3043 * descriptors for a single transmit as the header and previous 3044 * fragment are already consuming 2 descriptors. 3045 */ 3046 sum = 1 - skb_shinfo(skb)->gso_size; 3047 3048 /* Add size of frags 0 through 4 to create our initial sum */ 3049 sum += skb_frag_size(frag++); 3050 sum += skb_frag_size(frag++); 3051 sum += skb_frag_size(frag++); 3052 sum += skb_frag_size(frag++); 3053 sum += skb_frag_size(frag++); 3054 3055 /* Walk through fragments adding latest fragment, testing it, and 3056 * then removing stale fragments from the sum. 3057 */ 3058 stale = &skb_shinfo(skb)->frags[0]; 3059 for (;;) { 3060 sum += skb_frag_size(frag++); 3061 3062 /* if sum is negative we failed to make sufficient progress */ 3063 if (sum < 0) 3064 return true; 3065 3066 if (!nr_frags--) 3067 break; 3068 3069 sum -= skb_frag_size(stale++); 3070 } 3071 3072 return false; 3073 } 3074 3075 /** 3076 * i40e_tx_map - Build the Tx descriptor 3077 * @tx_ring: ring to send buffer on 3078 * @skb: send buffer 3079 * @first: first buffer info buffer to use 3080 * @tx_flags: collected send information 3081 * @hdr_len: size of the packet header 3082 * @td_cmd: the command field in the descriptor 3083 * @td_offset: offset for checksum or crc 3084 * 3085 * Returns 0 on success, -1 on failure to DMA 3086 **/ 3087 static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 3088 struct i40e_tx_buffer *first, u32 tx_flags, 3089 const u8 hdr_len, u32 td_cmd, u32 td_offset) 3090 { 3091 unsigned int data_len = skb->data_len; 3092 unsigned int size = skb_headlen(skb); 3093 struct skb_frag_struct *frag; 3094 struct i40e_tx_buffer *tx_bi; 3095 struct i40e_tx_desc *tx_desc; 3096 u16 i = tx_ring->next_to_use; 3097 u32 td_tag = 0; 3098 dma_addr_t dma; 3099 u16 desc_count = 1; 3100 3101 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { 3102 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; 3103 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> 3104 I40E_TX_FLAGS_VLAN_SHIFT; 3105 } 3106 3107 first->tx_flags = tx_flags; 3108 3109 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 3110 3111 tx_desc = I40E_TX_DESC(tx_ring, i); 3112 tx_bi = first; 3113 3114 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 3115 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 3116 3117 if (dma_mapping_error(tx_ring->dev, dma)) 3118 goto dma_error; 3119 3120 /* record length, and DMA address */ 3121 dma_unmap_len_set(tx_bi, len, size); 3122 dma_unmap_addr_set(tx_bi, dma, dma); 3123 3124 /* align size to end of page */ 3125 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); 3126 tx_desc->buffer_addr = cpu_to_le64(dma); 3127 3128 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { 3129 tx_desc->cmd_type_offset_bsz = 3130 build_ctob(td_cmd, td_offset, 3131 max_data, td_tag); 3132 3133 tx_desc++; 3134 i++; 3135 desc_count++; 3136 3137 if (i == tx_ring->count) { 3138 tx_desc = I40E_TX_DESC(tx_ring, 0); 3139 i = 0; 3140 } 3141 3142 dma += max_data; 3143 size -= max_data; 3144 3145 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 3146 tx_desc->buffer_addr = cpu_to_le64(dma); 3147 } 3148 3149 if (likely(!data_len)) 3150 break; 3151 3152 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, 3153 size, td_tag); 3154 3155 tx_desc++; 3156 i++; 3157 desc_count++; 3158 3159 if (i == tx_ring->count) { 3160 tx_desc = I40E_TX_DESC(tx_ring, 0); 3161 i = 0; 3162 } 3163 3164 size = skb_frag_size(frag); 3165 data_len -= size; 3166 3167 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 3168 DMA_TO_DEVICE); 3169 3170 tx_bi = &tx_ring->tx_bi[i]; 3171 } 3172 3173 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 3174 3175 i++; 3176 if (i == tx_ring->count) 3177 i = 0; 3178 3179 tx_ring->next_to_use = i; 3180 3181 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); 3182 3183 /* write last descriptor with EOP bit */ 3184 td_cmd |= I40E_TX_DESC_CMD_EOP; 3185 3186 /* We OR these values together to check both against 4 (WB_STRIDE) 3187 * below. This is safe since we don't re-use desc_count afterwards. 3188 */ 3189 desc_count |= ++tx_ring->packet_stride; 3190 3191 if (desc_count >= WB_STRIDE) { 3192 /* write last descriptor with RS bit set */ 3193 td_cmd |= I40E_TX_DESC_CMD_RS; 3194 tx_ring->packet_stride = 0; 3195 } 3196 3197 tx_desc->cmd_type_offset_bsz = 3198 build_ctob(td_cmd, td_offset, size, td_tag); 3199 3200 /* Force memory writes to complete before letting h/w know there 3201 * are new descriptors to fetch. 3202 * 3203 * We also use this memory barrier to make certain all of the 3204 * status bits have been updated before next_to_watch is written. 3205 */ 3206 wmb(); 3207 3208 /* set next_to_watch value indicating a packet is present */ 3209 first->next_to_watch = tx_desc; 3210 3211 /* notify HW of packet */ 3212 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 3213 writel(i, tx_ring->tail); 3214 3215 /* we need this if more than one processor can write to our tail 3216 * at a time, it synchronizes IO on IA64/Altix systems 3217 */ 3218 mmiowb(); 3219 } 3220 3221 return 0; 3222 3223 dma_error: 3224 dev_info(tx_ring->dev, "TX DMA map failed\n"); 3225 3226 /* clear dma mappings for failed tx_bi map */ 3227 for (;;) { 3228 tx_bi = &tx_ring->tx_bi[i]; 3229 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); 3230 if (tx_bi == first) 3231 break; 3232 if (i == 0) 3233 i = tx_ring->count; 3234 i--; 3235 } 3236 3237 tx_ring->next_to_use = i; 3238 3239 return -1; 3240 } 3241 3242 /** 3243 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring 3244 * @xdp: data to transmit 3245 * @xdp_ring: XDP Tx ring 3246 **/ 3247 static int i40e_xmit_xdp_ring(struct xdp_buff *xdp, 3248 struct i40e_ring *xdp_ring) 3249 { 3250 u32 size = xdp->data_end - xdp->data; 3251 u16 i = xdp_ring->next_to_use; 3252 struct i40e_tx_buffer *tx_bi; 3253 struct i40e_tx_desc *tx_desc; 3254 dma_addr_t dma; 3255 3256 if (!unlikely(I40E_DESC_UNUSED(xdp_ring))) { 3257 xdp_ring->tx_stats.tx_busy++; 3258 return I40E_XDP_CONSUMED; 3259 } 3260 3261 dma = dma_map_single(xdp_ring->dev, xdp->data, size, DMA_TO_DEVICE); 3262 if (dma_mapping_error(xdp_ring->dev, dma)) 3263 return I40E_XDP_CONSUMED; 3264 3265 tx_bi = &xdp_ring->tx_bi[i]; 3266 tx_bi->bytecount = size; 3267 tx_bi->gso_segs = 1; 3268 tx_bi->raw_buf = xdp->data; 3269 3270 /* record length, and DMA address */ 3271 dma_unmap_len_set(tx_bi, len, size); 3272 dma_unmap_addr_set(tx_bi, dma, dma); 3273 3274 tx_desc = I40E_TX_DESC(xdp_ring, i); 3275 tx_desc->buffer_addr = cpu_to_le64(dma); 3276 tx_desc->cmd_type_offset_bsz = build_ctob(I40E_TX_DESC_CMD_ICRC 3277 | I40E_TXD_CMD, 3278 0, size, 0); 3279 3280 /* Make certain all of the status bits have been updated 3281 * before next_to_watch is written. 3282 */ 3283 smp_wmb(); 3284 3285 i++; 3286 if (i == xdp_ring->count) 3287 i = 0; 3288 3289 tx_bi->next_to_watch = tx_desc; 3290 xdp_ring->next_to_use = i; 3291 3292 return I40E_XDP_TX; 3293 } 3294 3295 /** 3296 * i40e_xmit_frame_ring - Sends buffer on Tx ring 3297 * @skb: send buffer 3298 * @tx_ring: ring to send buffer on 3299 * 3300 * Returns NETDEV_TX_OK if sent, else an error code 3301 **/ 3302 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, 3303 struct i40e_ring *tx_ring) 3304 { 3305 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; 3306 u32 cd_tunneling = 0, cd_l2tag2 = 0; 3307 struct i40e_tx_buffer *first; 3308 u32 td_offset = 0; 3309 u32 tx_flags = 0; 3310 __be16 protocol; 3311 u32 td_cmd = 0; 3312 u8 hdr_len = 0; 3313 int tso, count; 3314 int tsyn; 3315 3316 /* prefetch the data, we'll need it later */ 3317 prefetch(skb->data); 3318 3319 i40e_trace(xmit_frame_ring, skb, tx_ring); 3320 3321 count = i40e_xmit_descriptor_count(skb); 3322 if (i40e_chk_linearize(skb, count)) { 3323 if (__skb_linearize(skb)) { 3324 dev_kfree_skb_any(skb); 3325 return NETDEV_TX_OK; 3326 } 3327 count = i40e_txd_use_count(skb->len); 3328 tx_ring->tx_stats.tx_linearize++; 3329 } 3330 3331 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, 3332 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, 3333 * + 4 desc gap to avoid the cache line where head is, 3334 * + 1 desc for context descriptor, 3335 * otherwise try next time 3336 */ 3337 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { 3338 tx_ring->tx_stats.tx_busy++; 3339 return NETDEV_TX_BUSY; 3340 } 3341 3342 /* record the location of the first descriptor for this packet */ 3343 first = &tx_ring->tx_bi[tx_ring->next_to_use]; 3344 first->skb = skb; 3345 first->bytecount = skb->len; 3346 first->gso_segs = 1; 3347 3348 /* prepare the xmit flags */ 3349 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) 3350 goto out_drop; 3351 3352 /* obtain protocol of skb */ 3353 protocol = vlan_get_protocol(skb); 3354 3355 /* setup IPv4/IPv6 offloads */ 3356 if (protocol == htons(ETH_P_IP)) 3357 tx_flags |= I40E_TX_FLAGS_IPV4; 3358 else if (protocol == htons(ETH_P_IPV6)) 3359 tx_flags |= I40E_TX_FLAGS_IPV6; 3360 3361 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); 3362 3363 if (tso < 0) 3364 goto out_drop; 3365 else if (tso) 3366 tx_flags |= I40E_TX_FLAGS_TSO; 3367 3368 /* Always offload the checksum, since it's in the data descriptor */ 3369 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, 3370 tx_ring, &cd_tunneling); 3371 if (tso < 0) 3372 goto out_drop; 3373 3374 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); 3375 3376 if (tsyn) 3377 tx_flags |= I40E_TX_FLAGS_TSYN; 3378 3379 skb_tx_timestamp(skb); 3380 3381 /* always enable CRC insertion offload */ 3382 td_cmd |= I40E_TX_DESC_CMD_ICRC; 3383 3384 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, 3385 cd_tunneling, cd_l2tag2); 3386 3387 /* Add Flow Director ATR if it's enabled. 3388 * 3389 * NOTE: this must always be directly before the data descriptor. 3390 */ 3391 i40e_atr(tx_ring, skb, tx_flags); 3392 3393 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, 3394 td_cmd, td_offset)) 3395 goto cleanup_tx_tstamp; 3396 3397 return NETDEV_TX_OK; 3398 3399 out_drop: 3400 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring); 3401 dev_kfree_skb_any(first->skb); 3402 first->skb = NULL; 3403 cleanup_tx_tstamp: 3404 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) { 3405 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev); 3406 3407 dev_kfree_skb_any(pf->ptp_tx_skb); 3408 pf->ptp_tx_skb = NULL; 3409 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 3410 } 3411 3412 return NETDEV_TX_OK; 3413 } 3414 3415 /** 3416 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer 3417 * @skb: send buffer 3418 * @netdev: network interface device structure 3419 * 3420 * Returns NETDEV_TX_OK if sent, else an error code 3421 **/ 3422 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 3423 { 3424 struct i40e_netdev_priv *np = netdev_priv(netdev); 3425 struct i40e_vsi *vsi = np->vsi; 3426 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; 3427 3428 /* hardware can't handle really short frames, hardware padding works 3429 * beyond this point 3430 */ 3431 if (skb_put_padto(skb, I40E_MIN_TX_LEN)) 3432 return NETDEV_TX_OK; 3433 3434 return i40e_xmit_frame_ring(skb, tx_ring); 3435 } 3436