1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include <linux/bpf_trace.h> 5 #include <linux/prefetch.h> 6 #include <linux/sctp.h> 7 #include <net/mpls.h> 8 #include <net/xdp.h> 9 #include "i40e_txrx_common.h" 10 #include "i40e_trace.h" 11 #include "i40e_xsk.h" 12 13 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) 14 /** 15 * i40e_fdir - Generate a Flow Director descriptor based on fdata 16 * @tx_ring: Tx ring to send buffer on 17 * @fdata: Flow director filter data 18 * @add: Indicate if we are adding a rule or deleting one 19 * 20 **/ 21 static void i40e_fdir(struct i40e_ring *tx_ring, 22 struct i40e_fdir_filter *fdata, bool add) 23 { 24 struct i40e_filter_program_desc *fdir_desc; 25 struct i40e_pf *pf = tx_ring->vsi->back; 26 u32 flex_ptype, dtype_cmd; 27 u16 i; 28 29 /* grab the next descriptor */ 30 i = tx_ring->next_to_use; 31 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 32 33 i++; 34 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 35 36 flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK & 37 (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT); 38 39 flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK & 40 (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); 41 42 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & 43 (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 44 45 /* Use LAN VSI Id if not programmed by user */ 46 flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK & 47 ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) << 48 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT); 49 50 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 51 52 dtype_cmd |= add ? 53 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 54 I40E_TXD_FLTR_QW1_PCMD_SHIFT : 55 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 56 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 57 58 dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK & 59 (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT); 60 61 dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK & 62 (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT); 63 64 if (fdata->cnt_index) { 65 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 66 dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK & 67 ((u32)fdata->cnt_index << 68 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT); 69 } 70 71 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 72 fdir_desc->rsvd = cpu_to_le32(0); 73 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 74 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id); 75 } 76 77 #define I40E_FD_CLEAN_DELAY 10 78 /** 79 * i40e_program_fdir_filter - Program a Flow Director filter 80 * @fdir_data: Packet data that will be filter parameters 81 * @raw_packet: the pre-allocated packet buffer for FDir 82 * @pf: The PF pointer 83 * @add: True for add/update, False for remove 84 **/ 85 static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, 86 u8 *raw_packet, struct i40e_pf *pf, 87 bool add) 88 { 89 struct i40e_tx_buffer *tx_buf, *first; 90 struct i40e_tx_desc *tx_desc; 91 struct i40e_ring *tx_ring; 92 struct i40e_vsi *vsi; 93 struct device *dev; 94 dma_addr_t dma; 95 u32 td_cmd = 0; 96 u16 i; 97 98 /* find existing FDIR VSI */ 99 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); 100 if (!vsi) 101 return -ENOENT; 102 103 tx_ring = vsi->tx_rings[0]; 104 dev = tx_ring->dev; 105 106 /* we need two descriptors to add/del a filter and we can wait */ 107 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) { 108 if (!i) 109 return -EAGAIN; 110 msleep_interruptible(1); 111 } 112 113 dma = dma_map_single(dev, raw_packet, 114 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); 115 if (dma_mapping_error(dev, dma)) 116 goto dma_fail; 117 118 /* grab the next descriptor */ 119 i = tx_ring->next_to_use; 120 first = &tx_ring->tx_bi[i]; 121 i40e_fdir(tx_ring, fdir_data, add); 122 123 /* Now program a dummy descriptor */ 124 i = tx_ring->next_to_use; 125 tx_desc = I40E_TX_DESC(tx_ring, i); 126 tx_buf = &tx_ring->tx_bi[i]; 127 128 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 129 130 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); 131 132 /* record length, and DMA address */ 133 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); 134 dma_unmap_addr_set(tx_buf, dma, dma); 135 136 tx_desc->buffer_addr = cpu_to_le64(dma); 137 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; 138 139 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; 140 tx_buf->raw_buf = (void *)raw_packet; 141 142 tx_desc->cmd_type_offset_bsz = 143 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); 144 145 /* Force memory writes to complete before letting h/w 146 * know there are new descriptors to fetch. 147 */ 148 wmb(); 149 150 /* Mark the data descriptor to be watched */ 151 first->next_to_watch = tx_desc; 152 153 writel(tx_ring->next_to_use, tx_ring->tail); 154 return 0; 155 156 dma_fail: 157 return -1; 158 } 159 160 /** 161 * i40e_create_dummy_packet - Constructs dummy packet for HW 162 * @dummy_packet: preallocated space for dummy packet 163 * @ipv4: is layer 3 packet of version 4 or 6 164 * @l4proto: next level protocol used in data portion of l3 165 * @data: filter data 166 * 167 * Returns address of layer 4 protocol dummy packet. 168 **/ 169 static char *i40e_create_dummy_packet(u8 *dummy_packet, bool ipv4, u8 l4proto, 170 struct i40e_fdir_filter *data) 171 { 172 bool is_vlan = !!data->vlan_tag; 173 struct vlan_hdr vlan = {}; 174 struct ipv6hdr ipv6 = {}; 175 struct ethhdr eth = {}; 176 struct iphdr ip = {}; 177 u8 *tmp; 178 179 if (ipv4) { 180 eth.h_proto = cpu_to_be16(ETH_P_IP); 181 ip.protocol = l4proto; 182 ip.version = 0x4; 183 ip.ihl = 0x5; 184 185 ip.daddr = data->dst_ip; 186 ip.saddr = data->src_ip; 187 } else { 188 eth.h_proto = cpu_to_be16(ETH_P_IPV6); 189 ipv6.nexthdr = l4proto; 190 ipv6.version = 0x6; 191 192 memcpy(&ipv6.saddr.in6_u.u6_addr32, data->src_ip6, 193 sizeof(__be32) * 4); 194 memcpy(&ipv6.daddr.in6_u.u6_addr32, data->dst_ip6, 195 sizeof(__be32) * 4); 196 } 197 198 if (is_vlan) { 199 vlan.h_vlan_TCI = data->vlan_tag; 200 vlan.h_vlan_encapsulated_proto = eth.h_proto; 201 eth.h_proto = data->vlan_etype; 202 } 203 204 tmp = dummy_packet; 205 memcpy(tmp, ð, sizeof(eth)); 206 tmp += sizeof(eth); 207 208 if (is_vlan) { 209 memcpy(tmp, &vlan, sizeof(vlan)); 210 tmp += sizeof(vlan); 211 } 212 213 if (ipv4) { 214 memcpy(tmp, &ip, sizeof(ip)); 215 tmp += sizeof(ip); 216 } else { 217 memcpy(tmp, &ipv6, sizeof(ipv6)); 218 tmp += sizeof(ipv6); 219 } 220 221 return tmp; 222 } 223 224 /** 225 * i40e_create_dummy_udp_packet - helper function to create UDP packet 226 * @raw_packet: preallocated space for dummy packet 227 * @ipv4: is layer 3 packet of version 4 or 6 228 * @l4proto: next level protocol used in data portion of l3 229 * @data: filter data 230 * 231 * Helper function to populate udp fields. 232 **/ 233 static void i40e_create_dummy_udp_packet(u8 *raw_packet, bool ipv4, u8 l4proto, 234 struct i40e_fdir_filter *data) 235 { 236 struct udphdr *udp; 237 u8 *tmp; 238 239 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_UDP, data); 240 udp = (struct udphdr *)(tmp); 241 udp->dest = data->dst_port; 242 udp->source = data->src_port; 243 } 244 245 /** 246 * i40e_create_dummy_tcp_packet - helper function to create TCP packet 247 * @raw_packet: preallocated space for dummy packet 248 * @ipv4: is layer 3 packet of version 4 or 6 249 * @l4proto: next level protocol used in data portion of l3 250 * @data: filter data 251 * 252 * Helper function to populate tcp fields. 253 **/ 254 static void i40e_create_dummy_tcp_packet(u8 *raw_packet, bool ipv4, u8 l4proto, 255 struct i40e_fdir_filter *data) 256 { 257 struct tcphdr *tcp; 258 u8 *tmp; 259 /* Dummy tcp packet */ 260 static const char tcp_packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 261 0x50, 0x11, 0x0, 0x72, 0, 0, 0, 0}; 262 263 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_TCP, data); 264 265 tcp = (struct tcphdr *)tmp; 266 memcpy(tcp, tcp_packet, sizeof(tcp_packet)); 267 tcp->dest = data->dst_port; 268 tcp->source = data->src_port; 269 } 270 271 /** 272 * i40e_create_dummy_sctp_packet - helper function to create SCTP packet 273 * @raw_packet: preallocated space for dummy packet 274 * @ipv4: is layer 3 packet of version 4 or 6 275 * @l4proto: next level protocol used in data portion of l3 276 * @data: filter data 277 * 278 * Helper function to populate sctp fields. 279 **/ 280 static void i40e_create_dummy_sctp_packet(u8 *raw_packet, bool ipv4, 281 u8 l4proto, 282 struct i40e_fdir_filter *data) 283 { 284 struct sctphdr *sctp; 285 u8 *tmp; 286 287 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_SCTP, data); 288 289 sctp = (struct sctphdr *)tmp; 290 sctp->dest = data->dst_port; 291 sctp->source = data->src_port; 292 } 293 294 /** 295 * i40e_prepare_fdir_filter - Prepare and program fdir filter 296 * @pf: physical function to attach filter to 297 * @fd_data: filter data 298 * @add: add or delete filter 299 * @packet_addr: address of dummy packet, used in filtering 300 * @payload_offset: offset from dummy packet address to user defined data 301 * @pctype: Packet type for which filter is used 302 * 303 * Helper function to offset data of dummy packet, program it and 304 * handle errors. 305 **/ 306 static int i40e_prepare_fdir_filter(struct i40e_pf *pf, 307 struct i40e_fdir_filter *fd_data, 308 bool add, char *packet_addr, 309 int payload_offset, u8 pctype) 310 { 311 int ret; 312 313 if (fd_data->flex_filter) { 314 u8 *payload; 315 __be16 pattern = fd_data->flex_word; 316 u16 off = fd_data->flex_offset; 317 318 payload = packet_addr + payload_offset; 319 320 /* If user provided vlan, offset payload by vlan header length */ 321 if (!!fd_data->vlan_tag) 322 payload += VLAN_HLEN; 323 324 *((__force __be16 *)(payload + off)) = pattern; 325 } 326 327 fd_data->pctype = pctype; 328 ret = i40e_program_fdir_filter(fd_data, packet_addr, pf, add); 329 if (ret) { 330 dev_info(&pf->pdev->dev, 331 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 332 fd_data->pctype, fd_data->fd_id, ret); 333 /* Free the packet buffer since it wasn't added to the ring */ 334 return -EOPNOTSUPP; 335 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 336 if (add) 337 dev_info(&pf->pdev->dev, 338 "Filter OK for PCTYPE %d loc = %d\n", 339 fd_data->pctype, fd_data->fd_id); 340 else 341 dev_info(&pf->pdev->dev, 342 "Filter deleted for PCTYPE %d loc = %d\n", 343 fd_data->pctype, fd_data->fd_id); 344 } 345 346 return ret; 347 } 348 349 /** 350 * i40e_change_filter_num - Prepare and program fdir filter 351 * @ipv4: is layer 3 packet of version 4 or 6 352 * @add: add or delete filter 353 * @ipv4_filter_num: field to update 354 * @ipv6_filter_num: field to update 355 * 356 * Update filter number field for pf. 357 **/ 358 static void i40e_change_filter_num(bool ipv4, bool add, u16 *ipv4_filter_num, 359 u16 *ipv6_filter_num) 360 { 361 if (add) { 362 if (ipv4) 363 (*ipv4_filter_num)++; 364 else 365 (*ipv6_filter_num)++; 366 } else { 367 if (ipv4) 368 (*ipv4_filter_num)--; 369 else 370 (*ipv6_filter_num)--; 371 } 372 } 373 374 #define I40E_UDPIP_DUMMY_PACKET_LEN 42 375 #define I40E_UDPIP6_DUMMY_PACKET_LEN 62 376 /** 377 * i40e_add_del_fdir_udp - Add/Remove UDP filters 378 * @vsi: pointer to the targeted VSI 379 * @fd_data: the flow director data required for the FDir descriptor 380 * @add: true adds a filter, false removes it 381 * @ipv4: true is v4, false is v6 382 * 383 * Returns 0 if the filters were successfully added or removed 384 **/ 385 static int i40e_add_del_fdir_udp(struct i40e_vsi *vsi, 386 struct i40e_fdir_filter *fd_data, 387 bool add, 388 bool ipv4) 389 { 390 struct i40e_pf *pf = vsi->back; 391 u8 *raw_packet; 392 int ret; 393 394 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 395 if (!raw_packet) 396 return -ENOMEM; 397 398 i40e_create_dummy_udp_packet(raw_packet, ipv4, IPPROTO_UDP, fd_data); 399 400 if (ipv4) 401 ret = i40e_prepare_fdir_filter 402 (pf, fd_data, add, raw_packet, 403 I40E_UDPIP_DUMMY_PACKET_LEN, 404 I40E_FILTER_PCTYPE_NONF_IPV4_UDP); 405 else 406 ret = i40e_prepare_fdir_filter 407 (pf, fd_data, add, raw_packet, 408 I40E_UDPIP6_DUMMY_PACKET_LEN, 409 I40E_FILTER_PCTYPE_NONF_IPV6_UDP); 410 411 if (ret) { 412 kfree(raw_packet); 413 return ret; 414 } 415 416 i40e_change_filter_num(ipv4, add, &pf->fd_udp4_filter_cnt, 417 &pf->fd_udp6_filter_cnt); 418 419 return 0; 420 } 421 422 #define I40E_TCPIP_DUMMY_PACKET_LEN 54 423 #define I40E_TCPIP6_DUMMY_PACKET_LEN 74 424 /** 425 * i40e_add_del_fdir_tcp - Add/Remove TCPv4 filters 426 * @vsi: pointer to the targeted VSI 427 * @fd_data: the flow director data required for the FDir descriptor 428 * @add: true adds a filter, false removes it 429 * @ipv4: true is v4, false is v6 430 * 431 * Returns 0 if the filters were successfully added or removed 432 **/ 433 static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi, 434 struct i40e_fdir_filter *fd_data, 435 bool add, 436 bool ipv4) 437 { 438 struct i40e_pf *pf = vsi->back; 439 u8 *raw_packet; 440 int ret; 441 442 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 443 if (!raw_packet) 444 return -ENOMEM; 445 446 i40e_create_dummy_tcp_packet(raw_packet, ipv4, IPPROTO_TCP, fd_data); 447 if (ipv4) 448 ret = i40e_prepare_fdir_filter 449 (pf, fd_data, add, raw_packet, 450 I40E_TCPIP_DUMMY_PACKET_LEN, 451 I40E_FILTER_PCTYPE_NONF_IPV4_TCP); 452 else 453 ret = i40e_prepare_fdir_filter 454 (pf, fd_data, add, raw_packet, 455 I40E_TCPIP6_DUMMY_PACKET_LEN, 456 I40E_FILTER_PCTYPE_NONF_IPV6_TCP); 457 458 if (ret) { 459 kfree(raw_packet); 460 return ret; 461 } 462 463 i40e_change_filter_num(ipv4, add, &pf->fd_tcp4_filter_cnt, 464 &pf->fd_tcp6_filter_cnt); 465 466 if (add) { 467 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && 468 I40E_DEBUG_FD & pf->hw.debug_mask) 469 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); 470 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); 471 } 472 return 0; 473 } 474 475 #define I40E_SCTPIP_DUMMY_PACKET_LEN 46 476 #define I40E_SCTPIP6_DUMMY_PACKET_LEN 66 477 /** 478 * i40e_add_del_fdir_sctp - Add/Remove SCTPv4 Flow Director filters for 479 * a specific flow spec 480 * @vsi: pointer to the targeted VSI 481 * @fd_data: the flow director data required for the FDir descriptor 482 * @add: true adds a filter, false removes it 483 * @ipv4: true is v4, false is v6 484 * 485 * Returns 0 if the filters were successfully added or removed 486 **/ 487 static int i40e_add_del_fdir_sctp(struct i40e_vsi *vsi, 488 struct i40e_fdir_filter *fd_data, 489 bool add, 490 bool ipv4) 491 { 492 struct i40e_pf *pf = vsi->back; 493 u8 *raw_packet; 494 int ret; 495 496 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 497 if (!raw_packet) 498 return -ENOMEM; 499 500 i40e_create_dummy_sctp_packet(raw_packet, ipv4, IPPROTO_SCTP, fd_data); 501 502 if (ipv4) 503 ret = i40e_prepare_fdir_filter 504 (pf, fd_data, add, raw_packet, 505 I40E_SCTPIP_DUMMY_PACKET_LEN, 506 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP); 507 else 508 ret = i40e_prepare_fdir_filter 509 (pf, fd_data, add, raw_packet, 510 I40E_SCTPIP6_DUMMY_PACKET_LEN, 511 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP); 512 513 if (ret) { 514 kfree(raw_packet); 515 return ret; 516 } 517 518 i40e_change_filter_num(ipv4, add, &pf->fd_sctp4_filter_cnt, 519 &pf->fd_sctp6_filter_cnt); 520 521 return 0; 522 } 523 524 #define I40E_IP_DUMMY_PACKET_LEN 34 525 #define I40E_IP6_DUMMY_PACKET_LEN 54 526 /** 527 * i40e_add_del_fdir_ip - Add/Remove IPv4 Flow Director filters for 528 * a specific flow spec 529 * @vsi: pointer to the targeted VSI 530 * @fd_data: the flow director data required for the FDir descriptor 531 * @add: true adds a filter, false removes it 532 * @ipv4: true is v4, false is v6 533 * 534 * Returns 0 if the filters were successfully added or removed 535 **/ 536 static int i40e_add_del_fdir_ip(struct i40e_vsi *vsi, 537 struct i40e_fdir_filter *fd_data, 538 bool add, 539 bool ipv4) 540 { 541 struct i40e_pf *pf = vsi->back; 542 int payload_offset; 543 u8 *raw_packet; 544 int iter_start; 545 int iter_end; 546 int ret; 547 int i; 548 549 if (ipv4) { 550 iter_start = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; 551 iter_end = I40E_FILTER_PCTYPE_FRAG_IPV4; 552 } else { 553 iter_start = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER; 554 iter_end = I40E_FILTER_PCTYPE_FRAG_IPV6; 555 } 556 557 for (i = iter_start; i <= iter_end; i++) { 558 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 559 if (!raw_packet) 560 return -ENOMEM; 561 562 /* IPv6 no header option differs from IPv4 */ 563 (void)i40e_create_dummy_packet 564 (raw_packet, ipv4, (ipv4) ? IPPROTO_IP : IPPROTO_NONE, 565 fd_data); 566 567 payload_offset = (ipv4) ? I40E_IP_DUMMY_PACKET_LEN : 568 I40E_IP6_DUMMY_PACKET_LEN; 569 ret = i40e_prepare_fdir_filter(pf, fd_data, add, raw_packet, 570 payload_offset, i); 571 if (ret) 572 goto err; 573 } 574 575 i40e_change_filter_num(ipv4, add, &pf->fd_ip4_filter_cnt, 576 &pf->fd_ip6_filter_cnt); 577 578 return 0; 579 err: 580 kfree(raw_packet); 581 return ret; 582 } 583 584 /** 585 * i40e_add_del_fdir - Build raw packets to add/del fdir filter 586 * @vsi: pointer to the targeted VSI 587 * @input: filter to add or delete 588 * @add: true adds a filter, false removes it 589 * 590 **/ 591 int i40e_add_del_fdir(struct i40e_vsi *vsi, 592 struct i40e_fdir_filter *input, bool add) 593 { 594 enum ip_ver { ipv6 = 0, ipv4 = 1 }; 595 struct i40e_pf *pf = vsi->back; 596 int ret; 597 598 switch (input->flow_type & ~FLOW_EXT) { 599 case TCP_V4_FLOW: 600 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4); 601 break; 602 case UDP_V4_FLOW: 603 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4); 604 break; 605 case SCTP_V4_FLOW: 606 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4); 607 break; 608 case TCP_V6_FLOW: 609 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6); 610 break; 611 case UDP_V6_FLOW: 612 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6); 613 break; 614 case SCTP_V6_FLOW: 615 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6); 616 break; 617 case IP_USER_FLOW: 618 switch (input->ipl4_proto) { 619 case IPPROTO_TCP: 620 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4); 621 break; 622 case IPPROTO_UDP: 623 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4); 624 break; 625 case IPPROTO_SCTP: 626 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4); 627 break; 628 case IPPROTO_IP: 629 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv4); 630 break; 631 default: 632 /* We cannot support masking based on protocol */ 633 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n", 634 input->ipl4_proto); 635 return -EINVAL; 636 } 637 break; 638 case IPV6_USER_FLOW: 639 switch (input->ipl4_proto) { 640 case IPPROTO_TCP: 641 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6); 642 break; 643 case IPPROTO_UDP: 644 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6); 645 break; 646 case IPPROTO_SCTP: 647 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6); 648 break; 649 case IPPROTO_IP: 650 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv6); 651 break; 652 default: 653 /* We cannot support masking based on protocol */ 654 dev_info(&pf->pdev->dev, "Unsupported IPv6 protocol 0x%02x\n", 655 input->ipl4_proto); 656 return -EINVAL; 657 } 658 break; 659 default: 660 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n", 661 input->flow_type); 662 return -EINVAL; 663 } 664 665 /* The buffer allocated here will be normally be freed by 666 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit 667 * completion. In the event of an error adding the buffer to the FDIR 668 * ring, it will immediately be freed. It may also be freed by 669 * i40e_clean_tx_ring() when closing the VSI. 670 */ 671 return ret; 672 } 673 674 /** 675 * i40e_fd_handle_status - check the Programming Status for FD 676 * @rx_ring: the Rx ring for this descriptor 677 * @qword0_raw: qword0 678 * @qword1: qword1 after le_to_cpu 679 * @prog_id: the id originally used for programming 680 * 681 * This is used to verify if the FD programming or invalidation 682 * requested by SW to the HW is successful or not and take actions accordingly. 683 **/ 684 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw, 685 u64 qword1, u8 prog_id) 686 { 687 struct i40e_pf *pf = rx_ring->vsi->back; 688 struct pci_dev *pdev = pf->pdev; 689 struct i40e_16b_rx_wb_qw0 *qw0; 690 u32 fcnt_prog, fcnt_avail; 691 u32 error; 692 693 qw0 = (struct i40e_16b_rx_wb_qw0 *)&qword0_raw; 694 error = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> 695 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; 696 697 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { 698 pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id); 699 if (qw0->hi_dword.fd_id != 0 || 700 (I40E_DEBUG_FD & pf->hw.debug_mask)) 701 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", 702 pf->fd_inv); 703 704 /* Check if the programming error is for ATR. 705 * If so, auto disable ATR and set a state for 706 * flush in progress. Next time we come here if flush is in 707 * progress do nothing, once flush is complete the state will 708 * be cleared. 709 */ 710 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) 711 return; 712 713 pf->fd_add_err++; 714 /* store the current atr filter count */ 715 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); 716 717 if (qw0->hi_dword.fd_id == 0 && 718 test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) { 719 /* These set_bit() calls aren't atomic with the 720 * test_bit() here, but worse case we potentially 721 * disable ATR and queue a flush right after SB 722 * support is re-enabled. That shouldn't cause an 723 * issue in practice 724 */ 725 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); 726 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); 727 } 728 729 /* filter programming failed most likely due to table full */ 730 fcnt_prog = i40e_get_global_fd_count(pf); 731 fcnt_avail = pf->fdir_pf_filter_count; 732 /* If ATR is running fcnt_prog can quickly change, 733 * if we are very close to full, it makes sense to disable 734 * FD ATR/SB and then re-enable it when there is room. 735 */ 736 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { 737 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && 738 !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED, 739 pf->state)) 740 if (I40E_DEBUG_FD & pf->hw.debug_mask) 741 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); 742 } 743 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { 744 if (I40E_DEBUG_FD & pf->hw.debug_mask) 745 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", 746 qw0->hi_dword.fd_id); 747 } 748 } 749 750 /** 751 * i40e_unmap_and_free_tx_resource - Release a Tx buffer 752 * @ring: the ring that owns the buffer 753 * @tx_buffer: the buffer to free 754 **/ 755 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, 756 struct i40e_tx_buffer *tx_buffer) 757 { 758 if (tx_buffer->skb) { 759 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) 760 kfree(tx_buffer->raw_buf); 761 else if (ring_is_xdp(ring)) 762 xdp_return_frame(tx_buffer->xdpf); 763 else 764 dev_kfree_skb_any(tx_buffer->skb); 765 if (dma_unmap_len(tx_buffer, len)) 766 dma_unmap_single(ring->dev, 767 dma_unmap_addr(tx_buffer, dma), 768 dma_unmap_len(tx_buffer, len), 769 DMA_TO_DEVICE); 770 } else if (dma_unmap_len(tx_buffer, len)) { 771 dma_unmap_page(ring->dev, 772 dma_unmap_addr(tx_buffer, dma), 773 dma_unmap_len(tx_buffer, len), 774 DMA_TO_DEVICE); 775 } 776 777 tx_buffer->next_to_watch = NULL; 778 tx_buffer->skb = NULL; 779 dma_unmap_len_set(tx_buffer, len, 0); 780 /* tx_buffer must be completely set up in the transmit path */ 781 } 782 783 /** 784 * i40e_clean_tx_ring - Free any empty Tx buffers 785 * @tx_ring: ring to be cleaned 786 **/ 787 void i40e_clean_tx_ring(struct i40e_ring *tx_ring) 788 { 789 unsigned long bi_size; 790 u16 i; 791 792 if (ring_is_xdp(tx_ring) && tx_ring->xsk_pool) { 793 i40e_xsk_clean_tx_ring(tx_ring); 794 } else { 795 /* ring already cleared, nothing to do */ 796 if (!tx_ring->tx_bi) 797 return; 798 799 /* Free all the Tx ring sk_buffs */ 800 for (i = 0; i < tx_ring->count; i++) 801 i40e_unmap_and_free_tx_resource(tx_ring, 802 &tx_ring->tx_bi[i]); 803 } 804 805 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 806 memset(tx_ring->tx_bi, 0, bi_size); 807 808 /* Zero out the descriptor ring */ 809 memset(tx_ring->desc, 0, tx_ring->size); 810 811 tx_ring->next_to_use = 0; 812 tx_ring->next_to_clean = 0; 813 814 if (!tx_ring->netdev) 815 return; 816 817 /* cleanup Tx queue statistics */ 818 netdev_tx_reset_queue(txring_txq(tx_ring)); 819 } 820 821 /** 822 * i40e_free_tx_resources - Free Tx resources per queue 823 * @tx_ring: Tx descriptor ring for a specific queue 824 * 825 * Free all transmit software resources 826 **/ 827 void i40e_free_tx_resources(struct i40e_ring *tx_ring) 828 { 829 i40e_clean_tx_ring(tx_ring); 830 kfree(tx_ring->tx_bi); 831 tx_ring->tx_bi = NULL; 832 833 if (tx_ring->desc) { 834 dma_free_coherent(tx_ring->dev, tx_ring->size, 835 tx_ring->desc, tx_ring->dma); 836 tx_ring->desc = NULL; 837 } 838 } 839 840 /** 841 * i40e_get_tx_pending - how many tx descriptors not processed 842 * @ring: the ring of descriptors 843 * @in_sw: use SW variables 844 * 845 * Since there is no access to the ring head register 846 * in XL710, we need to use our local copies 847 **/ 848 u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw) 849 { 850 u32 head, tail; 851 852 if (!in_sw) { 853 head = i40e_get_head(ring); 854 tail = readl(ring->tail); 855 } else { 856 head = ring->next_to_clean; 857 tail = ring->next_to_use; 858 } 859 860 if (head != tail) 861 return (head < tail) ? 862 tail - head : (tail + ring->count - head); 863 864 return 0; 865 } 866 867 /** 868 * i40e_detect_recover_hung - Function to detect and recover hung_queues 869 * @vsi: pointer to vsi struct with tx queues 870 * 871 * VSI has netdev and netdev has TX queues. This function is to check each of 872 * those TX queues if they are hung, trigger recovery by issuing SW interrupt. 873 **/ 874 void i40e_detect_recover_hung(struct i40e_vsi *vsi) 875 { 876 struct i40e_ring *tx_ring = NULL; 877 struct net_device *netdev; 878 unsigned int i; 879 int packets; 880 881 if (!vsi) 882 return; 883 884 if (test_bit(__I40E_VSI_DOWN, vsi->state)) 885 return; 886 887 netdev = vsi->netdev; 888 if (!netdev) 889 return; 890 891 if (!netif_carrier_ok(netdev)) 892 return; 893 894 for (i = 0; i < vsi->num_queue_pairs; i++) { 895 tx_ring = vsi->tx_rings[i]; 896 if (tx_ring && tx_ring->desc) { 897 /* If packet counter has not changed the queue is 898 * likely stalled, so force an interrupt for this 899 * queue. 900 * 901 * prev_pkt_ctr would be negative if there was no 902 * pending work. 903 */ 904 packets = tx_ring->stats.packets & INT_MAX; 905 if (tx_ring->tx_stats.prev_pkt_ctr == packets) { 906 i40e_force_wb(vsi, tx_ring->q_vector); 907 continue; 908 } 909 910 /* Memory barrier between read of packet count and call 911 * to i40e_get_tx_pending() 912 */ 913 smp_rmb(); 914 tx_ring->tx_stats.prev_pkt_ctr = 915 i40e_get_tx_pending(tx_ring, true) ? packets : -1; 916 } 917 } 918 } 919 920 /** 921 * i40e_clean_tx_irq - Reclaim resources after transmit completes 922 * @vsi: the VSI we care about 923 * @tx_ring: Tx ring to clean 924 * @napi_budget: Used to determine if we are in netpoll 925 * @tx_cleaned: Out parameter set to the number of TXes cleaned 926 * 927 * Returns true if there's any budget left (e.g. the clean is finished) 928 **/ 929 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, 930 struct i40e_ring *tx_ring, int napi_budget, 931 unsigned int *tx_cleaned) 932 { 933 int i = tx_ring->next_to_clean; 934 struct i40e_tx_buffer *tx_buf; 935 struct i40e_tx_desc *tx_head; 936 struct i40e_tx_desc *tx_desc; 937 unsigned int total_bytes = 0, total_packets = 0; 938 unsigned int budget = vsi->work_limit; 939 940 tx_buf = &tx_ring->tx_bi[i]; 941 tx_desc = I40E_TX_DESC(tx_ring, i); 942 i -= tx_ring->count; 943 944 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); 945 946 do { 947 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; 948 949 /* if next_to_watch is not set then there is no work pending */ 950 if (!eop_desc) 951 break; 952 953 /* prevent any other reads prior to eop_desc */ 954 smp_rmb(); 955 956 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); 957 /* we have caught up to head, no work left to do */ 958 if (tx_head == tx_desc) 959 break; 960 961 /* clear next_to_watch to prevent false hangs */ 962 tx_buf->next_to_watch = NULL; 963 964 /* update the statistics for this packet */ 965 total_bytes += tx_buf->bytecount; 966 total_packets += tx_buf->gso_segs; 967 968 /* free the skb/XDP data */ 969 if (ring_is_xdp(tx_ring)) 970 xdp_return_frame(tx_buf->xdpf); 971 else 972 napi_consume_skb(tx_buf->skb, napi_budget); 973 974 /* unmap skb header data */ 975 dma_unmap_single(tx_ring->dev, 976 dma_unmap_addr(tx_buf, dma), 977 dma_unmap_len(tx_buf, len), 978 DMA_TO_DEVICE); 979 980 /* clear tx_buffer data */ 981 tx_buf->skb = NULL; 982 dma_unmap_len_set(tx_buf, len, 0); 983 984 /* unmap remaining buffers */ 985 while (tx_desc != eop_desc) { 986 i40e_trace(clean_tx_irq_unmap, 987 tx_ring, tx_desc, tx_buf); 988 989 tx_buf++; 990 tx_desc++; 991 i++; 992 if (unlikely(!i)) { 993 i -= tx_ring->count; 994 tx_buf = tx_ring->tx_bi; 995 tx_desc = I40E_TX_DESC(tx_ring, 0); 996 } 997 998 /* unmap any remaining paged data */ 999 if (dma_unmap_len(tx_buf, len)) { 1000 dma_unmap_page(tx_ring->dev, 1001 dma_unmap_addr(tx_buf, dma), 1002 dma_unmap_len(tx_buf, len), 1003 DMA_TO_DEVICE); 1004 dma_unmap_len_set(tx_buf, len, 0); 1005 } 1006 } 1007 1008 /* move us one more past the eop_desc for start of next pkt */ 1009 tx_buf++; 1010 tx_desc++; 1011 i++; 1012 if (unlikely(!i)) { 1013 i -= tx_ring->count; 1014 tx_buf = tx_ring->tx_bi; 1015 tx_desc = I40E_TX_DESC(tx_ring, 0); 1016 } 1017 1018 prefetch(tx_desc); 1019 1020 /* update budget accounting */ 1021 budget--; 1022 } while (likely(budget)); 1023 1024 i += tx_ring->count; 1025 tx_ring->next_to_clean = i; 1026 i40e_update_tx_stats(tx_ring, total_packets, total_bytes); 1027 i40e_arm_wb(tx_ring, vsi, budget); 1028 1029 if (ring_is_xdp(tx_ring)) 1030 return !!budget; 1031 1032 /* notify netdev of completed buffers */ 1033 netdev_tx_completed_queue(txring_txq(tx_ring), 1034 total_packets, total_bytes); 1035 1036 #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2)) 1037 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1038 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 1039 /* Make sure that anybody stopping the queue after this 1040 * sees the new next_to_clean. 1041 */ 1042 smp_mb(); 1043 if (__netif_subqueue_stopped(tx_ring->netdev, 1044 tx_ring->queue_index) && 1045 !test_bit(__I40E_VSI_DOWN, vsi->state)) { 1046 netif_wake_subqueue(tx_ring->netdev, 1047 tx_ring->queue_index); 1048 ++tx_ring->tx_stats.restart_queue; 1049 } 1050 } 1051 1052 *tx_cleaned = total_packets; 1053 return !!budget; 1054 } 1055 1056 /** 1057 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled 1058 * @vsi: the VSI we care about 1059 * @q_vector: the vector on which to enable writeback 1060 * 1061 **/ 1062 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, 1063 struct i40e_q_vector *q_vector) 1064 { 1065 u16 flags = q_vector->tx.ring[0].flags; 1066 u32 val; 1067 1068 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) 1069 return; 1070 1071 if (q_vector->arm_wb_state) 1072 return; 1073 1074 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 1075 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | 1076 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ 1077 1078 wr32(&vsi->back->hw, 1079 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), 1080 val); 1081 } else { 1082 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | 1083 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ 1084 1085 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 1086 } 1087 q_vector->arm_wb_state = true; 1088 } 1089 1090 /** 1091 * i40e_force_wb - Issue SW Interrupt so HW does a wb 1092 * @vsi: the VSI we care about 1093 * @q_vector: the vector on which to force writeback 1094 * 1095 **/ 1096 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) 1097 { 1098 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 1099 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1100 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ 1101 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 1102 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; 1103 /* allow 00 to be written to the index */ 1104 1105 wr32(&vsi->back->hw, 1106 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val); 1107 } else { 1108 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | 1109 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ 1110 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | 1111 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; 1112 /* allow 00 to be written to the index */ 1113 1114 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 1115 } 1116 } 1117 1118 static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector, 1119 struct i40e_ring_container *rc) 1120 { 1121 return &q_vector->rx == rc; 1122 } 1123 1124 static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector) 1125 { 1126 unsigned int divisor; 1127 1128 switch (q_vector->vsi->back->hw.phy.link_info.link_speed) { 1129 case I40E_LINK_SPEED_40GB: 1130 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024; 1131 break; 1132 case I40E_LINK_SPEED_25GB: 1133 case I40E_LINK_SPEED_20GB: 1134 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512; 1135 break; 1136 default: 1137 case I40E_LINK_SPEED_10GB: 1138 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256; 1139 break; 1140 case I40E_LINK_SPEED_1GB: 1141 case I40E_LINK_SPEED_100MB: 1142 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32; 1143 break; 1144 } 1145 1146 return divisor; 1147 } 1148 1149 /** 1150 * i40e_update_itr - update the dynamic ITR value based on statistics 1151 * @q_vector: structure containing interrupt and ring information 1152 * @rc: structure containing ring performance data 1153 * 1154 * Stores a new ITR value based on packets and byte 1155 * counts during the last interrupt. The advantage of per interrupt 1156 * computation is faster updates and more accurate ITR for the current 1157 * traffic pattern. Constants in this function were computed 1158 * based on theoretical maximum wire speed and thresholds were set based 1159 * on testing data as well as attempting to minimize response time 1160 * while increasing bulk throughput. 1161 **/ 1162 static void i40e_update_itr(struct i40e_q_vector *q_vector, 1163 struct i40e_ring_container *rc) 1164 { 1165 unsigned int avg_wire_size, packets, bytes, itr; 1166 unsigned long next_update = jiffies; 1167 1168 /* If we don't have any rings just leave ourselves set for maximum 1169 * possible latency so we take ourselves out of the equation. 1170 */ 1171 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting)) 1172 return; 1173 1174 /* For Rx we want to push the delay up and default to low latency. 1175 * for Tx we want to pull the delay down and default to high latency. 1176 */ 1177 itr = i40e_container_is_rx(q_vector, rc) ? 1178 I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY : 1179 I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY; 1180 1181 /* If we didn't update within up to 1 - 2 jiffies we can assume 1182 * that either packets are coming in so slow there hasn't been 1183 * any work, or that there is so much work that NAPI is dealing 1184 * with interrupt moderation and we don't need to do anything. 1185 */ 1186 if (time_after(next_update, rc->next_update)) 1187 goto clear_counts; 1188 1189 /* If itr_countdown is set it means we programmed an ITR within 1190 * the last 4 interrupt cycles. This has a side effect of us 1191 * potentially firing an early interrupt. In order to work around 1192 * this we need to throw out any data received for a few 1193 * interrupts following the update. 1194 */ 1195 if (q_vector->itr_countdown) { 1196 itr = rc->target_itr; 1197 goto clear_counts; 1198 } 1199 1200 packets = rc->total_packets; 1201 bytes = rc->total_bytes; 1202 1203 if (i40e_container_is_rx(q_vector, rc)) { 1204 /* If Rx there are 1 to 4 packets and bytes are less than 1205 * 9000 assume insufficient data to use bulk rate limiting 1206 * approach unless Tx is already in bulk rate limiting. We 1207 * are likely latency driven. 1208 */ 1209 if (packets && packets < 4 && bytes < 9000 && 1210 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) { 1211 itr = I40E_ITR_ADAPTIVE_LATENCY; 1212 goto adjust_by_size; 1213 } 1214 } else if (packets < 4) { 1215 /* If we have Tx and Rx ITR maxed and Tx ITR is running in 1216 * bulk mode and we are receiving 4 or fewer packets just 1217 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so 1218 * that the Rx can relax. 1219 */ 1220 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS && 1221 (q_vector->rx.target_itr & I40E_ITR_MASK) == 1222 I40E_ITR_ADAPTIVE_MAX_USECS) 1223 goto clear_counts; 1224 } else if (packets > 32) { 1225 /* If we have processed over 32 packets in a single interrupt 1226 * for Tx assume we need to switch over to "bulk" mode. 1227 */ 1228 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY; 1229 } 1230 1231 /* We have no packets to actually measure against. This means 1232 * either one of the other queues on this vector is active or 1233 * we are a Tx queue doing TSO with too high of an interrupt rate. 1234 * 1235 * Between 4 and 56 we can assume that our current interrupt delay 1236 * is only slightly too low. As such we should increase it by a small 1237 * fixed amount. 1238 */ 1239 if (packets < 56) { 1240 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC; 1241 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { 1242 itr &= I40E_ITR_ADAPTIVE_LATENCY; 1243 itr += I40E_ITR_ADAPTIVE_MAX_USECS; 1244 } 1245 goto clear_counts; 1246 } 1247 1248 if (packets <= 256) { 1249 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr); 1250 itr &= I40E_ITR_MASK; 1251 1252 /* Between 56 and 112 is our "goldilocks" zone where we are 1253 * working out "just right". Just report that our current 1254 * ITR is good for us. 1255 */ 1256 if (packets <= 112) 1257 goto clear_counts; 1258 1259 /* If packet count is 128 or greater we are likely looking 1260 * at a slight overrun of the delay we want. Try halving 1261 * our delay to see if that will cut the number of packets 1262 * in half per interrupt. 1263 */ 1264 itr /= 2; 1265 itr &= I40E_ITR_MASK; 1266 if (itr < I40E_ITR_ADAPTIVE_MIN_USECS) 1267 itr = I40E_ITR_ADAPTIVE_MIN_USECS; 1268 1269 goto clear_counts; 1270 } 1271 1272 /* The paths below assume we are dealing with a bulk ITR since 1273 * number of packets is greater than 256. We are just going to have 1274 * to compute a value and try to bring the count under control, 1275 * though for smaller packet sizes there isn't much we can do as 1276 * NAPI polling will likely be kicking in sooner rather than later. 1277 */ 1278 itr = I40E_ITR_ADAPTIVE_BULK; 1279 1280 adjust_by_size: 1281 /* If packet counts are 256 or greater we can assume we have a gross 1282 * overestimation of what the rate should be. Instead of trying to fine 1283 * tune it just use the formula below to try and dial in an exact value 1284 * give the current packet size of the frame. 1285 */ 1286 avg_wire_size = bytes / packets; 1287 1288 /* The following is a crude approximation of: 1289 * wmem_default / (size + overhead) = desired_pkts_per_int 1290 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 1291 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 1292 * 1293 * Assuming wmem_default is 212992 and overhead is 640 bytes per 1294 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 1295 * formula down to 1296 * 1297 * (170 * (size + 24)) / (size + 640) = ITR 1298 * 1299 * We first do some math on the packet size and then finally bitshift 1300 * by 8 after rounding up. We also have to account for PCIe link speed 1301 * difference as ITR scales based on this. 1302 */ 1303 if (avg_wire_size <= 60) { 1304 /* Start at 250k ints/sec */ 1305 avg_wire_size = 4096; 1306 } else if (avg_wire_size <= 380) { 1307 /* 250K ints/sec to 60K ints/sec */ 1308 avg_wire_size *= 40; 1309 avg_wire_size += 1696; 1310 } else if (avg_wire_size <= 1084) { 1311 /* 60K ints/sec to 36K ints/sec */ 1312 avg_wire_size *= 15; 1313 avg_wire_size += 11452; 1314 } else if (avg_wire_size <= 1980) { 1315 /* 36K ints/sec to 30K ints/sec */ 1316 avg_wire_size *= 5; 1317 avg_wire_size += 22420; 1318 } else { 1319 /* plateau at a limit of 30K ints/sec */ 1320 avg_wire_size = 32256; 1321 } 1322 1323 /* If we are in low latency mode halve our delay which doubles the 1324 * rate to somewhere between 100K to 16K ints/sec 1325 */ 1326 if (itr & I40E_ITR_ADAPTIVE_LATENCY) 1327 avg_wire_size /= 2; 1328 1329 /* Resultant value is 256 times larger than it needs to be. This 1330 * gives us room to adjust the value as needed to either increase 1331 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 1332 * 1333 * Use addition as we have already recorded the new latency flag 1334 * for the ITR value. 1335 */ 1336 itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) * 1337 I40E_ITR_ADAPTIVE_MIN_INC; 1338 1339 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { 1340 itr &= I40E_ITR_ADAPTIVE_LATENCY; 1341 itr += I40E_ITR_ADAPTIVE_MAX_USECS; 1342 } 1343 1344 clear_counts: 1345 /* write back value */ 1346 rc->target_itr = itr; 1347 1348 /* next update should occur within next jiffy */ 1349 rc->next_update = next_update + 1; 1350 1351 rc->total_bytes = 0; 1352 rc->total_packets = 0; 1353 } 1354 1355 static struct i40e_rx_buffer *i40e_rx_bi(struct i40e_ring *rx_ring, u32 idx) 1356 { 1357 return &rx_ring->rx_bi[idx]; 1358 } 1359 1360 /** 1361 * i40e_reuse_rx_page - page flip buffer and store it back on the ring 1362 * @rx_ring: rx descriptor ring to store buffers on 1363 * @old_buff: donor buffer to have page reused 1364 * 1365 * Synchronizes page for reuse by the adapter 1366 **/ 1367 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, 1368 struct i40e_rx_buffer *old_buff) 1369 { 1370 struct i40e_rx_buffer *new_buff; 1371 u16 nta = rx_ring->next_to_alloc; 1372 1373 new_buff = i40e_rx_bi(rx_ring, nta); 1374 1375 /* update, and store next to alloc */ 1376 nta++; 1377 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1378 1379 /* transfer page from old buffer to new buffer */ 1380 new_buff->dma = old_buff->dma; 1381 new_buff->page = old_buff->page; 1382 new_buff->page_offset = old_buff->page_offset; 1383 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1384 1385 /* clear contents of buffer_info */ 1386 old_buff->page = NULL; 1387 } 1388 1389 /** 1390 * i40e_clean_programming_status - clean the programming status descriptor 1391 * @rx_ring: the rx ring that has this descriptor 1392 * @qword0_raw: qword0 1393 * @qword1: qword1 representing status_error_len in CPU ordering 1394 * 1395 * Flow director should handle FD_FILTER_STATUS to check its filter programming 1396 * status being successful or not and take actions accordingly. FCoE should 1397 * handle its context/filter programming/invalidation status and take actions. 1398 * 1399 * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL. 1400 **/ 1401 void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw, 1402 u64 qword1) 1403 { 1404 u8 id; 1405 1406 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> 1407 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; 1408 1409 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) 1410 i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id); 1411 } 1412 1413 /** 1414 * i40e_setup_tx_descriptors - Allocate the Tx descriptors 1415 * @tx_ring: the tx ring to set up 1416 * 1417 * Return 0 on success, negative on error 1418 **/ 1419 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) 1420 { 1421 struct device *dev = tx_ring->dev; 1422 int bi_size; 1423 1424 if (!dev) 1425 return -ENOMEM; 1426 1427 /* warn if we are about to overwrite the pointer */ 1428 WARN_ON(tx_ring->tx_bi); 1429 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 1430 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); 1431 if (!tx_ring->tx_bi) 1432 goto err; 1433 1434 u64_stats_init(&tx_ring->syncp); 1435 1436 /* round up to nearest 4K */ 1437 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); 1438 /* add u32 for head writeback, align after this takes care of 1439 * guaranteeing this is at least one cache line in size 1440 */ 1441 tx_ring->size += sizeof(u32); 1442 tx_ring->size = ALIGN(tx_ring->size, 4096); 1443 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 1444 &tx_ring->dma, GFP_KERNEL); 1445 if (!tx_ring->desc) { 1446 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 1447 tx_ring->size); 1448 goto err; 1449 } 1450 1451 tx_ring->next_to_use = 0; 1452 tx_ring->next_to_clean = 0; 1453 tx_ring->tx_stats.prev_pkt_ctr = -1; 1454 return 0; 1455 1456 err: 1457 kfree(tx_ring->tx_bi); 1458 tx_ring->tx_bi = NULL; 1459 return -ENOMEM; 1460 } 1461 1462 static void i40e_clear_rx_bi(struct i40e_ring *rx_ring) 1463 { 1464 memset(rx_ring->rx_bi, 0, sizeof(*rx_ring->rx_bi) * rx_ring->count); 1465 } 1466 1467 /** 1468 * i40e_clean_rx_ring - Free Rx buffers 1469 * @rx_ring: ring to be cleaned 1470 **/ 1471 void i40e_clean_rx_ring(struct i40e_ring *rx_ring) 1472 { 1473 u16 i; 1474 1475 /* ring already cleared, nothing to do */ 1476 if (!rx_ring->rx_bi) 1477 return; 1478 1479 if (rx_ring->xsk_pool) { 1480 i40e_xsk_clean_rx_ring(rx_ring); 1481 goto skip_free; 1482 } 1483 1484 /* Free all the Rx ring sk_buffs */ 1485 for (i = 0; i < rx_ring->count; i++) { 1486 struct i40e_rx_buffer *rx_bi = i40e_rx_bi(rx_ring, i); 1487 1488 if (!rx_bi->page) 1489 continue; 1490 1491 /* Invalidate cache lines that may have been written to by 1492 * device so that we avoid corrupting memory. 1493 */ 1494 dma_sync_single_range_for_cpu(rx_ring->dev, 1495 rx_bi->dma, 1496 rx_bi->page_offset, 1497 rx_ring->rx_buf_len, 1498 DMA_FROM_DEVICE); 1499 1500 /* free resources associated with mapping */ 1501 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, 1502 i40e_rx_pg_size(rx_ring), 1503 DMA_FROM_DEVICE, 1504 I40E_RX_DMA_ATTR); 1505 1506 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); 1507 1508 rx_bi->page = NULL; 1509 rx_bi->page_offset = 0; 1510 } 1511 1512 skip_free: 1513 if (rx_ring->xsk_pool) 1514 i40e_clear_rx_bi_zc(rx_ring); 1515 else 1516 i40e_clear_rx_bi(rx_ring); 1517 1518 /* Zero out the descriptor ring */ 1519 memset(rx_ring->desc, 0, rx_ring->size); 1520 1521 rx_ring->next_to_alloc = 0; 1522 rx_ring->next_to_clean = 0; 1523 rx_ring->next_to_process = 0; 1524 rx_ring->next_to_use = 0; 1525 } 1526 1527 /** 1528 * i40e_free_rx_resources - Free Rx resources 1529 * @rx_ring: ring to clean the resources from 1530 * 1531 * Free all receive software resources 1532 **/ 1533 void i40e_free_rx_resources(struct i40e_ring *rx_ring) 1534 { 1535 i40e_clean_rx_ring(rx_ring); 1536 if (rx_ring->vsi->type == I40E_VSI_MAIN) 1537 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 1538 rx_ring->xdp_prog = NULL; 1539 kfree(rx_ring->rx_bi); 1540 rx_ring->rx_bi = NULL; 1541 1542 if (rx_ring->desc) { 1543 dma_free_coherent(rx_ring->dev, rx_ring->size, 1544 rx_ring->desc, rx_ring->dma); 1545 rx_ring->desc = NULL; 1546 } 1547 } 1548 1549 /** 1550 * i40e_setup_rx_descriptors - Allocate Rx descriptors 1551 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1552 * 1553 * Returns 0 on success, negative on failure 1554 **/ 1555 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) 1556 { 1557 struct device *dev = rx_ring->dev; 1558 int err; 1559 1560 u64_stats_init(&rx_ring->syncp); 1561 1562 /* Round up to nearest 4K */ 1563 rx_ring->size = rx_ring->count * sizeof(union i40e_rx_desc); 1564 rx_ring->size = ALIGN(rx_ring->size, 4096); 1565 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 1566 &rx_ring->dma, GFP_KERNEL); 1567 1568 if (!rx_ring->desc) { 1569 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 1570 rx_ring->size); 1571 return -ENOMEM; 1572 } 1573 1574 rx_ring->next_to_alloc = 0; 1575 rx_ring->next_to_clean = 0; 1576 rx_ring->next_to_process = 0; 1577 rx_ring->next_to_use = 0; 1578 1579 /* XDP RX-queue info only needed for RX rings exposed to XDP */ 1580 if (rx_ring->vsi->type == I40E_VSI_MAIN) { 1581 err = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 1582 rx_ring->queue_index, rx_ring->q_vector->napi.napi_id); 1583 if (err < 0) 1584 return err; 1585 } 1586 1587 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog; 1588 1589 rx_ring->rx_bi = 1590 kcalloc(rx_ring->count, sizeof(*rx_ring->rx_bi), GFP_KERNEL); 1591 if (!rx_ring->rx_bi) 1592 return -ENOMEM; 1593 1594 return 0; 1595 } 1596 1597 /** 1598 * i40e_release_rx_desc - Store the new tail and head values 1599 * @rx_ring: ring to bump 1600 * @val: new head index 1601 **/ 1602 void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) 1603 { 1604 rx_ring->next_to_use = val; 1605 1606 /* update next to alloc since we have filled the ring */ 1607 rx_ring->next_to_alloc = val; 1608 1609 /* Force memory writes to complete before letting h/w 1610 * know there are new descriptors to fetch. (Only 1611 * applicable for weak-ordered memory model archs, 1612 * such as IA-64). 1613 */ 1614 wmb(); 1615 writel(val, rx_ring->tail); 1616 } 1617 1618 #if (PAGE_SIZE >= 8192) 1619 static unsigned int i40e_rx_frame_truesize(struct i40e_ring *rx_ring, 1620 unsigned int size) 1621 { 1622 unsigned int truesize; 1623 1624 truesize = rx_ring->rx_offset ? 1625 SKB_DATA_ALIGN(size + rx_ring->rx_offset) + 1626 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 1627 SKB_DATA_ALIGN(size); 1628 return truesize; 1629 } 1630 #endif 1631 1632 /** 1633 * i40e_alloc_mapped_page - recycle or make a new page 1634 * @rx_ring: ring to use 1635 * @bi: rx_buffer struct to modify 1636 * 1637 * Returns true if the page was successfully allocated or 1638 * reused. 1639 **/ 1640 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, 1641 struct i40e_rx_buffer *bi) 1642 { 1643 struct page *page = bi->page; 1644 dma_addr_t dma; 1645 1646 /* since we are recycling buffers we should seldom need to alloc */ 1647 if (likely(page)) { 1648 rx_ring->rx_stats.page_reuse_count++; 1649 return true; 1650 } 1651 1652 /* alloc new page for storage */ 1653 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring)); 1654 if (unlikely(!page)) { 1655 rx_ring->rx_stats.alloc_page_failed++; 1656 return false; 1657 } 1658 1659 rx_ring->rx_stats.page_alloc_count++; 1660 1661 /* map page for use */ 1662 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1663 i40e_rx_pg_size(rx_ring), 1664 DMA_FROM_DEVICE, 1665 I40E_RX_DMA_ATTR); 1666 1667 /* if mapping failed free memory back to system since 1668 * there isn't much point in holding memory we can't use 1669 */ 1670 if (dma_mapping_error(rx_ring->dev, dma)) { 1671 __free_pages(page, i40e_rx_pg_order(rx_ring)); 1672 rx_ring->rx_stats.alloc_page_failed++; 1673 return false; 1674 } 1675 1676 bi->dma = dma; 1677 bi->page = page; 1678 bi->page_offset = rx_ring->rx_offset; 1679 page_ref_add(page, USHRT_MAX - 1); 1680 bi->pagecnt_bias = USHRT_MAX; 1681 1682 return true; 1683 } 1684 1685 /** 1686 * i40e_alloc_rx_buffers - Replace used receive buffers 1687 * @rx_ring: ring to place buffers on 1688 * @cleaned_count: number of buffers to replace 1689 * 1690 * Returns false if all allocations were successful, true if any fail 1691 **/ 1692 bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) 1693 { 1694 u16 ntu = rx_ring->next_to_use; 1695 union i40e_rx_desc *rx_desc; 1696 struct i40e_rx_buffer *bi; 1697 1698 /* do nothing if no valid netdev defined */ 1699 if (!rx_ring->netdev || !cleaned_count) 1700 return false; 1701 1702 rx_desc = I40E_RX_DESC(rx_ring, ntu); 1703 bi = i40e_rx_bi(rx_ring, ntu); 1704 1705 do { 1706 if (!i40e_alloc_mapped_page(rx_ring, bi)) 1707 goto no_buffers; 1708 1709 /* sync the buffer for use by the device */ 1710 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1711 bi->page_offset, 1712 rx_ring->rx_buf_len, 1713 DMA_FROM_DEVICE); 1714 1715 /* Refresh the desc even if buffer_addrs didn't change 1716 * because each write-back erases this info. 1717 */ 1718 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1719 1720 rx_desc++; 1721 bi++; 1722 ntu++; 1723 if (unlikely(ntu == rx_ring->count)) { 1724 rx_desc = I40E_RX_DESC(rx_ring, 0); 1725 bi = i40e_rx_bi(rx_ring, 0); 1726 ntu = 0; 1727 } 1728 1729 /* clear the status bits for the next_to_use descriptor */ 1730 rx_desc->wb.qword1.status_error_len = 0; 1731 1732 cleaned_count--; 1733 } while (cleaned_count); 1734 1735 if (rx_ring->next_to_use != ntu) 1736 i40e_release_rx_desc(rx_ring, ntu); 1737 1738 return false; 1739 1740 no_buffers: 1741 if (rx_ring->next_to_use != ntu) 1742 i40e_release_rx_desc(rx_ring, ntu); 1743 1744 /* make sure to come back via polling to try again after 1745 * allocation failure 1746 */ 1747 return true; 1748 } 1749 1750 /** 1751 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum 1752 * @vsi: the VSI we care about 1753 * @skb: skb currently being received and modified 1754 * @rx_desc: the receive descriptor 1755 **/ 1756 static inline void i40e_rx_checksum(struct i40e_vsi *vsi, 1757 struct sk_buff *skb, 1758 union i40e_rx_desc *rx_desc) 1759 { 1760 struct i40e_rx_ptype_decoded decoded; 1761 u32 rx_error, rx_status; 1762 bool ipv4, ipv6; 1763 u8 ptype; 1764 u64 qword; 1765 1766 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1767 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; 1768 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> 1769 I40E_RXD_QW1_ERROR_SHIFT; 1770 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1771 I40E_RXD_QW1_STATUS_SHIFT; 1772 decoded = decode_rx_desc_ptype(ptype); 1773 1774 skb->ip_summed = CHECKSUM_NONE; 1775 1776 skb_checksum_none_assert(skb); 1777 1778 /* Rx csum enabled and ip headers found? */ 1779 if (!(vsi->netdev->features & NETIF_F_RXCSUM)) 1780 return; 1781 1782 /* did the hardware decode the packet and checksum? */ 1783 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) 1784 return; 1785 1786 /* both known and outer_ip must be set for the below code to work */ 1787 if (!(decoded.known && decoded.outer_ip)) 1788 return; 1789 1790 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && 1791 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); 1792 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && 1793 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); 1794 1795 if (ipv4 && 1796 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | 1797 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) 1798 goto checksum_fail; 1799 1800 /* likely incorrect csum if alternate IP extension headers found */ 1801 if (ipv6 && 1802 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) 1803 /* don't increment checksum err here, non-fatal err */ 1804 return; 1805 1806 /* there was some L4 error, count error and punt packet to the stack */ 1807 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) 1808 goto checksum_fail; 1809 1810 /* handle packets that were not able to be checksummed due 1811 * to arrival speed, in this case the stack can compute 1812 * the csum. 1813 */ 1814 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) 1815 return; 1816 1817 /* If there is an outer header present that might contain a checksum 1818 * we need to bump the checksum level by 1 to reflect the fact that 1819 * we are indicating we validated the inner checksum. 1820 */ 1821 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT) 1822 skb->csum_level = 1; 1823 1824 /* Only report checksum unnecessary for TCP, UDP, or SCTP */ 1825 switch (decoded.inner_prot) { 1826 case I40E_RX_PTYPE_INNER_PROT_TCP: 1827 case I40E_RX_PTYPE_INNER_PROT_UDP: 1828 case I40E_RX_PTYPE_INNER_PROT_SCTP: 1829 skb->ip_summed = CHECKSUM_UNNECESSARY; 1830 fallthrough; 1831 default: 1832 break; 1833 } 1834 1835 return; 1836 1837 checksum_fail: 1838 vsi->back->hw_csum_rx_error++; 1839 } 1840 1841 /** 1842 * i40e_ptype_to_htype - get a hash type 1843 * @ptype: the ptype value from the descriptor 1844 * 1845 * Returns a hash type to be used by skb_set_hash 1846 **/ 1847 static inline int i40e_ptype_to_htype(u8 ptype) 1848 { 1849 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); 1850 1851 if (!decoded.known) 1852 return PKT_HASH_TYPE_NONE; 1853 1854 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1855 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) 1856 return PKT_HASH_TYPE_L4; 1857 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1858 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) 1859 return PKT_HASH_TYPE_L3; 1860 else 1861 return PKT_HASH_TYPE_L2; 1862 } 1863 1864 /** 1865 * i40e_rx_hash - set the hash value in the skb 1866 * @ring: descriptor ring 1867 * @rx_desc: specific descriptor 1868 * @skb: skb currently being received and modified 1869 * @rx_ptype: Rx packet type 1870 **/ 1871 static inline void i40e_rx_hash(struct i40e_ring *ring, 1872 union i40e_rx_desc *rx_desc, 1873 struct sk_buff *skb, 1874 u8 rx_ptype) 1875 { 1876 u32 hash; 1877 const __le64 rss_mask = 1878 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << 1879 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); 1880 1881 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1882 return; 1883 1884 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { 1885 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); 1886 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); 1887 } 1888 } 1889 1890 /** 1891 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor 1892 * @rx_ring: rx descriptor ring packet is being transacted on 1893 * @rx_desc: pointer to the EOP Rx descriptor 1894 * @skb: pointer to current skb being populated 1895 * 1896 * This function checks the ring, descriptor, and packet information in 1897 * order to populate the hash, checksum, VLAN, protocol, and 1898 * other fields within the skb. 1899 **/ 1900 void i40e_process_skb_fields(struct i40e_ring *rx_ring, 1901 union i40e_rx_desc *rx_desc, struct sk_buff *skb) 1902 { 1903 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1904 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1905 I40E_RXD_QW1_STATUS_SHIFT; 1906 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK; 1907 u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> 1908 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT; 1909 u8 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> 1910 I40E_RXD_QW1_PTYPE_SHIFT; 1911 1912 if (unlikely(tsynvalid)) 1913 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn); 1914 1915 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); 1916 1917 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); 1918 1919 skb_record_rx_queue(skb, rx_ring->queue_index); 1920 1921 if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) { 1922 __le16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1; 1923 1924 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1925 le16_to_cpu(vlan_tag)); 1926 } 1927 1928 /* modifies the skb - consumes the enet header */ 1929 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1930 } 1931 1932 /** 1933 * i40e_cleanup_headers - Correct empty headers 1934 * @rx_ring: rx descriptor ring packet is being transacted on 1935 * @skb: pointer to current skb being fixed 1936 * @rx_desc: pointer to the EOP Rx descriptor 1937 * 1938 * In addition if skb is not at least 60 bytes we need to pad it so that 1939 * it is large enough to qualify as a valid Ethernet frame. 1940 * 1941 * Returns true if an error was encountered and skb was freed. 1942 **/ 1943 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb, 1944 union i40e_rx_desc *rx_desc) 1945 1946 { 1947 /* ERR_MASK will only have valid bits if EOP set, and 1948 * what we are doing here is actually checking 1949 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in 1950 * the error field 1951 */ 1952 if (unlikely(i40e_test_staterr(rx_desc, 1953 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { 1954 dev_kfree_skb_any(skb); 1955 return true; 1956 } 1957 1958 /* if eth_skb_pad returns an error the skb was freed */ 1959 if (eth_skb_pad(skb)) 1960 return true; 1961 1962 return false; 1963 } 1964 1965 /** 1966 * i40e_can_reuse_rx_page - Determine if page can be reused for another Rx 1967 * @rx_buffer: buffer containing the page 1968 * @rx_stats: rx stats structure for the rx ring 1969 * 1970 * If page is reusable, we have a green light for calling i40e_reuse_rx_page, 1971 * which will assign the current buffer to the buffer that next_to_alloc is 1972 * pointing to; otherwise, the DMA mapping needs to be destroyed and 1973 * page freed. 1974 * 1975 * rx_stats will be updated to indicate whether the page was waived 1976 * or busy if it could not be reused. 1977 */ 1978 static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer, 1979 struct i40e_rx_queue_stats *rx_stats) 1980 { 1981 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1982 struct page *page = rx_buffer->page; 1983 1984 /* Is any reuse possible? */ 1985 if (!dev_page_is_reusable(page)) { 1986 rx_stats->page_waive_count++; 1987 return false; 1988 } 1989 1990 #if (PAGE_SIZE < 8192) 1991 /* if we are only owner of page we can reuse it */ 1992 if (unlikely((rx_buffer->page_count - pagecnt_bias) > 1)) { 1993 rx_stats->page_busy_count++; 1994 return false; 1995 } 1996 #else 1997 #define I40E_LAST_OFFSET \ 1998 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048) 1999 if (rx_buffer->page_offset > I40E_LAST_OFFSET) { 2000 rx_stats->page_busy_count++; 2001 return false; 2002 } 2003 #endif 2004 2005 /* If we have drained the page fragment pool we need to update 2006 * the pagecnt_bias and page count so that we fully restock the 2007 * number of references the driver holds. 2008 */ 2009 if (unlikely(pagecnt_bias == 1)) { 2010 page_ref_add(page, USHRT_MAX - 1); 2011 rx_buffer->pagecnt_bias = USHRT_MAX; 2012 } 2013 2014 return true; 2015 } 2016 2017 /** 2018 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region 2019 * @rx_buffer: Rx buffer to adjust 2020 * @truesize: Size of adjustment 2021 **/ 2022 static void i40e_rx_buffer_flip(struct i40e_rx_buffer *rx_buffer, 2023 unsigned int truesize) 2024 { 2025 #if (PAGE_SIZE < 8192) 2026 rx_buffer->page_offset ^= truesize; 2027 #else 2028 rx_buffer->page_offset += truesize; 2029 #endif 2030 } 2031 2032 /** 2033 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use 2034 * @rx_ring: rx descriptor ring to transact packets on 2035 * @size: size of buffer to add to skb 2036 * 2037 * This function will pull an Rx buffer from the ring and synchronize it 2038 * for use by the CPU. 2039 */ 2040 static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring, 2041 const unsigned int size) 2042 { 2043 struct i40e_rx_buffer *rx_buffer; 2044 2045 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_process); 2046 rx_buffer->page_count = 2047 #if (PAGE_SIZE < 8192) 2048 page_count(rx_buffer->page); 2049 #else 2050 0; 2051 #endif 2052 prefetch_page_address(rx_buffer->page); 2053 2054 /* we are reusing so sync this buffer for CPU use */ 2055 dma_sync_single_range_for_cpu(rx_ring->dev, 2056 rx_buffer->dma, 2057 rx_buffer->page_offset, 2058 size, 2059 DMA_FROM_DEVICE); 2060 2061 /* We have pulled a buffer for use, so decrement pagecnt_bias */ 2062 rx_buffer->pagecnt_bias--; 2063 2064 return rx_buffer; 2065 } 2066 2067 /** 2068 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free 2069 * @rx_ring: rx descriptor ring to transact packets on 2070 * @rx_buffer: rx buffer to pull data from 2071 * 2072 * This function will clean up the contents of the rx_buffer. It will 2073 * either recycle the buffer or unmap it and free the associated resources. 2074 */ 2075 static void i40e_put_rx_buffer(struct i40e_ring *rx_ring, 2076 struct i40e_rx_buffer *rx_buffer) 2077 { 2078 if (i40e_can_reuse_rx_page(rx_buffer, &rx_ring->rx_stats)) { 2079 /* hand second half of page back to the ring */ 2080 i40e_reuse_rx_page(rx_ring, rx_buffer); 2081 } else { 2082 /* we are not reusing the buffer so unmap it */ 2083 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2084 i40e_rx_pg_size(rx_ring), 2085 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); 2086 __page_frag_cache_drain(rx_buffer->page, 2087 rx_buffer->pagecnt_bias); 2088 /* clear contents of buffer_info */ 2089 rx_buffer->page = NULL; 2090 } 2091 } 2092 2093 /** 2094 * i40e_process_rx_buffs- Processing of buffers post XDP prog or on error 2095 * @rx_ring: Rx descriptor ring to transact packets on 2096 * @xdp_res: Result of the XDP program 2097 * @xdp: xdp_buff pointing to the data 2098 **/ 2099 static void i40e_process_rx_buffs(struct i40e_ring *rx_ring, int xdp_res, 2100 struct xdp_buff *xdp) 2101 { 2102 u32 next = rx_ring->next_to_clean; 2103 struct i40e_rx_buffer *rx_buffer; 2104 2105 xdp->flags = 0; 2106 2107 while (1) { 2108 rx_buffer = i40e_rx_bi(rx_ring, next); 2109 if (++next == rx_ring->count) 2110 next = 0; 2111 2112 if (!rx_buffer->page) 2113 continue; 2114 2115 if (xdp_res == I40E_XDP_CONSUMED) 2116 rx_buffer->pagecnt_bias++; 2117 else 2118 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2119 2120 /* EOP buffer will be put in i40e_clean_rx_irq() */ 2121 if (next == rx_ring->next_to_process) 2122 return; 2123 2124 i40e_put_rx_buffer(rx_ring, rx_buffer); 2125 } 2126 } 2127 2128 /** 2129 * i40e_construct_skb - Allocate skb and populate it 2130 * @rx_ring: rx descriptor ring to transact packets on 2131 * @xdp: xdp_buff pointing to the data 2132 * @nr_frags: number of buffers for the packet 2133 * 2134 * This function allocates an skb. It then populates it with the page 2135 * data from the current receive descriptor, taking care to set up the 2136 * skb correctly. 2137 */ 2138 static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring, 2139 struct xdp_buff *xdp, 2140 u32 nr_frags) 2141 { 2142 unsigned int size = xdp->data_end - xdp->data; 2143 struct i40e_rx_buffer *rx_buffer; 2144 unsigned int headlen; 2145 struct sk_buff *skb; 2146 2147 /* prefetch first cache line of first page */ 2148 net_prefetch(xdp->data); 2149 2150 /* Note, we get here by enabling legacy-rx via: 2151 * 2152 * ethtool --set-priv-flags <dev> legacy-rx on 2153 * 2154 * In this mode, we currently get 0 extra XDP headroom as 2155 * opposed to having legacy-rx off, where we process XDP 2156 * packets going to stack via i40e_build_skb(). The latter 2157 * provides us currently with 192 bytes of headroom. 2158 * 2159 * For i40e_construct_skb() mode it means that the 2160 * xdp->data_meta will always point to xdp->data, since 2161 * the helper cannot expand the head. Should this ever 2162 * change in future for legacy-rx mode on, then lets also 2163 * add xdp->data_meta handling here. 2164 */ 2165 2166 /* allocate a skb to store the frags */ 2167 skb = __napi_alloc_skb(&rx_ring->q_vector->napi, 2168 I40E_RX_HDR_SIZE, 2169 GFP_ATOMIC | __GFP_NOWARN); 2170 if (unlikely(!skb)) 2171 return NULL; 2172 2173 /* Determine available headroom for copy */ 2174 headlen = size; 2175 if (headlen > I40E_RX_HDR_SIZE) 2176 headlen = eth_get_headlen(skb->dev, xdp->data, 2177 I40E_RX_HDR_SIZE); 2178 2179 /* align pull length to size of long to optimize memcpy performance */ 2180 memcpy(__skb_put(skb, headlen), xdp->data, 2181 ALIGN(headlen, sizeof(long))); 2182 2183 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean); 2184 /* update all of the pointers */ 2185 size -= headlen; 2186 if (size) { 2187 if (unlikely(nr_frags >= MAX_SKB_FRAGS)) { 2188 dev_kfree_skb(skb); 2189 return NULL; 2190 } 2191 skb_add_rx_frag(skb, 0, rx_buffer->page, 2192 rx_buffer->page_offset + headlen, 2193 size, xdp->frame_sz); 2194 /* buffer is used by skb, update page_offset */ 2195 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2196 } else { 2197 /* buffer is unused, reset bias back to rx_buffer */ 2198 rx_buffer->pagecnt_bias++; 2199 } 2200 2201 if (unlikely(xdp_buff_has_frags(xdp))) { 2202 struct skb_shared_info *sinfo, *skinfo = skb_shinfo(skb); 2203 2204 sinfo = xdp_get_shared_info_from_buff(xdp); 2205 memcpy(&skinfo->frags[skinfo->nr_frags], &sinfo->frags[0], 2206 sizeof(skb_frag_t) * nr_frags); 2207 2208 xdp_update_skb_shared_info(skb, skinfo->nr_frags + nr_frags, 2209 sinfo->xdp_frags_size, 2210 nr_frags * xdp->frame_sz, 2211 xdp_buff_is_frag_pfmemalloc(xdp)); 2212 2213 /* First buffer has already been processed, so bump ntc */ 2214 if (++rx_ring->next_to_clean == rx_ring->count) 2215 rx_ring->next_to_clean = 0; 2216 2217 i40e_process_rx_buffs(rx_ring, I40E_XDP_PASS, xdp); 2218 } 2219 2220 return skb; 2221 } 2222 2223 /** 2224 * i40e_build_skb - Build skb around an existing buffer 2225 * @rx_ring: Rx descriptor ring to transact packets on 2226 * @xdp: xdp_buff pointing to the data 2227 * @nr_frags: number of buffers for the packet 2228 * 2229 * This function builds an skb around an existing Rx buffer, taking care 2230 * to set up the skb correctly and avoid any memcpy overhead. 2231 */ 2232 static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring, 2233 struct xdp_buff *xdp, 2234 u32 nr_frags) 2235 { 2236 unsigned int metasize = xdp->data - xdp->data_meta; 2237 struct sk_buff *skb; 2238 2239 /* Prefetch first cache line of first page. If xdp->data_meta 2240 * is unused, this points exactly as xdp->data, otherwise we 2241 * likely have a consumer accessing first few bytes of meta 2242 * data, and then actual data. 2243 */ 2244 net_prefetch(xdp->data_meta); 2245 2246 /* build an skb around the page buffer */ 2247 skb = napi_build_skb(xdp->data_hard_start, xdp->frame_sz); 2248 if (unlikely(!skb)) 2249 return NULL; 2250 2251 /* update pointers within the skb to store the data */ 2252 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2253 __skb_put(skb, xdp->data_end - xdp->data); 2254 if (metasize) 2255 skb_metadata_set(skb, metasize); 2256 2257 if (unlikely(xdp_buff_has_frags(xdp))) { 2258 struct skb_shared_info *sinfo; 2259 2260 sinfo = xdp_get_shared_info_from_buff(xdp); 2261 xdp_update_skb_shared_info(skb, nr_frags, 2262 sinfo->xdp_frags_size, 2263 nr_frags * xdp->frame_sz, 2264 xdp_buff_is_frag_pfmemalloc(xdp)); 2265 2266 i40e_process_rx_buffs(rx_ring, I40E_XDP_PASS, xdp); 2267 } else { 2268 struct i40e_rx_buffer *rx_buffer; 2269 2270 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean); 2271 /* buffer is used by skb, update page_offset */ 2272 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2273 } 2274 2275 return skb; 2276 } 2277 2278 /** 2279 * i40e_is_non_eop - process handling of non-EOP buffers 2280 * @rx_ring: Rx ring being processed 2281 * @rx_desc: Rx descriptor for current buffer 2282 * 2283 * If the buffer is an EOP buffer, this function exits returning false, 2284 * otherwise return true indicating that this is in fact a non-EOP buffer. 2285 */ 2286 bool i40e_is_non_eop(struct i40e_ring *rx_ring, 2287 union i40e_rx_desc *rx_desc) 2288 { 2289 /* if we are the last buffer then there is nothing else to do */ 2290 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) 2291 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) 2292 return false; 2293 2294 rx_ring->rx_stats.non_eop_descs++; 2295 2296 return true; 2297 } 2298 2299 static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf, 2300 struct i40e_ring *xdp_ring); 2301 2302 int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring) 2303 { 2304 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2305 2306 if (unlikely(!xdpf)) 2307 return I40E_XDP_CONSUMED; 2308 2309 return i40e_xmit_xdp_ring(xdpf, xdp_ring); 2310 } 2311 2312 /** 2313 * i40e_run_xdp - run an XDP program 2314 * @rx_ring: Rx ring being processed 2315 * @xdp: XDP buffer containing the frame 2316 * @xdp_prog: XDP program to run 2317 **/ 2318 static int i40e_run_xdp(struct i40e_ring *rx_ring, struct xdp_buff *xdp, struct bpf_prog *xdp_prog) 2319 { 2320 int err, result = I40E_XDP_PASS; 2321 struct i40e_ring *xdp_ring; 2322 u32 act; 2323 2324 if (!xdp_prog) 2325 goto xdp_out; 2326 2327 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2328 2329 act = bpf_prog_run_xdp(xdp_prog, xdp); 2330 switch (act) { 2331 case XDP_PASS: 2332 break; 2333 case XDP_TX: 2334 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index]; 2335 result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring); 2336 if (result == I40E_XDP_CONSUMED) 2337 goto out_failure; 2338 break; 2339 case XDP_REDIRECT: 2340 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog); 2341 if (err) 2342 goto out_failure; 2343 result = I40E_XDP_REDIR; 2344 break; 2345 default: 2346 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act); 2347 fallthrough; 2348 case XDP_ABORTED: 2349 out_failure: 2350 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2351 fallthrough; /* handle aborts by dropping packet */ 2352 case XDP_DROP: 2353 result = I40E_XDP_CONSUMED; 2354 break; 2355 } 2356 xdp_out: 2357 return result; 2358 } 2359 2360 /** 2361 * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register 2362 * @xdp_ring: XDP Tx ring 2363 * 2364 * This function updates the XDP Tx ring tail register. 2365 **/ 2366 void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring) 2367 { 2368 /* Force memory writes to complete before letting h/w 2369 * know there are new descriptors to fetch. 2370 */ 2371 wmb(); 2372 writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail); 2373 } 2374 2375 /** 2376 * i40e_update_rx_stats - Update Rx ring statistics 2377 * @rx_ring: rx descriptor ring 2378 * @total_rx_bytes: number of bytes received 2379 * @total_rx_packets: number of packets received 2380 * 2381 * This function updates the Rx ring statistics. 2382 **/ 2383 void i40e_update_rx_stats(struct i40e_ring *rx_ring, 2384 unsigned int total_rx_bytes, 2385 unsigned int total_rx_packets) 2386 { 2387 u64_stats_update_begin(&rx_ring->syncp); 2388 rx_ring->stats.packets += total_rx_packets; 2389 rx_ring->stats.bytes += total_rx_bytes; 2390 u64_stats_update_end(&rx_ring->syncp); 2391 rx_ring->q_vector->rx.total_packets += total_rx_packets; 2392 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 2393 } 2394 2395 /** 2396 * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map 2397 * @rx_ring: Rx ring 2398 * @xdp_res: Result of the receive batch 2399 * 2400 * This function bumps XDP Tx tail and/or flush redirect map, and 2401 * should be called when a batch of packets has been processed in the 2402 * napi loop. 2403 **/ 2404 void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res) 2405 { 2406 if (xdp_res & I40E_XDP_REDIR) 2407 xdp_do_flush(); 2408 2409 if (xdp_res & I40E_XDP_TX) { 2410 struct i40e_ring *xdp_ring = 2411 rx_ring->vsi->xdp_rings[rx_ring->queue_index]; 2412 2413 i40e_xdp_ring_update_tail(xdp_ring); 2414 } 2415 } 2416 2417 /** 2418 * i40e_inc_ntp: Advance the next_to_process index 2419 * @rx_ring: Rx ring 2420 **/ 2421 static void i40e_inc_ntp(struct i40e_ring *rx_ring) 2422 { 2423 u32 ntp = rx_ring->next_to_process + 1; 2424 2425 ntp = (ntp < rx_ring->count) ? ntp : 0; 2426 rx_ring->next_to_process = ntp; 2427 prefetch(I40E_RX_DESC(rx_ring, ntp)); 2428 } 2429 2430 /** 2431 * i40e_add_xdp_frag: Add a frag to xdp_buff 2432 * @xdp: xdp_buff pointing to the data 2433 * @nr_frags: return number of buffers for the packet 2434 * @rx_buffer: rx_buffer holding data of the current frag 2435 * @size: size of data of current frag 2436 */ 2437 static int i40e_add_xdp_frag(struct xdp_buff *xdp, u32 *nr_frags, 2438 struct i40e_rx_buffer *rx_buffer, u32 size) 2439 { 2440 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2441 2442 if (!xdp_buff_has_frags(xdp)) { 2443 sinfo->nr_frags = 0; 2444 sinfo->xdp_frags_size = 0; 2445 xdp_buff_set_frags_flag(xdp); 2446 } else if (unlikely(sinfo->nr_frags >= MAX_SKB_FRAGS)) { 2447 /* Overflowing packet: All frags need to be dropped */ 2448 return -ENOMEM; 2449 } 2450 2451 __skb_fill_page_desc_noacc(sinfo, sinfo->nr_frags++, rx_buffer->page, 2452 rx_buffer->page_offset, size); 2453 2454 sinfo->xdp_frags_size += size; 2455 2456 if (page_is_pfmemalloc(rx_buffer->page)) 2457 xdp_buff_set_frag_pfmemalloc(xdp); 2458 *nr_frags = sinfo->nr_frags; 2459 2460 return 0; 2461 } 2462 2463 /** 2464 * i40e_consume_xdp_buff - Consume all the buffers of the packet and update ntc 2465 * @rx_ring: rx descriptor ring to transact packets on 2466 * @xdp: xdp_buff pointing to the data 2467 * @rx_buffer: rx_buffer of eop desc 2468 */ 2469 static void i40e_consume_xdp_buff(struct i40e_ring *rx_ring, 2470 struct xdp_buff *xdp, 2471 struct i40e_rx_buffer *rx_buffer) 2472 { 2473 i40e_process_rx_buffs(rx_ring, I40E_XDP_CONSUMED, xdp); 2474 i40e_put_rx_buffer(rx_ring, rx_buffer); 2475 rx_ring->next_to_clean = rx_ring->next_to_process; 2476 xdp->data = NULL; 2477 } 2478 2479 /** 2480 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2481 * @rx_ring: rx descriptor ring to transact packets on 2482 * @budget: Total limit on number of packets to process 2483 * @rx_cleaned: Out parameter of the number of packets processed 2484 * 2485 * This function provides a "bounce buffer" approach to Rx interrupt 2486 * processing. The advantage to this is that on systems that have 2487 * expensive overhead for IOMMU access this provides a means of avoiding 2488 * it by maintaining the mapping of the page to the system. 2489 * 2490 * Returns amount of work completed 2491 **/ 2492 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget, 2493 unsigned int *rx_cleaned) 2494 { 2495 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2496 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); 2497 u16 clean_threshold = rx_ring->count / 2; 2498 unsigned int offset = rx_ring->rx_offset; 2499 struct xdp_buff *xdp = &rx_ring->xdp; 2500 unsigned int xdp_xmit = 0; 2501 struct bpf_prog *xdp_prog; 2502 bool failure = false; 2503 int xdp_res = 0; 2504 2505 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2506 2507 while (likely(total_rx_packets < (unsigned int)budget)) { 2508 u16 ntp = rx_ring->next_to_process; 2509 struct i40e_rx_buffer *rx_buffer; 2510 union i40e_rx_desc *rx_desc; 2511 struct sk_buff *skb; 2512 unsigned int size; 2513 u32 nfrags = 0; 2514 bool neop; 2515 u64 qword; 2516 2517 /* return some buffers to hardware, one at a time is too slow */ 2518 if (cleaned_count >= clean_threshold) { 2519 failure = failure || 2520 i40e_alloc_rx_buffers(rx_ring, cleaned_count); 2521 cleaned_count = 0; 2522 } 2523 2524 rx_desc = I40E_RX_DESC(rx_ring, ntp); 2525 2526 /* status_error_len will always be zero for unused descriptors 2527 * because it's cleared in cleanup, and overlaps with hdr_addr 2528 * which is always zero because packet split isn't used, if the 2529 * hardware wrote DD then the length will be non-zero 2530 */ 2531 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 2532 2533 /* This memory barrier is needed to keep us from reading 2534 * any other fields out of the rx_desc until we have 2535 * verified the descriptor has been written back. 2536 */ 2537 dma_rmb(); 2538 2539 if (i40e_rx_is_programming_status(qword)) { 2540 i40e_clean_programming_status(rx_ring, 2541 rx_desc->raw.qword[0], 2542 qword); 2543 rx_buffer = i40e_rx_bi(rx_ring, ntp); 2544 i40e_inc_ntp(rx_ring); 2545 i40e_reuse_rx_page(rx_ring, rx_buffer); 2546 /* Update ntc and bump cleaned count if not in the 2547 * middle of mb packet. 2548 */ 2549 if (rx_ring->next_to_clean == ntp) { 2550 rx_ring->next_to_clean = 2551 rx_ring->next_to_process; 2552 cleaned_count++; 2553 } 2554 continue; 2555 } 2556 2557 size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> 2558 I40E_RXD_QW1_LENGTH_PBUF_SHIFT; 2559 if (!size) 2560 break; 2561 2562 i40e_trace(clean_rx_irq, rx_ring, rx_desc, xdp); 2563 /* retrieve a buffer from the ring */ 2564 rx_buffer = i40e_get_rx_buffer(rx_ring, size); 2565 2566 neop = i40e_is_non_eop(rx_ring, rx_desc); 2567 i40e_inc_ntp(rx_ring); 2568 2569 if (!xdp->data) { 2570 unsigned char *hard_start; 2571 2572 hard_start = page_address(rx_buffer->page) + 2573 rx_buffer->page_offset - offset; 2574 xdp_prepare_buff(xdp, hard_start, offset, size, true); 2575 #if (PAGE_SIZE > 4096) 2576 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2577 xdp->frame_sz = i40e_rx_frame_truesize(rx_ring, size); 2578 #endif 2579 } else if (i40e_add_xdp_frag(xdp, &nfrags, rx_buffer, size) && 2580 !neop) { 2581 /* Overflowing packet: Drop all frags on EOP */ 2582 i40e_consume_xdp_buff(rx_ring, xdp, rx_buffer); 2583 break; 2584 } 2585 2586 if (neop) 2587 continue; 2588 2589 xdp_res = i40e_run_xdp(rx_ring, xdp, xdp_prog); 2590 2591 if (xdp_res) { 2592 xdp_xmit |= xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR); 2593 2594 if (unlikely(xdp_buff_has_frags(xdp))) { 2595 i40e_process_rx_buffs(rx_ring, xdp_res, xdp); 2596 size = xdp_get_buff_len(xdp); 2597 } else if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) { 2598 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2599 } else { 2600 rx_buffer->pagecnt_bias++; 2601 } 2602 total_rx_bytes += size; 2603 } else { 2604 if (ring_uses_build_skb(rx_ring)) 2605 skb = i40e_build_skb(rx_ring, xdp, nfrags); 2606 else 2607 skb = i40e_construct_skb(rx_ring, xdp, nfrags); 2608 2609 /* drop if we failed to retrieve a buffer */ 2610 if (!skb) { 2611 rx_ring->rx_stats.alloc_buff_failed++; 2612 i40e_consume_xdp_buff(rx_ring, xdp, rx_buffer); 2613 break; 2614 } 2615 2616 if (i40e_cleanup_headers(rx_ring, skb, rx_desc)) 2617 goto process_next; 2618 2619 /* probably a little skewed due to removing CRC */ 2620 total_rx_bytes += skb->len; 2621 2622 /* populate checksum, VLAN, and protocol */ 2623 i40e_process_skb_fields(rx_ring, rx_desc, skb); 2624 2625 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, xdp); 2626 napi_gro_receive(&rx_ring->q_vector->napi, skb); 2627 } 2628 2629 /* update budget accounting */ 2630 total_rx_packets++; 2631 process_next: 2632 cleaned_count += nfrags + 1; 2633 i40e_put_rx_buffer(rx_ring, rx_buffer); 2634 rx_ring->next_to_clean = rx_ring->next_to_process; 2635 2636 xdp->data = NULL; 2637 } 2638 2639 i40e_finalize_xdp_rx(rx_ring, xdp_xmit); 2640 2641 i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets); 2642 2643 *rx_cleaned = total_rx_packets; 2644 2645 /* guarantee a trip back through this routine if there was a failure */ 2646 return failure ? budget : (int)total_rx_packets; 2647 } 2648 2649 static inline u32 i40e_buildreg_itr(const int type, u16 itr) 2650 { 2651 u32 val; 2652 2653 /* We don't bother with setting the CLEARPBA bit as the data sheet 2654 * points out doing so is "meaningless since it was already 2655 * auto-cleared". The auto-clearing happens when the interrupt is 2656 * asserted. 2657 * 2658 * Hardware errata 28 for also indicates that writing to a 2659 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear 2660 * an event in the PBA anyway so we need to rely on the automask 2661 * to hold pending events for us until the interrupt is re-enabled 2662 * 2663 * The itr value is reported in microseconds, and the register 2664 * value is recorded in 2 microsecond units. For this reason we 2665 * only need to shift by the interval shift - 1 instead of the 2666 * full value. 2667 */ 2668 itr &= I40E_ITR_MASK; 2669 2670 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 2671 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | 2672 (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1)); 2673 2674 return val; 2675 } 2676 2677 /* a small macro to shorten up some long lines */ 2678 #define INTREG I40E_PFINT_DYN_CTLN 2679 2680 /* The act of updating the ITR will cause it to immediately trigger. In order 2681 * to prevent this from throwing off adaptive update statistics we defer the 2682 * update so that it can only happen so often. So after either Tx or Rx are 2683 * updated we make the adaptive scheme wait until either the ITR completely 2684 * expires via the next_update expiration or we have been through at least 2685 * 3 interrupts. 2686 */ 2687 #define ITR_COUNTDOWN_START 3 2688 2689 /** 2690 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt 2691 * @vsi: the VSI we care about 2692 * @q_vector: q_vector for which itr is being updated and interrupt enabled 2693 * 2694 **/ 2695 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, 2696 struct i40e_q_vector *q_vector) 2697 { 2698 struct i40e_hw *hw = &vsi->back->hw; 2699 u32 intval; 2700 2701 /* If we don't have MSIX, then we only need to re-enable icr0 */ 2702 if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) { 2703 i40e_irq_dynamic_enable_icr0(vsi->back); 2704 return; 2705 } 2706 2707 /* These will do nothing if dynamic updates are not enabled */ 2708 i40e_update_itr(q_vector, &q_vector->tx); 2709 i40e_update_itr(q_vector, &q_vector->rx); 2710 2711 /* This block of logic allows us to get away with only updating 2712 * one ITR value with each interrupt. The idea is to perform a 2713 * pseudo-lazy update with the following criteria. 2714 * 2715 * 1. Rx is given higher priority than Tx if both are in same state 2716 * 2. If we must reduce an ITR that is given highest priority. 2717 * 3. We then give priority to increasing ITR based on amount. 2718 */ 2719 if (q_vector->rx.target_itr < q_vector->rx.current_itr) { 2720 /* Rx ITR needs to be reduced, this is highest priority */ 2721 intval = i40e_buildreg_itr(I40E_RX_ITR, 2722 q_vector->rx.target_itr); 2723 q_vector->rx.current_itr = q_vector->rx.target_itr; 2724 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2725 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) || 2726 ((q_vector->rx.target_itr - q_vector->rx.current_itr) < 2727 (q_vector->tx.target_itr - q_vector->tx.current_itr))) { 2728 /* Tx ITR needs to be reduced, this is second priority 2729 * Tx ITR needs to be increased more than Rx, fourth priority 2730 */ 2731 intval = i40e_buildreg_itr(I40E_TX_ITR, 2732 q_vector->tx.target_itr); 2733 q_vector->tx.current_itr = q_vector->tx.target_itr; 2734 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2735 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) { 2736 /* Rx ITR needs to be increased, third priority */ 2737 intval = i40e_buildreg_itr(I40E_RX_ITR, 2738 q_vector->rx.target_itr); 2739 q_vector->rx.current_itr = q_vector->rx.target_itr; 2740 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2741 } else { 2742 /* No ITR update, lowest priority */ 2743 intval = i40e_buildreg_itr(I40E_ITR_NONE, 0); 2744 if (q_vector->itr_countdown) 2745 q_vector->itr_countdown--; 2746 } 2747 2748 if (!test_bit(__I40E_VSI_DOWN, vsi->state)) 2749 wr32(hw, INTREG(q_vector->reg_idx), intval); 2750 } 2751 2752 /** 2753 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine 2754 * @napi: napi struct with our devices info in it 2755 * @budget: amount of work driver is allowed to do this pass, in packets 2756 * 2757 * This function will clean all queues associated with a q_vector. 2758 * 2759 * Returns the amount of work done 2760 **/ 2761 int i40e_napi_poll(struct napi_struct *napi, int budget) 2762 { 2763 struct i40e_q_vector *q_vector = 2764 container_of(napi, struct i40e_q_vector, napi); 2765 struct i40e_vsi *vsi = q_vector->vsi; 2766 struct i40e_ring *ring; 2767 bool tx_clean_complete = true; 2768 bool rx_clean_complete = true; 2769 unsigned int tx_cleaned = 0; 2770 unsigned int rx_cleaned = 0; 2771 bool clean_complete = true; 2772 bool arm_wb = false; 2773 int budget_per_ring; 2774 int work_done = 0; 2775 2776 if (test_bit(__I40E_VSI_DOWN, vsi->state)) { 2777 napi_complete(napi); 2778 return 0; 2779 } 2780 2781 /* Since the actual Tx work is minimal, we can give the Tx a larger 2782 * budget and be more aggressive about cleaning up the Tx descriptors. 2783 */ 2784 i40e_for_each_ring(ring, q_vector->tx) { 2785 bool wd = ring->xsk_pool ? 2786 i40e_clean_xdp_tx_irq(vsi, ring) : 2787 i40e_clean_tx_irq(vsi, ring, budget, &tx_cleaned); 2788 2789 if (!wd) { 2790 clean_complete = tx_clean_complete = false; 2791 continue; 2792 } 2793 arm_wb |= ring->arm_wb; 2794 ring->arm_wb = false; 2795 } 2796 2797 /* Handle case where we are called by netpoll with a budget of 0 */ 2798 if (budget <= 0) 2799 goto tx_only; 2800 2801 /* normally we have 1 Rx ring per q_vector */ 2802 if (unlikely(q_vector->num_ringpairs > 1)) 2803 /* We attempt to distribute budget to each Rx queue fairly, but 2804 * don't allow the budget to go below 1 because that would exit 2805 * polling early. 2806 */ 2807 budget_per_ring = max_t(int, budget / q_vector->num_ringpairs, 1); 2808 else 2809 /* Max of 1 Rx ring in this q_vector so give it the budget */ 2810 budget_per_ring = budget; 2811 2812 i40e_for_each_ring(ring, q_vector->rx) { 2813 int cleaned = ring->xsk_pool ? 2814 i40e_clean_rx_irq_zc(ring, budget_per_ring) : 2815 i40e_clean_rx_irq(ring, budget_per_ring, &rx_cleaned); 2816 2817 work_done += cleaned; 2818 /* if we clean as many as budgeted, we must not be done */ 2819 if (cleaned >= budget_per_ring) 2820 clean_complete = rx_clean_complete = false; 2821 } 2822 2823 if (!i40e_enabled_xdp_vsi(vsi)) 2824 trace_i40e_napi_poll(napi, q_vector, budget, budget_per_ring, rx_cleaned, 2825 tx_cleaned, rx_clean_complete, tx_clean_complete); 2826 2827 /* If work not completed, return budget and polling will return */ 2828 if (!clean_complete) { 2829 int cpu_id = smp_processor_id(); 2830 2831 /* It is possible that the interrupt affinity has changed but, 2832 * if the cpu is pegged at 100%, polling will never exit while 2833 * traffic continues and the interrupt will be stuck on this 2834 * cpu. We check to make sure affinity is correct before we 2835 * continue to poll, otherwise we must stop polling so the 2836 * interrupt can move to the correct cpu. 2837 */ 2838 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) { 2839 /* Tell napi that we are done polling */ 2840 napi_complete_done(napi, work_done); 2841 2842 /* Force an interrupt */ 2843 i40e_force_wb(vsi, q_vector); 2844 2845 /* Return budget-1 so that polling stops */ 2846 return budget - 1; 2847 } 2848 tx_only: 2849 if (arm_wb) { 2850 q_vector->tx.ring[0].tx_stats.tx_force_wb++; 2851 i40e_enable_wb_on_itr(vsi, q_vector); 2852 } 2853 return budget; 2854 } 2855 2856 if (q_vector->tx.ring[0].flags & I40E_TXR_FLAGS_WB_ON_ITR) 2857 q_vector->arm_wb_state = false; 2858 2859 /* Exit the polling mode, but don't re-enable interrupts if stack might 2860 * poll us due to busy-polling 2861 */ 2862 if (likely(napi_complete_done(napi, work_done))) 2863 i40e_update_enable_itr(vsi, q_vector); 2864 2865 return min(work_done, budget - 1); 2866 } 2867 2868 /** 2869 * i40e_atr - Add a Flow Director ATR filter 2870 * @tx_ring: ring to add programming descriptor to 2871 * @skb: send buffer 2872 * @tx_flags: send tx flags 2873 **/ 2874 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, 2875 u32 tx_flags) 2876 { 2877 struct i40e_filter_program_desc *fdir_desc; 2878 struct i40e_pf *pf = tx_ring->vsi->back; 2879 union { 2880 unsigned char *network; 2881 struct iphdr *ipv4; 2882 struct ipv6hdr *ipv6; 2883 } hdr; 2884 struct tcphdr *th; 2885 unsigned int hlen; 2886 u32 flex_ptype, dtype_cmd; 2887 int l4_proto; 2888 u16 i; 2889 2890 /* make sure ATR is enabled */ 2891 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) 2892 return; 2893 2894 if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) 2895 return; 2896 2897 /* if sampling is disabled do nothing */ 2898 if (!tx_ring->atr_sample_rate) 2899 return; 2900 2901 /* Currently only IPv4/IPv6 with TCP is supported */ 2902 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) 2903 return; 2904 2905 /* snag network header to get L4 type and address */ 2906 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? 2907 skb_inner_network_header(skb) : skb_network_header(skb); 2908 2909 /* Note: tx_flags gets modified to reflect inner protocols in 2910 * tx_enable_csum function if encap is enabled. 2911 */ 2912 if (tx_flags & I40E_TX_FLAGS_IPV4) { 2913 /* access ihl as u8 to avoid unaligned access on ia64 */ 2914 hlen = (hdr.network[0] & 0x0F) << 2; 2915 l4_proto = hdr.ipv4->protocol; 2916 } else { 2917 /* find the start of the innermost ipv6 header */ 2918 unsigned int inner_hlen = hdr.network - skb->data; 2919 unsigned int h_offset = inner_hlen; 2920 2921 /* this function updates h_offset to the end of the header */ 2922 l4_proto = 2923 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL); 2924 /* hlen will contain our best estimate of the tcp header */ 2925 hlen = h_offset - inner_hlen; 2926 } 2927 2928 if (l4_proto != IPPROTO_TCP) 2929 return; 2930 2931 th = (struct tcphdr *)(hdr.network + hlen); 2932 2933 /* Due to lack of space, no more new filters can be programmed */ 2934 if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) 2935 return; 2936 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) { 2937 /* HW ATR eviction will take care of removing filters on FIN 2938 * and RST packets. 2939 */ 2940 if (th->fin || th->rst) 2941 return; 2942 } 2943 2944 tx_ring->atr_count++; 2945 2946 /* sample on all syn/fin/rst packets or once every atr sample rate */ 2947 if (!th->fin && 2948 !th->syn && 2949 !th->rst && 2950 (tx_ring->atr_count < tx_ring->atr_sample_rate)) 2951 return; 2952 2953 tx_ring->atr_count = 0; 2954 2955 /* grab the next descriptor */ 2956 i = tx_ring->next_to_use; 2957 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 2958 2959 i++; 2960 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2961 2962 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 2963 I40E_TXD_FLTR_QW0_QINDEX_MASK; 2964 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? 2965 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 2966 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 2967 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 2968 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 2969 2970 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 2971 2972 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 2973 2974 dtype_cmd |= (th->fin || th->rst) ? 2975 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 2976 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 2977 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 2978 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 2979 2980 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 2981 I40E_TXD_FLTR_QW1_DEST_SHIFT; 2982 2983 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 2984 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 2985 2986 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 2987 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) 2988 dtype_cmd |= 2989 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << 2990 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2991 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2992 else 2993 dtype_cmd |= 2994 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << 2995 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2996 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2997 2998 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) 2999 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; 3000 3001 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 3002 fdir_desc->rsvd = cpu_to_le32(0); 3003 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 3004 fdir_desc->fd_id = cpu_to_le32(0); 3005 } 3006 3007 /** 3008 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW 3009 * @skb: send buffer 3010 * @tx_ring: ring to send buffer on 3011 * @flags: the tx flags to be set 3012 * 3013 * Checks the skb and set up correspondingly several generic transmit flags 3014 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 3015 * 3016 * Returns error code indicate the frame should be dropped upon error and the 3017 * otherwise returns 0 to indicate the flags has been set properly. 3018 **/ 3019 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 3020 struct i40e_ring *tx_ring, 3021 u32 *flags) 3022 { 3023 __be16 protocol = skb->protocol; 3024 u32 tx_flags = 0; 3025 3026 if (protocol == htons(ETH_P_8021Q) && 3027 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 3028 /* When HW VLAN acceleration is turned off by the user the 3029 * stack sets the protocol to 8021q so that the driver 3030 * can take any steps required to support the SW only 3031 * VLAN handling. In our case the driver doesn't need 3032 * to take any further steps so just set the protocol 3033 * to the encapsulated ethertype. 3034 */ 3035 skb->protocol = vlan_get_protocol(skb); 3036 goto out; 3037 } 3038 3039 /* if we have a HW VLAN tag being added, default to the HW one */ 3040 if (skb_vlan_tag_present(skb)) { 3041 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; 3042 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 3043 /* else if it is a SW VLAN, check the next protocol and store the tag */ 3044 } else if (protocol == htons(ETH_P_8021Q)) { 3045 struct vlan_hdr *vhdr, _vhdr; 3046 3047 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 3048 if (!vhdr) 3049 return -EINVAL; 3050 3051 protocol = vhdr->h_vlan_encapsulated_proto; 3052 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; 3053 tx_flags |= I40E_TX_FLAGS_SW_VLAN; 3054 } 3055 3056 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) 3057 goto out; 3058 3059 /* Insert 802.1p priority into VLAN header */ 3060 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || 3061 (skb->priority != TC_PRIO_CONTROL)) { 3062 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; 3063 tx_flags |= (skb->priority & 0x7) << 3064 I40E_TX_FLAGS_VLAN_PRIO_SHIFT; 3065 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { 3066 struct vlan_ethhdr *vhdr; 3067 int rc; 3068 3069 rc = skb_cow_head(skb, 0); 3070 if (rc < 0) 3071 return rc; 3072 vhdr = skb_vlan_eth_hdr(skb); 3073 vhdr->h_vlan_TCI = htons(tx_flags >> 3074 I40E_TX_FLAGS_VLAN_SHIFT); 3075 } else { 3076 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 3077 } 3078 } 3079 3080 out: 3081 *flags = tx_flags; 3082 return 0; 3083 } 3084 3085 /** 3086 * i40e_tso - set up the tso context descriptor 3087 * @first: pointer to first Tx buffer for xmit 3088 * @hdr_len: ptr to the size of the packet header 3089 * @cd_type_cmd_tso_mss: Quad Word 1 3090 * 3091 * Returns 0 if no TSO can happen, 1 if tso is going, or error 3092 **/ 3093 static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, 3094 u64 *cd_type_cmd_tso_mss) 3095 { 3096 struct sk_buff *skb = first->skb; 3097 u64 cd_cmd, cd_tso_len, cd_mss; 3098 __be16 protocol; 3099 union { 3100 struct iphdr *v4; 3101 struct ipv6hdr *v6; 3102 unsigned char *hdr; 3103 } ip; 3104 union { 3105 struct tcphdr *tcp; 3106 struct udphdr *udp; 3107 unsigned char *hdr; 3108 } l4; 3109 u32 paylen, l4_offset; 3110 u16 gso_size; 3111 int err; 3112 3113 if (skb->ip_summed != CHECKSUM_PARTIAL) 3114 return 0; 3115 3116 if (!skb_is_gso(skb)) 3117 return 0; 3118 3119 err = skb_cow_head(skb, 0); 3120 if (err < 0) 3121 return err; 3122 3123 protocol = vlan_get_protocol(skb); 3124 3125 if (eth_p_mpls(protocol)) 3126 ip.hdr = skb_inner_network_header(skb); 3127 else 3128 ip.hdr = skb_network_header(skb); 3129 l4.hdr = skb_checksum_start(skb); 3130 3131 /* initialize outer IP header fields */ 3132 if (ip.v4->version == 4) { 3133 ip.v4->tot_len = 0; 3134 ip.v4->check = 0; 3135 3136 first->tx_flags |= I40E_TX_FLAGS_TSO; 3137 } else { 3138 ip.v6->payload_len = 0; 3139 first->tx_flags |= I40E_TX_FLAGS_TSO; 3140 } 3141 3142 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 3143 SKB_GSO_GRE_CSUM | 3144 SKB_GSO_IPXIP4 | 3145 SKB_GSO_IPXIP6 | 3146 SKB_GSO_UDP_TUNNEL | 3147 SKB_GSO_UDP_TUNNEL_CSUM)) { 3148 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 3149 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { 3150 l4.udp->len = 0; 3151 3152 /* determine offset of outer transport header */ 3153 l4_offset = l4.hdr - skb->data; 3154 3155 /* remove payload length from outer checksum */ 3156 paylen = skb->len - l4_offset; 3157 csum_replace_by_diff(&l4.udp->check, 3158 (__force __wsum)htonl(paylen)); 3159 } 3160 3161 /* reset pointers to inner headers */ 3162 ip.hdr = skb_inner_network_header(skb); 3163 l4.hdr = skb_inner_transport_header(skb); 3164 3165 /* initialize inner IP header fields */ 3166 if (ip.v4->version == 4) { 3167 ip.v4->tot_len = 0; 3168 ip.v4->check = 0; 3169 } else { 3170 ip.v6->payload_len = 0; 3171 } 3172 } 3173 3174 /* determine offset of inner transport header */ 3175 l4_offset = l4.hdr - skb->data; 3176 3177 /* remove payload length from inner checksum */ 3178 paylen = skb->len - l4_offset; 3179 3180 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3181 csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen)); 3182 /* compute length of segmentation header */ 3183 *hdr_len = sizeof(*l4.udp) + l4_offset; 3184 } else { 3185 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); 3186 /* compute length of segmentation header */ 3187 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 3188 } 3189 3190 /* pull values out of skb_shinfo */ 3191 gso_size = skb_shinfo(skb)->gso_size; 3192 3193 /* update GSO size and bytecount with header size */ 3194 first->gso_segs = skb_shinfo(skb)->gso_segs; 3195 first->bytecount += (first->gso_segs - 1) * *hdr_len; 3196 3197 /* find the field values */ 3198 cd_cmd = I40E_TX_CTX_DESC_TSO; 3199 cd_tso_len = skb->len - *hdr_len; 3200 cd_mss = gso_size; 3201 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | 3202 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | 3203 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); 3204 return 1; 3205 } 3206 3207 /** 3208 * i40e_tsyn - set up the tsyn context descriptor 3209 * @tx_ring: ptr to the ring to send 3210 * @skb: ptr to the skb we're sending 3211 * @tx_flags: the collected send information 3212 * @cd_type_cmd_tso_mss: Quad Word 1 3213 * 3214 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen 3215 **/ 3216 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, 3217 u32 tx_flags, u64 *cd_type_cmd_tso_mss) 3218 { 3219 struct i40e_pf *pf; 3220 3221 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 3222 return 0; 3223 3224 /* Tx timestamps cannot be sampled when doing TSO */ 3225 if (tx_flags & I40E_TX_FLAGS_TSO) 3226 return 0; 3227 3228 /* only timestamp the outbound packet if the user has requested it and 3229 * we are not already transmitting a packet to be timestamped 3230 */ 3231 pf = i40e_netdev_to_pf(tx_ring->netdev); 3232 if (!(pf->flags & I40E_FLAG_PTP)) 3233 return 0; 3234 3235 if (pf->ptp_tx && 3236 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) { 3237 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3238 pf->ptp_tx_start = jiffies; 3239 pf->ptp_tx_skb = skb_get(skb); 3240 } else { 3241 pf->tx_hwtstamp_skipped++; 3242 return 0; 3243 } 3244 3245 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << 3246 I40E_TXD_CTX_QW1_CMD_SHIFT; 3247 3248 return 1; 3249 } 3250 3251 /** 3252 * i40e_tx_enable_csum - Enable Tx checksum offloads 3253 * @skb: send buffer 3254 * @tx_flags: pointer to Tx flags currently set 3255 * @td_cmd: Tx descriptor command bits to set 3256 * @td_offset: Tx descriptor header offsets to set 3257 * @tx_ring: Tx descriptor ring 3258 * @cd_tunneling: ptr to context desc bits 3259 **/ 3260 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, 3261 u32 *td_cmd, u32 *td_offset, 3262 struct i40e_ring *tx_ring, 3263 u32 *cd_tunneling) 3264 { 3265 union { 3266 struct iphdr *v4; 3267 struct ipv6hdr *v6; 3268 unsigned char *hdr; 3269 } ip; 3270 union { 3271 struct tcphdr *tcp; 3272 struct udphdr *udp; 3273 unsigned char *hdr; 3274 } l4; 3275 unsigned char *exthdr; 3276 u32 offset, cmd = 0; 3277 __be16 frag_off; 3278 __be16 protocol; 3279 u8 l4_proto = 0; 3280 3281 if (skb->ip_summed != CHECKSUM_PARTIAL) 3282 return 0; 3283 3284 protocol = vlan_get_protocol(skb); 3285 3286 if (eth_p_mpls(protocol)) { 3287 ip.hdr = skb_inner_network_header(skb); 3288 l4.hdr = skb_checksum_start(skb); 3289 } else { 3290 ip.hdr = skb_network_header(skb); 3291 l4.hdr = skb_transport_header(skb); 3292 } 3293 3294 /* set the tx_flags to indicate the IP protocol type. this is 3295 * required so that checksum header computation below is accurate. 3296 */ 3297 if (ip.v4->version == 4) 3298 *tx_flags |= I40E_TX_FLAGS_IPV4; 3299 else 3300 *tx_flags |= I40E_TX_FLAGS_IPV6; 3301 3302 /* compute outer L2 header size */ 3303 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; 3304 3305 if (skb->encapsulation) { 3306 u32 tunnel = 0; 3307 /* define outer network header type */ 3308 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 3309 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 3310 I40E_TX_CTX_EXT_IP_IPV4 : 3311 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; 3312 3313 l4_proto = ip.v4->protocol; 3314 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 3315 int ret; 3316 3317 tunnel |= I40E_TX_CTX_EXT_IP_IPV6; 3318 3319 exthdr = ip.hdr + sizeof(*ip.v6); 3320 l4_proto = ip.v6->nexthdr; 3321 ret = ipv6_skip_exthdr(skb, exthdr - skb->data, 3322 &l4_proto, &frag_off); 3323 if (ret < 0) 3324 return -1; 3325 } 3326 3327 /* define outer transport */ 3328 switch (l4_proto) { 3329 case IPPROTO_UDP: 3330 tunnel |= I40E_TXD_CTX_UDP_TUNNELING; 3331 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 3332 break; 3333 case IPPROTO_GRE: 3334 tunnel |= I40E_TXD_CTX_GRE_TUNNELING; 3335 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 3336 break; 3337 case IPPROTO_IPIP: 3338 case IPPROTO_IPV6: 3339 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 3340 l4.hdr = skb_inner_network_header(skb); 3341 break; 3342 default: 3343 if (*tx_flags & I40E_TX_FLAGS_TSO) 3344 return -1; 3345 3346 skb_checksum_help(skb); 3347 return 0; 3348 } 3349 3350 /* compute outer L3 header size */ 3351 tunnel |= ((l4.hdr - ip.hdr) / 4) << 3352 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; 3353 3354 /* switch IP header pointer from outer to inner header */ 3355 ip.hdr = skb_inner_network_header(skb); 3356 3357 /* compute tunnel header size */ 3358 tunnel |= ((ip.hdr - l4.hdr) / 2) << 3359 I40E_TXD_CTX_QW0_NATLEN_SHIFT; 3360 3361 /* indicate if we need to offload outer UDP header */ 3362 if ((*tx_flags & I40E_TX_FLAGS_TSO) && 3363 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 3364 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) 3365 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; 3366 3367 /* record tunnel offload values */ 3368 *cd_tunneling |= tunnel; 3369 3370 /* switch L4 header pointer from outer to inner */ 3371 l4.hdr = skb_inner_transport_header(skb); 3372 l4_proto = 0; 3373 3374 /* reset type as we transition from outer to inner headers */ 3375 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); 3376 if (ip.v4->version == 4) 3377 *tx_flags |= I40E_TX_FLAGS_IPV4; 3378 if (ip.v6->version == 6) 3379 *tx_flags |= I40E_TX_FLAGS_IPV6; 3380 } 3381 3382 /* Enable IP checksum offloads */ 3383 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 3384 l4_proto = ip.v4->protocol; 3385 /* the stack computes the IP header already, the only time we 3386 * need the hardware to recompute it is in the case of TSO. 3387 */ 3388 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 3389 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : 3390 I40E_TX_DESC_CMD_IIPT_IPV4; 3391 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 3392 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; 3393 3394 exthdr = ip.hdr + sizeof(*ip.v6); 3395 l4_proto = ip.v6->nexthdr; 3396 if (l4.hdr != exthdr) 3397 ipv6_skip_exthdr(skb, exthdr - skb->data, 3398 &l4_proto, &frag_off); 3399 } 3400 3401 /* compute inner L3 header size */ 3402 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 3403 3404 /* Enable L4 checksum offloads */ 3405 switch (l4_proto) { 3406 case IPPROTO_TCP: 3407 /* enable checksum offloads */ 3408 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; 3409 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 3410 break; 3411 case IPPROTO_SCTP: 3412 /* enable SCTP checksum offload */ 3413 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; 3414 offset |= (sizeof(struct sctphdr) >> 2) << 3415 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 3416 break; 3417 case IPPROTO_UDP: 3418 /* enable UDP checksum offload */ 3419 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; 3420 offset |= (sizeof(struct udphdr) >> 2) << 3421 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 3422 break; 3423 default: 3424 if (*tx_flags & I40E_TX_FLAGS_TSO) 3425 return -1; 3426 skb_checksum_help(skb); 3427 return 0; 3428 } 3429 3430 *td_cmd |= cmd; 3431 *td_offset |= offset; 3432 3433 return 1; 3434 } 3435 3436 /** 3437 * i40e_create_tx_ctx - Build the Tx context descriptor 3438 * @tx_ring: ring to create the descriptor on 3439 * @cd_type_cmd_tso_mss: Quad Word 1 3440 * @cd_tunneling: Quad Word 0 - bits 0-31 3441 * @cd_l2tag2: Quad Word 0 - bits 32-63 3442 **/ 3443 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, 3444 const u64 cd_type_cmd_tso_mss, 3445 const u32 cd_tunneling, const u32 cd_l2tag2) 3446 { 3447 struct i40e_tx_context_desc *context_desc; 3448 int i = tx_ring->next_to_use; 3449 3450 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && 3451 !cd_tunneling && !cd_l2tag2) 3452 return; 3453 3454 /* grab the next descriptor */ 3455 context_desc = I40E_TX_CTXTDESC(tx_ring, i); 3456 3457 i++; 3458 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 3459 3460 /* cpu_to_le32 and assign to struct fields */ 3461 context_desc->tunneling_params = cpu_to_le32(cd_tunneling); 3462 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); 3463 context_desc->rsvd = cpu_to_le16(0); 3464 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); 3465 } 3466 3467 /** 3468 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions 3469 * @tx_ring: the ring to be checked 3470 * @size: the size buffer we want to assure is available 3471 * 3472 * Returns -EBUSY if a stop is needed, else 0 3473 **/ 3474 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 3475 { 3476 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 3477 /* Memory barrier before checking head and tail */ 3478 smp_mb(); 3479 3480 ++tx_ring->tx_stats.tx_stopped; 3481 3482 /* Check again in a case another CPU has just made room available. */ 3483 if (likely(I40E_DESC_UNUSED(tx_ring) < size)) 3484 return -EBUSY; 3485 3486 /* A reprieve! - use start_queue because it doesn't call schedule */ 3487 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 3488 ++tx_ring->tx_stats.restart_queue; 3489 return 0; 3490 } 3491 3492 /** 3493 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet 3494 * @skb: send buffer 3495 * 3496 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire 3497 * and so we need to figure out the cases where we need to linearize the skb. 3498 * 3499 * For TSO we need to count the TSO header and segment payload separately. 3500 * As such we need to check cases where we have 7 fragments or more as we 3501 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for 3502 * the segment payload in the first descriptor, and another 7 for the 3503 * fragments. 3504 **/ 3505 bool __i40e_chk_linearize(struct sk_buff *skb) 3506 { 3507 const skb_frag_t *frag, *stale; 3508 int nr_frags, sum; 3509 3510 /* no need to check if number of frags is less than 7 */ 3511 nr_frags = skb_shinfo(skb)->nr_frags; 3512 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) 3513 return false; 3514 3515 /* We need to walk through the list and validate that each group 3516 * of 6 fragments totals at least gso_size. 3517 */ 3518 nr_frags -= I40E_MAX_BUFFER_TXD - 2; 3519 frag = &skb_shinfo(skb)->frags[0]; 3520 3521 /* Initialize size to the negative value of gso_size minus 1. We 3522 * use this as the worst case scenerio in which the frag ahead 3523 * of us only provides one byte which is why we are limited to 6 3524 * descriptors for a single transmit as the header and previous 3525 * fragment are already consuming 2 descriptors. 3526 */ 3527 sum = 1 - skb_shinfo(skb)->gso_size; 3528 3529 /* Add size of frags 0 through 4 to create our initial sum */ 3530 sum += skb_frag_size(frag++); 3531 sum += skb_frag_size(frag++); 3532 sum += skb_frag_size(frag++); 3533 sum += skb_frag_size(frag++); 3534 sum += skb_frag_size(frag++); 3535 3536 /* Walk through fragments adding latest fragment, testing it, and 3537 * then removing stale fragments from the sum. 3538 */ 3539 for (stale = &skb_shinfo(skb)->frags[0];; stale++) { 3540 int stale_size = skb_frag_size(stale); 3541 3542 sum += skb_frag_size(frag++); 3543 3544 /* The stale fragment may present us with a smaller 3545 * descriptor than the actual fragment size. To account 3546 * for that we need to remove all the data on the front and 3547 * figure out what the remainder would be in the last 3548 * descriptor associated with the fragment. 3549 */ 3550 if (stale_size > I40E_MAX_DATA_PER_TXD) { 3551 int align_pad = -(skb_frag_off(stale)) & 3552 (I40E_MAX_READ_REQ_SIZE - 1); 3553 3554 sum -= align_pad; 3555 stale_size -= align_pad; 3556 3557 do { 3558 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED; 3559 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED; 3560 } while (stale_size > I40E_MAX_DATA_PER_TXD); 3561 } 3562 3563 /* if sum is negative we failed to make sufficient progress */ 3564 if (sum < 0) 3565 return true; 3566 3567 if (!nr_frags--) 3568 break; 3569 3570 sum -= stale_size; 3571 } 3572 3573 return false; 3574 } 3575 3576 /** 3577 * i40e_tx_map - Build the Tx descriptor 3578 * @tx_ring: ring to send buffer on 3579 * @skb: send buffer 3580 * @first: first buffer info buffer to use 3581 * @tx_flags: collected send information 3582 * @hdr_len: size of the packet header 3583 * @td_cmd: the command field in the descriptor 3584 * @td_offset: offset for checksum or crc 3585 * 3586 * Returns 0 on success, -1 on failure to DMA 3587 **/ 3588 static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 3589 struct i40e_tx_buffer *first, u32 tx_flags, 3590 const u8 hdr_len, u32 td_cmd, u32 td_offset) 3591 { 3592 unsigned int data_len = skb->data_len; 3593 unsigned int size = skb_headlen(skb); 3594 skb_frag_t *frag; 3595 struct i40e_tx_buffer *tx_bi; 3596 struct i40e_tx_desc *tx_desc; 3597 u16 i = tx_ring->next_to_use; 3598 u32 td_tag = 0; 3599 dma_addr_t dma; 3600 u16 desc_count = 1; 3601 3602 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { 3603 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; 3604 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> 3605 I40E_TX_FLAGS_VLAN_SHIFT; 3606 } 3607 3608 first->tx_flags = tx_flags; 3609 3610 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 3611 3612 tx_desc = I40E_TX_DESC(tx_ring, i); 3613 tx_bi = first; 3614 3615 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 3616 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 3617 3618 if (dma_mapping_error(tx_ring->dev, dma)) 3619 goto dma_error; 3620 3621 /* record length, and DMA address */ 3622 dma_unmap_len_set(tx_bi, len, size); 3623 dma_unmap_addr_set(tx_bi, dma, dma); 3624 3625 /* align size to end of page */ 3626 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); 3627 tx_desc->buffer_addr = cpu_to_le64(dma); 3628 3629 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { 3630 tx_desc->cmd_type_offset_bsz = 3631 build_ctob(td_cmd, td_offset, 3632 max_data, td_tag); 3633 3634 tx_desc++; 3635 i++; 3636 desc_count++; 3637 3638 if (i == tx_ring->count) { 3639 tx_desc = I40E_TX_DESC(tx_ring, 0); 3640 i = 0; 3641 } 3642 3643 dma += max_data; 3644 size -= max_data; 3645 3646 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 3647 tx_desc->buffer_addr = cpu_to_le64(dma); 3648 } 3649 3650 if (likely(!data_len)) 3651 break; 3652 3653 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, 3654 size, td_tag); 3655 3656 tx_desc++; 3657 i++; 3658 desc_count++; 3659 3660 if (i == tx_ring->count) { 3661 tx_desc = I40E_TX_DESC(tx_ring, 0); 3662 i = 0; 3663 } 3664 3665 size = skb_frag_size(frag); 3666 data_len -= size; 3667 3668 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 3669 DMA_TO_DEVICE); 3670 3671 tx_bi = &tx_ring->tx_bi[i]; 3672 } 3673 3674 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 3675 3676 i++; 3677 if (i == tx_ring->count) 3678 i = 0; 3679 3680 tx_ring->next_to_use = i; 3681 3682 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); 3683 3684 /* write last descriptor with EOP bit */ 3685 td_cmd |= I40E_TX_DESC_CMD_EOP; 3686 3687 /* We OR these values together to check both against 4 (WB_STRIDE) 3688 * below. This is safe since we don't re-use desc_count afterwards. 3689 */ 3690 desc_count |= ++tx_ring->packet_stride; 3691 3692 if (desc_count >= WB_STRIDE) { 3693 /* write last descriptor with RS bit set */ 3694 td_cmd |= I40E_TX_DESC_CMD_RS; 3695 tx_ring->packet_stride = 0; 3696 } 3697 3698 tx_desc->cmd_type_offset_bsz = 3699 build_ctob(td_cmd, td_offset, size, td_tag); 3700 3701 skb_tx_timestamp(skb); 3702 3703 /* Force memory writes to complete before letting h/w know there 3704 * are new descriptors to fetch. 3705 * 3706 * We also use this memory barrier to make certain all of the 3707 * status bits have been updated before next_to_watch is written. 3708 */ 3709 wmb(); 3710 3711 /* set next_to_watch value indicating a packet is present */ 3712 first->next_to_watch = tx_desc; 3713 3714 /* notify HW of packet */ 3715 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 3716 writel(i, tx_ring->tail); 3717 } 3718 3719 return 0; 3720 3721 dma_error: 3722 dev_info(tx_ring->dev, "TX DMA map failed\n"); 3723 3724 /* clear dma mappings for failed tx_bi map */ 3725 for (;;) { 3726 tx_bi = &tx_ring->tx_bi[i]; 3727 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); 3728 if (tx_bi == first) 3729 break; 3730 if (i == 0) 3731 i = tx_ring->count; 3732 i--; 3733 } 3734 3735 tx_ring->next_to_use = i; 3736 3737 return -1; 3738 } 3739 3740 static u16 i40e_swdcb_skb_tx_hash(struct net_device *dev, 3741 const struct sk_buff *skb, 3742 u16 num_tx_queues) 3743 { 3744 u32 jhash_initval_salt = 0xd631614b; 3745 u32 hash; 3746 3747 if (skb->sk && skb->sk->sk_hash) 3748 hash = skb->sk->sk_hash; 3749 else 3750 hash = (__force u16)skb->protocol ^ skb->hash; 3751 3752 hash = jhash_1word(hash, jhash_initval_salt); 3753 3754 return (u16)(((u64)hash * num_tx_queues) >> 32); 3755 } 3756 3757 u16 i40e_lan_select_queue(struct net_device *netdev, 3758 struct sk_buff *skb, 3759 struct net_device __always_unused *sb_dev) 3760 { 3761 struct i40e_netdev_priv *np = netdev_priv(netdev); 3762 struct i40e_vsi *vsi = np->vsi; 3763 struct i40e_hw *hw; 3764 u16 qoffset; 3765 u16 qcount; 3766 u8 tclass; 3767 u16 hash; 3768 u8 prio; 3769 3770 /* is DCB enabled at all? */ 3771 if (vsi->tc_config.numtc == 1 || 3772 i40e_is_tc_mqprio_enabled(vsi->back)) 3773 return netdev_pick_tx(netdev, skb, sb_dev); 3774 3775 prio = skb->priority; 3776 hw = &vsi->back->hw; 3777 tclass = hw->local_dcbx_config.etscfg.prioritytable[prio]; 3778 /* sanity check */ 3779 if (unlikely(!(vsi->tc_config.enabled_tc & BIT(tclass)))) 3780 tclass = 0; 3781 3782 /* select a queue assigned for the given TC */ 3783 qcount = vsi->tc_config.tc_info[tclass].qcount; 3784 hash = i40e_swdcb_skb_tx_hash(netdev, skb, qcount); 3785 3786 qoffset = vsi->tc_config.tc_info[tclass].qoffset; 3787 return qoffset + hash; 3788 } 3789 3790 /** 3791 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring 3792 * @xdpf: data to transmit 3793 * @xdp_ring: XDP Tx ring 3794 **/ 3795 static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf, 3796 struct i40e_ring *xdp_ring) 3797 { 3798 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 3799 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 3800 u16 i = 0, index = xdp_ring->next_to_use; 3801 struct i40e_tx_buffer *tx_head = &xdp_ring->tx_bi[index]; 3802 struct i40e_tx_buffer *tx_bi = tx_head; 3803 struct i40e_tx_desc *tx_desc = I40E_TX_DESC(xdp_ring, index); 3804 void *data = xdpf->data; 3805 u32 size = xdpf->len; 3806 3807 if (unlikely(I40E_DESC_UNUSED(xdp_ring) < 1 + nr_frags)) { 3808 xdp_ring->tx_stats.tx_busy++; 3809 return I40E_XDP_CONSUMED; 3810 } 3811 3812 tx_head->bytecount = xdp_get_frame_len(xdpf); 3813 tx_head->gso_segs = 1; 3814 tx_head->xdpf = xdpf; 3815 3816 for (;;) { 3817 dma_addr_t dma; 3818 3819 dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE); 3820 if (dma_mapping_error(xdp_ring->dev, dma)) 3821 goto unmap; 3822 3823 /* record length, and DMA address */ 3824 dma_unmap_len_set(tx_bi, len, size); 3825 dma_unmap_addr_set(tx_bi, dma, dma); 3826 3827 tx_desc->buffer_addr = cpu_to_le64(dma); 3828 tx_desc->cmd_type_offset_bsz = 3829 build_ctob(I40E_TX_DESC_CMD_ICRC, 0, size, 0); 3830 3831 if (++index == xdp_ring->count) 3832 index = 0; 3833 3834 if (i == nr_frags) 3835 break; 3836 3837 tx_bi = &xdp_ring->tx_bi[index]; 3838 tx_desc = I40E_TX_DESC(xdp_ring, index); 3839 3840 data = skb_frag_address(&sinfo->frags[i]); 3841 size = skb_frag_size(&sinfo->frags[i]); 3842 i++; 3843 } 3844 3845 tx_desc->cmd_type_offset_bsz |= 3846 cpu_to_le64(I40E_TXD_CMD << I40E_TXD_QW1_CMD_SHIFT); 3847 3848 /* Make certain all of the status bits have been updated 3849 * before next_to_watch is written. 3850 */ 3851 smp_wmb(); 3852 3853 xdp_ring->xdp_tx_active++; 3854 3855 tx_head->next_to_watch = tx_desc; 3856 xdp_ring->next_to_use = index; 3857 3858 return I40E_XDP_TX; 3859 3860 unmap: 3861 for (;;) { 3862 tx_bi = &xdp_ring->tx_bi[index]; 3863 if (dma_unmap_len(tx_bi, len)) 3864 dma_unmap_page(xdp_ring->dev, 3865 dma_unmap_addr(tx_bi, dma), 3866 dma_unmap_len(tx_bi, len), 3867 DMA_TO_DEVICE); 3868 dma_unmap_len_set(tx_bi, len, 0); 3869 if (tx_bi == tx_head) 3870 break; 3871 3872 if (!index) 3873 index += xdp_ring->count; 3874 index--; 3875 } 3876 3877 return I40E_XDP_CONSUMED; 3878 } 3879 3880 /** 3881 * i40e_xmit_frame_ring - Sends buffer on Tx ring 3882 * @skb: send buffer 3883 * @tx_ring: ring to send buffer on 3884 * 3885 * Returns NETDEV_TX_OK if sent, else an error code 3886 **/ 3887 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, 3888 struct i40e_ring *tx_ring) 3889 { 3890 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; 3891 u32 cd_tunneling = 0, cd_l2tag2 = 0; 3892 struct i40e_tx_buffer *first; 3893 u32 td_offset = 0; 3894 u32 tx_flags = 0; 3895 u32 td_cmd = 0; 3896 u8 hdr_len = 0; 3897 int tso, count; 3898 int tsyn; 3899 3900 /* prefetch the data, we'll need it later */ 3901 prefetch(skb->data); 3902 3903 i40e_trace(xmit_frame_ring, skb, tx_ring); 3904 3905 count = i40e_xmit_descriptor_count(skb); 3906 if (i40e_chk_linearize(skb, count)) { 3907 if (__skb_linearize(skb)) { 3908 dev_kfree_skb_any(skb); 3909 return NETDEV_TX_OK; 3910 } 3911 count = i40e_txd_use_count(skb->len); 3912 tx_ring->tx_stats.tx_linearize++; 3913 } 3914 3915 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, 3916 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, 3917 * + 4 desc gap to avoid the cache line where head is, 3918 * + 1 desc for context descriptor, 3919 * otherwise try next time 3920 */ 3921 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { 3922 tx_ring->tx_stats.tx_busy++; 3923 return NETDEV_TX_BUSY; 3924 } 3925 3926 /* record the location of the first descriptor for this packet */ 3927 first = &tx_ring->tx_bi[tx_ring->next_to_use]; 3928 first->skb = skb; 3929 first->bytecount = skb->len; 3930 first->gso_segs = 1; 3931 3932 /* prepare the xmit flags */ 3933 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) 3934 goto out_drop; 3935 3936 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); 3937 3938 if (tso < 0) 3939 goto out_drop; 3940 else if (tso) 3941 tx_flags |= I40E_TX_FLAGS_TSO; 3942 3943 /* Always offload the checksum, since it's in the data descriptor */ 3944 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, 3945 tx_ring, &cd_tunneling); 3946 if (tso < 0) 3947 goto out_drop; 3948 3949 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); 3950 3951 if (tsyn) 3952 tx_flags |= I40E_TX_FLAGS_TSYN; 3953 3954 /* always enable CRC insertion offload */ 3955 td_cmd |= I40E_TX_DESC_CMD_ICRC; 3956 3957 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, 3958 cd_tunneling, cd_l2tag2); 3959 3960 /* Add Flow Director ATR if it's enabled. 3961 * 3962 * NOTE: this must always be directly before the data descriptor. 3963 */ 3964 i40e_atr(tx_ring, skb, tx_flags); 3965 3966 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, 3967 td_cmd, td_offset)) 3968 goto cleanup_tx_tstamp; 3969 3970 return NETDEV_TX_OK; 3971 3972 out_drop: 3973 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring); 3974 dev_kfree_skb_any(first->skb); 3975 first->skb = NULL; 3976 cleanup_tx_tstamp: 3977 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) { 3978 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev); 3979 3980 dev_kfree_skb_any(pf->ptp_tx_skb); 3981 pf->ptp_tx_skb = NULL; 3982 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 3983 } 3984 3985 return NETDEV_TX_OK; 3986 } 3987 3988 /** 3989 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer 3990 * @skb: send buffer 3991 * @netdev: network interface device structure 3992 * 3993 * Returns NETDEV_TX_OK if sent, else an error code 3994 **/ 3995 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 3996 { 3997 struct i40e_netdev_priv *np = netdev_priv(netdev); 3998 struct i40e_vsi *vsi = np->vsi; 3999 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; 4000 4001 /* hardware can't handle really short frames, hardware padding works 4002 * beyond this point 4003 */ 4004 if (skb_put_padto(skb, I40E_MIN_TX_LEN)) 4005 return NETDEV_TX_OK; 4006 4007 return i40e_xmit_frame_ring(skb, tx_ring); 4008 } 4009 4010 /** 4011 * i40e_xdp_xmit - Implements ndo_xdp_xmit 4012 * @dev: netdev 4013 * @n: number of frames 4014 * @frames: array of XDP buffer pointers 4015 * @flags: XDP extra info 4016 * 4017 * Returns number of frames successfully sent. Failed frames 4018 * will be free'ed by XDP core. 4019 * 4020 * For error cases, a negative errno code is returned and no-frames 4021 * are transmitted (caller must handle freeing frames). 4022 **/ 4023 int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames, 4024 u32 flags) 4025 { 4026 struct i40e_netdev_priv *np = netdev_priv(dev); 4027 unsigned int queue_index = smp_processor_id(); 4028 struct i40e_vsi *vsi = np->vsi; 4029 struct i40e_pf *pf = vsi->back; 4030 struct i40e_ring *xdp_ring; 4031 int nxmit = 0; 4032 int i; 4033 4034 if (test_bit(__I40E_VSI_DOWN, vsi->state)) 4035 return -ENETDOWN; 4036 4037 if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs || 4038 test_bit(__I40E_CONFIG_BUSY, pf->state)) 4039 return -ENXIO; 4040 4041 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 4042 return -EINVAL; 4043 4044 xdp_ring = vsi->xdp_rings[queue_index]; 4045 4046 for (i = 0; i < n; i++) { 4047 struct xdp_frame *xdpf = frames[i]; 4048 int err; 4049 4050 err = i40e_xmit_xdp_ring(xdpf, xdp_ring); 4051 if (err != I40E_XDP_TX) 4052 break; 4053 nxmit++; 4054 } 4055 4056 if (unlikely(flags & XDP_XMIT_FLUSH)) 4057 i40e_xdp_ring_update_tail(xdp_ring); 4058 4059 return nxmit; 4060 } 4061