1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include <linux/bpf_trace.h> 5 #include <linux/net/intel/libie/pctype.h> 6 #include <linux/net/intel/libie/rx.h> 7 #include <linux/prefetch.h> 8 #include <linux/sctp.h> 9 #include <net/mpls.h> 10 #include <net/xdp.h> 11 #include "i40e_txrx_common.h" 12 #include "i40e_trace.h" 13 #include "i40e_xsk.h" 14 15 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) 16 /** 17 * i40e_fdir - Generate a Flow Director descriptor based on fdata 18 * @tx_ring: Tx ring to send buffer on 19 * @fdata: Flow director filter data 20 * @add: Indicate if we are adding a rule or deleting one 21 * 22 **/ 23 static void i40e_fdir(struct i40e_ring *tx_ring, 24 struct i40e_fdir_filter *fdata, bool add) 25 { 26 struct i40e_filter_program_desc *fdir_desc; 27 struct i40e_pf *pf = tx_ring->vsi->back; 28 u32 flex_ptype, dtype_cmd, vsi_id; 29 u16 i; 30 31 /* grab the next descriptor */ 32 i = tx_ring->next_to_use; 33 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 34 35 i++; 36 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 37 38 flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK, fdata->q_index); 39 40 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_FLEXOFF_MASK, 41 fdata->flex_off); 42 43 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_PCTYPE_MASK, fdata->pctype); 44 45 /* Use LAN VSI Id if not programmed by user */ 46 vsi_id = fdata->dest_vsi ? : i40e_pf_get_main_vsi(pf)->id; 47 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_DEST_VSI_MASK, vsi_id); 48 49 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 50 51 dtype_cmd |= add ? 52 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 53 I40E_TXD_FLTR_QW1_PCMD_SHIFT : 54 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 55 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 56 57 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_DEST_MASK, fdata->dest_ctl); 58 59 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_FD_STATUS_MASK, 60 fdata->fd_status); 61 62 if (fdata->cnt_index) { 63 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 64 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK, 65 fdata->cnt_index); 66 } 67 68 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 69 fdir_desc->rsvd = cpu_to_le32(0); 70 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 71 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id); 72 } 73 74 #define I40E_FD_CLEAN_DELAY 10 75 /** 76 * i40e_program_fdir_filter - Program a Flow Director filter 77 * @fdir_data: Packet data that will be filter parameters 78 * @raw_packet: the pre-allocated packet buffer for FDir 79 * @pf: The PF pointer 80 * @add: True for add/update, False for remove 81 **/ 82 static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, 83 u8 *raw_packet, struct i40e_pf *pf, 84 bool add) 85 { 86 struct i40e_tx_buffer *tx_buf, *first; 87 struct i40e_tx_desc *tx_desc; 88 struct i40e_ring *tx_ring; 89 struct i40e_vsi *vsi; 90 struct device *dev; 91 dma_addr_t dma; 92 u32 td_cmd = 0; 93 u16 i; 94 95 /* find existing FDIR VSI */ 96 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); 97 if (!vsi) 98 return -ENOENT; 99 100 tx_ring = vsi->tx_rings[0]; 101 dev = tx_ring->dev; 102 103 /* we need two descriptors to add/del a filter and we can wait */ 104 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) { 105 if (!i) 106 return -EAGAIN; 107 msleep_interruptible(1); 108 } 109 110 dma = dma_map_single(dev, raw_packet, 111 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); 112 if (dma_mapping_error(dev, dma)) 113 goto dma_fail; 114 115 /* grab the next descriptor */ 116 i = tx_ring->next_to_use; 117 first = &tx_ring->tx_bi[i]; 118 i40e_fdir(tx_ring, fdir_data, add); 119 120 /* Now program a dummy descriptor */ 121 i = tx_ring->next_to_use; 122 tx_desc = I40E_TX_DESC(tx_ring, i); 123 tx_buf = &tx_ring->tx_bi[i]; 124 125 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 126 127 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); 128 129 /* record length, and DMA address */ 130 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); 131 dma_unmap_addr_set(tx_buf, dma, dma); 132 133 tx_desc->buffer_addr = cpu_to_le64(dma); 134 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; 135 136 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; 137 tx_buf->raw_buf = (void *)raw_packet; 138 139 tx_desc->cmd_type_offset_bsz = 140 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); 141 142 /* Force memory writes to complete before letting h/w 143 * know there are new descriptors to fetch. 144 */ 145 wmb(); 146 147 /* Mark the data descriptor to be watched */ 148 first->next_to_watch = tx_desc; 149 150 writel(tx_ring->next_to_use, tx_ring->tail); 151 return 0; 152 153 dma_fail: 154 return -1; 155 } 156 157 /** 158 * i40e_create_dummy_packet - Constructs dummy packet for HW 159 * @dummy_packet: preallocated space for dummy packet 160 * @ipv4: is layer 3 packet of version 4 or 6 161 * @l4proto: next level protocol used in data portion of l3 162 * @data: filter data 163 * 164 * Returns address of layer 4 protocol dummy packet. 165 **/ 166 static char *i40e_create_dummy_packet(u8 *dummy_packet, bool ipv4, u8 l4proto, 167 struct i40e_fdir_filter *data) 168 { 169 bool is_vlan = !!data->vlan_tag; 170 struct vlan_hdr vlan = {}; 171 struct ipv6hdr ipv6 = {}; 172 struct ethhdr eth = {}; 173 struct iphdr ip = {}; 174 u8 *tmp; 175 176 if (ipv4) { 177 eth.h_proto = cpu_to_be16(ETH_P_IP); 178 ip.protocol = l4proto; 179 ip.version = 0x4; 180 ip.ihl = 0x5; 181 182 ip.daddr = data->dst_ip; 183 ip.saddr = data->src_ip; 184 } else { 185 eth.h_proto = cpu_to_be16(ETH_P_IPV6); 186 ipv6.nexthdr = l4proto; 187 ipv6.version = 0x6; 188 189 memcpy(&ipv6.saddr.in6_u.u6_addr32, data->src_ip6, 190 sizeof(__be32) * 4); 191 memcpy(&ipv6.daddr.in6_u.u6_addr32, data->dst_ip6, 192 sizeof(__be32) * 4); 193 } 194 195 if (is_vlan) { 196 vlan.h_vlan_TCI = data->vlan_tag; 197 vlan.h_vlan_encapsulated_proto = eth.h_proto; 198 eth.h_proto = data->vlan_etype; 199 } 200 201 tmp = dummy_packet; 202 memcpy(tmp, ð, sizeof(eth)); 203 tmp += sizeof(eth); 204 205 if (is_vlan) { 206 memcpy(tmp, &vlan, sizeof(vlan)); 207 tmp += sizeof(vlan); 208 } 209 210 if (ipv4) { 211 memcpy(tmp, &ip, sizeof(ip)); 212 tmp += sizeof(ip); 213 } else { 214 memcpy(tmp, &ipv6, sizeof(ipv6)); 215 tmp += sizeof(ipv6); 216 } 217 218 return tmp; 219 } 220 221 /** 222 * i40e_create_dummy_udp_packet - helper function to create UDP packet 223 * @raw_packet: preallocated space for dummy packet 224 * @ipv4: is layer 3 packet of version 4 or 6 225 * @l4proto: next level protocol used in data portion of l3 226 * @data: filter data 227 * 228 * Helper function to populate udp fields. 229 **/ 230 static void i40e_create_dummy_udp_packet(u8 *raw_packet, bool ipv4, u8 l4proto, 231 struct i40e_fdir_filter *data) 232 { 233 struct udphdr *udp; 234 u8 *tmp; 235 236 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_UDP, data); 237 udp = (struct udphdr *)(tmp); 238 udp->dest = data->dst_port; 239 udp->source = data->src_port; 240 } 241 242 /** 243 * i40e_create_dummy_tcp_packet - helper function to create TCP packet 244 * @raw_packet: preallocated space for dummy packet 245 * @ipv4: is layer 3 packet of version 4 or 6 246 * @l4proto: next level protocol used in data portion of l3 247 * @data: filter data 248 * 249 * Helper function to populate tcp fields. 250 **/ 251 static void i40e_create_dummy_tcp_packet(u8 *raw_packet, bool ipv4, u8 l4proto, 252 struct i40e_fdir_filter *data) 253 { 254 struct tcphdr *tcp; 255 u8 *tmp; 256 /* Dummy tcp packet */ 257 static const char tcp_packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 258 0x50, 0x11, 0x0, 0x72, 0, 0, 0, 0}; 259 260 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_TCP, data); 261 262 tcp = (struct tcphdr *)tmp; 263 memcpy(tcp, tcp_packet, sizeof(tcp_packet)); 264 tcp->dest = data->dst_port; 265 tcp->source = data->src_port; 266 } 267 268 /** 269 * i40e_create_dummy_sctp_packet - helper function to create SCTP packet 270 * @raw_packet: preallocated space for dummy packet 271 * @ipv4: is layer 3 packet of version 4 or 6 272 * @l4proto: next level protocol used in data portion of l3 273 * @data: filter data 274 * 275 * Helper function to populate sctp fields. 276 **/ 277 static void i40e_create_dummy_sctp_packet(u8 *raw_packet, bool ipv4, 278 u8 l4proto, 279 struct i40e_fdir_filter *data) 280 { 281 struct sctphdr *sctp; 282 u8 *tmp; 283 284 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_SCTP, data); 285 286 sctp = (struct sctphdr *)tmp; 287 sctp->dest = data->dst_port; 288 sctp->source = data->src_port; 289 } 290 291 /** 292 * i40e_prepare_fdir_filter - Prepare and program fdir filter 293 * @pf: physical function to attach filter to 294 * @fd_data: filter data 295 * @add: add or delete filter 296 * @packet_addr: address of dummy packet, used in filtering 297 * @payload_offset: offset from dummy packet address to user defined data 298 * @pctype: Packet type for which filter is used 299 * 300 * Helper function to offset data of dummy packet, program it and 301 * handle errors. 302 **/ 303 static int i40e_prepare_fdir_filter(struct i40e_pf *pf, 304 struct i40e_fdir_filter *fd_data, 305 bool add, char *packet_addr, 306 int payload_offset, u8 pctype) 307 { 308 int ret; 309 310 if (fd_data->flex_filter) { 311 u8 *payload; 312 __be16 pattern = fd_data->flex_word; 313 u16 off = fd_data->flex_offset; 314 315 payload = packet_addr + payload_offset; 316 317 /* If user provided vlan, offset payload by vlan header length */ 318 if (!!fd_data->vlan_tag) 319 payload += VLAN_HLEN; 320 321 *((__force __be16 *)(payload + off)) = pattern; 322 } 323 324 fd_data->pctype = pctype; 325 ret = i40e_program_fdir_filter(fd_data, packet_addr, pf, add); 326 if (ret) { 327 dev_info(&pf->pdev->dev, 328 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 329 fd_data->pctype, fd_data->fd_id, ret); 330 /* Free the packet buffer since it wasn't added to the ring */ 331 return -EOPNOTSUPP; 332 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 333 if (add) 334 dev_info(&pf->pdev->dev, 335 "Filter OK for PCTYPE %d loc = %d\n", 336 fd_data->pctype, fd_data->fd_id); 337 else 338 dev_info(&pf->pdev->dev, 339 "Filter deleted for PCTYPE %d loc = %d\n", 340 fd_data->pctype, fd_data->fd_id); 341 } 342 343 return ret; 344 } 345 346 /** 347 * i40e_change_filter_num - Prepare and program fdir filter 348 * @ipv4: is layer 3 packet of version 4 or 6 349 * @add: add or delete filter 350 * @ipv4_filter_num: field to update 351 * @ipv6_filter_num: field to update 352 * 353 * Update filter number field for pf. 354 **/ 355 static void i40e_change_filter_num(bool ipv4, bool add, u16 *ipv4_filter_num, 356 u16 *ipv6_filter_num) 357 { 358 if (add) { 359 if (ipv4) 360 (*ipv4_filter_num)++; 361 else 362 (*ipv6_filter_num)++; 363 } else { 364 if (ipv4) 365 (*ipv4_filter_num)--; 366 else 367 (*ipv6_filter_num)--; 368 } 369 } 370 371 #define I40E_UDPIP_DUMMY_PACKET_LEN 42 372 #define I40E_UDPIP6_DUMMY_PACKET_LEN 62 373 /** 374 * i40e_add_del_fdir_udp - Add/Remove UDP filters 375 * @vsi: pointer to the targeted VSI 376 * @fd_data: the flow director data required for the FDir descriptor 377 * @add: true adds a filter, false removes it 378 * @ipv4: true is v4, false is v6 379 * 380 * Returns 0 if the filters were successfully added or removed 381 **/ 382 static int i40e_add_del_fdir_udp(struct i40e_vsi *vsi, 383 struct i40e_fdir_filter *fd_data, 384 bool add, 385 bool ipv4) 386 { 387 struct i40e_pf *pf = vsi->back; 388 u8 *raw_packet; 389 int ret; 390 391 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 392 if (!raw_packet) 393 return -ENOMEM; 394 395 i40e_create_dummy_udp_packet(raw_packet, ipv4, IPPROTO_UDP, fd_data); 396 397 if (ipv4) 398 ret = i40e_prepare_fdir_filter 399 (pf, fd_data, add, raw_packet, 400 I40E_UDPIP_DUMMY_PACKET_LEN, 401 LIBIE_FILTER_PCTYPE_NONF_IPV4_UDP); 402 else 403 ret = i40e_prepare_fdir_filter 404 (pf, fd_data, add, raw_packet, 405 I40E_UDPIP6_DUMMY_PACKET_LEN, 406 LIBIE_FILTER_PCTYPE_NONF_IPV6_UDP); 407 408 if (ret) { 409 kfree(raw_packet); 410 return ret; 411 } 412 413 i40e_change_filter_num(ipv4, add, &pf->fd_udp4_filter_cnt, 414 &pf->fd_udp6_filter_cnt); 415 416 return 0; 417 } 418 419 #define I40E_TCPIP_DUMMY_PACKET_LEN 54 420 #define I40E_TCPIP6_DUMMY_PACKET_LEN 74 421 /** 422 * i40e_add_del_fdir_tcp - Add/Remove TCPv4 filters 423 * @vsi: pointer to the targeted VSI 424 * @fd_data: the flow director data required for the FDir descriptor 425 * @add: true adds a filter, false removes it 426 * @ipv4: true is v4, false is v6 427 * 428 * Returns 0 if the filters were successfully added or removed 429 **/ 430 static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi, 431 struct i40e_fdir_filter *fd_data, 432 bool add, 433 bool ipv4) 434 { 435 struct i40e_pf *pf = vsi->back; 436 u8 *raw_packet; 437 int ret; 438 439 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 440 if (!raw_packet) 441 return -ENOMEM; 442 443 i40e_create_dummy_tcp_packet(raw_packet, ipv4, IPPROTO_TCP, fd_data); 444 if (ipv4) 445 ret = i40e_prepare_fdir_filter 446 (pf, fd_data, add, raw_packet, 447 I40E_TCPIP_DUMMY_PACKET_LEN, 448 LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP); 449 else 450 ret = i40e_prepare_fdir_filter 451 (pf, fd_data, add, raw_packet, 452 I40E_TCPIP6_DUMMY_PACKET_LEN, 453 LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP); 454 455 if (ret) { 456 kfree(raw_packet); 457 return ret; 458 } 459 460 i40e_change_filter_num(ipv4, add, &pf->fd_tcp4_filter_cnt, 461 &pf->fd_tcp6_filter_cnt); 462 463 if (add) { 464 if (test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags) && 465 I40E_DEBUG_FD & pf->hw.debug_mask) 466 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); 467 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); 468 } 469 return 0; 470 } 471 472 #define I40E_SCTPIP_DUMMY_PACKET_LEN 46 473 #define I40E_SCTPIP6_DUMMY_PACKET_LEN 66 474 /** 475 * i40e_add_del_fdir_sctp - Add/Remove SCTPv4 Flow Director filters for 476 * a specific flow spec 477 * @vsi: pointer to the targeted VSI 478 * @fd_data: the flow director data required for the FDir descriptor 479 * @add: true adds a filter, false removes it 480 * @ipv4: true is v4, false is v6 481 * 482 * Returns 0 if the filters were successfully added or removed 483 **/ 484 static int i40e_add_del_fdir_sctp(struct i40e_vsi *vsi, 485 struct i40e_fdir_filter *fd_data, 486 bool add, 487 bool ipv4) 488 { 489 struct i40e_pf *pf = vsi->back; 490 u8 *raw_packet; 491 int ret; 492 493 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 494 if (!raw_packet) 495 return -ENOMEM; 496 497 i40e_create_dummy_sctp_packet(raw_packet, ipv4, IPPROTO_SCTP, fd_data); 498 499 if (ipv4) 500 ret = i40e_prepare_fdir_filter 501 (pf, fd_data, add, raw_packet, 502 I40E_SCTPIP_DUMMY_PACKET_LEN, 503 LIBIE_FILTER_PCTYPE_NONF_IPV4_SCTP); 504 else 505 ret = i40e_prepare_fdir_filter 506 (pf, fd_data, add, raw_packet, 507 I40E_SCTPIP6_DUMMY_PACKET_LEN, 508 LIBIE_FILTER_PCTYPE_NONF_IPV6_SCTP); 509 510 if (ret) { 511 kfree(raw_packet); 512 return ret; 513 } 514 515 i40e_change_filter_num(ipv4, add, &pf->fd_sctp4_filter_cnt, 516 &pf->fd_sctp6_filter_cnt); 517 518 return 0; 519 } 520 521 #define I40E_IP_DUMMY_PACKET_LEN 34 522 #define I40E_IP6_DUMMY_PACKET_LEN 54 523 /** 524 * i40e_add_del_fdir_ip - Add/Remove IPv4 Flow Director filters for 525 * a specific flow spec 526 * @vsi: pointer to the targeted VSI 527 * @fd_data: the flow director data required for the FDir descriptor 528 * @add: true adds a filter, false removes it 529 * @ipv4: true is v4, false is v6 530 * 531 * Returns 0 if the filters were successfully added or removed 532 **/ 533 static int i40e_add_del_fdir_ip(struct i40e_vsi *vsi, 534 struct i40e_fdir_filter *fd_data, 535 bool add, 536 bool ipv4) 537 { 538 struct i40e_pf *pf = vsi->back; 539 int payload_offset; 540 u8 *raw_packet; 541 int iter_start; 542 int iter_end; 543 int ret; 544 int i; 545 546 if (ipv4) { 547 iter_start = LIBIE_FILTER_PCTYPE_NONF_IPV4_OTHER; 548 iter_end = LIBIE_FILTER_PCTYPE_FRAG_IPV4; 549 } else { 550 iter_start = LIBIE_FILTER_PCTYPE_NONF_IPV6_OTHER; 551 iter_end = LIBIE_FILTER_PCTYPE_FRAG_IPV6; 552 } 553 554 for (i = iter_start; i <= iter_end; i++) { 555 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 556 if (!raw_packet) 557 return -ENOMEM; 558 559 /* IPv6 no header option differs from IPv4 */ 560 (void)i40e_create_dummy_packet 561 (raw_packet, ipv4, (ipv4) ? IPPROTO_IP : IPPROTO_NONE, 562 fd_data); 563 564 payload_offset = (ipv4) ? I40E_IP_DUMMY_PACKET_LEN : 565 I40E_IP6_DUMMY_PACKET_LEN; 566 ret = i40e_prepare_fdir_filter(pf, fd_data, add, raw_packet, 567 payload_offset, i); 568 if (ret) 569 goto err; 570 } 571 572 i40e_change_filter_num(ipv4, add, &pf->fd_ip4_filter_cnt, 573 &pf->fd_ip6_filter_cnt); 574 575 return 0; 576 err: 577 kfree(raw_packet); 578 return ret; 579 } 580 581 /** 582 * i40e_add_del_fdir - Build raw packets to add/del fdir filter 583 * @vsi: pointer to the targeted VSI 584 * @input: filter to add or delete 585 * @add: true adds a filter, false removes it 586 * 587 **/ 588 int i40e_add_del_fdir(struct i40e_vsi *vsi, 589 struct i40e_fdir_filter *input, bool add) 590 { 591 enum ip_ver { ipv6 = 0, ipv4 = 1 }; 592 struct i40e_pf *pf = vsi->back; 593 int ret; 594 595 switch (input->flow_type & ~FLOW_EXT) { 596 case TCP_V4_FLOW: 597 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4); 598 break; 599 case UDP_V4_FLOW: 600 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4); 601 break; 602 case SCTP_V4_FLOW: 603 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4); 604 break; 605 case TCP_V6_FLOW: 606 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6); 607 break; 608 case UDP_V6_FLOW: 609 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6); 610 break; 611 case SCTP_V6_FLOW: 612 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6); 613 break; 614 case IP_USER_FLOW: 615 switch (input->ipl4_proto) { 616 case IPPROTO_TCP: 617 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4); 618 break; 619 case IPPROTO_UDP: 620 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4); 621 break; 622 case IPPROTO_SCTP: 623 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4); 624 break; 625 case IPPROTO_IP: 626 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv4); 627 break; 628 default: 629 /* We cannot support masking based on protocol */ 630 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n", 631 input->ipl4_proto); 632 return -EINVAL; 633 } 634 break; 635 case IPV6_USER_FLOW: 636 switch (input->ipl4_proto) { 637 case IPPROTO_TCP: 638 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6); 639 break; 640 case IPPROTO_UDP: 641 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6); 642 break; 643 case IPPROTO_SCTP: 644 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6); 645 break; 646 case IPPROTO_IP: 647 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv6); 648 break; 649 default: 650 /* We cannot support masking based on protocol */ 651 dev_info(&pf->pdev->dev, "Unsupported IPv6 protocol 0x%02x\n", 652 input->ipl4_proto); 653 return -EINVAL; 654 } 655 break; 656 default: 657 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n", 658 input->flow_type); 659 return -EINVAL; 660 } 661 662 /* The buffer allocated here will be normally be freed by 663 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit 664 * completion. In the event of an error adding the buffer to the FDIR 665 * ring, it will immediately be freed. It may also be freed by 666 * i40e_clean_tx_ring() when closing the VSI. 667 */ 668 return ret; 669 } 670 671 /** 672 * i40e_fd_handle_status - check the Programming Status for FD 673 * @rx_ring: the Rx ring for this descriptor 674 * @qword0_raw: qword0 675 * @qword1: qword1 after le_to_cpu 676 * @prog_id: the id originally used for programming 677 * 678 * This is used to verify if the FD programming or invalidation 679 * requested by SW to the HW is successful or not and take actions accordingly. 680 **/ 681 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw, 682 u64 qword1, u8 prog_id) 683 { 684 struct i40e_pf *pf = rx_ring->vsi->back; 685 struct pci_dev *pdev = pf->pdev; 686 struct i40e_16b_rx_wb_qw0 *qw0; 687 u32 fcnt_prog, fcnt_avail; 688 u32 error; 689 690 qw0 = (struct i40e_16b_rx_wb_qw0 *)&qword0_raw; 691 error = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK, qword1); 692 693 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { 694 pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id); 695 if (qw0->hi_dword.fd_id != 0 || 696 (I40E_DEBUG_FD & pf->hw.debug_mask)) 697 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", 698 pf->fd_inv); 699 700 /* Check if the programming error is for ATR. 701 * If so, auto disable ATR and set a state for 702 * flush in progress. Next time we come here if flush is in 703 * progress do nothing, once flush is complete the state will 704 * be cleared. 705 */ 706 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) 707 return; 708 709 pf->fd_add_err++; 710 /* store the current atr filter count */ 711 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); 712 713 if (qw0->hi_dword.fd_id == 0 && 714 test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) { 715 /* These set_bit() calls aren't atomic with the 716 * test_bit() here, but worse case we potentially 717 * disable ATR and queue a flush right after SB 718 * support is re-enabled. That shouldn't cause an 719 * issue in practice 720 */ 721 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); 722 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); 723 } 724 725 /* filter programming failed most likely due to table full */ 726 fcnt_prog = i40e_get_global_fd_count(pf); 727 fcnt_avail = pf->fdir_pf_filter_count; 728 /* If ATR is running fcnt_prog can quickly change, 729 * if we are very close to full, it makes sense to disable 730 * FD ATR/SB and then re-enable it when there is room. 731 */ 732 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { 733 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags) && 734 !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED, 735 pf->state)) 736 if (I40E_DEBUG_FD & pf->hw.debug_mask) 737 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); 738 } 739 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { 740 if (I40E_DEBUG_FD & pf->hw.debug_mask) 741 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", 742 qw0->hi_dword.fd_id); 743 } 744 } 745 746 /** 747 * i40e_unmap_and_free_tx_resource - Release a Tx buffer 748 * @ring: the ring that owns the buffer 749 * @tx_buffer: the buffer to free 750 **/ 751 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, 752 struct i40e_tx_buffer *tx_buffer) 753 { 754 if (tx_buffer->skb) { 755 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) 756 kfree(tx_buffer->raw_buf); 757 else if (ring_is_xdp(ring)) 758 xdp_return_frame(tx_buffer->xdpf); 759 else 760 dev_kfree_skb_any(tx_buffer->skb); 761 if (dma_unmap_len(tx_buffer, len)) 762 dma_unmap_single(ring->dev, 763 dma_unmap_addr(tx_buffer, dma), 764 dma_unmap_len(tx_buffer, len), 765 DMA_TO_DEVICE); 766 } else if (dma_unmap_len(tx_buffer, len)) { 767 dma_unmap_page(ring->dev, 768 dma_unmap_addr(tx_buffer, dma), 769 dma_unmap_len(tx_buffer, len), 770 DMA_TO_DEVICE); 771 } 772 773 tx_buffer->next_to_watch = NULL; 774 tx_buffer->skb = NULL; 775 dma_unmap_len_set(tx_buffer, len, 0); 776 /* tx_buffer must be completely set up in the transmit path */ 777 } 778 779 /** 780 * i40e_clean_tx_ring - Free any empty Tx buffers 781 * @tx_ring: ring to be cleaned 782 **/ 783 void i40e_clean_tx_ring(struct i40e_ring *tx_ring) 784 { 785 unsigned long bi_size; 786 u16 i; 787 788 if (ring_is_xdp(tx_ring) && tx_ring->xsk_pool) { 789 i40e_xsk_clean_tx_ring(tx_ring); 790 } else { 791 /* ring already cleared, nothing to do */ 792 if (!tx_ring->tx_bi) 793 return; 794 795 /* Free all the Tx ring sk_buffs */ 796 for (i = 0; i < tx_ring->count; i++) 797 i40e_unmap_and_free_tx_resource(tx_ring, 798 &tx_ring->tx_bi[i]); 799 } 800 801 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 802 memset(tx_ring->tx_bi, 0, bi_size); 803 804 /* Zero out the descriptor ring */ 805 memset(tx_ring->desc, 0, tx_ring->size); 806 807 tx_ring->next_to_use = 0; 808 tx_ring->next_to_clean = 0; 809 810 if (!tx_ring->netdev) 811 return; 812 813 /* cleanup Tx queue statistics */ 814 netdev_tx_reset_queue(txring_txq(tx_ring)); 815 } 816 817 /** 818 * i40e_free_tx_resources - Free Tx resources per queue 819 * @tx_ring: Tx descriptor ring for a specific queue 820 * 821 * Free all transmit software resources 822 **/ 823 void i40e_free_tx_resources(struct i40e_ring *tx_ring) 824 { 825 i40e_clean_tx_ring(tx_ring); 826 kfree(tx_ring->tx_bi); 827 tx_ring->tx_bi = NULL; 828 829 if (tx_ring->desc) { 830 dma_free_coherent(tx_ring->dev, tx_ring->size, 831 tx_ring->desc, tx_ring->dma); 832 tx_ring->desc = NULL; 833 } 834 } 835 836 /** 837 * i40e_get_tx_pending - how many tx descriptors not processed 838 * @ring: the ring of descriptors 839 * @in_sw: use SW variables 840 * 841 * Since there is no access to the ring head register 842 * in XL710, we need to use our local copies 843 **/ 844 u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw) 845 { 846 u32 head, tail; 847 848 if (!in_sw) { 849 head = i40e_get_head(ring); 850 tail = readl(ring->tail); 851 } else { 852 head = ring->next_to_clean; 853 tail = ring->next_to_use; 854 } 855 856 if (head != tail) 857 return (head < tail) ? 858 tail - head : (tail + ring->count - head); 859 860 return 0; 861 } 862 863 /** 864 * i40e_detect_recover_hung - Function to detect and recover hung_queues 865 * @pf: pointer to PF struct 866 * 867 * LAN VSI has netdev and netdev has TX queues. This function is to check 868 * each of those TX queues if they are hung, trigger recovery by issuing 869 * SW interrupt. 870 **/ 871 void i40e_detect_recover_hung(struct i40e_pf *pf) 872 { 873 struct i40e_vsi *vsi = i40e_pf_get_main_vsi(pf); 874 struct i40e_ring *tx_ring = NULL; 875 struct net_device *netdev; 876 unsigned int i; 877 int packets; 878 879 if (!vsi) 880 return; 881 882 if (test_bit(__I40E_VSI_DOWN, vsi->state)) 883 return; 884 885 netdev = vsi->netdev; 886 if (!netdev) 887 return; 888 889 if (!netif_carrier_ok(netdev)) 890 return; 891 892 for (i = 0; i < vsi->num_queue_pairs; i++) { 893 tx_ring = vsi->tx_rings[i]; 894 if (tx_ring && tx_ring->desc) { 895 /* If packet counter has not changed the queue is 896 * likely stalled, so force an interrupt for this 897 * queue. 898 * 899 * prev_pkt_ctr would be negative if there was no 900 * pending work. 901 */ 902 packets = tx_ring->stats.packets & INT_MAX; 903 if (tx_ring->tx_stats.prev_pkt_ctr == packets) { 904 i40e_force_wb(vsi, tx_ring->q_vector); 905 continue; 906 } 907 908 /* Memory barrier between read of packet count and call 909 * to i40e_get_tx_pending() 910 */ 911 smp_rmb(); 912 tx_ring->tx_stats.prev_pkt_ctr = 913 i40e_get_tx_pending(tx_ring, true) ? packets : -1; 914 } 915 } 916 } 917 918 /** 919 * i40e_clean_tx_irq - Reclaim resources after transmit completes 920 * @vsi: the VSI we care about 921 * @tx_ring: Tx ring to clean 922 * @napi_budget: Used to determine if we are in netpoll 923 * @tx_cleaned: Out parameter set to the number of TXes cleaned 924 * 925 * Returns true if there's any budget left (e.g. the clean is finished) 926 **/ 927 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, 928 struct i40e_ring *tx_ring, int napi_budget, 929 unsigned int *tx_cleaned) 930 { 931 int i = tx_ring->next_to_clean; 932 struct i40e_tx_buffer *tx_buf; 933 struct i40e_tx_desc *tx_head; 934 struct i40e_tx_desc *tx_desc; 935 unsigned int total_bytes = 0, total_packets = 0; 936 unsigned int budget = vsi->work_limit; 937 938 tx_buf = &tx_ring->tx_bi[i]; 939 tx_desc = I40E_TX_DESC(tx_ring, i); 940 i -= tx_ring->count; 941 942 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); 943 944 do { 945 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; 946 947 /* if next_to_watch is not set then there is no work pending */ 948 if (!eop_desc) 949 break; 950 951 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); 952 /* we have caught up to head, no work left to do */ 953 if (tx_head == tx_desc) 954 break; 955 956 /* clear next_to_watch to prevent false hangs */ 957 tx_buf->next_to_watch = NULL; 958 959 /* update the statistics for this packet */ 960 total_bytes += tx_buf->bytecount; 961 total_packets += tx_buf->gso_segs; 962 963 /* free the skb/XDP data */ 964 if (ring_is_xdp(tx_ring)) 965 xdp_return_frame(tx_buf->xdpf); 966 else 967 napi_consume_skb(tx_buf->skb, napi_budget); 968 969 /* unmap skb header data */ 970 dma_unmap_single(tx_ring->dev, 971 dma_unmap_addr(tx_buf, dma), 972 dma_unmap_len(tx_buf, len), 973 DMA_TO_DEVICE); 974 975 /* clear tx_buffer data */ 976 tx_buf->skb = NULL; 977 dma_unmap_len_set(tx_buf, len, 0); 978 979 /* unmap remaining buffers */ 980 while (tx_desc != eop_desc) { 981 i40e_trace(clean_tx_irq_unmap, 982 tx_ring, tx_desc, tx_buf); 983 984 tx_buf++; 985 tx_desc++; 986 i++; 987 if (unlikely(!i)) { 988 i -= tx_ring->count; 989 tx_buf = tx_ring->tx_bi; 990 tx_desc = I40E_TX_DESC(tx_ring, 0); 991 } 992 993 /* unmap any remaining paged data */ 994 if (dma_unmap_len(tx_buf, len)) { 995 dma_unmap_page(tx_ring->dev, 996 dma_unmap_addr(tx_buf, dma), 997 dma_unmap_len(tx_buf, len), 998 DMA_TO_DEVICE); 999 dma_unmap_len_set(tx_buf, len, 0); 1000 } 1001 } 1002 1003 /* move us one more past the eop_desc for start of next pkt */ 1004 tx_buf++; 1005 tx_desc++; 1006 i++; 1007 if (unlikely(!i)) { 1008 i -= tx_ring->count; 1009 tx_buf = tx_ring->tx_bi; 1010 tx_desc = I40E_TX_DESC(tx_ring, 0); 1011 } 1012 1013 prefetch(tx_desc); 1014 1015 /* update budget accounting */ 1016 budget--; 1017 } while (likely(budget)); 1018 1019 i += tx_ring->count; 1020 tx_ring->next_to_clean = i; 1021 i40e_update_tx_stats(tx_ring, total_packets, total_bytes); 1022 i40e_arm_wb(tx_ring, vsi, budget); 1023 1024 if (ring_is_xdp(tx_ring)) 1025 return !!budget; 1026 1027 /* notify netdev of completed buffers */ 1028 netdev_tx_completed_queue(txring_txq(tx_ring), 1029 total_packets, total_bytes); 1030 1031 #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2)) 1032 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1033 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 1034 /* Make sure that anybody stopping the queue after this 1035 * sees the new next_to_clean. 1036 */ 1037 smp_mb(); 1038 if (__netif_subqueue_stopped(tx_ring->netdev, 1039 tx_ring->queue_index) && 1040 !test_bit(__I40E_VSI_DOWN, vsi->state)) { 1041 netif_wake_subqueue(tx_ring->netdev, 1042 tx_ring->queue_index); 1043 ++tx_ring->tx_stats.restart_queue; 1044 } 1045 } 1046 1047 *tx_cleaned = total_packets; 1048 return !!budget; 1049 } 1050 1051 /** 1052 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled 1053 * @vsi: the VSI we care about 1054 * @q_vector: the vector on which to enable writeback 1055 * 1056 **/ 1057 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, 1058 struct i40e_q_vector *q_vector) 1059 { 1060 u16 flags = q_vector->tx.ring[0].flags; 1061 u32 val; 1062 1063 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) 1064 return; 1065 1066 if (q_vector->arm_wb_state) 1067 return; 1068 1069 if (test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) { 1070 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | 1071 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ 1072 1073 wr32(&vsi->back->hw, 1074 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), 1075 val); 1076 } else { 1077 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | 1078 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ 1079 1080 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 1081 } 1082 q_vector->arm_wb_state = true; 1083 } 1084 1085 /** 1086 * i40e_force_wb - Issue SW Interrupt so HW does a wb 1087 * @vsi: the VSI we care about 1088 * @q_vector: the vector on which to force writeback 1089 * 1090 **/ 1091 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) 1092 { 1093 if (test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) { 1094 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1095 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ 1096 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 1097 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; 1098 /* allow 00 to be written to the index */ 1099 1100 wr32(&vsi->back->hw, 1101 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val); 1102 } else { 1103 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | 1104 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ 1105 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | 1106 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; 1107 /* allow 00 to be written to the index */ 1108 1109 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 1110 } 1111 } 1112 1113 static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector, 1114 struct i40e_ring_container *rc) 1115 { 1116 return &q_vector->rx == rc; 1117 } 1118 1119 static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector) 1120 { 1121 unsigned int divisor; 1122 1123 switch (q_vector->vsi->back->hw.phy.link_info.link_speed) { 1124 case I40E_LINK_SPEED_40GB: 1125 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024; 1126 break; 1127 case I40E_LINK_SPEED_25GB: 1128 case I40E_LINK_SPEED_20GB: 1129 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512; 1130 break; 1131 default: 1132 case I40E_LINK_SPEED_10GB: 1133 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256; 1134 break; 1135 case I40E_LINK_SPEED_1GB: 1136 case I40E_LINK_SPEED_100MB: 1137 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32; 1138 break; 1139 } 1140 1141 return divisor; 1142 } 1143 1144 /** 1145 * i40e_update_itr - update the dynamic ITR value based on statistics 1146 * @q_vector: structure containing interrupt and ring information 1147 * @rc: structure containing ring performance data 1148 * 1149 * Stores a new ITR value based on packets and byte 1150 * counts during the last interrupt. The advantage of per interrupt 1151 * computation is faster updates and more accurate ITR for the current 1152 * traffic pattern. Constants in this function were computed 1153 * based on theoretical maximum wire speed and thresholds were set based 1154 * on testing data as well as attempting to minimize response time 1155 * while increasing bulk throughput. 1156 **/ 1157 static void i40e_update_itr(struct i40e_q_vector *q_vector, 1158 struct i40e_ring_container *rc) 1159 { 1160 unsigned int avg_wire_size, packets, bytes, itr; 1161 unsigned long next_update = jiffies; 1162 1163 /* If we don't have any rings just leave ourselves set for maximum 1164 * possible latency so we take ourselves out of the equation. 1165 */ 1166 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting)) 1167 return; 1168 1169 /* For Rx we want to push the delay up and default to low latency. 1170 * for Tx we want to pull the delay down and default to high latency. 1171 */ 1172 itr = i40e_container_is_rx(q_vector, rc) ? 1173 I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY : 1174 I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY; 1175 1176 /* If we didn't update within up to 1 - 2 jiffies we can assume 1177 * that either packets are coming in so slow there hasn't been 1178 * any work, or that there is so much work that NAPI is dealing 1179 * with interrupt moderation and we don't need to do anything. 1180 */ 1181 if (time_after(next_update, rc->next_update)) 1182 goto clear_counts; 1183 1184 /* If itr_countdown is set it means we programmed an ITR within 1185 * the last 4 interrupt cycles. This has a side effect of us 1186 * potentially firing an early interrupt. In order to work around 1187 * this we need to throw out any data received for a few 1188 * interrupts following the update. 1189 */ 1190 if (q_vector->itr_countdown) { 1191 itr = rc->target_itr; 1192 goto clear_counts; 1193 } 1194 1195 packets = rc->total_packets; 1196 bytes = rc->total_bytes; 1197 1198 if (i40e_container_is_rx(q_vector, rc)) { 1199 /* If Rx there are 1 to 4 packets and bytes are less than 1200 * 9000 assume insufficient data to use bulk rate limiting 1201 * approach unless Tx is already in bulk rate limiting. We 1202 * are likely latency driven. 1203 */ 1204 if (packets && packets < 4 && bytes < 9000 && 1205 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) { 1206 itr = I40E_ITR_ADAPTIVE_LATENCY; 1207 goto adjust_by_size; 1208 } 1209 } else if (packets < 4) { 1210 /* If we have Tx and Rx ITR maxed and Tx ITR is running in 1211 * bulk mode and we are receiving 4 or fewer packets just 1212 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so 1213 * that the Rx can relax. 1214 */ 1215 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS && 1216 (q_vector->rx.target_itr & I40E_ITR_MASK) == 1217 I40E_ITR_ADAPTIVE_MAX_USECS) 1218 goto clear_counts; 1219 } else if (packets > 32) { 1220 /* If we have processed over 32 packets in a single interrupt 1221 * for Tx assume we need to switch over to "bulk" mode. 1222 */ 1223 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY; 1224 } 1225 1226 /* We have no packets to actually measure against. This means 1227 * either one of the other queues on this vector is active or 1228 * we are a Tx queue doing TSO with too high of an interrupt rate. 1229 * 1230 * Between 4 and 56 we can assume that our current interrupt delay 1231 * is only slightly too low. As such we should increase it by a small 1232 * fixed amount. 1233 */ 1234 if (packets < 56) { 1235 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC; 1236 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { 1237 itr &= I40E_ITR_ADAPTIVE_LATENCY; 1238 itr += I40E_ITR_ADAPTIVE_MAX_USECS; 1239 } 1240 goto clear_counts; 1241 } 1242 1243 if (packets <= 256) { 1244 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr); 1245 itr &= I40E_ITR_MASK; 1246 1247 /* Between 56 and 112 is our "goldilocks" zone where we are 1248 * working out "just right". Just report that our current 1249 * ITR is good for us. 1250 */ 1251 if (packets <= 112) 1252 goto clear_counts; 1253 1254 /* If packet count is 128 or greater we are likely looking 1255 * at a slight overrun of the delay we want. Try halving 1256 * our delay to see if that will cut the number of packets 1257 * in half per interrupt. 1258 */ 1259 itr /= 2; 1260 itr &= I40E_ITR_MASK; 1261 if (itr < I40E_ITR_ADAPTIVE_MIN_USECS) 1262 itr = I40E_ITR_ADAPTIVE_MIN_USECS; 1263 1264 goto clear_counts; 1265 } 1266 1267 /* The paths below assume we are dealing with a bulk ITR since 1268 * number of packets is greater than 256. We are just going to have 1269 * to compute a value and try to bring the count under control, 1270 * though for smaller packet sizes there isn't much we can do as 1271 * NAPI polling will likely be kicking in sooner rather than later. 1272 */ 1273 itr = I40E_ITR_ADAPTIVE_BULK; 1274 1275 adjust_by_size: 1276 /* If packet counts are 256 or greater we can assume we have a gross 1277 * overestimation of what the rate should be. Instead of trying to fine 1278 * tune it just use the formula below to try and dial in an exact value 1279 * give the current packet size of the frame. 1280 */ 1281 avg_wire_size = bytes / packets; 1282 1283 /* The following is a crude approximation of: 1284 * wmem_default / (size + overhead) = desired_pkts_per_int 1285 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 1286 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 1287 * 1288 * Assuming wmem_default is 212992 and overhead is 640 bytes per 1289 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 1290 * formula down to 1291 * 1292 * (170 * (size + 24)) / (size + 640) = ITR 1293 * 1294 * We first do some math on the packet size and then finally bitshift 1295 * by 8 after rounding up. We also have to account for PCIe link speed 1296 * difference as ITR scales based on this. 1297 */ 1298 if (avg_wire_size <= 60) { 1299 /* Start at 250k ints/sec */ 1300 avg_wire_size = 4096; 1301 } else if (avg_wire_size <= 380) { 1302 /* 250K ints/sec to 60K ints/sec */ 1303 avg_wire_size *= 40; 1304 avg_wire_size += 1696; 1305 } else if (avg_wire_size <= 1084) { 1306 /* 60K ints/sec to 36K ints/sec */ 1307 avg_wire_size *= 15; 1308 avg_wire_size += 11452; 1309 } else if (avg_wire_size <= 1980) { 1310 /* 36K ints/sec to 30K ints/sec */ 1311 avg_wire_size *= 5; 1312 avg_wire_size += 22420; 1313 } else { 1314 /* plateau at a limit of 30K ints/sec */ 1315 avg_wire_size = 32256; 1316 } 1317 1318 /* If we are in low latency mode halve our delay which doubles the 1319 * rate to somewhere between 100K to 16K ints/sec 1320 */ 1321 if (itr & I40E_ITR_ADAPTIVE_LATENCY) 1322 avg_wire_size /= 2; 1323 1324 /* Resultant value is 256 times larger than it needs to be. This 1325 * gives us room to adjust the value as needed to either increase 1326 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 1327 * 1328 * Use addition as we have already recorded the new latency flag 1329 * for the ITR value. 1330 */ 1331 itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) * 1332 I40E_ITR_ADAPTIVE_MIN_INC; 1333 1334 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { 1335 itr &= I40E_ITR_ADAPTIVE_LATENCY; 1336 itr += I40E_ITR_ADAPTIVE_MAX_USECS; 1337 } 1338 1339 clear_counts: 1340 /* write back value */ 1341 rc->target_itr = itr; 1342 1343 /* next update should occur within next jiffy */ 1344 rc->next_update = next_update + 1; 1345 1346 rc->total_bytes = 0; 1347 rc->total_packets = 0; 1348 } 1349 1350 static struct i40e_rx_buffer *i40e_rx_bi(struct i40e_ring *rx_ring, u32 idx) 1351 { 1352 return &rx_ring->rx_bi[idx]; 1353 } 1354 1355 /** 1356 * i40e_reuse_rx_page - page flip buffer and store it back on the ring 1357 * @rx_ring: rx descriptor ring to store buffers on 1358 * @old_buff: donor buffer to have page reused 1359 * 1360 * Synchronizes page for reuse by the adapter 1361 **/ 1362 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, 1363 struct i40e_rx_buffer *old_buff) 1364 { 1365 struct i40e_rx_buffer *new_buff; 1366 u16 nta = rx_ring->next_to_alloc; 1367 1368 new_buff = i40e_rx_bi(rx_ring, nta); 1369 1370 /* update, and store next to alloc */ 1371 nta++; 1372 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1373 1374 /* transfer page from old buffer to new buffer */ 1375 new_buff->dma = old_buff->dma; 1376 new_buff->page = old_buff->page; 1377 new_buff->page_offset = old_buff->page_offset; 1378 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1379 1380 /* clear contents of buffer_info */ 1381 old_buff->page = NULL; 1382 } 1383 1384 /** 1385 * i40e_clean_programming_status - clean the programming status descriptor 1386 * @rx_ring: the rx ring that has this descriptor 1387 * @qword0_raw: qword0 1388 * @qword1: qword1 representing status_error_len in CPU ordering 1389 * 1390 * Flow director should handle FD_FILTER_STATUS to check its filter programming 1391 * status being successful or not and take actions accordingly. FCoE should 1392 * handle its context/filter programming/invalidation status and take actions. 1393 * 1394 * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL. 1395 **/ 1396 void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw, 1397 u64 qword1) 1398 { 1399 u8 id; 1400 1401 id = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK, qword1); 1402 1403 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) 1404 i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id); 1405 } 1406 1407 /** 1408 * i40e_setup_tx_descriptors - Allocate the Tx descriptors 1409 * @tx_ring: the tx ring to set up 1410 * 1411 * Return 0 on success, negative on error 1412 **/ 1413 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) 1414 { 1415 struct device *dev = tx_ring->dev; 1416 int bi_size; 1417 1418 if (!dev) 1419 return -ENOMEM; 1420 1421 /* warn if we are about to overwrite the pointer */ 1422 WARN_ON(tx_ring->tx_bi); 1423 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 1424 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); 1425 if (!tx_ring->tx_bi) 1426 goto err; 1427 1428 u64_stats_init(&tx_ring->syncp); 1429 1430 /* round up to nearest 4K */ 1431 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); 1432 /* add u32 for head writeback, align after this takes care of 1433 * guaranteeing this is at least one cache line in size 1434 */ 1435 tx_ring->size += sizeof(u32); 1436 tx_ring->size = ALIGN(tx_ring->size, 4096); 1437 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 1438 &tx_ring->dma, GFP_KERNEL); 1439 if (!tx_ring->desc) { 1440 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 1441 tx_ring->size); 1442 goto err; 1443 } 1444 1445 tx_ring->next_to_use = 0; 1446 tx_ring->next_to_clean = 0; 1447 tx_ring->tx_stats.prev_pkt_ctr = -1; 1448 return 0; 1449 1450 err: 1451 kfree(tx_ring->tx_bi); 1452 tx_ring->tx_bi = NULL; 1453 return -ENOMEM; 1454 } 1455 1456 static void i40e_clear_rx_bi(struct i40e_ring *rx_ring) 1457 { 1458 memset(rx_ring->rx_bi, 0, sizeof(*rx_ring->rx_bi) * rx_ring->count); 1459 } 1460 1461 /** 1462 * i40e_clean_rx_ring - Free Rx buffers 1463 * @rx_ring: ring to be cleaned 1464 **/ 1465 void i40e_clean_rx_ring(struct i40e_ring *rx_ring) 1466 { 1467 u16 i; 1468 1469 /* ring already cleared, nothing to do */ 1470 if (!rx_ring->rx_bi) 1471 return; 1472 1473 if (rx_ring->xsk_pool) { 1474 i40e_xsk_clean_rx_ring(rx_ring); 1475 goto skip_free; 1476 } 1477 1478 /* Free all the Rx ring sk_buffs */ 1479 for (i = 0; i < rx_ring->count; i++) { 1480 struct i40e_rx_buffer *rx_bi = i40e_rx_bi(rx_ring, i); 1481 1482 if (!rx_bi->page) 1483 continue; 1484 1485 /* Invalidate cache lines that may have been written to by 1486 * device so that we avoid corrupting memory. 1487 */ 1488 dma_sync_single_range_for_cpu(rx_ring->dev, 1489 rx_bi->dma, 1490 rx_bi->page_offset, 1491 rx_ring->rx_buf_len, 1492 DMA_FROM_DEVICE); 1493 1494 /* free resources associated with mapping */ 1495 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, 1496 i40e_rx_pg_size(rx_ring), 1497 DMA_FROM_DEVICE, 1498 I40E_RX_DMA_ATTR); 1499 1500 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); 1501 1502 rx_bi->page = NULL; 1503 rx_bi->page_offset = 0; 1504 } 1505 1506 skip_free: 1507 if (rx_ring->xsk_pool) 1508 i40e_clear_rx_bi_zc(rx_ring); 1509 else 1510 i40e_clear_rx_bi(rx_ring); 1511 1512 /* Zero out the descriptor ring */ 1513 memset(rx_ring->desc, 0, rx_ring->size); 1514 1515 rx_ring->next_to_alloc = 0; 1516 rx_ring->next_to_clean = 0; 1517 rx_ring->next_to_process = 0; 1518 rx_ring->next_to_use = 0; 1519 } 1520 1521 /** 1522 * i40e_free_rx_resources - Free Rx resources 1523 * @rx_ring: ring to clean the resources from 1524 * 1525 * Free all receive software resources 1526 **/ 1527 void i40e_free_rx_resources(struct i40e_ring *rx_ring) 1528 { 1529 i40e_clean_rx_ring(rx_ring); 1530 if (rx_ring->vsi->type == I40E_VSI_MAIN) 1531 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 1532 rx_ring->xdp_prog = NULL; 1533 kfree(rx_ring->rx_bi); 1534 rx_ring->rx_bi = NULL; 1535 1536 if (rx_ring->desc) { 1537 dma_free_coherent(rx_ring->dev, rx_ring->size, 1538 rx_ring->desc, rx_ring->dma); 1539 rx_ring->desc = NULL; 1540 } 1541 } 1542 1543 /** 1544 * i40e_setup_rx_descriptors - Allocate Rx descriptors 1545 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1546 * 1547 * Returns 0 on success, negative on failure 1548 **/ 1549 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) 1550 { 1551 struct device *dev = rx_ring->dev; 1552 1553 u64_stats_init(&rx_ring->syncp); 1554 1555 /* Round up to nearest 4K */ 1556 rx_ring->size = rx_ring->count * sizeof(union i40e_rx_desc); 1557 rx_ring->size = ALIGN(rx_ring->size, 4096); 1558 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 1559 &rx_ring->dma, GFP_KERNEL); 1560 1561 if (!rx_ring->desc) { 1562 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 1563 rx_ring->size); 1564 return -ENOMEM; 1565 } 1566 1567 rx_ring->next_to_alloc = 0; 1568 rx_ring->next_to_clean = 0; 1569 rx_ring->next_to_process = 0; 1570 rx_ring->next_to_use = 0; 1571 1572 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog; 1573 1574 rx_ring->rx_bi = 1575 kcalloc(rx_ring->count, sizeof(*rx_ring->rx_bi), GFP_KERNEL); 1576 if (!rx_ring->rx_bi) 1577 return -ENOMEM; 1578 1579 return 0; 1580 } 1581 1582 /** 1583 * i40e_release_rx_desc - Store the new tail and head values 1584 * @rx_ring: ring to bump 1585 * @val: new head index 1586 **/ 1587 void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) 1588 { 1589 rx_ring->next_to_use = val; 1590 1591 /* update next to alloc since we have filled the ring */ 1592 rx_ring->next_to_alloc = val; 1593 1594 /* Force memory writes to complete before letting h/w 1595 * know there are new descriptors to fetch. (Only 1596 * applicable for weak-ordered memory model archs, 1597 * such as IA-64). 1598 */ 1599 wmb(); 1600 writel(val, rx_ring->tail); 1601 } 1602 1603 #if (PAGE_SIZE >= 8192) 1604 static unsigned int i40e_rx_frame_truesize(struct i40e_ring *rx_ring, 1605 unsigned int size) 1606 { 1607 unsigned int truesize; 1608 1609 truesize = rx_ring->rx_offset ? 1610 SKB_DATA_ALIGN(size + rx_ring->rx_offset) + 1611 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 1612 SKB_DATA_ALIGN(size); 1613 return truesize; 1614 } 1615 #endif 1616 1617 /** 1618 * i40e_alloc_mapped_page - recycle or make a new page 1619 * @rx_ring: ring to use 1620 * @bi: rx_buffer struct to modify 1621 * 1622 * Returns true if the page was successfully allocated or 1623 * reused. 1624 **/ 1625 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, 1626 struct i40e_rx_buffer *bi) 1627 { 1628 struct page *page = bi->page; 1629 dma_addr_t dma; 1630 1631 /* since we are recycling buffers we should seldom need to alloc */ 1632 if (likely(page)) { 1633 rx_ring->rx_stats.page_reuse_count++; 1634 return true; 1635 } 1636 1637 /* alloc new page for storage */ 1638 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring)); 1639 if (unlikely(!page)) { 1640 rx_ring->rx_stats.alloc_page_failed++; 1641 return false; 1642 } 1643 1644 rx_ring->rx_stats.page_alloc_count++; 1645 1646 /* map page for use */ 1647 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1648 i40e_rx_pg_size(rx_ring), 1649 DMA_FROM_DEVICE, 1650 I40E_RX_DMA_ATTR); 1651 1652 /* if mapping failed free memory back to system since 1653 * there isn't much point in holding memory we can't use 1654 */ 1655 if (dma_mapping_error(rx_ring->dev, dma)) { 1656 __free_pages(page, i40e_rx_pg_order(rx_ring)); 1657 rx_ring->rx_stats.alloc_page_failed++; 1658 return false; 1659 } 1660 1661 bi->dma = dma; 1662 bi->page = page; 1663 bi->page_offset = rx_ring->rx_offset; 1664 page_ref_add(page, USHRT_MAX - 1); 1665 bi->pagecnt_bias = USHRT_MAX; 1666 1667 return true; 1668 } 1669 1670 /** 1671 * i40e_alloc_rx_buffers - Replace used receive buffers 1672 * @rx_ring: ring to place buffers on 1673 * @cleaned_count: number of buffers to replace 1674 * 1675 * Returns false if all allocations were successful, true if any fail 1676 **/ 1677 bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) 1678 { 1679 u16 ntu = rx_ring->next_to_use; 1680 union i40e_rx_desc *rx_desc; 1681 struct i40e_rx_buffer *bi; 1682 1683 /* do nothing if no valid netdev defined */ 1684 if (!rx_ring->netdev || !cleaned_count) 1685 return false; 1686 1687 rx_desc = I40E_RX_DESC(rx_ring, ntu); 1688 bi = i40e_rx_bi(rx_ring, ntu); 1689 1690 do { 1691 if (!i40e_alloc_mapped_page(rx_ring, bi)) 1692 goto no_buffers; 1693 1694 /* sync the buffer for use by the device */ 1695 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1696 bi->page_offset, 1697 rx_ring->rx_buf_len, 1698 DMA_FROM_DEVICE); 1699 1700 /* Refresh the desc even if buffer_addrs didn't change 1701 * because each write-back erases this info. 1702 */ 1703 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1704 1705 rx_desc++; 1706 bi++; 1707 ntu++; 1708 if (unlikely(ntu == rx_ring->count)) { 1709 rx_desc = I40E_RX_DESC(rx_ring, 0); 1710 bi = i40e_rx_bi(rx_ring, 0); 1711 ntu = 0; 1712 } 1713 1714 /* clear the status bits for the next_to_use descriptor */ 1715 rx_desc->wb.qword1.status_error_len = 0; 1716 1717 cleaned_count--; 1718 } while (cleaned_count); 1719 1720 if (rx_ring->next_to_use != ntu) 1721 i40e_release_rx_desc(rx_ring, ntu); 1722 1723 return false; 1724 1725 no_buffers: 1726 if (rx_ring->next_to_use != ntu) 1727 i40e_release_rx_desc(rx_ring, ntu); 1728 1729 /* make sure to come back via polling to try again after 1730 * allocation failure 1731 */ 1732 return true; 1733 } 1734 1735 /** 1736 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum 1737 * @vsi: the VSI we care about 1738 * @skb: skb currently being received and modified 1739 * @rx_desc: the receive descriptor 1740 **/ 1741 static inline void i40e_rx_checksum(struct i40e_vsi *vsi, 1742 struct sk_buff *skb, 1743 union i40e_rx_desc *rx_desc) 1744 { 1745 struct libeth_rx_pt decoded; 1746 u32 rx_error, rx_status; 1747 bool ipv4, ipv6; 1748 u8 ptype; 1749 u64 qword; 1750 1751 skb->ip_summed = CHECKSUM_NONE; 1752 1753 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1754 ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword); 1755 1756 decoded = libie_rx_pt_parse(ptype); 1757 if (!libeth_rx_pt_has_checksum(vsi->netdev, decoded)) 1758 return; 1759 1760 rx_error = FIELD_GET(I40E_RXD_QW1_ERROR_MASK, qword); 1761 rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword); 1762 1763 /* did the hardware decode the packet and checksum? */ 1764 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) 1765 return; 1766 1767 ipv4 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV4; 1768 ipv6 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV6; 1769 1770 if (ipv4 && 1771 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | 1772 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) 1773 goto checksum_fail; 1774 1775 /* likely incorrect csum if alternate IP extension headers found */ 1776 if (ipv6 && 1777 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) 1778 /* don't increment checksum err here, non-fatal err */ 1779 return; 1780 1781 /* there was some L4 error, count error and punt packet to the stack */ 1782 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) 1783 goto checksum_fail; 1784 1785 /* handle packets that were not able to be checksummed due 1786 * to arrival speed, in this case the stack can compute 1787 * the csum. 1788 */ 1789 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) 1790 return; 1791 1792 /* If there is an outer header present that might contain a checksum 1793 * we need to bump the checksum level by 1 to reflect the fact that 1794 * we are indicating we validated the inner checksum. 1795 */ 1796 if (decoded.tunnel_type >= LIBETH_RX_PT_TUNNEL_IP_GRENAT) 1797 skb->csum_level = 1; 1798 1799 skb->ip_summed = CHECKSUM_UNNECESSARY; 1800 return; 1801 1802 checksum_fail: 1803 vsi->back->hw_csum_rx_error++; 1804 } 1805 1806 /** 1807 * i40e_rx_hash - set the hash value in the skb 1808 * @ring: descriptor ring 1809 * @rx_desc: specific descriptor 1810 * @skb: skb currently being received and modified 1811 * @rx_ptype: Rx packet type 1812 **/ 1813 static inline void i40e_rx_hash(struct i40e_ring *ring, 1814 union i40e_rx_desc *rx_desc, 1815 struct sk_buff *skb, 1816 u8 rx_ptype) 1817 { 1818 struct libeth_rx_pt decoded; 1819 u32 hash; 1820 const __le64 rss_mask = 1821 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << 1822 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); 1823 1824 decoded = libie_rx_pt_parse(rx_ptype); 1825 if (!libeth_rx_pt_has_hash(ring->netdev, decoded)) 1826 return; 1827 1828 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { 1829 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); 1830 libeth_rx_pt_set_hash(skb, hash, decoded); 1831 } 1832 } 1833 1834 /** 1835 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor 1836 * @rx_ring: rx descriptor ring packet is being transacted on 1837 * @rx_desc: pointer to the EOP Rx descriptor 1838 * @skb: pointer to current skb being populated 1839 * 1840 * This function checks the ring, descriptor, and packet information in 1841 * order to populate the hash, checksum, VLAN, protocol, and 1842 * other fields within the skb. 1843 **/ 1844 void i40e_process_skb_fields(struct i40e_ring *rx_ring, 1845 union i40e_rx_desc *rx_desc, struct sk_buff *skb) 1846 { 1847 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1848 u32 rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword); 1849 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK; 1850 u32 tsyn = FIELD_GET(I40E_RXD_QW1_STATUS_TSYNINDX_MASK, rx_status); 1851 u8 rx_ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword); 1852 1853 if (unlikely(tsynvalid)) 1854 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn); 1855 1856 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); 1857 1858 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); 1859 1860 skb_record_rx_queue(skb, rx_ring->queue_index); 1861 1862 if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) { 1863 __le16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1; 1864 1865 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1866 le16_to_cpu(vlan_tag)); 1867 } 1868 1869 /* modifies the skb - consumes the enet header */ 1870 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1871 } 1872 1873 /** 1874 * i40e_cleanup_headers - Correct empty headers 1875 * @rx_ring: rx descriptor ring packet is being transacted on 1876 * @skb: pointer to current skb being fixed 1877 * @rx_desc: pointer to the EOP Rx descriptor 1878 * 1879 * In addition if skb is not at least 60 bytes we need to pad it so that 1880 * it is large enough to qualify as a valid Ethernet frame. 1881 * 1882 * Returns true if an error was encountered and skb was freed. 1883 **/ 1884 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb, 1885 union i40e_rx_desc *rx_desc) 1886 1887 { 1888 /* ERR_MASK will only have valid bits if EOP set, and 1889 * what we are doing here is actually checking 1890 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in 1891 * the error field 1892 */ 1893 if (unlikely(i40e_test_staterr(rx_desc, 1894 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { 1895 dev_kfree_skb_any(skb); 1896 return true; 1897 } 1898 1899 /* if eth_skb_pad returns an error the skb was freed */ 1900 if (eth_skb_pad(skb)) 1901 return true; 1902 1903 return false; 1904 } 1905 1906 /** 1907 * i40e_can_reuse_rx_page - Determine if page can be reused for another Rx 1908 * @rx_buffer: buffer containing the page 1909 * @rx_stats: rx stats structure for the rx ring 1910 * 1911 * If page is reusable, we have a green light for calling i40e_reuse_rx_page, 1912 * which will assign the current buffer to the buffer that next_to_alloc is 1913 * pointing to; otherwise, the DMA mapping needs to be destroyed and 1914 * page freed. 1915 * 1916 * rx_stats will be updated to indicate whether the page was waived 1917 * or busy if it could not be reused. 1918 */ 1919 static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer, 1920 struct i40e_rx_queue_stats *rx_stats) 1921 { 1922 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1923 struct page *page = rx_buffer->page; 1924 1925 /* Is any reuse possible? */ 1926 if (!dev_page_is_reusable(page)) { 1927 rx_stats->page_waive_count++; 1928 return false; 1929 } 1930 1931 #if (PAGE_SIZE < 8192) 1932 /* if we are only owner of page we can reuse it */ 1933 if (unlikely((rx_buffer->page_count - pagecnt_bias) > 1)) { 1934 rx_stats->page_busy_count++; 1935 return false; 1936 } 1937 #else 1938 #define I40E_LAST_OFFSET \ 1939 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048) 1940 if (rx_buffer->page_offset > I40E_LAST_OFFSET) { 1941 rx_stats->page_busy_count++; 1942 return false; 1943 } 1944 #endif 1945 1946 /* If we have drained the page fragment pool we need to update 1947 * the pagecnt_bias and page count so that we fully restock the 1948 * number of references the driver holds. 1949 */ 1950 if (unlikely(pagecnt_bias == 1)) { 1951 page_ref_add(page, USHRT_MAX - 1); 1952 rx_buffer->pagecnt_bias = USHRT_MAX; 1953 } 1954 1955 return true; 1956 } 1957 1958 /** 1959 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region 1960 * @rx_buffer: Rx buffer to adjust 1961 * @truesize: Size of adjustment 1962 **/ 1963 static void i40e_rx_buffer_flip(struct i40e_rx_buffer *rx_buffer, 1964 unsigned int truesize) 1965 { 1966 #if (PAGE_SIZE < 8192) 1967 rx_buffer->page_offset ^= truesize; 1968 #else 1969 rx_buffer->page_offset += truesize; 1970 #endif 1971 } 1972 1973 /** 1974 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use 1975 * @rx_ring: rx descriptor ring to transact packets on 1976 * @size: size of buffer to add to skb 1977 * 1978 * This function will pull an Rx buffer from the ring and synchronize it 1979 * for use by the CPU. 1980 */ 1981 static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring, 1982 const unsigned int size) 1983 { 1984 struct i40e_rx_buffer *rx_buffer; 1985 1986 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_process); 1987 rx_buffer->page_count = 1988 #if (PAGE_SIZE < 8192) 1989 page_count(rx_buffer->page); 1990 #else 1991 0; 1992 #endif 1993 prefetch_page_address(rx_buffer->page); 1994 1995 /* we are reusing so sync this buffer for CPU use */ 1996 dma_sync_single_range_for_cpu(rx_ring->dev, 1997 rx_buffer->dma, 1998 rx_buffer->page_offset, 1999 size, 2000 DMA_FROM_DEVICE); 2001 2002 /* We have pulled a buffer for use, so decrement pagecnt_bias */ 2003 rx_buffer->pagecnt_bias--; 2004 2005 return rx_buffer; 2006 } 2007 2008 /** 2009 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free 2010 * @rx_ring: rx descriptor ring to transact packets on 2011 * @rx_buffer: rx buffer to pull data from 2012 * 2013 * This function will clean up the contents of the rx_buffer. It will 2014 * either recycle the buffer or unmap it and free the associated resources. 2015 */ 2016 static void i40e_put_rx_buffer(struct i40e_ring *rx_ring, 2017 struct i40e_rx_buffer *rx_buffer) 2018 { 2019 if (i40e_can_reuse_rx_page(rx_buffer, &rx_ring->rx_stats)) { 2020 /* hand second half of page back to the ring */ 2021 i40e_reuse_rx_page(rx_ring, rx_buffer); 2022 } else { 2023 /* we are not reusing the buffer so unmap it */ 2024 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2025 i40e_rx_pg_size(rx_ring), 2026 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); 2027 __page_frag_cache_drain(rx_buffer->page, 2028 rx_buffer->pagecnt_bias); 2029 /* clear contents of buffer_info */ 2030 rx_buffer->page = NULL; 2031 } 2032 } 2033 2034 /** 2035 * i40e_process_rx_buffs- Processing of buffers post XDP prog or on error 2036 * @rx_ring: Rx descriptor ring to transact packets on 2037 * @xdp_res: Result of the XDP program 2038 * @xdp: xdp_buff pointing to the data 2039 **/ 2040 static void i40e_process_rx_buffs(struct i40e_ring *rx_ring, int xdp_res, 2041 struct xdp_buff *xdp) 2042 { 2043 u32 nr_frags = xdp_get_shared_info_from_buff(xdp)->nr_frags; 2044 u32 next = rx_ring->next_to_clean, i = 0; 2045 struct i40e_rx_buffer *rx_buffer; 2046 2047 xdp->flags = 0; 2048 2049 while (1) { 2050 rx_buffer = i40e_rx_bi(rx_ring, next); 2051 if (++next == rx_ring->count) 2052 next = 0; 2053 2054 if (!rx_buffer->page) 2055 continue; 2056 2057 if (xdp_res != I40E_XDP_CONSUMED) 2058 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2059 else if (i++ <= nr_frags) 2060 rx_buffer->pagecnt_bias++; 2061 2062 /* EOP buffer will be put in i40e_clean_rx_irq() */ 2063 if (next == rx_ring->next_to_process) 2064 return; 2065 2066 i40e_put_rx_buffer(rx_ring, rx_buffer); 2067 } 2068 } 2069 2070 /** 2071 * i40e_construct_skb - Allocate skb and populate it 2072 * @rx_ring: rx descriptor ring to transact packets on 2073 * @xdp: xdp_buff pointing to the data 2074 * 2075 * This function allocates an skb. It then populates it with the page 2076 * data from the current receive descriptor, taking care to set up the 2077 * skb correctly. 2078 */ 2079 static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring, 2080 struct xdp_buff *xdp) 2081 { 2082 unsigned int size = xdp->data_end - xdp->data; 2083 struct i40e_rx_buffer *rx_buffer; 2084 struct skb_shared_info *sinfo; 2085 unsigned int headlen; 2086 struct sk_buff *skb; 2087 u32 nr_frags = 0; 2088 2089 /* prefetch first cache line of first page */ 2090 net_prefetch(xdp->data); 2091 2092 /* Note, we get here by enabling legacy-rx via: 2093 * 2094 * ethtool --set-priv-flags <dev> legacy-rx on 2095 * 2096 * In this mode, we currently get 0 extra XDP headroom as 2097 * opposed to having legacy-rx off, where we process XDP 2098 * packets going to stack via i40e_build_skb(). The latter 2099 * provides us currently with 192 bytes of headroom. 2100 * 2101 * For i40e_construct_skb() mode it means that the 2102 * xdp->data_meta will always point to xdp->data, since 2103 * the helper cannot expand the head. Should this ever 2104 * change in future for legacy-rx mode on, then lets also 2105 * add xdp->data_meta handling here. 2106 */ 2107 2108 /* allocate a skb to store the frags */ 2109 skb = napi_alloc_skb(&rx_ring->q_vector->napi, I40E_RX_HDR_SIZE); 2110 if (unlikely(!skb)) 2111 return NULL; 2112 2113 /* Determine available headroom for copy */ 2114 headlen = size; 2115 if (headlen > I40E_RX_HDR_SIZE) 2116 headlen = eth_get_headlen(skb->dev, xdp->data, 2117 I40E_RX_HDR_SIZE); 2118 2119 /* align pull length to size of long to optimize memcpy performance */ 2120 memcpy(__skb_put(skb, headlen), xdp->data, 2121 ALIGN(headlen, sizeof(long))); 2122 2123 if (unlikely(xdp_buff_has_frags(xdp))) { 2124 sinfo = xdp_get_shared_info_from_buff(xdp); 2125 nr_frags = sinfo->nr_frags; 2126 } 2127 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean); 2128 /* update all of the pointers */ 2129 size -= headlen; 2130 if (size) { 2131 if (unlikely(nr_frags >= MAX_SKB_FRAGS)) { 2132 dev_kfree_skb(skb); 2133 return NULL; 2134 } 2135 skb_add_rx_frag(skb, 0, rx_buffer->page, 2136 rx_buffer->page_offset + headlen, 2137 size, xdp->frame_sz); 2138 /* buffer is used by skb, update page_offset */ 2139 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2140 } else { 2141 /* buffer is unused, reset bias back to rx_buffer */ 2142 rx_buffer->pagecnt_bias++; 2143 } 2144 2145 if (unlikely(xdp_buff_has_frags(xdp))) { 2146 struct skb_shared_info *skinfo = skb_shinfo(skb); 2147 2148 memcpy(&skinfo->frags[skinfo->nr_frags], &sinfo->frags[0], 2149 sizeof(skb_frag_t) * nr_frags); 2150 2151 xdp_update_skb_shared_info(skb, skinfo->nr_frags + nr_frags, 2152 sinfo->xdp_frags_size, 2153 nr_frags * xdp->frame_sz, 2154 xdp_buff_is_frag_pfmemalloc(xdp)); 2155 2156 /* First buffer has already been processed, so bump ntc */ 2157 if (++rx_ring->next_to_clean == rx_ring->count) 2158 rx_ring->next_to_clean = 0; 2159 2160 i40e_process_rx_buffs(rx_ring, I40E_XDP_PASS, xdp); 2161 } 2162 2163 return skb; 2164 } 2165 2166 /** 2167 * i40e_build_skb - Build skb around an existing buffer 2168 * @rx_ring: Rx descriptor ring to transact packets on 2169 * @xdp: xdp_buff pointing to the data 2170 * 2171 * This function builds an skb around an existing Rx buffer, taking care 2172 * to set up the skb correctly and avoid any memcpy overhead. 2173 */ 2174 static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring, 2175 struct xdp_buff *xdp) 2176 { 2177 unsigned int metasize = xdp->data - xdp->data_meta; 2178 struct skb_shared_info *sinfo; 2179 struct sk_buff *skb; 2180 u32 nr_frags; 2181 2182 /* Prefetch first cache line of first page. If xdp->data_meta 2183 * is unused, this points exactly as xdp->data, otherwise we 2184 * likely have a consumer accessing first few bytes of meta 2185 * data, and then actual data. 2186 */ 2187 net_prefetch(xdp->data_meta); 2188 2189 if (unlikely(xdp_buff_has_frags(xdp))) { 2190 sinfo = xdp_get_shared_info_from_buff(xdp); 2191 nr_frags = sinfo->nr_frags; 2192 } 2193 2194 /* build an skb around the page buffer */ 2195 skb = napi_build_skb(xdp->data_hard_start, xdp->frame_sz); 2196 if (unlikely(!skb)) 2197 return NULL; 2198 2199 /* update pointers within the skb to store the data */ 2200 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2201 __skb_put(skb, xdp->data_end - xdp->data); 2202 if (metasize) 2203 skb_metadata_set(skb, metasize); 2204 2205 if (unlikely(xdp_buff_has_frags(xdp))) { 2206 xdp_update_skb_shared_info(skb, nr_frags, 2207 sinfo->xdp_frags_size, 2208 nr_frags * xdp->frame_sz, 2209 xdp_buff_is_frag_pfmemalloc(xdp)); 2210 2211 i40e_process_rx_buffs(rx_ring, I40E_XDP_PASS, xdp); 2212 } else { 2213 struct i40e_rx_buffer *rx_buffer; 2214 2215 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean); 2216 /* buffer is used by skb, update page_offset */ 2217 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2218 } 2219 2220 return skb; 2221 } 2222 2223 /** 2224 * i40e_is_non_eop - process handling of non-EOP buffers 2225 * @rx_ring: Rx ring being processed 2226 * @rx_desc: Rx descriptor for current buffer 2227 * 2228 * If the buffer is an EOP buffer, this function exits returning false, 2229 * otherwise return true indicating that this is in fact a non-EOP buffer. 2230 */ 2231 bool i40e_is_non_eop(struct i40e_ring *rx_ring, 2232 union i40e_rx_desc *rx_desc) 2233 { 2234 /* if we are the last buffer then there is nothing else to do */ 2235 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) 2236 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) 2237 return false; 2238 2239 rx_ring->rx_stats.non_eop_descs++; 2240 2241 return true; 2242 } 2243 2244 static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf, 2245 struct i40e_ring *xdp_ring); 2246 2247 int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring) 2248 { 2249 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2250 2251 if (unlikely(!xdpf)) 2252 return I40E_XDP_CONSUMED; 2253 2254 return i40e_xmit_xdp_ring(xdpf, xdp_ring); 2255 } 2256 2257 /** 2258 * i40e_run_xdp - run an XDP program 2259 * @rx_ring: Rx ring being processed 2260 * @xdp: XDP buffer containing the frame 2261 * @xdp_prog: XDP program to run 2262 **/ 2263 static int i40e_run_xdp(struct i40e_ring *rx_ring, struct xdp_buff *xdp, struct bpf_prog *xdp_prog) 2264 { 2265 int err, result = I40E_XDP_PASS; 2266 struct i40e_ring *xdp_ring; 2267 u32 act; 2268 2269 if (!xdp_prog) 2270 goto xdp_out; 2271 2272 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2273 2274 act = bpf_prog_run_xdp(xdp_prog, xdp); 2275 switch (act) { 2276 case XDP_PASS: 2277 break; 2278 case XDP_TX: 2279 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index]; 2280 result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring); 2281 if (result == I40E_XDP_CONSUMED) 2282 goto out_failure; 2283 break; 2284 case XDP_REDIRECT: 2285 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog); 2286 if (err) 2287 goto out_failure; 2288 result = I40E_XDP_REDIR; 2289 break; 2290 default: 2291 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act); 2292 fallthrough; 2293 case XDP_ABORTED: 2294 out_failure: 2295 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2296 fallthrough; /* handle aborts by dropping packet */ 2297 case XDP_DROP: 2298 result = I40E_XDP_CONSUMED; 2299 break; 2300 } 2301 xdp_out: 2302 return result; 2303 } 2304 2305 /** 2306 * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register 2307 * @xdp_ring: XDP Tx ring 2308 * 2309 * This function updates the XDP Tx ring tail register. 2310 **/ 2311 void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring) 2312 { 2313 /* Force memory writes to complete before letting h/w 2314 * know there are new descriptors to fetch. 2315 */ 2316 wmb(); 2317 writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail); 2318 } 2319 2320 /** 2321 * i40e_update_rx_stats - Update Rx ring statistics 2322 * @rx_ring: rx descriptor ring 2323 * @total_rx_bytes: number of bytes received 2324 * @total_rx_packets: number of packets received 2325 * 2326 * This function updates the Rx ring statistics. 2327 **/ 2328 void i40e_update_rx_stats(struct i40e_ring *rx_ring, 2329 unsigned int total_rx_bytes, 2330 unsigned int total_rx_packets) 2331 { 2332 u64_stats_update_begin(&rx_ring->syncp); 2333 rx_ring->stats.packets += total_rx_packets; 2334 rx_ring->stats.bytes += total_rx_bytes; 2335 u64_stats_update_end(&rx_ring->syncp); 2336 rx_ring->q_vector->rx.total_packets += total_rx_packets; 2337 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 2338 } 2339 2340 /** 2341 * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map 2342 * @rx_ring: Rx ring 2343 * @xdp_res: Result of the receive batch 2344 * 2345 * This function bumps XDP Tx tail and/or flush redirect map, and 2346 * should be called when a batch of packets has been processed in the 2347 * napi loop. 2348 **/ 2349 void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res) 2350 { 2351 if (xdp_res & I40E_XDP_REDIR) 2352 xdp_do_flush(); 2353 2354 if (xdp_res & I40E_XDP_TX) { 2355 struct i40e_ring *xdp_ring = 2356 rx_ring->vsi->xdp_rings[rx_ring->queue_index]; 2357 2358 i40e_xdp_ring_update_tail(xdp_ring); 2359 } 2360 } 2361 2362 /** 2363 * i40e_inc_ntp: Advance the next_to_process index 2364 * @rx_ring: Rx ring 2365 **/ 2366 static void i40e_inc_ntp(struct i40e_ring *rx_ring) 2367 { 2368 u32 ntp = rx_ring->next_to_process + 1; 2369 2370 ntp = (ntp < rx_ring->count) ? ntp : 0; 2371 rx_ring->next_to_process = ntp; 2372 prefetch(I40E_RX_DESC(rx_ring, ntp)); 2373 } 2374 2375 /** 2376 * i40e_add_xdp_frag: Add a frag to xdp_buff 2377 * @xdp: xdp_buff pointing to the data 2378 * @nr_frags: return number of buffers for the packet 2379 * @rx_buffer: rx_buffer holding data of the current frag 2380 * @size: size of data of current frag 2381 */ 2382 static int i40e_add_xdp_frag(struct xdp_buff *xdp, u32 *nr_frags, 2383 struct i40e_rx_buffer *rx_buffer, u32 size) 2384 { 2385 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2386 2387 if (!xdp_buff_has_frags(xdp)) { 2388 sinfo->nr_frags = 0; 2389 sinfo->xdp_frags_size = 0; 2390 xdp_buff_set_frags_flag(xdp); 2391 } else if (unlikely(sinfo->nr_frags >= MAX_SKB_FRAGS)) { 2392 /* Overflowing packet: All frags need to be dropped */ 2393 return -ENOMEM; 2394 } 2395 2396 __skb_fill_page_desc_noacc(sinfo, sinfo->nr_frags++, rx_buffer->page, 2397 rx_buffer->page_offset, size); 2398 2399 sinfo->xdp_frags_size += size; 2400 2401 if (page_is_pfmemalloc(rx_buffer->page)) 2402 xdp_buff_set_frag_pfmemalloc(xdp); 2403 *nr_frags = sinfo->nr_frags; 2404 2405 return 0; 2406 } 2407 2408 /** 2409 * i40e_consume_xdp_buff - Consume all the buffers of the packet and update ntc 2410 * @rx_ring: rx descriptor ring to transact packets on 2411 * @xdp: xdp_buff pointing to the data 2412 * @rx_buffer: rx_buffer of eop desc 2413 */ 2414 static void i40e_consume_xdp_buff(struct i40e_ring *rx_ring, 2415 struct xdp_buff *xdp, 2416 struct i40e_rx_buffer *rx_buffer) 2417 { 2418 i40e_process_rx_buffs(rx_ring, I40E_XDP_CONSUMED, xdp); 2419 i40e_put_rx_buffer(rx_ring, rx_buffer); 2420 rx_ring->next_to_clean = rx_ring->next_to_process; 2421 xdp->data = NULL; 2422 } 2423 2424 /** 2425 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2426 * @rx_ring: rx descriptor ring to transact packets on 2427 * @budget: Total limit on number of packets to process 2428 * @rx_cleaned: Out parameter of the number of packets processed 2429 * 2430 * This function provides a "bounce buffer" approach to Rx interrupt 2431 * processing. The advantage to this is that on systems that have 2432 * expensive overhead for IOMMU access this provides a means of avoiding 2433 * it by maintaining the mapping of the page to the system. 2434 * 2435 * Returns amount of work completed 2436 **/ 2437 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget, 2438 unsigned int *rx_cleaned) 2439 { 2440 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2441 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); 2442 u16 clean_threshold = rx_ring->count / 2; 2443 unsigned int offset = rx_ring->rx_offset; 2444 struct xdp_buff *xdp = &rx_ring->xdp; 2445 unsigned int xdp_xmit = 0; 2446 struct bpf_prog *xdp_prog; 2447 bool failure = false; 2448 int xdp_res = 0; 2449 2450 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2451 2452 while (likely(total_rx_packets < (unsigned int)budget)) { 2453 u16 ntp = rx_ring->next_to_process; 2454 struct i40e_rx_buffer *rx_buffer; 2455 union i40e_rx_desc *rx_desc; 2456 struct sk_buff *skb; 2457 unsigned int size; 2458 u32 nfrags = 0; 2459 bool neop; 2460 u64 qword; 2461 2462 /* return some buffers to hardware, one at a time is too slow */ 2463 if (cleaned_count >= clean_threshold) { 2464 failure = failure || 2465 i40e_alloc_rx_buffers(rx_ring, cleaned_count); 2466 cleaned_count = 0; 2467 } 2468 2469 rx_desc = I40E_RX_DESC(rx_ring, ntp); 2470 2471 /* status_error_len will always be zero for unused descriptors 2472 * because it's cleared in cleanup, and overlaps with hdr_addr 2473 * which is always zero because packet split isn't used, if the 2474 * hardware wrote DD then the length will be non-zero 2475 */ 2476 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 2477 2478 /* This memory barrier is needed to keep us from reading 2479 * any other fields out of the rx_desc until we have 2480 * verified the descriptor has been written back. 2481 */ 2482 dma_rmb(); 2483 2484 if (i40e_rx_is_programming_status(qword)) { 2485 i40e_clean_programming_status(rx_ring, 2486 rx_desc->raw.qword[0], 2487 qword); 2488 rx_buffer = i40e_rx_bi(rx_ring, ntp); 2489 i40e_inc_ntp(rx_ring); 2490 i40e_reuse_rx_page(rx_ring, rx_buffer); 2491 /* Update ntc and bump cleaned count if not in the 2492 * middle of mb packet. 2493 */ 2494 if (rx_ring->next_to_clean == ntp) { 2495 rx_ring->next_to_clean = 2496 rx_ring->next_to_process; 2497 cleaned_count++; 2498 } 2499 continue; 2500 } 2501 2502 size = FIELD_GET(I40E_RXD_QW1_LENGTH_PBUF_MASK, qword); 2503 if (!size) 2504 break; 2505 2506 i40e_trace(clean_rx_irq, rx_ring, rx_desc, xdp); 2507 /* retrieve a buffer from the ring */ 2508 rx_buffer = i40e_get_rx_buffer(rx_ring, size); 2509 2510 neop = i40e_is_non_eop(rx_ring, rx_desc); 2511 i40e_inc_ntp(rx_ring); 2512 2513 if (!xdp->data) { 2514 unsigned char *hard_start; 2515 2516 hard_start = page_address(rx_buffer->page) + 2517 rx_buffer->page_offset - offset; 2518 xdp_prepare_buff(xdp, hard_start, offset, size, true); 2519 #if (PAGE_SIZE > 4096) 2520 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2521 xdp->frame_sz = i40e_rx_frame_truesize(rx_ring, size); 2522 #endif 2523 } else if (i40e_add_xdp_frag(xdp, &nfrags, rx_buffer, size) && 2524 !neop) { 2525 /* Overflowing packet: Drop all frags on EOP */ 2526 i40e_consume_xdp_buff(rx_ring, xdp, rx_buffer); 2527 break; 2528 } 2529 2530 if (neop) 2531 continue; 2532 2533 xdp_res = i40e_run_xdp(rx_ring, xdp, xdp_prog); 2534 2535 if (xdp_res) { 2536 xdp_xmit |= xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR); 2537 2538 if (unlikely(xdp_buff_has_frags(xdp))) { 2539 i40e_process_rx_buffs(rx_ring, xdp_res, xdp); 2540 size = xdp_get_buff_len(xdp); 2541 } else if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) { 2542 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz); 2543 } else { 2544 rx_buffer->pagecnt_bias++; 2545 } 2546 total_rx_bytes += size; 2547 } else { 2548 if (ring_uses_build_skb(rx_ring)) 2549 skb = i40e_build_skb(rx_ring, xdp); 2550 else 2551 skb = i40e_construct_skb(rx_ring, xdp); 2552 2553 /* drop if we failed to retrieve a buffer */ 2554 if (!skb) { 2555 rx_ring->rx_stats.alloc_buff_failed++; 2556 i40e_consume_xdp_buff(rx_ring, xdp, rx_buffer); 2557 break; 2558 } 2559 2560 if (i40e_cleanup_headers(rx_ring, skb, rx_desc)) 2561 goto process_next; 2562 2563 /* probably a little skewed due to removing CRC */ 2564 total_rx_bytes += skb->len; 2565 2566 /* populate checksum, VLAN, and protocol */ 2567 i40e_process_skb_fields(rx_ring, rx_desc, skb); 2568 2569 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, xdp); 2570 napi_gro_receive(&rx_ring->q_vector->napi, skb); 2571 } 2572 2573 /* update budget accounting */ 2574 total_rx_packets++; 2575 process_next: 2576 cleaned_count += nfrags + 1; 2577 i40e_put_rx_buffer(rx_ring, rx_buffer); 2578 rx_ring->next_to_clean = rx_ring->next_to_process; 2579 2580 xdp->data = NULL; 2581 } 2582 2583 i40e_finalize_xdp_rx(rx_ring, xdp_xmit); 2584 2585 i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets); 2586 2587 *rx_cleaned = total_rx_packets; 2588 2589 /* guarantee a trip back through this routine if there was a failure */ 2590 return failure ? budget : (int)total_rx_packets; 2591 } 2592 2593 /** 2594 * i40e_buildreg_itr - build a value for writing to I40E_PFINT_DYN_CTLN register 2595 * @itr_idx: interrupt throttling index 2596 * @interval: interrupt throttling interval value in usecs 2597 * @force_swint: force software interrupt 2598 * 2599 * The function builds a value for I40E_PFINT_DYN_CTLN register that 2600 * is used to update interrupt throttling interval for specified ITR index 2601 * and optionally enforces a software interrupt. If the @itr_idx is equal 2602 * to I40E_ITR_NONE then no interval change is applied and only @force_swint 2603 * parameter is taken into account. If the interval change and enforced 2604 * software interrupt are not requested then the built value just enables 2605 * appropriate vector interrupt. 2606 **/ 2607 static u32 i40e_buildreg_itr(enum i40e_dyn_idx itr_idx, u16 interval, 2608 bool force_swint) 2609 { 2610 u32 val; 2611 2612 /* We don't bother with setting the CLEARPBA bit as the data sheet 2613 * points out doing so is "meaningless since it was already 2614 * auto-cleared". The auto-clearing happens when the interrupt is 2615 * asserted. 2616 * 2617 * Hardware errata 28 for also indicates that writing to a 2618 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear 2619 * an event in the PBA anyway so we need to rely on the automask 2620 * to hold pending events for us until the interrupt is re-enabled 2621 * 2622 * We have to shift the given value as it is reported in microseconds 2623 * and the register value is recorded in 2 microsecond units. 2624 */ 2625 interval >>= 1; 2626 2627 /* 1. Enable vector interrupt 2628 * 2. Update the interval for the specified ITR index 2629 * (I40E_ITR_NONE in the register is used to indicate that 2630 * no interval update is requested) 2631 */ 2632 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 2633 FIELD_PREP(I40E_PFINT_DYN_CTLN_ITR_INDX_MASK, itr_idx) | 2634 FIELD_PREP(I40E_PFINT_DYN_CTLN_INTERVAL_MASK, interval); 2635 2636 /* 3. Enforce software interrupt trigger if requested 2637 * (These software interrupts rate is limited by ITR2 that is 2638 * set to 20K interrupts per second) 2639 */ 2640 if (force_swint) 2641 val |= I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 2642 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK | 2643 FIELD_PREP(I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK, 2644 I40E_SW_ITR); 2645 2646 return val; 2647 } 2648 2649 /* The act of updating the ITR will cause it to immediately trigger. In order 2650 * to prevent this from throwing off adaptive update statistics we defer the 2651 * update so that it can only happen so often. So after either Tx or Rx are 2652 * updated we make the adaptive scheme wait until either the ITR completely 2653 * expires via the next_update expiration or we have been through at least 2654 * 3 interrupts. 2655 */ 2656 #define ITR_COUNTDOWN_START 3 2657 2658 /** 2659 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt 2660 * @vsi: the VSI we care about 2661 * @q_vector: q_vector for which itr is being updated and interrupt enabled 2662 * 2663 **/ 2664 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, 2665 struct i40e_q_vector *q_vector) 2666 { 2667 enum i40e_dyn_idx itr_idx = I40E_ITR_NONE; 2668 struct i40e_hw *hw = &vsi->back->hw; 2669 u16 interval = 0; 2670 u32 itr_val; 2671 2672 /* If we don't have MSIX, then we only need to re-enable icr0 */ 2673 if (!test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) { 2674 i40e_irq_dynamic_enable_icr0(vsi->back); 2675 return; 2676 } 2677 2678 /* These will do nothing if dynamic updates are not enabled */ 2679 i40e_update_itr(q_vector, &q_vector->tx); 2680 i40e_update_itr(q_vector, &q_vector->rx); 2681 2682 /* This block of logic allows us to get away with only updating 2683 * one ITR value with each interrupt. The idea is to perform a 2684 * pseudo-lazy update with the following criteria. 2685 * 2686 * 1. Rx is given higher priority than Tx if both are in same state 2687 * 2. If we must reduce an ITR that is given highest priority. 2688 * 3. We then give priority to increasing ITR based on amount. 2689 */ 2690 if (q_vector->rx.target_itr < q_vector->rx.current_itr) { 2691 /* Rx ITR needs to be reduced, this is highest priority */ 2692 itr_idx = I40E_RX_ITR; 2693 interval = q_vector->rx.target_itr; 2694 q_vector->rx.current_itr = q_vector->rx.target_itr; 2695 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2696 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) || 2697 ((q_vector->rx.target_itr - q_vector->rx.current_itr) < 2698 (q_vector->tx.target_itr - q_vector->tx.current_itr))) { 2699 /* Tx ITR needs to be reduced, this is second priority 2700 * Tx ITR needs to be increased more than Rx, fourth priority 2701 */ 2702 itr_idx = I40E_TX_ITR; 2703 interval = q_vector->tx.target_itr; 2704 q_vector->tx.current_itr = q_vector->tx.target_itr; 2705 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2706 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) { 2707 /* Rx ITR needs to be increased, third priority */ 2708 itr_idx = I40E_RX_ITR; 2709 interval = q_vector->rx.target_itr; 2710 q_vector->rx.current_itr = q_vector->rx.target_itr; 2711 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2712 } else { 2713 /* No ITR update, lowest priority */ 2714 if (q_vector->itr_countdown) 2715 q_vector->itr_countdown--; 2716 } 2717 2718 /* Do not update interrupt control register if VSI is down */ 2719 if (test_bit(__I40E_VSI_DOWN, vsi->state)) 2720 return; 2721 2722 /* Update ITR interval if necessary and enforce software interrupt 2723 * if we are exiting busy poll. 2724 */ 2725 if (q_vector->in_busy_poll) { 2726 itr_val = i40e_buildreg_itr(itr_idx, interval, true); 2727 q_vector->in_busy_poll = false; 2728 } else { 2729 itr_val = i40e_buildreg_itr(itr_idx, interval, false); 2730 } 2731 wr32(hw, I40E_PFINT_DYN_CTLN(q_vector->reg_idx), itr_val); 2732 } 2733 2734 /** 2735 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine 2736 * @napi: napi struct with our devices info in it 2737 * @budget: amount of work driver is allowed to do this pass, in packets 2738 * 2739 * This function will clean all queues associated with a q_vector. 2740 * 2741 * Returns the amount of work done 2742 **/ 2743 int i40e_napi_poll(struct napi_struct *napi, int budget) 2744 { 2745 struct i40e_q_vector *q_vector = 2746 container_of(napi, struct i40e_q_vector, napi); 2747 struct i40e_vsi *vsi = q_vector->vsi; 2748 struct i40e_ring *ring; 2749 bool tx_clean_complete = true; 2750 bool rx_clean_complete = true; 2751 unsigned int tx_cleaned = 0; 2752 unsigned int rx_cleaned = 0; 2753 bool clean_complete = true; 2754 bool arm_wb = false; 2755 int budget_per_ring; 2756 int work_done = 0; 2757 2758 if (test_bit(__I40E_VSI_DOWN, vsi->state)) { 2759 napi_complete(napi); 2760 return 0; 2761 } 2762 2763 /* Since the actual Tx work is minimal, we can give the Tx a larger 2764 * budget and be more aggressive about cleaning up the Tx descriptors. 2765 */ 2766 i40e_for_each_ring(ring, q_vector->tx) { 2767 bool wd = ring->xsk_pool ? 2768 i40e_clean_xdp_tx_irq(vsi, ring) : 2769 i40e_clean_tx_irq(vsi, ring, budget, &tx_cleaned); 2770 2771 if (!wd) { 2772 clean_complete = tx_clean_complete = false; 2773 continue; 2774 } 2775 arm_wb |= ring->arm_wb; 2776 ring->arm_wb = false; 2777 } 2778 2779 /* Handle case where we are called by netpoll with a budget of 0 */ 2780 if (budget <= 0) 2781 goto tx_only; 2782 2783 /* normally we have 1 Rx ring per q_vector */ 2784 if (unlikely(q_vector->num_ringpairs > 1)) 2785 /* We attempt to distribute budget to each Rx queue fairly, but 2786 * don't allow the budget to go below 1 because that would exit 2787 * polling early. 2788 */ 2789 budget_per_ring = max_t(int, budget / q_vector->num_ringpairs, 1); 2790 else 2791 /* Max of 1 Rx ring in this q_vector so give it the budget */ 2792 budget_per_ring = budget; 2793 2794 i40e_for_each_ring(ring, q_vector->rx) { 2795 int cleaned = ring->xsk_pool ? 2796 i40e_clean_rx_irq_zc(ring, budget_per_ring) : 2797 i40e_clean_rx_irq(ring, budget_per_ring, &rx_cleaned); 2798 2799 work_done += cleaned; 2800 /* if we clean as many as budgeted, we must not be done */ 2801 if (cleaned >= budget_per_ring) 2802 clean_complete = rx_clean_complete = false; 2803 } 2804 2805 if (!i40e_enabled_xdp_vsi(vsi)) 2806 trace_i40e_napi_poll(napi, q_vector, budget, budget_per_ring, rx_cleaned, 2807 tx_cleaned, rx_clean_complete, tx_clean_complete); 2808 2809 /* If work not completed, return budget and polling will return */ 2810 if (!clean_complete) { 2811 int cpu_id = smp_processor_id(); 2812 2813 /* It is possible that the interrupt affinity has changed but, 2814 * if the cpu is pegged at 100%, polling will never exit while 2815 * traffic continues and the interrupt will be stuck on this 2816 * cpu. We check to make sure affinity is correct before we 2817 * continue to poll, otherwise we must stop polling so the 2818 * interrupt can move to the correct cpu. 2819 */ 2820 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) { 2821 /* Tell napi that we are done polling */ 2822 napi_complete_done(napi, work_done); 2823 2824 /* Force an interrupt */ 2825 i40e_force_wb(vsi, q_vector); 2826 2827 /* Return budget-1 so that polling stops */ 2828 return budget - 1; 2829 } 2830 tx_only: 2831 if (arm_wb) { 2832 q_vector->tx.ring[0].tx_stats.tx_force_wb++; 2833 i40e_enable_wb_on_itr(vsi, q_vector); 2834 } 2835 return budget; 2836 } 2837 2838 if (q_vector->tx.ring[0].flags & I40E_TXR_FLAGS_WB_ON_ITR) 2839 q_vector->arm_wb_state = false; 2840 2841 /* Exit the polling mode, but don't re-enable interrupts if stack might 2842 * poll us due to busy-polling 2843 */ 2844 if (likely(napi_complete_done(napi, work_done))) 2845 i40e_update_enable_itr(vsi, q_vector); 2846 else 2847 q_vector->in_busy_poll = true; 2848 2849 return min(work_done, budget - 1); 2850 } 2851 2852 /** 2853 * i40e_atr - Add a Flow Director ATR filter 2854 * @tx_ring: ring to add programming descriptor to 2855 * @skb: send buffer 2856 * @tx_flags: send tx flags 2857 **/ 2858 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, 2859 u32 tx_flags) 2860 { 2861 struct i40e_filter_program_desc *fdir_desc; 2862 struct i40e_pf *pf = tx_ring->vsi->back; 2863 union { 2864 unsigned char *network; 2865 struct iphdr *ipv4; 2866 struct ipv6hdr *ipv6; 2867 } hdr; 2868 struct tcphdr *th; 2869 unsigned int hlen; 2870 u32 flex_ptype, dtype_cmd; 2871 int l4_proto; 2872 u16 i; 2873 2874 /* make sure ATR is enabled */ 2875 if (!test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags)) 2876 return; 2877 2878 if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) 2879 return; 2880 2881 /* if sampling is disabled do nothing */ 2882 if (!tx_ring->atr_sample_rate) 2883 return; 2884 2885 /* Currently only IPv4/IPv6 with TCP is supported */ 2886 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) 2887 return; 2888 2889 /* snag network header to get L4 type and address */ 2890 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? 2891 skb_inner_network_header(skb) : skb_network_header(skb); 2892 2893 /* Note: tx_flags gets modified to reflect inner protocols in 2894 * tx_enable_csum function if encap is enabled. 2895 */ 2896 if (tx_flags & I40E_TX_FLAGS_IPV4) { 2897 /* access ihl as u8 to avoid unaligned access on ia64 */ 2898 hlen = (hdr.network[0] & 0x0F) << 2; 2899 l4_proto = hdr.ipv4->protocol; 2900 } else { 2901 /* find the start of the innermost ipv6 header */ 2902 unsigned int inner_hlen = hdr.network - skb->data; 2903 unsigned int h_offset = inner_hlen; 2904 2905 /* this function updates h_offset to the end of the header */ 2906 l4_proto = 2907 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL); 2908 /* hlen will contain our best estimate of the tcp header */ 2909 hlen = h_offset - inner_hlen; 2910 } 2911 2912 if (l4_proto != IPPROTO_TCP) 2913 return; 2914 2915 th = (struct tcphdr *)(hdr.network + hlen); 2916 2917 /* Due to lack of space, no more new filters can be programmed */ 2918 if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) 2919 return; 2920 if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags)) { 2921 /* HW ATR eviction will take care of removing filters on FIN 2922 * and RST packets. 2923 */ 2924 if (th->fin || th->rst) 2925 return; 2926 } 2927 2928 tx_ring->atr_count++; 2929 2930 /* sample on all syn/fin/rst packets or once every atr sample rate */ 2931 if (!th->fin && 2932 !th->syn && 2933 !th->rst && 2934 (tx_ring->atr_count < tx_ring->atr_sample_rate)) 2935 return; 2936 2937 tx_ring->atr_count = 0; 2938 2939 /* grab the next descriptor */ 2940 i = tx_ring->next_to_use; 2941 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 2942 2943 i++; 2944 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2945 2946 flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK, 2947 tx_ring->queue_index); 2948 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? 2949 (LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP << 2950 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 2951 (LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP << 2952 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 2953 2954 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 2955 2956 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 2957 2958 dtype_cmd |= (th->fin || th->rst) ? 2959 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 2960 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 2961 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 2962 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 2963 2964 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 2965 I40E_TXD_FLTR_QW1_DEST_SHIFT; 2966 2967 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 2968 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 2969 2970 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 2971 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) 2972 dtype_cmd |= 2973 FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK, 2974 I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)); 2975 else 2976 dtype_cmd |= 2977 FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK, 2978 I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)); 2979 2980 if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags)) 2981 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; 2982 2983 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 2984 fdir_desc->rsvd = cpu_to_le32(0); 2985 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 2986 fdir_desc->fd_id = cpu_to_le32(0); 2987 } 2988 2989 /** 2990 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW 2991 * @skb: send buffer 2992 * @tx_ring: ring to send buffer on 2993 * @flags: the tx flags to be set 2994 * 2995 * Checks the skb and set up correspondingly several generic transmit flags 2996 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 2997 * 2998 * Returns error code indicate the frame should be dropped upon error and the 2999 * otherwise returns 0 to indicate the flags has been set properly. 3000 **/ 3001 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 3002 struct i40e_ring *tx_ring, 3003 u32 *flags) 3004 { 3005 __be16 protocol = skb->protocol; 3006 u32 tx_flags = 0; 3007 3008 if (protocol == htons(ETH_P_8021Q) && 3009 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 3010 /* When HW VLAN acceleration is turned off by the user the 3011 * stack sets the protocol to 8021q so that the driver 3012 * can take any steps required to support the SW only 3013 * VLAN handling. In our case the driver doesn't need 3014 * to take any further steps so just set the protocol 3015 * to the encapsulated ethertype. 3016 */ 3017 skb->protocol = vlan_get_protocol(skb); 3018 goto out; 3019 } 3020 3021 /* if we have a HW VLAN tag being added, default to the HW one */ 3022 if (skb_vlan_tag_present(skb)) { 3023 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; 3024 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 3025 /* else if it is a SW VLAN, check the next protocol and store the tag */ 3026 } else if (protocol == htons(ETH_P_8021Q)) { 3027 struct vlan_hdr *vhdr, _vhdr; 3028 3029 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 3030 if (!vhdr) 3031 return -EINVAL; 3032 3033 protocol = vhdr->h_vlan_encapsulated_proto; 3034 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; 3035 tx_flags |= I40E_TX_FLAGS_SW_VLAN; 3036 } 3037 3038 if (!test_bit(I40E_FLAG_DCB_ENA, tx_ring->vsi->back->flags)) 3039 goto out; 3040 3041 /* Insert 802.1p priority into VLAN header */ 3042 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || 3043 (skb->priority != TC_PRIO_CONTROL)) { 3044 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; 3045 tx_flags |= (skb->priority & 0x7) << 3046 I40E_TX_FLAGS_VLAN_PRIO_SHIFT; 3047 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { 3048 struct vlan_ethhdr *vhdr; 3049 int rc; 3050 3051 rc = skb_cow_head(skb, 0); 3052 if (rc < 0) 3053 return rc; 3054 vhdr = skb_vlan_eth_hdr(skb); 3055 vhdr->h_vlan_TCI = htons(tx_flags >> 3056 I40E_TX_FLAGS_VLAN_SHIFT); 3057 } else { 3058 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 3059 } 3060 } 3061 3062 out: 3063 *flags = tx_flags; 3064 return 0; 3065 } 3066 3067 /** 3068 * i40e_tso - set up the tso context descriptor 3069 * @first: pointer to first Tx buffer for xmit 3070 * @hdr_len: ptr to the size of the packet header 3071 * @cd_type_cmd_tso_mss: Quad Word 1 3072 * 3073 * Returns 0 if no TSO can happen, 1 if tso is going, or error 3074 **/ 3075 static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, 3076 u64 *cd_type_cmd_tso_mss) 3077 { 3078 struct sk_buff *skb = first->skb; 3079 u64 cd_cmd, cd_tso_len, cd_mss; 3080 __be16 protocol; 3081 union { 3082 struct iphdr *v4; 3083 struct ipv6hdr *v6; 3084 unsigned char *hdr; 3085 } ip; 3086 union { 3087 struct tcphdr *tcp; 3088 struct udphdr *udp; 3089 unsigned char *hdr; 3090 } l4; 3091 u32 paylen, l4_offset; 3092 u16 gso_size; 3093 int err; 3094 3095 if (skb->ip_summed != CHECKSUM_PARTIAL) 3096 return 0; 3097 3098 if (!skb_is_gso(skb)) 3099 return 0; 3100 3101 err = skb_cow_head(skb, 0); 3102 if (err < 0) 3103 return err; 3104 3105 protocol = vlan_get_protocol(skb); 3106 3107 if (eth_p_mpls(protocol)) 3108 ip.hdr = skb_inner_network_header(skb); 3109 else 3110 ip.hdr = skb_network_header(skb); 3111 l4.hdr = skb_checksum_start(skb); 3112 3113 /* initialize outer IP header fields */ 3114 if (ip.v4->version == 4) { 3115 ip.v4->tot_len = 0; 3116 ip.v4->check = 0; 3117 3118 first->tx_flags |= I40E_TX_FLAGS_TSO; 3119 } else { 3120 ip.v6->payload_len = 0; 3121 first->tx_flags |= I40E_TX_FLAGS_TSO; 3122 } 3123 3124 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 3125 SKB_GSO_GRE_CSUM | 3126 SKB_GSO_IPXIP4 | 3127 SKB_GSO_IPXIP6 | 3128 SKB_GSO_UDP_TUNNEL | 3129 SKB_GSO_UDP_TUNNEL_CSUM)) { 3130 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 3131 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { 3132 l4.udp->len = 0; 3133 3134 /* determine offset of outer transport header */ 3135 l4_offset = l4.hdr - skb->data; 3136 3137 /* remove payload length from outer checksum */ 3138 paylen = skb->len - l4_offset; 3139 csum_replace_by_diff(&l4.udp->check, 3140 (__force __wsum)htonl(paylen)); 3141 } 3142 3143 /* reset pointers to inner headers */ 3144 ip.hdr = skb_inner_network_header(skb); 3145 l4.hdr = skb_inner_transport_header(skb); 3146 3147 /* initialize inner IP header fields */ 3148 if (ip.v4->version == 4) { 3149 ip.v4->tot_len = 0; 3150 ip.v4->check = 0; 3151 } else { 3152 ip.v6->payload_len = 0; 3153 } 3154 } 3155 3156 /* determine offset of inner transport header */ 3157 l4_offset = l4.hdr - skb->data; 3158 3159 /* remove payload length from inner checksum */ 3160 paylen = skb->len - l4_offset; 3161 3162 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3163 csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen)); 3164 /* compute length of segmentation header */ 3165 *hdr_len = sizeof(*l4.udp) + l4_offset; 3166 } else { 3167 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); 3168 /* compute length of segmentation header */ 3169 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 3170 } 3171 3172 /* pull values out of skb_shinfo */ 3173 gso_size = skb_shinfo(skb)->gso_size; 3174 3175 /* update GSO size and bytecount with header size */ 3176 first->gso_segs = skb_shinfo(skb)->gso_segs; 3177 first->bytecount += (first->gso_segs - 1) * *hdr_len; 3178 3179 /* find the field values */ 3180 cd_cmd = I40E_TX_CTX_DESC_TSO; 3181 cd_tso_len = skb->len - *hdr_len; 3182 cd_mss = gso_size; 3183 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | 3184 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | 3185 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); 3186 return 1; 3187 } 3188 3189 /** 3190 * i40e_tsyn - set up the tsyn context descriptor 3191 * @tx_ring: ptr to the ring to send 3192 * @skb: ptr to the skb we're sending 3193 * @tx_flags: the collected send information 3194 * @cd_type_cmd_tso_mss: Quad Word 1 3195 * 3196 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen 3197 **/ 3198 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, 3199 u32 tx_flags, u64 *cd_type_cmd_tso_mss) 3200 { 3201 struct i40e_pf *pf; 3202 3203 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 3204 return 0; 3205 3206 /* Tx timestamps cannot be sampled when doing TSO */ 3207 if (tx_flags & I40E_TX_FLAGS_TSO) 3208 return 0; 3209 3210 /* only timestamp the outbound packet if the user has requested it and 3211 * we are not already transmitting a packet to be timestamped 3212 */ 3213 pf = i40e_netdev_to_pf(tx_ring->netdev); 3214 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags)) 3215 return 0; 3216 3217 if (pf->ptp_tx && 3218 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) { 3219 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3220 pf->ptp_tx_start = jiffies; 3221 pf->ptp_tx_skb = skb_get(skb); 3222 } else { 3223 pf->tx_hwtstamp_skipped++; 3224 return 0; 3225 } 3226 3227 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << 3228 I40E_TXD_CTX_QW1_CMD_SHIFT; 3229 3230 return 1; 3231 } 3232 3233 /** 3234 * i40e_tx_enable_csum - Enable Tx checksum offloads 3235 * @skb: send buffer 3236 * @tx_flags: pointer to Tx flags currently set 3237 * @td_cmd: Tx descriptor command bits to set 3238 * @td_offset: Tx descriptor header offsets to set 3239 * @tx_ring: Tx descriptor ring 3240 * @cd_tunneling: ptr to context desc bits 3241 **/ 3242 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, 3243 u32 *td_cmd, u32 *td_offset, 3244 struct i40e_ring *tx_ring, 3245 u32 *cd_tunneling) 3246 { 3247 union { 3248 struct iphdr *v4; 3249 struct ipv6hdr *v6; 3250 unsigned char *hdr; 3251 } ip; 3252 union { 3253 struct tcphdr *tcp; 3254 struct udphdr *udp; 3255 unsigned char *hdr; 3256 } l4; 3257 unsigned char *exthdr; 3258 u32 offset, cmd = 0; 3259 __be16 frag_off; 3260 __be16 protocol; 3261 u8 l4_proto = 0; 3262 3263 if (skb->ip_summed != CHECKSUM_PARTIAL) 3264 return 0; 3265 3266 protocol = vlan_get_protocol(skb); 3267 3268 if (eth_p_mpls(protocol)) { 3269 ip.hdr = skb_inner_network_header(skb); 3270 l4.hdr = skb_checksum_start(skb); 3271 } else { 3272 ip.hdr = skb_network_header(skb); 3273 l4.hdr = skb_transport_header(skb); 3274 } 3275 3276 /* set the tx_flags to indicate the IP protocol type. this is 3277 * required so that checksum header computation below is accurate. 3278 */ 3279 if (ip.v4->version == 4) 3280 *tx_flags |= I40E_TX_FLAGS_IPV4; 3281 else 3282 *tx_flags |= I40E_TX_FLAGS_IPV6; 3283 3284 /* compute outer L2 header size */ 3285 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; 3286 3287 if (skb->encapsulation) { 3288 u32 tunnel = 0; 3289 /* define outer network header type */ 3290 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 3291 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 3292 I40E_TX_CTX_EXT_IP_IPV4 : 3293 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; 3294 3295 l4_proto = ip.v4->protocol; 3296 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 3297 int ret; 3298 3299 tunnel |= I40E_TX_CTX_EXT_IP_IPV6; 3300 3301 exthdr = ip.hdr + sizeof(*ip.v6); 3302 l4_proto = ip.v6->nexthdr; 3303 ret = ipv6_skip_exthdr(skb, exthdr - skb->data, 3304 &l4_proto, &frag_off); 3305 if (ret < 0) 3306 return -1; 3307 } 3308 3309 /* define outer transport */ 3310 switch (l4_proto) { 3311 case IPPROTO_UDP: 3312 tunnel |= I40E_TXD_CTX_UDP_TUNNELING; 3313 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 3314 break; 3315 case IPPROTO_GRE: 3316 tunnel |= I40E_TXD_CTX_GRE_TUNNELING; 3317 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 3318 break; 3319 case IPPROTO_IPIP: 3320 case IPPROTO_IPV6: 3321 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 3322 l4.hdr = skb_inner_network_header(skb); 3323 break; 3324 default: 3325 if (*tx_flags & I40E_TX_FLAGS_TSO) 3326 return -1; 3327 3328 skb_checksum_help(skb); 3329 return 0; 3330 } 3331 3332 /* compute outer L3 header size */ 3333 tunnel |= ((l4.hdr - ip.hdr) / 4) << 3334 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; 3335 3336 /* switch IP header pointer from outer to inner header */ 3337 ip.hdr = skb_inner_network_header(skb); 3338 3339 /* compute tunnel header size */ 3340 tunnel |= ((ip.hdr - l4.hdr) / 2) << 3341 I40E_TXD_CTX_QW0_NATLEN_SHIFT; 3342 3343 /* indicate if we need to offload outer UDP header */ 3344 if ((*tx_flags & I40E_TX_FLAGS_TSO) && 3345 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 3346 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) 3347 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; 3348 3349 /* record tunnel offload values */ 3350 *cd_tunneling |= tunnel; 3351 3352 /* switch L4 header pointer from outer to inner */ 3353 l4.hdr = skb_inner_transport_header(skb); 3354 l4_proto = 0; 3355 3356 /* reset type as we transition from outer to inner headers */ 3357 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); 3358 if (ip.v4->version == 4) 3359 *tx_flags |= I40E_TX_FLAGS_IPV4; 3360 if (ip.v6->version == 6) 3361 *tx_flags |= I40E_TX_FLAGS_IPV6; 3362 } 3363 3364 /* Enable IP checksum offloads */ 3365 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 3366 l4_proto = ip.v4->protocol; 3367 /* the stack computes the IP header already, the only time we 3368 * need the hardware to recompute it is in the case of TSO. 3369 */ 3370 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 3371 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : 3372 I40E_TX_DESC_CMD_IIPT_IPV4; 3373 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 3374 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; 3375 3376 exthdr = ip.hdr + sizeof(*ip.v6); 3377 l4_proto = ip.v6->nexthdr; 3378 if (l4.hdr != exthdr) 3379 ipv6_skip_exthdr(skb, exthdr - skb->data, 3380 &l4_proto, &frag_off); 3381 } 3382 3383 /* compute inner L3 header size */ 3384 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 3385 3386 /* Enable L4 checksum offloads */ 3387 switch (l4_proto) { 3388 case IPPROTO_TCP: 3389 /* enable checksum offloads */ 3390 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; 3391 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 3392 break; 3393 case IPPROTO_SCTP: 3394 /* enable SCTP checksum offload */ 3395 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; 3396 offset |= (sizeof(struct sctphdr) >> 2) << 3397 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 3398 break; 3399 case IPPROTO_UDP: 3400 /* enable UDP checksum offload */ 3401 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; 3402 offset |= (sizeof(struct udphdr) >> 2) << 3403 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 3404 break; 3405 default: 3406 if (*tx_flags & I40E_TX_FLAGS_TSO) 3407 return -1; 3408 skb_checksum_help(skb); 3409 return 0; 3410 } 3411 3412 *td_cmd |= cmd; 3413 *td_offset |= offset; 3414 3415 return 1; 3416 } 3417 3418 /** 3419 * i40e_create_tx_ctx - Build the Tx context descriptor 3420 * @tx_ring: ring to create the descriptor on 3421 * @cd_type_cmd_tso_mss: Quad Word 1 3422 * @cd_tunneling: Quad Word 0 - bits 0-31 3423 * @cd_l2tag2: Quad Word 0 - bits 32-63 3424 **/ 3425 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, 3426 const u64 cd_type_cmd_tso_mss, 3427 const u32 cd_tunneling, const u32 cd_l2tag2) 3428 { 3429 struct i40e_tx_context_desc *context_desc; 3430 int i = tx_ring->next_to_use; 3431 3432 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && 3433 !cd_tunneling && !cd_l2tag2) 3434 return; 3435 3436 /* grab the next descriptor */ 3437 context_desc = I40E_TX_CTXTDESC(tx_ring, i); 3438 3439 i++; 3440 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 3441 3442 /* cpu_to_le32 and assign to struct fields */ 3443 context_desc->tunneling_params = cpu_to_le32(cd_tunneling); 3444 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); 3445 context_desc->rsvd = cpu_to_le16(0); 3446 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); 3447 } 3448 3449 /** 3450 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions 3451 * @tx_ring: the ring to be checked 3452 * @size: the size buffer we want to assure is available 3453 * 3454 * Returns -EBUSY if a stop is needed, else 0 3455 **/ 3456 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 3457 { 3458 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 3459 /* Memory barrier before checking head and tail */ 3460 smp_mb(); 3461 3462 ++tx_ring->tx_stats.tx_stopped; 3463 3464 /* Check again in a case another CPU has just made room available. */ 3465 if (likely(I40E_DESC_UNUSED(tx_ring) < size)) 3466 return -EBUSY; 3467 3468 /* A reprieve! - use start_queue because it doesn't call schedule */ 3469 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 3470 ++tx_ring->tx_stats.restart_queue; 3471 return 0; 3472 } 3473 3474 /** 3475 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet 3476 * @skb: send buffer 3477 * 3478 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire 3479 * and so we need to figure out the cases where we need to linearize the skb. 3480 * 3481 * For TSO we need to count the TSO header and segment payload separately. 3482 * As such we need to check cases where we have 7 fragments or more as we 3483 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for 3484 * the segment payload in the first descriptor, and another 7 for the 3485 * fragments. 3486 **/ 3487 bool __i40e_chk_linearize(struct sk_buff *skb) 3488 { 3489 const skb_frag_t *frag, *stale; 3490 int nr_frags, sum; 3491 3492 /* no need to check if number of frags is less than 7 */ 3493 nr_frags = skb_shinfo(skb)->nr_frags; 3494 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) 3495 return false; 3496 3497 /* We need to walk through the list and validate that each group 3498 * of 6 fragments totals at least gso_size. 3499 */ 3500 nr_frags -= I40E_MAX_BUFFER_TXD - 2; 3501 frag = &skb_shinfo(skb)->frags[0]; 3502 3503 /* Initialize size to the negative value of gso_size minus 1. We 3504 * use this as the worst case scenerio in which the frag ahead 3505 * of us only provides one byte which is why we are limited to 6 3506 * descriptors for a single transmit as the header and previous 3507 * fragment are already consuming 2 descriptors. 3508 */ 3509 sum = 1 - skb_shinfo(skb)->gso_size; 3510 3511 /* Add size of frags 0 through 4 to create our initial sum */ 3512 sum += skb_frag_size(frag++); 3513 sum += skb_frag_size(frag++); 3514 sum += skb_frag_size(frag++); 3515 sum += skb_frag_size(frag++); 3516 sum += skb_frag_size(frag++); 3517 3518 /* Walk through fragments adding latest fragment, testing it, and 3519 * then removing stale fragments from the sum. 3520 */ 3521 for (stale = &skb_shinfo(skb)->frags[0];; stale++) { 3522 int stale_size = skb_frag_size(stale); 3523 3524 sum += skb_frag_size(frag++); 3525 3526 /* The stale fragment may present us with a smaller 3527 * descriptor than the actual fragment size. To account 3528 * for that we need to remove all the data on the front and 3529 * figure out what the remainder would be in the last 3530 * descriptor associated with the fragment. 3531 */ 3532 if (stale_size > I40E_MAX_DATA_PER_TXD) { 3533 int align_pad = -(skb_frag_off(stale)) & 3534 (I40E_MAX_READ_REQ_SIZE - 1); 3535 3536 sum -= align_pad; 3537 stale_size -= align_pad; 3538 3539 do { 3540 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED; 3541 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED; 3542 } while (stale_size > I40E_MAX_DATA_PER_TXD); 3543 } 3544 3545 /* if sum is negative we failed to make sufficient progress */ 3546 if (sum < 0) 3547 return true; 3548 3549 if (!nr_frags--) 3550 break; 3551 3552 sum -= stale_size; 3553 } 3554 3555 return false; 3556 } 3557 3558 /** 3559 * i40e_tx_map - Build the Tx descriptor 3560 * @tx_ring: ring to send buffer on 3561 * @skb: send buffer 3562 * @first: first buffer info buffer to use 3563 * @tx_flags: collected send information 3564 * @hdr_len: size of the packet header 3565 * @td_cmd: the command field in the descriptor 3566 * @td_offset: offset for checksum or crc 3567 * 3568 * Returns 0 on success, -1 on failure to DMA 3569 **/ 3570 static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 3571 struct i40e_tx_buffer *first, u32 tx_flags, 3572 const u8 hdr_len, u32 td_cmd, u32 td_offset) 3573 { 3574 unsigned int data_len = skb->data_len; 3575 unsigned int size = skb_headlen(skb); 3576 skb_frag_t *frag; 3577 struct i40e_tx_buffer *tx_bi; 3578 struct i40e_tx_desc *tx_desc; 3579 u16 i = tx_ring->next_to_use; 3580 u32 td_tag = 0; 3581 dma_addr_t dma; 3582 u16 desc_count = 1; 3583 3584 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { 3585 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; 3586 td_tag = FIELD_GET(I40E_TX_FLAGS_VLAN_MASK, tx_flags); 3587 } 3588 3589 first->tx_flags = tx_flags; 3590 3591 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 3592 3593 tx_desc = I40E_TX_DESC(tx_ring, i); 3594 tx_bi = first; 3595 3596 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 3597 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 3598 3599 if (dma_mapping_error(tx_ring->dev, dma)) 3600 goto dma_error; 3601 3602 /* record length, and DMA address */ 3603 dma_unmap_len_set(tx_bi, len, size); 3604 dma_unmap_addr_set(tx_bi, dma, dma); 3605 3606 /* align size to end of page */ 3607 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); 3608 tx_desc->buffer_addr = cpu_to_le64(dma); 3609 3610 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { 3611 tx_desc->cmd_type_offset_bsz = 3612 build_ctob(td_cmd, td_offset, 3613 max_data, td_tag); 3614 3615 tx_desc++; 3616 i++; 3617 desc_count++; 3618 3619 if (i == tx_ring->count) { 3620 tx_desc = I40E_TX_DESC(tx_ring, 0); 3621 i = 0; 3622 } 3623 3624 dma += max_data; 3625 size -= max_data; 3626 3627 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 3628 tx_desc->buffer_addr = cpu_to_le64(dma); 3629 } 3630 3631 if (likely(!data_len)) 3632 break; 3633 3634 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, 3635 size, td_tag); 3636 3637 tx_desc++; 3638 i++; 3639 desc_count++; 3640 3641 if (i == tx_ring->count) { 3642 tx_desc = I40E_TX_DESC(tx_ring, 0); 3643 i = 0; 3644 } 3645 3646 size = skb_frag_size(frag); 3647 data_len -= size; 3648 3649 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 3650 DMA_TO_DEVICE); 3651 3652 tx_bi = &tx_ring->tx_bi[i]; 3653 } 3654 3655 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 3656 3657 i++; 3658 if (i == tx_ring->count) 3659 i = 0; 3660 3661 tx_ring->next_to_use = i; 3662 3663 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); 3664 3665 /* write last descriptor with EOP bit */ 3666 td_cmd |= I40E_TX_DESC_CMD_EOP; 3667 3668 /* We OR these values together to check both against 4 (WB_STRIDE) 3669 * below. This is safe since we don't re-use desc_count afterwards. 3670 */ 3671 desc_count |= ++tx_ring->packet_stride; 3672 3673 if (desc_count >= WB_STRIDE) { 3674 /* write last descriptor with RS bit set */ 3675 td_cmd |= I40E_TX_DESC_CMD_RS; 3676 tx_ring->packet_stride = 0; 3677 } 3678 3679 tx_desc->cmd_type_offset_bsz = 3680 build_ctob(td_cmd, td_offset, size, td_tag); 3681 3682 skb_tx_timestamp(skb); 3683 3684 /* Force memory writes to complete before letting h/w know there 3685 * are new descriptors to fetch. 3686 * 3687 * We also use this memory barrier to make certain all of the 3688 * status bits have been updated before next_to_watch is written. 3689 */ 3690 wmb(); 3691 3692 /* set next_to_watch value indicating a packet is present */ 3693 first->next_to_watch = tx_desc; 3694 3695 /* notify HW of packet */ 3696 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 3697 writel(i, tx_ring->tail); 3698 } 3699 3700 return 0; 3701 3702 dma_error: 3703 dev_info(tx_ring->dev, "TX DMA map failed\n"); 3704 3705 /* clear dma mappings for failed tx_bi map */ 3706 for (;;) { 3707 tx_bi = &tx_ring->tx_bi[i]; 3708 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); 3709 if (tx_bi == first) 3710 break; 3711 if (i == 0) 3712 i = tx_ring->count; 3713 i--; 3714 } 3715 3716 tx_ring->next_to_use = i; 3717 3718 return -1; 3719 } 3720 3721 static u16 i40e_swdcb_skb_tx_hash(struct net_device *dev, 3722 const struct sk_buff *skb, 3723 u16 num_tx_queues) 3724 { 3725 u32 jhash_initval_salt = 0xd631614b; 3726 u32 hash; 3727 3728 if (skb->sk && skb->sk->sk_hash) 3729 hash = skb->sk->sk_hash; 3730 else 3731 hash = (__force u16)skb->protocol ^ skb->hash; 3732 3733 hash = jhash_1word(hash, jhash_initval_salt); 3734 3735 return (u16)(((u64)hash * num_tx_queues) >> 32); 3736 } 3737 3738 u16 i40e_lan_select_queue(struct net_device *netdev, 3739 struct sk_buff *skb, 3740 struct net_device __always_unused *sb_dev) 3741 { 3742 struct i40e_netdev_priv *np = netdev_priv(netdev); 3743 struct i40e_vsi *vsi = np->vsi; 3744 struct i40e_hw *hw; 3745 u16 qoffset; 3746 u16 qcount; 3747 u8 tclass; 3748 u16 hash; 3749 u8 prio; 3750 3751 /* is DCB enabled at all? */ 3752 if (vsi->tc_config.numtc == 1 || 3753 i40e_is_tc_mqprio_enabled(vsi->back)) 3754 return netdev_pick_tx(netdev, skb, sb_dev); 3755 3756 prio = skb->priority; 3757 hw = &vsi->back->hw; 3758 tclass = hw->local_dcbx_config.etscfg.prioritytable[prio]; 3759 /* sanity check */ 3760 if (unlikely(!(vsi->tc_config.enabled_tc & BIT(tclass)))) 3761 tclass = 0; 3762 3763 /* select a queue assigned for the given TC */ 3764 qcount = vsi->tc_config.tc_info[tclass].qcount; 3765 hash = i40e_swdcb_skb_tx_hash(netdev, skb, qcount); 3766 3767 qoffset = vsi->tc_config.tc_info[tclass].qoffset; 3768 return qoffset + hash; 3769 } 3770 3771 /** 3772 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring 3773 * @xdpf: data to transmit 3774 * @xdp_ring: XDP Tx ring 3775 **/ 3776 static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf, 3777 struct i40e_ring *xdp_ring) 3778 { 3779 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 3780 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 3781 u16 i = 0, index = xdp_ring->next_to_use; 3782 struct i40e_tx_buffer *tx_head = &xdp_ring->tx_bi[index]; 3783 struct i40e_tx_buffer *tx_bi = tx_head; 3784 struct i40e_tx_desc *tx_desc = I40E_TX_DESC(xdp_ring, index); 3785 void *data = xdpf->data; 3786 u32 size = xdpf->len; 3787 3788 if (unlikely(I40E_DESC_UNUSED(xdp_ring) < 1 + nr_frags)) { 3789 xdp_ring->tx_stats.tx_busy++; 3790 return I40E_XDP_CONSUMED; 3791 } 3792 3793 tx_head->bytecount = xdp_get_frame_len(xdpf); 3794 tx_head->gso_segs = 1; 3795 tx_head->xdpf = xdpf; 3796 3797 for (;;) { 3798 dma_addr_t dma; 3799 3800 dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE); 3801 if (dma_mapping_error(xdp_ring->dev, dma)) 3802 goto unmap; 3803 3804 /* record length, and DMA address */ 3805 dma_unmap_len_set(tx_bi, len, size); 3806 dma_unmap_addr_set(tx_bi, dma, dma); 3807 3808 tx_desc->buffer_addr = cpu_to_le64(dma); 3809 tx_desc->cmd_type_offset_bsz = 3810 build_ctob(I40E_TX_DESC_CMD_ICRC, 0, size, 0); 3811 3812 if (++index == xdp_ring->count) 3813 index = 0; 3814 3815 if (i == nr_frags) 3816 break; 3817 3818 tx_bi = &xdp_ring->tx_bi[index]; 3819 tx_desc = I40E_TX_DESC(xdp_ring, index); 3820 3821 data = skb_frag_address(&sinfo->frags[i]); 3822 size = skb_frag_size(&sinfo->frags[i]); 3823 i++; 3824 } 3825 3826 tx_desc->cmd_type_offset_bsz |= 3827 cpu_to_le64(I40E_TXD_CMD << I40E_TXD_QW1_CMD_SHIFT); 3828 3829 /* Make certain all of the status bits have been updated 3830 * before next_to_watch is written. 3831 */ 3832 smp_wmb(); 3833 3834 xdp_ring->xdp_tx_active++; 3835 3836 tx_head->next_to_watch = tx_desc; 3837 xdp_ring->next_to_use = index; 3838 3839 return I40E_XDP_TX; 3840 3841 unmap: 3842 for (;;) { 3843 tx_bi = &xdp_ring->tx_bi[index]; 3844 if (dma_unmap_len(tx_bi, len)) 3845 dma_unmap_page(xdp_ring->dev, 3846 dma_unmap_addr(tx_bi, dma), 3847 dma_unmap_len(tx_bi, len), 3848 DMA_TO_DEVICE); 3849 dma_unmap_len_set(tx_bi, len, 0); 3850 if (tx_bi == tx_head) 3851 break; 3852 3853 if (!index) 3854 index += xdp_ring->count; 3855 index--; 3856 } 3857 3858 return I40E_XDP_CONSUMED; 3859 } 3860 3861 /** 3862 * i40e_xmit_frame_ring - Sends buffer on Tx ring 3863 * @skb: send buffer 3864 * @tx_ring: ring to send buffer on 3865 * 3866 * Returns NETDEV_TX_OK if sent, else an error code 3867 **/ 3868 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, 3869 struct i40e_ring *tx_ring) 3870 { 3871 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; 3872 u32 cd_tunneling = 0, cd_l2tag2 = 0; 3873 struct i40e_tx_buffer *first; 3874 u32 td_offset = 0; 3875 u32 tx_flags = 0; 3876 u32 td_cmd = 0; 3877 u8 hdr_len = 0; 3878 int tso, count; 3879 int tsyn; 3880 3881 /* prefetch the data, we'll need it later */ 3882 prefetch(skb->data); 3883 3884 i40e_trace(xmit_frame_ring, skb, tx_ring); 3885 3886 count = i40e_xmit_descriptor_count(skb); 3887 if (i40e_chk_linearize(skb, count)) { 3888 if (__skb_linearize(skb)) { 3889 dev_kfree_skb_any(skb); 3890 return NETDEV_TX_OK; 3891 } 3892 count = i40e_txd_use_count(skb->len); 3893 tx_ring->tx_stats.tx_linearize++; 3894 } 3895 3896 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, 3897 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, 3898 * + 4 desc gap to avoid the cache line where head is, 3899 * + 1 desc for context descriptor, 3900 * otherwise try next time 3901 */ 3902 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { 3903 tx_ring->tx_stats.tx_busy++; 3904 return NETDEV_TX_BUSY; 3905 } 3906 3907 /* record the location of the first descriptor for this packet */ 3908 first = &tx_ring->tx_bi[tx_ring->next_to_use]; 3909 first->skb = skb; 3910 first->bytecount = skb->len; 3911 first->gso_segs = 1; 3912 3913 /* prepare the xmit flags */ 3914 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) 3915 goto out_drop; 3916 3917 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); 3918 3919 if (tso < 0) 3920 goto out_drop; 3921 else if (tso) 3922 tx_flags |= I40E_TX_FLAGS_TSO; 3923 3924 /* Always offload the checksum, since it's in the data descriptor */ 3925 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, 3926 tx_ring, &cd_tunneling); 3927 if (tso < 0) 3928 goto out_drop; 3929 3930 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); 3931 3932 if (tsyn) 3933 tx_flags |= I40E_TX_FLAGS_TSYN; 3934 3935 /* always enable CRC insertion offload */ 3936 td_cmd |= I40E_TX_DESC_CMD_ICRC; 3937 3938 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, 3939 cd_tunneling, cd_l2tag2); 3940 3941 /* Add Flow Director ATR if it's enabled. 3942 * 3943 * NOTE: this must always be directly before the data descriptor. 3944 */ 3945 i40e_atr(tx_ring, skb, tx_flags); 3946 3947 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, 3948 td_cmd, td_offset)) 3949 goto cleanup_tx_tstamp; 3950 3951 return NETDEV_TX_OK; 3952 3953 out_drop: 3954 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring); 3955 dev_kfree_skb_any(first->skb); 3956 first->skb = NULL; 3957 cleanup_tx_tstamp: 3958 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) { 3959 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev); 3960 3961 dev_kfree_skb_any(pf->ptp_tx_skb); 3962 pf->ptp_tx_skb = NULL; 3963 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 3964 } 3965 3966 return NETDEV_TX_OK; 3967 } 3968 3969 /** 3970 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer 3971 * @skb: send buffer 3972 * @netdev: network interface device structure 3973 * 3974 * Returns NETDEV_TX_OK if sent, else an error code 3975 **/ 3976 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 3977 { 3978 struct i40e_netdev_priv *np = netdev_priv(netdev); 3979 struct i40e_vsi *vsi = np->vsi; 3980 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; 3981 3982 /* hardware can't handle really short frames, hardware padding works 3983 * beyond this point 3984 */ 3985 if (skb_put_padto(skb, I40E_MIN_TX_LEN)) 3986 return NETDEV_TX_OK; 3987 3988 return i40e_xmit_frame_ring(skb, tx_ring); 3989 } 3990 3991 /** 3992 * i40e_xdp_xmit - Implements ndo_xdp_xmit 3993 * @dev: netdev 3994 * @n: number of frames 3995 * @frames: array of XDP buffer pointers 3996 * @flags: XDP extra info 3997 * 3998 * Returns number of frames successfully sent. Failed frames 3999 * will be free'ed by XDP core. 4000 * 4001 * For error cases, a negative errno code is returned and no-frames 4002 * are transmitted (caller must handle freeing frames). 4003 **/ 4004 int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames, 4005 u32 flags) 4006 { 4007 struct i40e_netdev_priv *np = netdev_priv(dev); 4008 unsigned int queue_index = smp_processor_id(); 4009 struct i40e_vsi *vsi = np->vsi; 4010 struct i40e_pf *pf = vsi->back; 4011 struct i40e_ring *xdp_ring; 4012 int nxmit = 0; 4013 int i; 4014 4015 if (test_bit(__I40E_VSI_DOWN, vsi->state)) 4016 return -ENETDOWN; 4017 4018 if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs || 4019 test_bit(__I40E_CONFIG_BUSY, pf->state)) 4020 return -ENXIO; 4021 4022 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 4023 return -EINVAL; 4024 4025 xdp_ring = vsi->xdp_rings[queue_index]; 4026 4027 for (i = 0; i < n; i++) { 4028 struct xdp_frame *xdpf = frames[i]; 4029 int err; 4030 4031 err = i40e_xmit_xdp_ring(xdpf, xdp_ring); 4032 if (err != I40E_XDP_TX) 4033 break; 4034 nxmit++; 4035 } 4036 4037 if (unlikely(flags & XDP_XMIT_FLUSH)) 4038 i40e_xdp_ring_update_tail(xdp_ring); 4039 4040 return nxmit; 4041 } 4042