1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include <linux/prefetch.h> 28 #include <net/busy_poll.h> 29 #include "i40e.h" 30 #include "i40e_prototype.h" 31 32 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, 33 u32 td_tag) 34 { 35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | 36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | 37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | 38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | 39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); 40 } 41 42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) 43 #define I40E_FD_CLEAN_DELAY 10 44 /** 45 * i40e_program_fdir_filter - Program a Flow Director filter 46 * @fdir_data: Packet data that will be filter parameters 47 * @raw_packet: the pre-allocated packet buffer for FDir 48 * @pf: The PF pointer 49 * @add: True for add/update, False for remove 50 **/ 51 int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet, 52 struct i40e_pf *pf, bool add) 53 { 54 struct i40e_filter_program_desc *fdir_desc; 55 struct i40e_tx_buffer *tx_buf, *first; 56 struct i40e_tx_desc *tx_desc; 57 struct i40e_ring *tx_ring; 58 unsigned int fpt, dcc; 59 struct i40e_vsi *vsi; 60 struct device *dev; 61 dma_addr_t dma; 62 u32 td_cmd = 0; 63 u16 delay = 0; 64 u16 i; 65 66 /* find existing FDIR VSI */ 67 vsi = NULL; 68 for (i = 0; i < pf->num_alloc_vsi; i++) 69 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) 70 vsi = pf->vsi[i]; 71 if (!vsi) 72 return -ENOENT; 73 74 tx_ring = vsi->tx_rings[0]; 75 dev = tx_ring->dev; 76 77 /* we need two descriptors to add/del a filter and we can wait */ 78 do { 79 if (I40E_DESC_UNUSED(tx_ring) > 1) 80 break; 81 msleep_interruptible(1); 82 delay++; 83 } while (delay < I40E_FD_CLEAN_DELAY); 84 85 if (!(I40E_DESC_UNUSED(tx_ring) > 1)) 86 return -EAGAIN; 87 88 dma = dma_map_single(dev, raw_packet, 89 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); 90 if (dma_mapping_error(dev, dma)) 91 goto dma_fail; 92 93 /* grab the next descriptor */ 94 i = tx_ring->next_to_use; 95 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 96 first = &tx_ring->tx_bi[i]; 97 memset(first, 0, sizeof(struct i40e_tx_buffer)); 98 99 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 100 101 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 102 I40E_TXD_FLTR_QW0_QINDEX_MASK; 103 104 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) & 105 I40E_TXD_FLTR_QW0_FLEXOFF_MASK; 106 107 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) & 108 I40E_TXD_FLTR_QW0_PCTYPE_MASK; 109 110 /* Use LAN VSI Id if not programmed by user */ 111 if (fdir_data->dest_vsi == 0) 112 fpt |= (pf->vsi[pf->lan_vsi]->id) << 113 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 114 else 115 fpt |= ((u32)fdir_data->dest_vsi << 116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) & 117 I40E_TXD_FLTR_QW0_DEST_VSI_MASK; 118 119 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG; 120 121 if (add) 122 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 123 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 124 else 125 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 126 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 127 128 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) & 129 I40E_TXD_FLTR_QW1_DEST_MASK; 130 131 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) & 132 I40E_TXD_FLTR_QW1_FD_STATUS_MASK; 133 134 if (fdir_data->cnt_index != 0) { 135 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 136 dcc |= ((u32)fdir_data->cnt_index << 137 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 138 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 139 } 140 141 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt); 142 fdir_desc->rsvd = cpu_to_le32(0); 143 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc); 144 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id); 145 146 /* Now program a dummy descriptor */ 147 i = tx_ring->next_to_use; 148 tx_desc = I40E_TX_DESC(tx_ring, i); 149 tx_buf = &tx_ring->tx_bi[i]; 150 151 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 152 153 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); 154 155 /* record length, and DMA address */ 156 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); 157 dma_unmap_addr_set(tx_buf, dma, dma); 158 159 tx_desc->buffer_addr = cpu_to_le64(dma); 160 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; 161 162 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; 163 tx_buf->raw_buf = (void *)raw_packet; 164 165 tx_desc->cmd_type_offset_bsz = 166 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); 167 168 /* Force memory writes to complete before letting h/w 169 * know there are new descriptors to fetch. 170 */ 171 wmb(); 172 173 /* Mark the data descriptor to be watched */ 174 first->next_to_watch = tx_desc; 175 176 writel(tx_ring->next_to_use, tx_ring->tail); 177 return 0; 178 179 dma_fail: 180 return -1; 181 } 182 183 #define IP_HEADER_OFFSET 14 184 #define I40E_UDPIP_DUMMY_PACKET_LEN 42 185 /** 186 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters 187 * @vsi: pointer to the targeted VSI 188 * @fd_data: the flow director data required for the FDir descriptor 189 * @add: true adds a filter, false removes it 190 * 191 * Returns 0 if the filters were successfully added or removed 192 **/ 193 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, 194 struct i40e_fdir_filter *fd_data, 195 bool add) 196 { 197 struct i40e_pf *pf = vsi->back; 198 struct udphdr *udp; 199 struct iphdr *ip; 200 bool err = false; 201 u8 *raw_packet; 202 int ret; 203 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 204 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, 205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 206 207 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 208 if (!raw_packet) 209 return -ENOMEM; 210 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); 211 212 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 213 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET 214 + sizeof(struct iphdr)); 215 216 ip->daddr = fd_data->dst_ip[0]; 217 udp->dest = fd_data->dst_port; 218 ip->saddr = fd_data->src_ip[0]; 219 udp->source = fd_data->src_port; 220 221 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 222 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 223 if (ret) { 224 dev_info(&pf->pdev->dev, 225 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 226 fd_data->pctype, fd_data->fd_id, ret); 227 err = true; 228 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 229 if (add) 230 dev_info(&pf->pdev->dev, 231 "Filter OK for PCTYPE %d loc = %d\n", 232 fd_data->pctype, fd_data->fd_id); 233 else 234 dev_info(&pf->pdev->dev, 235 "Filter deleted for PCTYPE %d loc = %d\n", 236 fd_data->pctype, fd_data->fd_id); 237 } 238 if (err) 239 kfree(raw_packet); 240 241 return err ? -EOPNOTSUPP : 0; 242 } 243 244 #define I40E_TCPIP_DUMMY_PACKET_LEN 54 245 /** 246 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters 247 * @vsi: pointer to the targeted VSI 248 * @fd_data: the flow director data required for the FDir descriptor 249 * @add: true adds a filter, false removes it 250 * 251 * Returns 0 if the filters were successfully added or removed 252 **/ 253 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, 254 struct i40e_fdir_filter *fd_data, 255 bool add) 256 { 257 struct i40e_pf *pf = vsi->back; 258 struct tcphdr *tcp; 259 struct iphdr *ip; 260 bool err = false; 261 u8 *raw_packet; 262 int ret; 263 /* Dummy packet */ 264 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 265 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, 266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, 267 0x0, 0x72, 0, 0, 0, 0}; 268 269 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 270 if (!raw_packet) 271 return -ENOMEM; 272 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); 273 274 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 275 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET 276 + sizeof(struct iphdr)); 277 278 ip->daddr = fd_data->dst_ip[0]; 279 tcp->dest = fd_data->dst_port; 280 ip->saddr = fd_data->src_ip[0]; 281 tcp->source = fd_data->src_port; 282 283 if (add) { 284 pf->fd_tcp_rule++; 285 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) { 286 if (I40E_DEBUG_FD & pf->hw.debug_mask) 287 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); 288 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED; 289 } 290 } else { 291 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ? 292 (pf->fd_tcp_rule - 1) : 0; 293 if (pf->fd_tcp_rule == 0) { 294 pf->flags |= I40E_FLAG_FD_ATR_ENABLED; 295 if (I40E_DEBUG_FD & pf->hw.debug_mask) 296 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n"); 297 } 298 } 299 300 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; 301 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 302 303 if (ret) { 304 dev_info(&pf->pdev->dev, 305 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 306 fd_data->pctype, fd_data->fd_id, ret); 307 err = true; 308 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 309 if (add) 310 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", 311 fd_data->pctype, fd_data->fd_id); 312 else 313 dev_info(&pf->pdev->dev, 314 "Filter deleted for PCTYPE %d loc = %d\n", 315 fd_data->pctype, fd_data->fd_id); 316 } 317 318 if (err) 319 kfree(raw_packet); 320 321 return err ? -EOPNOTSUPP : 0; 322 } 323 324 /** 325 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for 326 * a specific flow spec 327 * @vsi: pointer to the targeted VSI 328 * @fd_data: the flow director data required for the FDir descriptor 329 * @add: true adds a filter, false removes it 330 * 331 * Returns 0 if the filters were successfully added or removed 332 **/ 333 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, 334 struct i40e_fdir_filter *fd_data, 335 bool add) 336 { 337 return -EOPNOTSUPP; 338 } 339 340 #define I40E_IP_DUMMY_PACKET_LEN 34 341 /** 342 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for 343 * a specific flow spec 344 * @vsi: pointer to the targeted VSI 345 * @fd_data: the flow director data required for the FDir descriptor 346 * @add: true adds a filter, false removes it 347 * 348 * Returns 0 if the filters were successfully added or removed 349 **/ 350 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, 351 struct i40e_fdir_filter *fd_data, 352 bool add) 353 { 354 struct i40e_pf *pf = vsi->back; 355 struct iphdr *ip; 356 bool err = false; 357 u8 *raw_packet; 358 int ret; 359 int i; 360 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 361 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, 362 0, 0, 0, 0}; 363 364 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; 365 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { 366 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 367 if (!raw_packet) 368 return -ENOMEM; 369 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); 370 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 371 372 ip->saddr = fd_data->src_ip[0]; 373 ip->daddr = fd_data->dst_ip[0]; 374 ip->protocol = 0; 375 376 fd_data->pctype = i; 377 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 378 379 if (ret) { 380 dev_info(&pf->pdev->dev, 381 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 382 fd_data->pctype, fd_data->fd_id, ret); 383 err = true; 384 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 385 if (add) 386 dev_info(&pf->pdev->dev, 387 "Filter OK for PCTYPE %d loc = %d\n", 388 fd_data->pctype, fd_data->fd_id); 389 else 390 dev_info(&pf->pdev->dev, 391 "Filter deleted for PCTYPE %d loc = %d\n", 392 fd_data->pctype, fd_data->fd_id); 393 } 394 } 395 396 if (err) 397 kfree(raw_packet); 398 399 return err ? -EOPNOTSUPP : 0; 400 } 401 402 /** 403 * i40e_add_del_fdir - Build raw packets to add/del fdir filter 404 * @vsi: pointer to the targeted VSI 405 * @cmd: command to get or set RX flow classification rules 406 * @add: true adds a filter, false removes it 407 * 408 **/ 409 int i40e_add_del_fdir(struct i40e_vsi *vsi, 410 struct i40e_fdir_filter *input, bool add) 411 { 412 struct i40e_pf *pf = vsi->back; 413 int ret; 414 415 switch (input->flow_type & ~FLOW_EXT) { 416 case TCP_V4_FLOW: 417 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 418 break; 419 case UDP_V4_FLOW: 420 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 421 break; 422 case SCTP_V4_FLOW: 423 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 424 break; 425 case IPV4_FLOW: 426 ret = i40e_add_del_fdir_ipv4(vsi, input, add); 427 break; 428 case IP_USER_FLOW: 429 switch (input->ip4_proto) { 430 case IPPROTO_TCP: 431 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 432 break; 433 case IPPROTO_UDP: 434 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 435 break; 436 case IPPROTO_SCTP: 437 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 438 break; 439 default: 440 ret = i40e_add_del_fdir_ipv4(vsi, input, add); 441 break; 442 } 443 break; 444 default: 445 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n", 446 input->flow_type); 447 ret = -EINVAL; 448 } 449 450 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */ 451 return ret; 452 } 453 454 /** 455 * i40e_fd_handle_status - check the Programming Status for FD 456 * @rx_ring: the Rx ring for this descriptor 457 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. 458 * @prog_id: the id originally used for programming 459 * 460 * This is used to verify if the FD programming or invalidation 461 * requested by SW to the HW is successful or not and take actions accordingly. 462 **/ 463 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, 464 union i40e_rx_desc *rx_desc, u8 prog_id) 465 { 466 struct i40e_pf *pf = rx_ring->vsi->back; 467 struct pci_dev *pdev = pf->pdev; 468 u32 fcnt_prog, fcnt_avail; 469 u32 error; 470 u64 qw; 471 472 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 473 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> 474 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; 475 476 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { 477 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id); 478 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || 479 (I40E_DEBUG_FD & pf->hw.debug_mask)) 480 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", 481 pf->fd_inv); 482 483 /* Check if the programming error is for ATR. 484 * If so, auto disable ATR and set a state for 485 * flush in progress. Next time we come here if flush is in 486 * progress do nothing, once flush is complete the state will 487 * be cleared. 488 */ 489 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) 490 return; 491 492 pf->fd_add_err++; 493 /* store the current atr filter count */ 494 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); 495 496 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) && 497 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) { 498 pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED; 499 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state); 500 } 501 502 /* filter programming failed most likely due to table full */ 503 fcnt_prog = i40e_get_global_fd_count(pf); 504 fcnt_avail = pf->fdir_pf_filter_count; 505 /* If ATR is running fcnt_prog can quickly change, 506 * if we are very close to full, it makes sense to disable 507 * FD ATR/SB and then re-enable it when there is room. 508 */ 509 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { 510 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && 511 !(pf->auto_disable_flags & 512 I40E_FLAG_FD_SB_ENABLED)) { 513 if (I40E_DEBUG_FD & pf->hw.debug_mask) 514 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); 515 pf->auto_disable_flags |= 516 I40E_FLAG_FD_SB_ENABLED; 517 } 518 } 519 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { 520 if (I40E_DEBUG_FD & pf->hw.debug_mask) 521 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", 522 rx_desc->wb.qword0.hi_dword.fd_id); 523 } 524 } 525 526 /** 527 * i40e_unmap_and_free_tx_resource - Release a Tx buffer 528 * @ring: the ring that owns the buffer 529 * @tx_buffer: the buffer to free 530 **/ 531 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, 532 struct i40e_tx_buffer *tx_buffer) 533 { 534 if (tx_buffer->skb) { 535 dev_kfree_skb_any(tx_buffer->skb); 536 if (dma_unmap_len(tx_buffer, len)) 537 dma_unmap_single(ring->dev, 538 dma_unmap_addr(tx_buffer, dma), 539 dma_unmap_len(tx_buffer, len), 540 DMA_TO_DEVICE); 541 } else if (dma_unmap_len(tx_buffer, len)) { 542 dma_unmap_page(ring->dev, 543 dma_unmap_addr(tx_buffer, dma), 544 dma_unmap_len(tx_buffer, len), 545 DMA_TO_DEVICE); 546 } 547 548 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) 549 kfree(tx_buffer->raw_buf); 550 551 tx_buffer->next_to_watch = NULL; 552 tx_buffer->skb = NULL; 553 dma_unmap_len_set(tx_buffer, len, 0); 554 /* tx_buffer must be completely set up in the transmit path */ 555 } 556 557 /** 558 * i40e_clean_tx_ring - Free any empty Tx buffers 559 * @tx_ring: ring to be cleaned 560 **/ 561 void i40e_clean_tx_ring(struct i40e_ring *tx_ring) 562 { 563 unsigned long bi_size; 564 u16 i; 565 566 /* ring already cleared, nothing to do */ 567 if (!tx_ring->tx_bi) 568 return; 569 570 /* Free all the Tx ring sk_buffs */ 571 for (i = 0; i < tx_ring->count; i++) 572 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); 573 574 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 575 memset(tx_ring->tx_bi, 0, bi_size); 576 577 /* Zero out the descriptor ring */ 578 memset(tx_ring->desc, 0, tx_ring->size); 579 580 tx_ring->next_to_use = 0; 581 tx_ring->next_to_clean = 0; 582 583 if (!tx_ring->netdev) 584 return; 585 586 /* cleanup Tx queue statistics */ 587 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev, 588 tx_ring->queue_index)); 589 } 590 591 /** 592 * i40e_free_tx_resources - Free Tx resources per queue 593 * @tx_ring: Tx descriptor ring for a specific queue 594 * 595 * Free all transmit software resources 596 **/ 597 void i40e_free_tx_resources(struct i40e_ring *tx_ring) 598 { 599 i40e_clean_tx_ring(tx_ring); 600 kfree(tx_ring->tx_bi); 601 tx_ring->tx_bi = NULL; 602 603 if (tx_ring->desc) { 604 dma_free_coherent(tx_ring->dev, tx_ring->size, 605 tx_ring->desc, tx_ring->dma); 606 tx_ring->desc = NULL; 607 } 608 } 609 610 /** 611 * i40e_get_tx_pending - how many tx descriptors not processed 612 * @tx_ring: the ring of descriptors 613 * @in_sw: is tx_pending being checked in SW or HW 614 * 615 * Since there is no access to the ring head register 616 * in XL710, we need to use our local copies 617 **/ 618 u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw) 619 { 620 u32 head, tail; 621 622 if (!in_sw) 623 head = i40e_get_head(ring); 624 else 625 head = ring->next_to_clean; 626 tail = readl(ring->tail); 627 628 if (head != tail) 629 return (head < tail) ? 630 tail - head : (tail + ring->count - head); 631 632 return 0; 633 } 634 635 #define WB_STRIDE 0x3 636 637 /** 638 * i40e_clean_tx_irq - Reclaim resources after transmit completes 639 * @vsi: the VSI we care about 640 * @tx_ring: Tx ring to clean 641 * @napi_budget: Used to determine if we are in netpoll 642 * 643 * Returns true if there's any budget left (e.g. the clean is finished) 644 **/ 645 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, 646 struct i40e_ring *tx_ring, int napi_budget) 647 { 648 u16 i = tx_ring->next_to_clean; 649 struct i40e_tx_buffer *tx_buf; 650 struct i40e_tx_desc *tx_head; 651 struct i40e_tx_desc *tx_desc; 652 unsigned int total_bytes = 0, total_packets = 0; 653 unsigned int budget = vsi->work_limit; 654 655 tx_buf = &tx_ring->tx_bi[i]; 656 tx_desc = I40E_TX_DESC(tx_ring, i); 657 i -= tx_ring->count; 658 659 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); 660 661 do { 662 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; 663 664 /* if next_to_watch is not set then there is no work pending */ 665 if (!eop_desc) 666 break; 667 668 /* prevent any other reads prior to eop_desc */ 669 read_barrier_depends(); 670 671 /* we have caught up to head, no work left to do */ 672 if (tx_head == tx_desc) 673 break; 674 675 /* clear next_to_watch to prevent false hangs */ 676 tx_buf->next_to_watch = NULL; 677 678 /* update the statistics for this packet */ 679 total_bytes += tx_buf->bytecount; 680 total_packets += tx_buf->gso_segs; 681 682 /* free the skb */ 683 napi_consume_skb(tx_buf->skb, napi_budget); 684 685 /* unmap skb header data */ 686 dma_unmap_single(tx_ring->dev, 687 dma_unmap_addr(tx_buf, dma), 688 dma_unmap_len(tx_buf, len), 689 DMA_TO_DEVICE); 690 691 /* clear tx_buffer data */ 692 tx_buf->skb = NULL; 693 dma_unmap_len_set(tx_buf, len, 0); 694 695 /* unmap remaining buffers */ 696 while (tx_desc != eop_desc) { 697 698 tx_buf++; 699 tx_desc++; 700 i++; 701 if (unlikely(!i)) { 702 i -= tx_ring->count; 703 tx_buf = tx_ring->tx_bi; 704 tx_desc = I40E_TX_DESC(tx_ring, 0); 705 } 706 707 /* unmap any remaining paged data */ 708 if (dma_unmap_len(tx_buf, len)) { 709 dma_unmap_page(tx_ring->dev, 710 dma_unmap_addr(tx_buf, dma), 711 dma_unmap_len(tx_buf, len), 712 DMA_TO_DEVICE); 713 dma_unmap_len_set(tx_buf, len, 0); 714 } 715 } 716 717 /* move us one more past the eop_desc for start of next pkt */ 718 tx_buf++; 719 tx_desc++; 720 i++; 721 if (unlikely(!i)) { 722 i -= tx_ring->count; 723 tx_buf = tx_ring->tx_bi; 724 tx_desc = I40E_TX_DESC(tx_ring, 0); 725 } 726 727 prefetch(tx_desc); 728 729 /* update budget accounting */ 730 budget--; 731 } while (likely(budget)); 732 733 i += tx_ring->count; 734 tx_ring->next_to_clean = i; 735 u64_stats_update_begin(&tx_ring->syncp); 736 tx_ring->stats.bytes += total_bytes; 737 tx_ring->stats.packets += total_packets; 738 u64_stats_update_end(&tx_ring->syncp); 739 tx_ring->q_vector->tx.total_bytes += total_bytes; 740 tx_ring->q_vector->tx.total_packets += total_packets; 741 742 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { 743 unsigned int j = 0; 744 745 /* check to see if there are < 4 descriptors 746 * waiting to be written back, then kick the hardware to force 747 * them to be written back in case we stay in NAPI. 748 * In this mode on X722 we do not enable Interrupt. 749 */ 750 j = i40e_get_tx_pending(tx_ring, false); 751 752 if (budget && 753 ((j / (WB_STRIDE + 1)) == 0) && (j != 0) && 754 !test_bit(__I40E_DOWN, &vsi->state) && 755 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) 756 tx_ring->arm_wb = true; 757 } 758 759 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev, 760 tx_ring->queue_index), 761 total_packets, total_bytes); 762 763 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 764 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 765 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 766 /* Make sure that anybody stopping the queue after this 767 * sees the new next_to_clean. 768 */ 769 smp_mb(); 770 if (__netif_subqueue_stopped(tx_ring->netdev, 771 tx_ring->queue_index) && 772 !test_bit(__I40E_DOWN, &vsi->state)) { 773 netif_wake_subqueue(tx_ring->netdev, 774 tx_ring->queue_index); 775 ++tx_ring->tx_stats.restart_queue; 776 } 777 } 778 779 return !!budget; 780 } 781 782 /** 783 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled 784 * @vsi: the VSI we care about 785 * @q_vector: the vector on which to enable writeback 786 * 787 **/ 788 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, 789 struct i40e_q_vector *q_vector) 790 { 791 u16 flags = q_vector->tx.ring[0].flags; 792 u32 val; 793 794 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) 795 return; 796 797 if (q_vector->arm_wb_state) 798 return; 799 800 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 801 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | 802 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ 803 804 wr32(&vsi->back->hw, 805 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), 806 val); 807 } else { 808 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | 809 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ 810 811 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 812 } 813 q_vector->arm_wb_state = true; 814 } 815 816 /** 817 * i40e_force_wb - Issue SW Interrupt so HW does a wb 818 * @vsi: the VSI we care about 819 * @q_vector: the vector on which to force writeback 820 * 821 **/ 822 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) 823 { 824 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 825 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 826 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ 827 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 828 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; 829 /* allow 00 to be written to the index */ 830 831 wr32(&vsi->back->hw, 832 I40E_PFINT_DYN_CTLN(q_vector->v_idx + 833 vsi->base_vector - 1), val); 834 } else { 835 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | 836 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ 837 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | 838 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; 839 /* allow 00 to be written to the index */ 840 841 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 842 } 843 } 844 845 /** 846 * i40e_set_new_dynamic_itr - Find new ITR level 847 * @rc: structure containing ring performance data 848 * 849 * Returns true if ITR changed, false if not 850 * 851 * Stores a new ITR value based on packets and byte counts during 852 * the last interrupt. The advantage of per interrupt computation 853 * is faster updates and more accurate ITR for the current traffic 854 * pattern. Constants in this function were computed based on 855 * theoretical maximum wire speed and thresholds were set based on 856 * testing data as well as attempting to minimize response time 857 * while increasing bulk throughput. 858 **/ 859 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) 860 { 861 enum i40e_latency_range new_latency_range = rc->latency_range; 862 struct i40e_q_vector *qv = rc->ring->q_vector; 863 u32 new_itr = rc->itr; 864 int bytes_per_int; 865 int usecs; 866 867 if (rc->total_packets == 0 || !rc->itr) 868 return false; 869 870 /* simple throttlerate management 871 * 0-10MB/s lowest (50000 ints/s) 872 * 10-20MB/s low (20000 ints/s) 873 * 20-1249MB/s bulk (18000 ints/s) 874 * > 40000 Rx packets per second (8000 ints/s) 875 * 876 * The math works out because the divisor is in 10^(-6) which 877 * turns the bytes/us input value into MB/s values, but 878 * make sure to use usecs, as the register values written 879 * are in 2 usec increments in the ITR registers, and make sure 880 * to use the smoothed values that the countdown timer gives us. 881 */ 882 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; 883 bytes_per_int = rc->total_bytes / usecs; 884 885 switch (new_latency_range) { 886 case I40E_LOWEST_LATENCY: 887 if (bytes_per_int > 10) 888 new_latency_range = I40E_LOW_LATENCY; 889 break; 890 case I40E_LOW_LATENCY: 891 if (bytes_per_int > 20) 892 new_latency_range = I40E_BULK_LATENCY; 893 else if (bytes_per_int <= 10) 894 new_latency_range = I40E_LOWEST_LATENCY; 895 break; 896 case I40E_BULK_LATENCY: 897 case I40E_ULTRA_LATENCY: 898 default: 899 if (bytes_per_int <= 20) 900 new_latency_range = I40E_LOW_LATENCY; 901 break; 902 } 903 904 /* this is to adjust RX more aggressively when streaming small 905 * packets. The value of 40000 was picked as it is just beyond 906 * what the hardware can receive per second if in low latency 907 * mode. 908 */ 909 #define RX_ULTRA_PACKET_RATE 40000 910 911 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) && 912 (&qv->rx == rc)) 913 new_latency_range = I40E_ULTRA_LATENCY; 914 915 rc->latency_range = new_latency_range; 916 917 switch (new_latency_range) { 918 case I40E_LOWEST_LATENCY: 919 new_itr = I40E_ITR_50K; 920 break; 921 case I40E_LOW_LATENCY: 922 new_itr = I40E_ITR_20K; 923 break; 924 case I40E_BULK_LATENCY: 925 new_itr = I40E_ITR_18K; 926 break; 927 case I40E_ULTRA_LATENCY: 928 new_itr = I40E_ITR_8K; 929 break; 930 default: 931 break; 932 } 933 934 rc->total_bytes = 0; 935 rc->total_packets = 0; 936 937 if (new_itr != rc->itr) { 938 rc->itr = new_itr; 939 return true; 940 } 941 942 return false; 943 } 944 945 /** 946 * i40e_clean_programming_status - clean the programming status descriptor 947 * @rx_ring: the rx ring that has this descriptor 948 * @rx_desc: the rx descriptor written back by HW 949 * 950 * Flow director should handle FD_FILTER_STATUS to check its filter programming 951 * status being successful or not and take actions accordingly. FCoE should 952 * handle its context/filter programming/invalidation status and take actions. 953 * 954 **/ 955 static void i40e_clean_programming_status(struct i40e_ring *rx_ring, 956 union i40e_rx_desc *rx_desc) 957 { 958 u64 qw; 959 u8 id; 960 961 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 962 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> 963 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; 964 965 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) 966 i40e_fd_handle_status(rx_ring, rx_desc, id); 967 #ifdef I40E_FCOE 968 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) || 969 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS)) 970 i40e_fcoe_handle_status(rx_ring, rx_desc, id); 971 #endif 972 } 973 974 /** 975 * i40e_setup_tx_descriptors - Allocate the Tx descriptors 976 * @tx_ring: the tx ring to set up 977 * 978 * Return 0 on success, negative on error 979 **/ 980 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) 981 { 982 struct device *dev = tx_ring->dev; 983 int bi_size; 984 985 if (!dev) 986 return -ENOMEM; 987 988 /* warn if we are about to overwrite the pointer */ 989 WARN_ON(tx_ring->tx_bi); 990 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 991 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); 992 if (!tx_ring->tx_bi) 993 goto err; 994 995 /* round up to nearest 4K */ 996 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); 997 /* add u32 for head writeback, align after this takes care of 998 * guaranteeing this is at least one cache line in size 999 */ 1000 tx_ring->size += sizeof(u32); 1001 tx_ring->size = ALIGN(tx_ring->size, 4096); 1002 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 1003 &tx_ring->dma, GFP_KERNEL); 1004 if (!tx_ring->desc) { 1005 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 1006 tx_ring->size); 1007 goto err; 1008 } 1009 1010 tx_ring->next_to_use = 0; 1011 tx_ring->next_to_clean = 0; 1012 return 0; 1013 1014 err: 1015 kfree(tx_ring->tx_bi); 1016 tx_ring->tx_bi = NULL; 1017 return -ENOMEM; 1018 } 1019 1020 /** 1021 * i40e_clean_rx_ring - Free Rx buffers 1022 * @rx_ring: ring to be cleaned 1023 **/ 1024 void i40e_clean_rx_ring(struct i40e_ring *rx_ring) 1025 { 1026 struct device *dev = rx_ring->dev; 1027 unsigned long bi_size; 1028 u16 i; 1029 1030 /* ring already cleared, nothing to do */ 1031 if (!rx_ring->rx_bi) 1032 return; 1033 1034 /* Free all the Rx ring sk_buffs */ 1035 for (i = 0; i < rx_ring->count; i++) { 1036 struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; 1037 1038 if (rx_bi->skb) { 1039 dev_kfree_skb(rx_bi->skb); 1040 rx_bi->skb = NULL; 1041 } 1042 if (!rx_bi->page) 1043 continue; 1044 1045 dma_unmap_page(dev, rx_bi->dma, PAGE_SIZE, DMA_FROM_DEVICE); 1046 __free_pages(rx_bi->page, 0); 1047 1048 rx_bi->page = NULL; 1049 rx_bi->page_offset = 0; 1050 } 1051 1052 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1053 memset(rx_ring->rx_bi, 0, bi_size); 1054 1055 /* Zero out the descriptor ring */ 1056 memset(rx_ring->desc, 0, rx_ring->size); 1057 1058 rx_ring->next_to_alloc = 0; 1059 rx_ring->next_to_clean = 0; 1060 rx_ring->next_to_use = 0; 1061 } 1062 1063 /** 1064 * i40e_free_rx_resources - Free Rx resources 1065 * @rx_ring: ring to clean the resources from 1066 * 1067 * Free all receive software resources 1068 **/ 1069 void i40e_free_rx_resources(struct i40e_ring *rx_ring) 1070 { 1071 i40e_clean_rx_ring(rx_ring); 1072 kfree(rx_ring->rx_bi); 1073 rx_ring->rx_bi = NULL; 1074 1075 if (rx_ring->desc) { 1076 dma_free_coherent(rx_ring->dev, rx_ring->size, 1077 rx_ring->desc, rx_ring->dma); 1078 rx_ring->desc = NULL; 1079 } 1080 } 1081 1082 /** 1083 * i40e_setup_rx_descriptors - Allocate Rx descriptors 1084 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1085 * 1086 * Returns 0 on success, negative on failure 1087 **/ 1088 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) 1089 { 1090 struct device *dev = rx_ring->dev; 1091 int bi_size; 1092 1093 /* warn if we are about to overwrite the pointer */ 1094 WARN_ON(rx_ring->rx_bi); 1095 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1096 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); 1097 if (!rx_ring->rx_bi) 1098 goto err; 1099 1100 u64_stats_init(&rx_ring->syncp); 1101 1102 /* Round up to nearest 4K */ 1103 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); 1104 rx_ring->size = ALIGN(rx_ring->size, 4096); 1105 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 1106 &rx_ring->dma, GFP_KERNEL); 1107 1108 if (!rx_ring->desc) { 1109 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 1110 rx_ring->size); 1111 goto err; 1112 } 1113 1114 rx_ring->next_to_alloc = 0; 1115 rx_ring->next_to_clean = 0; 1116 rx_ring->next_to_use = 0; 1117 1118 return 0; 1119 err: 1120 kfree(rx_ring->rx_bi); 1121 rx_ring->rx_bi = NULL; 1122 return -ENOMEM; 1123 } 1124 1125 /** 1126 * i40e_release_rx_desc - Store the new tail and head values 1127 * @rx_ring: ring to bump 1128 * @val: new head index 1129 **/ 1130 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) 1131 { 1132 rx_ring->next_to_use = val; 1133 1134 /* update next to alloc since we have filled the ring */ 1135 rx_ring->next_to_alloc = val; 1136 1137 /* Force memory writes to complete before letting h/w 1138 * know there are new descriptors to fetch. (Only 1139 * applicable for weak-ordered memory model archs, 1140 * such as IA-64). 1141 */ 1142 wmb(); 1143 writel(val, rx_ring->tail); 1144 } 1145 1146 /** 1147 * i40e_alloc_mapped_page - recycle or make a new page 1148 * @rx_ring: ring to use 1149 * @bi: rx_buffer struct to modify 1150 * 1151 * Returns true if the page was successfully allocated or 1152 * reused. 1153 **/ 1154 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, 1155 struct i40e_rx_buffer *bi) 1156 { 1157 struct page *page = bi->page; 1158 dma_addr_t dma; 1159 1160 /* since we are recycling buffers we should seldom need to alloc */ 1161 if (likely(page)) { 1162 rx_ring->rx_stats.page_reuse_count++; 1163 return true; 1164 } 1165 1166 /* alloc new page for storage */ 1167 page = dev_alloc_page(); 1168 if (unlikely(!page)) { 1169 rx_ring->rx_stats.alloc_page_failed++; 1170 return false; 1171 } 1172 1173 /* map page for use */ 1174 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 1175 1176 /* if mapping failed free memory back to system since 1177 * there isn't much point in holding memory we can't use 1178 */ 1179 if (dma_mapping_error(rx_ring->dev, dma)) { 1180 __free_pages(page, 0); 1181 rx_ring->rx_stats.alloc_page_failed++; 1182 return false; 1183 } 1184 1185 bi->dma = dma; 1186 bi->page = page; 1187 bi->page_offset = 0; 1188 1189 return true; 1190 } 1191 1192 /** 1193 * i40e_receive_skb - Send a completed packet up the stack 1194 * @rx_ring: rx ring in play 1195 * @skb: packet to send up 1196 * @vlan_tag: vlan tag for packet 1197 **/ 1198 static void i40e_receive_skb(struct i40e_ring *rx_ring, 1199 struct sk_buff *skb, u16 vlan_tag) 1200 { 1201 struct i40e_q_vector *q_vector = rx_ring->q_vector; 1202 1203 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1204 (vlan_tag & VLAN_VID_MASK)) 1205 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 1206 1207 napi_gro_receive(&q_vector->napi, skb); 1208 } 1209 1210 /** 1211 * i40e_alloc_rx_buffers - Replace used receive buffers 1212 * @rx_ring: ring to place buffers on 1213 * @cleaned_count: number of buffers to replace 1214 * 1215 * Returns false if all allocations were successful, true if any fail 1216 **/ 1217 bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) 1218 { 1219 u16 ntu = rx_ring->next_to_use; 1220 union i40e_rx_desc *rx_desc; 1221 struct i40e_rx_buffer *bi; 1222 1223 /* do nothing if no valid netdev defined */ 1224 if (!rx_ring->netdev || !cleaned_count) 1225 return false; 1226 1227 rx_desc = I40E_RX_DESC(rx_ring, ntu); 1228 bi = &rx_ring->rx_bi[ntu]; 1229 1230 do { 1231 if (!i40e_alloc_mapped_page(rx_ring, bi)) 1232 goto no_buffers; 1233 1234 /* Refresh the desc even if buffer_addrs didn't change 1235 * because each write-back erases this info. 1236 */ 1237 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1238 rx_desc->read.hdr_addr = 0; 1239 1240 rx_desc++; 1241 bi++; 1242 ntu++; 1243 if (unlikely(ntu == rx_ring->count)) { 1244 rx_desc = I40E_RX_DESC(rx_ring, 0); 1245 bi = rx_ring->rx_bi; 1246 ntu = 0; 1247 } 1248 1249 /* clear the status bits for the next_to_use descriptor */ 1250 rx_desc->wb.qword1.status_error_len = 0; 1251 1252 cleaned_count--; 1253 } while (cleaned_count); 1254 1255 if (rx_ring->next_to_use != ntu) 1256 i40e_release_rx_desc(rx_ring, ntu); 1257 1258 return false; 1259 1260 no_buffers: 1261 if (rx_ring->next_to_use != ntu) 1262 i40e_release_rx_desc(rx_ring, ntu); 1263 1264 /* make sure to come back via polling to try again after 1265 * allocation failure 1266 */ 1267 return true; 1268 } 1269 1270 /** 1271 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum 1272 * @vsi: the VSI we care about 1273 * @skb: skb currently being received and modified 1274 * @rx_desc: the receive descriptor 1275 * 1276 * skb->protocol must be set before this function is called 1277 **/ 1278 static inline void i40e_rx_checksum(struct i40e_vsi *vsi, 1279 struct sk_buff *skb, 1280 union i40e_rx_desc *rx_desc) 1281 { 1282 struct i40e_rx_ptype_decoded decoded; 1283 bool ipv4, ipv6, tunnel = false; 1284 u32 rx_error, rx_status; 1285 u8 ptype; 1286 u64 qword; 1287 1288 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1289 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; 1290 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> 1291 I40E_RXD_QW1_ERROR_SHIFT; 1292 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1293 I40E_RXD_QW1_STATUS_SHIFT; 1294 decoded = decode_rx_desc_ptype(ptype); 1295 1296 skb->ip_summed = CHECKSUM_NONE; 1297 1298 skb_checksum_none_assert(skb); 1299 1300 /* Rx csum enabled and ip headers found? */ 1301 if (!(vsi->netdev->features & NETIF_F_RXCSUM)) 1302 return; 1303 1304 /* did the hardware decode the packet and checksum? */ 1305 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) 1306 return; 1307 1308 /* both known and outer_ip must be set for the below code to work */ 1309 if (!(decoded.known && decoded.outer_ip)) 1310 return; 1311 1312 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && 1313 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); 1314 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && 1315 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); 1316 1317 if (ipv4 && 1318 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | 1319 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) 1320 goto checksum_fail; 1321 1322 /* likely incorrect csum if alternate IP extension headers found */ 1323 if (ipv6 && 1324 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) 1325 /* don't increment checksum err here, non-fatal err */ 1326 return; 1327 1328 /* there was some L4 error, count error and punt packet to the stack */ 1329 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) 1330 goto checksum_fail; 1331 1332 /* handle packets that were not able to be checksummed due 1333 * to arrival speed, in this case the stack can compute 1334 * the csum. 1335 */ 1336 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) 1337 return; 1338 1339 /* The hardware supported by this driver does not validate outer 1340 * checksums for tunneled VXLAN or GENEVE frames. I don't agree 1341 * with it but the specification states that you "MAY validate", it 1342 * doesn't make it a hard requirement so if we have validated the 1343 * inner checksum report CHECKSUM_UNNECESSARY. 1344 */ 1345 if (decoded.inner_prot & (I40E_RX_PTYPE_INNER_PROT_TCP | 1346 I40E_RX_PTYPE_INNER_PROT_UDP | 1347 I40E_RX_PTYPE_INNER_PROT_SCTP)) 1348 tunnel = true; 1349 1350 skb->ip_summed = CHECKSUM_UNNECESSARY; 1351 skb->csum_level = tunnel ? 1 : 0; 1352 1353 return; 1354 1355 checksum_fail: 1356 vsi->back->hw_csum_rx_error++; 1357 } 1358 1359 /** 1360 * i40e_ptype_to_htype - get a hash type 1361 * @ptype: the ptype value from the descriptor 1362 * 1363 * Returns a hash type to be used by skb_set_hash 1364 **/ 1365 static inline int i40e_ptype_to_htype(u8 ptype) 1366 { 1367 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); 1368 1369 if (!decoded.known) 1370 return PKT_HASH_TYPE_NONE; 1371 1372 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1373 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) 1374 return PKT_HASH_TYPE_L4; 1375 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1376 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) 1377 return PKT_HASH_TYPE_L3; 1378 else 1379 return PKT_HASH_TYPE_L2; 1380 } 1381 1382 /** 1383 * i40e_rx_hash - set the hash value in the skb 1384 * @ring: descriptor ring 1385 * @rx_desc: specific descriptor 1386 **/ 1387 static inline void i40e_rx_hash(struct i40e_ring *ring, 1388 union i40e_rx_desc *rx_desc, 1389 struct sk_buff *skb, 1390 u8 rx_ptype) 1391 { 1392 u32 hash; 1393 const __le64 rss_mask = 1394 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << 1395 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); 1396 1397 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1398 return; 1399 1400 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { 1401 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); 1402 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); 1403 } 1404 } 1405 1406 /** 1407 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor 1408 * @rx_ring: rx descriptor ring packet is being transacted on 1409 * @rx_desc: pointer to the EOP Rx descriptor 1410 * @skb: pointer to current skb being populated 1411 * @rx_ptype: the packet type decoded by hardware 1412 * 1413 * This function checks the ring, descriptor, and packet information in 1414 * order to populate the hash, checksum, VLAN, protocol, and 1415 * other fields within the skb. 1416 **/ 1417 static inline 1418 void i40e_process_skb_fields(struct i40e_ring *rx_ring, 1419 union i40e_rx_desc *rx_desc, struct sk_buff *skb, 1420 u8 rx_ptype) 1421 { 1422 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1423 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1424 I40E_RXD_QW1_STATUS_SHIFT; 1425 u32 rsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> 1426 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT; 1427 1428 if (unlikely(rsyn)) { 1429 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, rsyn); 1430 rx_ring->last_rx_timestamp = jiffies; 1431 } 1432 1433 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); 1434 1435 /* modifies the skb - consumes the enet header */ 1436 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1437 1438 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); 1439 1440 skb_record_rx_queue(skb, rx_ring->queue_index); 1441 } 1442 1443 /** 1444 * i40e_pull_tail - i40e specific version of skb_pull_tail 1445 * @rx_ring: rx descriptor ring packet is being transacted on 1446 * @skb: pointer to current skb being adjusted 1447 * 1448 * This function is an i40e specific version of __pskb_pull_tail. The 1449 * main difference between this version and the original function is that 1450 * this function can make several assumptions about the state of things 1451 * that allow for significant optimizations versus the standard function. 1452 * As a result we can do things like drop a frag and maintain an accurate 1453 * truesize for the skb. 1454 */ 1455 static void i40e_pull_tail(struct i40e_ring *rx_ring, struct sk_buff *skb) 1456 { 1457 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1458 unsigned char *va; 1459 unsigned int pull_len; 1460 1461 /* it is valid to use page_address instead of kmap since we are 1462 * working with pages allocated out of the lomem pool per 1463 * alloc_page(GFP_ATOMIC) 1464 */ 1465 va = skb_frag_address(frag); 1466 1467 /* we need the header to contain the greater of either ETH_HLEN or 1468 * 60 bytes if the skb->len is less than 60 for skb_pad. 1469 */ 1470 pull_len = eth_get_headlen(va, I40E_RX_HDR_SIZE); 1471 1472 /* align pull length to size of long to optimize memcpy performance */ 1473 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1474 1475 /* update all of the pointers */ 1476 skb_frag_size_sub(frag, pull_len); 1477 frag->page_offset += pull_len; 1478 skb->data_len -= pull_len; 1479 skb->tail += pull_len; 1480 } 1481 1482 /** 1483 * i40e_cleanup_headers - Correct empty headers 1484 * @rx_ring: rx descriptor ring packet is being transacted on 1485 * @skb: pointer to current skb being fixed 1486 * 1487 * Also address the case where we are pulling data in on pages only 1488 * and as such no data is present in the skb header. 1489 * 1490 * In addition if skb is not at least 60 bytes we need to pad it so that 1491 * it is large enough to qualify as a valid Ethernet frame. 1492 * 1493 * Returns true if an error was encountered and skb was freed. 1494 **/ 1495 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb) 1496 { 1497 /* place header in linear portion of buffer */ 1498 if (skb_is_nonlinear(skb)) 1499 i40e_pull_tail(rx_ring, skb); 1500 1501 /* if eth_skb_pad returns an error the skb was freed */ 1502 if (eth_skb_pad(skb)) 1503 return true; 1504 1505 return false; 1506 } 1507 1508 /** 1509 * i40e_reuse_rx_page - page flip buffer and store it back on the ring 1510 * @rx_ring: rx descriptor ring to store buffers on 1511 * @old_buff: donor buffer to have page reused 1512 * 1513 * Synchronizes page for reuse by the adapter 1514 **/ 1515 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, 1516 struct i40e_rx_buffer *old_buff) 1517 { 1518 struct i40e_rx_buffer *new_buff; 1519 u16 nta = rx_ring->next_to_alloc; 1520 1521 new_buff = &rx_ring->rx_bi[nta]; 1522 1523 /* update, and store next to alloc */ 1524 nta++; 1525 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1526 1527 /* transfer page from old buffer to new buffer */ 1528 *new_buff = *old_buff; 1529 } 1530 1531 /** 1532 * i40e_page_is_reserved - check if reuse is possible 1533 * @page: page struct to check 1534 */ 1535 static inline bool i40e_page_is_reserved(struct page *page) 1536 { 1537 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1538 } 1539 1540 /** 1541 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff 1542 * @rx_ring: rx descriptor ring to transact packets on 1543 * @rx_buffer: buffer containing page to add 1544 * @rx_desc: descriptor containing length of buffer written by hardware 1545 * @skb: sk_buff to place the data into 1546 * 1547 * This function will add the data contained in rx_buffer->page to the skb. 1548 * This is done either through a direct copy if the data in the buffer is 1549 * less than the skb header size, otherwise it will just attach the page as 1550 * a frag to the skb. 1551 * 1552 * The function will then update the page offset if necessary and return 1553 * true if the buffer can be reused by the adapter. 1554 **/ 1555 static bool i40e_add_rx_frag(struct i40e_ring *rx_ring, 1556 struct i40e_rx_buffer *rx_buffer, 1557 union i40e_rx_desc *rx_desc, 1558 struct sk_buff *skb) 1559 { 1560 struct page *page = rx_buffer->page; 1561 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1562 unsigned int size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> 1563 I40E_RXD_QW1_LENGTH_PBUF_SHIFT; 1564 #if (PAGE_SIZE < 8192) 1565 unsigned int truesize = I40E_RXBUFFER_2048; 1566 #else 1567 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 1568 unsigned int last_offset = PAGE_SIZE - I40E_RXBUFFER_2048; 1569 #endif 1570 1571 /* will the data fit in the skb we allocated? if so, just 1572 * copy it as it is pretty small anyway 1573 */ 1574 if ((size <= I40E_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { 1575 unsigned char *va = page_address(page) + rx_buffer->page_offset; 1576 1577 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 1578 1579 /* page is not reserved, we can reuse buffer as-is */ 1580 if (likely(!i40e_page_is_reserved(page))) 1581 return true; 1582 1583 /* this page cannot be reused so discard it */ 1584 __free_pages(page, 0); 1585 return false; 1586 } 1587 1588 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1589 rx_buffer->page_offset, size, truesize); 1590 1591 /* avoid re-using remote pages */ 1592 if (unlikely(i40e_page_is_reserved(page))) 1593 return false; 1594 1595 #if (PAGE_SIZE < 8192) 1596 /* if we are only owner of page we can reuse it */ 1597 if (unlikely(page_count(page) != 1)) 1598 return false; 1599 1600 /* flip page offset to other buffer */ 1601 rx_buffer->page_offset ^= truesize; 1602 #else 1603 /* move offset up to the next cache line */ 1604 rx_buffer->page_offset += truesize; 1605 1606 if (rx_buffer->page_offset > last_offset) 1607 return false; 1608 #endif 1609 1610 /* Even if we own the page, we are not allowed to use atomic_set() 1611 * This would break get_page_unless_zero() users. 1612 */ 1613 get_page(rx_buffer->page); 1614 1615 return true; 1616 } 1617 1618 /** 1619 * i40e_fetch_rx_buffer - Allocate skb and populate it 1620 * @rx_ring: rx descriptor ring to transact packets on 1621 * @rx_desc: descriptor containing info written by hardware 1622 * 1623 * This function allocates an skb on the fly, and populates it with the page 1624 * data from the current receive descriptor, taking care to set up the skb 1625 * correctly, as well as handling calling the page recycle function if 1626 * necessary. 1627 */ 1628 static inline 1629 struct sk_buff *i40e_fetch_rx_buffer(struct i40e_ring *rx_ring, 1630 union i40e_rx_desc *rx_desc) 1631 { 1632 struct i40e_rx_buffer *rx_buffer; 1633 struct sk_buff *skb; 1634 struct page *page; 1635 1636 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; 1637 page = rx_buffer->page; 1638 prefetchw(page); 1639 1640 skb = rx_buffer->skb; 1641 1642 if (likely(!skb)) { 1643 void *page_addr = page_address(page) + rx_buffer->page_offset; 1644 1645 /* prefetch first cache line of first page */ 1646 prefetch(page_addr); 1647 #if L1_CACHE_BYTES < 128 1648 prefetch(page_addr + L1_CACHE_BYTES); 1649 #endif 1650 1651 /* allocate a skb to store the frags */ 1652 skb = __napi_alloc_skb(&rx_ring->q_vector->napi, 1653 I40E_RX_HDR_SIZE, 1654 GFP_ATOMIC | __GFP_NOWARN); 1655 if (unlikely(!skb)) { 1656 rx_ring->rx_stats.alloc_buff_failed++; 1657 return NULL; 1658 } 1659 1660 /* we will be copying header into skb->data in 1661 * pskb_may_pull so it is in our interest to prefetch 1662 * it now to avoid a possible cache miss 1663 */ 1664 prefetchw(skb->data); 1665 } else { 1666 rx_buffer->skb = NULL; 1667 } 1668 1669 /* we are reusing so sync this buffer for CPU use */ 1670 dma_sync_single_range_for_cpu(rx_ring->dev, 1671 rx_buffer->dma, 1672 rx_buffer->page_offset, 1673 I40E_RXBUFFER_2048, 1674 DMA_FROM_DEVICE); 1675 1676 /* pull page into skb */ 1677 if (i40e_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 1678 /* hand second half of page back to the ring */ 1679 i40e_reuse_rx_page(rx_ring, rx_buffer); 1680 rx_ring->rx_stats.page_reuse_count++; 1681 } else { 1682 /* we are not reusing the buffer so unmap it */ 1683 dma_unmap_page(rx_ring->dev, rx_buffer->dma, PAGE_SIZE, 1684 DMA_FROM_DEVICE); 1685 } 1686 1687 /* clear contents of buffer_info */ 1688 rx_buffer->page = NULL; 1689 1690 return skb; 1691 } 1692 1693 /** 1694 * i40e_is_non_eop - process handling of non-EOP buffers 1695 * @rx_ring: Rx ring being processed 1696 * @rx_desc: Rx descriptor for current buffer 1697 * @skb: Current socket buffer containing buffer in progress 1698 * 1699 * This function updates next to clean. If the buffer is an EOP buffer 1700 * this function exits returning false, otherwise it will place the 1701 * sk_buff in the next buffer to be chained and return true indicating 1702 * that this is in fact a non-EOP buffer. 1703 **/ 1704 static bool i40e_is_non_eop(struct i40e_ring *rx_ring, 1705 union i40e_rx_desc *rx_desc, 1706 struct sk_buff *skb) 1707 { 1708 u32 ntc = rx_ring->next_to_clean + 1; 1709 1710 /* fetch, update, and store next to clean */ 1711 ntc = (ntc < rx_ring->count) ? ntc : 0; 1712 rx_ring->next_to_clean = ntc; 1713 1714 prefetch(I40E_RX_DESC(rx_ring, ntc)); 1715 1716 #define staterrlen rx_desc->wb.qword1.status_error_len 1717 if (unlikely(i40e_rx_is_programming_status(le64_to_cpu(staterrlen)))) { 1718 i40e_clean_programming_status(rx_ring, rx_desc); 1719 rx_ring->rx_bi[ntc].skb = skb; 1720 return true; 1721 } 1722 /* if we are the last buffer then there is nothing else to do */ 1723 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) 1724 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) 1725 return false; 1726 1727 /* place skb in next buffer to be received */ 1728 rx_ring->rx_bi[ntc].skb = skb; 1729 rx_ring->rx_stats.non_eop_descs++; 1730 1731 return true; 1732 } 1733 1734 /** 1735 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 1736 * @rx_ring: rx descriptor ring to transact packets on 1737 * @budget: Total limit on number of packets to process 1738 * 1739 * This function provides a "bounce buffer" approach to Rx interrupt 1740 * processing. The advantage to this is that on systems that have 1741 * expensive overhead for IOMMU access this provides a means of avoiding 1742 * it by maintaining the mapping of the page to the system. 1743 * 1744 * Returns amount of work completed 1745 **/ 1746 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) 1747 { 1748 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1749 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); 1750 bool failure = false; 1751 1752 while (likely(total_rx_packets < budget)) { 1753 union i40e_rx_desc *rx_desc; 1754 struct sk_buff *skb; 1755 u32 rx_status; 1756 u16 vlan_tag; 1757 u8 rx_ptype; 1758 u64 qword; 1759 1760 /* return some buffers to hardware, one at a time is too slow */ 1761 if (cleaned_count >= I40E_RX_BUFFER_WRITE) { 1762 failure = failure || 1763 i40e_alloc_rx_buffers(rx_ring, cleaned_count); 1764 cleaned_count = 0; 1765 } 1766 1767 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); 1768 1769 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1770 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> 1771 I40E_RXD_QW1_PTYPE_SHIFT; 1772 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1773 I40E_RXD_QW1_STATUS_SHIFT; 1774 1775 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT))) 1776 break; 1777 1778 /* status_error_len will always be zero for unused descriptors 1779 * because it's cleared in cleanup, and overlaps with hdr_addr 1780 * which is always zero because packet split isn't used, if the 1781 * hardware wrote DD then it will be non-zero 1782 */ 1783 if (!rx_desc->wb.qword1.status_error_len) 1784 break; 1785 1786 /* This memory barrier is needed to keep us from reading 1787 * any other fields out of the rx_desc until we know the 1788 * DD bit is set. 1789 */ 1790 dma_rmb(); 1791 1792 skb = i40e_fetch_rx_buffer(rx_ring, rx_desc); 1793 if (!skb) 1794 break; 1795 1796 cleaned_count++; 1797 1798 if (i40e_is_non_eop(rx_ring, rx_desc, skb)) 1799 continue; 1800 1801 /* ERR_MASK will only have valid bits if EOP set, and 1802 * what we are doing here is actually checking 1803 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in 1804 * the error field 1805 */ 1806 if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { 1807 dev_kfree_skb_any(skb); 1808 continue; 1809 } 1810 1811 if (i40e_cleanup_headers(rx_ring, skb)) 1812 continue; 1813 1814 /* probably a little skewed due to removing CRC */ 1815 total_rx_bytes += skb->len; 1816 1817 /* populate checksum, VLAN, and protocol */ 1818 i40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); 1819 1820 #ifdef I40E_FCOE 1821 if (unlikely( 1822 i40e_rx_is_fcoe(rx_ptype) && 1823 !i40e_fcoe_handle_offload(rx_ring, rx_desc, skb))) { 1824 dev_kfree_skb_any(skb); 1825 continue; 1826 } 1827 #endif 1828 1829 vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? 1830 le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; 1831 1832 i40e_receive_skb(rx_ring, skb, vlan_tag); 1833 1834 /* update budget accounting */ 1835 total_rx_packets++; 1836 } 1837 1838 u64_stats_update_begin(&rx_ring->syncp); 1839 rx_ring->stats.packets += total_rx_packets; 1840 rx_ring->stats.bytes += total_rx_bytes; 1841 u64_stats_update_end(&rx_ring->syncp); 1842 rx_ring->q_vector->rx.total_packets += total_rx_packets; 1843 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 1844 1845 /* guarantee a trip back through this routine if there was a failure */ 1846 return failure ? budget : total_rx_packets; 1847 } 1848 1849 static u32 i40e_buildreg_itr(const int type, const u16 itr) 1850 { 1851 u32 val; 1852 1853 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1854 /* Don't clear PBA because that can cause lost interrupts that 1855 * came in while we were cleaning/polling 1856 */ 1857 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | 1858 (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); 1859 1860 return val; 1861 } 1862 1863 /* a small macro to shorten up some long lines */ 1864 #define INTREG I40E_PFINT_DYN_CTLN 1865 1866 /** 1867 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt 1868 * @vsi: the VSI we care about 1869 * @q_vector: q_vector for which itr is being updated and interrupt enabled 1870 * 1871 **/ 1872 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, 1873 struct i40e_q_vector *q_vector) 1874 { 1875 struct i40e_hw *hw = &vsi->back->hw; 1876 bool rx = false, tx = false; 1877 u32 rxval, txval; 1878 int vector; 1879 int idx = q_vector->v_idx; 1880 1881 vector = (q_vector->v_idx + vsi->base_vector); 1882 1883 /* avoid dynamic calculation if in countdown mode OR if 1884 * all dynamic is disabled 1885 */ 1886 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); 1887 1888 if (q_vector->itr_countdown > 0 || 1889 (!ITR_IS_DYNAMIC(vsi->rx_rings[idx]->rx_itr_setting) && 1890 !ITR_IS_DYNAMIC(vsi->tx_rings[idx]->tx_itr_setting))) { 1891 goto enable_int; 1892 } 1893 1894 if (ITR_IS_DYNAMIC(vsi->rx_rings[idx]->rx_itr_setting)) { 1895 rx = i40e_set_new_dynamic_itr(&q_vector->rx); 1896 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); 1897 } 1898 1899 if (ITR_IS_DYNAMIC(vsi->tx_rings[idx]->tx_itr_setting)) { 1900 tx = i40e_set_new_dynamic_itr(&q_vector->tx); 1901 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); 1902 } 1903 1904 if (rx || tx) { 1905 /* get the higher of the two ITR adjustments and 1906 * use the same value for both ITR registers 1907 * when in adaptive mode (Rx and/or Tx) 1908 */ 1909 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); 1910 1911 q_vector->tx.itr = q_vector->rx.itr = itr; 1912 txval = i40e_buildreg_itr(I40E_TX_ITR, itr); 1913 tx = true; 1914 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); 1915 rx = true; 1916 } 1917 1918 /* only need to enable the interrupt once, but need 1919 * to possibly update both ITR values 1920 */ 1921 if (rx) { 1922 /* set the INTENA_MSK_MASK so that this first write 1923 * won't actually enable the interrupt, instead just 1924 * updating the ITR (it's bit 31 PF and VF) 1925 */ 1926 rxval |= BIT(31); 1927 /* don't check _DOWN because interrupt isn't being enabled */ 1928 wr32(hw, INTREG(vector - 1), rxval); 1929 } 1930 1931 enable_int: 1932 if (!test_bit(__I40E_DOWN, &vsi->state)) 1933 wr32(hw, INTREG(vector - 1), txval); 1934 1935 if (q_vector->itr_countdown) 1936 q_vector->itr_countdown--; 1937 else 1938 q_vector->itr_countdown = ITR_COUNTDOWN_START; 1939 } 1940 1941 /** 1942 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine 1943 * @napi: napi struct with our devices info in it 1944 * @budget: amount of work driver is allowed to do this pass, in packets 1945 * 1946 * This function will clean all queues associated with a q_vector. 1947 * 1948 * Returns the amount of work done 1949 **/ 1950 int i40e_napi_poll(struct napi_struct *napi, int budget) 1951 { 1952 struct i40e_q_vector *q_vector = 1953 container_of(napi, struct i40e_q_vector, napi); 1954 struct i40e_vsi *vsi = q_vector->vsi; 1955 struct i40e_ring *ring; 1956 bool clean_complete = true; 1957 bool arm_wb = false; 1958 int budget_per_ring; 1959 int work_done = 0; 1960 1961 if (test_bit(__I40E_DOWN, &vsi->state)) { 1962 napi_complete(napi); 1963 return 0; 1964 } 1965 1966 /* Clear hung_detected bit */ 1967 clear_bit(I40E_Q_VECTOR_HUNG_DETECT, &q_vector->hung_detected); 1968 /* Since the actual Tx work is minimal, we can give the Tx a larger 1969 * budget and be more aggressive about cleaning up the Tx descriptors. 1970 */ 1971 i40e_for_each_ring(ring, q_vector->tx) { 1972 if (!i40e_clean_tx_irq(vsi, ring, budget)) { 1973 clean_complete = false; 1974 continue; 1975 } 1976 arm_wb |= ring->arm_wb; 1977 ring->arm_wb = false; 1978 } 1979 1980 /* Handle case where we are called by netpoll with a budget of 0 */ 1981 if (budget <= 0) 1982 goto tx_only; 1983 1984 /* We attempt to distribute budget to each Rx queue fairly, but don't 1985 * allow the budget to go below 1 because that would exit polling early. 1986 */ 1987 budget_per_ring = max(budget/q_vector->num_ringpairs, 1); 1988 1989 i40e_for_each_ring(ring, q_vector->rx) { 1990 int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); 1991 1992 work_done += cleaned; 1993 /* if we clean as many as budgeted, we must not be done */ 1994 if (cleaned >= budget_per_ring) 1995 clean_complete = false; 1996 } 1997 1998 /* If work not completed, return budget and polling will return */ 1999 if (!clean_complete) { 2000 tx_only: 2001 if (arm_wb) { 2002 q_vector->tx.ring[0].tx_stats.tx_force_wb++; 2003 i40e_enable_wb_on_itr(vsi, q_vector); 2004 } 2005 return budget; 2006 } 2007 2008 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) 2009 q_vector->arm_wb_state = false; 2010 2011 /* Work is done so exit the polling mode and re-enable the interrupt */ 2012 napi_complete_done(napi, work_done); 2013 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 2014 i40e_update_enable_itr(vsi, q_vector); 2015 } else { /* Legacy mode */ 2016 i40e_irq_dynamic_enable_icr0(vsi->back, false); 2017 } 2018 return 0; 2019 } 2020 2021 /** 2022 * i40e_atr - Add a Flow Director ATR filter 2023 * @tx_ring: ring to add programming descriptor to 2024 * @skb: send buffer 2025 * @tx_flags: send tx flags 2026 **/ 2027 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, 2028 u32 tx_flags) 2029 { 2030 struct i40e_filter_program_desc *fdir_desc; 2031 struct i40e_pf *pf = tx_ring->vsi->back; 2032 union { 2033 unsigned char *network; 2034 struct iphdr *ipv4; 2035 struct ipv6hdr *ipv6; 2036 } hdr; 2037 struct tcphdr *th; 2038 unsigned int hlen; 2039 u32 flex_ptype, dtype_cmd; 2040 int l4_proto; 2041 u16 i; 2042 2043 /* make sure ATR is enabled */ 2044 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) 2045 return; 2046 2047 if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) 2048 return; 2049 2050 /* if sampling is disabled do nothing */ 2051 if (!tx_ring->atr_sample_rate) 2052 return; 2053 2054 /* Currently only IPv4/IPv6 with TCP is supported */ 2055 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) 2056 return; 2057 2058 /* snag network header to get L4 type and address */ 2059 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? 2060 skb_inner_network_header(skb) : skb_network_header(skb); 2061 2062 /* Note: tx_flags gets modified to reflect inner protocols in 2063 * tx_enable_csum function if encap is enabled. 2064 */ 2065 if (tx_flags & I40E_TX_FLAGS_IPV4) { 2066 /* access ihl as u8 to avoid unaligned access on ia64 */ 2067 hlen = (hdr.network[0] & 0x0F) << 2; 2068 l4_proto = hdr.ipv4->protocol; 2069 } else { 2070 hlen = hdr.network - skb->data; 2071 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 2072 hlen -= hdr.network - skb->data; 2073 } 2074 2075 if (l4_proto != IPPROTO_TCP) 2076 return; 2077 2078 th = (struct tcphdr *)(hdr.network + hlen); 2079 2080 /* Due to lack of space, no more new filters can be programmed */ 2081 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) 2082 return; 2083 if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) && 2084 (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) { 2085 /* HW ATR eviction will take care of removing filters on FIN 2086 * and RST packets. 2087 */ 2088 if (th->fin || th->rst) 2089 return; 2090 } 2091 2092 tx_ring->atr_count++; 2093 2094 /* sample on all syn/fin/rst packets or once every atr sample rate */ 2095 if (!th->fin && 2096 !th->syn && 2097 !th->rst && 2098 (tx_ring->atr_count < tx_ring->atr_sample_rate)) 2099 return; 2100 2101 tx_ring->atr_count = 0; 2102 2103 /* grab the next descriptor */ 2104 i = tx_ring->next_to_use; 2105 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 2106 2107 i++; 2108 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2109 2110 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 2111 I40E_TXD_FLTR_QW0_QINDEX_MASK; 2112 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? 2113 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 2114 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 2115 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 2116 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 2117 2118 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 2119 2120 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 2121 2122 dtype_cmd |= (th->fin || th->rst) ? 2123 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 2124 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 2125 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 2126 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 2127 2128 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 2129 I40E_TXD_FLTR_QW1_DEST_SHIFT; 2130 2131 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 2132 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 2133 2134 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 2135 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) 2136 dtype_cmd |= 2137 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << 2138 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2139 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2140 else 2141 dtype_cmd |= 2142 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << 2143 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2144 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2145 2146 if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) && 2147 (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) 2148 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; 2149 2150 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 2151 fdir_desc->rsvd = cpu_to_le32(0); 2152 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 2153 fdir_desc->fd_id = cpu_to_le32(0); 2154 } 2155 2156 /** 2157 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW 2158 * @skb: send buffer 2159 * @tx_ring: ring to send buffer on 2160 * @flags: the tx flags to be set 2161 * 2162 * Checks the skb and set up correspondingly several generic transmit flags 2163 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 2164 * 2165 * Returns error code indicate the frame should be dropped upon error and the 2166 * otherwise returns 0 to indicate the flags has been set properly. 2167 **/ 2168 #ifdef I40E_FCOE 2169 inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 2170 struct i40e_ring *tx_ring, 2171 u32 *flags) 2172 #else 2173 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 2174 struct i40e_ring *tx_ring, 2175 u32 *flags) 2176 #endif 2177 { 2178 __be16 protocol = skb->protocol; 2179 u32 tx_flags = 0; 2180 2181 if (protocol == htons(ETH_P_8021Q) && 2182 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 2183 /* When HW VLAN acceleration is turned off by the user the 2184 * stack sets the protocol to 8021q so that the driver 2185 * can take any steps required to support the SW only 2186 * VLAN handling. In our case the driver doesn't need 2187 * to take any further steps so just set the protocol 2188 * to the encapsulated ethertype. 2189 */ 2190 skb->protocol = vlan_get_protocol(skb); 2191 goto out; 2192 } 2193 2194 /* if we have a HW VLAN tag being added, default to the HW one */ 2195 if (skb_vlan_tag_present(skb)) { 2196 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; 2197 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 2198 /* else if it is a SW VLAN, check the next protocol and store the tag */ 2199 } else if (protocol == htons(ETH_P_8021Q)) { 2200 struct vlan_hdr *vhdr, _vhdr; 2201 2202 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 2203 if (!vhdr) 2204 return -EINVAL; 2205 2206 protocol = vhdr->h_vlan_encapsulated_proto; 2207 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; 2208 tx_flags |= I40E_TX_FLAGS_SW_VLAN; 2209 } 2210 2211 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) 2212 goto out; 2213 2214 /* Insert 802.1p priority into VLAN header */ 2215 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || 2216 (skb->priority != TC_PRIO_CONTROL)) { 2217 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; 2218 tx_flags |= (skb->priority & 0x7) << 2219 I40E_TX_FLAGS_VLAN_PRIO_SHIFT; 2220 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { 2221 struct vlan_ethhdr *vhdr; 2222 int rc; 2223 2224 rc = skb_cow_head(skb, 0); 2225 if (rc < 0) 2226 return rc; 2227 vhdr = (struct vlan_ethhdr *)skb->data; 2228 vhdr->h_vlan_TCI = htons(tx_flags >> 2229 I40E_TX_FLAGS_VLAN_SHIFT); 2230 } else { 2231 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 2232 } 2233 } 2234 2235 out: 2236 *flags = tx_flags; 2237 return 0; 2238 } 2239 2240 /** 2241 * i40e_tso - set up the tso context descriptor 2242 * @skb: ptr to the skb we're sending 2243 * @hdr_len: ptr to the size of the packet header 2244 * @cd_type_cmd_tso_mss: Quad Word 1 2245 * 2246 * Returns 0 if no TSO can happen, 1 if tso is going, or error 2247 **/ 2248 static int i40e_tso(struct sk_buff *skb, u8 *hdr_len, u64 *cd_type_cmd_tso_mss) 2249 { 2250 u64 cd_cmd, cd_tso_len, cd_mss; 2251 union { 2252 struct iphdr *v4; 2253 struct ipv6hdr *v6; 2254 unsigned char *hdr; 2255 } ip; 2256 union { 2257 struct tcphdr *tcp; 2258 struct udphdr *udp; 2259 unsigned char *hdr; 2260 } l4; 2261 u32 paylen, l4_offset; 2262 int err; 2263 2264 if (skb->ip_summed != CHECKSUM_PARTIAL) 2265 return 0; 2266 2267 if (!skb_is_gso(skb)) 2268 return 0; 2269 2270 err = skb_cow_head(skb, 0); 2271 if (err < 0) 2272 return err; 2273 2274 ip.hdr = skb_network_header(skb); 2275 l4.hdr = skb_transport_header(skb); 2276 2277 /* initialize outer IP header fields */ 2278 if (ip.v4->version == 4) { 2279 ip.v4->tot_len = 0; 2280 ip.v4->check = 0; 2281 } else { 2282 ip.v6->payload_len = 0; 2283 } 2284 2285 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 2286 SKB_GSO_GRE_CSUM | 2287 SKB_GSO_IPXIP4 | 2288 SKB_GSO_IPXIP6 | 2289 SKB_GSO_UDP_TUNNEL | 2290 SKB_GSO_UDP_TUNNEL_CSUM)) { 2291 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 2292 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { 2293 l4.udp->len = 0; 2294 2295 /* determine offset of outer transport header */ 2296 l4_offset = l4.hdr - skb->data; 2297 2298 /* remove payload length from outer checksum */ 2299 paylen = skb->len - l4_offset; 2300 csum_replace_by_diff(&l4.udp->check, htonl(paylen)); 2301 } 2302 2303 /* reset pointers to inner headers */ 2304 ip.hdr = skb_inner_network_header(skb); 2305 l4.hdr = skb_inner_transport_header(skb); 2306 2307 /* initialize inner IP header fields */ 2308 if (ip.v4->version == 4) { 2309 ip.v4->tot_len = 0; 2310 ip.v4->check = 0; 2311 } else { 2312 ip.v6->payload_len = 0; 2313 } 2314 } 2315 2316 /* determine offset of inner transport header */ 2317 l4_offset = l4.hdr - skb->data; 2318 2319 /* remove payload length from inner checksum */ 2320 paylen = skb->len - l4_offset; 2321 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 2322 2323 /* compute length of segmentation header */ 2324 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 2325 2326 /* find the field values */ 2327 cd_cmd = I40E_TX_CTX_DESC_TSO; 2328 cd_tso_len = skb->len - *hdr_len; 2329 cd_mss = skb_shinfo(skb)->gso_size; 2330 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | 2331 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | 2332 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); 2333 return 1; 2334 } 2335 2336 /** 2337 * i40e_tsyn - set up the tsyn context descriptor 2338 * @tx_ring: ptr to the ring to send 2339 * @skb: ptr to the skb we're sending 2340 * @tx_flags: the collected send information 2341 * @cd_type_cmd_tso_mss: Quad Word 1 2342 * 2343 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen 2344 **/ 2345 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, 2346 u32 tx_flags, u64 *cd_type_cmd_tso_mss) 2347 { 2348 struct i40e_pf *pf; 2349 2350 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 2351 return 0; 2352 2353 /* Tx timestamps cannot be sampled when doing TSO */ 2354 if (tx_flags & I40E_TX_FLAGS_TSO) 2355 return 0; 2356 2357 /* only timestamp the outbound packet if the user has requested it and 2358 * we are not already transmitting a packet to be timestamped 2359 */ 2360 pf = i40e_netdev_to_pf(tx_ring->netdev); 2361 if (!(pf->flags & I40E_FLAG_PTP)) 2362 return 0; 2363 2364 if (pf->ptp_tx && 2365 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) { 2366 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2367 pf->ptp_tx_skb = skb_get(skb); 2368 } else { 2369 return 0; 2370 } 2371 2372 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << 2373 I40E_TXD_CTX_QW1_CMD_SHIFT; 2374 2375 return 1; 2376 } 2377 2378 /** 2379 * i40e_tx_enable_csum - Enable Tx checksum offloads 2380 * @skb: send buffer 2381 * @tx_flags: pointer to Tx flags currently set 2382 * @td_cmd: Tx descriptor command bits to set 2383 * @td_offset: Tx descriptor header offsets to set 2384 * @tx_ring: Tx descriptor ring 2385 * @cd_tunneling: ptr to context desc bits 2386 **/ 2387 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, 2388 u32 *td_cmd, u32 *td_offset, 2389 struct i40e_ring *tx_ring, 2390 u32 *cd_tunneling) 2391 { 2392 union { 2393 struct iphdr *v4; 2394 struct ipv6hdr *v6; 2395 unsigned char *hdr; 2396 } ip; 2397 union { 2398 struct tcphdr *tcp; 2399 struct udphdr *udp; 2400 unsigned char *hdr; 2401 } l4; 2402 unsigned char *exthdr; 2403 u32 offset, cmd = 0; 2404 __be16 frag_off; 2405 u8 l4_proto = 0; 2406 2407 if (skb->ip_summed != CHECKSUM_PARTIAL) 2408 return 0; 2409 2410 ip.hdr = skb_network_header(skb); 2411 l4.hdr = skb_transport_header(skb); 2412 2413 /* compute outer L2 header size */ 2414 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; 2415 2416 if (skb->encapsulation) { 2417 u32 tunnel = 0; 2418 /* define outer network header type */ 2419 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 2420 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 2421 I40E_TX_CTX_EXT_IP_IPV4 : 2422 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; 2423 2424 l4_proto = ip.v4->protocol; 2425 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 2426 tunnel |= I40E_TX_CTX_EXT_IP_IPV6; 2427 2428 exthdr = ip.hdr + sizeof(*ip.v6); 2429 l4_proto = ip.v6->nexthdr; 2430 if (l4.hdr != exthdr) 2431 ipv6_skip_exthdr(skb, exthdr - skb->data, 2432 &l4_proto, &frag_off); 2433 } 2434 2435 /* define outer transport */ 2436 switch (l4_proto) { 2437 case IPPROTO_UDP: 2438 tunnel |= I40E_TXD_CTX_UDP_TUNNELING; 2439 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2440 break; 2441 case IPPROTO_GRE: 2442 tunnel |= I40E_TXD_CTX_GRE_TUNNELING; 2443 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2444 break; 2445 case IPPROTO_IPIP: 2446 case IPPROTO_IPV6: 2447 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2448 l4.hdr = skb_inner_network_header(skb); 2449 break; 2450 default: 2451 if (*tx_flags & I40E_TX_FLAGS_TSO) 2452 return -1; 2453 2454 skb_checksum_help(skb); 2455 return 0; 2456 } 2457 2458 /* compute outer L3 header size */ 2459 tunnel |= ((l4.hdr - ip.hdr) / 4) << 2460 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; 2461 2462 /* switch IP header pointer from outer to inner header */ 2463 ip.hdr = skb_inner_network_header(skb); 2464 2465 /* compute tunnel header size */ 2466 tunnel |= ((ip.hdr - l4.hdr) / 2) << 2467 I40E_TXD_CTX_QW0_NATLEN_SHIFT; 2468 2469 /* indicate if we need to offload outer UDP header */ 2470 if ((*tx_flags & I40E_TX_FLAGS_TSO) && 2471 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 2472 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) 2473 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; 2474 2475 /* record tunnel offload values */ 2476 *cd_tunneling |= tunnel; 2477 2478 /* switch L4 header pointer from outer to inner */ 2479 l4.hdr = skb_inner_transport_header(skb); 2480 l4_proto = 0; 2481 2482 /* reset type as we transition from outer to inner headers */ 2483 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); 2484 if (ip.v4->version == 4) 2485 *tx_flags |= I40E_TX_FLAGS_IPV4; 2486 if (ip.v6->version == 6) 2487 *tx_flags |= I40E_TX_FLAGS_IPV6; 2488 } 2489 2490 /* Enable IP checksum offloads */ 2491 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 2492 l4_proto = ip.v4->protocol; 2493 /* the stack computes the IP header already, the only time we 2494 * need the hardware to recompute it is in the case of TSO. 2495 */ 2496 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 2497 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : 2498 I40E_TX_DESC_CMD_IIPT_IPV4; 2499 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 2500 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; 2501 2502 exthdr = ip.hdr + sizeof(*ip.v6); 2503 l4_proto = ip.v6->nexthdr; 2504 if (l4.hdr != exthdr) 2505 ipv6_skip_exthdr(skb, exthdr - skb->data, 2506 &l4_proto, &frag_off); 2507 } 2508 2509 /* compute inner L3 header size */ 2510 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 2511 2512 /* Enable L4 checksum offloads */ 2513 switch (l4_proto) { 2514 case IPPROTO_TCP: 2515 /* enable checksum offloads */ 2516 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; 2517 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2518 break; 2519 case IPPROTO_SCTP: 2520 /* enable SCTP checksum offload */ 2521 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; 2522 offset |= (sizeof(struct sctphdr) >> 2) << 2523 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2524 break; 2525 case IPPROTO_UDP: 2526 /* enable UDP checksum offload */ 2527 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; 2528 offset |= (sizeof(struct udphdr) >> 2) << 2529 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2530 break; 2531 default: 2532 if (*tx_flags & I40E_TX_FLAGS_TSO) 2533 return -1; 2534 skb_checksum_help(skb); 2535 return 0; 2536 } 2537 2538 *td_cmd |= cmd; 2539 *td_offset |= offset; 2540 2541 return 1; 2542 } 2543 2544 /** 2545 * i40e_create_tx_ctx Build the Tx context descriptor 2546 * @tx_ring: ring to create the descriptor on 2547 * @cd_type_cmd_tso_mss: Quad Word 1 2548 * @cd_tunneling: Quad Word 0 - bits 0-31 2549 * @cd_l2tag2: Quad Word 0 - bits 32-63 2550 **/ 2551 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, 2552 const u64 cd_type_cmd_tso_mss, 2553 const u32 cd_tunneling, const u32 cd_l2tag2) 2554 { 2555 struct i40e_tx_context_desc *context_desc; 2556 int i = tx_ring->next_to_use; 2557 2558 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && 2559 !cd_tunneling && !cd_l2tag2) 2560 return; 2561 2562 /* grab the next descriptor */ 2563 context_desc = I40E_TX_CTXTDESC(tx_ring, i); 2564 2565 i++; 2566 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2567 2568 /* cpu_to_le32 and assign to struct fields */ 2569 context_desc->tunneling_params = cpu_to_le32(cd_tunneling); 2570 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); 2571 context_desc->rsvd = cpu_to_le16(0); 2572 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); 2573 } 2574 2575 /** 2576 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions 2577 * @tx_ring: the ring to be checked 2578 * @size: the size buffer we want to assure is available 2579 * 2580 * Returns -EBUSY if a stop is needed, else 0 2581 **/ 2582 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 2583 { 2584 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 2585 /* Memory barrier before checking head and tail */ 2586 smp_mb(); 2587 2588 /* Check again in a case another CPU has just made room available. */ 2589 if (likely(I40E_DESC_UNUSED(tx_ring) < size)) 2590 return -EBUSY; 2591 2592 /* A reprieve! - use start_queue because it doesn't call schedule */ 2593 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 2594 ++tx_ring->tx_stats.restart_queue; 2595 return 0; 2596 } 2597 2598 /** 2599 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet 2600 * @skb: send buffer 2601 * 2602 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire 2603 * and so we need to figure out the cases where we need to linearize the skb. 2604 * 2605 * For TSO we need to count the TSO header and segment payload separately. 2606 * As such we need to check cases where we have 7 fragments or more as we 2607 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for 2608 * the segment payload in the first descriptor, and another 7 for the 2609 * fragments. 2610 **/ 2611 bool __i40e_chk_linearize(struct sk_buff *skb) 2612 { 2613 const struct skb_frag_struct *frag, *stale; 2614 int nr_frags, sum; 2615 2616 /* no need to check if number of frags is less than 7 */ 2617 nr_frags = skb_shinfo(skb)->nr_frags; 2618 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) 2619 return false; 2620 2621 /* We need to walk through the list and validate that each group 2622 * of 6 fragments totals at least gso_size. However we don't need 2623 * to perform such validation on the last 6 since the last 6 cannot 2624 * inherit any data from a descriptor after them. 2625 */ 2626 nr_frags -= I40E_MAX_BUFFER_TXD - 2; 2627 frag = &skb_shinfo(skb)->frags[0]; 2628 2629 /* Initialize size to the negative value of gso_size minus 1. We 2630 * use this as the worst case scenerio in which the frag ahead 2631 * of us only provides one byte which is why we are limited to 6 2632 * descriptors for a single transmit as the header and previous 2633 * fragment are already consuming 2 descriptors. 2634 */ 2635 sum = 1 - skb_shinfo(skb)->gso_size; 2636 2637 /* Add size of frags 0 through 4 to create our initial sum */ 2638 sum += skb_frag_size(frag++); 2639 sum += skb_frag_size(frag++); 2640 sum += skb_frag_size(frag++); 2641 sum += skb_frag_size(frag++); 2642 sum += skb_frag_size(frag++); 2643 2644 /* Walk through fragments adding latest fragment, testing it, and 2645 * then removing stale fragments from the sum. 2646 */ 2647 stale = &skb_shinfo(skb)->frags[0]; 2648 for (;;) { 2649 sum += skb_frag_size(frag++); 2650 2651 /* if sum is negative we failed to make sufficient progress */ 2652 if (sum < 0) 2653 return true; 2654 2655 /* use pre-decrement to avoid processing last fragment */ 2656 if (!--nr_frags) 2657 break; 2658 2659 sum -= skb_frag_size(stale++); 2660 } 2661 2662 return false; 2663 } 2664 2665 /** 2666 * i40e_tx_map - Build the Tx descriptor 2667 * @tx_ring: ring to send buffer on 2668 * @skb: send buffer 2669 * @first: first buffer info buffer to use 2670 * @tx_flags: collected send information 2671 * @hdr_len: size of the packet header 2672 * @td_cmd: the command field in the descriptor 2673 * @td_offset: offset for checksum or crc 2674 **/ 2675 #ifdef I40E_FCOE 2676 inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 2677 struct i40e_tx_buffer *first, u32 tx_flags, 2678 const u8 hdr_len, u32 td_cmd, u32 td_offset) 2679 #else 2680 static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 2681 struct i40e_tx_buffer *first, u32 tx_flags, 2682 const u8 hdr_len, u32 td_cmd, u32 td_offset) 2683 #endif 2684 { 2685 unsigned int data_len = skb->data_len; 2686 unsigned int size = skb_headlen(skb); 2687 struct skb_frag_struct *frag; 2688 struct i40e_tx_buffer *tx_bi; 2689 struct i40e_tx_desc *tx_desc; 2690 u16 i = tx_ring->next_to_use; 2691 u32 td_tag = 0; 2692 dma_addr_t dma; 2693 u16 gso_segs; 2694 u16 desc_count = 0; 2695 bool tail_bump = true; 2696 bool do_rs = false; 2697 2698 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { 2699 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; 2700 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> 2701 I40E_TX_FLAGS_VLAN_SHIFT; 2702 } 2703 2704 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) 2705 gso_segs = skb_shinfo(skb)->gso_segs; 2706 else 2707 gso_segs = 1; 2708 2709 /* multiply data chunks by size of headers */ 2710 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len); 2711 first->gso_segs = gso_segs; 2712 first->skb = skb; 2713 first->tx_flags = tx_flags; 2714 2715 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 2716 2717 tx_desc = I40E_TX_DESC(tx_ring, i); 2718 tx_bi = first; 2719 2720 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 2721 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 2722 2723 if (dma_mapping_error(tx_ring->dev, dma)) 2724 goto dma_error; 2725 2726 /* record length, and DMA address */ 2727 dma_unmap_len_set(tx_bi, len, size); 2728 dma_unmap_addr_set(tx_bi, dma, dma); 2729 2730 /* align size to end of page */ 2731 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); 2732 tx_desc->buffer_addr = cpu_to_le64(dma); 2733 2734 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { 2735 tx_desc->cmd_type_offset_bsz = 2736 build_ctob(td_cmd, td_offset, 2737 max_data, td_tag); 2738 2739 tx_desc++; 2740 i++; 2741 desc_count++; 2742 2743 if (i == tx_ring->count) { 2744 tx_desc = I40E_TX_DESC(tx_ring, 0); 2745 i = 0; 2746 } 2747 2748 dma += max_data; 2749 size -= max_data; 2750 2751 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 2752 tx_desc->buffer_addr = cpu_to_le64(dma); 2753 } 2754 2755 if (likely(!data_len)) 2756 break; 2757 2758 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, 2759 size, td_tag); 2760 2761 tx_desc++; 2762 i++; 2763 desc_count++; 2764 2765 if (i == tx_ring->count) { 2766 tx_desc = I40E_TX_DESC(tx_ring, 0); 2767 i = 0; 2768 } 2769 2770 size = skb_frag_size(frag); 2771 data_len -= size; 2772 2773 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 2774 DMA_TO_DEVICE); 2775 2776 tx_bi = &tx_ring->tx_bi[i]; 2777 } 2778 2779 /* set next_to_watch value indicating a packet is present */ 2780 first->next_to_watch = tx_desc; 2781 2782 i++; 2783 if (i == tx_ring->count) 2784 i = 0; 2785 2786 tx_ring->next_to_use = i; 2787 2788 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev, 2789 tx_ring->queue_index), 2790 first->bytecount); 2791 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); 2792 2793 /* Algorithm to optimize tail and RS bit setting: 2794 * if xmit_more is supported 2795 * if xmit_more is true 2796 * do not update tail and do not mark RS bit. 2797 * if xmit_more is false and last xmit_more was false 2798 * if every packet spanned less than 4 desc 2799 * then set RS bit on 4th packet and update tail 2800 * on every packet 2801 * else 2802 * update tail and set RS bit on every packet. 2803 * if xmit_more is false and last_xmit_more was true 2804 * update tail and set RS bit. 2805 * 2806 * Optimization: wmb to be issued only in case of tail update. 2807 * Also optimize the Descriptor WB path for RS bit with the same 2808 * algorithm. 2809 * 2810 * Note: If there are less than 4 packets 2811 * pending and interrupts were disabled the service task will 2812 * trigger a force WB. 2813 */ 2814 if (skb->xmit_more && 2815 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, 2816 tx_ring->queue_index))) { 2817 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET; 2818 tail_bump = false; 2819 } else if (!skb->xmit_more && 2820 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, 2821 tx_ring->queue_index)) && 2822 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) && 2823 (tx_ring->packet_stride < WB_STRIDE) && 2824 (desc_count < WB_STRIDE)) { 2825 tx_ring->packet_stride++; 2826 } else { 2827 tx_ring->packet_stride = 0; 2828 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET; 2829 do_rs = true; 2830 } 2831 if (do_rs) 2832 tx_ring->packet_stride = 0; 2833 2834 tx_desc->cmd_type_offset_bsz = 2835 build_ctob(td_cmd, td_offset, size, td_tag) | 2836 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD : 2837 I40E_TX_DESC_CMD_EOP) << 2838 I40E_TXD_QW1_CMD_SHIFT); 2839 2840 /* notify HW of packet */ 2841 if (!tail_bump) 2842 prefetchw(tx_desc + 1); 2843 2844 if (tail_bump) { 2845 /* Force memory writes to complete before letting h/w 2846 * know there are new descriptors to fetch. (Only 2847 * applicable for weak-ordered memory model archs, 2848 * such as IA-64). 2849 */ 2850 wmb(); 2851 writel(i, tx_ring->tail); 2852 } 2853 2854 return; 2855 2856 dma_error: 2857 dev_info(tx_ring->dev, "TX DMA map failed\n"); 2858 2859 /* clear dma mappings for failed tx_bi map */ 2860 for (;;) { 2861 tx_bi = &tx_ring->tx_bi[i]; 2862 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); 2863 if (tx_bi == first) 2864 break; 2865 if (i == 0) 2866 i = tx_ring->count; 2867 i--; 2868 } 2869 2870 tx_ring->next_to_use = i; 2871 } 2872 2873 /** 2874 * i40e_xmit_frame_ring - Sends buffer on Tx ring 2875 * @skb: send buffer 2876 * @tx_ring: ring to send buffer on 2877 * 2878 * Returns NETDEV_TX_OK if sent, else an error code 2879 **/ 2880 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, 2881 struct i40e_ring *tx_ring) 2882 { 2883 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; 2884 u32 cd_tunneling = 0, cd_l2tag2 = 0; 2885 struct i40e_tx_buffer *first; 2886 u32 td_offset = 0; 2887 u32 tx_flags = 0; 2888 __be16 protocol; 2889 u32 td_cmd = 0; 2890 u8 hdr_len = 0; 2891 int tso, count; 2892 int tsyn; 2893 2894 /* prefetch the data, we'll need it later */ 2895 prefetch(skb->data); 2896 2897 count = i40e_xmit_descriptor_count(skb); 2898 if (i40e_chk_linearize(skb, count)) { 2899 if (__skb_linearize(skb)) 2900 goto out_drop; 2901 count = i40e_txd_use_count(skb->len); 2902 tx_ring->tx_stats.tx_linearize++; 2903 } 2904 2905 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, 2906 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, 2907 * + 4 desc gap to avoid the cache line where head is, 2908 * + 1 desc for context descriptor, 2909 * otherwise try next time 2910 */ 2911 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { 2912 tx_ring->tx_stats.tx_busy++; 2913 return NETDEV_TX_BUSY; 2914 } 2915 2916 /* prepare the xmit flags */ 2917 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) 2918 goto out_drop; 2919 2920 /* obtain protocol of skb */ 2921 protocol = vlan_get_protocol(skb); 2922 2923 /* record the location of the first descriptor for this packet */ 2924 first = &tx_ring->tx_bi[tx_ring->next_to_use]; 2925 2926 /* setup IPv4/IPv6 offloads */ 2927 if (protocol == htons(ETH_P_IP)) 2928 tx_flags |= I40E_TX_FLAGS_IPV4; 2929 else if (protocol == htons(ETH_P_IPV6)) 2930 tx_flags |= I40E_TX_FLAGS_IPV6; 2931 2932 tso = i40e_tso(skb, &hdr_len, &cd_type_cmd_tso_mss); 2933 2934 if (tso < 0) 2935 goto out_drop; 2936 else if (tso) 2937 tx_flags |= I40E_TX_FLAGS_TSO; 2938 2939 /* Always offload the checksum, since it's in the data descriptor */ 2940 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, 2941 tx_ring, &cd_tunneling); 2942 if (tso < 0) 2943 goto out_drop; 2944 2945 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); 2946 2947 if (tsyn) 2948 tx_flags |= I40E_TX_FLAGS_TSYN; 2949 2950 skb_tx_timestamp(skb); 2951 2952 /* always enable CRC insertion offload */ 2953 td_cmd |= I40E_TX_DESC_CMD_ICRC; 2954 2955 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, 2956 cd_tunneling, cd_l2tag2); 2957 2958 /* Add Flow Director ATR if it's enabled. 2959 * 2960 * NOTE: this must always be directly before the data descriptor. 2961 */ 2962 i40e_atr(tx_ring, skb, tx_flags); 2963 2964 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, 2965 td_cmd, td_offset); 2966 2967 return NETDEV_TX_OK; 2968 2969 out_drop: 2970 dev_kfree_skb_any(skb); 2971 return NETDEV_TX_OK; 2972 } 2973 2974 /** 2975 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer 2976 * @skb: send buffer 2977 * @netdev: network interface device structure 2978 * 2979 * Returns NETDEV_TX_OK if sent, else an error code 2980 **/ 2981 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2982 { 2983 struct i40e_netdev_priv *np = netdev_priv(netdev); 2984 struct i40e_vsi *vsi = np->vsi; 2985 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; 2986 2987 /* hardware can't handle really short frames, hardware padding works 2988 * beyond this point 2989 */ 2990 if (skb_put_padto(skb, I40E_MIN_TX_LEN)) 2991 return NETDEV_TX_OK; 2992 2993 return i40e_xmit_frame_ring(skb, tx_ring); 2994 } 2995