1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #ifndef _I40E_REGISTER_H_ 5 #define _I40E_REGISTER_H_ 6 7 /* I40E_MASK is a macro used on 32 bit registers */ 8 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift)) 9 10 #define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30 11 #define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT) 12 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */ 13 #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */ 14 #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */ 15 #define I40E_PF_ARQH_ARQH_SHIFT 0 16 #define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT) 17 #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */ 18 #define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 19 #define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT) 20 #define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 21 #define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT) 22 #define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 23 #define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT) 24 #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 25 #define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT) 26 #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 27 #define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 28 #define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 29 #define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */ 30 #define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */ 31 #define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 32 #define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT) 33 #define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 34 #define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT) 35 #define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 36 #define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT) 37 #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 38 #define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT) 39 #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 40 #define I40E_PRT_SWR_PM_THR 0x0026CD00 /* Reset: CORER */ 41 #define I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT 0 42 #define I40E_PRT_SWR_PM_THR_THRESHOLD_MASK I40E_MASK(0xFF, I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT) 43 #define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */ 44 #define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3 45 #define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT) 46 #define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */ 47 #define I40E_PRTDCB_GENC_NUMTC_SHIFT 2 48 #define I40E_PRTDCB_GENC_NUMTC_MASK I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT) 49 #define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16 50 #define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT) 51 #define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */ 52 #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0 53 #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT) 54 #define I40E_PRTDCB_MFLCN 0x001E2400 /* Reset: GLOBR */ 55 #define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0 56 #define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT) 57 #define I40E_PRTDCB_MFLCN_DPF_SHIFT 1 58 #define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT) 59 #define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2 60 #define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIFT) 61 #define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3 62 #define I40E_PRTDCB_MFLCN_RFCE_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT) 63 #define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4 64 #define I40E_PRTDCB_MFLCN_RPFCE_MASK I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT) 65 #define I40E_PRTDCB_RETSC 0x001223E0 /* Reset: CORER */ 66 #define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0 67 #define I40E_PRTDCB_RETSC_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) 68 #define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1 69 #define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) 70 #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2 71 #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) 72 #define I40E_PRTDCB_RETSC_LLTC_SHIFT 8 73 #define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT) 74 #define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 75 #define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 76 #define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 77 #define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) 78 #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 79 #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) 80 #define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 81 #define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1u, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) 82 #define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */ 83 #define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 84 #define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) 85 #define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 86 #define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) 87 #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 88 #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) 89 #define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */ 90 #define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0 91 #define I40E_PRTDCB_RUP_NOVLANUP_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT) 92 #define I40E_PRTDCB_RUP2TC 0x001C09A0 /* Reset: CORER */ 93 #define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0 94 #define I40E_PRTDCB_RUP2TC_UP0TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT) 95 #define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3 96 #define I40E_PRTDCB_RUP2TC_UP1TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT) 97 #define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6 98 #define I40E_PRTDCB_RUP2TC_UP2TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT) 99 #define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9 100 #define I40E_PRTDCB_RUP2TC_UP3TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT) 101 #define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12 102 #define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT) 103 #define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15 104 #define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT) 105 #define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18 106 #define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) 107 #define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 108 #define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT) 109 #define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 110 #define I40E_PRTDCB_RUPTQ_MAX_INDEX 7 111 #define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0 112 #define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT) 113 #define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */ 114 #define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 115 #define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) 116 #define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 117 #define I40E_PRTDCB_TCMSTC_MAX_INDEX 7 118 #define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0 119 #define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT) 120 #define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */ 121 #define I40E_PRTDCB_TCPMC_CPM_SHIFT 0 122 #define I40E_PRTDCB_TCPMC_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT) 123 #define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13 124 #define I40E_PRTDCB_TCPMC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT) 125 #define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30 126 #define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT) 127 #define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 128 #define I40E_PRTDCB_TCWSTC_MAX_INDEX 7 129 #define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0 130 #define I40E_PRTDCB_TCWSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT) 131 #define I40E_PRTDCB_TDPMC 0x000A0180 /* Reset: CORER */ 132 #define I40E_PRTDCB_TDPMC_DPM_SHIFT 0 133 #define I40E_PRTDCB_TDPMC_DPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT) 134 #define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30 135 #define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT) 136 #define I40E_PRTDCB_TETSC_TCB 0x000AE060 /* Reset: CORER */ 137 #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0 138 #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, \ 139 I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT) 140 #define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8 141 #define I40E_PRTDCB_TETSC_TCB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT) 142 #define I40E_PRTDCB_TETSC_TPB 0x00098060 /* Reset: CORER */ 143 #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0 144 #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, \ 145 I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT) 146 #define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8 147 #define I40E_PRTDCB_TETSC_TPB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT) 148 #define I40E_PRTDCB_TFCS 0x001E4560 /* Reset: GLOBR */ 149 #define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0 150 #define I40E_PRTDCB_TFCS_TXOFF_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT) 151 #define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8 152 #define I40E_PRTDCB_TFCS_TXOFF0_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF0_SHIFT) 153 #define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9 154 #define I40E_PRTDCB_TFCS_TXOFF1_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF1_SHIFT) 155 #define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10 156 #define I40E_PRTDCB_TFCS_TXOFF2_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF2_SHIFT) 157 #define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11 158 #define I40E_PRTDCB_TFCS_TXOFF3_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF3_SHIFT) 159 #define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12 160 #define I40E_PRTDCB_TFCS_TXOFF4_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF4_SHIFT) 161 #define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13 162 #define I40E_PRTDCB_TFCS_TXOFF5_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF5_SHIFT) 163 #define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14 164 #define I40E_PRTDCB_TFCS_TXOFF6_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT) 165 #define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15 166 #define I40E_PRTDCB_TFCS_TXOFF7_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT) 167 #define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */ 168 #define I40E_PRTDCB_TPFCTS_MAX_INDEX 7 169 #define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0 170 #define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT) 171 #define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 172 #define I40E_GL_FWSTS_FWS1B_SHIFT 16 173 #define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) 174 #define I40E_GL_FWSTS_FWS1B_EMPR_0 I40E_MASK(0x20, I40E_GL_FWSTS_FWS1B_SHIFT) 175 #define I40E_GL_FWSTS_FWS1B_EMPR_10 I40E_MASK(0x2A, I40E_GL_FWSTS_FWS1B_SHIFT) 176 #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT) 177 #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0x31, I40E_GL_FWSTS_FWS1B_SHIFT) 178 #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK I40E_MASK(0x32, I40E_GL_FWSTS_FWS1B_SHIFT) 179 #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT) 180 #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT) 181 #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT) 182 #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */ 183 #define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29 184 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0 185 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 186 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3 187 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 188 #define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4 189 #define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5 190 #define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6 191 #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7 192 #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 193 #define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11 194 #define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 195 #define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 196 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19 197 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 198 #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 199 #define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */ 200 #define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5 201 #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6 202 #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 203 #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 204 #define I40E_GLGEN_MSCA_MDIADD_SHIFT 0 205 #define I40E_GLGEN_MSCA_DEVADD_SHIFT 16 206 #define I40E_GLGEN_MSCA_PHYADD_SHIFT 21 207 #define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 208 #define I40E_GLGEN_MSCA_OPCODE_MASK(_i) I40E_MASK(_i, I40E_GLGEN_MSCA_OPCODE_SHIFT) 209 #define I40E_GLGEN_MSCA_STCODE_SHIFT 28 210 #define I40E_GLGEN_MSCA_STCODE_MASK(_i) I40E_MASK(_i, I40E_GLGEN_MSCA_STCODE_SHIFT) 211 #define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 212 #define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT) 213 #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 214 #define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) 215 #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 216 #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 217 #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 218 #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 219 #define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ 220 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 221 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT) 222 #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16 223 #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT) 224 #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */ 225 #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 226 #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) 227 #define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2 228 #define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT) 229 #define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */ 230 #define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 231 #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) 232 #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */ 233 #define I40E_GLGEN_RTRIG_CORER_SHIFT 0 234 #define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT) 235 #define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 236 #define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT) 237 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */ 238 #define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */ 239 #define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */ 240 #define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */ 241 #define I40E_PFGEN_CTRL_PFSWR_SHIFT 0 242 #define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT) 243 #define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */ 244 #define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0 245 #define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT) 246 #define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */ 247 #define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0 248 #define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT) 249 #define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */ 250 #define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 251 #define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 252 #define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0 253 #define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT) 254 #define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 255 #define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0 256 #define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT) 257 #define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 258 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0 259 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT) 260 #define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 261 #define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */ 262 #define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 263 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0 264 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT) 265 #define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 266 #define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */ 267 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0 268 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT) 269 #define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */ 270 #define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */ 271 #define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */ 272 #define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 273 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0 274 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT) 275 #define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 276 #define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */ 277 #define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 278 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0 279 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT) 280 #define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 281 #define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */ 282 #define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */ 283 #define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */ 284 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */ 285 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0 286 #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16 287 #define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */ 288 #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31 289 #define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */ 290 #define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */ 291 #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0 292 #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1 293 #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2 294 #define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */ 295 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4 296 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT) 297 #define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */ 298 #define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0 299 #define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11 300 #define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30 301 #define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT) 302 #define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 303 #define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0 304 #define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11 305 #define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 306 #define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 307 #define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) 308 #define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */ 309 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1 310 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT) 311 #define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */ 312 #define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 313 #define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT) 314 #define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1 315 #define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT) 316 #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 317 #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 318 #define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 319 #define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) 320 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 321 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 322 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 323 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 324 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 325 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT) 326 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 327 #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0 328 #define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT) 329 #define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1 330 #define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT) 331 #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 332 #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 333 #define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3 334 #define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) 335 #define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5 336 #define I40E_PFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT) 337 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 338 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 339 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 340 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) 341 #define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */ 342 #define I40E_PFINT_ICR0_INTEVENT_SHIFT 0 343 #define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT) 344 #define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1 345 #define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT) 346 #define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16 347 #define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT) 348 #define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19 349 #define I40E_PFINT_ICR0_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_MAL_DETECT_SHIFT) 350 #define I40E_PFINT_ICR0_GRST_SHIFT 20 351 #define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT) 352 #define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21 353 #define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT) 354 #define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23 355 #define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT) 356 #define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26 357 #define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT) 358 #define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28 359 #define I40E_PFINT_ICR0_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PE_CRITERR_SHIFT) 360 #define I40E_PFINT_ICR0_VFLR_SHIFT 29 361 #define I40E_PFINT_ICR0_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_VFLR_SHIFT) 362 #define I40E_PFINT_ICR0_ADMINQ_SHIFT 30 363 #define I40E_PFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT) 364 #define I40E_PFINT_ICR0_SWINT_SHIFT 31 365 #define I40E_PFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT) 366 #define I40E_PFINT_ICR0_ENA 0x00038800 /* Reset: CORER */ 367 #define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16 368 #define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT) 369 #define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19 370 #define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT) 371 #define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20 372 #define I40E_PFINT_ICR0_ENA_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GRST_SHIFT) 373 #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21 374 #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT) 375 #define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22 376 #define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT) 377 #define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23 378 #define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT) 379 #define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26 380 #define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT) 381 #define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28 382 #define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT) 383 #define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29 384 #define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT) 385 #define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30 386 #define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT) 387 #define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */ 388 #define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */ 389 #define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */ 390 #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 391 #define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 392 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 393 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 394 #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 395 #define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 396 #define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */ 397 #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 398 #define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 399 #define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT) 400 #define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 401 #define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT) 402 #define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13 403 #define I40E_QINT_RQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) 404 #define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16 405 #define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) 406 #define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27 407 #define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30 408 #define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) 409 #define I40E_QINT_RQCTL_INTEVENT_SHIFT 31 410 #define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT) 411 #define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 412 #define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0 413 #define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT) 414 #define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11 415 #define I40E_QINT_TQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT) 416 #define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13 417 #define I40E_QINT_TQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) 418 #define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16 419 #define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) 420 #define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27 421 #define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30 422 #define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT) 423 #define I40E_QINT_TQCTL_INTEVENT_SHIFT 31 424 #define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT) 425 #define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 426 #define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 427 #define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1 428 #define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT) 429 #define I40E_VFINT_ICR0_ADMINQ_SHIFT 30 430 #define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT) 431 #define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 432 #define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 433 #define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 434 #define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 435 #define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30 436 #define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT) 437 #define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 438 #define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0 439 #define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11 440 #define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16 441 #define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT) 442 #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 443 #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) 444 #define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30 445 #define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT) 446 #define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 447 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 448 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) 449 #define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 450 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 451 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 452 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 453 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 454 #define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */ 455 #define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0 456 #define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT) 457 #define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */ 458 #define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */ 459 #define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */ 460 #define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */ 461 #define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 462 #define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 463 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 464 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 465 #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 466 #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) 467 #define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */ 468 #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 469 #define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 470 #define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 471 #define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT) 472 #define I40E_PFLAN_QALLOC_VALID_SHIFT 31 473 #define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT) 474 #define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 475 #define I40E_QRX_ENA_QENA_REQ_SHIFT 0 476 #define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT) 477 #define I40E_QRX_ENA_QENA_STAT_SHIFT 2 478 #define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT) 479 #define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 480 #define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 481 #define I40E_QTX_CTL_PFVF_Q_SHIFT 0 482 #define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT) 483 #define I40E_QTX_CTL_PF_INDX_SHIFT 2 484 #define I40E_QTX_CTL_PF_INDX_MASK I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT) 485 #define I40E_QTX_CTL_VFVM_INDX_SHIFT 7 486 #define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT) 487 #define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 488 #define I40E_QTX_ENA_QENA_REQ_SHIFT 0 489 #define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT) 490 #define I40E_QTX_ENA_QENA_STAT_SHIFT 2 491 #define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT) 492 #define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 493 #define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 494 #define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 495 #define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0 496 #define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT) 497 #define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */ 498 #define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0 499 #define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT) 500 #define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */ 501 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11 502 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT) 503 #define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */ 504 #define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */ 505 #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0 506 #define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT) 507 #define I40E_PRTGL_SAH_MFS_SHIFT 16 508 #define I40E_PRTGL_SAH_MFS_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT) 509 #define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */ 510 #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0 511 #define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT) 512 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 /* Reset: GLOBR */ 513 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0 514 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_MASK I40E_MASK(0x1, \ 515 I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_SHIFT) 516 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 /* Reset: GLOBR */ 517 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0 518 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_MASK I40E_MASK(0x1, \ 519 I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_SHIFT) 520 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 /* Reset: GLOBR */ 521 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0 522 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, \ 523 I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) 524 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 /* Reset: GLOBR */ 525 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0 526 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, \ 527 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) 528 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ 529 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8 530 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0 531 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK I40E_MASK(0xFFFF, \ 532 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) 533 #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 534 #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 535 #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 536 #define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */ 537 #define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5 538 #define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT) 539 #define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */ 540 #define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 541 #define I40E_GLNVM_SRCTL_START_SHIFT 30 542 #define I40E_GLNVM_SRCTL_DONE_SHIFT 31 543 #define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT) 544 #define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 545 #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 546 #define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT) 547 #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 548 #define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3 549 #define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT) 550 #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4 551 #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT) 552 #define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */ 553 #define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4 554 #define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT) 555 #define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */ 556 #define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2 557 #define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) 558 #define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13 559 #define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT) 560 #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ 561 #define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6 562 #define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT) 563 #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */ 564 #define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */ 565 #define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12 566 #define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */ 567 #define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */ 568 #define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */ 569 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30 570 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT) 571 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31 572 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT) 573 #define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16 574 #define I40E_PRTPM_EEER_TX_LPI_EN_MASK I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT) 575 #define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */ 576 #define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */ 577 #define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 578 #define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0 579 #define I40E_PRTRPB_DHW_DHW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT) 580 #define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 581 #define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0 582 #define I40E_PRTRPB_DLW_DLW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT) 583 #define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 584 #define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0 585 #define I40E_PRTRPB_DPS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT) 586 #define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 587 #define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0 588 #define I40E_PRTRPB_SHT_SHT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT) 589 #define I40E_PRTRPB_SHW 0x000AC580 /* Reset: CORER */ 590 #define I40E_PRTRPB_SHW_SHW_SHIFT 0 591 #define I40E_PRTRPB_SHW_SHW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT) 592 #define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 593 #define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0 594 #define I40E_PRTRPB_SLT_SLT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT) 595 #define I40E_PRTRPB_SLW 0x000AC6A0 /* Reset: CORER */ 596 #define I40E_PRTRPB_SLW_SLW_SHIFT 0 597 #define I40E_PRTRPB_SLW_SLW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT) 598 #define I40E_PRTRPB_SPS 0x000AC7C0 /* Reset: CORER */ 599 #define I40E_PRTRPB_SPS_SPS_SHIFT 0 600 #define I40E_PRTRPB_SPS_SPS_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT) 601 #define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */ 602 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0 603 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT) 604 #define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13 605 #define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT) 606 #define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 607 #define I40E_GLQF_HKEY_MAX_INDEX 12 608 #define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */ 609 #define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */ 610 #define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0 611 #define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT) 612 #define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5 613 #define I40E_PFQF_CTL_0_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT) 614 #define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10 615 #define I40E_PFQF_CTL_0_PFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) 616 #define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14 617 #define I40E_PFQF_CTL_0_PFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) 618 #define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16 619 #define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) 620 #define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17 621 #define I40E_PFQF_CTL_0_FD_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_FD_ENA_SHIFT) 622 #define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18 623 #define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT) 624 #define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19 625 #define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT) 626 #define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */ 627 #define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0 628 #define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT) 629 #define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */ 630 #define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0 631 #define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT) 632 #define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16 633 #define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT) 634 #define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */ 635 #define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */ 636 #define I40E_PFQF_HKEY_MAX_INDEX 12 637 #define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */ 638 #define I40E_PFQF_HLUT_MAX_INDEX 127 639 #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 640 #define I40E_PRTQF_FD_INSET_MAX_INDEX 63 641 #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 642 #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) 643 #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 644 #define I40E_PRTQF_FD_INSET_MAX_INDEX 63 645 #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 646 #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) 647 #define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */ 648 #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0 649 #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 650 #define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5 651 #define I40E_PRTQF_FLX_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 652 #define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10 653 #define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 654 #define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */ 655 #define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */ 656 #define I40E_VFQF_HKEY1_MAX_INDEX 12 657 #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */ 658 #define I40E_VFQF_HLUT1_MAX_INDEX 15 659 #define I40E_GL_RXERR1H(_i) (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 660 #define I40E_GL_RXERR1H_MAX_INDEX 143 661 #define I40E_GL_RXERR1H_RXERR1H_SHIFT 0 662 #define I40E_GL_RXERR1H_RXERR1H_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1H_RXERR1H_SHIFT) 663 #define I40E_GL_RXERR1L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 664 #define I40E_GL_RXERR1L_MAX_INDEX 143 665 #define I40E_GL_RXERR1L_RXERR1L_SHIFT 0 666 #define I40E_GL_RXERR1L_RXERR1L_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1L_RXERR1L_SHIFT) 667 #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 668 #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 669 #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 670 #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 671 #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 672 #define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 673 #define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 674 #define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 675 #define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 676 #define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 677 #define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 678 #define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 679 #define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 680 #define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 681 #define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 682 #define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 683 #define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 684 #define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 685 #define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 686 #define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 687 #define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 688 #define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 689 #define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 690 #define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 691 #define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 692 #define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 693 #define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 694 #define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 695 #define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 696 #define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 697 #define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 698 #define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 699 #define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 700 #define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 701 #define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 702 #define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 703 #define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 704 #define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 705 #define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 706 #define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 707 #define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 708 #define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 709 #define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 710 #define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 711 #define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 712 #define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 713 #define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 714 #define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 715 #define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 716 #define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 717 #define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 718 #define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 719 #define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 720 #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 721 #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 722 #define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 723 #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 724 #define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 725 #define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 726 #define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 727 #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 728 #define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 729 #define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 730 #define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 731 #define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 732 #define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 733 #define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 734 #define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 735 #define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 736 #define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 737 #define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 738 #define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 739 #define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 740 #define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 741 #define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 742 #define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 743 #define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 744 #define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 745 #define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 746 #define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 747 #define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 748 #define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 749 #define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 750 #define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 751 #define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 752 #define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 753 #define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 754 #define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 755 #define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 756 #define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 757 #define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 758 #define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 759 #define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 760 #define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 761 #define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 762 #define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 763 #define I40E_GLV_TEPC(_i) (0x00344000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 764 #define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 765 #define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 766 #define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 767 #define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 768 #define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 769 #define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 770 #define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 771 #define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 772 #define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 773 #define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 774 #define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 775 #define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 776 #define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */ 777 #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1 778 #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT) 779 #define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2 780 #define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT) 781 #define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8 782 #define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT) 783 #define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31 784 #define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT) 785 #define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */ 786 #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0 787 #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT) 788 #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16 789 #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT) 790 #define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24 791 #define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26 792 #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT) 793 #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31 794 #define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT) 795 #define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */ 796 #define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */ 797 #define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 798 #define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 799 #define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3 800 #define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */ 801 #define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0 802 #define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT) 803 #define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4 804 #define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT) 805 #define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */ 806 #define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */ 807 #define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */ 808 #define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */ 809 #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */ 810 #define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 811 #define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 812 #define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 813 #define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0 814 #define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1 815 #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16 816 #define I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT 17 817 #define I40E_PRTTSYN_AUX_0_PTPFLAG_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT) 818 #define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 819 #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0 820 #define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 821 #define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 822 #define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 823 #define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */ 824 #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */ 825 #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 826 #define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT) 827 #define I40E_GL_MDET_RX_EVENT_SHIFT 8 828 #define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT) 829 #define I40E_GL_MDET_RX_QUEUE_SHIFT 17 830 #define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT) 831 #define I40E_GL_MDET_RX_VALID_SHIFT 31 832 #define I40E_GL_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_RX_VALID_SHIFT) 833 #define I40E_GL_MDET_TX 0x000E6480 /* Reset: CORER */ 834 #define I40E_GL_MDET_TX_QUEUE_SHIFT 0 835 #define I40E_GL_MDET_TX_QUEUE_MASK I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT) 836 #define I40E_GL_MDET_TX_VF_NUM_SHIFT 12 837 #define I40E_GL_MDET_TX_VF_NUM_MASK I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT) 838 #define I40E_GL_MDET_TX_PF_NUM_SHIFT 21 839 #define I40E_GL_MDET_TX_PF_NUM_MASK I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT) 840 #define I40E_GL_MDET_TX_EVENT_SHIFT 25 841 #define I40E_GL_MDET_TX_EVENT_MASK I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT) 842 #define I40E_GL_MDET_TX_VALID_SHIFT 31 843 #define I40E_GL_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT) 844 #define I40E_PF_MDET_RX 0x0012A400 /* Reset: CORER */ 845 #define I40E_PF_MDET_RX_VALID_SHIFT 0 846 #define I40E_PF_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_RX_VALID_SHIFT) 847 #define I40E_PF_MDET_TX 0x000E6400 /* Reset: CORER */ 848 #define I40E_PF_MDET_TX_VALID_SHIFT 0 849 #define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT) 850 #define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */ 851 #define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 852 #define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 853 #define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 854 #define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 855 #define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 856 #define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT) 857 #define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 858 #define I40E_VP_MDET_RX_VALID_SHIFT 0 859 #define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT) 860 #define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 861 #define I40E_VP_MDET_TX_VALID_SHIFT 0 862 #define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT) 863 #define I40E_PFPM_APM 0x000B8080 /* Reset: POR */ 864 #define I40E_PFPM_APM_APME_SHIFT 0 865 #define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT) 866 #define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */ 867 #define I40E_PFPM_WUFC_MAG_SHIFT 1 868 #define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT) 869 #define I40E_VFQF_HLUT_MAX_INDEX 15 870 871 872 873 874 #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30 875 #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT) 876 #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30 877 #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT) 878 #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 879 #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 880 #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 881 882 #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 883 884 885 886 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 887 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */ 888 #define I40E_GLQF_ORT_PIT_INDX_SHIFT 0 889 #define I40E_GLQF_ORT_PIT_INDX_MASK I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT) 890 #define I40E_GLQF_ORT_FIELD_CNT_SHIFT 5 891 #define I40E_GLQF_ORT_FIELD_CNT_MASK I40E_MASK(0x3, I40E_GLQF_ORT_FIELD_CNT_SHIFT) 892 #define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7 893 #define I40E_GLQF_ORT_FLX_PAYLOAD_MASK I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) 894 #define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 895 #define I40E_FDEVICT_PCTYPE_DEFAULT 0xc03 896 /* Redefined for X722 family */ 897 #define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */ 898 #endif /* _I40E_REGISTER_H_ */ 899