1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_prototype.h" 28 29 /** 30 * i40e_init_nvm_ops - Initialize NVM function pointers 31 * @hw: pointer to the HW structure 32 * 33 * Setup the function pointers and the NVM info structure. Should be called 34 * once per NVM initialization, e.g. inside the i40e_init_shared_code(). 35 * Please notice that the NVM term is used here (& in all methods covered 36 * in this file) as an equivalent of the FLASH part mapped into the SR. 37 * We are accessing FLASH always thru the Shadow RAM. 38 **/ 39 i40e_status i40e_init_nvm(struct i40e_hw *hw) 40 { 41 struct i40e_nvm_info *nvm = &hw->nvm; 42 i40e_status ret_code = 0; 43 u32 fla, gens; 44 u8 sr_size; 45 46 /* The SR size is stored regardless of the nvm programming mode 47 * as the blank mode may be used in the factory line. 48 */ 49 gens = rd32(hw, I40E_GLNVM_GENS); 50 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >> 51 I40E_GLNVM_GENS_SR_SIZE_SHIFT); 52 /* Switching to words (sr_size contains power of 2KB) */ 53 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; 54 55 /* Check if we are in the normal or blank NVM programming mode */ 56 fla = rd32(hw, I40E_GLNVM_FLA); 57 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */ 58 /* Max NVM timeout */ 59 nvm->timeout = I40E_MAX_NVM_TIMEOUT; 60 nvm->blank_nvm_mode = false; 61 } else { /* Blank programming mode */ 62 nvm->blank_nvm_mode = true; 63 ret_code = I40E_ERR_NVM_BLANK_MODE; 64 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n"); 65 } 66 67 return ret_code; 68 } 69 70 /** 71 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership 72 * @hw: pointer to the HW structure 73 * @access: NVM access type (read or write) 74 * 75 * This function will request NVM ownership for reading 76 * via the proper Admin Command. 77 **/ 78 i40e_status i40e_acquire_nvm(struct i40e_hw *hw, 79 enum i40e_aq_resource_access_type access) 80 { 81 i40e_status ret_code = 0; 82 u64 gtime, timeout; 83 u64 time_left = 0; 84 85 if (hw->nvm.blank_nvm_mode) 86 goto i40e_i40e_acquire_nvm_exit; 87 88 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access, 89 0, &time_left, NULL); 90 /* Reading the Global Device Timer */ 91 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 92 93 /* Store the timeout */ 94 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime; 95 96 if (ret_code) 97 i40e_debug(hw, I40E_DEBUG_NVM, 98 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n", 99 access, time_left, ret_code, hw->aq.asq_last_status); 100 101 if (ret_code && time_left) { 102 /* Poll until the current NVM owner timeouts */ 103 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime; 104 while ((gtime < timeout) && time_left) { 105 usleep_range(10000, 20000); 106 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 107 ret_code = i40e_aq_request_resource(hw, 108 I40E_NVM_RESOURCE_ID, 109 access, 0, &time_left, 110 NULL); 111 if (!ret_code) { 112 hw->nvm.hw_semaphore_timeout = 113 I40E_MS_TO_GTIME(time_left) + gtime; 114 break; 115 } 116 } 117 if (ret_code) { 118 hw->nvm.hw_semaphore_timeout = 0; 119 i40e_debug(hw, I40E_DEBUG_NVM, 120 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n", 121 time_left, ret_code, hw->aq.asq_last_status); 122 } 123 } 124 125 i40e_i40e_acquire_nvm_exit: 126 return ret_code; 127 } 128 129 /** 130 * i40e_release_nvm - Generic request for releasing the NVM ownership 131 * @hw: pointer to the HW structure 132 * 133 * This function will release NVM resource via the proper Admin Command. 134 **/ 135 void i40e_release_nvm(struct i40e_hw *hw) 136 { 137 if (!hw->nvm.blank_nvm_mode) 138 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); 139 } 140 141 /** 142 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit 143 * @hw: pointer to the HW structure 144 * 145 * Polls the SRCTL Shadow RAM register done bit. 146 **/ 147 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw) 148 { 149 i40e_status ret_code = I40E_ERR_TIMEOUT; 150 u32 srctl, wait_cnt; 151 152 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */ 153 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) { 154 srctl = rd32(hw, I40E_GLNVM_SRCTL); 155 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) { 156 ret_code = 0; 157 break; 158 } 159 udelay(5); 160 } 161 if (ret_code == I40E_ERR_TIMEOUT) 162 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set"); 163 return ret_code; 164 } 165 166 /** 167 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register 168 * @hw: pointer to the HW structure 169 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 170 * @data: word read from the Shadow RAM 171 * 172 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 173 **/ 174 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, 175 u16 *data) 176 { 177 i40e_status ret_code = I40E_ERR_TIMEOUT; 178 u32 sr_reg; 179 180 if (offset >= hw->nvm.sr_size) { 181 i40e_debug(hw, I40E_DEBUG_NVM, 182 "NVM read error: offset %d beyond Shadow RAM limit %d\n", 183 offset, hw->nvm.sr_size); 184 ret_code = I40E_ERR_PARAM; 185 goto read_nvm_exit; 186 } 187 188 /* Poll the done bit first */ 189 ret_code = i40e_poll_sr_srctl_done_bit(hw); 190 if (!ret_code) { 191 /* Write the address and start reading */ 192 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) | 193 BIT(I40E_GLNVM_SRCTL_START_SHIFT); 194 wr32(hw, I40E_GLNVM_SRCTL, sr_reg); 195 196 /* Poll I40E_GLNVM_SRCTL until the done bit is set */ 197 ret_code = i40e_poll_sr_srctl_done_bit(hw); 198 if (!ret_code) { 199 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); 200 *data = (u16)((sr_reg & 201 I40E_GLNVM_SRDATA_RDDATA_MASK) 202 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT); 203 } 204 } 205 if (ret_code) 206 i40e_debug(hw, I40E_DEBUG_NVM, 207 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n", 208 offset); 209 210 read_nvm_exit: 211 return ret_code; 212 } 213 214 /** 215 * i40e_read_nvm_aq - Read Shadow RAM. 216 * @hw: pointer to the HW structure. 217 * @module_pointer: module pointer location in words from the NVM beginning 218 * @offset: offset in words from module start 219 * @words: number of words to write 220 * @data: buffer with words to write to the Shadow RAM 221 * @last_command: tells the AdminQ that this is the last command 222 * 223 * Writes a 16 bit words buffer to the Shadow RAM using the admin command. 224 **/ 225 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer, 226 u32 offset, u16 words, void *data, 227 bool last_command) 228 { 229 i40e_status ret_code = I40E_ERR_NVM; 230 struct i40e_asq_cmd_details cmd_details; 231 232 memset(&cmd_details, 0, sizeof(cmd_details)); 233 234 /* Here we are checking the SR limit only for the flat memory model. 235 * We cannot do it for the module-based model, as we did not acquire 236 * the NVM resource yet (we cannot get the module pointer value). 237 * Firmware will check the module-based model. 238 */ 239 if ((offset + words) > hw->nvm.sr_size) 240 i40e_debug(hw, I40E_DEBUG_NVM, 241 "NVM write error: offset %d beyond Shadow RAM limit %d\n", 242 (offset + words), hw->nvm.sr_size); 243 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) 244 /* We can write only up to 4KB (one sector), in one AQ write */ 245 i40e_debug(hw, I40E_DEBUG_NVM, 246 "NVM write fail error: tried to write %d words, limit is %d.\n", 247 words, I40E_SR_SECTOR_SIZE_IN_WORDS); 248 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) 249 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) 250 /* A single write cannot spread over two sectors */ 251 i40e_debug(hw, I40E_DEBUG_NVM, 252 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", 253 offset, words); 254 else 255 ret_code = i40e_aq_read_nvm(hw, module_pointer, 256 2 * offset, /*bytes*/ 257 2 * words, /*bytes*/ 258 data, last_command, &cmd_details); 259 260 return ret_code; 261 } 262 263 /** 264 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ 265 * @hw: pointer to the HW structure 266 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 267 * @data: word read from the Shadow RAM 268 * 269 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 270 **/ 271 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset, 272 u16 *data) 273 { 274 i40e_status ret_code = I40E_ERR_TIMEOUT; 275 276 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true); 277 *data = le16_to_cpu(*(__le16 *)data); 278 279 return ret_code; 280 } 281 282 /** 283 * i40e_read_nvm_word - Reads Shadow RAM 284 * @hw: pointer to the HW structure 285 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 286 * @data: word read from the Shadow RAM 287 * 288 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 289 **/ 290 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, 291 u16 *data) 292 { 293 if (hw->mac.type == I40E_MAC_X722) 294 return i40e_read_nvm_word_aq(hw, offset, data); 295 return i40e_read_nvm_word_srctl(hw, offset, data); 296 } 297 298 /** 299 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register 300 * @hw: pointer to the HW structure 301 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 302 * @words: (in) number of words to read; (out) number of words actually read 303 * @data: words read from the Shadow RAM 304 * 305 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 306 * method. The buffer read is preceded by the NVM ownership take 307 * and followed by the release. 308 **/ 309 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset, 310 u16 *words, u16 *data) 311 { 312 i40e_status ret_code = 0; 313 u16 index, word; 314 315 /* Loop thru the selected region */ 316 for (word = 0; word < *words; word++) { 317 index = offset + word; 318 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]); 319 if (ret_code) 320 break; 321 } 322 323 /* Update the number of words read from the Shadow RAM */ 324 *words = word; 325 326 return ret_code; 327 } 328 329 /** 330 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ 331 * @hw: pointer to the HW structure 332 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 333 * @words: (in) number of words to read; (out) number of words actually read 334 * @data: words read from the Shadow RAM 335 * 336 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq() 337 * method. The buffer read is preceded by the NVM ownership take 338 * and followed by the release. 339 **/ 340 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset, 341 u16 *words, u16 *data) 342 { 343 i40e_status ret_code; 344 u16 read_size = *words; 345 bool last_cmd = false; 346 u16 words_read = 0; 347 u16 i = 0; 348 349 do { 350 /* Calculate number of bytes we should read in this step. 351 * FVL AQ do not allow to read more than one page at a time or 352 * to cross page boundaries. 353 */ 354 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS) 355 read_size = min(*words, 356 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS - 357 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS))); 358 else 359 read_size = min((*words - words_read), 360 I40E_SR_SECTOR_SIZE_IN_WORDS); 361 362 /* Check if this is last command, if so set proper flag */ 363 if ((words_read + read_size) >= *words) 364 last_cmd = true; 365 366 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size, 367 data + words_read, last_cmd); 368 if (ret_code) 369 goto read_nvm_buffer_aq_exit; 370 371 /* Increment counter for words already read and move offset to 372 * new read location 373 */ 374 words_read += read_size; 375 offset += read_size; 376 } while (words_read < *words); 377 378 for (i = 0; i < *words; i++) 379 data[i] = le16_to_cpu(((__le16 *)data)[i]); 380 381 read_nvm_buffer_aq_exit: 382 *words = words_read; 383 return ret_code; 384 } 385 386 /** 387 * i40e_read_nvm_buffer - Reads Shadow RAM buffer 388 * @hw: pointer to the HW structure 389 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 390 * @words: (in) number of words to read; (out) number of words actually read 391 * @data: words read from the Shadow RAM 392 * 393 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 394 * method. The buffer read is preceded by the NVM ownership take 395 * and followed by the release. 396 **/ 397 i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, 398 u16 *words, u16 *data) 399 { 400 if (hw->mac.type == I40E_MAC_X722) 401 return i40e_read_nvm_buffer_aq(hw, offset, words, data); 402 return i40e_read_nvm_buffer_srctl(hw, offset, words, data); 403 } 404 405 /** 406 * i40e_write_nvm_aq - Writes Shadow RAM. 407 * @hw: pointer to the HW structure. 408 * @module_pointer: module pointer location in words from the NVM beginning 409 * @offset: offset in words from module start 410 * @words: number of words to write 411 * @data: buffer with words to write to the Shadow RAM 412 * @last_command: tells the AdminQ that this is the last command 413 * 414 * Writes a 16 bit words buffer to the Shadow RAM using the admin command. 415 **/ 416 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer, 417 u32 offset, u16 words, void *data, 418 bool last_command) 419 { 420 i40e_status ret_code = I40E_ERR_NVM; 421 422 /* Here we are checking the SR limit only for the flat memory model. 423 * We cannot do it for the module-based model, as we did not acquire 424 * the NVM resource yet (we cannot get the module pointer value). 425 * Firmware will check the module-based model. 426 */ 427 if ((offset + words) > hw->nvm.sr_size) 428 i40e_debug(hw, I40E_DEBUG_NVM, 429 "NVM write error: offset %d beyond Shadow RAM limit %d\n", 430 (offset + words), hw->nvm.sr_size); 431 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) 432 /* We can write only up to 4KB (one sector), in one AQ write */ 433 i40e_debug(hw, I40E_DEBUG_NVM, 434 "NVM write fail error: tried to write %d words, limit is %d.\n", 435 words, I40E_SR_SECTOR_SIZE_IN_WORDS); 436 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) 437 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) 438 /* A single write cannot spread over two sectors */ 439 i40e_debug(hw, I40E_DEBUG_NVM, 440 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", 441 offset, words); 442 else 443 ret_code = i40e_aq_update_nvm(hw, module_pointer, 444 2 * offset, /*bytes*/ 445 2 * words, /*bytes*/ 446 data, last_command, NULL); 447 448 return ret_code; 449 } 450 451 /** 452 * i40e_calc_nvm_checksum - Calculates and returns the checksum 453 * @hw: pointer to hardware structure 454 * @checksum: pointer to the checksum 455 * 456 * This function calculates SW Checksum that covers the whole 64kB shadow RAM 457 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD 458 * is customer specific and unknown. Therefore, this function skips all maximum 459 * possible size of VPD (1kB). 460 **/ 461 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw, 462 u16 *checksum) 463 { 464 i40e_status ret_code = 0; 465 struct i40e_virt_mem vmem; 466 u16 pcie_alt_module = 0; 467 u16 checksum_local = 0; 468 u16 vpd_module = 0; 469 u16 *data; 470 u16 i = 0; 471 472 ret_code = i40e_allocate_virt_mem(hw, &vmem, 473 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16)); 474 if (ret_code) 475 goto i40e_calc_nvm_checksum_exit; 476 data = (u16 *)vmem.va; 477 478 /* read pointer to VPD area */ 479 ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module); 480 if (ret_code) { 481 ret_code = I40E_ERR_NVM_CHECKSUM; 482 goto i40e_calc_nvm_checksum_exit; 483 } 484 485 /* read pointer to PCIe Alt Auto-load module */ 486 ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR, 487 &pcie_alt_module); 488 if (ret_code) { 489 ret_code = I40E_ERR_NVM_CHECKSUM; 490 goto i40e_calc_nvm_checksum_exit; 491 } 492 493 /* Calculate SW checksum that covers the whole 64kB shadow RAM 494 * except the VPD and PCIe ALT Auto-load modules 495 */ 496 for (i = 0; i < hw->nvm.sr_size; i++) { 497 /* Read SR page */ 498 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) { 499 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS; 500 501 ret_code = i40e_read_nvm_buffer(hw, i, &words, data); 502 if (ret_code) { 503 ret_code = I40E_ERR_NVM_CHECKSUM; 504 goto i40e_calc_nvm_checksum_exit; 505 } 506 } 507 508 /* Skip Checksum word */ 509 if (i == I40E_SR_SW_CHECKSUM_WORD) 510 continue; 511 /* Skip VPD module (convert byte size to word count) */ 512 if ((i >= (u32)vpd_module) && 513 (i < ((u32)vpd_module + 514 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) { 515 continue; 516 } 517 /* Skip PCIe ALT module (convert byte size to word count) */ 518 if ((i >= (u32)pcie_alt_module) && 519 (i < ((u32)pcie_alt_module + 520 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) { 521 continue; 522 } 523 524 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS]; 525 } 526 527 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local; 528 529 i40e_calc_nvm_checksum_exit: 530 i40e_free_virt_mem(hw, &vmem); 531 return ret_code; 532 } 533 534 /** 535 * i40e_update_nvm_checksum - Updates the NVM checksum 536 * @hw: pointer to hardware structure 537 * 538 * NVM ownership must be acquired before calling this function and released 539 * on ARQ completion event reception by caller. 540 * This function will commit SR to NVM. 541 **/ 542 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw) 543 { 544 i40e_status ret_code = 0; 545 u16 checksum; 546 547 ret_code = i40e_calc_nvm_checksum(hw, &checksum); 548 if (!ret_code) 549 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD, 550 1, &checksum, true); 551 552 return ret_code; 553 } 554 555 /** 556 * i40e_validate_nvm_checksum - Validate EEPROM checksum 557 * @hw: pointer to hardware structure 558 * @checksum: calculated checksum 559 * 560 * Performs checksum calculation and validates the NVM SW checksum. If the 561 * caller does not need checksum, the value can be NULL. 562 **/ 563 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw, 564 u16 *checksum) 565 { 566 i40e_status ret_code = 0; 567 u16 checksum_sr = 0; 568 u16 checksum_local = 0; 569 570 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local); 571 if (ret_code) 572 goto i40e_validate_nvm_checksum_exit; 573 574 /* Do not use i40e_read_nvm_word() because we do not want to take 575 * the synchronization semaphores twice here. 576 */ 577 i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr); 578 579 /* Verify read checksum from EEPROM is the same as 580 * calculated checksum 581 */ 582 if (checksum_local != checksum_sr) 583 ret_code = I40E_ERR_NVM_CHECKSUM; 584 585 /* If the user cares, return the calculated checksum */ 586 if (checksum) 587 *checksum = checksum_local; 588 589 i40e_validate_nvm_checksum_exit: 590 return ret_code; 591 } 592 593 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, 594 struct i40e_nvm_access *cmd, 595 u8 *bytes, int *errno); 596 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, 597 struct i40e_nvm_access *cmd, 598 u8 *bytes, int *errno); 599 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, 600 struct i40e_nvm_access *cmd, 601 u8 *bytes, int *errno); 602 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 603 struct i40e_nvm_access *cmd, 604 int *errno); 605 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 606 struct i40e_nvm_access *cmd, 607 int *errno); 608 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, 609 struct i40e_nvm_access *cmd, 610 u8 *bytes, int *errno); 611 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, 612 struct i40e_nvm_access *cmd, 613 u8 *bytes, int *errno); 614 static inline u8 i40e_nvmupd_get_module(u32 val) 615 { 616 return (u8)(val & I40E_NVM_MOD_PNT_MASK); 617 } 618 static inline u8 i40e_nvmupd_get_transaction(u32 val) 619 { 620 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT); 621 } 622 623 static char *i40e_nvm_update_state_str[] = { 624 "I40E_NVMUPD_INVALID", 625 "I40E_NVMUPD_READ_CON", 626 "I40E_NVMUPD_READ_SNT", 627 "I40E_NVMUPD_READ_LCB", 628 "I40E_NVMUPD_READ_SA", 629 "I40E_NVMUPD_WRITE_ERA", 630 "I40E_NVMUPD_WRITE_CON", 631 "I40E_NVMUPD_WRITE_SNT", 632 "I40E_NVMUPD_WRITE_LCB", 633 "I40E_NVMUPD_WRITE_SA", 634 "I40E_NVMUPD_CSUM_CON", 635 "I40E_NVMUPD_CSUM_SA", 636 "I40E_NVMUPD_CSUM_LCB", 637 }; 638 639 /** 640 * i40e_nvmupd_command - Process an NVM update command 641 * @hw: pointer to hardware structure 642 * @cmd: pointer to nvm update command 643 * @bytes: pointer to the data buffer 644 * @errno: pointer to return error code 645 * 646 * Dispatches command depending on what update state is current 647 **/ 648 i40e_status i40e_nvmupd_command(struct i40e_hw *hw, 649 struct i40e_nvm_access *cmd, 650 u8 *bytes, int *errno) 651 { 652 i40e_status status; 653 654 /* assume success */ 655 *errno = 0; 656 657 switch (hw->nvmupd_state) { 658 case I40E_NVMUPD_STATE_INIT: 659 status = i40e_nvmupd_state_init(hw, cmd, bytes, errno); 660 break; 661 662 case I40E_NVMUPD_STATE_READING: 663 status = i40e_nvmupd_state_reading(hw, cmd, bytes, errno); 664 break; 665 666 case I40E_NVMUPD_STATE_WRITING: 667 status = i40e_nvmupd_state_writing(hw, cmd, bytes, errno); 668 break; 669 670 default: 671 /* invalid state, should never happen */ 672 i40e_debug(hw, I40E_DEBUG_NVM, 673 "NVMUPD: no such state %d\n", hw->nvmupd_state); 674 status = I40E_NOT_SUPPORTED; 675 *errno = -ESRCH; 676 break; 677 } 678 return status; 679 } 680 681 /** 682 * i40e_nvmupd_state_init - Handle NVM update state Init 683 * @hw: pointer to hardware structure 684 * @cmd: pointer to nvm update command buffer 685 * @bytes: pointer to the data buffer 686 * @errno: pointer to return error code 687 * 688 * Process legitimate commands of the Init state and conditionally set next 689 * state. Reject all other commands. 690 **/ 691 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, 692 struct i40e_nvm_access *cmd, 693 u8 *bytes, int *errno) 694 { 695 i40e_status status = 0; 696 enum i40e_nvmupd_cmd upd_cmd; 697 698 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, errno); 699 700 switch (upd_cmd) { 701 case I40E_NVMUPD_READ_SA: 702 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 703 if (status) { 704 *errno = i40e_aq_rc_to_posix(status, 705 hw->aq.asq_last_status); 706 } else { 707 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno); 708 i40e_release_nvm(hw); 709 } 710 break; 711 712 case I40E_NVMUPD_READ_SNT: 713 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 714 if (status) { 715 *errno = i40e_aq_rc_to_posix(status, 716 hw->aq.asq_last_status); 717 } else { 718 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno); 719 if (status) 720 i40e_release_nvm(hw); 721 else 722 hw->nvmupd_state = I40E_NVMUPD_STATE_READING; 723 } 724 break; 725 726 case I40E_NVMUPD_WRITE_ERA: 727 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 728 if (status) { 729 *errno = i40e_aq_rc_to_posix(status, 730 hw->aq.asq_last_status); 731 } else { 732 status = i40e_nvmupd_nvm_erase(hw, cmd, errno); 733 if (status) 734 i40e_release_nvm(hw); 735 else 736 hw->aq.nvm_release_on_done = true; 737 } 738 break; 739 740 case I40E_NVMUPD_WRITE_SA: 741 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 742 if (status) { 743 *errno = i40e_aq_rc_to_posix(status, 744 hw->aq.asq_last_status); 745 } else { 746 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno); 747 if (status) 748 i40e_release_nvm(hw); 749 else 750 hw->aq.nvm_release_on_done = true; 751 } 752 break; 753 754 case I40E_NVMUPD_WRITE_SNT: 755 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 756 if (status) { 757 *errno = i40e_aq_rc_to_posix(status, 758 hw->aq.asq_last_status); 759 } else { 760 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno); 761 if (status) 762 i40e_release_nvm(hw); 763 else 764 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; 765 } 766 break; 767 768 case I40E_NVMUPD_CSUM_SA: 769 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 770 if (status) { 771 *errno = i40e_aq_rc_to_posix(status, 772 hw->aq.asq_last_status); 773 } else { 774 status = i40e_update_nvm_checksum(hw); 775 if (status) { 776 *errno = hw->aq.asq_last_status ? 777 i40e_aq_rc_to_posix(status, 778 hw->aq.asq_last_status) : 779 -EIO; 780 i40e_release_nvm(hw); 781 } else { 782 hw->aq.nvm_release_on_done = true; 783 } 784 } 785 break; 786 787 default: 788 i40e_debug(hw, I40E_DEBUG_NVM, 789 "NVMUPD: bad cmd %s in init state\n", 790 i40e_nvm_update_state_str[upd_cmd]); 791 status = I40E_ERR_NVM; 792 *errno = -ESRCH; 793 break; 794 } 795 return status; 796 } 797 798 /** 799 * i40e_nvmupd_state_reading - Handle NVM update state Reading 800 * @hw: pointer to hardware structure 801 * @cmd: pointer to nvm update command buffer 802 * @bytes: pointer to the data buffer 803 * @errno: pointer to return error code 804 * 805 * NVM ownership is already held. Process legitimate commands and set any 806 * change in state; reject all other commands. 807 **/ 808 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, 809 struct i40e_nvm_access *cmd, 810 u8 *bytes, int *errno) 811 { 812 i40e_status status; 813 enum i40e_nvmupd_cmd upd_cmd; 814 815 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, errno); 816 817 switch (upd_cmd) { 818 case I40E_NVMUPD_READ_SA: 819 case I40E_NVMUPD_READ_CON: 820 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno); 821 break; 822 823 case I40E_NVMUPD_READ_LCB: 824 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno); 825 i40e_release_nvm(hw); 826 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 827 break; 828 829 default: 830 i40e_debug(hw, I40E_DEBUG_NVM, 831 "NVMUPD: bad cmd %s in reading state.\n", 832 i40e_nvm_update_state_str[upd_cmd]); 833 status = I40E_NOT_SUPPORTED; 834 *errno = -ESRCH; 835 break; 836 } 837 return status; 838 } 839 840 /** 841 * i40e_nvmupd_state_writing - Handle NVM update state Writing 842 * @hw: pointer to hardware structure 843 * @cmd: pointer to nvm update command buffer 844 * @bytes: pointer to the data buffer 845 * @errno: pointer to return error code 846 * 847 * NVM ownership is already held. Process legitimate commands and set any 848 * change in state; reject all other commands 849 **/ 850 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, 851 struct i40e_nvm_access *cmd, 852 u8 *bytes, int *errno) 853 { 854 i40e_status status; 855 enum i40e_nvmupd_cmd upd_cmd; 856 bool retry_attempt = false; 857 858 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, errno); 859 860 retry: 861 switch (upd_cmd) { 862 case I40E_NVMUPD_WRITE_CON: 863 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno); 864 break; 865 866 case I40E_NVMUPD_WRITE_LCB: 867 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno); 868 if (!status) 869 hw->aq.nvm_release_on_done = true; 870 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 871 break; 872 873 case I40E_NVMUPD_CSUM_CON: 874 status = i40e_update_nvm_checksum(hw); 875 if (status) { 876 *errno = hw->aq.asq_last_status ? 877 i40e_aq_rc_to_posix(status, 878 hw->aq.asq_last_status) : 879 -EIO; 880 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 881 } 882 break; 883 884 case I40E_NVMUPD_CSUM_LCB: 885 status = i40e_update_nvm_checksum(hw); 886 if (status) 887 *errno = hw->aq.asq_last_status ? 888 i40e_aq_rc_to_posix(status, 889 hw->aq.asq_last_status) : 890 -EIO; 891 else 892 hw->aq.nvm_release_on_done = true; 893 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 894 break; 895 896 default: 897 i40e_debug(hw, I40E_DEBUG_NVM, 898 "NVMUPD: bad cmd %s in writing state.\n", 899 i40e_nvm_update_state_str[upd_cmd]); 900 status = I40E_NOT_SUPPORTED; 901 *errno = -ESRCH; 902 break; 903 } 904 905 /* In some circumstances, a multi-write transaction takes longer 906 * than the default 3 minute timeout on the write semaphore. If 907 * the write failed with an EBUSY status, this is likely the problem, 908 * so here we try to reacquire the semaphore then retry the write. 909 * We only do one retry, then give up. 910 */ 911 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) && 912 !retry_attempt) { 913 i40e_status old_status = status; 914 u32 old_asq_status = hw->aq.asq_last_status; 915 u32 gtime; 916 917 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 918 if (gtime >= hw->nvm.hw_semaphore_timeout) { 919 i40e_debug(hw, I40E_DEBUG_ALL, 920 "NVMUPD: write semaphore expired (%d >= %lld), retrying\n", 921 gtime, hw->nvm.hw_semaphore_timeout); 922 i40e_release_nvm(hw); 923 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 924 if (status) { 925 i40e_debug(hw, I40E_DEBUG_ALL, 926 "NVMUPD: write semaphore reacquire failed aq_err = %d\n", 927 hw->aq.asq_last_status); 928 status = old_status; 929 hw->aq.asq_last_status = old_asq_status; 930 } else { 931 retry_attempt = true; 932 goto retry; 933 } 934 } 935 } 936 937 return status; 938 } 939 940 /** 941 * i40e_nvmupd_validate_command - Validate given command 942 * @hw: pointer to hardware structure 943 * @cmd: pointer to nvm update command buffer 944 * @errno: pointer to return error code 945 * 946 * Return one of the valid command types or I40E_NVMUPD_INVALID 947 **/ 948 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 949 struct i40e_nvm_access *cmd, 950 int *errno) 951 { 952 enum i40e_nvmupd_cmd upd_cmd; 953 u8 transaction; 954 955 /* anything that doesn't match a recognized case is an error */ 956 upd_cmd = I40E_NVMUPD_INVALID; 957 958 transaction = i40e_nvmupd_get_transaction(cmd->config); 959 960 /* limits on data size */ 961 if ((cmd->data_size < 1) || 962 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) { 963 i40e_debug(hw, I40E_DEBUG_NVM, 964 "i40e_nvmupd_validate_command data_size %d\n", 965 cmd->data_size); 966 *errno = -EFAULT; 967 return I40E_NVMUPD_INVALID; 968 } 969 970 switch (cmd->command) { 971 case I40E_NVM_READ: 972 switch (transaction) { 973 case I40E_NVM_CON: 974 upd_cmd = I40E_NVMUPD_READ_CON; 975 break; 976 case I40E_NVM_SNT: 977 upd_cmd = I40E_NVMUPD_READ_SNT; 978 break; 979 case I40E_NVM_LCB: 980 upd_cmd = I40E_NVMUPD_READ_LCB; 981 break; 982 case I40E_NVM_SA: 983 upd_cmd = I40E_NVMUPD_READ_SA; 984 break; 985 } 986 break; 987 988 case I40E_NVM_WRITE: 989 switch (transaction) { 990 case I40E_NVM_CON: 991 upd_cmd = I40E_NVMUPD_WRITE_CON; 992 break; 993 case I40E_NVM_SNT: 994 upd_cmd = I40E_NVMUPD_WRITE_SNT; 995 break; 996 case I40E_NVM_LCB: 997 upd_cmd = I40E_NVMUPD_WRITE_LCB; 998 break; 999 case I40E_NVM_SA: 1000 upd_cmd = I40E_NVMUPD_WRITE_SA; 1001 break; 1002 case I40E_NVM_ERA: 1003 upd_cmd = I40E_NVMUPD_WRITE_ERA; 1004 break; 1005 case I40E_NVM_CSUM: 1006 upd_cmd = I40E_NVMUPD_CSUM_CON; 1007 break; 1008 case (I40E_NVM_CSUM|I40E_NVM_SA): 1009 upd_cmd = I40E_NVMUPD_CSUM_SA; 1010 break; 1011 case (I40E_NVM_CSUM|I40E_NVM_LCB): 1012 upd_cmd = I40E_NVMUPD_CSUM_LCB; 1013 break; 1014 } 1015 break; 1016 } 1017 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d\n", 1018 i40e_nvm_update_state_str[upd_cmd], 1019 hw->nvmupd_state, 1020 hw->aq.nvm_release_on_done); 1021 1022 if (upd_cmd == I40E_NVMUPD_INVALID) { 1023 *errno = -EFAULT; 1024 i40e_debug(hw, I40E_DEBUG_NVM, 1025 "i40e_nvmupd_validate_command returns %d errno %d\n", 1026 upd_cmd, *errno); 1027 } 1028 return upd_cmd; 1029 } 1030 1031 /** 1032 * i40e_nvmupd_nvm_read - Read NVM 1033 * @hw: pointer to hardware structure 1034 * @cmd: pointer to nvm update command buffer 1035 * @bytes: pointer to the data buffer 1036 * @errno: pointer to return error code 1037 * 1038 * cmd structure contains identifiers and data buffer 1039 **/ 1040 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, 1041 struct i40e_nvm_access *cmd, 1042 u8 *bytes, int *errno) 1043 { 1044 i40e_status status; 1045 u8 module, transaction; 1046 bool last; 1047 1048 transaction = i40e_nvmupd_get_transaction(cmd->config); 1049 module = i40e_nvmupd_get_module(cmd->config); 1050 last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA); 1051 1052 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1053 bytes, last, NULL); 1054 if (status) { 1055 i40e_debug(hw, I40E_DEBUG_NVM, 1056 "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n", 1057 module, cmd->offset, cmd->data_size); 1058 i40e_debug(hw, I40E_DEBUG_NVM, 1059 "i40e_nvmupd_nvm_read status %d aq %d\n", 1060 status, hw->aq.asq_last_status); 1061 *errno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1062 } 1063 1064 return status; 1065 } 1066 1067 /** 1068 * i40e_nvmupd_nvm_erase - Erase an NVM module 1069 * @hw: pointer to hardware structure 1070 * @cmd: pointer to nvm update command buffer 1071 * @errno: pointer to return error code 1072 * 1073 * module, offset, data_size and data are in cmd structure 1074 **/ 1075 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 1076 struct i40e_nvm_access *cmd, 1077 int *errno) 1078 { 1079 i40e_status status = 0; 1080 u8 module, transaction; 1081 bool last; 1082 1083 transaction = i40e_nvmupd_get_transaction(cmd->config); 1084 module = i40e_nvmupd_get_module(cmd->config); 1085 last = (transaction & I40E_NVM_LCB); 1086 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1087 last, NULL); 1088 if (status) { 1089 i40e_debug(hw, I40E_DEBUG_NVM, 1090 "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n", 1091 module, cmd->offset, cmd->data_size); 1092 i40e_debug(hw, I40E_DEBUG_NVM, 1093 "i40e_nvmupd_nvm_erase status %d aq %d\n", 1094 status, hw->aq.asq_last_status); 1095 *errno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1096 } 1097 1098 return status; 1099 } 1100 1101 /** 1102 * i40e_nvmupd_nvm_write - Write NVM 1103 * @hw: pointer to hardware structure 1104 * @cmd: pointer to nvm update command buffer 1105 * @bytes: pointer to the data buffer 1106 * @errno: pointer to return error code 1107 * 1108 * module, offset, data_size and data are in cmd structure 1109 **/ 1110 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, 1111 struct i40e_nvm_access *cmd, 1112 u8 *bytes, int *errno) 1113 { 1114 i40e_status status = 0; 1115 u8 module, transaction; 1116 bool last; 1117 1118 transaction = i40e_nvmupd_get_transaction(cmd->config); 1119 module = i40e_nvmupd_get_module(cmd->config); 1120 last = (transaction & I40E_NVM_LCB); 1121 1122 status = i40e_aq_update_nvm(hw, module, cmd->offset, 1123 (u16)cmd->data_size, bytes, last, NULL); 1124 if (status) { 1125 i40e_debug(hw, I40E_DEBUG_NVM, 1126 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n", 1127 module, cmd->offset, cmd->data_size); 1128 i40e_debug(hw, I40E_DEBUG_NVM, 1129 "i40e_nvmupd_nvm_write status %d aq %d\n", 1130 status, hw->aq.asq_last_status); 1131 *errno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1132 } 1133 1134 return status; 1135 } 1136