1 // SPDX-License-Identifier: GPL-2.0 2 /******************************************************************************* 3 * 4 * Intel Ethernet Controller XL710 Family Linux Driver 5 * Copyright(c) 2013 - 2014 Intel Corporation. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program. If not, see <http://www.gnu.org/licenses/>. 18 * 19 * The full GNU General Public License is included in this distribution in 20 * the file called "COPYING". 21 * 22 * Contact Information: 23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 * 26 ******************************************************************************/ 27 28 #include "i40e_prototype.h" 29 30 /** 31 * i40e_init_nvm_ops - Initialize NVM function pointers 32 * @hw: pointer to the HW structure 33 * 34 * Setup the function pointers and the NVM info structure. Should be called 35 * once per NVM initialization, e.g. inside the i40e_init_shared_code(). 36 * Please notice that the NVM term is used here (& in all methods covered 37 * in this file) as an equivalent of the FLASH part mapped into the SR. 38 * We are accessing FLASH always thru the Shadow RAM. 39 **/ 40 i40e_status i40e_init_nvm(struct i40e_hw *hw) 41 { 42 struct i40e_nvm_info *nvm = &hw->nvm; 43 i40e_status ret_code = 0; 44 u32 fla, gens; 45 u8 sr_size; 46 47 /* The SR size is stored regardless of the nvm programming mode 48 * as the blank mode may be used in the factory line. 49 */ 50 gens = rd32(hw, I40E_GLNVM_GENS); 51 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >> 52 I40E_GLNVM_GENS_SR_SIZE_SHIFT); 53 /* Switching to words (sr_size contains power of 2KB) */ 54 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; 55 56 /* Check if we are in the normal or blank NVM programming mode */ 57 fla = rd32(hw, I40E_GLNVM_FLA); 58 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */ 59 /* Max NVM timeout */ 60 nvm->timeout = I40E_MAX_NVM_TIMEOUT; 61 nvm->blank_nvm_mode = false; 62 } else { /* Blank programming mode */ 63 nvm->blank_nvm_mode = true; 64 ret_code = I40E_ERR_NVM_BLANK_MODE; 65 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n"); 66 } 67 68 return ret_code; 69 } 70 71 /** 72 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership 73 * @hw: pointer to the HW structure 74 * @access: NVM access type (read or write) 75 * 76 * This function will request NVM ownership for reading 77 * via the proper Admin Command. 78 **/ 79 i40e_status i40e_acquire_nvm(struct i40e_hw *hw, 80 enum i40e_aq_resource_access_type access) 81 { 82 i40e_status ret_code = 0; 83 u64 gtime, timeout; 84 u64 time_left = 0; 85 86 if (hw->nvm.blank_nvm_mode) 87 goto i40e_i40e_acquire_nvm_exit; 88 89 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access, 90 0, &time_left, NULL); 91 /* Reading the Global Device Timer */ 92 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 93 94 /* Store the timeout */ 95 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime; 96 97 if (ret_code) 98 i40e_debug(hw, I40E_DEBUG_NVM, 99 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n", 100 access, time_left, ret_code, hw->aq.asq_last_status); 101 102 if (ret_code && time_left) { 103 /* Poll until the current NVM owner timeouts */ 104 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime; 105 while ((gtime < timeout) && time_left) { 106 usleep_range(10000, 20000); 107 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 108 ret_code = i40e_aq_request_resource(hw, 109 I40E_NVM_RESOURCE_ID, 110 access, 0, &time_left, 111 NULL); 112 if (!ret_code) { 113 hw->nvm.hw_semaphore_timeout = 114 I40E_MS_TO_GTIME(time_left) + gtime; 115 break; 116 } 117 } 118 if (ret_code) { 119 hw->nvm.hw_semaphore_timeout = 0; 120 i40e_debug(hw, I40E_DEBUG_NVM, 121 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n", 122 time_left, ret_code, hw->aq.asq_last_status); 123 } 124 } 125 126 i40e_i40e_acquire_nvm_exit: 127 return ret_code; 128 } 129 130 /** 131 * i40e_release_nvm - Generic request for releasing the NVM ownership 132 * @hw: pointer to the HW structure 133 * 134 * This function will release NVM resource via the proper Admin Command. 135 **/ 136 void i40e_release_nvm(struct i40e_hw *hw) 137 { 138 i40e_status ret_code = I40E_SUCCESS; 139 u32 total_delay = 0; 140 141 if (hw->nvm.blank_nvm_mode) 142 return; 143 144 ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); 145 146 /* there are some rare cases when trying to release the resource 147 * results in an admin Q timeout, so handle them correctly 148 */ 149 while ((ret_code == I40E_ERR_ADMIN_QUEUE_TIMEOUT) && 150 (total_delay < hw->aq.asq_cmd_timeout)) { 151 usleep_range(1000, 2000); 152 ret_code = i40e_aq_release_resource(hw, 153 I40E_NVM_RESOURCE_ID, 154 0, NULL); 155 total_delay++; 156 } 157 } 158 159 /** 160 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit 161 * @hw: pointer to the HW structure 162 * 163 * Polls the SRCTL Shadow RAM register done bit. 164 **/ 165 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw) 166 { 167 i40e_status ret_code = I40E_ERR_TIMEOUT; 168 u32 srctl, wait_cnt; 169 170 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */ 171 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) { 172 srctl = rd32(hw, I40E_GLNVM_SRCTL); 173 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) { 174 ret_code = 0; 175 break; 176 } 177 udelay(5); 178 } 179 if (ret_code == I40E_ERR_TIMEOUT) 180 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set"); 181 return ret_code; 182 } 183 184 /** 185 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register 186 * @hw: pointer to the HW structure 187 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 188 * @data: word read from the Shadow RAM 189 * 190 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 191 **/ 192 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, 193 u16 *data) 194 { 195 i40e_status ret_code = I40E_ERR_TIMEOUT; 196 u32 sr_reg; 197 198 if (offset >= hw->nvm.sr_size) { 199 i40e_debug(hw, I40E_DEBUG_NVM, 200 "NVM read error: offset %d beyond Shadow RAM limit %d\n", 201 offset, hw->nvm.sr_size); 202 ret_code = I40E_ERR_PARAM; 203 goto read_nvm_exit; 204 } 205 206 /* Poll the done bit first */ 207 ret_code = i40e_poll_sr_srctl_done_bit(hw); 208 if (!ret_code) { 209 /* Write the address and start reading */ 210 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) | 211 BIT(I40E_GLNVM_SRCTL_START_SHIFT); 212 wr32(hw, I40E_GLNVM_SRCTL, sr_reg); 213 214 /* Poll I40E_GLNVM_SRCTL until the done bit is set */ 215 ret_code = i40e_poll_sr_srctl_done_bit(hw); 216 if (!ret_code) { 217 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); 218 *data = (u16)((sr_reg & 219 I40E_GLNVM_SRDATA_RDDATA_MASK) 220 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT); 221 } 222 } 223 if (ret_code) 224 i40e_debug(hw, I40E_DEBUG_NVM, 225 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n", 226 offset); 227 228 read_nvm_exit: 229 return ret_code; 230 } 231 232 /** 233 * i40e_read_nvm_aq - Read Shadow RAM. 234 * @hw: pointer to the HW structure. 235 * @module_pointer: module pointer location in words from the NVM beginning 236 * @offset: offset in words from module start 237 * @words: number of words to write 238 * @data: buffer with words to write to the Shadow RAM 239 * @last_command: tells the AdminQ that this is the last command 240 * 241 * Writes a 16 bit words buffer to the Shadow RAM using the admin command. 242 **/ 243 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, 244 u8 module_pointer, u32 offset, 245 u16 words, void *data, 246 bool last_command) 247 { 248 i40e_status ret_code = I40E_ERR_NVM; 249 struct i40e_asq_cmd_details cmd_details; 250 251 memset(&cmd_details, 0, sizeof(cmd_details)); 252 cmd_details.wb_desc = &hw->nvm_wb_desc; 253 254 /* Here we are checking the SR limit only for the flat memory model. 255 * We cannot do it for the module-based model, as we did not acquire 256 * the NVM resource yet (we cannot get the module pointer value). 257 * Firmware will check the module-based model. 258 */ 259 if ((offset + words) > hw->nvm.sr_size) 260 i40e_debug(hw, I40E_DEBUG_NVM, 261 "NVM write error: offset %d beyond Shadow RAM limit %d\n", 262 (offset + words), hw->nvm.sr_size); 263 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) 264 /* We can write only up to 4KB (one sector), in one AQ write */ 265 i40e_debug(hw, I40E_DEBUG_NVM, 266 "NVM write fail error: tried to write %d words, limit is %d.\n", 267 words, I40E_SR_SECTOR_SIZE_IN_WORDS); 268 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) 269 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) 270 /* A single write cannot spread over two sectors */ 271 i40e_debug(hw, I40E_DEBUG_NVM, 272 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", 273 offset, words); 274 else 275 ret_code = i40e_aq_read_nvm(hw, module_pointer, 276 2 * offset, /*bytes*/ 277 2 * words, /*bytes*/ 278 data, last_command, &cmd_details); 279 280 return ret_code; 281 } 282 283 /** 284 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ 285 * @hw: pointer to the HW structure 286 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 287 * @data: word read from the Shadow RAM 288 * 289 * Reads one 16 bit word from the Shadow RAM using the AdminQ 290 **/ 291 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset, 292 u16 *data) 293 { 294 i40e_status ret_code = I40E_ERR_TIMEOUT; 295 296 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true); 297 *data = le16_to_cpu(*(__le16 *)data); 298 299 return ret_code; 300 } 301 302 /** 303 * __i40e_read_nvm_word - Reads nvm word, assumes caller does the locking 304 * @hw: pointer to the HW structure 305 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 306 * @data: word read from the Shadow RAM 307 * 308 * Reads one 16 bit word from the Shadow RAM. 309 * 310 * Do not use this function except in cases where the nvm lock is already 311 * taken via i40e_acquire_nvm(). 312 **/ 313 static i40e_status __i40e_read_nvm_word(struct i40e_hw *hw, 314 u16 offset, u16 *data) 315 { 316 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) 317 return i40e_read_nvm_word_aq(hw, offset, data); 318 319 return i40e_read_nvm_word_srctl(hw, offset, data); 320 } 321 322 /** 323 * i40e_read_nvm_word - Reads nvm word and acquire lock if necessary 324 * @hw: pointer to the HW structure 325 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 326 * @data: word read from the Shadow RAM 327 * 328 * Reads one 16 bit word from the Shadow RAM. 329 **/ 330 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, 331 u16 *data) 332 { 333 i40e_status ret_code = 0; 334 335 if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK) 336 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 337 if (ret_code) 338 return ret_code; 339 340 ret_code = __i40e_read_nvm_word(hw, offset, data); 341 342 if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK) 343 i40e_release_nvm(hw); 344 345 return ret_code; 346 } 347 348 /** 349 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register 350 * @hw: pointer to the HW structure 351 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 352 * @words: (in) number of words to read; (out) number of words actually read 353 * @data: words read from the Shadow RAM 354 * 355 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 356 * method. The buffer read is preceded by the NVM ownership take 357 * and followed by the release. 358 **/ 359 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset, 360 u16 *words, u16 *data) 361 { 362 i40e_status ret_code = 0; 363 u16 index, word; 364 365 /* Loop thru the selected region */ 366 for (word = 0; word < *words; word++) { 367 index = offset + word; 368 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]); 369 if (ret_code) 370 break; 371 } 372 373 /* Update the number of words read from the Shadow RAM */ 374 *words = word; 375 376 return ret_code; 377 } 378 379 /** 380 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ 381 * @hw: pointer to the HW structure 382 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 383 * @words: (in) number of words to read; (out) number of words actually read 384 * @data: words read from the Shadow RAM 385 * 386 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq() 387 * method. The buffer read is preceded by the NVM ownership take 388 * and followed by the release. 389 **/ 390 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset, 391 u16 *words, u16 *data) 392 { 393 i40e_status ret_code; 394 u16 read_size; 395 bool last_cmd = false; 396 u16 words_read = 0; 397 u16 i = 0; 398 399 do { 400 /* Calculate number of bytes we should read in this step. 401 * FVL AQ do not allow to read more than one page at a time or 402 * to cross page boundaries. 403 */ 404 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS) 405 read_size = min(*words, 406 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS - 407 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS))); 408 else 409 read_size = min((*words - words_read), 410 I40E_SR_SECTOR_SIZE_IN_WORDS); 411 412 /* Check if this is last command, if so set proper flag */ 413 if ((words_read + read_size) >= *words) 414 last_cmd = true; 415 416 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size, 417 data + words_read, last_cmd); 418 if (ret_code) 419 goto read_nvm_buffer_aq_exit; 420 421 /* Increment counter for words already read and move offset to 422 * new read location 423 */ 424 words_read += read_size; 425 offset += read_size; 426 } while (words_read < *words); 427 428 for (i = 0; i < *words; i++) 429 data[i] = le16_to_cpu(((__le16 *)data)[i]); 430 431 read_nvm_buffer_aq_exit: 432 *words = words_read; 433 return ret_code; 434 } 435 436 /** 437 * __i40e_read_nvm_buffer - Reads nvm buffer, caller must acquire lock 438 * @hw: pointer to the HW structure 439 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 440 * @words: (in) number of words to read; (out) number of words actually read 441 * @data: words read from the Shadow RAM 442 * 443 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 444 * method. 445 **/ 446 static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw, 447 u16 offset, u16 *words, 448 u16 *data) 449 { 450 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) 451 return i40e_read_nvm_buffer_aq(hw, offset, words, data); 452 453 return i40e_read_nvm_buffer_srctl(hw, offset, words, data); 454 } 455 456 /** 457 * i40e_write_nvm_aq - Writes Shadow RAM. 458 * @hw: pointer to the HW structure. 459 * @module_pointer: module pointer location in words from the NVM beginning 460 * @offset: offset in words from module start 461 * @words: number of words to write 462 * @data: buffer with words to write to the Shadow RAM 463 * @last_command: tells the AdminQ that this is the last command 464 * 465 * Writes a 16 bit words buffer to the Shadow RAM using the admin command. 466 **/ 467 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer, 468 u32 offset, u16 words, void *data, 469 bool last_command) 470 { 471 i40e_status ret_code = I40E_ERR_NVM; 472 struct i40e_asq_cmd_details cmd_details; 473 474 memset(&cmd_details, 0, sizeof(cmd_details)); 475 cmd_details.wb_desc = &hw->nvm_wb_desc; 476 477 /* Here we are checking the SR limit only for the flat memory model. 478 * We cannot do it for the module-based model, as we did not acquire 479 * the NVM resource yet (we cannot get the module pointer value). 480 * Firmware will check the module-based model. 481 */ 482 if ((offset + words) > hw->nvm.sr_size) 483 i40e_debug(hw, I40E_DEBUG_NVM, 484 "NVM write error: offset %d beyond Shadow RAM limit %d\n", 485 (offset + words), hw->nvm.sr_size); 486 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) 487 /* We can write only up to 4KB (one sector), in one AQ write */ 488 i40e_debug(hw, I40E_DEBUG_NVM, 489 "NVM write fail error: tried to write %d words, limit is %d.\n", 490 words, I40E_SR_SECTOR_SIZE_IN_WORDS); 491 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) 492 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) 493 /* A single write cannot spread over two sectors */ 494 i40e_debug(hw, I40E_DEBUG_NVM, 495 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", 496 offset, words); 497 else 498 ret_code = i40e_aq_update_nvm(hw, module_pointer, 499 2 * offset, /*bytes*/ 500 2 * words, /*bytes*/ 501 data, last_command, 0, 502 &cmd_details); 503 504 return ret_code; 505 } 506 507 /** 508 * i40e_calc_nvm_checksum - Calculates and returns the checksum 509 * @hw: pointer to hardware structure 510 * @checksum: pointer to the checksum 511 * 512 * This function calculates SW Checksum that covers the whole 64kB shadow RAM 513 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD 514 * is customer specific and unknown. Therefore, this function skips all maximum 515 * possible size of VPD (1kB). 516 **/ 517 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw, 518 u16 *checksum) 519 { 520 i40e_status ret_code; 521 struct i40e_virt_mem vmem; 522 u16 pcie_alt_module = 0; 523 u16 checksum_local = 0; 524 u16 vpd_module = 0; 525 u16 *data; 526 u16 i = 0; 527 528 ret_code = i40e_allocate_virt_mem(hw, &vmem, 529 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16)); 530 if (ret_code) 531 goto i40e_calc_nvm_checksum_exit; 532 data = (u16 *)vmem.va; 533 534 /* read pointer to VPD area */ 535 ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module); 536 if (ret_code) { 537 ret_code = I40E_ERR_NVM_CHECKSUM; 538 goto i40e_calc_nvm_checksum_exit; 539 } 540 541 /* read pointer to PCIe Alt Auto-load module */ 542 ret_code = __i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR, 543 &pcie_alt_module); 544 if (ret_code) { 545 ret_code = I40E_ERR_NVM_CHECKSUM; 546 goto i40e_calc_nvm_checksum_exit; 547 } 548 549 /* Calculate SW checksum that covers the whole 64kB shadow RAM 550 * except the VPD and PCIe ALT Auto-load modules 551 */ 552 for (i = 0; i < hw->nvm.sr_size; i++) { 553 /* Read SR page */ 554 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) { 555 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS; 556 557 ret_code = __i40e_read_nvm_buffer(hw, i, &words, data); 558 if (ret_code) { 559 ret_code = I40E_ERR_NVM_CHECKSUM; 560 goto i40e_calc_nvm_checksum_exit; 561 } 562 } 563 564 /* Skip Checksum word */ 565 if (i == I40E_SR_SW_CHECKSUM_WORD) 566 continue; 567 /* Skip VPD module (convert byte size to word count) */ 568 if ((i >= (u32)vpd_module) && 569 (i < ((u32)vpd_module + 570 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) { 571 continue; 572 } 573 /* Skip PCIe ALT module (convert byte size to word count) */ 574 if ((i >= (u32)pcie_alt_module) && 575 (i < ((u32)pcie_alt_module + 576 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) { 577 continue; 578 } 579 580 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS]; 581 } 582 583 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local; 584 585 i40e_calc_nvm_checksum_exit: 586 i40e_free_virt_mem(hw, &vmem); 587 return ret_code; 588 } 589 590 /** 591 * i40e_update_nvm_checksum - Updates the NVM checksum 592 * @hw: pointer to hardware structure 593 * 594 * NVM ownership must be acquired before calling this function and released 595 * on ARQ completion event reception by caller. 596 * This function will commit SR to NVM. 597 **/ 598 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw) 599 { 600 i40e_status ret_code; 601 u16 checksum; 602 __le16 le_sum; 603 604 ret_code = i40e_calc_nvm_checksum(hw, &checksum); 605 if (!ret_code) { 606 le_sum = cpu_to_le16(checksum); 607 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD, 608 1, &le_sum, true); 609 } 610 611 return ret_code; 612 } 613 614 /** 615 * i40e_validate_nvm_checksum - Validate EEPROM checksum 616 * @hw: pointer to hardware structure 617 * @checksum: calculated checksum 618 * 619 * Performs checksum calculation and validates the NVM SW checksum. If the 620 * caller does not need checksum, the value can be NULL. 621 **/ 622 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw, 623 u16 *checksum) 624 { 625 i40e_status ret_code = 0; 626 u16 checksum_sr = 0; 627 u16 checksum_local = 0; 628 629 /* We must acquire the NVM lock in order to correctly synchronize the 630 * NVM accesses across multiple PFs. Without doing so it is possible 631 * for one of the PFs to read invalid data potentially indicating that 632 * the checksum is invalid. 633 */ 634 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 635 if (ret_code) 636 return ret_code; 637 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local); 638 __i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr); 639 i40e_release_nvm(hw); 640 if (ret_code) 641 return ret_code; 642 643 /* Verify read checksum from EEPROM is the same as 644 * calculated checksum 645 */ 646 if (checksum_local != checksum_sr) 647 ret_code = I40E_ERR_NVM_CHECKSUM; 648 649 /* If the user cares, return the calculated checksum */ 650 if (checksum) 651 *checksum = checksum_local; 652 653 return ret_code; 654 } 655 656 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, 657 struct i40e_nvm_access *cmd, 658 u8 *bytes, int *perrno); 659 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, 660 struct i40e_nvm_access *cmd, 661 u8 *bytes, int *perrno); 662 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, 663 struct i40e_nvm_access *cmd, 664 u8 *bytes, int *errno); 665 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 666 struct i40e_nvm_access *cmd, 667 int *perrno); 668 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 669 struct i40e_nvm_access *cmd, 670 int *perrno); 671 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, 672 struct i40e_nvm_access *cmd, 673 u8 *bytes, int *perrno); 674 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, 675 struct i40e_nvm_access *cmd, 676 u8 *bytes, int *perrno); 677 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw, 678 struct i40e_nvm_access *cmd, 679 u8 *bytes, int *perrno); 680 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw, 681 struct i40e_nvm_access *cmd, 682 u8 *bytes, int *perrno); 683 static i40e_status i40e_nvmupd_get_aq_event(struct i40e_hw *hw, 684 struct i40e_nvm_access *cmd, 685 u8 *bytes, int *perrno); 686 static inline u8 i40e_nvmupd_get_module(u32 val) 687 { 688 return (u8)(val & I40E_NVM_MOD_PNT_MASK); 689 } 690 static inline u8 i40e_nvmupd_get_transaction(u32 val) 691 { 692 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT); 693 } 694 695 static inline u8 i40e_nvmupd_get_preservation_flags(u32 val) 696 { 697 return (u8)((val & I40E_NVM_PRESERVATION_FLAGS_MASK) >> 698 I40E_NVM_PRESERVATION_FLAGS_SHIFT); 699 } 700 701 static const char * const i40e_nvm_update_state_str[] = { 702 "I40E_NVMUPD_INVALID", 703 "I40E_NVMUPD_READ_CON", 704 "I40E_NVMUPD_READ_SNT", 705 "I40E_NVMUPD_READ_LCB", 706 "I40E_NVMUPD_READ_SA", 707 "I40E_NVMUPD_WRITE_ERA", 708 "I40E_NVMUPD_WRITE_CON", 709 "I40E_NVMUPD_WRITE_SNT", 710 "I40E_NVMUPD_WRITE_LCB", 711 "I40E_NVMUPD_WRITE_SA", 712 "I40E_NVMUPD_CSUM_CON", 713 "I40E_NVMUPD_CSUM_SA", 714 "I40E_NVMUPD_CSUM_LCB", 715 "I40E_NVMUPD_STATUS", 716 "I40E_NVMUPD_EXEC_AQ", 717 "I40E_NVMUPD_GET_AQ_RESULT", 718 "I40E_NVMUPD_GET_AQ_EVENT", 719 }; 720 721 /** 722 * i40e_nvmupd_command - Process an NVM update command 723 * @hw: pointer to hardware structure 724 * @cmd: pointer to nvm update command 725 * @bytes: pointer to the data buffer 726 * @perrno: pointer to return error code 727 * 728 * Dispatches command depending on what update state is current 729 **/ 730 i40e_status i40e_nvmupd_command(struct i40e_hw *hw, 731 struct i40e_nvm_access *cmd, 732 u8 *bytes, int *perrno) 733 { 734 i40e_status status; 735 enum i40e_nvmupd_cmd upd_cmd; 736 737 /* assume success */ 738 *perrno = 0; 739 740 /* early check for status command and debug msgs */ 741 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 742 743 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n", 744 i40e_nvm_update_state_str[upd_cmd], 745 hw->nvmupd_state, 746 hw->nvm_release_on_done, hw->nvm_wait_opcode, 747 cmd->command, cmd->config, cmd->offset, cmd->data_size); 748 749 if (upd_cmd == I40E_NVMUPD_INVALID) { 750 *perrno = -EFAULT; 751 i40e_debug(hw, I40E_DEBUG_NVM, 752 "i40e_nvmupd_validate_command returns %d errno %d\n", 753 upd_cmd, *perrno); 754 } 755 756 /* a status request returns immediately rather than 757 * going into the state machine 758 */ 759 if (upd_cmd == I40E_NVMUPD_STATUS) { 760 if (!cmd->data_size) { 761 *perrno = -EFAULT; 762 return I40E_ERR_BUF_TOO_SHORT; 763 } 764 765 bytes[0] = hw->nvmupd_state; 766 767 if (cmd->data_size >= 4) { 768 bytes[1] = 0; 769 *((u16 *)&bytes[2]) = hw->nvm_wait_opcode; 770 } 771 772 /* Clear error status on read */ 773 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) 774 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 775 776 return 0; 777 } 778 779 /* Clear status even it is not read and log */ 780 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) { 781 i40e_debug(hw, I40E_DEBUG_NVM, 782 "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n"); 783 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 784 } 785 786 /* Acquire lock to prevent race condition where adminq_task 787 * can execute after i40e_nvmupd_nvm_read/write but before state 788 * variables (nvm_wait_opcode, nvm_release_on_done) are updated. 789 * 790 * During NVMUpdate, it is observed that lock could be held for 791 * ~5ms for most commands. However lock is held for ~60ms for 792 * NVMUPD_CSUM_LCB command. 793 */ 794 mutex_lock(&hw->aq.arq_mutex); 795 switch (hw->nvmupd_state) { 796 case I40E_NVMUPD_STATE_INIT: 797 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); 798 break; 799 800 case I40E_NVMUPD_STATE_READING: 801 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); 802 break; 803 804 case I40E_NVMUPD_STATE_WRITING: 805 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); 806 break; 807 808 case I40E_NVMUPD_STATE_INIT_WAIT: 809 case I40E_NVMUPD_STATE_WRITE_WAIT: 810 /* if we need to stop waiting for an event, clear 811 * the wait info and return before doing anything else 812 */ 813 if (cmd->offset == 0xffff) { 814 i40e_nvmupd_clear_wait_state(hw); 815 status = 0; 816 break; 817 } 818 819 status = I40E_ERR_NOT_READY; 820 *perrno = -EBUSY; 821 break; 822 823 default: 824 /* invalid state, should never happen */ 825 i40e_debug(hw, I40E_DEBUG_NVM, 826 "NVMUPD: no such state %d\n", hw->nvmupd_state); 827 status = I40E_NOT_SUPPORTED; 828 *perrno = -ESRCH; 829 break; 830 } 831 832 mutex_unlock(&hw->aq.arq_mutex); 833 return status; 834 } 835 836 /** 837 * i40e_nvmupd_state_init - Handle NVM update state Init 838 * @hw: pointer to hardware structure 839 * @cmd: pointer to nvm update command buffer 840 * @bytes: pointer to the data buffer 841 * @perrno: pointer to return error code 842 * 843 * Process legitimate commands of the Init state and conditionally set next 844 * state. Reject all other commands. 845 **/ 846 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, 847 struct i40e_nvm_access *cmd, 848 u8 *bytes, int *perrno) 849 { 850 i40e_status status = 0; 851 enum i40e_nvmupd_cmd upd_cmd; 852 853 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 854 855 switch (upd_cmd) { 856 case I40E_NVMUPD_READ_SA: 857 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 858 if (status) { 859 *perrno = i40e_aq_rc_to_posix(status, 860 hw->aq.asq_last_status); 861 } else { 862 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 863 i40e_release_nvm(hw); 864 } 865 break; 866 867 case I40E_NVMUPD_READ_SNT: 868 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 869 if (status) { 870 *perrno = i40e_aq_rc_to_posix(status, 871 hw->aq.asq_last_status); 872 } else { 873 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 874 if (status) 875 i40e_release_nvm(hw); 876 else 877 hw->nvmupd_state = I40E_NVMUPD_STATE_READING; 878 } 879 break; 880 881 case I40E_NVMUPD_WRITE_ERA: 882 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 883 if (status) { 884 *perrno = i40e_aq_rc_to_posix(status, 885 hw->aq.asq_last_status); 886 } else { 887 status = i40e_nvmupd_nvm_erase(hw, cmd, perrno); 888 if (status) { 889 i40e_release_nvm(hw); 890 } else { 891 hw->nvm_release_on_done = true; 892 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase; 893 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 894 } 895 } 896 break; 897 898 case I40E_NVMUPD_WRITE_SA: 899 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 900 if (status) { 901 *perrno = i40e_aq_rc_to_posix(status, 902 hw->aq.asq_last_status); 903 } else { 904 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 905 if (status) { 906 i40e_release_nvm(hw); 907 } else { 908 hw->nvm_release_on_done = true; 909 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 910 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 911 } 912 } 913 break; 914 915 case I40E_NVMUPD_WRITE_SNT: 916 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 917 if (status) { 918 *perrno = i40e_aq_rc_to_posix(status, 919 hw->aq.asq_last_status); 920 } else { 921 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 922 if (status) { 923 i40e_release_nvm(hw); 924 } else { 925 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 926 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 927 } 928 } 929 break; 930 931 case I40E_NVMUPD_CSUM_SA: 932 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 933 if (status) { 934 *perrno = i40e_aq_rc_to_posix(status, 935 hw->aq.asq_last_status); 936 } else { 937 status = i40e_update_nvm_checksum(hw); 938 if (status) { 939 *perrno = hw->aq.asq_last_status ? 940 i40e_aq_rc_to_posix(status, 941 hw->aq.asq_last_status) : 942 -EIO; 943 i40e_release_nvm(hw); 944 } else { 945 hw->nvm_release_on_done = true; 946 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 947 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 948 } 949 } 950 break; 951 952 case I40E_NVMUPD_EXEC_AQ: 953 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); 954 break; 955 956 case I40E_NVMUPD_GET_AQ_RESULT: 957 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno); 958 break; 959 960 case I40E_NVMUPD_GET_AQ_EVENT: 961 status = i40e_nvmupd_get_aq_event(hw, cmd, bytes, perrno); 962 break; 963 964 default: 965 i40e_debug(hw, I40E_DEBUG_NVM, 966 "NVMUPD: bad cmd %s in init state\n", 967 i40e_nvm_update_state_str[upd_cmd]); 968 status = I40E_ERR_NVM; 969 *perrno = -ESRCH; 970 break; 971 } 972 return status; 973 } 974 975 /** 976 * i40e_nvmupd_state_reading - Handle NVM update state Reading 977 * @hw: pointer to hardware structure 978 * @cmd: pointer to nvm update command buffer 979 * @bytes: pointer to the data buffer 980 * @perrno: pointer to return error code 981 * 982 * NVM ownership is already held. Process legitimate commands and set any 983 * change in state; reject all other commands. 984 **/ 985 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, 986 struct i40e_nvm_access *cmd, 987 u8 *bytes, int *perrno) 988 { 989 i40e_status status = 0; 990 enum i40e_nvmupd_cmd upd_cmd; 991 992 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 993 994 switch (upd_cmd) { 995 case I40E_NVMUPD_READ_SA: 996 case I40E_NVMUPD_READ_CON: 997 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 998 break; 999 1000 case I40E_NVMUPD_READ_LCB: 1001 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 1002 i40e_release_nvm(hw); 1003 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1004 break; 1005 1006 default: 1007 i40e_debug(hw, I40E_DEBUG_NVM, 1008 "NVMUPD: bad cmd %s in reading state.\n", 1009 i40e_nvm_update_state_str[upd_cmd]); 1010 status = I40E_NOT_SUPPORTED; 1011 *perrno = -ESRCH; 1012 break; 1013 } 1014 return status; 1015 } 1016 1017 /** 1018 * i40e_nvmupd_state_writing - Handle NVM update state Writing 1019 * @hw: pointer to hardware structure 1020 * @cmd: pointer to nvm update command buffer 1021 * @bytes: pointer to the data buffer 1022 * @perrno: pointer to return error code 1023 * 1024 * NVM ownership is already held. Process legitimate commands and set any 1025 * change in state; reject all other commands 1026 **/ 1027 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, 1028 struct i40e_nvm_access *cmd, 1029 u8 *bytes, int *perrno) 1030 { 1031 i40e_status status = 0; 1032 enum i40e_nvmupd_cmd upd_cmd; 1033 bool retry_attempt = false; 1034 1035 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 1036 1037 retry: 1038 switch (upd_cmd) { 1039 case I40E_NVMUPD_WRITE_CON: 1040 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 1041 if (!status) { 1042 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1043 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 1044 } 1045 break; 1046 1047 case I40E_NVMUPD_WRITE_LCB: 1048 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 1049 if (status) { 1050 *perrno = hw->aq.asq_last_status ? 1051 i40e_aq_rc_to_posix(status, 1052 hw->aq.asq_last_status) : 1053 -EIO; 1054 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1055 } else { 1056 hw->nvm_release_on_done = true; 1057 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1058 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1059 } 1060 break; 1061 1062 case I40E_NVMUPD_CSUM_CON: 1063 /* Assumes the caller has acquired the nvm */ 1064 status = i40e_update_nvm_checksum(hw); 1065 if (status) { 1066 *perrno = hw->aq.asq_last_status ? 1067 i40e_aq_rc_to_posix(status, 1068 hw->aq.asq_last_status) : 1069 -EIO; 1070 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1071 } else { 1072 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1073 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 1074 } 1075 break; 1076 1077 case I40E_NVMUPD_CSUM_LCB: 1078 /* Assumes the caller has acquired the nvm */ 1079 status = i40e_update_nvm_checksum(hw); 1080 if (status) { 1081 *perrno = hw->aq.asq_last_status ? 1082 i40e_aq_rc_to_posix(status, 1083 hw->aq.asq_last_status) : 1084 -EIO; 1085 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1086 } else { 1087 hw->nvm_release_on_done = true; 1088 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1089 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1090 } 1091 break; 1092 1093 default: 1094 i40e_debug(hw, I40E_DEBUG_NVM, 1095 "NVMUPD: bad cmd %s in writing state.\n", 1096 i40e_nvm_update_state_str[upd_cmd]); 1097 status = I40E_NOT_SUPPORTED; 1098 *perrno = -ESRCH; 1099 break; 1100 } 1101 1102 /* In some circumstances, a multi-write transaction takes longer 1103 * than the default 3 minute timeout on the write semaphore. If 1104 * the write failed with an EBUSY status, this is likely the problem, 1105 * so here we try to reacquire the semaphore then retry the write. 1106 * We only do one retry, then give up. 1107 */ 1108 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) && 1109 !retry_attempt) { 1110 i40e_status old_status = status; 1111 u32 old_asq_status = hw->aq.asq_last_status; 1112 u32 gtime; 1113 1114 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 1115 if (gtime >= hw->nvm.hw_semaphore_timeout) { 1116 i40e_debug(hw, I40E_DEBUG_ALL, 1117 "NVMUPD: write semaphore expired (%d >= %lld), retrying\n", 1118 gtime, hw->nvm.hw_semaphore_timeout); 1119 i40e_release_nvm(hw); 1120 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 1121 if (status) { 1122 i40e_debug(hw, I40E_DEBUG_ALL, 1123 "NVMUPD: write semaphore reacquire failed aq_err = %d\n", 1124 hw->aq.asq_last_status); 1125 status = old_status; 1126 hw->aq.asq_last_status = old_asq_status; 1127 } else { 1128 retry_attempt = true; 1129 goto retry; 1130 } 1131 } 1132 } 1133 1134 return status; 1135 } 1136 1137 /** 1138 * i40e_nvmupd_clear_wait_state - clear wait state on hw 1139 * @hw: pointer to the hardware structure 1140 **/ 1141 void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw) 1142 { 1143 i40e_debug(hw, I40E_DEBUG_NVM, 1144 "NVMUPD: clearing wait on opcode 0x%04x\n", 1145 hw->nvm_wait_opcode); 1146 1147 if (hw->nvm_release_on_done) { 1148 i40e_release_nvm(hw); 1149 hw->nvm_release_on_done = false; 1150 } 1151 hw->nvm_wait_opcode = 0; 1152 1153 if (hw->aq.arq_last_status) { 1154 hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR; 1155 return; 1156 } 1157 1158 switch (hw->nvmupd_state) { 1159 case I40E_NVMUPD_STATE_INIT_WAIT: 1160 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1161 break; 1162 1163 case I40E_NVMUPD_STATE_WRITE_WAIT: 1164 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; 1165 break; 1166 1167 default: 1168 break; 1169 } 1170 } 1171 1172 /** 1173 * i40e_nvmupd_check_wait_event - handle NVM update operation events 1174 * @hw: pointer to the hardware structure 1175 * @opcode: the event that just happened 1176 **/ 1177 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode, 1178 struct i40e_aq_desc *desc) 1179 { 1180 u32 aq_desc_len = sizeof(struct i40e_aq_desc); 1181 1182 if (opcode == hw->nvm_wait_opcode) { 1183 memcpy(&hw->nvm_aq_event_desc, desc, aq_desc_len); 1184 i40e_nvmupd_clear_wait_state(hw); 1185 } 1186 } 1187 1188 /** 1189 * i40e_nvmupd_validate_command - Validate given command 1190 * @hw: pointer to hardware structure 1191 * @cmd: pointer to nvm update command buffer 1192 * @perrno: pointer to return error code 1193 * 1194 * Return one of the valid command types or I40E_NVMUPD_INVALID 1195 **/ 1196 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 1197 struct i40e_nvm_access *cmd, 1198 int *perrno) 1199 { 1200 enum i40e_nvmupd_cmd upd_cmd; 1201 u8 module, transaction; 1202 1203 /* anything that doesn't match a recognized case is an error */ 1204 upd_cmd = I40E_NVMUPD_INVALID; 1205 1206 transaction = i40e_nvmupd_get_transaction(cmd->config); 1207 module = i40e_nvmupd_get_module(cmd->config); 1208 1209 /* limits on data size */ 1210 if ((cmd->data_size < 1) || 1211 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) { 1212 i40e_debug(hw, I40E_DEBUG_NVM, 1213 "i40e_nvmupd_validate_command data_size %d\n", 1214 cmd->data_size); 1215 *perrno = -EFAULT; 1216 return I40E_NVMUPD_INVALID; 1217 } 1218 1219 switch (cmd->command) { 1220 case I40E_NVM_READ: 1221 switch (transaction) { 1222 case I40E_NVM_CON: 1223 upd_cmd = I40E_NVMUPD_READ_CON; 1224 break; 1225 case I40E_NVM_SNT: 1226 upd_cmd = I40E_NVMUPD_READ_SNT; 1227 break; 1228 case I40E_NVM_LCB: 1229 upd_cmd = I40E_NVMUPD_READ_LCB; 1230 break; 1231 case I40E_NVM_SA: 1232 upd_cmd = I40E_NVMUPD_READ_SA; 1233 break; 1234 case I40E_NVM_EXEC: 1235 if (module == 0xf) 1236 upd_cmd = I40E_NVMUPD_STATUS; 1237 else if (module == 0) 1238 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT; 1239 break; 1240 case I40E_NVM_AQE: 1241 upd_cmd = I40E_NVMUPD_GET_AQ_EVENT; 1242 break; 1243 } 1244 break; 1245 1246 case I40E_NVM_WRITE: 1247 switch (transaction) { 1248 case I40E_NVM_CON: 1249 upd_cmd = I40E_NVMUPD_WRITE_CON; 1250 break; 1251 case I40E_NVM_SNT: 1252 upd_cmd = I40E_NVMUPD_WRITE_SNT; 1253 break; 1254 case I40E_NVM_LCB: 1255 upd_cmd = I40E_NVMUPD_WRITE_LCB; 1256 break; 1257 case I40E_NVM_SA: 1258 upd_cmd = I40E_NVMUPD_WRITE_SA; 1259 break; 1260 case I40E_NVM_ERA: 1261 upd_cmd = I40E_NVMUPD_WRITE_ERA; 1262 break; 1263 case I40E_NVM_CSUM: 1264 upd_cmd = I40E_NVMUPD_CSUM_CON; 1265 break; 1266 case (I40E_NVM_CSUM|I40E_NVM_SA): 1267 upd_cmd = I40E_NVMUPD_CSUM_SA; 1268 break; 1269 case (I40E_NVM_CSUM|I40E_NVM_LCB): 1270 upd_cmd = I40E_NVMUPD_CSUM_LCB; 1271 break; 1272 case I40E_NVM_EXEC: 1273 if (module == 0) 1274 upd_cmd = I40E_NVMUPD_EXEC_AQ; 1275 break; 1276 } 1277 break; 1278 } 1279 1280 return upd_cmd; 1281 } 1282 1283 /** 1284 * i40e_nvmupd_exec_aq - Run an AQ command 1285 * @hw: pointer to hardware structure 1286 * @cmd: pointer to nvm update command buffer 1287 * @bytes: pointer to the data buffer 1288 * @perrno: pointer to return error code 1289 * 1290 * cmd structure contains identifiers and data buffer 1291 **/ 1292 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw, 1293 struct i40e_nvm_access *cmd, 1294 u8 *bytes, int *perrno) 1295 { 1296 struct i40e_asq_cmd_details cmd_details; 1297 i40e_status status; 1298 struct i40e_aq_desc *aq_desc; 1299 u32 buff_size = 0; 1300 u8 *buff = NULL; 1301 u32 aq_desc_len; 1302 u32 aq_data_len; 1303 1304 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1305 if (cmd->offset == 0xffff) 1306 return 0; 1307 1308 memset(&cmd_details, 0, sizeof(cmd_details)); 1309 cmd_details.wb_desc = &hw->nvm_wb_desc; 1310 1311 aq_desc_len = sizeof(struct i40e_aq_desc); 1312 memset(&hw->nvm_wb_desc, 0, aq_desc_len); 1313 1314 /* get the aq descriptor */ 1315 if (cmd->data_size < aq_desc_len) { 1316 i40e_debug(hw, I40E_DEBUG_NVM, 1317 "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n", 1318 cmd->data_size, aq_desc_len); 1319 *perrno = -EINVAL; 1320 return I40E_ERR_PARAM; 1321 } 1322 aq_desc = (struct i40e_aq_desc *)bytes; 1323 1324 /* if data buffer needed, make sure it's ready */ 1325 aq_data_len = cmd->data_size - aq_desc_len; 1326 buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen)); 1327 if (buff_size) { 1328 if (!hw->nvm_buff.va) { 1329 status = i40e_allocate_virt_mem(hw, &hw->nvm_buff, 1330 hw->aq.asq_buf_size); 1331 if (status) 1332 i40e_debug(hw, I40E_DEBUG_NVM, 1333 "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n", 1334 status); 1335 } 1336 1337 if (hw->nvm_buff.va) { 1338 buff = hw->nvm_buff.va; 1339 memcpy(buff, &bytes[aq_desc_len], aq_data_len); 1340 } 1341 } 1342 1343 if (cmd->offset) 1344 memset(&hw->nvm_aq_event_desc, 0, aq_desc_len); 1345 1346 /* and away we go! */ 1347 status = i40e_asq_send_command(hw, aq_desc, buff, 1348 buff_size, &cmd_details); 1349 if (status) { 1350 i40e_debug(hw, I40E_DEBUG_NVM, 1351 "i40e_nvmupd_exec_aq err %s aq_err %s\n", 1352 i40e_stat_str(hw, status), 1353 i40e_aq_str(hw, hw->aq.asq_last_status)); 1354 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1355 return status; 1356 } 1357 1358 /* should we wait for a followup event? */ 1359 if (cmd->offset) { 1360 hw->nvm_wait_opcode = cmd->offset; 1361 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1362 } 1363 1364 return status; 1365 } 1366 1367 /** 1368 * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq 1369 * @hw: pointer to hardware structure 1370 * @cmd: pointer to nvm update command buffer 1371 * @bytes: pointer to the data buffer 1372 * @perrno: pointer to return error code 1373 * 1374 * cmd structure contains identifiers and data buffer 1375 **/ 1376 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw, 1377 struct i40e_nvm_access *cmd, 1378 u8 *bytes, int *perrno) 1379 { 1380 u32 aq_total_len; 1381 u32 aq_desc_len; 1382 int remainder; 1383 u8 *buff; 1384 1385 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1386 1387 aq_desc_len = sizeof(struct i40e_aq_desc); 1388 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen); 1389 1390 /* check offset range */ 1391 if (cmd->offset > aq_total_len) { 1392 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n", 1393 __func__, cmd->offset, aq_total_len); 1394 *perrno = -EINVAL; 1395 return I40E_ERR_PARAM; 1396 } 1397 1398 /* check copylength range */ 1399 if (cmd->data_size > (aq_total_len - cmd->offset)) { 1400 int new_len = aq_total_len - cmd->offset; 1401 1402 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n", 1403 __func__, cmd->data_size, new_len); 1404 cmd->data_size = new_len; 1405 } 1406 1407 remainder = cmd->data_size; 1408 if (cmd->offset < aq_desc_len) { 1409 u32 len = aq_desc_len - cmd->offset; 1410 1411 len = min(len, cmd->data_size); 1412 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n", 1413 __func__, cmd->offset, cmd->offset + len); 1414 1415 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset; 1416 memcpy(bytes, buff, len); 1417 1418 bytes += len; 1419 remainder -= len; 1420 buff = hw->nvm_buff.va; 1421 } else { 1422 buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len); 1423 } 1424 1425 if (remainder > 0) { 1426 int start_byte = buff - (u8 *)hw->nvm_buff.va; 1427 1428 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n", 1429 __func__, start_byte, start_byte + remainder); 1430 memcpy(bytes, buff, remainder); 1431 } 1432 1433 return 0; 1434 } 1435 1436 /** 1437 * i40e_nvmupd_get_aq_event - Get the Admin Queue event from previous exec_aq 1438 * @hw: pointer to hardware structure 1439 * @cmd: pointer to nvm update command buffer 1440 * @bytes: pointer to the data buffer 1441 * @perrno: pointer to return error code 1442 * 1443 * cmd structure contains identifiers and data buffer 1444 **/ 1445 static i40e_status i40e_nvmupd_get_aq_event(struct i40e_hw *hw, 1446 struct i40e_nvm_access *cmd, 1447 u8 *bytes, int *perrno) 1448 { 1449 u32 aq_total_len; 1450 u32 aq_desc_len; 1451 1452 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1453 1454 aq_desc_len = sizeof(struct i40e_aq_desc); 1455 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_aq_event_desc.datalen); 1456 1457 /* check copylength range */ 1458 if (cmd->data_size > aq_total_len) { 1459 i40e_debug(hw, I40E_DEBUG_NVM, 1460 "%s: copy length %d too big, trimming to %d\n", 1461 __func__, cmd->data_size, aq_total_len); 1462 cmd->data_size = aq_total_len; 1463 } 1464 1465 memcpy(bytes, &hw->nvm_aq_event_desc, cmd->data_size); 1466 1467 return 0; 1468 } 1469 1470 /** 1471 * i40e_nvmupd_nvm_read - Read NVM 1472 * @hw: pointer to hardware structure 1473 * @cmd: pointer to nvm update command buffer 1474 * @bytes: pointer to the data buffer 1475 * @perrno: pointer to return error code 1476 * 1477 * cmd structure contains identifiers and data buffer 1478 **/ 1479 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, 1480 struct i40e_nvm_access *cmd, 1481 u8 *bytes, int *perrno) 1482 { 1483 struct i40e_asq_cmd_details cmd_details; 1484 i40e_status status; 1485 u8 module, transaction; 1486 bool last; 1487 1488 transaction = i40e_nvmupd_get_transaction(cmd->config); 1489 module = i40e_nvmupd_get_module(cmd->config); 1490 last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA); 1491 1492 memset(&cmd_details, 0, sizeof(cmd_details)); 1493 cmd_details.wb_desc = &hw->nvm_wb_desc; 1494 1495 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1496 bytes, last, &cmd_details); 1497 if (status) { 1498 i40e_debug(hw, I40E_DEBUG_NVM, 1499 "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n", 1500 module, cmd->offset, cmd->data_size); 1501 i40e_debug(hw, I40E_DEBUG_NVM, 1502 "i40e_nvmupd_nvm_read status %d aq %d\n", 1503 status, hw->aq.asq_last_status); 1504 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1505 } 1506 1507 return status; 1508 } 1509 1510 /** 1511 * i40e_nvmupd_nvm_erase - Erase an NVM module 1512 * @hw: pointer to hardware structure 1513 * @cmd: pointer to nvm update command buffer 1514 * @perrno: pointer to return error code 1515 * 1516 * module, offset, data_size and data are in cmd structure 1517 **/ 1518 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 1519 struct i40e_nvm_access *cmd, 1520 int *perrno) 1521 { 1522 i40e_status status = 0; 1523 struct i40e_asq_cmd_details cmd_details; 1524 u8 module, transaction; 1525 bool last; 1526 1527 transaction = i40e_nvmupd_get_transaction(cmd->config); 1528 module = i40e_nvmupd_get_module(cmd->config); 1529 last = (transaction & I40E_NVM_LCB); 1530 1531 memset(&cmd_details, 0, sizeof(cmd_details)); 1532 cmd_details.wb_desc = &hw->nvm_wb_desc; 1533 1534 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1535 last, &cmd_details); 1536 if (status) { 1537 i40e_debug(hw, I40E_DEBUG_NVM, 1538 "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n", 1539 module, cmd->offset, cmd->data_size); 1540 i40e_debug(hw, I40E_DEBUG_NVM, 1541 "i40e_nvmupd_nvm_erase status %d aq %d\n", 1542 status, hw->aq.asq_last_status); 1543 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1544 } 1545 1546 return status; 1547 } 1548 1549 /** 1550 * i40e_nvmupd_nvm_write - Write NVM 1551 * @hw: pointer to hardware structure 1552 * @cmd: pointer to nvm update command buffer 1553 * @bytes: pointer to the data buffer 1554 * @perrno: pointer to return error code 1555 * 1556 * module, offset, data_size and data are in cmd structure 1557 **/ 1558 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, 1559 struct i40e_nvm_access *cmd, 1560 u8 *bytes, int *perrno) 1561 { 1562 i40e_status status = 0; 1563 struct i40e_asq_cmd_details cmd_details; 1564 u8 module, transaction; 1565 u8 preservation_flags; 1566 bool last; 1567 1568 transaction = i40e_nvmupd_get_transaction(cmd->config); 1569 module = i40e_nvmupd_get_module(cmd->config); 1570 last = (transaction & I40E_NVM_LCB); 1571 preservation_flags = i40e_nvmupd_get_preservation_flags(cmd->config); 1572 1573 memset(&cmd_details, 0, sizeof(cmd_details)); 1574 cmd_details.wb_desc = &hw->nvm_wb_desc; 1575 1576 status = i40e_aq_update_nvm(hw, module, cmd->offset, 1577 (u16)cmd->data_size, bytes, last, 1578 preservation_flags, &cmd_details); 1579 if (status) { 1580 i40e_debug(hw, I40E_DEBUG_NVM, 1581 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n", 1582 module, cmd->offset, cmd->data_size); 1583 i40e_debug(hw, I40E_DEBUG_NVM, 1584 "i40e_nvmupd_nvm_write status %d aq %d\n", 1585 status, hw->aq.asq_last_status); 1586 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1587 } 1588 1589 return status; 1590 } 1591