1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #include <linux/avf/virtchnl.h> 5 #include <linux/bitfield.h> 6 #include <linux/delay.h> 7 #include <linux/etherdevice.h> 8 #include <linux/pci.h> 9 #include "i40e_adminq_cmd.h" 10 #include "i40e_devids.h" 11 #include "i40e_prototype.h" 12 #include "i40e_register.h" 13 14 /** 15 * i40e_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the mac type of the adapter based on the 19 * vendor ID and device ID stored in the hw structure. 20 **/ 21 int i40e_set_mac_type(struct i40e_hw *hw) 22 { 23 int status = 0; 24 25 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 26 switch (hw->device_id) { 27 case I40E_DEV_ID_SFP_XL710: 28 case I40E_DEV_ID_QEMU: 29 case I40E_DEV_ID_KX_B: 30 case I40E_DEV_ID_KX_C: 31 case I40E_DEV_ID_QSFP_A: 32 case I40E_DEV_ID_QSFP_B: 33 case I40E_DEV_ID_QSFP_C: 34 case I40E_DEV_ID_1G_BASE_T_BC: 35 case I40E_DEV_ID_5G_BASE_T_BC: 36 case I40E_DEV_ID_10G_BASE_T: 37 case I40E_DEV_ID_10G_BASE_T4: 38 case I40E_DEV_ID_10G_BASE_T_BC: 39 case I40E_DEV_ID_10G_B: 40 case I40E_DEV_ID_10G_SFP: 41 case I40E_DEV_ID_20G_KR2: 42 case I40E_DEV_ID_20G_KR2_A: 43 case I40E_DEV_ID_25G_B: 44 case I40E_DEV_ID_25G_SFP28: 45 case I40E_DEV_ID_X710_N3000: 46 case I40E_DEV_ID_XXV710_N3000: 47 hw->mac.type = I40E_MAC_XL710; 48 break; 49 case I40E_DEV_ID_KX_X722: 50 case I40E_DEV_ID_QSFP_X722: 51 case I40E_DEV_ID_SFP_X722: 52 case I40E_DEV_ID_1G_BASE_T_X722: 53 case I40E_DEV_ID_10G_BASE_T_X722: 54 case I40E_DEV_ID_SFP_I_X722: 55 case I40E_DEV_ID_SFP_X722_A: 56 hw->mac.type = I40E_MAC_X722; 57 break; 58 default: 59 hw->mac.type = I40E_MAC_GENERIC; 60 break; 61 } 62 } else { 63 status = -ENODEV; 64 } 65 66 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 67 hw->mac.type, status); 68 return status; 69 } 70 71 /** 72 * i40e_aq_str - convert AQ err code to a string 73 * @hw: pointer to the HW structure 74 * @aq_err: the AQ error code to convert 75 **/ 76 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 77 { 78 switch (aq_err) { 79 case I40E_AQ_RC_OK: 80 return "OK"; 81 case I40E_AQ_RC_EPERM: 82 return "I40E_AQ_RC_EPERM"; 83 case I40E_AQ_RC_ENOENT: 84 return "I40E_AQ_RC_ENOENT"; 85 case I40E_AQ_RC_ESRCH: 86 return "I40E_AQ_RC_ESRCH"; 87 case I40E_AQ_RC_EINTR: 88 return "I40E_AQ_RC_EINTR"; 89 case I40E_AQ_RC_EIO: 90 return "I40E_AQ_RC_EIO"; 91 case I40E_AQ_RC_ENXIO: 92 return "I40E_AQ_RC_ENXIO"; 93 case I40E_AQ_RC_E2BIG: 94 return "I40E_AQ_RC_E2BIG"; 95 case I40E_AQ_RC_EAGAIN: 96 return "I40E_AQ_RC_EAGAIN"; 97 case I40E_AQ_RC_ENOMEM: 98 return "I40E_AQ_RC_ENOMEM"; 99 case I40E_AQ_RC_EACCES: 100 return "I40E_AQ_RC_EACCES"; 101 case I40E_AQ_RC_EFAULT: 102 return "I40E_AQ_RC_EFAULT"; 103 case I40E_AQ_RC_EBUSY: 104 return "I40E_AQ_RC_EBUSY"; 105 case I40E_AQ_RC_EEXIST: 106 return "I40E_AQ_RC_EEXIST"; 107 case I40E_AQ_RC_EINVAL: 108 return "I40E_AQ_RC_EINVAL"; 109 case I40E_AQ_RC_ENOTTY: 110 return "I40E_AQ_RC_ENOTTY"; 111 case I40E_AQ_RC_ENOSPC: 112 return "I40E_AQ_RC_ENOSPC"; 113 case I40E_AQ_RC_ENOSYS: 114 return "I40E_AQ_RC_ENOSYS"; 115 case I40E_AQ_RC_ERANGE: 116 return "I40E_AQ_RC_ERANGE"; 117 case I40E_AQ_RC_EFLUSHED: 118 return "I40E_AQ_RC_EFLUSHED"; 119 case I40E_AQ_RC_BAD_ADDR: 120 return "I40E_AQ_RC_BAD_ADDR"; 121 case I40E_AQ_RC_EMODE: 122 return "I40E_AQ_RC_EMODE"; 123 case I40E_AQ_RC_EFBIG: 124 return "I40E_AQ_RC_EFBIG"; 125 } 126 127 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 128 return hw->err_str; 129 } 130 131 /** 132 * i40e_debug_aq 133 * @hw: debug mask related to admin queue 134 * @mask: debug mask 135 * @desc: pointer to admin queue descriptor 136 * @buffer: pointer to command buffer 137 * @buf_len: max length of buffer 138 * 139 * Dumps debug log about adminq command with descriptor contents. 140 **/ 141 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 142 void *buffer, u16 buf_len) 143 { 144 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 145 u32 effective_mask = hw->debug_mask & mask; 146 char prefix[27]; 147 u16 len; 148 u8 *buf = (u8 *)buffer; 149 150 if (!effective_mask || !desc) 151 return; 152 153 len = le16_to_cpu(aq_desc->datalen); 154 155 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 156 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 157 le16_to_cpu(aq_desc->opcode), 158 le16_to_cpu(aq_desc->flags), 159 le16_to_cpu(aq_desc->datalen), 160 le16_to_cpu(aq_desc->retval)); 161 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 162 "\tcookie (h,l) 0x%08X 0x%08X\n", 163 le32_to_cpu(aq_desc->cookie_high), 164 le32_to_cpu(aq_desc->cookie_low)); 165 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 166 "\tparam (0,1) 0x%08X 0x%08X\n", 167 le32_to_cpu(aq_desc->params.internal.param0), 168 le32_to_cpu(aq_desc->params.internal.param1)); 169 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 170 "\taddr (h,l) 0x%08X 0x%08X\n", 171 le32_to_cpu(aq_desc->params.external.addr_high), 172 le32_to_cpu(aq_desc->params.external.addr_low)); 173 174 if (buffer && buf_len != 0 && len != 0 && 175 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { 176 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 177 if (buf_len < len) 178 len = buf_len; 179 180 snprintf(prefix, sizeof(prefix), 181 "i40e %02x:%02x.%x: \t0x", 182 hw->bus.bus_id, 183 hw->bus.device, 184 hw->bus.func); 185 186 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 187 16, 1, buf, len, false); 188 } 189 } 190 191 /** 192 * i40e_check_asq_alive 193 * @hw: pointer to the hw struct 194 * 195 * Returns true if Queue is enabled else false. 196 **/ 197 bool i40e_check_asq_alive(struct i40e_hw *hw) 198 { 199 /* Check if the queue is initialized */ 200 if (!hw->aq.asq.count) 201 return false; 202 203 return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK); 204 } 205 206 /** 207 * i40e_aq_queue_shutdown 208 * @hw: pointer to the hw struct 209 * @unloading: is the driver unloading itself 210 * 211 * Tell the Firmware that we're shutting down the AdminQ and whether 212 * or not the driver is unloading as well. 213 **/ 214 int i40e_aq_queue_shutdown(struct i40e_hw *hw, 215 bool unloading) 216 { 217 struct i40e_aq_desc desc; 218 struct i40e_aqc_queue_shutdown *cmd = 219 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 220 int status; 221 222 i40e_fill_default_direct_cmd_desc(&desc, 223 i40e_aqc_opc_queue_shutdown); 224 225 if (unloading) 226 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 227 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 228 229 return status; 230 } 231 232 /** 233 * i40e_aq_get_set_rss_lut 234 * @hw: pointer to the hardware structure 235 * @vsi_id: vsi fw index 236 * @pf_lut: for PF table set true, for VSI table set false 237 * @lut: pointer to the lut buffer provided by the caller 238 * @lut_size: size of the lut buffer 239 * @set: set true to set the table, false to get the table 240 * 241 * Internal function to get or set RSS look up table 242 **/ 243 static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 244 u16 vsi_id, bool pf_lut, 245 u8 *lut, u16 lut_size, 246 bool set) 247 { 248 struct i40e_aq_desc desc; 249 struct i40e_aqc_get_set_rss_lut *cmd_resp = 250 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 251 int status; 252 u16 flags; 253 254 if (set) 255 i40e_fill_default_direct_cmd_desc(&desc, 256 i40e_aqc_opc_set_rss_lut); 257 else 258 i40e_fill_default_direct_cmd_desc(&desc, 259 i40e_aqc_opc_get_rss_lut); 260 261 /* Indirect command */ 262 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 263 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 264 265 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) | 266 FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1); 267 cmd_resp->vsi_id = cpu_to_le16(vsi_id); 268 269 if (pf_lut) 270 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 271 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF); 272 else 273 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 274 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI); 275 276 cmd_resp->flags = cpu_to_le16(flags); 277 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 278 279 return status; 280 } 281 282 /** 283 * i40e_aq_get_rss_lut 284 * @hw: pointer to the hardware structure 285 * @vsi_id: vsi fw index 286 * @pf_lut: for PF table set true, for VSI table set false 287 * @lut: pointer to the lut buffer provided by the caller 288 * @lut_size: size of the lut buffer 289 * 290 * get the RSS lookup table, PF or VSI type 291 **/ 292 int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 293 bool pf_lut, u8 *lut, u16 lut_size) 294 { 295 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 296 false); 297 } 298 299 /** 300 * i40e_aq_set_rss_lut 301 * @hw: pointer to the hardware structure 302 * @vsi_id: vsi fw index 303 * @pf_lut: for PF table set true, for VSI table set false 304 * @lut: pointer to the lut buffer provided by the caller 305 * @lut_size: size of the lut buffer 306 * 307 * set the RSS lookup table, PF or VSI type 308 **/ 309 int i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 310 bool pf_lut, u8 *lut, u16 lut_size) 311 { 312 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 313 } 314 315 /** 316 * i40e_aq_get_set_rss_key 317 * @hw: pointer to the hw struct 318 * @vsi_id: vsi fw index 319 * @key: pointer to key info struct 320 * @set: set true to set the key, false to get the key 321 * 322 * get the RSS key per VSI 323 **/ 324 static int i40e_aq_get_set_rss_key(struct i40e_hw *hw, 325 u16 vsi_id, 326 struct i40e_aqc_get_set_rss_key_data *key, 327 bool set) 328 { 329 struct i40e_aq_desc desc; 330 struct i40e_aqc_get_set_rss_key *cmd_resp = 331 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 332 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 333 int status; 334 335 if (set) 336 i40e_fill_default_direct_cmd_desc(&desc, 337 i40e_aqc_opc_set_rss_key); 338 else 339 i40e_fill_default_direct_cmd_desc(&desc, 340 i40e_aqc_opc_get_rss_key); 341 342 /* Indirect command */ 343 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 344 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 345 346 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) | 347 FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1); 348 cmd_resp->vsi_id = cpu_to_le16(vsi_id); 349 350 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 351 352 return status; 353 } 354 355 /** 356 * i40e_aq_get_rss_key 357 * @hw: pointer to the hw struct 358 * @vsi_id: vsi fw index 359 * @key: pointer to key info struct 360 * 361 **/ 362 int i40e_aq_get_rss_key(struct i40e_hw *hw, 363 u16 vsi_id, 364 struct i40e_aqc_get_set_rss_key_data *key) 365 { 366 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 367 } 368 369 /** 370 * i40e_aq_set_rss_key 371 * @hw: pointer to the hw struct 372 * @vsi_id: vsi fw index 373 * @key: pointer to key info struct 374 * 375 * set the RSS key per VSI 376 **/ 377 int i40e_aq_set_rss_key(struct i40e_hw *hw, 378 u16 vsi_id, 379 struct i40e_aqc_get_set_rss_key_data *key) 380 { 381 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 382 } 383 384 /** 385 * i40e_init_shared_code - Initialize the shared code 386 * @hw: pointer to hardware structure 387 * 388 * This assigns the MAC type and PHY code and inits the NVM. 389 * Does not touch the hardware. This function must be called prior to any 390 * other function in the shared code. The i40e_hw structure should be 391 * memset to 0 prior to calling this function. The following fields in 392 * hw structure should be filled in prior to calling this function: 393 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 394 * subsystem_vendor_id, and revision_id 395 **/ 396 int i40e_init_shared_code(struct i40e_hw *hw) 397 { 398 u32 port, ari, func_rid; 399 int status = 0; 400 401 i40e_set_mac_type(hw); 402 403 switch (hw->mac.type) { 404 case I40E_MAC_XL710: 405 case I40E_MAC_X722: 406 break; 407 default: 408 return -ENODEV; 409 } 410 411 hw->phy.get_link_info = true; 412 413 /* Determine port number and PF number*/ 414 port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK, 415 rd32(hw, I40E_PFGEN_PORTNUM)); 416 hw->port = (u8)port; 417 ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK, 418 rd32(hw, I40E_GLPCI_CAPSUP)); 419 func_rid = rd32(hw, I40E_PF_FUNC_RID); 420 if (ari) 421 hw->pf_id = (u8)(func_rid & 0xff); 422 else 423 hw->pf_id = (u8)(func_rid & 0x7); 424 425 status = i40e_init_nvm(hw); 426 return status; 427 } 428 429 /** 430 * i40e_aq_mac_address_read - Retrieve the MAC addresses 431 * @hw: pointer to the hw struct 432 * @flags: a return indicator of what addresses were added to the addr store 433 * @addrs: the requestor's mac addr store 434 * @cmd_details: pointer to command details structure or NULL 435 **/ 436 static int 437 i40e_aq_mac_address_read(struct i40e_hw *hw, 438 u16 *flags, 439 struct i40e_aqc_mac_address_read_data *addrs, 440 struct i40e_asq_cmd_details *cmd_details) 441 { 442 struct i40e_aq_desc desc; 443 struct i40e_aqc_mac_address_read *cmd_data = 444 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 445 int status; 446 447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 448 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 449 450 status = i40e_asq_send_command(hw, &desc, addrs, 451 sizeof(*addrs), cmd_details); 452 *flags = le16_to_cpu(cmd_data->command_flags); 453 454 return status; 455 } 456 457 /** 458 * i40e_aq_mac_address_write - Change the MAC addresses 459 * @hw: pointer to the hw struct 460 * @flags: indicates which MAC to be written 461 * @mac_addr: address to write 462 * @cmd_details: pointer to command details structure or NULL 463 **/ 464 int i40e_aq_mac_address_write(struct i40e_hw *hw, 465 u16 flags, u8 *mac_addr, 466 struct i40e_asq_cmd_details *cmd_details) 467 { 468 struct i40e_aq_desc desc; 469 struct i40e_aqc_mac_address_write *cmd_data = 470 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 471 int status; 472 473 i40e_fill_default_direct_cmd_desc(&desc, 474 i40e_aqc_opc_mac_address_write); 475 cmd_data->command_flags = cpu_to_le16(flags); 476 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 477 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 478 ((u32)mac_addr[3] << 16) | 479 ((u32)mac_addr[4] << 8) | 480 mac_addr[5]); 481 482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 483 484 return status; 485 } 486 487 /** 488 * i40e_get_mac_addr - get MAC address 489 * @hw: pointer to the HW structure 490 * @mac_addr: pointer to MAC address 491 * 492 * Reads the adapter's MAC address from register 493 **/ 494 int i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 495 { 496 struct i40e_aqc_mac_address_read_data addrs; 497 u16 flags = 0; 498 int status; 499 500 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 501 502 if (flags & I40E_AQC_LAN_ADDR_VALID) 503 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 504 505 return status; 506 } 507 508 /** 509 * i40e_get_port_mac_addr - get Port MAC address 510 * @hw: pointer to the HW structure 511 * @mac_addr: pointer to Port MAC address 512 * 513 * Reads the adapter's Port MAC address 514 **/ 515 int i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 516 { 517 struct i40e_aqc_mac_address_read_data addrs; 518 u16 flags = 0; 519 int status; 520 521 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 522 if (status) 523 return status; 524 525 if (flags & I40E_AQC_PORT_ADDR_VALID) 526 ether_addr_copy(mac_addr, addrs.port_mac); 527 else 528 status = -EINVAL; 529 530 return status; 531 } 532 533 /** 534 * i40e_pre_tx_queue_cfg - pre tx queue configure 535 * @hw: pointer to the HW structure 536 * @queue: target PF queue index 537 * @enable: state change request 538 * 539 * Handles hw requirement to indicate intention to enable 540 * or disable target queue. 541 **/ 542 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 543 { 544 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 545 u32 reg_block = 0; 546 u32 reg_val; 547 548 if (abs_queue_idx >= 128) { 549 reg_block = abs_queue_idx / 128; 550 abs_queue_idx %= 128; 551 } 552 553 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 554 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 555 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 556 557 if (enable) 558 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 559 else 560 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 561 562 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 563 } 564 565 /** 566 * i40e_get_pba_string - Reads part number string from EEPROM 567 * @hw: pointer to hardware structure 568 * 569 * Reads the part number string from the EEPROM and stores it 570 * into newly allocated buffer and saves resulting pointer 571 * to i40e_hw->pba_id field. 572 **/ 573 void i40e_get_pba_string(struct i40e_hw *hw) 574 { 575 #define I40E_NVM_PBA_FLAGS_BLK_PRESENT 0xFAFA 576 u16 pba_word = 0; 577 u16 pba_size = 0; 578 u16 pba_ptr = 0; 579 int status; 580 char *ptr; 581 u16 i; 582 583 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 584 if (status) { 585 hw_dbg(hw, "Failed to read PBA flags.\n"); 586 return; 587 } 588 if (pba_word != I40E_NVM_PBA_FLAGS_BLK_PRESENT) { 589 hw_dbg(hw, "PBA block is not present.\n"); 590 return; 591 } 592 593 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 594 if (status) { 595 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 596 return; 597 } 598 599 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 600 if (status) { 601 hw_dbg(hw, "Failed to read PBA Block size.\n"); 602 return; 603 } 604 605 /* Subtract one to get PBA word count (PBA Size word is included in 606 * total size) and advance pointer to first PBA word. 607 */ 608 pba_size--; 609 pba_ptr++; 610 if (!pba_size) { 611 hw_dbg(hw, "PBA ID is empty.\n"); 612 return; 613 } 614 615 ptr = devm_kzalloc(i40e_hw_to_dev(hw), pba_size * 2 + 1, GFP_KERNEL); 616 if (!ptr) 617 return; 618 hw->pba_id = ptr; 619 620 for (i = 0; i < pba_size; i++) { 621 status = i40e_read_nvm_word(hw, pba_ptr + i, &pba_word); 622 if (status) { 623 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 624 devm_kfree(i40e_hw_to_dev(hw), hw->pba_id); 625 hw->pba_id = NULL; 626 return; 627 } 628 629 *ptr++ = (pba_word >> 8) & 0xFF; 630 *ptr++ = pba_word & 0xFF; 631 } 632 } 633 634 /** 635 * i40e_get_media_type - Gets media type 636 * @hw: pointer to the hardware structure 637 **/ 638 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 639 { 640 enum i40e_media_type media; 641 642 switch (hw->phy.link_info.phy_type) { 643 case I40E_PHY_TYPE_10GBASE_SR: 644 case I40E_PHY_TYPE_10GBASE_LR: 645 case I40E_PHY_TYPE_1000BASE_SX: 646 case I40E_PHY_TYPE_1000BASE_LX: 647 case I40E_PHY_TYPE_40GBASE_SR4: 648 case I40E_PHY_TYPE_40GBASE_LR4: 649 case I40E_PHY_TYPE_25GBASE_LR: 650 case I40E_PHY_TYPE_25GBASE_SR: 651 media = I40E_MEDIA_TYPE_FIBER; 652 break; 653 case I40E_PHY_TYPE_100BASE_TX: 654 case I40E_PHY_TYPE_1000BASE_T: 655 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS: 656 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS: 657 case I40E_PHY_TYPE_10GBASE_T: 658 media = I40E_MEDIA_TYPE_BASET; 659 break; 660 case I40E_PHY_TYPE_10GBASE_CR1_CU: 661 case I40E_PHY_TYPE_40GBASE_CR4_CU: 662 case I40E_PHY_TYPE_10GBASE_CR1: 663 case I40E_PHY_TYPE_40GBASE_CR4: 664 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 665 case I40E_PHY_TYPE_40GBASE_AOC: 666 case I40E_PHY_TYPE_10GBASE_AOC: 667 case I40E_PHY_TYPE_25GBASE_CR: 668 case I40E_PHY_TYPE_25GBASE_AOC: 669 case I40E_PHY_TYPE_25GBASE_ACC: 670 media = I40E_MEDIA_TYPE_DA; 671 break; 672 case I40E_PHY_TYPE_1000BASE_KX: 673 case I40E_PHY_TYPE_10GBASE_KX4: 674 case I40E_PHY_TYPE_10GBASE_KR: 675 case I40E_PHY_TYPE_40GBASE_KR4: 676 case I40E_PHY_TYPE_20GBASE_KR2: 677 case I40E_PHY_TYPE_25GBASE_KR: 678 media = I40E_MEDIA_TYPE_BACKPLANE; 679 break; 680 case I40E_PHY_TYPE_SGMII: 681 case I40E_PHY_TYPE_XAUI: 682 case I40E_PHY_TYPE_XFI: 683 case I40E_PHY_TYPE_XLAUI: 684 case I40E_PHY_TYPE_XLPPI: 685 default: 686 media = I40E_MEDIA_TYPE_UNKNOWN; 687 break; 688 } 689 690 return media; 691 } 692 693 /** 694 * i40e_poll_globr - Poll for Global Reset completion 695 * @hw: pointer to the hardware structure 696 * @retry_limit: how many times to retry before failure 697 **/ 698 static int i40e_poll_globr(struct i40e_hw *hw, 699 u32 retry_limit) 700 { 701 u32 cnt, reg = 0; 702 703 for (cnt = 0; cnt < retry_limit; cnt++) { 704 reg = rd32(hw, I40E_GLGEN_RSTAT); 705 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 706 return 0; 707 msleep(100); 708 } 709 710 hw_dbg(hw, "Global reset failed.\n"); 711 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg); 712 713 return -EIO; 714 } 715 716 #define I40E_PF_RESET_WAIT_COUNT_A0 200 717 #define I40E_PF_RESET_WAIT_COUNT 200 718 /** 719 * i40e_pf_reset - Reset the PF 720 * @hw: pointer to the hardware structure 721 * 722 * Assuming someone else has triggered a global reset, 723 * assure the global reset is complete and then reset the PF 724 **/ 725 int i40e_pf_reset(struct i40e_hw *hw) 726 { 727 u32 cnt = 0; 728 u32 cnt1 = 0; 729 u32 reg = 0; 730 u32 grst_del; 731 732 /* Poll for Global Reset steady state in case of recent GRST. 733 * The grst delay value is in 100ms units, and we'll wait a 734 * couple counts longer to be sure we don't just miss the end. 735 */ 736 grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK, 737 rd32(hw, I40E_GLGEN_RSTCTL)); 738 739 /* It can take upto 15 secs for GRST steady state. 740 * Bump it to 16 secs max to be safe. 741 */ 742 grst_del = grst_del * 20; 743 744 for (cnt = 0; cnt < grst_del; cnt++) { 745 reg = rd32(hw, I40E_GLGEN_RSTAT); 746 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 747 break; 748 msleep(100); 749 } 750 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 751 hw_dbg(hw, "Global reset polling failed to complete.\n"); 752 return -EIO; 753 } 754 755 /* Now Wait for the FW to be ready */ 756 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 757 reg = rd32(hw, I40E_GLNVM_ULD); 758 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 759 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 760 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 761 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 762 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 763 break; 764 } 765 usleep_range(10000, 20000); 766 } 767 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 768 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 769 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 770 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 771 return -EIO; 772 } 773 774 /* If there was a Global Reset in progress when we got here, 775 * we don't need to do the PF Reset 776 */ 777 if (!cnt) { 778 u32 reg2 = 0; 779 if (hw->revision_id == 0) 780 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 781 else 782 cnt = I40E_PF_RESET_WAIT_COUNT; 783 reg = rd32(hw, I40E_PFGEN_CTRL); 784 wr32(hw, I40E_PFGEN_CTRL, 785 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 786 for (; cnt; cnt--) { 787 reg = rd32(hw, I40E_PFGEN_CTRL); 788 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 789 break; 790 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 791 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 792 break; 793 usleep_range(1000, 2000); 794 } 795 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 796 if (i40e_poll_globr(hw, grst_del)) 797 return -EIO; 798 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 799 hw_dbg(hw, "PF reset polling failed to complete.\n"); 800 return -EIO; 801 } 802 } 803 804 i40e_clear_pxe_mode(hw); 805 806 return 0; 807 } 808 809 /** 810 * i40e_clear_hw - clear out any left over hw state 811 * @hw: pointer to the hw struct 812 * 813 * Clear queues and interrupts, typically called at init time, 814 * but after the capabilities have been found so we know how many 815 * queues and msix vectors have been allocated. 816 **/ 817 void i40e_clear_hw(struct i40e_hw *hw) 818 { 819 u32 num_queues, base_queue; 820 u32 num_pf_int; 821 u32 num_vf_int; 822 u32 num_vfs; 823 u32 i, j; 824 u32 val; 825 u32 eol = 0x7ff; 826 827 /* get number of interrupts, queues, and VFs */ 828 val = rd32(hw, I40E_GLPCI_CNF2); 829 num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val); 830 num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val); 831 832 val = rd32(hw, I40E_PFLAN_QALLOC); 833 base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val); 834 j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val); 835 if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue) 836 num_queues = (j - base_queue) + 1; 837 else 838 num_queues = 0; 839 840 val = rd32(hw, I40E_PF_VT_PFALLOC); 841 i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val); 842 j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val); 843 if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i) 844 num_vfs = (j - i) + 1; 845 else 846 num_vfs = 0; 847 848 /* stop all the interrupts */ 849 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 850 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 851 for (i = 0; i < num_pf_int - 2; i++) 852 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 853 854 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 855 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 856 wr32(hw, I40E_PFINT_LNKLST0, val); 857 for (i = 0; i < num_pf_int - 2; i++) 858 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 859 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 860 for (i = 0; i < num_vfs; i++) 861 wr32(hw, I40E_VPINT_LNKLST0(i), val); 862 for (i = 0; i < num_vf_int - 2; i++) 863 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 864 865 /* warn the HW of the coming Tx disables */ 866 for (i = 0; i < num_queues; i++) { 867 u32 abs_queue_idx = base_queue + i; 868 u32 reg_block = 0; 869 870 if (abs_queue_idx >= 128) { 871 reg_block = abs_queue_idx / 128; 872 abs_queue_idx %= 128; 873 } 874 875 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 876 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 877 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 878 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 879 880 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 881 } 882 udelay(400); 883 884 /* stop all the queues */ 885 for (i = 0; i < num_queues; i++) { 886 wr32(hw, I40E_QINT_TQCTL(i), 0); 887 wr32(hw, I40E_QTX_ENA(i), 0); 888 wr32(hw, I40E_QINT_RQCTL(i), 0); 889 wr32(hw, I40E_QRX_ENA(i), 0); 890 } 891 892 /* short wait for all queue disables to settle */ 893 udelay(50); 894 } 895 896 /** 897 * i40e_clear_pxe_mode - clear pxe operations mode 898 * @hw: pointer to the hw struct 899 * 900 * Make sure all PXE mode settings are cleared, including things 901 * like descriptor fetch/write-back mode. 902 **/ 903 void i40e_clear_pxe_mode(struct i40e_hw *hw) 904 { 905 u32 reg; 906 907 if (i40e_check_asq_alive(hw)) 908 i40e_aq_clear_pxe_mode(hw, NULL); 909 910 /* Clear single descriptor fetch/write-back mode */ 911 reg = rd32(hw, I40E_GLLAN_RCTL_0); 912 913 if (hw->revision_id == 0) { 914 /* As a work around clear PXE_MODE instead of setting it */ 915 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 916 } else { 917 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 918 } 919 } 920 921 /** 922 * i40e_led_is_mine - helper to find matching led 923 * @hw: pointer to the hw struct 924 * @idx: index into GPIO registers 925 * 926 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 927 */ 928 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 929 { 930 u32 gpio_val = 0; 931 u32 port; 932 933 if (!I40E_IS_X710TL_DEVICE(hw->device_id) && 934 !hw->func_caps.led[idx]) 935 return 0; 936 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 937 port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val); 938 939 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 940 * if it is not our port then ignore 941 */ 942 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 943 (port != hw->port)) 944 return 0; 945 946 return gpio_val; 947 } 948 949 #define I40E_FW_LED BIT(4) 950 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \ 951 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 952 953 #define I40E_LED0 22 954 955 #define I40E_PIN_FUNC_SDP 0x0 956 #define I40E_PIN_FUNC_LED 0x1 957 958 /** 959 * i40e_led_get - return current on/off mode 960 * @hw: pointer to the hw struct 961 * 962 * The value returned is the 'mode' field as defined in the 963 * GPIO register definitions: 0x0 = off, 0xf = on, and other 964 * values are variations of possible behaviors relating to 965 * blink, link, and wire. 966 **/ 967 u32 i40e_led_get(struct i40e_hw *hw) 968 { 969 u32 mode = 0; 970 int i; 971 972 /* as per the documentation GPIO 22-29 are the LED 973 * GPIO pins named LED0..LED7 974 */ 975 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 976 u32 gpio_val = i40e_led_is_mine(hw, i); 977 978 if (!gpio_val) 979 continue; 980 981 mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val); 982 break; 983 } 984 985 return mode; 986 } 987 988 /** 989 * i40e_led_set - set new on/off mode 990 * @hw: pointer to the hw struct 991 * @mode: 0=off, 0xf=on (else see manual for mode details) 992 * @blink: true if the LED should blink when on, false if steady 993 * 994 * if this function is used to turn on the blink it should 995 * be used to disable the blink when restoring the original state. 996 **/ 997 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 998 { 999 int i; 1000 1001 if (mode & ~I40E_LED_MODE_VALID) { 1002 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1003 return; 1004 } 1005 1006 /* as per the documentation GPIO 22-29 are the LED 1007 * GPIO pins named LED0..LED7 1008 */ 1009 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1010 u32 gpio_val = i40e_led_is_mine(hw, i); 1011 1012 if (!gpio_val) 1013 continue; 1014 1015 if (I40E_IS_X710TL_DEVICE(hw->device_id)) { 1016 u32 pin_func = 0; 1017 1018 if (mode & I40E_FW_LED) 1019 pin_func = I40E_PIN_FUNC_SDP; 1020 else 1021 pin_func = I40E_PIN_FUNC_LED; 1022 1023 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK; 1024 gpio_val |= 1025 FIELD_PREP(I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK, 1026 pin_func); 1027 } 1028 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1029 /* this & is a bit of paranoia, but serves as a range check */ 1030 gpio_val |= FIELD_PREP(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, 1031 mode); 1032 1033 if (blink) 1034 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1035 else 1036 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1037 1038 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1039 break; 1040 } 1041 } 1042 1043 /* Admin command wrappers */ 1044 1045 /** 1046 * i40e_aq_get_phy_capabilities 1047 * @hw: pointer to the hw struct 1048 * @abilities: structure for PHY capabilities to be filled 1049 * @qualified_modules: report Qualified Modules 1050 * @report_init: report init capabilities (active are default) 1051 * @cmd_details: pointer to command details structure or NULL 1052 * 1053 * Returns the various PHY abilities supported on the Port. 1054 **/ 1055 int 1056 i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1057 bool qualified_modules, bool report_init, 1058 struct i40e_aq_get_phy_abilities_resp *abilities, 1059 struct i40e_asq_cmd_details *cmd_details) 1060 { 1061 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1062 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1063 struct i40e_aq_desc desc; 1064 int status; 1065 1066 if (!abilities) 1067 return -EINVAL; 1068 1069 do { 1070 i40e_fill_default_direct_cmd_desc(&desc, 1071 i40e_aqc_opc_get_phy_abilities); 1072 1073 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1074 if (abilities_size > I40E_AQ_LARGE_BUF) 1075 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1076 1077 if (qualified_modules) 1078 desc.params.external.param0 |= 1079 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1080 1081 if (report_init) 1082 desc.params.external.param0 |= 1083 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1084 1085 status = i40e_asq_send_command(hw, &desc, abilities, 1086 abilities_size, cmd_details); 1087 1088 switch (hw->aq.asq_last_status) { 1089 case I40E_AQ_RC_EIO: 1090 status = -EIO; 1091 break; 1092 case I40E_AQ_RC_EAGAIN: 1093 usleep_range(1000, 2000); 1094 total_delay++; 1095 status = -EIO; 1096 break; 1097 /* also covers I40E_AQ_RC_OK */ 1098 default: 1099 break; 1100 } 1101 1102 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) && 1103 (total_delay < max_delay)); 1104 1105 if (status) 1106 return status; 1107 1108 if (report_init) { 1109 if (hw->mac.type == I40E_MAC_XL710 && 1110 i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR, 1111 I40E_MINOR_VER_GET_LINK_INFO_XL710)) { 1112 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1113 } else { 1114 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1115 hw->phy.phy_types |= 1116 ((u64)abilities->phy_type_ext << 32); 1117 } 1118 } 1119 1120 return status; 1121 } 1122 1123 /** 1124 * i40e_aq_set_phy_config 1125 * @hw: pointer to the hw struct 1126 * @config: structure with PHY configuration to be set 1127 * @cmd_details: pointer to command details structure or NULL 1128 * 1129 * Set the various PHY configuration parameters 1130 * supported on the Port.One or more of the Set PHY config parameters may be 1131 * ignored in an MFP mode as the PF may not have the privilege to set some 1132 * of the PHY Config parameters. This status will be indicated by the 1133 * command response. 1134 **/ 1135 int i40e_aq_set_phy_config(struct i40e_hw *hw, 1136 struct i40e_aq_set_phy_config *config, 1137 struct i40e_asq_cmd_details *cmd_details) 1138 { 1139 struct i40e_aq_desc desc; 1140 struct i40e_aq_set_phy_config *cmd = 1141 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1142 int status; 1143 1144 if (!config) 1145 return -EINVAL; 1146 1147 i40e_fill_default_direct_cmd_desc(&desc, 1148 i40e_aqc_opc_set_phy_config); 1149 1150 *cmd = *config; 1151 1152 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1153 1154 return status; 1155 } 1156 1157 static noinline_for_stack int 1158 i40e_set_fc_status(struct i40e_hw *hw, 1159 struct i40e_aq_get_phy_abilities_resp *abilities, 1160 bool atomic_restart) 1161 { 1162 struct i40e_aq_set_phy_config config; 1163 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1164 u8 pause_mask = 0x0; 1165 1166 switch (fc_mode) { 1167 case I40E_FC_FULL: 1168 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1169 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1170 break; 1171 case I40E_FC_RX_PAUSE: 1172 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1173 break; 1174 case I40E_FC_TX_PAUSE: 1175 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1176 break; 1177 default: 1178 break; 1179 } 1180 1181 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1182 /* clear the old pause settings */ 1183 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1184 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1185 /* set the new abilities */ 1186 config.abilities |= pause_mask; 1187 /* If the abilities have changed, then set the new config */ 1188 if (config.abilities == abilities->abilities) 1189 return 0; 1190 1191 /* Auto restart link so settings take effect */ 1192 if (atomic_restart) 1193 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1194 /* Copy over all the old settings */ 1195 config.phy_type = abilities->phy_type; 1196 config.phy_type_ext = abilities->phy_type_ext; 1197 config.link_speed = abilities->link_speed; 1198 config.eee_capability = abilities->eee_capability; 1199 config.eeer = abilities->eeer_val; 1200 config.low_power_ctrl = abilities->d3_lpan; 1201 config.fec_config = abilities->fec_cfg_curr_mod_ext_info & 1202 I40E_AQ_PHY_FEC_CONFIG_MASK; 1203 1204 return i40e_aq_set_phy_config(hw, &config, NULL); 1205 } 1206 1207 /** 1208 * i40e_set_fc 1209 * @hw: pointer to the hw struct 1210 * @aq_failures: buffer to return AdminQ failure information 1211 * @atomic_restart: whether to enable atomic link restart 1212 * 1213 * Set the requested flow control mode using set_phy_config. 1214 **/ 1215 int i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1216 bool atomic_restart) 1217 { 1218 struct i40e_aq_get_phy_abilities_resp abilities; 1219 int status; 1220 1221 *aq_failures = 0x0; 1222 1223 /* Get the current phy config */ 1224 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1225 NULL); 1226 if (status) { 1227 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1228 return status; 1229 } 1230 1231 status = i40e_set_fc_status(hw, &abilities, atomic_restart); 1232 if (status) 1233 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1234 1235 /* Update the link info */ 1236 status = i40e_update_link_info(hw); 1237 if (status) { 1238 /* Wait a little bit (on 40G cards it sometimes takes a really 1239 * long time for link to come back from the atomic reset) 1240 * and try once more 1241 */ 1242 msleep(1000); 1243 status = i40e_update_link_info(hw); 1244 } 1245 if (status) 1246 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1247 1248 return status; 1249 } 1250 1251 /** 1252 * i40e_aq_clear_pxe_mode 1253 * @hw: pointer to the hw struct 1254 * @cmd_details: pointer to command details structure or NULL 1255 * 1256 * Tell the firmware that the driver is taking over from PXE 1257 **/ 1258 int i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1259 struct i40e_asq_cmd_details *cmd_details) 1260 { 1261 struct i40e_aq_desc desc; 1262 struct i40e_aqc_clear_pxe *cmd = 1263 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1264 int status; 1265 1266 i40e_fill_default_direct_cmd_desc(&desc, 1267 i40e_aqc_opc_clear_pxe_mode); 1268 1269 cmd->rx_cnt = 0x2; 1270 1271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1272 1273 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1274 1275 return status; 1276 } 1277 1278 /** 1279 * i40e_aq_set_link_restart_an 1280 * @hw: pointer to the hw struct 1281 * @enable_link: if true: enable link, if false: disable link 1282 * @cmd_details: pointer to command details structure or NULL 1283 * 1284 * Sets up the link and restarts the Auto-Negotiation over the link. 1285 **/ 1286 int i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1287 bool enable_link, 1288 struct i40e_asq_cmd_details *cmd_details) 1289 { 1290 struct i40e_aq_desc desc; 1291 struct i40e_aqc_set_link_restart_an *cmd = 1292 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1293 int status; 1294 1295 i40e_fill_default_direct_cmd_desc(&desc, 1296 i40e_aqc_opc_set_link_restart_an); 1297 1298 cmd->command = I40E_AQ_PHY_RESTART_AN; 1299 if (enable_link) 1300 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1301 else 1302 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1303 1304 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1305 1306 return status; 1307 } 1308 1309 /** 1310 * i40e_aq_get_link_info 1311 * @hw: pointer to the hw struct 1312 * @enable_lse: enable/disable LinkStatusEvent reporting 1313 * @link: pointer to link status structure - optional 1314 * @cmd_details: pointer to command details structure or NULL 1315 * 1316 * Returns the link status of the adapter. 1317 **/ 1318 int i40e_aq_get_link_info(struct i40e_hw *hw, 1319 bool enable_lse, struct i40e_link_status *link, 1320 struct i40e_asq_cmd_details *cmd_details) 1321 { 1322 struct i40e_aq_desc desc; 1323 struct i40e_aqc_get_link_status *resp = 1324 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1325 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1326 bool tx_pause, rx_pause; 1327 u16 command_flags; 1328 int status; 1329 1330 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1331 1332 if (enable_lse) 1333 command_flags = I40E_AQ_LSE_ENABLE; 1334 else 1335 command_flags = I40E_AQ_LSE_DISABLE; 1336 resp->command_flags = cpu_to_le16(command_flags); 1337 1338 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1339 1340 if (status) 1341 goto aq_get_link_info_exit; 1342 1343 /* save off old link status information */ 1344 hw->phy.link_info_old = *hw_link_info; 1345 1346 /* update link status */ 1347 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1348 hw->phy.media_type = i40e_get_media_type(hw); 1349 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1350 hw_link_info->link_info = resp->link_info; 1351 hw_link_info->an_info = resp->an_info; 1352 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1353 I40E_AQ_CONFIG_FEC_RS_ENA); 1354 hw_link_info->ext_info = resp->ext_info; 1355 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1356 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1357 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1358 1359 /* update fc info */ 1360 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1361 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1362 if (tx_pause & rx_pause) 1363 hw->fc.current_mode = I40E_FC_FULL; 1364 else if (tx_pause) 1365 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1366 else if (rx_pause) 1367 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1368 else 1369 hw->fc.current_mode = I40E_FC_NONE; 1370 1371 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1372 hw_link_info->crc_enable = true; 1373 else 1374 hw_link_info->crc_enable = false; 1375 1376 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1377 hw_link_info->lse_enable = true; 1378 else 1379 hw_link_info->lse_enable = false; 1380 1381 if (hw->mac.type == I40E_MAC_XL710 && i40e_is_fw_ver_lt(hw, 4, 40) && 1382 hw_link_info->phy_type == 0xE) 1383 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1384 1385 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps) && 1386 hw->mac.type != I40E_MAC_X722) { 1387 __le32 tmp; 1388 1389 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1390 hw->phy.phy_types = le32_to_cpu(tmp); 1391 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1392 } 1393 1394 /* save link status information */ 1395 if (link) 1396 *link = *hw_link_info; 1397 1398 /* flag cleared so helper functions don't call AQ again */ 1399 hw->phy.get_link_info = false; 1400 1401 aq_get_link_info_exit: 1402 return status; 1403 } 1404 1405 /** 1406 * i40e_aq_set_phy_int_mask 1407 * @hw: pointer to the hw struct 1408 * @mask: interrupt mask to be set 1409 * @cmd_details: pointer to command details structure or NULL 1410 * 1411 * Set link interrupt mask. 1412 **/ 1413 int i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1414 u16 mask, 1415 struct i40e_asq_cmd_details *cmd_details) 1416 { 1417 struct i40e_aq_desc desc; 1418 struct i40e_aqc_set_phy_int_mask *cmd = 1419 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1420 int status; 1421 1422 i40e_fill_default_direct_cmd_desc(&desc, 1423 i40e_aqc_opc_set_phy_int_mask); 1424 1425 cmd->event_mask = cpu_to_le16(mask); 1426 1427 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1428 1429 return status; 1430 } 1431 1432 /** 1433 * i40e_aq_set_mac_loopback 1434 * @hw: pointer to the HW struct 1435 * @ena_lpbk: Enable or Disable loopback 1436 * @cmd_details: pointer to command details structure or NULL 1437 * 1438 * Enable/disable loopback on a given port 1439 */ 1440 int i40e_aq_set_mac_loopback(struct i40e_hw *hw, bool ena_lpbk, 1441 struct i40e_asq_cmd_details *cmd_details) 1442 { 1443 struct i40e_aq_desc desc; 1444 struct i40e_aqc_set_lb_mode *cmd = 1445 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 1446 1447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_lb_modes); 1448 if (ena_lpbk) { 1449 if (hw->nvm.version <= I40E_LEGACY_LOOPBACK_NVM_VER) 1450 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL_LEGACY); 1451 else 1452 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL); 1453 } 1454 1455 return i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1456 } 1457 1458 /** 1459 * i40e_aq_set_phy_debug 1460 * @hw: pointer to the hw struct 1461 * @cmd_flags: debug command flags 1462 * @cmd_details: pointer to command details structure or NULL 1463 * 1464 * Reset the external PHY. 1465 **/ 1466 int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1467 struct i40e_asq_cmd_details *cmd_details) 1468 { 1469 struct i40e_aq_desc desc; 1470 struct i40e_aqc_set_phy_debug *cmd = 1471 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1472 int status; 1473 1474 i40e_fill_default_direct_cmd_desc(&desc, 1475 i40e_aqc_opc_set_phy_debug); 1476 1477 cmd->command_flags = cmd_flags; 1478 1479 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1480 1481 return status; 1482 } 1483 1484 /** 1485 * i40e_aq_add_vsi 1486 * @hw: pointer to the hw struct 1487 * @vsi_ctx: pointer to a vsi context struct 1488 * @cmd_details: pointer to command details structure or NULL 1489 * 1490 * Add a VSI context to the hardware. 1491 **/ 1492 int i40e_aq_add_vsi(struct i40e_hw *hw, 1493 struct i40e_vsi_context *vsi_ctx, 1494 struct i40e_asq_cmd_details *cmd_details) 1495 { 1496 struct i40e_aq_desc desc; 1497 struct i40e_aqc_add_get_update_vsi *cmd = 1498 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1499 struct i40e_aqc_add_get_update_vsi_completion *resp = 1500 (struct i40e_aqc_add_get_update_vsi_completion *) 1501 &desc.params.raw; 1502 int status; 1503 1504 i40e_fill_default_direct_cmd_desc(&desc, 1505 i40e_aqc_opc_add_vsi); 1506 1507 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1508 cmd->connection_type = vsi_ctx->connection_type; 1509 cmd->vf_id = vsi_ctx->vf_num; 1510 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1511 1512 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1513 1514 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1515 sizeof(vsi_ctx->info), 1516 cmd_details, true); 1517 1518 if (status) 1519 goto aq_add_vsi_exit; 1520 1521 vsi_ctx->seid = le16_to_cpu(resp->seid); 1522 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1523 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1524 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1525 1526 aq_add_vsi_exit: 1527 return status; 1528 } 1529 1530 /** 1531 * i40e_aq_set_default_vsi 1532 * @hw: pointer to the hw struct 1533 * @seid: vsi number 1534 * @cmd_details: pointer to command details structure or NULL 1535 **/ 1536 int i40e_aq_set_default_vsi(struct i40e_hw *hw, 1537 u16 seid, 1538 struct i40e_asq_cmd_details *cmd_details) 1539 { 1540 struct i40e_aq_desc desc; 1541 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1542 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1543 &desc.params.raw; 1544 int status; 1545 1546 i40e_fill_default_direct_cmd_desc(&desc, 1547 i40e_aqc_opc_set_vsi_promiscuous_modes); 1548 1549 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1550 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1551 cmd->seid = cpu_to_le16(seid); 1552 1553 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1554 1555 return status; 1556 } 1557 1558 /** 1559 * i40e_aq_clear_default_vsi 1560 * @hw: pointer to the hw struct 1561 * @seid: vsi number 1562 * @cmd_details: pointer to command details structure or NULL 1563 **/ 1564 int i40e_aq_clear_default_vsi(struct i40e_hw *hw, 1565 u16 seid, 1566 struct i40e_asq_cmd_details *cmd_details) 1567 { 1568 struct i40e_aq_desc desc; 1569 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1570 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1571 &desc.params.raw; 1572 int status; 1573 1574 i40e_fill_default_direct_cmd_desc(&desc, 1575 i40e_aqc_opc_set_vsi_promiscuous_modes); 1576 1577 cmd->promiscuous_flags = cpu_to_le16(0); 1578 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1579 cmd->seid = cpu_to_le16(seid); 1580 1581 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1582 1583 return status; 1584 } 1585 1586 /** 1587 * i40e_aq_set_vsi_unicast_promiscuous 1588 * @hw: pointer to the hw struct 1589 * @seid: vsi number 1590 * @set: set unicast promiscuous enable/disable 1591 * @cmd_details: pointer to command details structure or NULL 1592 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 1593 **/ 1594 int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1595 u16 seid, bool set, 1596 struct i40e_asq_cmd_details *cmd_details, 1597 bool rx_only_promisc) 1598 { 1599 struct i40e_aq_desc desc; 1600 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1601 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1602 u16 flags = 0; 1603 int status; 1604 1605 i40e_fill_default_direct_cmd_desc(&desc, 1606 i40e_aqc_opc_set_vsi_promiscuous_modes); 1607 1608 if (set) { 1609 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1610 if (rx_only_promisc && i40e_is_aq_api_ver_ge(hw, 1, 5)) 1611 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1612 } 1613 1614 cmd->promiscuous_flags = cpu_to_le16(flags); 1615 1616 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1617 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1618 cmd->valid_flags |= 1619 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 1620 1621 cmd->seid = cpu_to_le16(seid); 1622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1623 1624 return status; 1625 } 1626 1627 /** 1628 * i40e_aq_set_vsi_multicast_promiscuous 1629 * @hw: pointer to the hw struct 1630 * @seid: vsi number 1631 * @set: set multicast promiscuous enable/disable 1632 * @cmd_details: pointer to command details structure or NULL 1633 **/ 1634 int i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1635 u16 seid, bool set, 1636 struct i40e_asq_cmd_details *cmd_details) 1637 { 1638 struct i40e_aq_desc desc; 1639 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1640 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1641 u16 flags = 0; 1642 int status; 1643 1644 i40e_fill_default_direct_cmd_desc(&desc, 1645 i40e_aqc_opc_set_vsi_promiscuous_modes); 1646 1647 if (set) 1648 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1649 1650 cmd->promiscuous_flags = cpu_to_le16(flags); 1651 1652 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1653 1654 cmd->seid = cpu_to_le16(seid); 1655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1656 1657 return status; 1658 } 1659 1660 /** 1661 * i40e_aq_set_vsi_mc_promisc_on_vlan 1662 * @hw: pointer to the hw struct 1663 * @seid: vsi number 1664 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1665 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 1666 * @cmd_details: pointer to command details structure or NULL 1667 **/ 1668 int i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 1669 u16 seid, bool enable, 1670 u16 vid, 1671 struct i40e_asq_cmd_details *cmd_details) 1672 { 1673 struct i40e_aq_desc desc; 1674 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1675 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1676 u16 flags = 0; 1677 int status; 1678 1679 i40e_fill_default_direct_cmd_desc(&desc, 1680 i40e_aqc_opc_set_vsi_promiscuous_modes); 1681 1682 if (enable) 1683 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1684 1685 cmd->promiscuous_flags = cpu_to_le16(flags); 1686 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1687 cmd->seid = cpu_to_le16(seid); 1688 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1689 1690 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 1691 cmd_details, true); 1692 1693 return status; 1694 } 1695 1696 /** 1697 * i40e_aq_set_vsi_uc_promisc_on_vlan 1698 * @hw: pointer to the hw struct 1699 * @seid: vsi number 1700 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1701 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 1702 * @cmd_details: pointer to command details structure or NULL 1703 **/ 1704 int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 1705 u16 seid, bool enable, 1706 u16 vid, 1707 struct i40e_asq_cmd_details *cmd_details) 1708 { 1709 struct i40e_aq_desc desc; 1710 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1711 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1712 u16 flags = 0; 1713 int status; 1714 1715 i40e_fill_default_direct_cmd_desc(&desc, 1716 i40e_aqc_opc_set_vsi_promiscuous_modes); 1717 1718 if (enable) { 1719 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1720 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1721 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1722 } 1723 1724 cmd->promiscuous_flags = cpu_to_le16(flags); 1725 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1726 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1727 cmd->valid_flags |= 1728 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 1729 cmd->seid = cpu_to_le16(seid); 1730 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1731 1732 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 1733 cmd_details, true); 1734 1735 return status; 1736 } 1737 1738 /** 1739 * i40e_aq_set_vsi_bc_promisc_on_vlan 1740 * @hw: pointer to the hw struct 1741 * @seid: vsi number 1742 * @enable: set broadcast promiscuous enable/disable for a given VLAN 1743 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 1744 * @cmd_details: pointer to command details structure or NULL 1745 **/ 1746 int i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 1747 u16 seid, bool enable, u16 vid, 1748 struct i40e_asq_cmd_details *cmd_details) 1749 { 1750 struct i40e_aq_desc desc; 1751 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1752 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1753 u16 flags = 0; 1754 int status; 1755 1756 i40e_fill_default_direct_cmd_desc(&desc, 1757 i40e_aqc_opc_set_vsi_promiscuous_modes); 1758 1759 if (enable) 1760 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 1761 1762 cmd->promiscuous_flags = cpu_to_le16(flags); 1763 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1764 cmd->seid = cpu_to_le16(seid); 1765 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1766 1767 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1768 1769 return status; 1770 } 1771 1772 /** 1773 * i40e_aq_set_vsi_broadcast 1774 * @hw: pointer to the hw struct 1775 * @seid: vsi number 1776 * @set_filter: true to set filter, false to clear filter 1777 * @cmd_details: pointer to command details structure or NULL 1778 * 1779 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1780 **/ 1781 int i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1782 u16 seid, bool set_filter, 1783 struct i40e_asq_cmd_details *cmd_details) 1784 { 1785 struct i40e_aq_desc desc; 1786 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1787 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1788 int status; 1789 1790 i40e_fill_default_direct_cmd_desc(&desc, 1791 i40e_aqc_opc_set_vsi_promiscuous_modes); 1792 1793 if (set_filter) 1794 cmd->promiscuous_flags 1795 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1796 else 1797 cmd->promiscuous_flags 1798 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1799 1800 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1801 cmd->seid = cpu_to_le16(seid); 1802 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1803 1804 return status; 1805 } 1806 1807 /** 1808 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 1809 * @hw: pointer to the hw struct 1810 * @seid: vsi number 1811 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1812 * @cmd_details: pointer to command details structure or NULL 1813 **/ 1814 int i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 1815 u16 seid, bool enable, 1816 struct i40e_asq_cmd_details *cmd_details) 1817 { 1818 struct i40e_aq_desc desc; 1819 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1820 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1821 u16 flags = 0; 1822 int status; 1823 1824 i40e_fill_default_direct_cmd_desc(&desc, 1825 i40e_aqc_opc_set_vsi_promiscuous_modes); 1826 if (enable) 1827 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 1828 1829 cmd->promiscuous_flags = cpu_to_le16(flags); 1830 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 1831 cmd->seid = cpu_to_le16(seid); 1832 1833 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1834 1835 return status; 1836 } 1837 1838 /** 1839 * i40e_aq_get_vsi_params - get VSI configuration info 1840 * @hw: pointer to the hw struct 1841 * @vsi_ctx: pointer to a vsi context struct 1842 * @cmd_details: pointer to command details structure or NULL 1843 **/ 1844 int i40e_aq_get_vsi_params(struct i40e_hw *hw, 1845 struct i40e_vsi_context *vsi_ctx, 1846 struct i40e_asq_cmd_details *cmd_details) 1847 { 1848 struct i40e_aq_desc desc; 1849 struct i40e_aqc_add_get_update_vsi *cmd = 1850 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1851 struct i40e_aqc_add_get_update_vsi_completion *resp = 1852 (struct i40e_aqc_add_get_update_vsi_completion *) 1853 &desc.params.raw; 1854 int status; 1855 1856 i40e_fill_default_direct_cmd_desc(&desc, 1857 i40e_aqc_opc_get_vsi_parameters); 1858 1859 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1860 1861 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1862 1863 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1864 sizeof(vsi_ctx->info), NULL); 1865 1866 if (status) 1867 goto aq_get_vsi_params_exit; 1868 1869 vsi_ctx->seid = le16_to_cpu(resp->seid); 1870 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1871 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1872 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1873 1874 aq_get_vsi_params_exit: 1875 return status; 1876 } 1877 1878 /** 1879 * i40e_aq_update_vsi_params 1880 * @hw: pointer to the hw struct 1881 * @vsi_ctx: pointer to a vsi context struct 1882 * @cmd_details: pointer to command details structure or NULL 1883 * 1884 * Update a VSI context. 1885 **/ 1886 int i40e_aq_update_vsi_params(struct i40e_hw *hw, 1887 struct i40e_vsi_context *vsi_ctx, 1888 struct i40e_asq_cmd_details *cmd_details) 1889 { 1890 struct i40e_aq_desc desc; 1891 struct i40e_aqc_add_get_update_vsi *cmd = 1892 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1893 struct i40e_aqc_add_get_update_vsi_completion *resp = 1894 (struct i40e_aqc_add_get_update_vsi_completion *) 1895 &desc.params.raw; 1896 int status; 1897 1898 i40e_fill_default_direct_cmd_desc(&desc, 1899 i40e_aqc_opc_update_vsi_parameters); 1900 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1901 1902 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1903 1904 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1905 sizeof(vsi_ctx->info), 1906 cmd_details, true); 1907 1908 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1909 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1910 1911 return status; 1912 } 1913 1914 /** 1915 * i40e_aq_get_switch_config 1916 * @hw: pointer to the hardware structure 1917 * @buf: pointer to the result buffer 1918 * @buf_size: length of input buffer 1919 * @start_seid: seid to start for the report, 0 == beginning 1920 * @cmd_details: pointer to command details structure or NULL 1921 * 1922 * Fill the buf with switch configuration returned from AdminQ command 1923 **/ 1924 int i40e_aq_get_switch_config(struct i40e_hw *hw, 1925 struct i40e_aqc_get_switch_config_resp *buf, 1926 u16 buf_size, u16 *start_seid, 1927 struct i40e_asq_cmd_details *cmd_details) 1928 { 1929 struct i40e_aq_desc desc; 1930 struct i40e_aqc_switch_seid *scfg = 1931 (struct i40e_aqc_switch_seid *)&desc.params.raw; 1932 int status; 1933 1934 i40e_fill_default_direct_cmd_desc(&desc, 1935 i40e_aqc_opc_get_switch_config); 1936 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1937 if (buf_size > I40E_AQ_LARGE_BUF) 1938 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1939 scfg->seid = cpu_to_le16(*start_seid); 1940 1941 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1942 *start_seid = le16_to_cpu(scfg->seid); 1943 1944 return status; 1945 } 1946 1947 /** 1948 * i40e_aq_set_switch_config 1949 * @hw: pointer to the hardware structure 1950 * @flags: bit flag values to set 1951 * @mode: cloud filter mode 1952 * @valid_flags: which bit flags to set 1953 * @mode: cloud filter mode 1954 * @cmd_details: pointer to command details structure or NULL 1955 * 1956 * Set switch configuration bits 1957 **/ 1958 int i40e_aq_set_switch_config(struct i40e_hw *hw, 1959 u16 flags, 1960 u16 valid_flags, u8 mode, 1961 struct i40e_asq_cmd_details *cmd_details) 1962 { 1963 struct i40e_aq_desc desc; 1964 struct i40e_aqc_set_switch_config *scfg = 1965 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 1966 int status; 1967 1968 i40e_fill_default_direct_cmd_desc(&desc, 1969 i40e_aqc_opc_set_switch_config); 1970 scfg->flags = cpu_to_le16(flags); 1971 scfg->valid_flags = cpu_to_le16(valid_flags); 1972 scfg->mode = mode; 1973 if (test_bit(I40E_HW_CAP_802_1AD, hw->caps)) { 1974 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 1975 scfg->first_tag = cpu_to_le16(hw->first_tag); 1976 scfg->second_tag = cpu_to_le16(hw->second_tag); 1977 } 1978 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1979 1980 return status; 1981 } 1982 1983 /** 1984 * i40e_aq_get_firmware_version 1985 * @hw: pointer to the hw struct 1986 * @fw_major_version: firmware major version 1987 * @fw_minor_version: firmware minor version 1988 * @fw_build: firmware build number 1989 * @api_major_version: major queue version 1990 * @api_minor_version: minor queue version 1991 * @cmd_details: pointer to command details structure or NULL 1992 * 1993 * Get the firmware version from the admin queue commands 1994 **/ 1995 int i40e_aq_get_firmware_version(struct i40e_hw *hw, 1996 u16 *fw_major_version, u16 *fw_minor_version, 1997 u32 *fw_build, 1998 u16 *api_major_version, u16 *api_minor_version, 1999 struct i40e_asq_cmd_details *cmd_details) 2000 { 2001 struct i40e_aq_desc desc; 2002 struct i40e_aqc_get_version *resp = 2003 (struct i40e_aqc_get_version *)&desc.params.raw; 2004 int status; 2005 2006 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2007 2008 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2009 2010 if (!status) { 2011 if (fw_major_version) 2012 *fw_major_version = le16_to_cpu(resp->fw_major); 2013 if (fw_minor_version) 2014 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2015 if (fw_build) 2016 *fw_build = le32_to_cpu(resp->fw_build); 2017 if (api_major_version) 2018 *api_major_version = le16_to_cpu(resp->api_major); 2019 if (api_minor_version) 2020 *api_minor_version = le16_to_cpu(resp->api_minor); 2021 } 2022 2023 return status; 2024 } 2025 2026 /** 2027 * i40e_aq_send_driver_version 2028 * @hw: pointer to the hw struct 2029 * @dv: driver's major, minor version 2030 * @cmd_details: pointer to command details structure or NULL 2031 * 2032 * Send the driver version to the firmware 2033 **/ 2034 int i40e_aq_send_driver_version(struct i40e_hw *hw, 2035 struct i40e_driver_version *dv, 2036 struct i40e_asq_cmd_details *cmd_details) 2037 { 2038 struct i40e_aq_desc desc; 2039 struct i40e_aqc_driver_version *cmd = 2040 (struct i40e_aqc_driver_version *)&desc.params.raw; 2041 int status; 2042 u16 len; 2043 2044 if (dv == NULL) 2045 return -EINVAL; 2046 2047 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2048 2049 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2050 cmd->driver_major_ver = dv->major_version; 2051 cmd->driver_minor_ver = dv->minor_version; 2052 cmd->driver_build_ver = dv->build_version; 2053 cmd->driver_subbuild_ver = dv->subbuild_version; 2054 2055 len = 0; 2056 while (len < sizeof(dv->driver_string) && 2057 (dv->driver_string[len] < 0x80) && 2058 dv->driver_string[len]) 2059 len++; 2060 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2061 len, cmd_details); 2062 2063 return status; 2064 } 2065 2066 /** 2067 * i40e_get_link_status - get status of the HW network link 2068 * @hw: pointer to the hw struct 2069 * @link_up: pointer to bool (true/false = linkup/linkdown) 2070 * 2071 * Variable link_up true if link is up, false if link is down. 2072 * The variable link_up is invalid if returned value of status != 0 2073 * 2074 * Side effect: LinkStatusEvent reporting becomes enabled 2075 **/ 2076 int i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2077 { 2078 int status = 0; 2079 2080 if (hw->phy.get_link_info) { 2081 status = i40e_update_link_info(hw); 2082 2083 if (status) 2084 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2085 status); 2086 } 2087 2088 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2089 2090 return status; 2091 } 2092 2093 /** 2094 * i40e_update_link_info - update status of the HW network link 2095 * @hw: pointer to the hw struct 2096 **/ 2097 noinline_for_stack int i40e_update_link_info(struct i40e_hw *hw) 2098 { 2099 struct i40e_aq_get_phy_abilities_resp abilities; 2100 int status = 0; 2101 2102 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2103 if (status) 2104 return status; 2105 2106 /* extra checking needed to ensure link info to user is timely */ 2107 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2108 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2109 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2110 status = i40e_aq_get_phy_capabilities(hw, false, false, 2111 &abilities, NULL); 2112 if (status) 2113 return status; 2114 2115 if (abilities.fec_cfg_curr_mod_ext_info & 2116 I40E_AQ_ENABLE_FEC_AUTO) 2117 hw->phy.link_info.req_fec_info = 2118 (I40E_AQ_REQUEST_FEC_KR | 2119 I40E_AQ_REQUEST_FEC_RS); 2120 else 2121 hw->phy.link_info.req_fec_info = 2122 abilities.fec_cfg_curr_mod_ext_info & 2123 (I40E_AQ_REQUEST_FEC_KR | 2124 I40E_AQ_REQUEST_FEC_RS); 2125 2126 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2127 sizeof(hw->phy.link_info.module_type)); 2128 } 2129 2130 return status; 2131 } 2132 2133 /** 2134 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2135 * @hw: pointer to the hw struct 2136 * @uplink_seid: the MAC or other gizmo SEID 2137 * @downlink_seid: the VSI SEID 2138 * @enabled_tc: bitmap of TCs to be enabled 2139 * @default_port: true for default port VSI, false for control port 2140 * @veb_seid: pointer to where to put the resulting VEB SEID 2141 * @enable_stats: true to turn on VEB stats 2142 * @cmd_details: pointer to command details structure or NULL 2143 * 2144 * This asks the FW to add a VEB between the uplink and downlink 2145 * elements. If the uplink SEID is 0, this will be a floating VEB. 2146 **/ 2147 int i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2148 u16 downlink_seid, u8 enabled_tc, 2149 bool default_port, u16 *veb_seid, 2150 bool enable_stats, 2151 struct i40e_asq_cmd_details *cmd_details) 2152 { 2153 struct i40e_aq_desc desc; 2154 struct i40e_aqc_add_veb *cmd = 2155 (struct i40e_aqc_add_veb *)&desc.params.raw; 2156 struct i40e_aqc_add_veb_completion *resp = 2157 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2158 u16 veb_flags = 0; 2159 int status; 2160 2161 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2162 if (!!uplink_seid != !!downlink_seid) 2163 return -EINVAL; 2164 2165 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2166 2167 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2168 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2169 cmd->enable_tcs = enabled_tc; 2170 if (!uplink_seid) 2171 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2172 if (default_port) 2173 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2174 else 2175 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2176 2177 /* reverse logic here: set the bitflag to disable the stats */ 2178 if (!enable_stats) 2179 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2180 2181 cmd->veb_flags = cpu_to_le16(veb_flags); 2182 2183 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2184 2185 if (!status && veb_seid) 2186 *veb_seid = le16_to_cpu(resp->veb_seid); 2187 2188 return status; 2189 } 2190 2191 /** 2192 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2193 * @hw: pointer to the hw struct 2194 * @veb_seid: the SEID of the VEB to query 2195 * @switch_id: the uplink switch id 2196 * @floating: set to true if the VEB is floating 2197 * @statistic_index: index of the stats counter block for this VEB 2198 * @vebs_used: number of VEB's used by function 2199 * @vebs_free: total VEB's not reserved by any function 2200 * @cmd_details: pointer to command details structure or NULL 2201 * 2202 * This retrieves the parameters for a particular VEB, specified by 2203 * uplink_seid, and returns them to the caller. 2204 **/ 2205 int i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2206 u16 veb_seid, u16 *switch_id, 2207 bool *floating, u16 *statistic_index, 2208 u16 *vebs_used, u16 *vebs_free, 2209 struct i40e_asq_cmd_details *cmd_details) 2210 { 2211 struct i40e_aq_desc desc; 2212 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2213 (struct i40e_aqc_get_veb_parameters_completion *) 2214 &desc.params.raw; 2215 int status; 2216 2217 if (veb_seid == 0) 2218 return -EINVAL; 2219 2220 i40e_fill_default_direct_cmd_desc(&desc, 2221 i40e_aqc_opc_get_veb_parameters); 2222 cmd_resp->seid = cpu_to_le16(veb_seid); 2223 2224 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2225 if (status) 2226 goto get_veb_exit; 2227 2228 if (switch_id) 2229 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2230 if (statistic_index) 2231 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2232 if (vebs_used) 2233 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2234 if (vebs_free) 2235 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2236 if (floating) { 2237 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2238 2239 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2240 *floating = true; 2241 else 2242 *floating = false; 2243 } 2244 2245 get_veb_exit: 2246 return status; 2247 } 2248 2249 /** 2250 * i40e_prepare_add_macvlan 2251 * @mv_list: list of macvlans to be added 2252 * @desc: pointer to AQ descriptor structure 2253 * @count: length of the list 2254 * @seid: VSI for the mac address 2255 * 2256 * Internal helper function that prepares the add macvlan request 2257 * and returns the buffer size. 2258 **/ 2259 static u16 2260 i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list, 2261 struct i40e_aq_desc *desc, u16 count, u16 seid) 2262 { 2263 struct i40e_aqc_macvlan *cmd = 2264 (struct i40e_aqc_macvlan *)&desc->params.raw; 2265 u16 buf_size; 2266 int i; 2267 2268 buf_size = count * sizeof(*mv_list); 2269 2270 /* prep the rest of the request */ 2271 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan); 2272 cmd->num_addresses = cpu_to_le16(count); 2273 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2274 cmd->seid[1] = 0; 2275 cmd->seid[2] = 0; 2276 2277 for (i = 0; i < count; i++) 2278 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2279 mv_list[i].flags |= 2280 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2281 2282 desc->flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2283 if (buf_size > I40E_AQ_LARGE_BUF) 2284 desc->flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2285 2286 return buf_size; 2287 } 2288 2289 /** 2290 * i40e_aq_add_macvlan 2291 * @hw: pointer to the hw struct 2292 * @seid: VSI for the mac address 2293 * @mv_list: list of macvlans to be added 2294 * @count: length of the list 2295 * @cmd_details: pointer to command details structure or NULL 2296 * 2297 * Add MAC/VLAN addresses to the HW filtering 2298 **/ 2299 int 2300 i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2301 struct i40e_aqc_add_macvlan_element_data *mv_list, 2302 u16 count, struct i40e_asq_cmd_details *cmd_details) 2303 { 2304 struct i40e_aq_desc desc; 2305 u16 buf_size; 2306 2307 if (count == 0 || !mv_list || !hw) 2308 return -EINVAL; 2309 2310 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 2311 2312 return i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2313 cmd_details, true); 2314 } 2315 2316 /** 2317 * i40e_aq_add_macvlan_v2 2318 * @hw: pointer to the hw struct 2319 * @seid: VSI for the mac address 2320 * @mv_list: list of macvlans to be added 2321 * @count: length of the list 2322 * @cmd_details: pointer to command details structure or NULL 2323 * @aq_status: pointer to Admin Queue status return value 2324 * 2325 * Add MAC/VLAN addresses to the HW filtering. 2326 * The _v2 version returns the last Admin Queue status in aq_status 2327 * to avoid race conditions in access to hw->aq.asq_last_status. 2328 * It also calls _v2 versions of asq_send_command functions to 2329 * get the aq_status on the stack. 2330 **/ 2331 int 2332 i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid, 2333 struct i40e_aqc_add_macvlan_element_data *mv_list, 2334 u16 count, struct i40e_asq_cmd_details *cmd_details, 2335 enum i40e_admin_queue_err *aq_status) 2336 { 2337 struct i40e_aq_desc desc; 2338 u16 buf_size; 2339 2340 if (count == 0 || !mv_list || !hw) 2341 return -EINVAL; 2342 2343 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 2344 2345 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2346 cmd_details, true, aq_status); 2347 } 2348 2349 /** 2350 * i40e_aq_remove_macvlan 2351 * @hw: pointer to the hw struct 2352 * @seid: VSI for the mac address 2353 * @mv_list: list of macvlans to be removed 2354 * @count: length of the list 2355 * @cmd_details: pointer to command details structure or NULL 2356 * 2357 * Remove MAC/VLAN addresses from the HW filtering 2358 **/ 2359 int 2360 i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2361 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2362 u16 count, struct i40e_asq_cmd_details *cmd_details) 2363 { 2364 struct i40e_aq_desc desc; 2365 struct i40e_aqc_macvlan *cmd = 2366 (struct i40e_aqc_macvlan *)&desc.params.raw; 2367 u16 buf_size; 2368 int status; 2369 2370 if (count == 0 || !mv_list || !hw) 2371 return -EINVAL; 2372 2373 buf_size = count * sizeof(*mv_list); 2374 2375 /* prep the rest of the request */ 2376 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2377 cmd->num_addresses = cpu_to_le16(count); 2378 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2379 cmd->seid[1] = 0; 2380 cmd->seid[2] = 0; 2381 2382 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2383 if (buf_size > I40E_AQ_LARGE_BUF) 2384 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2385 2386 status = i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2387 cmd_details, true); 2388 2389 return status; 2390 } 2391 2392 /** 2393 * i40e_aq_remove_macvlan_v2 2394 * @hw: pointer to the hw struct 2395 * @seid: VSI for the mac address 2396 * @mv_list: list of macvlans to be removed 2397 * @count: length of the list 2398 * @cmd_details: pointer to command details structure or NULL 2399 * @aq_status: pointer to Admin Queue status return value 2400 * 2401 * Remove MAC/VLAN addresses from the HW filtering. 2402 * The _v2 version returns the last Admin Queue status in aq_status 2403 * to avoid race conditions in access to hw->aq.asq_last_status. 2404 * It also calls _v2 versions of asq_send_command functions to 2405 * get the aq_status on the stack. 2406 **/ 2407 int 2408 i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid, 2409 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2410 u16 count, struct i40e_asq_cmd_details *cmd_details, 2411 enum i40e_admin_queue_err *aq_status) 2412 { 2413 struct i40e_aqc_macvlan *cmd; 2414 struct i40e_aq_desc desc; 2415 u16 buf_size; 2416 2417 if (count == 0 || !mv_list || !hw) 2418 return -EINVAL; 2419 2420 buf_size = count * sizeof(*mv_list); 2421 2422 /* prep the rest of the request */ 2423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2424 cmd = (struct i40e_aqc_macvlan *)&desc.params.raw; 2425 cmd->num_addresses = cpu_to_le16(count); 2426 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2427 cmd->seid[1] = 0; 2428 cmd->seid[2] = 0; 2429 2430 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2431 if (buf_size > I40E_AQ_LARGE_BUF) 2432 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2433 2434 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2435 cmd_details, true, aq_status); 2436 } 2437 2438 /** 2439 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2440 * @hw: pointer to the hw struct 2441 * @opcode: AQ opcode for add or delete mirror rule 2442 * @sw_seid: Switch SEID (to which rule refers) 2443 * @rule_type: Rule Type (ingress/egress/VLAN) 2444 * @id: Destination VSI SEID or Rule ID 2445 * @count: length of the list 2446 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2447 * @cmd_details: pointer to command details structure or NULL 2448 * @rule_id: Rule ID returned from FW 2449 * @rules_used: Number of rules used in internal switch 2450 * @rules_free: Number of rules free in internal switch 2451 * 2452 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2453 * VEBs/VEPA elements only 2454 **/ 2455 static int i40e_mirrorrule_op(struct i40e_hw *hw, 2456 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2457 u16 count, __le16 *mr_list, 2458 struct i40e_asq_cmd_details *cmd_details, 2459 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2460 { 2461 struct i40e_aq_desc desc; 2462 struct i40e_aqc_add_delete_mirror_rule *cmd = 2463 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2464 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2465 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2466 u16 buf_size; 2467 int status; 2468 2469 buf_size = count * sizeof(*mr_list); 2470 2471 /* prep the rest of the request */ 2472 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2473 cmd->seid = cpu_to_le16(sw_seid); 2474 cmd->rule_type = cpu_to_le16(rule_type & 2475 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2476 cmd->num_entries = cpu_to_le16(count); 2477 /* Dest VSI for add, rule_id for delete */ 2478 cmd->destination = cpu_to_le16(id); 2479 if (mr_list) { 2480 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2481 I40E_AQ_FLAG_RD)); 2482 if (buf_size > I40E_AQ_LARGE_BUF) 2483 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2484 } 2485 2486 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2487 cmd_details); 2488 if (!status || 2489 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2490 if (rule_id) 2491 *rule_id = le16_to_cpu(resp->rule_id); 2492 if (rules_used) 2493 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2494 if (rules_free) 2495 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2496 } 2497 return status; 2498 } 2499 2500 /** 2501 * i40e_aq_add_mirrorrule - add a mirror rule 2502 * @hw: pointer to the hw struct 2503 * @sw_seid: Switch SEID (to which rule refers) 2504 * @rule_type: Rule Type (ingress/egress/VLAN) 2505 * @dest_vsi: SEID of VSI to which packets will be mirrored 2506 * @count: length of the list 2507 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2508 * @cmd_details: pointer to command details structure or NULL 2509 * @rule_id: Rule ID returned from FW 2510 * @rules_used: Number of rules used in internal switch 2511 * @rules_free: Number of rules free in internal switch 2512 * 2513 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2514 **/ 2515 int i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2516 u16 rule_type, u16 dest_vsi, u16 count, 2517 __le16 *mr_list, 2518 struct i40e_asq_cmd_details *cmd_details, 2519 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2520 { 2521 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2522 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2523 if (count == 0 || !mr_list) 2524 return -EINVAL; 2525 } 2526 2527 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2528 rule_type, dest_vsi, count, mr_list, 2529 cmd_details, rule_id, rules_used, rules_free); 2530 } 2531 2532 /** 2533 * i40e_aq_delete_mirrorrule - delete a mirror rule 2534 * @hw: pointer to the hw struct 2535 * @sw_seid: Switch SEID (to which rule refers) 2536 * @rule_type: Rule Type (ingress/egress/VLAN) 2537 * @count: length of the list 2538 * @rule_id: Rule ID that is returned in the receive desc as part of 2539 * add_mirrorrule. 2540 * @mr_list: list of mirrored VLAN IDs to be removed 2541 * @cmd_details: pointer to command details structure or NULL 2542 * @rules_used: Number of rules used in internal switch 2543 * @rules_free: Number of rules free in internal switch 2544 * 2545 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2546 **/ 2547 int i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2548 u16 rule_type, u16 rule_id, u16 count, 2549 __le16 *mr_list, 2550 struct i40e_asq_cmd_details *cmd_details, 2551 u16 *rules_used, u16 *rules_free) 2552 { 2553 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2554 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2555 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2556 * mirroring. For other rule_type, count and rule_type should 2557 * not matter. 2558 */ 2559 if (count == 0 || !mr_list) 2560 return -EINVAL; 2561 } 2562 2563 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2564 rule_type, rule_id, count, mr_list, 2565 cmd_details, NULL, rules_used, rules_free); 2566 } 2567 2568 /** 2569 * i40e_aq_send_msg_to_vf 2570 * @hw: pointer to the hardware structure 2571 * @vfid: VF id to send msg 2572 * @v_opcode: opcodes for VF-PF communication 2573 * @v_retval: return error code 2574 * @msg: pointer to the msg buffer 2575 * @msglen: msg length 2576 * @cmd_details: pointer to command details 2577 * 2578 * send msg to vf 2579 **/ 2580 int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2581 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2582 struct i40e_asq_cmd_details *cmd_details) 2583 { 2584 struct i40e_aq_desc desc; 2585 struct i40e_aqc_pf_vf_message *cmd = 2586 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2587 int status; 2588 2589 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2590 cmd->id = cpu_to_le32(vfid); 2591 desc.cookie_high = cpu_to_le32(v_opcode); 2592 desc.cookie_low = cpu_to_le32(v_retval); 2593 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2594 if (msglen) { 2595 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2596 I40E_AQ_FLAG_RD)); 2597 if (msglen > I40E_AQ_LARGE_BUF) 2598 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2599 desc.datalen = cpu_to_le16(msglen); 2600 } 2601 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2602 2603 return status; 2604 } 2605 2606 /** 2607 * i40e_aq_debug_read_register 2608 * @hw: pointer to the hw struct 2609 * @reg_addr: register address 2610 * @reg_val: register value 2611 * @cmd_details: pointer to command details structure or NULL 2612 * 2613 * Read the register using the admin queue commands 2614 **/ 2615 int i40e_aq_debug_read_register(struct i40e_hw *hw, 2616 u32 reg_addr, u64 *reg_val, 2617 struct i40e_asq_cmd_details *cmd_details) 2618 { 2619 struct i40e_aq_desc desc; 2620 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2621 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2622 int status; 2623 2624 if (reg_val == NULL) 2625 return -EINVAL; 2626 2627 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2628 2629 cmd_resp->address = cpu_to_le32(reg_addr); 2630 2631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2632 2633 if (!status) { 2634 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2635 (u64)le32_to_cpu(cmd_resp->value_low); 2636 } 2637 2638 return status; 2639 } 2640 2641 /** 2642 * i40e_aq_debug_write_register 2643 * @hw: pointer to the hw struct 2644 * @reg_addr: register address 2645 * @reg_val: register value 2646 * @cmd_details: pointer to command details structure or NULL 2647 * 2648 * Write to a register using the admin queue commands 2649 **/ 2650 int i40e_aq_debug_write_register(struct i40e_hw *hw, 2651 u32 reg_addr, u64 reg_val, 2652 struct i40e_asq_cmd_details *cmd_details) 2653 { 2654 struct i40e_aq_desc desc; 2655 struct i40e_aqc_debug_reg_read_write *cmd = 2656 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2657 int status; 2658 2659 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2660 2661 cmd->address = cpu_to_le32(reg_addr); 2662 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2663 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2664 2665 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2666 2667 return status; 2668 } 2669 2670 /** 2671 * i40e_aq_request_resource 2672 * @hw: pointer to the hw struct 2673 * @resource: resource id 2674 * @access: access type 2675 * @sdp_number: resource number 2676 * @timeout: the maximum time in ms that the driver may hold the resource 2677 * @cmd_details: pointer to command details structure or NULL 2678 * 2679 * requests common resource using the admin queue commands 2680 **/ 2681 int i40e_aq_request_resource(struct i40e_hw *hw, 2682 enum i40e_aq_resources_ids resource, 2683 enum i40e_aq_resource_access_type access, 2684 u8 sdp_number, u64 *timeout, 2685 struct i40e_asq_cmd_details *cmd_details) 2686 { 2687 struct i40e_aq_desc desc; 2688 struct i40e_aqc_request_resource *cmd_resp = 2689 (struct i40e_aqc_request_resource *)&desc.params.raw; 2690 int status; 2691 2692 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2693 2694 cmd_resp->resource_id = cpu_to_le16(resource); 2695 cmd_resp->access_type = cpu_to_le16(access); 2696 cmd_resp->resource_number = cpu_to_le32(sdp_number); 2697 2698 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2699 /* The completion specifies the maximum time in ms that the driver 2700 * may hold the resource in the Timeout field. 2701 * If the resource is held by someone else, the command completes with 2702 * busy return value and the timeout field indicates the maximum time 2703 * the current owner of the resource has to free it. 2704 */ 2705 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2706 *timeout = le32_to_cpu(cmd_resp->timeout); 2707 2708 return status; 2709 } 2710 2711 /** 2712 * i40e_aq_release_resource 2713 * @hw: pointer to the hw struct 2714 * @resource: resource id 2715 * @sdp_number: resource number 2716 * @cmd_details: pointer to command details structure or NULL 2717 * 2718 * release common resource using the admin queue commands 2719 **/ 2720 int i40e_aq_release_resource(struct i40e_hw *hw, 2721 enum i40e_aq_resources_ids resource, 2722 u8 sdp_number, 2723 struct i40e_asq_cmd_details *cmd_details) 2724 { 2725 struct i40e_aq_desc desc; 2726 struct i40e_aqc_request_resource *cmd = 2727 (struct i40e_aqc_request_resource *)&desc.params.raw; 2728 int status; 2729 2730 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2731 2732 cmd->resource_id = cpu_to_le16(resource); 2733 cmd->resource_number = cpu_to_le32(sdp_number); 2734 2735 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2736 2737 return status; 2738 } 2739 2740 /** 2741 * i40e_aq_read_nvm 2742 * @hw: pointer to the hw struct 2743 * @module_pointer: module pointer location in words from the NVM beginning 2744 * @offset: byte offset from the module beginning 2745 * @length: length of the section to be read (in bytes from the offset) 2746 * @data: command buffer (size [bytes] = length) 2747 * @last_command: tells if this is the last command in a series 2748 * @cmd_details: pointer to command details structure or NULL 2749 * 2750 * Read the NVM using the admin queue commands 2751 **/ 2752 int i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2753 u32 offset, u16 length, void *data, 2754 bool last_command, 2755 struct i40e_asq_cmd_details *cmd_details) 2756 { 2757 struct i40e_aq_desc desc; 2758 struct i40e_aqc_nvm_update *cmd = 2759 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2760 int status; 2761 2762 /* In offset the highest byte must be zeroed. */ 2763 if (offset & 0xFF000000) { 2764 status = -EINVAL; 2765 goto i40e_aq_read_nvm_exit; 2766 } 2767 2768 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2769 2770 /* If this is the last command in a series, set the proper flag. */ 2771 if (last_command) 2772 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2773 cmd->module_pointer = module_pointer; 2774 cmd->offset = cpu_to_le32(offset); 2775 cmd->length = cpu_to_le16(length); 2776 2777 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2778 if (length > I40E_AQ_LARGE_BUF) 2779 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2780 2781 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2782 2783 i40e_aq_read_nvm_exit: 2784 return status; 2785 } 2786 2787 /** 2788 * i40e_aq_erase_nvm 2789 * @hw: pointer to the hw struct 2790 * @module_pointer: module pointer location in words from the NVM beginning 2791 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2792 * @length: length of the section to be erased (expressed in 4 KB) 2793 * @last_command: tells if this is the last command in a series 2794 * @cmd_details: pointer to command details structure or NULL 2795 * 2796 * Erase the NVM sector using the admin queue commands 2797 **/ 2798 int i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2799 u32 offset, u16 length, bool last_command, 2800 struct i40e_asq_cmd_details *cmd_details) 2801 { 2802 struct i40e_aq_desc desc; 2803 struct i40e_aqc_nvm_update *cmd = 2804 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2805 int status; 2806 2807 /* In offset the highest byte must be zeroed. */ 2808 if (offset & 0xFF000000) { 2809 status = -EINVAL; 2810 goto i40e_aq_erase_nvm_exit; 2811 } 2812 2813 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2814 2815 /* If this is the last command in a series, set the proper flag. */ 2816 if (last_command) 2817 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2818 cmd->module_pointer = module_pointer; 2819 cmd->offset = cpu_to_le32(offset); 2820 cmd->length = cpu_to_le16(length); 2821 2822 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2823 2824 i40e_aq_erase_nvm_exit: 2825 return status; 2826 } 2827 2828 /** 2829 * i40e_parse_discover_capabilities 2830 * @hw: pointer to the hw struct 2831 * @buff: pointer to a buffer containing device/function capability records 2832 * @cap_count: number of capability records in the list 2833 * @list_type_opc: type of capabilities list to parse 2834 * 2835 * Parse the device/function capabilities list. 2836 **/ 2837 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2838 u32 cap_count, 2839 enum i40e_admin_queue_opc list_type_opc) 2840 { 2841 struct i40e_aqc_list_capabilities_element_resp *cap; 2842 u32 valid_functions, num_functions; 2843 u32 number, logical_id, phys_id; 2844 struct i40e_hw_capabilities *p; 2845 u16 id, ocp_cfg_word0; 2846 u8 major_rev; 2847 int status; 2848 u32 i = 0; 2849 2850 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2851 2852 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2853 p = &hw->dev_caps; 2854 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2855 p = &hw->func_caps; 2856 else 2857 return; 2858 2859 for (i = 0; i < cap_count; i++, cap++) { 2860 id = le16_to_cpu(cap->id); 2861 number = le32_to_cpu(cap->number); 2862 logical_id = le32_to_cpu(cap->logical_id); 2863 phys_id = le32_to_cpu(cap->phys_id); 2864 major_rev = cap->major_rev; 2865 2866 switch (id) { 2867 case I40E_AQ_CAP_ID_SWITCH_MODE: 2868 p->switch_mode = number; 2869 break; 2870 case I40E_AQ_CAP_ID_MNG_MODE: 2871 p->management_mode = number; 2872 if (major_rev > 1) { 2873 p->mng_protocols_over_mctp = logical_id; 2874 i40e_debug(hw, I40E_DEBUG_INIT, 2875 "HW Capability: Protocols over MCTP = %d\n", 2876 p->mng_protocols_over_mctp); 2877 } else { 2878 p->mng_protocols_over_mctp = 0; 2879 } 2880 break; 2881 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 2882 p->npar_enable = number; 2883 break; 2884 case I40E_AQ_CAP_ID_OS2BMC_CAP: 2885 p->os2bmc = number; 2886 break; 2887 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 2888 p->valid_functions = number; 2889 break; 2890 case I40E_AQ_CAP_ID_SRIOV: 2891 if (number == 1) 2892 p->sr_iov_1_1 = true; 2893 break; 2894 case I40E_AQ_CAP_ID_VF: 2895 p->num_vfs = number; 2896 p->vf_base_id = logical_id; 2897 break; 2898 case I40E_AQ_CAP_ID_VMDQ: 2899 if (number == 1) 2900 p->vmdq = true; 2901 break; 2902 case I40E_AQ_CAP_ID_8021QBG: 2903 if (number == 1) 2904 p->evb_802_1_qbg = true; 2905 break; 2906 case I40E_AQ_CAP_ID_8021QBR: 2907 if (number == 1) 2908 p->evb_802_1_qbh = true; 2909 break; 2910 case I40E_AQ_CAP_ID_VSI: 2911 p->num_vsis = number; 2912 break; 2913 case I40E_AQ_CAP_ID_DCB: 2914 if (number == 1) { 2915 p->dcb = true; 2916 p->enabled_tcmap = logical_id; 2917 p->maxtc = phys_id; 2918 } 2919 break; 2920 case I40E_AQ_CAP_ID_FCOE: 2921 if (number == 1) 2922 p->fcoe = true; 2923 break; 2924 case I40E_AQ_CAP_ID_ISCSI: 2925 if (number == 1) 2926 p->iscsi = true; 2927 break; 2928 case I40E_AQ_CAP_ID_RSS: 2929 p->rss = true; 2930 p->rss_table_size = number; 2931 p->rss_table_entry_width = logical_id; 2932 break; 2933 case I40E_AQ_CAP_ID_RXQ: 2934 p->num_rx_qp = number; 2935 p->base_queue = phys_id; 2936 break; 2937 case I40E_AQ_CAP_ID_TXQ: 2938 p->num_tx_qp = number; 2939 p->base_queue = phys_id; 2940 break; 2941 case I40E_AQ_CAP_ID_MSIX: 2942 p->num_msix_vectors = number; 2943 i40e_debug(hw, I40E_DEBUG_INIT, 2944 "HW Capability: MSIX vector count = %d\n", 2945 p->num_msix_vectors); 2946 break; 2947 case I40E_AQ_CAP_ID_VF_MSIX: 2948 p->num_msix_vectors_vf = number; 2949 break; 2950 case I40E_AQ_CAP_ID_FLEX10: 2951 if (major_rev == 1) { 2952 if (number == 1) { 2953 p->flex10_enable = true; 2954 p->flex10_capable = true; 2955 } 2956 } else { 2957 /* Capability revision >= 2 */ 2958 if (number & 1) 2959 p->flex10_enable = true; 2960 if (number & 2) 2961 p->flex10_capable = true; 2962 } 2963 p->flex10_mode = logical_id; 2964 p->flex10_status = phys_id; 2965 break; 2966 case I40E_AQ_CAP_ID_CEM: 2967 if (number == 1) 2968 p->mgmt_cem = true; 2969 break; 2970 case I40E_AQ_CAP_ID_IWARP: 2971 if (number == 1) 2972 p->iwarp = true; 2973 break; 2974 case I40E_AQ_CAP_ID_LED: 2975 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2976 p->led[phys_id] = true; 2977 break; 2978 case I40E_AQ_CAP_ID_SDP: 2979 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2980 p->sdp[phys_id] = true; 2981 break; 2982 case I40E_AQ_CAP_ID_MDIO: 2983 if (number == 1) { 2984 p->mdio_port_num = phys_id; 2985 p->mdio_port_mode = logical_id; 2986 } 2987 break; 2988 case I40E_AQ_CAP_ID_1588: 2989 if (number == 1) 2990 p->ieee_1588 = true; 2991 break; 2992 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 2993 p->fd = true; 2994 p->fd_filters_guaranteed = number; 2995 p->fd_filters_best_effort = logical_id; 2996 break; 2997 case I40E_AQ_CAP_ID_WSR_PROT: 2998 p->wr_csr_prot = (u64)number; 2999 p->wr_csr_prot |= (u64)logical_id << 32; 3000 break; 3001 case I40E_AQ_CAP_ID_NVM_MGMT: 3002 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3003 p->sec_rev_disabled = true; 3004 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3005 p->update_disabled = true; 3006 break; 3007 default: 3008 break; 3009 } 3010 } 3011 3012 if (p->fcoe) 3013 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3014 3015 /* Software override ensuring FCoE is disabled if npar or mfp 3016 * mode because it is not supported in these modes. 3017 */ 3018 if (p->npar_enable || p->flex10_enable) 3019 p->fcoe = false; 3020 3021 /* count the enabled ports (aka the "not disabled" ports) */ 3022 hw->num_ports = 0; 3023 for (i = 0; i < 4; i++) { 3024 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3025 u64 port_cfg = 0; 3026 3027 /* use AQ read to get the physical register offset instead 3028 * of the port relative offset 3029 */ 3030 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3031 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3032 hw->num_ports++; 3033 } 3034 3035 /* OCP cards case: if a mezz is removed the Ethernet port is at 3036 * disabled state in PRTGEN_CNF register. Additional NVM read is 3037 * needed in order to check if we are dealing with OCP card. 3038 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 3039 * physical ports results in wrong partition id calculation and thus 3040 * not supporting WoL. 3041 */ 3042 if (hw->mac.type == I40E_MAC_X722) { 3043 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) { 3044 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 3045 2 * I40E_SR_OCP_CFG_WORD0, 3046 sizeof(ocp_cfg_word0), 3047 &ocp_cfg_word0, true, NULL); 3048 if (!status && 3049 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 3050 hw->num_ports = 4; 3051 i40e_release_nvm(hw); 3052 } 3053 } 3054 3055 valid_functions = p->valid_functions; 3056 num_functions = 0; 3057 while (valid_functions) { 3058 if (valid_functions & 1) 3059 num_functions++; 3060 valid_functions >>= 1; 3061 } 3062 3063 /* partition id is 1-based, and functions are evenly spread 3064 * across the ports as partitions 3065 */ 3066 if (hw->num_ports != 0) { 3067 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3068 hw->num_partitions = num_functions / hw->num_ports; 3069 } 3070 3071 /* additional HW specific goodies that might 3072 * someday be HW version specific 3073 */ 3074 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3075 } 3076 3077 /** 3078 * i40e_aq_discover_capabilities 3079 * @hw: pointer to the hw struct 3080 * @buff: a virtual buffer to hold the capabilities 3081 * @buff_size: Size of the virtual buffer 3082 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3083 * @list_type_opc: capabilities type to discover - pass in the command opcode 3084 * @cmd_details: pointer to command details structure or NULL 3085 * 3086 * Get the device capabilities descriptions from the firmware 3087 **/ 3088 int i40e_aq_discover_capabilities(struct i40e_hw *hw, 3089 void *buff, u16 buff_size, u16 *data_size, 3090 enum i40e_admin_queue_opc list_type_opc, 3091 struct i40e_asq_cmd_details *cmd_details) 3092 { 3093 struct i40e_aqc_list_capabilites *cmd; 3094 struct i40e_aq_desc desc; 3095 int status = 0; 3096 3097 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3098 3099 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3100 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3101 status = -EINVAL; 3102 goto exit; 3103 } 3104 3105 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3106 3107 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3108 if (buff_size > I40E_AQ_LARGE_BUF) 3109 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3110 3111 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3112 *data_size = le16_to_cpu(desc.datalen); 3113 3114 if (status) 3115 goto exit; 3116 3117 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3118 list_type_opc); 3119 3120 exit: 3121 return status; 3122 } 3123 3124 /** 3125 * i40e_aq_update_nvm 3126 * @hw: pointer to the hw struct 3127 * @module_pointer: module pointer location in words from the NVM beginning 3128 * @offset: byte offset from the module beginning 3129 * @length: length of the section to be written (in bytes from the offset) 3130 * @data: command buffer (size [bytes] = length) 3131 * @last_command: tells if this is the last command in a series 3132 * @preservation_flags: Preservation mode flags 3133 * @cmd_details: pointer to command details structure or NULL 3134 * 3135 * Update the NVM using the admin queue commands 3136 **/ 3137 int i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3138 u32 offset, u16 length, void *data, 3139 bool last_command, u8 preservation_flags, 3140 struct i40e_asq_cmd_details *cmd_details) 3141 { 3142 struct i40e_aq_desc desc; 3143 struct i40e_aqc_nvm_update *cmd = 3144 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3145 int status; 3146 3147 /* In offset the highest byte must be zeroed. */ 3148 if (offset & 0xFF000000) { 3149 status = -EINVAL; 3150 goto i40e_aq_update_nvm_exit; 3151 } 3152 3153 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3154 3155 /* If this is the last command in a series, set the proper flag. */ 3156 if (last_command) 3157 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3158 if (hw->mac.type == I40E_MAC_X722) { 3159 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 3160 cmd->command_flags |= 3161 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 3162 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3163 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 3164 cmd->command_flags |= 3165 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 3166 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3167 } 3168 cmd->module_pointer = module_pointer; 3169 cmd->offset = cpu_to_le32(offset); 3170 cmd->length = cpu_to_le16(length); 3171 3172 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3173 if (length > I40E_AQ_LARGE_BUF) 3174 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3175 3176 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3177 3178 i40e_aq_update_nvm_exit: 3179 return status; 3180 } 3181 3182 /** 3183 * i40e_aq_rearrange_nvm 3184 * @hw: pointer to the hw struct 3185 * @rearrange_nvm: defines direction of rearrangement 3186 * @cmd_details: pointer to command details structure or NULL 3187 * 3188 * Rearrange NVM structure, available only for transition FW 3189 **/ 3190 int i40e_aq_rearrange_nvm(struct i40e_hw *hw, 3191 u8 rearrange_nvm, 3192 struct i40e_asq_cmd_details *cmd_details) 3193 { 3194 struct i40e_aqc_nvm_update *cmd; 3195 struct i40e_aq_desc desc; 3196 int status; 3197 3198 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw; 3199 3200 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3201 3202 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT | 3203 I40E_AQ_NVM_REARRANGE_TO_STRUCT); 3204 3205 if (!rearrange_nvm) { 3206 status = -EINVAL; 3207 goto i40e_aq_rearrange_nvm_exit; 3208 } 3209 3210 cmd->command_flags |= rearrange_nvm; 3211 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3212 3213 i40e_aq_rearrange_nvm_exit: 3214 return status; 3215 } 3216 3217 /** 3218 * i40e_aq_get_lldp_mib 3219 * @hw: pointer to the hw struct 3220 * @bridge_type: type of bridge requested 3221 * @mib_type: Local, Remote or both Local and Remote MIBs 3222 * @buff: pointer to a user supplied buffer to store the MIB block 3223 * @buff_size: size of the buffer (in bytes) 3224 * @local_len : length of the returned Local LLDP MIB 3225 * @remote_len: length of the returned Remote LLDP MIB 3226 * @cmd_details: pointer to command details structure or NULL 3227 * 3228 * Requests the complete LLDP MIB (entire packet). 3229 **/ 3230 int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3231 u8 mib_type, void *buff, u16 buff_size, 3232 u16 *local_len, u16 *remote_len, 3233 struct i40e_asq_cmd_details *cmd_details) 3234 { 3235 struct i40e_aq_desc desc; 3236 struct i40e_aqc_lldp_get_mib *cmd = 3237 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3238 struct i40e_aqc_lldp_get_mib *resp = 3239 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3240 int status; 3241 3242 if (buff_size == 0 || !buff) 3243 return -EINVAL; 3244 3245 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3246 /* Indirect Command */ 3247 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3248 3249 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3250 cmd->type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type); 3251 3252 desc.datalen = cpu_to_le16(buff_size); 3253 3254 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3255 if (buff_size > I40E_AQ_LARGE_BUF) 3256 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3257 3258 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3259 if (!status) { 3260 if (local_len != NULL) 3261 *local_len = le16_to_cpu(resp->local_len); 3262 if (remote_len != NULL) 3263 *remote_len = le16_to_cpu(resp->remote_len); 3264 } 3265 3266 return status; 3267 } 3268 3269 /** 3270 * i40e_aq_set_lldp_mib - Set the LLDP MIB 3271 * @hw: pointer to the hw struct 3272 * @mib_type: Local, Remote or both Local and Remote MIBs 3273 * @buff: pointer to a user supplied buffer to store the MIB block 3274 * @buff_size: size of the buffer (in bytes) 3275 * @cmd_details: pointer to command details structure or NULL 3276 * 3277 * Set the LLDP MIB. 3278 **/ 3279 int 3280 i40e_aq_set_lldp_mib(struct i40e_hw *hw, 3281 u8 mib_type, void *buff, u16 buff_size, 3282 struct i40e_asq_cmd_details *cmd_details) 3283 { 3284 struct i40e_aqc_lldp_set_local_mib *cmd; 3285 struct i40e_aq_desc desc; 3286 int status; 3287 3288 cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 3289 if (buff_size == 0 || !buff) 3290 return -EINVAL; 3291 3292 i40e_fill_default_direct_cmd_desc(&desc, 3293 i40e_aqc_opc_lldp_set_local_mib); 3294 /* Indirect Command */ 3295 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3296 if (buff_size > I40E_AQ_LARGE_BUF) 3297 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3298 desc.datalen = cpu_to_le16(buff_size); 3299 3300 cmd->type = mib_type; 3301 cmd->length = cpu_to_le16(buff_size); 3302 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff)); 3303 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff)); 3304 3305 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3306 return status; 3307 } 3308 3309 /** 3310 * i40e_aq_cfg_lldp_mib_change_event 3311 * @hw: pointer to the hw struct 3312 * @enable_update: Enable or Disable event posting 3313 * @cmd_details: pointer to command details structure or NULL 3314 * 3315 * Enable or Disable posting of an event on ARQ when LLDP MIB 3316 * associated with the interface changes 3317 **/ 3318 int i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3319 bool enable_update, 3320 struct i40e_asq_cmd_details *cmd_details) 3321 { 3322 struct i40e_aq_desc desc; 3323 struct i40e_aqc_lldp_update_mib *cmd = 3324 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3325 int status; 3326 3327 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3328 3329 if (!enable_update) 3330 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3331 3332 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3333 3334 return status; 3335 } 3336 3337 /** 3338 * i40e_aq_restore_lldp 3339 * @hw: pointer to the hw struct 3340 * @setting: pointer to factory setting variable or NULL 3341 * @restore: True if factory settings should be restored 3342 * @cmd_details: pointer to command details structure or NULL 3343 * 3344 * Restore LLDP Agent factory settings if @restore set to True. In other case 3345 * only returns factory setting in AQ response. 3346 **/ 3347 int 3348 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore, 3349 struct i40e_asq_cmd_details *cmd_details) 3350 { 3351 struct i40e_aq_desc desc; 3352 struct i40e_aqc_lldp_restore *cmd = 3353 (struct i40e_aqc_lldp_restore *)&desc.params.raw; 3354 int status; 3355 3356 if (!test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) { 3357 i40e_debug(hw, I40E_DEBUG_ALL, 3358 "Restore LLDP not supported by current FW version.\n"); 3359 return -ENODEV; 3360 } 3361 3362 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore); 3363 3364 if (restore) 3365 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE; 3366 3367 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3368 3369 if (setting) 3370 *setting = cmd->command & 1; 3371 3372 return status; 3373 } 3374 3375 /** 3376 * i40e_aq_stop_lldp 3377 * @hw: pointer to the hw struct 3378 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3379 * @persist: True if stop of LLDP should be persistent across power cycles 3380 * @cmd_details: pointer to command details structure or NULL 3381 * 3382 * Stop or Shutdown the embedded LLDP Agent 3383 **/ 3384 int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3385 bool persist, 3386 struct i40e_asq_cmd_details *cmd_details) 3387 { 3388 struct i40e_aq_desc desc; 3389 struct i40e_aqc_lldp_stop *cmd = 3390 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3391 int status; 3392 3393 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3394 3395 if (shutdown_agent) 3396 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3397 3398 if (persist) { 3399 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) 3400 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST; 3401 else 3402 i40e_debug(hw, I40E_DEBUG_ALL, 3403 "Persistent Stop LLDP not supported by current FW version.\n"); 3404 } 3405 3406 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3407 3408 return status; 3409 } 3410 3411 /** 3412 * i40e_aq_start_lldp 3413 * @hw: pointer to the hw struct 3414 * @persist: True if start of LLDP should be persistent across power cycles 3415 * @cmd_details: pointer to command details structure or NULL 3416 * 3417 * Start the embedded LLDP Agent on all ports. 3418 **/ 3419 int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist, 3420 struct i40e_asq_cmd_details *cmd_details) 3421 { 3422 struct i40e_aq_desc desc; 3423 struct i40e_aqc_lldp_start *cmd = 3424 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3425 int status; 3426 3427 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3428 3429 cmd->command = I40E_AQ_LLDP_AGENT_START; 3430 3431 if (persist) { 3432 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) 3433 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST; 3434 else 3435 i40e_debug(hw, I40E_DEBUG_ALL, 3436 "Persistent Start LLDP not supported by current FW version.\n"); 3437 } 3438 3439 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3440 3441 return status; 3442 } 3443 3444 /** 3445 * i40e_aq_set_dcb_parameters 3446 * @hw: pointer to the hw struct 3447 * @cmd_details: pointer to command details structure or NULL 3448 * @dcb_enable: True if DCB configuration needs to be applied 3449 * 3450 **/ 3451 int 3452 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 3453 struct i40e_asq_cmd_details *cmd_details) 3454 { 3455 struct i40e_aq_desc desc; 3456 struct i40e_aqc_set_dcb_parameters *cmd = 3457 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 3458 int status; 3459 3460 if (!test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps)) 3461 return -ENODEV; 3462 3463 i40e_fill_default_direct_cmd_desc(&desc, 3464 i40e_aqc_opc_set_dcb_parameters); 3465 3466 if (dcb_enable) { 3467 cmd->valid_flags = I40E_DCB_VALID; 3468 cmd->command = I40E_AQ_DCB_SET_AGENT; 3469 } 3470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3471 3472 return status; 3473 } 3474 3475 /** 3476 * i40e_aq_get_cee_dcb_config 3477 * @hw: pointer to the hw struct 3478 * @buff: response buffer that stores CEE operational configuration 3479 * @buff_size: size of the buffer passed 3480 * @cmd_details: pointer to command details structure or NULL 3481 * 3482 * Get CEE DCBX mode operational configuration from firmware 3483 **/ 3484 int i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3485 void *buff, u16 buff_size, 3486 struct i40e_asq_cmd_details *cmd_details) 3487 { 3488 struct i40e_aq_desc desc; 3489 int status; 3490 3491 if (buff_size == 0 || !buff) 3492 return -EINVAL; 3493 3494 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3495 3496 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3497 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3498 cmd_details); 3499 3500 return status; 3501 } 3502 3503 /** 3504 * i40e_aq_add_udp_tunnel 3505 * @hw: pointer to the hw struct 3506 * @udp_port: the UDP port to add in Host byte order 3507 * @protocol_index: protocol index type 3508 * @filter_index: pointer to filter index 3509 * @cmd_details: pointer to command details structure or NULL 3510 * 3511 * Note: Firmware expects the udp_port value to be in Little Endian format, 3512 * and this function will call cpu_to_le16 to convert from Host byte order to 3513 * Little Endian order. 3514 **/ 3515 int i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3516 u16 udp_port, u8 protocol_index, 3517 u8 *filter_index, 3518 struct i40e_asq_cmd_details *cmd_details) 3519 { 3520 struct i40e_aq_desc desc; 3521 struct i40e_aqc_add_udp_tunnel *cmd = 3522 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3523 struct i40e_aqc_del_udp_tunnel_completion *resp = 3524 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3525 int status; 3526 3527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3528 3529 cmd->udp_port = cpu_to_le16(udp_port); 3530 cmd->protocol_type = protocol_index; 3531 3532 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3533 3534 if (!status && filter_index) 3535 *filter_index = resp->index; 3536 3537 return status; 3538 } 3539 3540 /** 3541 * i40e_aq_del_udp_tunnel 3542 * @hw: pointer to the hw struct 3543 * @index: filter index 3544 * @cmd_details: pointer to command details structure or NULL 3545 **/ 3546 int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3547 struct i40e_asq_cmd_details *cmd_details) 3548 { 3549 struct i40e_aq_desc desc; 3550 struct i40e_aqc_remove_udp_tunnel *cmd = 3551 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3552 int status; 3553 3554 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3555 3556 cmd->index = index; 3557 3558 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3559 3560 return status; 3561 } 3562 3563 /** 3564 * i40e_aq_delete_element - Delete switch element 3565 * @hw: pointer to the hw struct 3566 * @seid: the SEID to delete from the switch 3567 * @cmd_details: pointer to command details structure or NULL 3568 * 3569 * This deletes a switch element from the switch. 3570 **/ 3571 int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3572 struct i40e_asq_cmd_details *cmd_details) 3573 { 3574 struct i40e_aq_desc desc; 3575 struct i40e_aqc_switch_seid *cmd = 3576 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3577 int status; 3578 3579 if (seid == 0) 3580 return -EINVAL; 3581 3582 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3583 3584 cmd->seid = cpu_to_le16(seid); 3585 3586 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 3587 cmd_details, true); 3588 3589 return status; 3590 } 3591 3592 /** 3593 * i40e_aq_dcb_updated - DCB Updated Command 3594 * @hw: pointer to the hw struct 3595 * @cmd_details: pointer to command details structure or NULL 3596 * 3597 * EMP will return when the shared RPB settings have been 3598 * recomputed and modified. The retval field in the descriptor 3599 * will be set to 0 when RPB is modified. 3600 **/ 3601 int i40e_aq_dcb_updated(struct i40e_hw *hw, 3602 struct i40e_asq_cmd_details *cmd_details) 3603 { 3604 struct i40e_aq_desc desc; 3605 int status; 3606 3607 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3608 3609 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3610 3611 return status; 3612 } 3613 3614 /** 3615 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3616 * @hw: pointer to the hw struct 3617 * @seid: seid for the physical port/switching component/vsi 3618 * @buff: Indirect buffer to hold data parameters and response 3619 * @buff_size: Indirect buffer size 3620 * @opcode: Tx scheduler AQ command opcode 3621 * @cmd_details: pointer to command details structure or NULL 3622 * 3623 * Generic command handler for Tx scheduler AQ commands 3624 **/ 3625 static int i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3626 void *buff, u16 buff_size, 3627 enum i40e_admin_queue_opc opcode, 3628 struct i40e_asq_cmd_details *cmd_details) 3629 { 3630 struct i40e_aq_desc desc; 3631 struct i40e_aqc_tx_sched_ind *cmd = 3632 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3633 int status; 3634 bool cmd_param_flag = false; 3635 3636 switch (opcode) { 3637 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3638 case i40e_aqc_opc_configure_vsi_tc_bw: 3639 case i40e_aqc_opc_enable_switching_comp_ets: 3640 case i40e_aqc_opc_modify_switching_comp_ets: 3641 case i40e_aqc_opc_disable_switching_comp_ets: 3642 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3643 case i40e_aqc_opc_configure_switching_comp_bw_config: 3644 cmd_param_flag = true; 3645 break; 3646 case i40e_aqc_opc_query_vsi_bw_config: 3647 case i40e_aqc_opc_query_vsi_ets_sla_config: 3648 case i40e_aqc_opc_query_switching_comp_ets_config: 3649 case i40e_aqc_opc_query_port_ets_config: 3650 case i40e_aqc_opc_query_switching_comp_bw_config: 3651 cmd_param_flag = false; 3652 break; 3653 default: 3654 return -EINVAL; 3655 } 3656 3657 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3658 3659 /* Indirect command */ 3660 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3661 if (cmd_param_flag) 3662 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3663 if (buff_size > I40E_AQ_LARGE_BUF) 3664 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3665 3666 desc.datalen = cpu_to_le16(buff_size); 3667 3668 cmd->vsi_seid = cpu_to_le16(seid); 3669 3670 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3671 3672 return status; 3673 } 3674 3675 /** 3676 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3677 * @hw: pointer to the hw struct 3678 * @seid: VSI seid 3679 * @credit: BW limit credits (0 = disabled) 3680 * @max_credit: Max BW limit credits 3681 * @cmd_details: pointer to command details structure or NULL 3682 **/ 3683 int i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3684 u16 seid, u16 credit, u8 max_credit, 3685 struct i40e_asq_cmd_details *cmd_details) 3686 { 3687 struct i40e_aq_desc desc; 3688 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3689 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3690 int status; 3691 3692 i40e_fill_default_direct_cmd_desc(&desc, 3693 i40e_aqc_opc_configure_vsi_bw_limit); 3694 3695 cmd->vsi_seid = cpu_to_le16(seid); 3696 cmd->credit = cpu_to_le16(credit); 3697 cmd->max_credit = max_credit; 3698 3699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3700 3701 return status; 3702 } 3703 3704 /** 3705 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3706 * @hw: pointer to the hw struct 3707 * @seid: VSI seid 3708 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3709 * @cmd_details: pointer to command details structure or NULL 3710 **/ 3711 int i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3712 u16 seid, 3713 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3714 struct i40e_asq_cmd_details *cmd_details) 3715 { 3716 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3717 i40e_aqc_opc_configure_vsi_tc_bw, 3718 cmd_details); 3719 } 3720 3721 /** 3722 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3723 * @hw: pointer to the hw struct 3724 * @seid: seid of the switching component connected to Physical Port 3725 * @ets_data: Buffer holding ETS parameters 3726 * @opcode: Tx scheduler AQ command opcode 3727 * @cmd_details: pointer to command details structure or NULL 3728 **/ 3729 int 3730 i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3731 u16 seid, 3732 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3733 enum i40e_admin_queue_opc opcode, 3734 struct i40e_asq_cmd_details *cmd_details) 3735 { 3736 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3737 sizeof(*ets_data), opcode, cmd_details); 3738 } 3739 3740 /** 3741 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3742 * @hw: pointer to the hw struct 3743 * @seid: seid of the switching component 3744 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3745 * @cmd_details: pointer to command details structure or NULL 3746 **/ 3747 int 3748 i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3749 u16 seid, 3750 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3751 struct i40e_asq_cmd_details *cmd_details) 3752 { 3753 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3754 i40e_aqc_opc_configure_switching_comp_bw_config, 3755 cmd_details); 3756 } 3757 3758 /** 3759 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3760 * @hw: pointer to the hw struct 3761 * @seid: seid of the VSI 3762 * @bw_data: Buffer to hold VSI BW configuration 3763 * @cmd_details: pointer to command details structure or NULL 3764 **/ 3765 int 3766 i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3767 u16 seid, 3768 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3769 struct i40e_asq_cmd_details *cmd_details) 3770 { 3771 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3772 i40e_aqc_opc_query_vsi_bw_config, 3773 cmd_details); 3774 } 3775 3776 /** 3777 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3778 * @hw: pointer to the hw struct 3779 * @seid: seid of the VSI 3780 * @bw_data: Buffer to hold VSI BW configuration per TC 3781 * @cmd_details: pointer to command details structure or NULL 3782 **/ 3783 int 3784 i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3785 u16 seid, 3786 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3787 struct i40e_asq_cmd_details *cmd_details) 3788 { 3789 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3790 i40e_aqc_opc_query_vsi_ets_sla_config, 3791 cmd_details); 3792 } 3793 3794 /** 3795 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3796 * @hw: pointer to the hw struct 3797 * @seid: seid of the switching component 3798 * @bw_data: Buffer to hold switching component's per TC BW config 3799 * @cmd_details: pointer to command details structure or NULL 3800 **/ 3801 int 3802 i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3803 u16 seid, 3804 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3805 struct i40e_asq_cmd_details *cmd_details) 3806 { 3807 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3808 i40e_aqc_opc_query_switching_comp_ets_config, 3809 cmd_details); 3810 } 3811 3812 /** 3813 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3814 * @hw: pointer to the hw struct 3815 * @seid: seid of the VSI or switching component connected to Physical Port 3816 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3817 * @cmd_details: pointer to command details structure or NULL 3818 **/ 3819 int 3820 i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3821 u16 seid, 3822 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3823 struct i40e_asq_cmd_details *cmd_details) 3824 { 3825 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3826 i40e_aqc_opc_query_port_ets_config, 3827 cmd_details); 3828 } 3829 3830 /** 3831 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3832 * @hw: pointer to the hw struct 3833 * @seid: seid of the switching component 3834 * @bw_data: Buffer to hold switching component's BW configuration 3835 * @cmd_details: pointer to command details structure or NULL 3836 **/ 3837 int 3838 i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3839 u16 seid, 3840 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3841 struct i40e_asq_cmd_details *cmd_details) 3842 { 3843 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3844 i40e_aqc_opc_query_switching_comp_bw_config, 3845 cmd_details); 3846 } 3847 3848 /** 3849 * i40e_validate_filter_settings 3850 * @hw: pointer to the hardware structure 3851 * @settings: Filter control settings 3852 * 3853 * Check and validate the filter control settings passed. 3854 * The function checks for the valid filter/context sizes being 3855 * passed for FCoE and PE. 3856 * 3857 * Returns 0 if the values passed are valid and within 3858 * range else returns an error. 3859 **/ 3860 static int 3861 i40e_validate_filter_settings(struct i40e_hw *hw, 3862 struct i40e_filter_control_settings *settings) 3863 { 3864 u32 fcoe_cntx_size, fcoe_filt_size; 3865 u32 fcoe_fmax; 3866 u32 val; 3867 3868 /* Validate FCoE settings passed */ 3869 switch (settings->fcoe_filt_num) { 3870 case I40E_HASH_FILTER_SIZE_1K: 3871 case I40E_HASH_FILTER_SIZE_2K: 3872 case I40E_HASH_FILTER_SIZE_4K: 3873 case I40E_HASH_FILTER_SIZE_8K: 3874 case I40E_HASH_FILTER_SIZE_16K: 3875 case I40E_HASH_FILTER_SIZE_32K: 3876 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3877 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3878 break; 3879 default: 3880 return -EINVAL; 3881 } 3882 3883 switch (settings->fcoe_cntx_num) { 3884 case I40E_DMA_CNTX_SIZE_512: 3885 case I40E_DMA_CNTX_SIZE_1K: 3886 case I40E_DMA_CNTX_SIZE_2K: 3887 case I40E_DMA_CNTX_SIZE_4K: 3888 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3889 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3890 break; 3891 default: 3892 return -EINVAL; 3893 } 3894 3895 /* Validate PE settings passed */ 3896 switch (settings->pe_filt_num) { 3897 case I40E_HASH_FILTER_SIZE_1K: 3898 case I40E_HASH_FILTER_SIZE_2K: 3899 case I40E_HASH_FILTER_SIZE_4K: 3900 case I40E_HASH_FILTER_SIZE_8K: 3901 case I40E_HASH_FILTER_SIZE_16K: 3902 case I40E_HASH_FILTER_SIZE_32K: 3903 case I40E_HASH_FILTER_SIZE_64K: 3904 case I40E_HASH_FILTER_SIZE_128K: 3905 case I40E_HASH_FILTER_SIZE_256K: 3906 case I40E_HASH_FILTER_SIZE_512K: 3907 case I40E_HASH_FILTER_SIZE_1M: 3908 break; 3909 default: 3910 return -EINVAL; 3911 } 3912 3913 switch (settings->pe_cntx_num) { 3914 case I40E_DMA_CNTX_SIZE_512: 3915 case I40E_DMA_CNTX_SIZE_1K: 3916 case I40E_DMA_CNTX_SIZE_2K: 3917 case I40E_DMA_CNTX_SIZE_4K: 3918 case I40E_DMA_CNTX_SIZE_8K: 3919 case I40E_DMA_CNTX_SIZE_16K: 3920 case I40E_DMA_CNTX_SIZE_32K: 3921 case I40E_DMA_CNTX_SIZE_64K: 3922 case I40E_DMA_CNTX_SIZE_128K: 3923 case I40E_DMA_CNTX_SIZE_256K: 3924 break; 3925 default: 3926 return -EINVAL; 3927 } 3928 3929 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3930 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3931 fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val); 3932 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3933 return -EINVAL; 3934 3935 return 0; 3936 } 3937 3938 /** 3939 * i40e_set_filter_control 3940 * @hw: pointer to the hardware structure 3941 * @settings: Filter control settings 3942 * 3943 * Set the Queue Filters for PE/FCoE and enable filters required 3944 * for a single PF. It is expected that these settings are programmed 3945 * at the driver initialization time. 3946 **/ 3947 int i40e_set_filter_control(struct i40e_hw *hw, 3948 struct i40e_filter_control_settings *settings) 3949 { 3950 u32 hash_lut_size = 0; 3951 int ret = 0; 3952 u32 val; 3953 3954 if (!settings) 3955 return -EINVAL; 3956 3957 /* Validate the input settings */ 3958 ret = i40e_validate_filter_settings(hw, settings); 3959 if (ret) 3960 return ret; 3961 3962 /* Read the PF Queue Filter control register */ 3963 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 3964 3965 /* Program required PE hash buckets for the PF */ 3966 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 3967 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEHSIZE_MASK, settings->pe_filt_num); 3968 /* Program required PE contexts for the PF */ 3969 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 3970 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEDSIZE_MASK, settings->pe_cntx_num); 3971 3972 /* Program required FCoE hash buckets for the PF */ 3973 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3974 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCHSIZE_MASK, 3975 settings->fcoe_filt_num); 3976 /* Program required FCoE DDP contexts for the PF */ 3977 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3978 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCDSIZE_MASK, 3979 settings->fcoe_cntx_num); 3980 3981 /* Program Hash LUT size for the PF */ 3982 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3983 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 3984 hash_lut_size = 1; 3985 val |= FIELD_PREP(I40E_PFQF_CTL_0_HASHLUTSIZE_MASK, hash_lut_size); 3986 3987 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 3988 if (settings->enable_fdir) 3989 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 3990 if (settings->enable_ethtype) 3991 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 3992 if (settings->enable_macvlan) 3993 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 3994 3995 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 3996 3997 return 0; 3998 } 3999 4000 /** 4001 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4002 * @hw: pointer to the hw struct 4003 * @mac_addr: MAC address to use in the filter 4004 * @ethtype: Ethertype to use in the filter 4005 * @flags: Flags that needs to be applied to the filter 4006 * @vsi_seid: seid of the control VSI 4007 * @queue: VSI queue number to send the packet to 4008 * @is_add: Add control packet filter if True else remove 4009 * @stats: Structure to hold information on control filter counts 4010 * @cmd_details: pointer to command details structure or NULL 4011 * 4012 * This command will Add or Remove control packet filter for a control VSI. 4013 * In return it will update the total number of perfect filter count in 4014 * the stats member. 4015 **/ 4016 int i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4017 u8 *mac_addr, u16 ethtype, u16 flags, 4018 u16 vsi_seid, u16 queue, bool is_add, 4019 struct i40e_control_filter_stats *stats, 4020 struct i40e_asq_cmd_details *cmd_details) 4021 { 4022 struct i40e_aq_desc desc; 4023 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4024 (struct i40e_aqc_add_remove_control_packet_filter *) 4025 &desc.params.raw; 4026 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4027 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4028 &desc.params.raw; 4029 int status; 4030 4031 if (vsi_seid == 0) 4032 return -EINVAL; 4033 4034 if (is_add) { 4035 i40e_fill_default_direct_cmd_desc(&desc, 4036 i40e_aqc_opc_add_control_packet_filter); 4037 cmd->queue = cpu_to_le16(queue); 4038 } else { 4039 i40e_fill_default_direct_cmd_desc(&desc, 4040 i40e_aqc_opc_remove_control_packet_filter); 4041 } 4042 4043 if (mac_addr) 4044 ether_addr_copy(cmd->mac, mac_addr); 4045 4046 cmd->etype = cpu_to_le16(ethtype); 4047 cmd->flags = cpu_to_le16(flags); 4048 cmd->seid = cpu_to_le16(vsi_seid); 4049 4050 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4051 4052 if (!status && stats) { 4053 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4054 stats->etype_used = le16_to_cpu(resp->etype_used); 4055 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4056 stats->etype_free = le16_to_cpu(resp->etype_free); 4057 } 4058 4059 return status; 4060 } 4061 4062 /** 4063 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4064 * @hw: pointer to the hw struct 4065 * @seid: VSI seid to add ethertype filter from 4066 **/ 4067 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4068 u16 seid) 4069 { 4070 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4071 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4072 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4073 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4074 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4075 int status; 4076 4077 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4078 seid, 0, true, NULL, 4079 NULL); 4080 if (status) 4081 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4082 } 4083 4084 /** 4085 * i40e_aq_alternate_read 4086 * @hw: pointer to the hardware structure 4087 * @reg_addr0: address of first dword to be read 4088 * @reg_val0: pointer for data read from 'reg_addr0' 4089 * @reg_addr1: address of second dword to be read 4090 * @reg_val1: pointer for data read from 'reg_addr1' 4091 * 4092 * Read one or two dwords from alternate structure. Fields are indicated 4093 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4094 * is not passed then only register at 'reg_addr0' is read. 4095 * 4096 **/ 4097 static int i40e_aq_alternate_read(struct i40e_hw *hw, 4098 u32 reg_addr0, u32 *reg_val0, 4099 u32 reg_addr1, u32 *reg_val1) 4100 { 4101 struct i40e_aq_desc desc; 4102 struct i40e_aqc_alternate_write *cmd_resp = 4103 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4104 int status; 4105 4106 if (!reg_val0) 4107 return -EINVAL; 4108 4109 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4110 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4111 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4112 4113 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4114 4115 if (!status) { 4116 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4117 4118 if (reg_val1) 4119 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4120 } 4121 4122 return status; 4123 } 4124 4125 /** 4126 * i40e_aq_suspend_port_tx 4127 * @hw: pointer to the hardware structure 4128 * @seid: port seid 4129 * @cmd_details: pointer to command details structure or NULL 4130 * 4131 * Suspend port's Tx traffic 4132 **/ 4133 int i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, 4134 struct i40e_asq_cmd_details *cmd_details) 4135 { 4136 struct i40e_aqc_tx_sched_ind *cmd; 4137 struct i40e_aq_desc desc; 4138 int status; 4139 4140 cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 4141 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx); 4142 cmd->vsi_seid = cpu_to_le16(seid); 4143 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4144 4145 return status; 4146 } 4147 4148 /** 4149 * i40e_aq_resume_port_tx 4150 * @hw: pointer to the hardware structure 4151 * @cmd_details: pointer to command details structure or NULL 4152 * 4153 * Resume port's Tx traffic 4154 **/ 4155 int i40e_aq_resume_port_tx(struct i40e_hw *hw, 4156 struct i40e_asq_cmd_details *cmd_details) 4157 { 4158 struct i40e_aq_desc desc; 4159 int status; 4160 4161 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4162 4163 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4164 4165 return status; 4166 } 4167 4168 /** 4169 * i40e_set_pci_config_data - store PCI bus info 4170 * @hw: pointer to hardware structure 4171 * @link_status: the link status word from PCI config space 4172 * 4173 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4174 **/ 4175 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4176 { 4177 hw->bus.type = i40e_bus_type_pci_express; 4178 4179 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4180 case PCI_EXP_LNKSTA_NLW_X1: 4181 hw->bus.width = i40e_bus_width_pcie_x1; 4182 break; 4183 case PCI_EXP_LNKSTA_NLW_X2: 4184 hw->bus.width = i40e_bus_width_pcie_x2; 4185 break; 4186 case PCI_EXP_LNKSTA_NLW_X4: 4187 hw->bus.width = i40e_bus_width_pcie_x4; 4188 break; 4189 case PCI_EXP_LNKSTA_NLW_X8: 4190 hw->bus.width = i40e_bus_width_pcie_x8; 4191 break; 4192 default: 4193 hw->bus.width = i40e_bus_width_unknown; 4194 break; 4195 } 4196 4197 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4198 case PCI_EXP_LNKSTA_CLS_2_5GB: 4199 hw->bus.speed = i40e_bus_speed_2500; 4200 break; 4201 case PCI_EXP_LNKSTA_CLS_5_0GB: 4202 hw->bus.speed = i40e_bus_speed_5000; 4203 break; 4204 case PCI_EXP_LNKSTA_CLS_8_0GB: 4205 hw->bus.speed = i40e_bus_speed_8000; 4206 break; 4207 default: 4208 hw->bus.speed = i40e_bus_speed_unknown; 4209 break; 4210 } 4211 } 4212 4213 /** 4214 * i40e_aq_debug_dump 4215 * @hw: pointer to the hardware structure 4216 * @cluster_id: specific cluster to dump 4217 * @table_id: table id within cluster 4218 * @start_index: index of line in the block to read 4219 * @buff_size: dump buffer size 4220 * @buff: dump buffer 4221 * @ret_buff_size: actual buffer size returned 4222 * @ret_next_table: next block to read 4223 * @ret_next_index: next index to read 4224 * @cmd_details: pointer to command details structure or NULL 4225 * 4226 * Dump internal FW/HW data for debug purposes. 4227 * 4228 **/ 4229 int i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4230 u8 table_id, u32 start_index, u16 buff_size, 4231 void *buff, u16 *ret_buff_size, 4232 u8 *ret_next_table, u32 *ret_next_index, 4233 struct i40e_asq_cmd_details *cmd_details) 4234 { 4235 struct i40e_aq_desc desc; 4236 struct i40e_aqc_debug_dump_internals *cmd = 4237 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4238 struct i40e_aqc_debug_dump_internals *resp = 4239 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4240 int status; 4241 4242 if (buff_size == 0 || !buff) 4243 return -EINVAL; 4244 4245 i40e_fill_default_direct_cmd_desc(&desc, 4246 i40e_aqc_opc_debug_dump_internals); 4247 /* Indirect Command */ 4248 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4249 if (buff_size > I40E_AQ_LARGE_BUF) 4250 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4251 4252 cmd->cluster_id = cluster_id; 4253 cmd->table_id = table_id; 4254 cmd->idx = cpu_to_le32(start_index); 4255 4256 desc.datalen = cpu_to_le16(buff_size); 4257 4258 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4259 if (!status) { 4260 if (ret_buff_size) 4261 *ret_buff_size = le16_to_cpu(desc.datalen); 4262 if (ret_next_table) 4263 *ret_next_table = resp->table_id; 4264 if (ret_next_index) 4265 *ret_next_index = le32_to_cpu(resp->idx); 4266 } 4267 4268 return status; 4269 } 4270 4271 /** 4272 * i40e_read_bw_from_alt_ram 4273 * @hw: pointer to the hardware structure 4274 * @max_bw: pointer for max_bw read 4275 * @min_bw: pointer for min_bw read 4276 * @min_valid: pointer for bool that is true if min_bw is a valid value 4277 * @max_valid: pointer for bool that is true if max_bw is a valid value 4278 * 4279 * Read bw from the alternate ram for the given pf 4280 **/ 4281 int i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4282 u32 *max_bw, u32 *min_bw, 4283 bool *min_valid, bool *max_valid) 4284 { 4285 u32 max_bw_addr, min_bw_addr; 4286 int status; 4287 4288 /* Calculate the address of the min/max bw registers */ 4289 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4290 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4291 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4292 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4293 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4294 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4295 4296 /* Read the bandwidths from alt ram */ 4297 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4298 min_bw_addr, min_bw); 4299 4300 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4301 *min_valid = true; 4302 else 4303 *min_valid = false; 4304 4305 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4306 *max_valid = true; 4307 else 4308 *max_valid = false; 4309 4310 return status; 4311 } 4312 4313 /** 4314 * i40e_aq_configure_partition_bw 4315 * @hw: pointer to the hardware structure 4316 * @bw_data: Buffer holding valid pfs and bw limits 4317 * @cmd_details: pointer to command details 4318 * 4319 * Configure partitions guaranteed/max bw 4320 **/ 4321 int 4322 i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4323 struct i40e_aqc_configure_partition_bw_data *bw_data, 4324 struct i40e_asq_cmd_details *cmd_details) 4325 { 4326 u16 bwd_size = sizeof(*bw_data); 4327 struct i40e_aq_desc desc; 4328 int status; 4329 4330 i40e_fill_default_direct_cmd_desc(&desc, 4331 i40e_aqc_opc_configure_partition_bw); 4332 4333 /* Indirect command */ 4334 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4335 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4336 4337 if (bwd_size > I40E_AQ_LARGE_BUF) 4338 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4339 4340 desc.datalen = cpu_to_le16(bwd_size); 4341 4342 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4343 cmd_details); 4344 4345 return status; 4346 } 4347 4348 /** 4349 * i40e_read_phy_register_clause22 4350 * @hw: pointer to the HW structure 4351 * @reg: register address in the page 4352 * @phy_addr: PHY address on MDIO interface 4353 * @value: PHY register value 4354 * 4355 * Reads specified PHY register value 4356 **/ 4357 int i40e_read_phy_register_clause22(struct i40e_hw *hw, 4358 u16 reg, u8 phy_addr, u16 *value) 4359 { 4360 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4361 int status = -EIO; 4362 u32 command = 0; 4363 u16 retry = 1000; 4364 4365 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4366 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4367 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4368 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4369 (I40E_GLGEN_MSCA_MDICMD_MASK); 4370 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4371 do { 4372 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4373 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4374 status = 0; 4375 break; 4376 } 4377 udelay(10); 4378 retry--; 4379 } while (retry); 4380 4381 if (status) { 4382 i40e_debug(hw, I40E_DEBUG_PHY, 4383 "PHY: Can't write command to external PHY.\n"); 4384 } else { 4385 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4386 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4387 } 4388 4389 return status; 4390 } 4391 4392 /** 4393 * i40e_write_phy_register_clause22 4394 * @hw: pointer to the HW structure 4395 * @reg: register address in the page 4396 * @phy_addr: PHY address on MDIO interface 4397 * @value: PHY register value 4398 * 4399 * Writes specified PHY register value 4400 **/ 4401 int i40e_write_phy_register_clause22(struct i40e_hw *hw, 4402 u16 reg, u8 phy_addr, u16 value) 4403 { 4404 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4405 int status = -EIO; 4406 u32 command = 0; 4407 u16 retry = 1000; 4408 4409 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4410 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4411 4412 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4413 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4414 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4415 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4416 (I40E_GLGEN_MSCA_MDICMD_MASK); 4417 4418 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4419 do { 4420 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4421 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4422 status = 0; 4423 break; 4424 } 4425 udelay(10); 4426 retry--; 4427 } while (retry); 4428 4429 return status; 4430 } 4431 4432 /** 4433 * i40e_read_phy_register_clause45 4434 * @hw: pointer to the HW structure 4435 * @page: registers page number 4436 * @reg: register address in the page 4437 * @phy_addr: PHY address on MDIO interface 4438 * @value: PHY register value 4439 * 4440 * Reads specified PHY register value 4441 **/ 4442 int i40e_read_phy_register_clause45(struct i40e_hw *hw, 4443 u8 page, u16 reg, u8 phy_addr, u16 *value) 4444 { 4445 u8 port_num = hw->func_caps.mdio_port_num; 4446 int status = -EIO; 4447 u32 command = 0; 4448 u16 retry = 1000; 4449 4450 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4451 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4452 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4453 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4454 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4455 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4456 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4457 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4458 do { 4459 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4460 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4461 status = 0; 4462 break; 4463 } 4464 usleep_range(10, 20); 4465 retry--; 4466 } while (retry); 4467 4468 if (status) { 4469 i40e_debug(hw, I40E_DEBUG_PHY, 4470 "PHY: Can't write command to external PHY.\n"); 4471 goto phy_read_end; 4472 } 4473 4474 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4475 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4476 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4477 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4478 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4479 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4480 status = -EIO; 4481 retry = 1000; 4482 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4483 do { 4484 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4485 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4486 status = 0; 4487 break; 4488 } 4489 usleep_range(10, 20); 4490 retry--; 4491 } while (retry); 4492 4493 if (!status) { 4494 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4495 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4496 } else { 4497 i40e_debug(hw, I40E_DEBUG_PHY, 4498 "PHY: Can't read register value from external PHY.\n"); 4499 } 4500 4501 phy_read_end: 4502 return status; 4503 } 4504 4505 /** 4506 * i40e_write_phy_register_clause45 4507 * @hw: pointer to the HW structure 4508 * @page: registers page number 4509 * @reg: register address in the page 4510 * @phy_addr: PHY address on MDIO interface 4511 * @value: PHY register value 4512 * 4513 * Writes value to specified PHY register 4514 **/ 4515 int i40e_write_phy_register_clause45(struct i40e_hw *hw, 4516 u8 page, u16 reg, u8 phy_addr, u16 value) 4517 { 4518 u8 port_num = hw->func_caps.mdio_port_num; 4519 int status = -EIO; 4520 u16 retry = 1000; 4521 u32 command = 0; 4522 4523 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4524 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4525 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4526 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4527 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4528 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4529 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4530 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4531 do { 4532 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4533 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4534 status = 0; 4535 break; 4536 } 4537 usleep_range(10, 20); 4538 retry--; 4539 } while (retry); 4540 if (status) { 4541 i40e_debug(hw, I40E_DEBUG_PHY, 4542 "PHY: Can't write command to external PHY.\n"); 4543 goto phy_write_end; 4544 } 4545 4546 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4547 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4548 4549 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4550 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4551 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4552 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4553 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4554 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4555 status = -EIO; 4556 retry = 1000; 4557 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4558 do { 4559 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4560 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4561 status = 0; 4562 break; 4563 } 4564 usleep_range(10, 20); 4565 retry--; 4566 } while (retry); 4567 4568 phy_write_end: 4569 return status; 4570 } 4571 4572 /** 4573 * i40e_write_phy_register 4574 * @hw: pointer to the HW structure 4575 * @page: registers page number 4576 * @reg: register address in the page 4577 * @phy_addr: PHY address on MDIO interface 4578 * @value: PHY register value 4579 * 4580 * Writes value to specified PHY register 4581 **/ 4582 int i40e_write_phy_register(struct i40e_hw *hw, 4583 u8 page, u16 reg, u8 phy_addr, u16 value) 4584 { 4585 int status; 4586 4587 switch (hw->device_id) { 4588 case I40E_DEV_ID_1G_BASE_T_X722: 4589 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4590 value); 4591 break; 4592 case I40E_DEV_ID_1G_BASE_T_BC: 4593 case I40E_DEV_ID_5G_BASE_T_BC: 4594 case I40E_DEV_ID_10G_BASE_T: 4595 case I40E_DEV_ID_10G_BASE_T4: 4596 case I40E_DEV_ID_10G_BASE_T_BC: 4597 case I40E_DEV_ID_10G_BASE_T_X722: 4598 case I40E_DEV_ID_25G_B: 4599 case I40E_DEV_ID_25G_SFP28: 4600 status = i40e_write_phy_register_clause45(hw, page, reg, 4601 phy_addr, value); 4602 break; 4603 default: 4604 status = -EIO; 4605 break; 4606 } 4607 4608 return status; 4609 } 4610 4611 /** 4612 * i40e_read_phy_register 4613 * @hw: pointer to the HW structure 4614 * @page: registers page number 4615 * @reg: register address in the page 4616 * @phy_addr: PHY address on MDIO interface 4617 * @value: PHY register value 4618 * 4619 * Reads specified PHY register value 4620 **/ 4621 int i40e_read_phy_register(struct i40e_hw *hw, 4622 u8 page, u16 reg, u8 phy_addr, u16 *value) 4623 { 4624 int status; 4625 4626 switch (hw->device_id) { 4627 case I40E_DEV_ID_1G_BASE_T_X722: 4628 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4629 value); 4630 break; 4631 case I40E_DEV_ID_1G_BASE_T_BC: 4632 case I40E_DEV_ID_5G_BASE_T_BC: 4633 case I40E_DEV_ID_10G_BASE_T: 4634 case I40E_DEV_ID_10G_BASE_T4: 4635 case I40E_DEV_ID_10G_BASE_T_BC: 4636 case I40E_DEV_ID_10G_BASE_T_X722: 4637 case I40E_DEV_ID_25G_B: 4638 case I40E_DEV_ID_25G_SFP28: 4639 status = i40e_read_phy_register_clause45(hw, page, reg, 4640 phy_addr, value); 4641 break; 4642 default: 4643 status = -EIO; 4644 break; 4645 } 4646 4647 return status; 4648 } 4649 4650 /** 4651 * i40e_get_phy_address 4652 * @hw: pointer to the HW structure 4653 * @dev_num: PHY port num that address we want 4654 * 4655 * Gets PHY address for current port 4656 **/ 4657 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4658 { 4659 u8 port_num = hw->func_caps.mdio_port_num; 4660 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4661 4662 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4663 } 4664 4665 /** 4666 * i40e_blink_phy_link_led 4667 * @hw: pointer to the HW structure 4668 * @time: time how long led will blinks in secs 4669 * @interval: gap between LED on and off in msecs 4670 * 4671 * Blinks PHY link LED 4672 **/ 4673 int i40e_blink_phy_link_led(struct i40e_hw *hw, 4674 u32 time, u32 interval) 4675 { 4676 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4677 u16 gpio_led_port; 4678 u8 phy_addr = 0; 4679 int status = 0; 4680 u16 led_ctl; 4681 u8 port_num; 4682 u16 led_reg; 4683 u32 i; 4684 4685 i = rd32(hw, I40E_PFGEN_PORTNUM); 4686 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4687 phy_addr = i40e_get_phy_address(hw, port_num); 4688 4689 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4690 led_addr++) { 4691 status = i40e_read_phy_register_clause45(hw, 4692 I40E_PHY_COM_REG_PAGE, 4693 led_addr, phy_addr, 4694 &led_reg); 4695 if (status) 4696 goto phy_blinking_end; 4697 led_ctl = led_reg; 4698 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4699 led_reg = 0; 4700 status = i40e_write_phy_register_clause45(hw, 4701 I40E_PHY_COM_REG_PAGE, 4702 led_addr, phy_addr, 4703 led_reg); 4704 if (status) 4705 goto phy_blinking_end; 4706 break; 4707 } 4708 } 4709 4710 if (time > 0 && interval > 0) { 4711 for (i = 0; i < time * 1000; i += interval) { 4712 status = i40e_read_phy_register_clause45(hw, 4713 I40E_PHY_COM_REG_PAGE, 4714 led_addr, phy_addr, &led_reg); 4715 if (status) 4716 goto restore_config; 4717 if (led_reg & I40E_PHY_LED_MANUAL_ON) 4718 led_reg = 0; 4719 else 4720 led_reg = I40E_PHY_LED_MANUAL_ON; 4721 status = i40e_write_phy_register_clause45(hw, 4722 I40E_PHY_COM_REG_PAGE, 4723 led_addr, phy_addr, led_reg); 4724 if (status) 4725 goto restore_config; 4726 msleep(interval); 4727 } 4728 } 4729 4730 restore_config: 4731 status = i40e_write_phy_register_clause45(hw, 4732 I40E_PHY_COM_REG_PAGE, 4733 led_addr, phy_addr, led_ctl); 4734 4735 phy_blinking_end: 4736 return status; 4737 } 4738 4739 /** 4740 * i40e_led_get_reg - read LED register 4741 * @hw: pointer to the HW structure 4742 * @led_addr: LED register address 4743 * @reg_val: read register value 4744 **/ 4745 static int i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 4746 u32 *reg_val) 4747 { 4748 u8 phy_addr = 0; 4749 u8 port_num; 4750 int status; 4751 u32 i; 4752 4753 *reg_val = 0; 4754 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4755 status = 4756 i40e_aq_get_phy_register(hw, 4757 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4758 I40E_PHY_COM_REG_PAGE, true, 4759 I40E_PHY_LED_PROV_REG_1, 4760 reg_val, NULL); 4761 } else { 4762 i = rd32(hw, I40E_PFGEN_PORTNUM); 4763 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4764 phy_addr = i40e_get_phy_address(hw, port_num); 4765 status = i40e_read_phy_register_clause45(hw, 4766 I40E_PHY_COM_REG_PAGE, 4767 led_addr, phy_addr, 4768 (u16 *)reg_val); 4769 } 4770 return status; 4771 } 4772 4773 /** 4774 * i40e_led_set_reg - write LED register 4775 * @hw: pointer to the HW structure 4776 * @led_addr: LED register address 4777 * @reg_val: register value to write 4778 **/ 4779 static int i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 4780 u32 reg_val) 4781 { 4782 u8 phy_addr = 0; 4783 u8 port_num; 4784 int status; 4785 u32 i; 4786 4787 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4788 status = 4789 i40e_aq_set_phy_register(hw, 4790 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4791 I40E_PHY_COM_REG_PAGE, true, 4792 I40E_PHY_LED_PROV_REG_1, 4793 reg_val, NULL); 4794 } else { 4795 i = rd32(hw, I40E_PFGEN_PORTNUM); 4796 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4797 phy_addr = i40e_get_phy_address(hw, port_num); 4798 status = i40e_write_phy_register_clause45(hw, 4799 I40E_PHY_COM_REG_PAGE, 4800 led_addr, phy_addr, 4801 (u16)reg_val); 4802 } 4803 4804 return status; 4805 } 4806 4807 /** 4808 * i40e_led_get_phy - return current on/off mode 4809 * @hw: pointer to the hw struct 4810 * @led_addr: address of led register to use 4811 * @val: original value of register to use 4812 * 4813 **/ 4814 int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4815 u16 *val) 4816 { 4817 u16 gpio_led_port; 4818 u8 phy_addr = 0; 4819 u32 reg_val_aq; 4820 int status = 0; 4821 u16 temp_addr; 4822 u16 reg_val; 4823 u8 port_num; 4824 u32 i; 4825 4826 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4827 status = 4828 i40e_aq_get_phy_register(hw, 4829 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4830 I40E_PHY_COM_REG_PAGE, true, 4831 I40E_PHY_LED_PROV_REG_1, 4832 ®_val_aq, NULL); 4833 if (status == 0) 4834 *val = (u16)reg_val_aq; 4835 return status; 4836 } 4837 temp_addr = I40E_PHY_LED_PROV_REG_1; 4838 i = rd32(hw, I40E_PFGEN_PORTNUM); 4839 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4840 phy_addr = i40e_get_phy_address(hw, port_num); 4841 4842 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4843 temp_addr++) { 4844 status = i40e_read_phy_register_clause45(hw, 4845 I40E_PHY_COM_REG_PAGE, 4846 temp_addr, phy_addr, 4847 ®_val); 4848 if (status) 4849 return status; 4850 *val = reg_val; 4851 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4852 *led_addr = temp_addr; 4853 break; 4854 } 4855 } 4856 return status; 4857 } 4858 4859 /** 4860 * i40e_led_set_phy 4861 * @hw: pointer to the HW structure 4862 * @on: true or false 4863 * @led_addr: address of led register to use 4864 * @mode: original val plus bit for set or ignore 4865 * 4866 * Set led's on or off when controlled by the PHY 4867 * 4868 **/ 4869 int i40e_led_set_phy(struct i40e_hw *hw, bool on, 4870 u16 led_addr, u32 mode) 4871 { 4872 u32 led_ctl = 0; 4873 u32 led_reg = 0; 4874 int status = 0; 4875 4876 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4877 if (status) 4878 return status; 4879 led_ctl = led_reg; 4880 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4881 led_reg = 0; 4882 status = i40e_led_set_reg(hw, led_addr, led_reg); 4883 if (status) 4884 return status; 4885 } 4886 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4887 if (status) 4888 goto restore_config; 4889 if (on) 4890 led_reg = I40E_PHY_LED_MANUAL_ON; 4891 else 4892 led_reg = 0; 4893 4894 status = i40e_led_set_reg(hw, led_addr, led_reg); 4895 if (status) 4896 goto restore_config; 4897 if (mode & I40E_PHY_LED_MODE_ORIG) { 4898 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 4899 status = i40e_led_set_reg(hw, led_addr, led_ctl); 4900 } 4901 return status; 4902 4903 restore_config: 4904 status = i40e_led_set_reg(hw, led_addr, led_ctl); 4905 return status; 4906 } 4907 4908 /** 4909 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 4910 * @hw: pointer to the hw struct 4911 * @reg_addr: register address 4912 * @reg_val: ptr to register value 4913 * @cmd_details: pointer to command details structure or NULL 4914 * 4915 * Use the firmware to read the Rx control register, 4916 * especially useful if the Rx unit is under heavy pressure 4917 **/ 4918 int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 4919 u32 reg_addr, u32 *reg_val, 4920 struct i40e_asq_cmd_details *cmd_details) 4921 { 4922 struct i40e_aq_desc desc; 4923 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 4924 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 4925 int status; 4926 4927 if (!reg_val) 4928 return -EINVAL; 4929 4930 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 4931 4932 cmd_resp->address = cpu_to_le32(reg_addr); 4933 4934 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4935 4936 if (status == 0) 4937 *reg_val = le32_to_cpu(cmd_resp->value); 4938 4939 return status; 4940 } 4941 4942 /** 4943 * i40e_read_rx_ctl - read from an Rx control register 4944 * @hw: pointer to the hw struct 4945 * @reg_addr: register address 4946 **/ 4947 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 4948 { 4949 bool use_register = false; 4950 int status = 0; 4951 int retry = 5; 4952 u32 val = 0; 4953 4954 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722) 4955 use_register = true; 4956 4957 if (!use_register) { 4958 do_retry: 4959 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 4960 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 4961 usleep_range(1000, 2000); 4962 retry--; 4963 goto do_retry; 4964 } 4965 } 4966 4967 /* if the AQ access failed, try the old-fashioned way */ 4968 if (status || use_register) 4969 val = rd32(hw, reg_addr); 4970 4971 return val; 4972 } 4973 4974 /** 4975 * i40e_aq_rx_ctl_write_register 4976 * @hw: pointer to the hw struct 4977 * @reg_addr: register address 4978 * @reg_val: register value 4979 * @cmd_details: pointer to command details structure or NULL 4980 * 4981 * Use the firmware to write to an Rx control register, 4982 * especially useful if the Rx unit is under heavy pressure 4983 **/ 4984 int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 4985 u32 reg_addr, u32 reg_val, 4986 struct i40e_asq_cmd_details *cmd_details) 4987 { 4988 struct i40e_aq_desc desc; 4989 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 4990 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 4991 int status; 4992 4993 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 4994 4995 cmd->address = cpu_to_le32(reg_addr); 4996 cmd->value = cpu_to_le32(reg_val); 4997 4998 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4999 5000 return status; 5001 } 5002 5003 /** 5004 * i40e_write_rx_ctl - write to an Rx control register 5005 * @hw: pointer to the hw struct 5006 * @reg_addr: register address 5007 * @reg_val: register value 5008 **/ 5009 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5010 { 5011 bool use_register = false; 5012 int status = 0; 5013 int retry = 5; 5014 5015 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722) 5016 use_register = true; 5017 5018 if (!use_register) { 5019 do_retry: 5020 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5021 reg_val, NULL); 5022 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5023 usleep_range(1000, 2000); 5024 retry--; 5025 goto do_retry; 5026 } 5027 } 5028 5029 /* if the AQ access failed, try the old-fashioned way */ 5030 if (status || use_register) 5031 wr32(hw, reg_addr, reg_val); 5032 } 5033 5034 /** 5035 * i40e_mdio_if_number_selection - MDIO I/F number selection 5036 * @hw: pointer to the hw struct 5037 * @set_mdio: use MDIO I/F number specified by mdio_num 5038 * @mdio_num: MDIO I/F number 5039 * @cmd: pointer to PHY Register command structure 5040 **/ 5041 static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, 5042 u8 mdio_num, 5043 struct i40e_aqc_phy_register_access *cmd) 5044 { 5045 if (!set_mdio || 5046 cmd->phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL) 5047 return; 5048 5049 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps)) { 5050 cmd->cmd_flags |= 5051 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 5052 FIELD_PREP(I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK, 5053 mdio_num); 5054 } else { 5055 i40e_debug(hw, I40E_DEBUG_PHY, "MDIO I/F number selection not supported by current FW version.\n"); 5056 } 5057 } 5058 5059 /** 5060 * i40e_aq_set_phy_register_ext 5061 * @hw: pointer to the hw struct 5062 * @phy_select: select which phy should be accessed 5063 * @dev_addr: PHY device address 5064 * @page_change: flag to indicate if phy page should be updated 5065 * @set_mdio: use MDIO I/F number specified by mdio_num 5066 * @mdio_num: MDIO I/F number 5067 * @reg_addr: PHY register address 5068 * @reg_val: new register value 5069 * @cmd_details: pointer to command details structure or NULL 5070 * 5071 * Write the external PHY register. 5072 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 5073 * may use simple wrapper i40e_aq_set_phy_register. 5074 **/ 5075 int i40e_aq_set_phy_register_ext(struct i40e_hw *hw, 5076 u8 phy_select, u8 dev_addr, bool page_change, 5077 bool set_mdio, u8 mdio_num, 5078 u32 reg_addr, u32 reg_val, 5079 struct i40e_asq_cmd_details *cmd_details) 5080 { 5081 struct i40e_aq_desc desc; 5082 struct i40e_aqc_phy_register_access *cmd = 5083 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5084 int status; 5085 5086 i40e_fill_default_direct_cmd_desc(&desc, 5087 i40e_aqc_opc_set_phy_register); 5088 5089 cmd->phy_interface = phy_select; 5090 cmd->dev_address = dev_addr; 5091 cmd->reg_address = cpu_to_le32(reg_addr); 5092 cmd->reg_value = cpu_to_le32(reg_val); 5093 5094 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 5095 5096 if (!page_change) 5097 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 5098 5099 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5100 5101 return status; 5102 } 5103 5104 /** 5105 * i40e_aq_get_phy_register_ext 5106 * @hw: pointer to the hw struct 5107 * @phy_select: select which phy should be accessed 5108 * @dev_addr: PHY device address 5109 * @page_change: flag to indicate if phy page should be updated 5110 * @set_mdio: use MDIO I/F number specified by mdio_num 5111 * @mdio_num: MDIO I/F number 5112 * @reg_addr: PHY register address 5113 * @reg_val: read register value 5114 * @cmd_details: pointer to command details structure or NULL 5115 * 5116 * Read the external PHY register. 5117 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 5118 * may use simple wrapper i40e_aq_get_phy_register. 5119 **/ 5120 int i40e_aq_get_phy_register_ext(struct i40e_hw *hw, 5121 u8 phy_select, u8 dev_addr, bool page_change, 5122 bool set_mdio, u8 mdio_num, 5123 u32 reg_addr, u32 *reg_val, 5124 struct i40e_asq_cmd_details *cmd_details) 5125 { 5126 struct i40e_aq_desc desc; 5127 struct i40e_aqc_phy_register_access *cmd = 5128 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5129 int status; 5130 5131 i40e_fill_default_direct_cmd_desc(&desc, 5132 i40e_aqc_opc_get_phy_register); 5133 5134 cmd->phy_interface = phy_select; 5135 cmd->dev_address = dev_addr; 5136 cmd->reg_address = cpu_to_le32(reg_addr); 5137 5138 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 5139 5140 if (!page_change) 5141 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 5142 5143 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5144 if (!status) 5145 *reg_val = le32_to_cpu(cmd->reg_value); 5146 5147 return status; 5148 } 5149 5150 /** 5151 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 5152 * @hw: pointer to the hw struct 5153 * @buff: command buffer (size in bytes = buff_size) 5154 * @buff_size: buffer size in bytes 5155 * @track_id: package tracking id 5156 * @error_offset: returns error offset 5157 * @error_info: returns error information 5158 * @cmd_details: pointer to command details structure or NULL 5159 **/ 5160 int i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 5161 u16 buff_size, u32 track_id, 5162 u32 *error_offset, u32 *error_info, 5163 struct i40e_asq_cmd_details *cmd_details) 5164 { 5165 struct i40e_aq_desc desc; 5166 struct i40e_aqc_write_personalization_profile *cmd = 5167 (struct i40e_aqc_write_personalization_profile *) 5168 &desc.params.raw; 5169 struct i40e_aqc_write_ddp_resp *resp; 5170 int status; 5171 5172 i40e_fill_default_direct_cmd_desc(&desc, 5173 i40e_aqc_opc_write_personalization_profile); 5174 5175 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 5176 if (buff_size > I40E_AQ_LARGE_BUF) 5177 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5178 5179 desc.datalen = cpu_to_le16(buff_size); 5180 5181 cmd->profile_track_id = cpu_to_le32(track_id); 5182 5183 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5184 if (!status) { 5185 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 5186 if (error_offset) 5187 *error_offset = le32_to_cpu(resp->error_offset); 5188 if (error_info) 5189 *error_info = le32_to_cpu(resp->error_info); 5190 } 5191 5192 return status; 5193 } 5194 5195 /** 5196 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 5197 * @hw: pointer to the hw struct 5198 * @buff: command buffer (size in bytes = buff_size) 5199 * @buff_size: buffer size in bytes 5200 * @flags: AdminQ command flags 5201 * @cmd_details: pointer to command details structure or NULL 5202 **/ 5203 int i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 5204 u16 buff_size, u8 flags, 5205 struct i40e_asq_cmd_details *cmd_details) 5206 { 5207 struct i40e_aq_desc desc; 5208 struct i40e_aqc_get_applied_profiles *cmd = 5209 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 5210 int status; 5211 5212 i40e_fill_default_direct_cmd_desc(&desc, 5213 i40e_aqc_opc_get_personalization_profile_list); 5214 5215 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 5216 if (buff_size > I40E_AQ_LARGE_BUF) 5217 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5218 desc.datalen = cpu_to_le16(buff_size); 5219 5220 cmd->flags = flags; 5221 5222 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5223 5224 return status; 5225 } 5226 5227 /** 5228 * i40e_find_segment_in_package 5229 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 5230 * @pkg_hdr: pointer to the package header to be searched 5231 * 5232 * This function searches a package file for a particular segment type. On 5233 * success it returns a pointer to the segment header, otherwise it will 5234 * return NULL. 5235 **/ 5236 struct i40e_generic_seg_header * 5237 i40e_find_segment_in_package(u32 segment_type, 5238 struct i40e_package_header *pkg_hdr) 5239 { 5240 struct i40e_generic_seg_header *segment; 5241 u32 i; 5242 5243 /* Search all package segments for the requested segment type */ 5244 for (i = 0; i < pkg_hdr->segment_count; i++) { 5245 segment = 5246 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 5247 pkg_hdr->segment_offset[i]); 5248 5249 if (segment->type == segment_type) 5250 return segment; 5251 } 5252 5253 return NULL; 5254 } 5255 5256 /* Get section table in profile */ 5257 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 5258 do { \ 5259 struct i40e_profile_segment *p = (profile); \ 5260 u32 count; \ 5261 u32 *nvm; \ 5262 count = p->device_table_count; \ 5263 nvm = (u32 *)&p->device_table[count]; \ 5264 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 5265 } while (0) 5266 5267 /* Get section header in profile */ 5268 #define I40E_SECTION_HEADER(profile, offset) \ 5269 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 5270 5271 /** 5272 * i40e_find_section_in_profile 5273 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE) 5274 * @profile: pointer to the i40e segment header to be searched 5275 * 5276 * This function searches i40e segment for a particular section type. On 5277 * success it returns a pointer to the section header, otherwise it will 5278 * return NULL. 5279 **/ 5280 struct i40e_profile_section_header * 5281 i40e_find_section_in_profile(u32 section_type, 5282 struct i40e_profile_segment *profile) 5283 { 5284 struct i40e_profile_section_header *sec; 5285 struct i40e_section_table *sec_tbl; 5286 u32 sec_off; 5287 u32 i; 5288 5289 if (profile->header.type != SEGMENT_TYPE_I40E) 5290 return NULL; 5291 5292 I40E_SECTION_TABLE(profile, sec_tbl); 5293 5294 for (i = 0; i < sec_tbl->section_count; i++) { 5295 sec_off = sec_tbl->section_offset[i]; 5296 sec = I40E_SECTION_HEADER(profile, sec_off); 5297 if (sec->section.type == section_type) 5298 return sec; 5299 } 5300 5301 return NULL; 5302 } 5303 5304 /** 5305 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 5306 * @hw: pointer to the hw struct 5307 * @aq: command buffer containing all data to execute AQ 5308 **/ 5309 static int i40e_ddp_exec_aq_section(struct i40e_hw *hw, 5310 struct i40e_profile_aq_section *aq) 5311 { 5312 struct i40e_aq_desc desc; 5313 u8 *msg = NULL; 5314 u16 msglen; 5315 int status; 5316 5317 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 5318 desc.flags |= cpu_to_le16(aq->flags); 5319 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw)); 5320 5321 msglen = aq->datalen; 5322 if (msglen) { 5323 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 5324 I40E_AQ_FLAG_RD)); 5325 if (msglen > I40E_AQ_LARGE_BUF) 5326 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5327 desc.datalen = cpu_to_le16(msglen); 5328 msg = &aq->data[0]; 5329 } 5330 5331 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 5332 5333 if (status) { 5334 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5335 "unable to exec DDP AQ opcode %u, error %d\n", 5336 aq->opcode, status); 5337 return status; 5338 } 5339 5340 /* copy returned desc to aq_buf */ 5341 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw)); 5342 5343 return 0; 5344 } 5345 5346 /** 5347 * i40e_validate_profile 5348 * @hw: pointer to the hardware structure 5349 * @profile: pointer to the profile segment of the package to be validated 5350 * @track_id: package tracking id 5351 * @rollback: flag if the profile is for rollback. 5352 * 5353 * Validates supported devices and profile's sections. 5354 */ 5355 static int 5356 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5357 u32 track_id, bool rollback) 5358 { 5359 struct i40e_profile_section_header *sec = NULL; 5360 struct i40e_section_table *sec_tbl; 5361 u32 vendor_dev_id; 5362 int status = 0; 5363 u32 dev_cnt; 5364 u32 sec_off; 5365 u32 i; 5366 5367 if (track_id == I40E_DDP_TRACKID_INVALID) { 5368 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 5369 return -EOPNOTSUPP; 5370 } 5371 5372 dev_cnt = profile->device_table_count; 5373 for (i = 0; i < dev_cnt; i++) { 5374 vendor_dev_id = profile->device_table[i].vendor_dev_id; 5375 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL && 5376 hw->device_id == (vendor_dev_id & 0xFFFF)) 5377 break; 5378 } 5379 if (dev_cnt && i == dev_cnt) { 5380 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5381 "Device doesn't support DDP\n"); 5382 return -ENODEV; 5383 } 5384 5385 I40E_SECTION_TABLE(profile, sec_tbl); 5386 5387 /* Validate sections types */ 5388 for (i = 0; i < sec_tbl->section_count; i++) { 5389 sec_off = sec_tbl->section_offset[i]; 5390 sec = I40E_SECTION_HEADER(profile, sec_off); 5391 if (rollback) { 5392 if (sec->section.type == SECTION_TYPE_MMIO || 5393 sec->section.type == SECTION_TYPE_AQ || 5394 sec->section.type == SECTION_TYPE_RB_AQ) { 5395 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5396 "Not a roll-back package\n"); 5397 return -EOPNOTSUPP; 5398 } 5399 } else { 5400 if (sec->section.type == SECTION_TYPE_RB_AQ || 5401 sec->section.type == SECTION_TYPE_RB_MMIO) { 5402 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5403 "Not an original package\n"); 5404 return -EOPNOTSUPP; 5405 } 5406 } 5407 } 5408 5409 return status; 5410 } 5411 5412 /** 5413 * i40e_write_profile 5414 * @hw: pointer to the hardware structure 5415 * @profile: pointer to the profile segment of the package to be downloaded 5416 * @track_id: package tracking id 5417 * 5418 * Handles the download of a complete package. 5419 */ 5420 int 5421 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5422 u32 track_id) 5423 { 5424 struct i40e_profile_section_header *sec = NULL; 5425 struct i40e_profile_aq_section *ddp_aq; 5426 struct i40e_section_table *sec_tbl; 5427 u32 offset = 0, info = 0; 5428 u32 section_size = 0; 5429 int status = 0; 5430 u32 sec_off; 5431 u32 i; 5432 5433 status = i40e_validate_profile(hw, profile, track_id, false); 5434 if (status) 5435 return status; 5436 5437 I40E_SECTION_TABLE(profile, sec_tbl); 5438 5439 for (i = 0; i < sec_tbl->section_count; i++) { 5440 sec_off = sec_tbl->section_offset[i]; 5441 sec = I40E_SECTION_HEADER(profile, sec_off); 5442 /* Process generic admin command */ 5443 if (sec->section.type == SECTION_TYPE_AQ) { 5444 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 5445 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 5446 if (status) { 5447 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5448 "Failed to execute aq: section %d, opcode %u\n", 5449 i, ddp_aq->opcode); 5450 break; 5451 } 5452 sec->section.type = SECTION_TYPE_RB_AQ; 5453 } 5454 5455 /* Skip any non-mmio sections */ 5456 if (sec->section.type != SECTION_TYPE_MMIO) 5457 continue; 5458 5459 section_size = sec->section.size + 5460 sizeof(struct i40e_profile_section_header); 5461 5462 /* Write MMIO section */ 5463 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5464 track_id, &offset, &info, NULL); 5465 if (status) { 5466 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5467 "Failed to write profile: section %d, offset %d, info %d\n", 5468 i, offset, info); 5469 break; 5470 } 5471 } 5472 return status; 5473 } 5474 5475 /** 5476 * i40e_rollback_profile 5477 * @hw: pointer to the hardware structure 5478 * @profile: pointer to the profile segment of the package to be removed 5479 * @track_id: package tracking id 5480 * 5481 * Rolls back previously loaded package. 5482 */ 5483 int 5484 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5485 u32 track_id) 5486 { 5487 struct i40e_profile_section_header *sec = NULL; 5488 struct i40e_section_table *sec_tbl; 5489 u32 offset = 0, info = 0; 5490 u32 section_size = 0; 5491 int status = 0; 5492 u32 sec_off; 5493 int i; 5494 5495 status = i40e_validate_profile(hw, profile, track_id, true); 5496 if (status) 5497 return status; 5498 5499 I40E_SECTION_TABLE(profile, sec_tbl); 5500 5501 /* For rollback write sections in reverse */ 5502 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 5503 sec_off = sec_tbl->section_offset[i]; 5504 sec = I40E_SECTION_HEADER(profile, sec_off); 5505 5506 /* Skip any non-rollback sections */ 5507 if (sec->section.type != SECTION_TYPE_RB_MMIO) 5508 continue; 5509 5510 section_size = sec->section.size + 5511 sizeof(struct i40e_profile_section_header); 5512 5513 /* Write roll-back MMIO section */ 5514 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5515 track_id, &offset, &info, NULL); 5516 if (status) { 5517 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5518 "Failed to write profile: section %d, offset %d, info %d\n", 5519 i, offset, info); 5520 break; 5521 } 5522 } 5523 return status; 5524 } 5525 5526 /** 5527 * i40e_add_pinfo_to_list 5528 * @hw: pointer to the hardware structure 5529 * @profile: pointer to the profile segment of the package 5530 * @profile_info_sec: buffer for information section 5531 * @track_id: package tracking id 5532 * 5533 * Register a profile to the list of loaded profiles. 5534 */ 5535 int 5536 i40e_add_pinfo_to_list(struct i40e_hw *hw, 5537 struct i40e_profile_segment *profile, 5538 u8 *profile_info_sec, u32 track_id) 5539 { 5540 struct i40e_profile_section_header *sec = NULL; 5541 struct i40e_profile_info *pinfo; 5542 u32 offset = 0, info = 0; 5543 int status = 0; 5544 5545 sec = (struct i40e_profile_section_header *)profile_info_sec; 5546 sec->tbl_size = 1; 5547 sec->data_end = sizeof(struct i40e_profile_section_header) + 5548 sizeof(struct i40e_profile_info); 5549 sec->section.type = SECTION_TYPE_INFO; 5550 sec->section.offset = sizeof(struct i40e_profile_section_header); 5551 sec->section.size = sizeof(struct i40e_profile_info); 5552 pinfo = (struct i40e_profile_info *)(profile_info_sec + 5553 sec->section.offset); 5554 pinfo->track_id = track_id; 5555 pinfo->version = profile->version; 5556 pinfo->op = I40E_DDP_ADD_TRACKID; 5557 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE); 5558 5559 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end, 5560 track_id, &offset, &info, NULL); 5561 5562 return status; 5563 } 5564 5565 /** 5566 * i40e_aq_add_cloud_filters 5567 * @hw: pointer to the hardware structure 5568 * @seid: VSI seid to add cloud filters from 5569 * @filters: Buffer which contains the filters to be added 5570 * @filter_count: number of filters contained in the buffer 5571 * 5572 * Set the cloud filters for a given VSI. The contents of the 5573 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5574 * of the function. 5575 * 5576 **/ 5577 int 5578 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5579 struct i40e_aqc_cloud_filters_element_data *filters, 5580 u8 filter_count) 5581 { 5582 struct i40e_aq_desc desc; 5583 struct i40e_aqc_add_remove_cloud_filters *cmd = 5584 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5585 u16 buff_len; 5586 int status; 5587 5588 i40e_fill_default_direct_cmd_desc(&desc, 5589 i40e_aqc_opc_add_cloud_filters); 5590 5591 buff_len = filter_count * sizeof(*filters); 5592 desc.datalen = cpu_to_le16(buff_len); 5593 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5594 cmd->num_filters = filter_count; 5595 cmd->seid = cpu_to_le16(seid); 5596 5597 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5598 5599 return status; 5600 } 5601 5602 /** 5603 * i40e_aq_add_cloud_filters_bb 5604 * @hw: pointer to the hardware structure 5605 * @seid: VSI seid to add cloud filters from 5606 * @filters: Buffer which contains the filters in big buffer to be added 5607 * @filter_count: number of filters contained in the buffer 5608 * 5609 * Set the big buffer cloud filters for a given VSI. The contents of the 5610 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5611 * function. 5612 * 5613 **/ 5614 int 5615 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5616 struct i40e_aqc_cloud_filters_element_bb *filters, 5617 u8 filter_count) 5618 { 5619 struct i40e_aq_desc desc; 5620 struct i40e_aqc_add_remove_cloud_filters *cmd = 5621 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5622 u16 buff_len; 5623 int status; 5624 int i; 5625 5626 i40e_fill_default_direct_cmd_desc(&desc, 5627 i40e_aqc_opc_add_cloud_filters); 5628 5629 buff_len = filter_count * sizeof(*filters); 5630 desc.datalen = cpu_to_le16(buff_len); 5631 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5632 cmd->num_filters = filter_count; 5633 cmd->seid = cpu_to_le16(seid); 5634 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5635 5636 for (i = 0; i < filter_count; i++) { 5637 u16 tnl_type; 5638 u32 ti; 5639 5640 tnl_type = le16_get_bits(filters[i].element.flags, 5641 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5642 5643 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5644 * one more byte further than normally used for Tenant ID in 5645 * other tunnel types. 5646 */ 5647 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5648 ti = le32_to_cpu(filters[i].element.tenant_id); 5649 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5650 } 5651 } 5652 5653 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5654 5655 return status; 5656 } 5657 5658 /** 5659 * i40e_aq_rem_cloud_filters 5660 * @hw: pointer to the hardware structure 5661 * @seid: VSI seid to remove cloud filters from 5662 * @filters: Buffer which contains the filters to be removed 5663 * @filter_count: number of filters contained in the buffer 5664 * 5665 * Remove the cloud filters for a given VSI. The contents of the 5666 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5667 * of the function. 5668 * 5669 **/ 5670 int 5671 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5672 struct i40e_aqc_cloud_filters_element_data *filters, 5673 u8 filter_count) 5674 { 5675 struct i40e_aq_desc desc; 5676 struct i40e_aqc_add_remove_cloud_filters *cmd = 5677 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5678 u16 buff_len; 5679 int status; 5680 5681 i40e_fill_default_direct_cmd_desc(&desc, 5682 i40e_aqc_opc_remove_cloud_filters); 5683 5684 buff_len = filter_count * sizeof(*filters); 5685 desc.datalen = cpu_to_le16(buff_len); 5686 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5687 cmd->num_filters = filter_count; 5688 cmd->seid = cpu_to_le16(seid); 5689 5690 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5691 5692 return status; 5693 } 5694 5695 /** 5696 * i40e_aq_rem_cloud_filters_bb 5697 * @hw: pointer to the hardware structure 5698 * @seid: VSI seid to remove cloud filters from 5699 * @filters: Buffer which contains the filters in big buffer to be removed 5700 * @filter_count: number of filters contained in the buffer 5701 * 5702 * Remove the big buffer cloud filters for a given VSI. The contents of the 5703 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5704 * function. 5705 * 5706 **/ 5707 int 5708 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5709 struct i40e_aqc_cloud_filters_element_bb *filters, 5710 u8 filter_count) 5711 { 5712 struct i40e_aq_desc desc; 5713 struct i40e_aqc_add_remove_cloud_filters *cmd = 5714 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5715 u16 buff_len; 5716 int status; 5717 int i; 5718 5719 i40e_fill_default_direct_cmd_desc(&desc, 5720 i40e_aqc_opc_remove_cloud_filters); 5721 5722 buff_len = filter_count * sizeof(*filters); 5723 desc.datalen = cpu_to_le16(buff_len); 5724 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5725 cmd->num_filters = filter_count; 5726 cmd->seid = cpu_to_le16(seid); 5727 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5728 5729 for (i = 0; i < filter_count; i++) { 5730 u16 tnl_type; 5731 u32 ti; 5732 5733 tnl_type = le16_get_bits(filters[i].element.flags, 5734 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5735 5736 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5737 * one more byte further than normally used for Tenant ID in 5738 * other tunnel types. 5739 */ 5740 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5741 ti = le32_to_cpu(filters[i].element.tenant_id); 5742 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5743 } 5744 } 5745 5746 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5747 5748 return status; 5749 } 5750