1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_type.h" 28 #include "i40e_adminq.h" 29 #include "i40e_prototype.h" 30 #include <linux/avf/virtchnl.h> 31 32 /** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40 { 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_B: 48 case I40E_DEV_ID_KX_C: 49 case I40E_DEV_ID_QSFP_A: 50 case I40E_DEV_ID_QSFP_B: 51 case I40E_DEV_ID_QSFP_C: 52 case I40E_DEV_ID_10G_BASE_T: 53 case I40E_DEV_ID_10G_BASE_T4: 54 case I40E_DEV_ID_20G_KR2: 55 case I40E_DEV_ID_20G_KR2_A: 56 case I40E_DEV_ID_25G_B: 57 case I40E_DEV_ID_25G_SFP28: 58 hw->mac.type = I40E_MAC_XL710; 59 break; 60 case I40E_DEV_ID_KX_X722: 61 case I40E_DEV_ID_QSFP_X722: 62 case I40E_DEV_ID_SFP_X722: 63 case I40E_DEV_ID_1G_BASE_T_X722: 64 case I40E_DEV_ID_10G_BASE_T_X722: 65 case I40E_DEV_ID_SFP_I_X722: 66 hw->mac.type = I40E_MAC_X722; 67 break; 68 default: 69 hw->mac.type = I40E_MAC_GENERIC; 70 break; 71 } 72 } else { 73 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 74 } 75 76 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 77 hw->mac.type, status); 78 return status; 79 } 80 81 /** 82 * i40e_aq_str - convert AQ err code to a string 83 * @hw: pointer to the HW structure 84 * @aq_err: the AQ error code to convert 85 **/ 86 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 87 { 88 switch (aq_err) { 89 case I40E_AQ_RC_OK: 90 return "OK"; 91 case I40E_AQ_RC_EPERM: 92 return "I40E_AQ_RC_EPERM"; 93 case I40E_AQ_RC_ENOENT: 94 return "I40E_AQ_RC_ENOENT"; 95 case I40E_AQ_RC_ESRCH: 96 return "I40E_AQ_RC_ESRCH"; 97 case I40E_AQ_RC_EINTR: 98 return "I40E_AQ_RC_EINTR"; 99 case I40E_AQ_RC_EIO: 100 return "I40E_AQ_RC_EIO"; 101 case I40E_AQ_RC_ENXIO: 102 return "I40E_AQ_RC_ENXIO"; 103 case I40E_AQ_RC_E2BIG: 104 return "I40E_AQ_RC_E2BIG"; 105 case I40E_AQ_RC_EAGAIN: 106 return "I40E_AQ_RC_EAGAIN"; 107 case I40E_AQ_RC_ENOMEM: 108 return "I40E_AQ_RC_ENOMEM"; 109 case I40E_AQ_RC_EACCES: 110 return "I40E_AQ_RC_EACCES"; 111 case I40E_AQ_RC_EFAULT: 112 return "I40E_AQ_RC_EFAULT"; 113 case I40E_AQ_RC_EBUSY: 114 return "I40E_AQ_RC_EBUSY"; 115 case I40E_AQ_RC_EEXIST: 116 return "I40E_AQ_RC_EEXIST"; 117 case I40E_AQ_RC_EINVAL: 118 return "I40E_AQ_RC_EINVAL"; 119 case I40E_AQ_RC_ENOTTY: 120 return "I40E_AQ_RC_ENOTTY"; 121 case I40E_AQ_RC_ENOSPC: 122 return "I40E_AQ_RC_ENOSPC"; 123 case I40E_AQ_RC_ENOSYS: 124 return "I40E_AQ_RC_ENOSYS"; 125 case I40E_AQ_RC_ERANGE: 126 return "I40E_AQ_RC_ERANGE"; 127 case I40E_AQ_RC_EFLUSHED: 128 return "I40E_AQ_RC_EFLUSHED"; 129 case I40E_AQ_RC_BAD_ADDR: 130 return "I40E_AQ_RC_BAD_ADDR"; 131 case I40E_AQ_RC_EMODE: 132 return "I40E_AQ_RC_EMODE"; 133 case I40E_AQ_RC_EFBIG: 134 return "I40E_AQ_RC_EFBIG"; 135 } 136 137 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 138 return hw->err_str; 139 } 140 141 /** 142 * i40e_stat_str - convert status err code to a string 143 * @hw: pointer to the HW structure 144 * @stat_err: the status error code to convert 145 **/ 146 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 147 { 148 switch (stat_err) { 149 case 0: 150 return "OK"; 151 case I40E_ERR_NVM: 152 return "I40E_ERR_NVM"; 153 case I40E_ERR_NVM_CHECKSUM: 154 return "I40E_ERR_NVM_CHECKSUM"; 155 case I40E_ERR_PHY: 156 return "I40E_ERR_PHY"; 157 case I40E_ERR_CONFIG: 158 return "I40E_ERR_CONFIG"; 159 case I40E_ERR_PARAM: 160 return "I40E_ERR_PARAM"; 161 case I40E_ERR_MAC_TYPE: 162 return "I40E_ERR_MAC_TYPE"; 163 case I40E_ERR_UNKNOWN_PHY: 164 return "I40E_ERR_UNKNOWN_PHY"; 165 case I40E_ERR_LINK_SETUP: 166 return "I40E_ERR_LINK_SETUP"; 167 case I40E_ERR_ADAPTER_STOPPED: 168 return "I40E_ERR_ADAPTER_STOPPED"; 169 case I40E_ERR_INVALID_MAC_ADDR: 170 return "I40E_ERR_INVALID_MAC_ADDR"; 171 case I40E_ERR_DEVICE_NOT_SUPPORTED: 172 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 173 case I40E_ERR_MASTER_REQUESTS_PENDING: 174 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 175 case I40E_ERR_INVALID_LINK_SETTINGS: 176 return "I40E_ERR_INVALID_LINK_SETTINGS"; 177 case I40E_ERR_AUTONEG_NOT_COMPLETE: 178 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 179 case I40E_ERR_RESET_FAILED: 180 return "I40E_ERR_RESET_FAILED"; 181 case I40E_ERR_SWFW_SYNC: 182 return "I40E_ERR_SWFW_SYNC"; 183 case I40E_ERR_NO_AVAILABLE_VSI: 184 return "I40E_ERR_NO_AVAILABLE_VSI"; 185 case I40E_ERR_NO_MEMORY: 186 return "I40E_ERR_NO_MEMORY"; 187 case I40E_ERR_BAD_PTR: 188 return "I40E_ERR_BAD_PTR"; 189 case I40E_ERR_RING_FULL: 190 return "I40E_ERR_RING_FULL"; 191 case I40E_ERR_INVALID_PD_ID: 192 return "I40E_ERR_INVALID_PD_ID"; 193 case I40E_ERR_INVALID_QP_ID: 194 return "I40E_ERR_INVALID_QP_ID"; 195 case I40E_ERR_INVALID_CQ_ID: 196 return "I40E_ERR_INVALID_CQ_ID"; 197 case I40E_ERR_INVALID_CEQ_ID: 198 return "I40E_ERR_INVALID_CEQ_ID"; 199 case I40E_ERR_INVALID_AEQ_ID: 200 return "I40E_ERR_INVALID_AEQ_ID"; 201 case I40E_ERR_INVALID_SIZE: 202 return "I40E_ERR_INVALID_SIZE"; 203 case I40E_ERR_INVALID_ARP_INDEX: 204 return "I40E_ERR_INVALID_ARP_INDEX"; 205 case I40E_ERR_INVALID_FPM_FUNC_ID: 206 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 207 case I40E_ERR_QP_INVALID_MSG_SIZE: 208 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 209 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 210 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 211 case I40E_ERR_INVALID_FRAG_COUNT: 212 return "I40E_ERR_INVALID_FRAG_COUNT"; 213 case I40E_ERR_QUEUE_EMPTY: 214 return "I40E_ERR_QUEUE_EMPTY"; 215 case I40E_ERR_INVALID_ALIGNMENT: 216 return "I40E_ERR_INVALID_ALIGNMENT"; 217 case I40E_ERR_FLUSHED_QUEUE: 218 return "I40E_ERR_FLUSHED_QUEUE"; 219 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 220 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 221 case I40E_ERR_INVALID_IMM_DATA_SIZE: 222 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 223 case I40E_ERR_TIMEOUT: 224 return "I40E_ERR_TIMEOUT"; 225 case I40E_ERR_OPCODE_MISMATCH: 226 return "I40E_ERR_OPCODE_MISMATCH"; 227 case I40E_ERR_CQP_COMPL_ERROR: 228 return "I40E_ERR_CQP_COMPL_ERROR"; 229 case I40E_ERR_INVALID_VF_ID: 230 return "I40E_ERR_INVALID_VF_ID"; 231 case I40E_ERR_INVALID_HMCFN_ID: 232 return "I40E_ERR_INVALID_HMCFN_ID"; 233 case I40E_ERR_BACKING_PAGE_ERROR: 234 return "I40E_ERR_BACKING_PAGE_ERROR"; 235 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 236 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 237 case I40E_ERR_INVALID_PBLE_INDEX: 238 return "I40E_ERR_INVALID_PBLE_INDEX"; 239 case I40E_ERR_INVALID_SD_INDEX: 240 return "I40E_ERR_INVALID_SD_INDEX"; 241 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 242 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 243 case I40E_ERR_INVALID_SD_TYPE: 244 return "I40E_ERR_INVALID_SD_TYPE"; 245 case I40E_ERR_MEMCPY_FAILED: 246 return "I40E_ERR_MEMCPY_FAILED"; 247 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 248 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 249 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 250 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 251 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 252 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 253 case I40E_ERR_SRQ_ENABLED: 254 return "I40E_ERR_SRQ_ENABLED"; 255 case I40E_ERR_ADMIN_QUEUE_ERROR: 256 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 257 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 258 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 259 case I40E_ERR_BUF_TOO_SHORT: 260 return "I40E_ERR_BUF_TOO_SHORT"; 261 case I40E_ERR_ADMIN_QUEUE_FULL: 262 return "I40E_ERR_ADMIN_QUEUE_FULL"; 263 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 264 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 265 case I40E_ERR_BAD_IWARP_CQE: 266 return "I40E_ERR_BAD_IWARP_CQE"; 267 case I40E_ERR_NVM_BLANK_MODE: 268 return "I40E_ERR_NVM_BLANK_MODE"; 269 case I40E_ERR_NOT_IMPLEMENTED: 270 return "I40E_ERR_NOT_IMPLEMENTED"; 271 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 272 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 273 case I40E_ERR_DIAG_TEST_FAILED: 274 return "I40E_ERR_DIAG_TEST_FAILED"; 275 case I40E_ERR_NOT_READY: 276 return "I40E_ERR_NOT_READY"; 277 case I40E_NOT_SUPPORTED: 278 return "I40E_NOT_SUPPORTED"; 279 case I40E_ERR_FIRMWARE_API_VERSION: 280 return "I40E_ERR_FIRMWARE_API_VERSION"; 281 } 282 283 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 284 return hw->err_str; 285 } 286 287 /** 288 * i40e_debug_aq 289 * @hw: debug mask related to admin queue 290 * @mask: debug mask 291 * @desc: pointer to admin queue descriptor 292 * @buffer: pointer to command buffer 293 * @buf_len: max length of buffer 294 * 295 * Dumps debug log about adminq command with descriptor contents. 296 **/ 297 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 298 void *buffer, u16 buf_len) 299 { 300 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 301 u16 len; 302 u8 *buf = (u8 *)buffer; 303 304 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 305 return; 306 307 len = le16_to_cpu(aq_desc->datalen); 308 309 i40e_debug(hw, mask, 310 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 311 le16_to_cpu(aq_desc->opcode), 312 le16_to_cpu(aq_desc->flags), 313 le16_to_cpu(aq_desc->datalen), 314 le16_to_cpu(aq_desc->retval)); 315 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 316 le32_to_cpu(aq_desc->cookie_high), 317 le32_to_cpu(aq_desc->cookie_low)); 318 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 319 le32_to_cpu(aq_desc->params.internal.param0), 320 le32_to_cpu(aq_desc->params.internal.param1)); 321 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 322 le32_to_cpu(aq_desc->params.external.addr_high), 323 le32_to_cpu(aq_desc->params.external.addr_low)); 324 325 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 326 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 327 if (buf_len < len) 328 len = buf_len; 329 /* write the full 16-byte chunks */ 330 if (hw->debug_mask & mask) { 331 char prefix[27]; 332 333 snprintf(prefix, sizeof(prefix), 334 "i40e %02x:%02x.%x: \t0x", 335 hw->bus.bus_id, 336 hw->bus.device, 337 hw->bus.func); 338 339 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 340 16, 1, buf, len, false); 341 } 342 } 343 } 344 345 /** 346 * i40e_check_asq_alive 347 * @hw: pointer to the hw struct 348 * 349 * Returns true if Queue is enabled else false. 350 **/ 351 bool i40e_check_asq_alive(struct i40e_hw *hw) 352 { 353 if (hw->aq.asq.len) 354 return !!(rd32(hw, hw->aq.asq.len) & 355 I40E_PF_ATQLEN_ATQENABLE_MASK); 356 else 357 return false; 358 } 359 360 /** 361 * i40e_aq_queue_shutdown 362 * @hw: pointer to the hw struct 363 * @unloading: is the driver unloading itself 364 * 365 * Tell the Firmware that we're shutting down the AdminQ and whether 366 * or not the driver is unloading as well. 367 **/ 368 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 369 bool unloading) 370 { 371 struct i40e_aq_desc desc; 372 struct i40e_aqc_queue_shutdown *cmd = 373 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 374 i40e_status status; 375 376 i40e_fill_default_direct_cmd_desc(&desc, 377 i40e_aqc_opc_queue_shutdown); 378 379 if (unloading) 380 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 381 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 382 383 return status; 384 } 385 386 /** 387 * i40e_aq_get_set_rss_lut 388 * @hw: pointer to the hardware structure 389 * @vsi_id: vsi fw index 390 * @pf_lut: for PF table set true, for VSI table set false 391 * @lut: pointer to the lut buffer provided by the caller 392 * @lut_size: size of the lut buffer 393 * @set: set true to set the table, false to get the table 394 * 395 * Internal function to get or set RSS look up table 396 **/ 397 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 398 u16 vsi_id, bool pf_lut, 399 u8 *lut, u16 lut_size, 400 bool set) 401 { 402 i40e_status status; 403 struct i40e_aq_desc desc; 404 struct i40e_aqc_get_set_rss_lut *cmd_resp = 405 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 406 407 if (set) 408 i40e_fill_default_direct_cmd_desc(&desc, 409 i40e_aqc_opc_set_rss_lut); 410 else 411 i40e_fill_default_direct_cmd_desc(&desc, 412 i40e_aqc_opc_get_rss_lut); 413 414 /* Indirect command */ 415 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 416 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 417 418 cmd_resp->vsi_id = 419 cpu_to_le16((u16)((vsi_id << 420 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 421 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 422 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 423 424 if (pf_lut) 425 cmd_resp->flags |= cpu_to_le16((u16) 426 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 427 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 428 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 429 else 430 cmd_resp->flags |= cpu_to_le16((u16) 431 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 432 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 433 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 434 435 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 436 437 return status; 438 } 439 440 /** 441 * i40e_aq_get_rss_lut 442 * @hw: pointer to the hardware structure 443 * @vsi_id: vsi fw index 444 * @pf_lut: for PF table set true, for VSI table set false 445 * @lut: pointer to the lut buffer provided by the caller 446 * @lut_size: size of the lut buffer 447 * 448 * get the RSS lookup table, PF or VSI type 449 **/ 450 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 451 bool pf_lut, u8 *lut, u16 lut_size) 452 { 453 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 454 false); 455 } 456 457 /** 458 * i40e_aq_set_rss_lut 459 * @hw: pointer to the hardware structure 460 * @vsi_id: vsi fw index 461 * @pf_lut: for PF table set true, for VSI table set false 462 * @lut: pointer to the lut buffer provided by the caller 463 * @lut_size: size of the lut buffer 464 * 465 * set the RSS lookup table, PF or VSI type 466 **/ 467 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 468 bool pf_lut, u8 *lut, u16 lut_size) 469 { 470 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 471 } 472 473 /** 474 * i40e_aq_get_set_rss_key 475 * @hw: pointer to the hw struct 476 * @vsi_id: vsi fw index 477 * @key: pointer to key info struct 478 * @set: set true to set the key, false to get the key 479 * 480 * get the RSS key per VSI 481 **/ 482 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 483 u16 vsi_id, 484 struct i40e_aqc_get_set_rss_key_data *key, 485 bool set) 486 { 487 i40e_status status; 488 struct i40e_aq_desc desc; 489 struct i40e_aqc_get_set_rss_key *cmd_resp = 490 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 491 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 492 493 if (set) 494 i40e_fill_default_direct_cmd_desc(&desc, 495 i40e_aqc_opc_set_rss_key); 496 else 497 i40e_fill_default_direct_cmd_desc(&desc, 498 i40e_aqc_opc_get_rss_key); 499 500 /* Indirect command */ 501 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 502 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 503 504 cmd_resp->vsi_id = 505 cpu_to_le16((u16)((vsi_id << 506 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 507 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 508 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 509 510 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 511 512 return status; 513 } 514 515 /** 516 * i40e_aq_get_rss_key 517 * @hw: pointer to the hw struct 518 * @vsi_id: vsi fw index 519 * @key: pointer to key info struct 520 * 521 **/ 522 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 523 u16 vsi_id, 524 struct i40e_aqc_get_set_rss_key_data *key) 525 { 526 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 527 } 528 529 /** 530 * i40e_aq_set_rss_key 531 * @hw: pointer to the hw struct 532 * @vsi_id: vsi fw index 533 * @key: pointer to key info struct 534 * 535 * set the RSS key per VSI 536 **/ 537 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 538 u16 vsi_id, 539 struct i40e_aqc_get_set_rss_key_data *key) 540 { 541 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 542 } 543 544 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 545 * hardware to a bit-field that can be used by SW to more easily determine the 546 * packet type. 547 * 548 * Macros are used to shorten the table lines and make this table human 549 * readable. 550 * 551 * We store the PTYPE in the top byte of the bit field - this is just so that 552 * we can check that the table doesn't have a row missing, as the index into 553 * the table should be the PTYPE. 554 * 555 * Typical work flow: 556 * 557 * IF NOT i40e_ptype_lookup[ptype].known 558 * THEN 559 * Packet is unknown 560 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 561 * Use the rest of the fields to look at the tunnels, inner protocols, etc 562 * ELSE 563 * Use the enum i40e_rx_l2_ptype to decode the packet type 564 * ENDIF 565 */ 566 567 /* macro to make the table lines short */ 568 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 569 { PTYPE, \ 570 1, \ 571 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 572 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 573 I40E_RX_PTYPE_##OUTER_FRAG, \ 574 I40E_RX_PTYPE_TUNNEL_##T, \ 575 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 576 I40E_RX_PTYPE_##TEF, \ 577 I40E_RX_PTYPE_INNER_PROT_##I, \ 578 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 579 580 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 581 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 582 583 /* shorter macros makes the table fit but are terse */ 584 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 585 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 586 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 587 588 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 589 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 590 /* L2 Packet types */ 591 I40E_PTT_UNUSED_ENTRY(0), 592 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 593 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 594 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 595 I40E_PTT_UNUSED_ENTRY(4), 596 I40E_PTT_UNUSED_ENTRY(5), 597 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 598 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 599 I40E_PTT_UNUSED_ENTRY(8), 600 I40E_PTT_UNUSED_ENTRY(9), 601 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 602 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 603 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 604 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 605 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 606 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 607 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 608 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 609 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 610 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 611 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 612 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 613 614 /* Non Tunneled IPv4 */ 615 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 616 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 617 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 618 I40E_PTT_UNUSED_ENTRY(25), 619 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 620 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 621 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 622 623 /* IPv4 --> IPv4 */ 624 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 625 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 626 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 627 I40E_PTT_UNUSED_ENTRY(32), 628 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 629 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 630 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 631 632 /* IPv4 --> IPv6 */ 633 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 634 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 635 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 636 I40E_PTT_UNUSED_ENTRY(39), 637 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 638 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 639 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 640 641 /* IPv4 --> GRE/NAT */ 642 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 643 644 /* IPv4 --> GRE/NAT --> IPv4 */ 645 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 646 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 647 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 648 I40E_PTT_UNUSED_ENTRY(47), 649 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 650 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 651 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 652 653 /* IPv4 --> GRE/NAT --> IPv6 */ 654 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 655 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 656 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 657 I40E_PTT_UNUSED_ENTRY(54), 658 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 659 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 660 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 661 662 /* IPv4 --> GRE/NAT --> MAC */ 663 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 664 665 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 666 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 667 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 668 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 669 I40E_PTT_UNUSED_ENTRY(62), 670 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 671 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 672 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 673 674 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 675 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 676 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 677 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 678 I40E_PTT_UNUSED_ENTRY(69), 679 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 680 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 681 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 682 683 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 684 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 685 686 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 687 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 688 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 689 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 690 I40E_PTT_UNUSED_ENTRY(77), 691 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 692 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 693 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 694 695 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 696 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 697 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 698 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 699 I40E_PTT_UNUSED_ENTRY(84), 700 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 701 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 702 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 703 704 /* Non Tunneled IPv6 */ 705 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 706 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 707 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 708 I40E_PTT_UNUSED_ENTRY(91), 709 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 710 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 711 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 712 713 /* IPv6 --> IPv4 */ 714 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 715 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 716 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 717 I40E_PTT_UNUSED_ENTRY(98), 718 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 719 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 720 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 721 722 /* IPv6 --> IPv6 */ 723 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 724 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 725 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 726 I40E_PTT_UNUSED_ENTRY(105), 727 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 728 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 729 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 730 731 /* IPv6 --> GRE/NAT */ 732 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 733 734 /* IPv6 --> GRE/NAT -> IPv4 */ 735 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 736 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 737 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 738 I40E_PTT_UNUSED_ENTRY(113), 739 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 740 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 741 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 742 743 /* IPv6 --> GRE/NAT -> IPv6 */ 744 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 745 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 746 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 747 I40E_PTT_UNUSED_ENTRY(120), 748 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 749 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 750 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 751 752 /* IPv6 --> GRE/NAT -> MAC */ 753 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 754 755 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 756 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 757 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 758 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 759 I40E_PTT_UNUSED_ENTRY(128), 760 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 761 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 762 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 763 764 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 765 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 766 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 767 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 768 I40E_PTT_UNUSED_ENTRY(135), 769 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 770 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 771 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 772 773 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 774 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 775 776 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 777 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 778 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 779 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 780 I40E_PTT_UNUSED_ENTRY(143), 781 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 782 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 783 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 784 785 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 786 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 787 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 788 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 789 I40E_PTT_UNUSED_ENTRY(150), 790 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 791 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 792 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 793 794 /* unused entries */ 795 I40E_PTT_UNUSED_ENTRY(154), 796 I40E_PTT_UNUSED_ENTRY(155), 797 I40E_PTT_UNUSED_ENTRY(156), 798 I40E_PTT_UNUSED_ENTRY(157), 799 I40E_PTT_UNUSED_ENTRY(158), 800 I40E_PTT_UNUSED_ENTRY(159), 801 802 I40E_PTT_UNUSED_ENTRY(160), 803 I40E_PTT_UNUSED_ENTRY(161), 804 I40E_PTT_UNUSED_ENTRY(162), 805 I40E_PTT_UNUSED_ENTRY(163), 806 I40E_PTT_UNUSED_ENTRY(164), 807 I40E_PTT_UNUSED_ENTRY(165), 808 I40E_PTT_UNUSED_ENTRY(166), 809 I40E_PTT_UNUSED_ENTRY(167), 810 I40E_PTT_UNUSED_ENTRY(168), 811 I40E_PTT_UNUSED_ENTRY(169), 812 813 I40E_PTT_UNUSED_ENTRY(170), 814 I40E_PTT_UNUSED_ENTRY(171), 815 I40E_PTT_UNUSED_ENTRY(172), 816 I40E_PTT_UNUSED_ENTRY(173), 817 I40E_PTT_UNUSED_ENTRY(174), 818 I40E_PTT_UNUSED_ENTRY(175), 819 I40E_PTT_UNUSED_ENTRY(176), 820 I40E_PTT_UNUSED_ENTRY(177), 821 I40E_PTT_UNUSED_ENTRY(178), 822 I40E_PTT_UNUSED_ENTRY(179), 823 824 I40E_PTT_UNUSED_ENTRY(180), 825 I40E_PTT_UNUSED_ENTRY(181), 826 I40E_PTT_UNUSED_ENTRY(182), 827 I40E_PTT_UNUSED_ENTRY(183), 828 I40E_PTT_UNUSED_ENTRY(184), 829 I40E_PTT_UNUSED_ENTRY(185), 830 I40E_PTT_UNUSED_ENTRY(186), 831 I40E_PTT_UNUSED_ENTRY(187), 832 I40E_PTT_UNUSED_ENTRY(188), 833 I40E_PTT_UNUSED_ENTRY(189), 834 835 I40E_PTT_UNUSED_ENTRY(190), 836 I40E_PTT_UNUSED_ENTRY(191), 837 I40E_PTT_UNUSED_ENTRY(192), 838 I40E_PTT_UNUSED_ENTRY(193), 839 I40E_PTT_UNUSED_ENTRY(194), 840 I40E_PTT_UNUSED_ENTRY(195), 841 I40E_PTT_UNUSED_ENTRY(196), 842 I40E_PTT_UNUSED_ENTRY(197), 843 I40E_PTT_UNUSED_ENTRY(198), 844 I40E_PTT_UNUSED_ENTRY(199), 845 846 I40E_PTT_UNUSED_ENTRY(200), 847 I40E_PTT_UNUSED_ENTRY(201), 848 I40E_PTT_UNUSED_ENTRY(202), 849 I40E_PTT_UNUSED_ENTRY(203), 850 I40E_PTT_UNUSED_ENTRY(204), 851 I40E_PTT_UNUSED_ENTRY(205), 852 I40E_PTT_UNUSED_ENTRY(206), 853 I40E_PTT_UNUSED_ENTRY(207), 854 I40E_PTT_UNUSED_ENTRY(208), 855 I40E_PTT_UNUSED_ENTRY(209), 856 857 I40E_PTT_UNUSED_ENTRY(210), 858 I40E_PTT_UNUSED_ENTRY(211), 859 I40E_PTT_UNUSED_ENTRY(212), 860 I40E_PTT_UNUSED_ENTRY(213), 861 I40E_PTT_UNUSED_ENTRY(214), 862 I40E_PTT_UNUSED_ENTRY(215), 863 I40E_PTT_UNUSED_ENTRY(216), 864 I40E_PTT_UNUSED_ENTRY(217), 865 I40E_PTT_UNUSED_ENTRY(218), 866 I40E_PTT_UNUSED_ENTRY(219), 867 868 I40E_PTT_UNUSED_ENTRY(220), 869 I40E_PTT_UNUSED_ENTRY(221), 870 I40E_PTT_UNUSED_ENTRY(222), 871 I40E_PTT_UNUSED_ENTRY(223), 872 I40E_PTT_UNUSED_ENTRY(224), 873 I40E_PTT_UNUSED_ENTRY(225), 874 I40E_PTT_UNUSED_ENTRY(226), 875 I40E_PTT_UNUSED_ENTRY(227), 876 I40E_PTT_UNUSED_ENTRY(228), 877 I40E_PTT_UNUSED_ENTRY(229), 878 879 I40E_PTT_UNUSED_ENTRY(230), 880 I40E_PTT_UNUSED_ENTRY(231), 881 I40E_PTT_UNUSED_ENTRY(232), 882 I40E_PTT_UNUSED_ENTRY(233), 883 I40E_PTT_UNUSED_ENTRY(234), 884 I40E_PTT_UNUSED_ENTRY(235), 885 I40E_PTT_UNUSED_ENTRY(236), 886 I40E_PTT_UNUSED_ENTRY(237), 887 I40E_PTT_UNUSED_ENTRY(238), 888 I40E_PTT_UNUSED_ENTRY(239), 889 890 I40E_PTT_UNUSED_ENTRY(240), 891 I40E_PTT_UNUSED_ENTRY(241), 892 I40E_PTT_UNUSED_ENTRY(242), 893 I40E_PTT_UNUSED_ENTRY(243), 894 I40E_PTT_UNUSED_ENTRY(244), 895 I40E_PTT_UNUSED_ENTRY(245), 896 I40E_PTT_UNUSED_ENTRY(246), 897 I40E_PTT_UNUSED_ENTRY(247), 898 I40E_PTT_UNUSED_ENTRY(248), 899 I40E_PTT_UNUSED_ENTRY(249), 900 901 I40E_PTT_UNUSED_ENTRY(250), 902 I40E_PTT_UNUSED_ENTRY(251), 903 I40E_PTT_UNUSED_ENTRY(252), 904 I40E_PTT_UNUSED_ENTRY(253), 905 I40E_PTT_UNUSED_ENTRY(254), 906 I40E_PTT_UNUSED_ENTRY(255) 907 }; 908 909 /** 910 * i40e_init_shared_code - Initialize the shared code 911 * @hw: pointer to hardware structure 912 * 913 * This assigns the MAC type and PHY code and inits the NVM. 914 * Does not touch the hardware. This function must be called prior to any 915 * other function in the shared code. The i40e_hw structure should be 916 * memset to 0 prior to calling this function. The following fields in 917 * hw structure should be filled in prior to calling this function: 918 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 919 * subsystem_vendor_id, and revision_id 920 **/ 921 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 922 { 923 i40e_status status = 0; 924 u32 port, ari, func_rid; 925 926 i40e_set_mac_type(hw); 927 928 switch (hw->mac.type) { 929 case I40E_MAC_XL710: 930 case I40E_MAC_X722: 931 break; 932 default: 933 return I40E_ERR_DEVICE_NOT_SUPPORTED; 934 } 935 936 hw->phy.get_link_info = true; 937 938 /* Determine port number and PF number*/ 939 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 940 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 941 hw->port = (u8)port; 942 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 943 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 944 func_rid = rd32(hw, I40E_PF_FUNC_RID); 945 if (ari) 946 hw->pf_id = (u8)(func_rid & 0xff); 947 else 948 hw->pf_id = (u8)(func_rid & 0x7); 949 950 if (hw->mac.type == I40E_MAC_X722) 951 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 952 953 status = i40e_init_nvm(hw); 954 return status; 955 } 956 957 /** 958 * i40e_aq_mac_address_read - Retrieve the MAC addresses 959 * @hw: pointer to the hw struct 960 * @flags: a return indicator of what addresses were added to the addr store 961 * @addrs: the requestor's mac addr store 962 * @cmd_details: pointer to command details structure or NULL 963 **/ 964 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 965 u16 *flags, 966 struct i40e_aqc_mac_address_read_data *addrs, 967 struct i40e_asq_cmd_details *cmd_details) 968 { 969 struct i40e_aq_desc desc; 970 struct i40e_aqc_mac_address_read *cmd_data = 971 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 972 i40e_status status; 973 974 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 975 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 976 977 status = i40e_asq_send_command(hw, &desc, addrs, 978 sizeof(*addrs), cmd_details); 979 *flags = le16_to_cpu(cmd_data->command_flags); 980 981 return status; 982 } 983 984 /** 985 * i40e_aq_mac_address_write - Change the MAC addresses 986 * @hw: pointer to the hw struct 987 * @flags: indicates which MAC to be written 988 * @mac_addr: address to write 989 * @cmd_details: pointer to command details structure or NULL 990 **/ 991 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 992 u16 flags, u8 *mac_addr, 993 struct i40e_asq_cmd_details *cmd_details) 994 { 995 struct i40e_aq_desc desc; 996 struct i40e_aqc_mac_address_write *cmd_data = 997 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 998 i40e_status status; 999 1000 i40e_fill_default_direct_cmd_desc(&desc, 1001 i40e_aqc_opc_mac_address_write); 1002 cmd_data->command_flags = cpu_to_le16(flags); 1003 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 1004 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 1005 ((u32)mac_addr[3] << 16) | 1006 ((u32)mac_addr[4] << 8) | 1007 mac_addr[5]); 1008 1009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1010 1011 return status; 1012 } 1013 1014 /** 1015 * i40e_get_mac_addr - get MAC address 1016 * @hw: pointer to the HW structure 1017 * @mac_addr: pointer to MAC address 1018 * 1019 * Reads the adapter's MAC address from register 1020 **/ 1021 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1022 { 1023 struct i40e_aqc_mac_address_read_data addrs; 1024 i40e_status status; 1025 u16 flags = 0; 1026 1027 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1028 1029 if (flags & I40E_AQC_LAN_ADDR_VALID) 1030 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1031 1032 return status; 1033 } 1034 1035 /** 1036 * i40e_get_port_mac_addr - get Port MAC address 1037 * @hw: pointer to the HW structure 1038 * @mac_addr: pointer to Port MAC address 1039 * 1040 * Reads the adapter's Port MAC address 1041 **/ 1042 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1043 { 1044 struct i40e_aqc_mac_address_read_data addrs; 1045 i40e_status status; 1046 u16 flags = 0; 1047 1048 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1049 if (status) 1050 return status; 1051 1052 if (flags & I40E_AQC_PORT_ADDR_VALID) 1053 ether_addr_copy(mac_addr, addrs.port_mac); 1054 else 1055 status = I40E_ERR_INVALID_MAC_ADDR; 1056 1057 return status; 1058 } 1059 1060 /** 1061 * i40e_pre_tx_queue_cfg - pre tx queue configure 1062 * @hw: pointer to the HW structure 1063 * @queue: target PF queue index 1064 * @enable: state change request 1065 * 1066 * Handles hw requirement to indicate intention to enable 1067 * or disable target queue. 1068 **/ 1069 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1070 { 1071 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1072 u32 reg_block = 0; 1073 u32 reg_val; 1074 1075 if (abs_queue_idx >= 128) { 1076 reg_block = abs_queue_idx / 128; 1077 abs_queue_idx %= 128; 1078 } 1079 1080 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1081 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1082 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1083 1084 if (enable) 1085 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1086 else 1087 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1088 1089 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1090 } 1091 1092 /** 1093 * i40e_read_pba_string - Reads part number string from EEPROM 1094 * @hw: pointer to hardware structure 1095 * @pba_num: stores the part number string from the EEPROM 1096 * @pba_num_size: part number string buffer length 1097 * 1098 * Reads the part number string from the EEPROM. 1099 **/ 1100 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1101 u32 pba_num_size) 1102 { 1103 i40e_status status = 0; 1104 u16 pba_word = 0; 1105 u16 pba_size = 0; 1106 u16 pba_ptr = 0; 1107 u16 i = 0; 1108 1109 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1110 if (status || (pba_word != 0xFAFA)) { 1111 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1112 return status; 1113 } 1114 1115 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1116 if (status) { 1117 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1118 return status; 1119 } 1120 1121 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1122 if (status) { 1123 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1124 return status; 1125 } 1126 1127 /* Subtract one to get PBA word count (PBA Size word is included in 1128 * total size) 1129 */ 1130 pba_size--; 1131 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1132 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1133 return I40E_ERR_PARAM; 1134 } 1135 1136 for (i = 0; i < pba_size; i++) { 1137 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1138 if (status) { 1139 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1140 return status; 1141 } 1142 1143 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1144 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1145 } 1146 pba_num[(pba_size * 2)] = '\0'; 1147 1148 return status; 1149 } 1150 1151 /** 1152 * i40e_get_media_type - Gets media type 1153 * @hw: pointer to the hardware structure 1154 **/ 1155 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1156 { 1157 enum i40e_media_type media; 1158 1159 switch (hw->phy.link_info.phy_type) { 1160 case I40E_PHY_TYPE_10GBASE_SR: 1161 case I40E_PHY_TYPE_10GBASE_LR: 1162 case I40E_PHY_TYPE_1000BASE_SX: 1163 case I40E_PHY_TYPE_1000BASE_LX: 1164 case I40E_PHY_TYPE_40GBASE_SR4: 1165 case I40E_PHY_TYPE_40GBASE_LR4: 1166 case I40E_PHY_TYPE_25GBASE_LR: 1167 case I40E_PHY_TYPE_25GBASE_SR: 1168 media = I40E_MEDIA_TYPE_FIBER; 1169 break; 1170 case I40E_PHY_TYPE_100BASE_TX: 1171 case I40E_PHY_TYPE_1000BASE_T: 1172 case I40E_PHY_TYPE_10GBASE_T: 1173 media = I40E_MEDIA_TYPE_BASET; 1174 break; 1175 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1176 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1177 case I40E_PHY_TYPE_10GBASE_CR1: 1178 case I40E_PHY_TYPE_40GBASE_CR4: 1179 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1180 case I40E_PHY_TYPE_40GBASE_AOC: 1181 case I40E_PHY_TYPE_10GBASE_AOC: 1182 case I40E_PHY_TYPE_25GBASE_CR: 1183 media = I40E_MEDIA_TYPE_DA; 1184 break; 1185 case I40E_PHY_TYPE_1000BASE_KX: 1186 case I40E_PHY_TYPE_10GBASE_KX4: 1187 case I40E_PHY_TYPE_10GBASE_KR: 1188 case I40E_PHY_TYPE_40GBASE_KR4: 1189 case I40E_PHY_TYPE_20GBASE_KR2: 1190 case I40E_PHY_TYPE_25GBASE_KR: 1191 media = I40E_MEDIA_TYPE_BACKPLANE; 1192 break; 1193 case I40E_PHY_TYPE_SGMII: 1194 case I40E_PHY_TYPE_XAUI: 1195 case I40E_PHY_TYPE_XFI: 1196 case I40E_PHY_TYPE_XLAUI: 1197 case I40E_PHY_TYPE_XLPPI: 1198 default: 1199 media = I40E_MEDIA_TYPE_UNKNOWN; 1200 break; 1201 } 1202 1203 return media; 1204 } 1205 1206 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1207 #define I40E_PF_RESET_WAIT_COUNT 200 1208 /** 1209 * i40e_pf_reset - Reset the PF 1210 * @hw: pointer to the hardware structure 1211 * 1212 * Assuming someone else has triggered a global reset, 1213 * assure the global reset is complete and then reset the PF 1214 **/ 1215 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1216 { 1217 u32 cnt = 0; 1218 u32 cnt1 = 0; 1219 u32 reg = 0; 1220 u32 grst_del; 1221 1222 /* Poll for Global Reset steady state in case of recent GRST. 1223 * The grst delay value is in 100ms units, and we'll wait a 1224 * couple counts longer to be sure we don't just miss the end. 1225 */ 1226 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1227 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1228 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1229 1230 /* It can take upto 15 secs for GRST steady state. 1231 * Bump it to 16 secs max to be safe. 1232 */ 1233 grst_del = grst_del * 20; 1234 1235 for (cnt = 0; cnt < grst_del; cnt++) { 1236 reg = rd32(hw, I40E_GLGEN_RSTAT); 1237 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1238 break; 1239 msleep(100); 1240 } 1241 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1242 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1243 return I40E_ERR_RESET_FAILED; 1244 } 1245 1246 /* Now Wait for the FW to be ready */ 1247 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1248 reg = rd32(hw, I40E_GLNVM_ULD); 1249 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1250 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1251 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1252 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1253 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1254 break; 1255 } 1256 usleep_range(10000, 20000); 1257 } 1258 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1259 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1260 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1261 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1262 return I40E_ERR_RESET_FAILED; 1263 } 1264 1265 /* If there was a Global Reset in progress when we got here, 1266 * we don't need to do the PF Reset 1267 */ 1268 if (!cnt) { 1269 if (hw->revision_id == 0) 1270 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1271 else 1272 cnt = I40E_PF_RESET_WAIT_COUNT; 1273 reg = rd32(hw, I40E_PFGEN_CTRL); 1274 wr32(hw, I40E_PFGEN_CTRL, 1275 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1276 for (; cnt; cnt--) { 1277 reg = rd32(hw, I40E_PFGEN_CTRL); 1278 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1279 break; 1280 usleep_range(1000, 2000); 1281 } 1282 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1283 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1284 return I40E_ERR_RESET_FAILED; 1285 } 1286 } 1287 1288 i40e_clear_pxe_mode(hw); 1289 1290 return 0; 1291 } 1292 1293 /** 1294 * i40e_clear_hw - clear out any left over hw state 1295 * @hw: pointer to the hw struct 1296 * 1297 * Clear queues and interrupts, typically called at init time, 1298 * but after the capabilities have been found so we know how many 1299 * queues and msix vectors have been allocated. 1300 **/ 1301 void i40e_clear_hw(struct i40e_hw *hw) 1302 { 1303 u32 num_queues, base_queue; 1304 u32 num_pf_int; 1305 u32 num_vf_int; 1306 u32 num_vfs; 1307 u32 i, j; 1308 u32 val; 1309 u32 eol = 0x7ff; 1310 1311 /* get number of interrupts, queues, and VFs */ 1312 val = rd32(hw, I40E_GLPCI_CNF2); 1313 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1314 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1315 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1316 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1317 1318 val = rd32(hw, I40E_PFLAN_QALLOC); 1319 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1320 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1321 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1322 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1323 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1324 num_queues = (j - base_queue) + 1; 1325 else 1326 num_queues = 0; 1327 1328 val = rd32(hw, I40E_PF_VT_PFALLOC); 1329 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1330 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1331 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1332 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1333 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1334 num_vfs = (j - i) + 1; 1335 else 1336 num_vfs = 0; 1337 1338 /* stop all the interrupts */ 1339 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1340 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1341 for (i = 0; i < num_pf_int - 2; i++) 1342 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1343 1344 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1345 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1346 wr32(hw, I40E_PFINT_LNKLST0, val); 1347 for (i = 0; i < num_pf_int - 2; i++) 1348 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1349 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1350 for (i = 0; i < num_vfs; i++) 1351 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1352 for (i = 0; i < num_vf_int - 2; i++) 1353 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1354 1355 /* warn the HW of the coming Tx disables */ 1356 for (i = 0; i < num_queues; i++) { 1357 u32 abs_queue_idx = base_queue + i; 1358 u32 reg_block = 0; 1359 1360 if (abs_queue_idx >= 128) { 1361 reg_block = abs_queue_idx / 128; 1362 abs_queue_idx %= 128; 1363 } 1364 1365 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1366 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1367 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1368 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1369 1370 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1371 } 1372 udelay(400); 1373 1374 /* stop all the queues */ 1375 for (i = 0; i < num_queues; i++) { 1376 wr32(hw, I40E_QINT_TQCTL(i), 0); 1377 wr32(hw, I40E_QTX_ENA(i), 0); 1378 wr32(hw, I40E_QINT_RQCTL(i), 0); 1379 wr32(hw, I40E_QRX_ENA(i), 0); 1380 } 1381 1382 /* short wait for all queue disables to settle */ 1383 udelay(50); 1384 } 1385 1386 /** 1387 * i40e_clear_pxe_mode - clear pxe operations mode 1388 * @hw: pointer to the hw struct 1389 * 1390 * Make sure all PXE mode settings are cleared, including things 1391 * like descriptor fetch/write-back mode. 1392 **/ 1393 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1394 { 1395 u32 reg; 1396 1397 if (i40e_check_asq_alive(hw)) 1398 i40e_aq_clear_pxe_mode(hw, NULL); 1399 1400 /* Clear single descriptor fetch/write-back mode */ 1401 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1402 1403 if (hw->revision_id == 0) { 1404 /* As a work around clear PXE_MODE instead of setting it */ 1405 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1406 } else { 1407 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1408 } 1409 } 1410 1411 /** 1412 * i40e_led_is_mine - helper to find matching led 1413 * @hw: pointer to the hw struct 1414 * @idx: index into GPIO registers 1415 * 1416 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1417 */ 1418 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1419 { 1420 u32 gpio_val = 0; 1421 u32 port; 1422 1423 if (!hw->func_caps.led[idx]) 1424 return 0; 1425 1426 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1427 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1428 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1429 1430 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1431 * if it is not our port then ignore 1432 */ 1433 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1434 (port != hw->port)) 1435 return 0; 1436 1437 return gpio_val; 1438 } 1439 1440 #define I40E_COMBINED_ACTIVITY 0xA 1441 #define I40E_FILTER_ACTIVITY 0xE 1442 #define I40E_LINK_ACTIVITY 0xC 1443 #define I40E_MAC_ACTIVITY 0xD 1444 #define I40E_LED0 22 1445 1446 /** 1447 * i40e_led_get - return current on/off mode 1448 * @hw: pointer to the hw struct 1449 * 1450 * The value returned is the 'mode' field as defined in the 1451 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1452 * values are variations of possible behaviors relating to 1453 * blink, link, and wire. 1454 **/ 1455 u32 i40e_led_get(struct i40e_hw *hw) 1456 { 1457 u32 current_mode = 0; 1458 u32 mode = 0; 1459 int i; 1460 1461 /* as per the documentation GPIO 22-29 are the LED 1462 * GPIO pins named LED0..LED7 1463 */ 1464 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1465 u32 gpio_val = i40e_led_is_mine(hw, i); 1466 1467 if (!gpio_val) 1468 continue; 1469 1470 /* ignore gpio LED src mode entries related to the activity 1471 * LEDs 1472 */ 1473 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1474 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1475 switch (current_mode) { 1476 case I40E_COMBINED_ACTIVITY: 1477 case I40E_FILTER_ACTIVITY: 1478 case I40E_MAC_ACTIVITY: 1479 continue; 1480 default: 1481 break; 1482 } 1483 1484 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1485 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1486 break; 1487 } 1488 1489 return mode; 1490 } 1491 1492 /** 1493 * i40e_led_set - set new on/off mode 1494 * @hw: pointer to the hw struct 1495 * @mode: 0=off, 0xf=on (else see manual for mode details) 1496 * @blink: true if the LED should blink when on, false if steady 1497 * 1498 * if this function is used to turn on the blink it should 1499 * be used to disable the blink when restoring the original state. 1500 **/ 1501 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1502 { 1503 u32 current_mode = 0; 1504 int i; 1505 1506 if (mode & 0xfffffff0) 1507 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1508 1509 /* as per the documentation GPIO 22-29 are the LED 1510 * GPIO pins named LED0..LED7 1511 */ 1512 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1513 u32 gpio_val = i40e_led_is_mine(hw, i); 1514 1515 if (!gpio_val) 1516 continue; 1517 1518 /* ignore gpio LED src mode entries related to the activity 1519 * LEDs 1520 */ 1521 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1522 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1523 switch (current_mode) { 1524 case I40E_COMBINED_ACTIVITY: 1525 case I40E_FILTER_ACTIVITY: 1526 case I40E_MAC_ACTIVITY: 1527 continue; 1528 default: 1529 break; 1530 } 1531 1532 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1533 /* this & is a bit of paranoia, but serves as a range check */ 1534 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1535 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1536 1537 if (mode == I40E_LINK_ACTIVITY) 1538 blink = false; 1539 1540 if (blink) 1541 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1542 else 1543 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1544 1545 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1546 break; 1547 } 1548 } 1549 1550 /* Admin command wrappers */ 1551 1552 /** 1553 * i40e_aq_get_phy_capabilities 1554 * @hw: pointer to the hw struct 1555 * @abilities: structure for PHY capabilities to be filled 1556 * @qualified_modules: report Qualified Modules 1557 * @report_init: report init capabilities (active are default) 1558 * @cmd_details: pointer to command details structure or NULL 1559 * 1560 * Returns the various PHY abilities supported on the Port. 1561 **/ 1562 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1563 bool qualified_modules, bool report_init, 1564 struct i40e_aq_get_phy_abilities_resp *abilities, 1565 struct i40e_asq_cmd_details *cmd_details) 1566 { 1567 struct i40e_aq_desc desc; 1568 i40e_status status; 1569 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1570 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1571 1572 if (!abilities) 1573 return I40E_ERR_PARAM; 1574 1575 do { 1576 i40e_fill_default_direct_cmd_desc(&desc, 1577 i40e_aqc_opc_get_phy_abilities); 1578 1579 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1580 if (abilities_size > I40E_AQ_LARGE_BUF) 1581 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1582 1583 if (qualified_modules) 1584 desc.params.external.param0 |= 1585 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1586 1587 if (report_init) 1588 desc.params.external.param0 |= 1589 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1590 1591 status = i40e_asq_send_command(hw, &desc, abilities, 1592 abilities_size, cmd_details); 1593 1594 if (status) 1595 break; 1596 1597 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) { 1598 status = I40E_ERR_UNKNOWN_PHY; 1599 break; 1600 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) { 1601 usleep_range(1000, 2000); 1602 total_delay++; 1603 status = I40E_ERR_TIMEOUT; 1604 } 1605 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) && 1606 (total_delay < max_delay)); 1607 1608 if (status) 1609 return status; 1610 1611 if (report_init) { 1612 if (hw->mac.type == I40E_MAC_XL710 && 1613 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1614 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1615 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1616 } else { 1617 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1618 hw->phy.phy_types |= 1619 ((u64)abilities->phy_type_ext << 32); 1620 } 1621 } 1622 1623 return status; 1624 } 1625 1626 /** 1627 * i40e_aq_set_phy_config 1628 * @hw: pointer to the hw struct 1629 * @config: structure with PHY configuration to be set 1630 * @cmd_details: pointer to command details structure or NULL 1631 * 1632 * Set the various PHY configuration parameters 1633 * supported on the Port.One or more of the Set PHY config parameters may be 1634 * ignored in an MFP mode as the PF may not have the privilege to set some 1635 * of the PHY Config parameters. This status will be indicated by the 1636 * command response. 1637 **/ 1638 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1639 struct i40e_aq_set_phy_config *config, 1640 struct i40e_asq_cmd_details *cmd_details) 1641 { 1642 struct i40e_aq_desc desc; 1643 struct i40e_aq_set_phy_config *cmd = 1644 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1645 enum i40e_status_code status; 1646 1647 if (!config) 1648 return I40E_ERR_PARAM; 1649 1650 i40e_fill_default_direct_cmd_desc(&desc, 1651 i40e_aqc_opc_set_phy_config); 1652 1653 *cmd = *config; 1654 1655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1656 1657 return status; 1658 } 1659 1660 /** 1661 * i40e_set_fc 1662 * @hw: pointer to the hw struct 1663 * 1664 * Set the requested flow control mode using set_phy_config. 1665 **/ 1666 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1667 bool atomic_restart) 1668 { 1669 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1670 struct i40e_aq_get_phy_abilities_resp abilities; 1671 struct i40e_aq_set_phy_config config; 1672 enum i40e_status_code status; 1673 u8 pause_mask = 0x0; 1674 1675 *aq_failures = 0x0; 1676 1677 switch (fc_mode) { 1678 case I40E_FC_FULL: 1679 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1680 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1681 break; 1682 case I40E_FC_RX_PAUSE: 1683 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1684 break; 1685 case I40E_FC_TX_PAUSE: 1686 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1687 break; 1688 default: 1689 break; 1690 } 1691 1692 /* Get the current phy config */ 1693 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1694 NULL); 1695 if (status) { 1696 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1697 return status; 1698 } 1699 1700 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1701 /* clear the old pause settings */ 1702 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1703 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1704 /* set the new abilities */ 1705 config.abilities |= pause_mask; 1706 /* If the abilities have changed, then set the new config */ 1707 if (config.abilities != abilities.abilities) { 1708 /* Auto restart link so settings take effect */ 1709 if (atomic_restart) 1710 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1711 /* Copy over all the old settings */ 1712 config.phy_type = abilities.phy_type; 1713 config.phy_type_ext = abilities.phy_type_ext; 1714 config.link_speed = abilities.link_speed; 1715 config.eee_capability = abilities.eee_capability; 1716 config.eeer = abilities.eeer_val; 1717 config.low_power_ctrl = abilities.d3_lpan; 1718 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1719 I40E_AQ_PHY_FEC_CONFIG_MASK; 1720 status = i40e_aq_set_phy_config(hw, &config, NULL); 1721 1722 if (status) 1723 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1724 } 1725 /* Update the link info */ 1726 status = i40e_update_link_info(hw); 1727 if (status) { 1728 /* Wait a little bit (on 40G cards it sometimes takes a really 1729 * long time for link to come back from the atomic reset) 1730 * and try once more 1731 */ 1732 msleep(1000); 1733 status = i40e_update_link_info(hw); 1734 } 1735 if (status) 1736 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1737 1738 return status; 1739 } 1740 1741 /** 1742 * i40e_aq_clear_pxe_mode 1743 * @hw: pointer to the hw struct 1744 * @cmd_details: pointer to command details structure or NULL 1745 * 1746 * Tell the firmware that the driver is taking over from PXE 1747 **/ 1748 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1749 struct i40e_asq_cmd_details *cmd_details) 1750 { 1751 i40e_status status; 1752 struct i40e_aq_desc desc; 1753 struct i40e_aqc_clear_pxe *cmd = 1754 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1755 1756 i40e_fill_default_direct_cmd_desc(&desc, 1757 i40e_aqc_opc_clear_pxe_mode); 1758 1759 cmd->rx_cnt = 0x2; 1760 1761 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1762 1763 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1764 1765 return status; 1766 } 1767 1768 /** 1769 * i40e_aq_set_link_restart_an 1770 * @hw: pointer to the hw struct 1771 * @enable_link: if true: enable link, if false: disable link 1772 * @cmd_details: pointer to command details structure or NULL 1773 * 1774 * Sets up the link and restarts the Auto-Negotiation over the link. 1775 **/ 1776 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1777 bool enable_link, 1778 struct i40e_asq_cmd_details *cmd_details) 1779 { 1780 struct i40e_aq_desc desc; 1781 struct i40e_aqc_set_link_restart_an *cmd = 1782 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1783 i40e_status status; 1784 1785 i40e_fill_default_direct_cmd_desc(&desc, 1786 i40e_aqc_opc_set_link_restart_an); 1787 1788 cmd->command = I40E_AQ_PHY_RESTART_AN; 1789 if (enable_link) 1790 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1791 else 1792 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1793 1794 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1795 1796 return status; 1797 } 1798 1799 /** 1800 * i40e_aq_get_link_info 1801 * @hw: pointer to the hw struct 1802 * @enable_lse: enable/disable LinkStatusEvent reporting 1803 * @link: pointer to link status structure - optional 1804 * @cmd_details: pointer to command details structure or NULL 1805 * 1806 * Returns the link status of the adapter. 1807 **/ 1808 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1809 bool enable_lse, struct i40e_link_status *link, 1810 struct i40e_asq_cmd_details *cmd_details) 1811 { 1812 struct i40e_aq_desc desc; 1813 struct i40e_aqc_get_link_status *resp = 1814 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1815 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1816 i40e_status status; 1817 bool tx_pause, rx_pause; 1818 u16 command_flags; 1819 1820 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1821 1822 if (enable_lse) 1823 command_flags = I40E_AQ_LSE_ENABLE; 1824 else 1825 command_flags = I40E_AQ_LSE_DISABLE; 1826 resp->command_flags = cpu_to_le16(command_flags); 1827 1828 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1829 1830 if (status) 1831 goto aq_get_link_info_exit; 1832 1833 /* save off old link status information */ 1834 hw->phy.link_info_old = *hw_link_info; 1835 1836 /* update link status */ 1837 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1838 hw->phy.media_type = i40e_get_media_type(hw); 1839 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1840 hw_link_info->link_info = resp->link_info; 1841 hw_link_info->an_info = resp->an_info; 1842 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1843 I40E_AQ_CONFIG_FEC_RS_ENA); 1844 hw_link_info->ext_info = resp->ext_info; 1845 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1846 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1847 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1848 1849 /* update fc info */ 1850 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1851 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1852 if (tx_pause & rx_pause) 1853 hw->fc.current_mode = I40E_FC_FULL; 1854 else if (tx_pause) 1855 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1856 else if (rx_pause) 1857 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1858 else 1859 hw->fc.current_mode = I40E_FC_NONE; 1860 1861 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1862 hw_link_info->crc_enable = true; 1863 else 1864 hw_link_info->crc_enable = false; 1865 1866 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1867 hw_link_info->lse_enable = true; 1868 else 1869 hw_link_info->lse_enable = false; 1870 1871 if ((hw->mac.type == I40E_MAC_XL710) && 1872 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1873 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1874 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1875 1876 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1877 hw->aq.api_min_ver >= 7) { 1878 __le32 tmp; 1879 1880 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1881 hw->phy.phy_types = le32_to_cpu(tmp); 1882 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1883 } 1884 1885 /* save link status information */ 1886 if (link) 1887 *link = *hw_link_info; 1888 1889 /* flag cleared so helper functions don't call AQ again */ 1890 hw->phy.get_link_info = false; 1891 1892 aq_get_link_info_exit: 1893 return status; 1894 } 1895 1896 /** 1897 * i40e_aq_set_phy_int_mask 1898 * @hw: pointer to the hw struct 1899 * @mask: interrupt mask to be set 1900 * @cmd_details: pointer to command details structure or NULL 1901 * 1902 * Set link interrupt mask. 1903 **/ 1904 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1905 u16 mask, 1906 struct i40e_asq_cmd_details *cmd_details) 1907 { 1908 struct i40e_aq_desc desc; 1909 struct i40e_aqc_set_phy_int_mask *cmd = 1910 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1911 i40e_status status; 1912 1913 i40e_fill_default_direct_cmd_desc(&desc, 1914 i40e_aqc_opc_set_phy_int_mask); 1915 1916 cmd->event_mask = cpu_to_le16(mask); 1917 1918 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1919 1920 return status; 1921 } 1922 1923 /** 1924 * i40e_aq_set_phy_debug 1925 * @hw: pointer to the hw struct 1926 * @cmd_flags: debug command flags 1927 * @cmd_details: pointer to command details structure or NULL 1928 * 1929 * Reset the external PHY. 1930 **/ 1931 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1932 struct i40e_asq_cmd_details *cmd_details) 1933 { 1934 struct i40e_aq_desc desc; 1935 struct i40e_aqc_set_phy_debug *cmd = 1936 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1937 i40e_status status; 1938 1939 i40e_fill_default_direct_cmd_desc(&desc, 1940 i40e_aqc_opc_set_phy_debug); 1941 1942 cmd->command_flags = cmd_flags; 1943 1944 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1945 1946 return status; 1947 } 1948 1949 /** 1950 * i40e_aq_add_vsi 1951 * @hw: pointer to the hw struct 1952 * @vsi_ctx: pointer to a vsi context struct 1953 * @cmd_details: pointer to command details structure or NULL 1954 * 1955 * Add a VSI context to the hardware. 1956 **/ 1957 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1958 struct i40e_vsi_context *vsi_ctx, 1959 struct i40e_asq_cmd_details *cmd_details) 1960 { 1961 struct i40e_aq_desc desc; 1962 struct i40e_aqc_add_get_update_vsi *cmd = 1963 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1964 struct i40e_aqc_add_get_update_vsi_completion *resp = 1965 (struct i40e_aqc_add_get_update_vsi_completion *) 1966 &desc.params.raw; 1967 i40e_status status; 1968 1969 i40e_fill_default_direct_cmd_desc(&desc, 1970 i40e_aqc_opc_add_vsi); 1971 1972 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1973 cmd->connection_type = vsi_ctx->connection_type; 1974 cmd->vf_id = vsi_ctx->vf_num; 1975 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1976 1977 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1978 1979 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1980 sizeof(vsi_ctx->info), cmd_details); 1981 1982 if (status) 1983 goto aq_add_vsi_exit; 1984 1985 vsi_ctx->seid = le16_to_cpu(resp->seid); 1986 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1987 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1988 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1989 1990 aq_add_vsi_exit: 1991 return status; 1992 } 1993 1994 /** 1995 * i40e_aq_set_default_vsi 1996 * @hw: pointer to the hw struct 1997 * @seid: vsi number 1998 * @cmd_details: pointer to command details structure or NULL 1999 **/ 2000 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 2001 u16 seid, 2002 struct i40e_asq_cmd_details *cmd_details) 2003 { 2004 struct i40e_aq_desc desc; 2005 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2006 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2007 &desc.params.raw; 2008 i40e_status status; 2009 2010 i40e_fill_default_direct_cmd_desc(&desc, 2011 i40e_aqc_opc_set_vsi_promiscuous_modes); 2012 2013 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2014 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2015 cmd->seid = cpu_to_le16(seid); 2016 2017 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2018 2019 return status; 2020 } 2021 2022 /** 2023 * i40e_aq_clear_default_vsi 2024 * @hw: pointer to the hw struct 2025 * @seid: vsi number 2026 * @cmd_details: pointer to command details structure or NULL 2027 **/ 2028 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2029 u16 seid, 2030 struct i40e_asq_cmd_details *cmd_details) 2031 { 2032 struct i40e_aq_desc desc; 2033 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2034 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2035 &desc.params.raw; 2036 i40e_status status; 2037 2038 i40e_fill_default_direct_cmd_desc(&desc, 2039 i40e_aqc_opc_set_vsi_promiscuous_modes); 2040 2041 cmd->promiscuous_flags = cpu_to_le16(0); 2042 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2043 cmd->seid = cpu_to_le16(seid); 2044 2045 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2046 2047 return status; 2048 } 2049 2050 /** 2051 * i40e_aq_set_vsi_unicast_promiscuous 2052 * @hw: pointer to the hw struct 2053 * @seid: vsi number 2054 * @set: set unicast promiscuous enable/disable 2055 * @cmd_details: pointer to command details structure or NULL 2056 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2057 **/ 2058 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2059 u16 seid, bool set, 2060 struct i40e_asq_cmd_details *cmd_details, 2061 bool rx_only_promisc) 2062 { 2063 struct i40e_aq_desc desc; 2064 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2065 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2066 i40e_status status; 2067 u16 flags = 0; 2068 2069 i40e_fill_default_direct_cmd_desc(&desc, 2070 i40e_aqc_opc_set_vsi_promiscuous_modes); 2071 2072 if (set) { 2073 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2074 if (rx_only_promisc && 2075 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2076 (hw->aq.api_maj_ver > 1))) 2077 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2078 } 2079 2080 cmd->promiscuous_flags = cpu_to_le16(flags); 2081 2082 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2083 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2084 (hw->aq.api_maj_ver > 1)) 2085 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX); 2086 2087 cmd->seid = cpu_to_le16(seid); 2088 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2089 2090 return status; 2091 } 2092 2093 /** 2094 * i40e_aq_set_vsi_multicast_promiscuous 2095 * @hw: pointer to the hw struct 2096 * @seid: vsi number 2097 * @set: set multicast promiscuous enable/disable 2098 * @cmd_details: pointer to command details structure or NULL 2099 **/ 2100 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2101 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2102 { 2103 struct i40e_aq_desc desc; 2104 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2105 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2106 i40e_status status; 2107 u16 flags = 0; 2108 2109 i40e_fill_default_direct_cmd_desc(&desc, 2110 i40e_aqc_opc_set_vsi_promiscuous_modes); 2111 2112 if (set) 2113 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2114 2115 cmd->promiscuous_flags = cpu_to_le16(flags); 2116 2117 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2118 2119 cmd->seid = cpu_to_le16(seid); 2120 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2121 2122 return status; 2123 } 2124 2125 /** 2126 * i40e_aq_set_vsi_mc_promisc_on_vlan 2127 * @hw: pointer to the hw struct 2128 * @seid: vsi number 2129 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2130 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2131 * @cmd_details: pointer to command details structure or NULL 2132 **/ 2133 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2134 u16 seid, bool enable, 2135 u16 vid, 2136 struct i40e_asq_cmd_details *cmd_details) 2137 { 2138 struct i40e_aq_desc desc; 2139 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2140 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2141 enum i40e_status_code status; 2142 u16 flags = 0; 2143 2144 i40e_fill_default_direct_cmd_desc(&desc, 2145 i40e_aqc_opc_set_vsi_promiscuous_modes); 2146 2147 if (enable) 2148 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2149 2150 cmd->promiscuous_flags = cpu_to_le16(flags); 2151 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2152 cmd->seid = cpu_to_le16(seid); 2153 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2154 2155 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2156 2157 return status; 2158 } 2159 2160 /** 2161 * i40e_aq_set_vsi_uc_promisc_on_vlan 2162 * @hw: pointer to the hw struct 2163 * @seid: vsi number 2164 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2165 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2166 * @cmd_details: pointer to command details structure or NULL 2167 **/ 2168 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2169 u16 seid, bool enable, 2170 u16 vid, 2171 struct i40e_asq_cmd_details *cmd_details) 2172 { 2173 struct i40e_aq_desc desc; 2174 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2175 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2176 enum i40e_status_code status; 2177 u16 flags = 0; 2178 2179 i40e_fill_default_direct_cmd_desc(&desc, 2180 i40e_aqc_opc_set_vsi_promiscuous_modes); 2181 2182 if (enable) 2183 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2184 2185 cmd->promiscuous_flags = cpu_to_le16(flags); 2186 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2187 cmd->seid = cpu_to_le16(seid); 2188 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2189 2190 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2191 2192 return status; 2193 } 2194 2195 /** 2196 * i40e_aq_set_vsi_bc_promisc_on_vlan 2197 * @hw: pointer to the hw struct 2198 * @seid: vsi number 2199 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2200 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2201 * @cmd_details: pointer to command details structure or NULL 2202 **/ 2203 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2204 u16 seid, bool enable, u16 vid, 2205 struct i40e_asq_cmd_details *cmd_details) 2206 { 2207 struct i40e_aq_desc desc; 2208 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2209 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2210 i40e_status status; 2211 u16 flags = 0; 2212 2213 i40e_fill_default_direct_cmd_desc(&desc, 2214 i40e_aqc_opc_set_vsi_promiscuous_modes); 2215 2216 if (enable) 2217 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2218 2219 cmd->promiscuous_flags = cpu_to_le16(flags); 2220 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2221 cmd->seid = cpu_to_le16(seid); 2222 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2223 2224 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2225 2226 return status; 2227 } 2228 2229 /** 2230 * i40e_aq_set_vsi_broadcast 2231 * @hw: pointer to the hw struct 2232 * @seid: vsi number 2233 * @set_filter: true to set filter, false to clear filter 2234 * @cmd_details: pointer to command details structure or NULL 2235 * 2236 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2237 **/ 2238 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2239 u16 seid, bool set_filter, 2240 struct i40e_asq_cmd_details *cmd_details) 2241 { 2242 struct i40e_aq_desc desc; 2243 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2244 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2245 i40e_status status; 2246 2247 i40e_fill_default_direct_cmd_desc(&desc, 2248 i40e_aqc_opc_set_vsi_promiscuous_modes); 2249 2250 if (set_filter) 2251 cmd->promiscuous_flags 2252 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2253 else 2254 cmd->promiscuous_flags 2255 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2256 2257 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2258 cmd->seid = cpu_to_le16(seid); 2259 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2260 2261 return status; 2262 } 2263 2264 /** 2265 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2266 * @hw: pointer to the hw struct 2267 * @seid: vsi number 2268 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2269 * @cmd_details: pointer to command details structure or NULL 2270 **/ 2271 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2272 u16 seid, bool enable, 2273 struct i40e_asq_cmd_details *cmd_details) 2274 { 2275 struct i40e_aq_desc desc; 2276 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2277 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2278 i40e_status status; 2279 u16 flags = 0; 2280 2281 i40e_fill_default_direct_cmd_desc(&desc, 2282 i40e_aqc_opc_set_vsi_promiscuous_modes); 2283 if (enable) 2284 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2285 2286 cmd->promiscuous_flags = cpu_to_le16(flags); 2287 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2288 cmd->seid = cpu_to_le16(seid); 2289 2290 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2291 2292 return status; 2293 } 2294 2295 /** 2296 * i40e_get_vsi_params - get VSI configuration info 2297 * @hw: pointer to the hw struct 2298 * @vsi_ctx: pointer to a vsi context struct 2299 * @cmd_details: pointer to command details structure or NULL 2300 **/ 2301 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2302 struct i40e_vsi_context *vsi_ctx, 2303 struct i40e_asq_cmd_details *cmd_details) 2304 { 2305 struct i40e_aq_desc desc; 2306 struct i40e_aqc_add_get_update_vsi *cmd = 2307 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2308 struct i40e_aqc_add_get_update_vsi_completion *resp = 2309 (struct i40e_aqc_add_get_update_vsi_completion *) 2310 &desc.params.raw; 2311 i40e_status status; 2312 2313 i40e_fill_default_direct_cmd_desc(&desc, 2314 i40e_aqc_opc_get_vsi_parameters); 2315 2316 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2317 2318 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2319 2320 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2321 sizeof(vsi_ctx->info), NULL); 2322 2323 if (status) 2324 goto aq_get_vsi_params_exit; 2325 2326 vsi_ctx->seid = le16_to_cpu(resp->seid); 2327 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2328 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2329 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2330 2331 aq_get_vsi_params_exit: 2332 return status; 2333 } 2334 2335 /** 2336 * i40e_aq_update_vsi_params 2337 * @hw: pointer to the hw struct 2338 * @vsi_ctx: pointer to a vsi context struct 2339 * @cmd_details: pointer to command details structure or NULL 2340 * 2341 * Update a VSI context. 2342 **/ 2343 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2344 struct i40e_vsi_context *vsi_ctx, 2345 struct i40e_asq_cmd_details *cmd_details) 2346 { 2347 struct i40e_aq_desc desc; 2348 struct i40e_aqc_add_get_update_vsi *cmd = 2349 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2350 struct i40e_aqc_add_get_update_vsi_completion *resp = 2351 (struct i40e_aqc_add_get_update_vsi_completion *) 2352 &desc.params.raw; 2353 i40e_status status; 2354 2355 i40e_fill_default_direct_cmd_desc(&desc, 2356 i40e_aqc_opc_update_vsi_parameters); 2357 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2358 2359 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2360 2361 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2362 sizeof(vsi_ctx->info), cmd_details); 2363 2364 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2365 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2366 2367 return status; 2368 } 2369 2370 /** 2371 * i40e_aq_get_switch_config 2372 * @hw: pointer to the hardware structure 2373 * @buf: pointer to the result buffer 2374 * @buf_size: length of input buffer 2375 * @start_seid: seid to start for the report, 0 == beginning 2376 * @cmd_details: pointer to command details structure or NULL 2377 * 2378 * Fill the buf with switch configuration returned from AdminQ command 2379 **/ 2380 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2381 struct i40e_aqc_get_switch_config_resp *buf, 2382 u16 buf_size, u16 *start_seid, 2383 struct i40e_asq_cmd_details *cmd_details) 2384 { 2385 struct i40e_aq_desc desc; 2386 struct i40e_aqc_switch_seid *scfg = 2387 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2388 i40e_status status; 2389 2390 i40e_fill_default_direct_cmd_desc(&desc, 2391 i40e_aqc_opc_get_switch_config); 2392 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2393 if (buf_size > I40E_AQ_LARGE_BUF) 2394 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2395 scfg->seid = cpu_to_le16(*start_seid); 2396 2397 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2398 *start_seid = le16_to_cpu(scfg->seid); 2399 2400 return status; 2401 } 2402 2403 /** 2404 * i40e_aq_set_switch_config 2405 * @hw: pointer to the hardware structure 2406 * @flags: bit flag values to set 2407 * @valid_flags: which bit flags to set 2408 * @cmd_details: pointer to command details structure or NULL 2409 * 2410 * Set switch configuration bits 2411 **/ 2412 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2413 u16 flags, 2414 u16 valid_flags, 2415 struct i40e_asq_cmd_details *cmd_details) 2416 { 2417 struct i40e_aq_desc desc; 2418 struct i40e_aqc_set_switch_config *scfg = 2419 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2420 enum i40e_status_code status; 2421 2422 i40e_fill_default_direct_cmd_desc(&desc, 2423 i40e_aqc_opc_set_switch_config); 2424 scfg->flags = cpu_to_le16(flags); 2425 scfg->valid_flags = cpu_to_le16(valid_flags); 2426 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2427 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 2428 scfg->first_tag = cpu_to_le16(hw->first_tag); 2429 scfg->second_tag = cpu_to_le16(hw->second_tag); 2430 } 2431 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2432 2433 return status; 2434 } 2435 2436 /** 2437 * i40e_aq_get_firmware_version 2438 * @hw: pointer to the hw struct 2439 * @fw_major_version: firmware major version 2440 * @fw_minor_version: firmware minor version 2441 * @fw_build: firmware build number 2442 * @api_major_version: major queue version 2443 * @api_minor_version: minor queue version 2444 * @cmd_details: pointer to command details structure or NULL 2445 * 2446 * Get the firmware version from the admin queue commands 2447 **/ 2448 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2449 u16 *fw_major_version, u16 *fw_minor_version, 2450 u32 *fw_build, 2451 u16 *api_major_version, u16 *api_minor_version, 2452 struct i40e_asq_cmd_details *cmd_details) 2453 { 2454 struct i40e_aq_desc desc; 2455 struct i40e_aqc_get_version *resp = 2456 (struct i40e_aqc_get_version *)&desc.params.raw; 2457 i40e_status status; 2458 2459 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2460 2461 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2462 2463 if (!status) { 2464 if (fw_major_version) 2465 *fw_major_version = le16_to_cpu(resp->fw_major); 2466 if (fw_minor_version) 2467 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2468 if (fw_build) 2469 *fw_build = le32_to_cpu(resp->fw_build); 2470 if (api_major_version) 2471 *api_major_version = le16_to_cpu(resp->api_major); 2472 if (api_minor_version) 2473 *api_minor_version = le16_to_cpu(resp->api_minor); 2474 } 2475 2476 return status; 2477 } 2478 2479 /** 2480 * i40e_aq_send_driver_version 2481 * @hw: pointer to the hw struct 2482 * @dv: driver's major, minor version 2483 * @cmd_details: pointer to command details structure or NULL 2484 * 2485 * Send the driver version to the firmware 2486 **/ 2487 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2488 struct i40e_driver_version *dv, 2489 struct i40e_asq_cmd_details *cmd_details) 2490 { 2491 struct i40e_aq_desc desc; 2492 struct i40e_aqc_driver_version *cmd = 2493 (struct i40e_aqc_driver_version *)&desc.params.raw; 2494 i40e_status status; 2495 u16 len; 2496 2497 if (dv == NULL) 2498 return I40E_ERR_PARAM; 2499 2500 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2501 2502 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2503 cmd->driver_major_ver = dv->major_version; 2504 cmd->driver_minor_ver = dv->minor_version; 2505 cmd->driver_build_ver = dv->build_version; 2506 cmd->driver_subbuild_ver = dv->subbuild_version; 2507 2508 len = 0; 2509 while (len < sizeof(dv->driver_string) && 2510 (dv->driver_string[len] < 0x80) && 2511 dv->driver_string[len]) 2512 len++; 2513 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2514 len, cmd_details); 2515 2516 return status; 2517 } 2518 2519 /** 2520 * i40e_get_link_status - get status of the HW network link 2521 * @hw: pointer to the hw struct 2522 * @link_up: pointer to bool (true/false = linkup/linkdown) 2523 * 2524 * Variable link_up true if link is up, false if link is down. 2525 * The variable link_up is invalid if returned value of status != 0 2526 * 2527 * Side effect: LinkStatusEvent reporting becomes enabled 2528 **/ 2529 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2530 { 2531 i40e_status status = 0; 2532 2533 if (hw->phy.get_link_info) { 2534 status = i40e_update_link_info(hw); 2535 2536 if (status) 2537 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2538 status); 2539 } 2540 2541 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2542 2543 return status; 2544 } 2545 2546 /** 2547 * i40e_updatelink_status - update status of the HW network link 2548 * @hw: pointer to the hw struct 2549 **/ 2550 i40e_status i40e_update_link_info(struct i40e_hw *hw) 2551 { 2552 struct i40e_aq_get_phy_abilities_resp abilities; 2553 i40e_status status = 0; 2554 2555 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2556 if (status) 2557 return status; 2558 2559 /* extra checking needed to ensure link info to user is timely */ 2560 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2561 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2562 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2563 status = i40e_aq_get_phy_capabilities(hw, false, false, 2564 &abilities, NULL); 2565 if (status) 2566 return status; 2567 2568 hw->phy.link_info.req_fec_info = 2569 abilities.fec_cfg_curr_mod_ext_info & 2570 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2571 2572 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2573 sizeof(hw->phy.link_info.module_type)); 2574 } 2575 2576 return status; 2577 } 2578 2579 /** 2580 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2581 * @hw: pointer to the hw struct 2582 * @uplink_seid: the MAC or other gizmo SEID 2583 * @downlink_seid: the VSI SEID 2584 * @enabled_tc: bitmap of TCs to be enabled 2585 * @default_port: true for default port VSI, false for control port 2586 * @veb_seid: pointer to where to put the resulting VEB SEID 2587 * @enable_stats: true to turn on VEB stats 2588 * @cmd_details: pointer to command details structure or NULL 2589 * 2590 * This asks the FW to add a VEB between the uplink and downlink 2591 * elements. If the uplink SEID is 0, this will be a floating VEB. 2592 **/ 2593 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2594 u16 downlink_seid, u8 enabled_tc, 2595 bool default_port, u16 *veb_seid, 2596 bool enable_stats, 2597 struct i40e_asq_cmd_details *cmd_details) 2598 { 2599 struct i40e_aq_desc desc; 2600 struct i40e_aqc_add_veb *cmd = 2601 (struct i40e_aqc_add_veb *)&desc.params.raw; 2602 struct i40e_aqc_add_veb_completion *resp = 2603 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2604 i40e_status status; 2605 u16 veb_flags = 0; 2606 2607 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2608 if (!!uplink_seid != !!downlink_seid) 2609 return I40E_ERR_PARAM; 2610 2611 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2612 2613 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2614 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2615 cmd->enable_tcs = enabled_tc; 2616 if (!uplink_seid) 2617 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2618 if (default_port) 2619 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2620 else 2621 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2622 2623 /* reverse logic here: set the bitflag to disable the stats */ 2624 if (!enable_stats) 2625 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2626 2627 cmd->veb_flags = cpu_to_le16(veb_flags); 2628 2629 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2630 2631 if (!status && veb_seid) 2632 *veb_seid = le16_to_cpu(resp->veb_seid); 2633 2634 return status; 2635 } 2636 2637 /** 2638 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2639 * @hw: pointer to the hw struct 2640 * @veb_seid: the SEID of the VEB to query 2641 * @switch_id: the uplink switch id 2642 * @floating: set to true if the VEB is floating 2643 * @statistic_index: index of the stats counter block for this VEB 2644 * @vebs_used: number of VEB's used by function 2645 * @vebs_free: total VEB's not reserved by any function 2646 * @cmd_details: pointer to command details structure or NULL 2647 * 2648 * This retrieves the parameters for a particular VEB, specified by 2649 * uplink_seid, and returns them to the caller. 2650 **/ 2651 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2652 u16 veb_seid, u16 *switch_id, 2653 bool *floating, u16 *statistic_index, 2654 u16 *vebs_used, u16 *vebs_free, 2655 struct i40e_asq_cmd_details *cmd_details) 2656 { 2657 struct i40e_aq_desc desc; 2658 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2659 (struct i40e_aqc_get_veb_parameters_completion *) 2660 &desc.params.raw; 2661 i40e_status status; 2662 2663 if (veb_seid == 0) 2664 return I40E_ERR_PARAM; 2665 2666 i40e_fill_default_direct_cmd_desc(&desc, 2667 i40e_aqc_opc_get_veb_parameters); 2668 cmd_resp->seid = cpu_to_le16(veb_seid); 2669 2670 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2671 if (status) 2672 goto get_veb_exit; 2673 2674 if (switch_id) 2675 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2676 if (statistic_index) 2677 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2678 if (vebs_used) 2679 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2680 if (vebs_free) 2681 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2682 if (floating) { 2683 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2684 2685 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2686 *floating = true; 2687 else 2688 *floating = false; 2689 } 2690 2691 get_veb_exit: 2692 return status; 2693 } 2694 2695 /** 2696 * i40e_aq_add_macvlan 2697 * @hw: pointer to the hw struct 2698 * @seid: VSI for the mac address 2699 * @mv_list: list of macvlans to be added 2700 * @count: length of the list 2701 * @cmd_details: pointer to command details structure or NULL 2702 * 2703 * Add MAC/VLAN addresses to the HW filtering 2704 **/ 2705 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2706 struct i40e_aqc_add_macvlan_element_data *mv_list, 2707 u16 count, struct i40e_asq_cmd_details *cmd_details) 2708 { 2709 struct i40e_aq_desc desc; 2710 struct i40e_aqc_macvlan *cmd = 2711 (struct i40e_aqc_macvlan *)&desc.params.raw; 2712 i40e_status status; 2713 u16 buf_size; 2714 int i; 2715 2716 if (count == 0 || !mv_list || !hw) 2717 return I40E_ERR_PARAM; 2718 2719 buf_size = count * sizeof(*mv_list); 2720 2721 /* prep the rest of the request */ 2722 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2723 cmd->num_addresses = cpu_to_le16(count); 2724 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2725 cmd->seid[1] = 0; 2726 cmd->seid[2] = 0; 2727 2728 for (i = 0; i < count; i++) 2729 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2730 mv_list[i].flags |= 2731 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2732 2733 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2734 if (buf_size > I40E_AQ_LARGE_BUF) 2735 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2736 2737 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2738 cmd_details); 2739 2740 return status; 2741 } 2742 2743 /** 2744 * i40e_aq_remove_macvlan 2745 * @hw: pointer to the hw struct 2746 * @seid: VSI for the mac address 2747 * @mv_list: list of macvlans to be removed 2748 * @count: length of the list 2749 * @cmd_details: pointer to command details structure or NULL 2750 * 2751 * Remove MAC/VLAN addresses from the HW filtering 2752 **/ 2753 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2754 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2755 u16 count, struct i40e_asq_cmd_details *cmd_details) 2756 { 2757 struct i40e_aq_desc desc; 2758 struct i40e_aqc_macvlan *cmd = 2759 (struct i40e_aqc_macvlan *)&desc.params.raw; 2760 i40e_status status; 2761 u16 buf_size; 2762 2763 if (count == 0 || !mv_list || !hw) 2764 return I40E_ERR_PARAM; 2765 2766 buf_size = count * sizeof(*mv_list); 2767 2768 /* prep the rest of the request */ 2769 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2770 cmd->num_addresses = cpu_to_le16(count); 2771 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2772 cmd->seid[1] = 0; 2773 cmd->seid[2] = 0; 2774 2775 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2776 if (buf_size > I40E_AQ_LARGE_BUF) 2777 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2778 2779 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2780 cmd_details); 2781 2782 return status; 2783 } 2784 2785 /** 2786 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2787 * @hw: pointer to the hw struct 2788 * @opcode: AQ opcode for add or delete mirror rule 2789 * @sw_seid: Switch SEID (to which rule refers) 2790 * @rule_type: Rule Type (ingress/egress/VLAN) 2791 * @id: Destination VSI SEID or Rule ID 2792 * @count: length of the list 2793 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2794 * @cmd_details: pointer to command details structure or NULL 2795 * @rule_id: Rule ID returned from FW 2796 * @rule_used: Number of rules used in internal switch 2797 * @rule_free: Number of rules free in internal switch 2798 * 2799 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2800 * VEBs/VEPA elements only 2801 **/ 2802 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2803 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2804 u16 count, __le16 *mr_list, 2805 struct i40e_asq_cmd_details *cmd_details, 2806 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2807 { 2808 struct i40e_aq_desc desc; 2809 struct i40e_aqc_add_delete_mirror_rule *cmd = 2810 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2811 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2812 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2813 i40e_status status; 2814 u16 buf_size; 2815 2816 buf_size = count * sizeof(*mr_list); 2817 2818 /* prep the rest of the request */ 2819 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2820 cmd->seid = cpu_to_le16(sw_seid); 2821 cmd->rule_type = cpu_to_le16(rule_type & 2822 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2823 cmd->num_entries = cpu_to_le16(count); 2824 /* Dest VSI for add, rule_id for delete */ 2825 cmd->destination = cpu_to_le16(id); 2826 if (mr_list) { 2827 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2828 I40E_AQ_FLAG_RD)); 2829 if (buf_size > I40E_AQ_LARGE_BUF) 2830 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2831 } 2832 2833 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2834 cmd_details); 2835 if (!status || 2836 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2837 if (rule_id) 2838 *rule_id = le16_to_cpu(resp->rule_id); 2839 if (rules_used) 2840 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2841 if (rules_free) 2842 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2843 } 2844 return status; 2845 } 2846 2847 /** 2848 * i40e_aq_add_mirrorrule - add a mirror rule 2849 * @hw: pointer to the hw struct 2850 * @sw_seid: Switch SEID (to which rule refers) 2851 * @rule_type: Rule Type (ingress/egress/VLAN) 2852 * @dest_vsi: SEID of VSI to which packets will be mirrored 2853 * @count: length of the list 2854 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2855 * @cmd_details: pointer to command details structure or NULL 2856 * @rule_id: Rule ID returned from FW 2857 * @rule_used: Number of rules used in internal switch 2858 * @rule_free: Number of rules free in internal switch 2859 * 2860 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2861 **/ 2862 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2863 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2864 struct i40e_asq_cmd_details *cmd_details, 2865 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2866 { 2867 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2868 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2869 if (count == 0 || !mr_list) 2870 return I40E_ERR_PARAM; 2871 } 2872 2873 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2874 rule_type, dest_vsi, count, mr_list, 2875 cmd_details, rule_id, rules_used, rules_free); 2876 } 2877 2878 /** 2879 * i40e_aq_delete_mirrorrule - delete a mirror rule 2880 * @hw: pointer to the hw struct 2881 * @sw_seid: Switch SEID (to which rule refers) 2882 * @rule_type: Rule Type (ingress/egress/VLAN) 2883 * @count: length of the list 2884 * @rule_id: Rule ID that is returned in the receive desc as part of 2885 * add_mirrorrule. 2886 * @mr_list: list of mirrored VLAN IDs to be removed 2887 * @cmd_details: pointer to command details structure or NULL 2888 * @rule_used: Number of rules used in internal switch 2889 * @rule_free: Number of rules free in internal switch 2890 * 2891 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2892 **/ 2893 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2894 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2895 struct i40e_asq_cmd_details *cmd_details, 2896 u16 *rules_used, u16 *rules_free) 2897 { 2898 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2899 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2900 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2901 * mirroring. For other rule_type, count and rule_type should 2902 * not matter. 2903 */ 2904 if (count == 0 || !mr_list) 2905 return I40E_ERR_PARAM; 2906 } 2907 2908 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2909 rule_type, rule_id, count, mr_list, 2910 cmd_details, NULL, rules_used, rules_free); 2911 } 2912 2913 /** 2914 * i40e_aq_send_msg_to_vf 2915 * @hw: pointer to the hardware structure 2916 * @vfid: VF id to send msg 2917 * @v_opcode: opcodes for VF-PF communication 2918 * @v_retval: return error code 2919 * @msg: pointer to the msg buffer 2920 * @msglen: msg length 2921 * @cmd_details: pointer to command details 2922 * 2923 * send msg to vf 2924 **/ 2925 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2926 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2927 struct i40e_asq_cmd_details *cmd_details) 2928 { 2929 struct i40e_aq_desc desc; 2930 struct i40e_aqc_pf_vf_message *cmd = 2931 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2932 i40e_status status; 2933 2934 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2935 cmd->id = cpu_to_le32(vfid); 2936 desc.cookie_high = cpu_to_le32(v_opcode); 2937 desc.cookie_low = cpu_to_le32(v_retval); 2938 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2939 if (msglen) { 2940 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2941 I40E_AQ_FLAG_RD)); 2942 if (msglen > I40E_AQ_LARGE_BUF) 2943 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2944 desc.datalen = cpu_to_le16(msglen); 2945 } 2946 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2947 2948 return status; 2949 } 2950 2951 /** 2952 * i40e_aq_debug_read_register 2953 * @hw: pointer to the hw struct 2954 * @reg_addr: register address 2955 * @reg_val: register value 2956 * @cmd_details: pointer to command details structure or NULL 2957 * 2958 * Read the register using the admin queue commands 2959 **/ 2960 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2961 u32 reg_addr, u64 *reg_val, 2962 struct i40e_asq_cmd_details *cmd_details) 2963 { 2964 struct i40e_aq_desc desc; 2965 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2966 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2967 i40e_status status; 2968 2969 if (reg_val == NULL) 2970 return I40E_ERR_PARAM; 2971 2972 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2973 2974 cmd_resp->address = cpu_to_le32(reg_addr); 2975 2976 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2977 2978 if (!status) { 2979 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2980 (u64)le32_to_cpu(cmd_resp->value_low); 2981 } 2982 2983 return status; 2984 } 2985 2986 /** 2987 * i40e_aq_debug_write_register 2988 * @hw: pointer to the hw struct 2989 * @reg_addr: register address 2990 * @reg_val: register value 2991 * @cmd_details: pointer to command details structure or NULL 2992 * 2993 * Write to a register using the admin queue commands 2994 **/ 2995 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2996 u32 reg_addr, u64 reg_val, 2997 struct i40e_asq_cmd_details *cmd_details) 2998 { 2999 struct i40e_aq_desc desc; 3000 struct i40e_aqc_debug_reg_read_write *cmd = 3001 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3002 i40e_status status; 3003 3004 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3005 3006 cmd->address = cpu_to_le32(reg_addr); 3007 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 3008 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 3009 3010 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3011 3012 return status; 3013 } 3014 3015 /** 3016 * i40e_aq_request_resource 3017 * @hw: pointer to the hw struct 3018 * @resource: resource id 3019 * @access: access type 3020 * @sdp_number: resource number 3021 * @timeout: the maximum time in ms that the driver may hold the resource 3022 * @cmd_details: pointer to command details structure or NULL 3023 * 3024 * requests common resource using the admin queue commands 3025 **/ 3026 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 3027 enum i40e_aq_resources_ids resource, 3028 enum i40e_aq_resource_access_type access, 3029 u8 sdp_number, u64 *timeout, 3030 struct i40e_asq_cmd_details *cmd_details) 3031 { 3032 struct i40e_aq_desc desc; 3033 struct i40e_aqc_request_resource *cmd_resp = 3034 (struct i40e_aqc_request_resource *)&desc.params.raw; 3035 i40e_status status; 3036 3037 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3038 3039 cmd_resp->resource_id = cpu_to_le16(resource); 3040 cmd_resp->access_type = cpu_to_le16(access); 3041 cmd_resp->resource_number = cpu_to_le32(sdp_number); 3042 3043 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3044 /* The completion specifies the maximum time in ms that the driver 3045 * may hold the resource in the Timeout field. 3046 * If the resource is held by someone else, the command completes with 3047 * busy return value and the timeout field indicates the maximum time 3048 * the current owner of the resource has to free it. 3049 */ 3050 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3051 *timeout = le32_to_cpu(cmd_resp->timeout); 3052 3053 return status; 3054 } 3055 3056 /** 3057 * i40e_aq_release_resource 3058 * @hw: pointer to the hw struct 3059 * @resource: resource id 3060 * @sdp_number: resource number 3061 * @cmd_details: pointer to command details structure or NULL 3062 * 3063 * release common resource using the admin queue commands 3064 **/ 3065 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 3066 enum i40e_aq_resources_ids resource, 3067 u8 sdp_number, 3068 struct i40e_asq_cmd_details *cmd_details) 3069 { 3070 struct i40e_aq_desc desc; 3071 struct i40e_aqc_request_resource *cmd = 3072 (struct i40e_aqc_request_resource *)&desc.params.raw; 3073 i40e_status status; 3074 3075 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3076 3077 cmd->resource_id = cpu_to_le16(resource); 3078 cmd->resource_number = cpu_to_le32(sdp_number); 3079 3080 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3081 3082 return status; 3083 } 3084 3085 /** 3086 * i40e_aq_read_nvm 3087 * @hw: pointer to the hw struct 3088 * @module_pointer: module pointer location in words from the NVM beginning 3089 * @offset: byte offset from the module beginning 3090 * @length: length of the section to be read (in bytes from the offset) 3091 * @data: command buffer (size [bytes] = length) 3092 * @last_command: tells if this is the last command in a series 3093 * @cmd_details: pointer to command details structure or NULL 3094 * 3095 * Read the NVM using the admin queue commands 3096 **/ 3097 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3098 u32 offset, u16 length, void *data, 3099 bool last_command, 3100 struct i40e_asq_cmd_details *cmd_details) 3101 { 3102 struct i40e_aq_desc desc; 3103 struct i40e_aqc_nvm_update *cmd = 3104 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3105 i40e_status status; 3106 3107 /* In offset the highest byte must be zeroed. */ 3108 if (offset & 0xFF000000) { 3109 status = I40E_ERR_PARAM; 3110 goto i40e_aq_read_nvm_exit; 3111 } 3112 3113 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3114 3115 /* If this is the last command in a series, set the proper flag. */ 3116 if (last_command) 3117 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3118 cmd->module_pointer = module_pointer; 3119 cmd->offset = cpu_to_le32(offset); 3120 cmd->length = cpu_to_le16(length); 3121 3122 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3123 if (length > I40E_AQ_LARGE_BUF) 3124 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3125 3126 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3127 3128 i40e_aq_read_nvm_exit: 3129 return status; 3130 } 3131 3132 /** 3133 * i40e_aq_erase_nvm 3134 * @hw: pointer to the hw struct 3135 * @module_pointer: module pointer location in words from the NVM beginning 3136 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3137 * @length: length of the section to be erased (expressed in 4 KB) 3138 * @last_command: tells if this is the last command in a series 3139 * @cmd_details: pointer to command details structure or NULL 3140 * 3141 * Erase the NVM sector using the admin queue commands 3142 **/ 3143 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3144 u32 offset, u16 length, bool last_command, 3145 struct i40e_asq_cmd_details *cmd_details) 3146 { 3147 struct i40e_aq_desc desc; 3148 struct i40e_aqc_nvm_update *cmd = 3149 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3150 i40e_status status; 3151 3152 /* In offset the highest byte must be zeroed. */ 3153 if (offset & 0xFF000000) { 3154 status = I40E_ERR_PARAM; 3155 goto i40e_aq_erase_nvm_exit; 3156 } 3157 3158 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3159 3160 /* If this is the last command in a series, set the proper flag. */ 3161 if (last_command) 3162 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3163 cmd->module_pointer = module_pointer; 3164 cmd->offset = cpu_to_le32(offset); 3165 cmd->length = cpu_to_le16(length); 3166 3167 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3168 3169 i40e_aq_erase_nvm_exit: 3170 return status; 3171 } 3172 3173 /** 3174 * i40e_parse_discover_capabilities 3175 * @hw: pointer to the hw struct 3176 * @buff: pointer to a buffer containing device/function capability records 3177 * @cap_count: number of capability records in the list 3178 * @list_type_opc: type of capabilities list to parse 3179 * 3180 * Parse the device/function capabilities list. 3181 **/ 3182 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3183 u32 cap_count, 3184 enum i40e_admin_queue_opc list_type_opc) 3185 { 3186 struct i40e_aqc_list_capabilities_element_resp *cap; 3187 u32 valid_functions, num_functions; 3188 u32 number, logical_id, phys_id; 3189 struct i40e_hw_capabilities *p; 3190 u8 major_rev; 3191 u32 i = 0; 3192 u16 id; 3193 3194 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3195 3196 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3197 p = &hw->dev_caps; 3198 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3199 p = &hw->func_caps; 3200 else 3201 return; 3202 3203 for (i = 0; i < cap_count; i++, cap++) { 3204 id = le16_to_cpu(cap->id); 3205 number = le32_to_cpu(cap->number); 3206 logical_id = le32_to_cpu(cap->logical_id); 3207 phys_id = le32_to_cpu(cap->phys_id); 3208 major_rev = cap->major_rev; 3209 3210 switch (id) { 3211 case I40E_AQ_CAP_ID_SWITCH_MODE: 3212 p->switch_mode = number; 3213 break; 3214 case I40E_AQ_CAP_ID_MNG_MODE: 3215 p->management_mode = number; 3216 if (major_rev > 1) { 3217 p->mng_protocols_over_mctp = logical_id; 3218 i40e_debug(hw, I40E_DEBUG_INIT, 3219 "HW Capability: Protocols over MCTP = %d\n", 3220 p->mng_protocols_over_mctp); 3221 } else { 3222 p->mng_protocols_over_mctp = 0; 3223 } 3224 break; 3225 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3226 p->npar_enable = number; 3227 break; 3228 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3229 p->os2bmc = number; 3230 break; 3231 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3232 p->valid_functions = number; 3233 break; 3234 case I40E_AQ_CAP_ID_SRIOV: 3235 if (number == 1) 3236 p->sr_iov_1_1 = true; 3237 break; 3238 case I40E_AQ_CAP_ID_VF: 3239 p->num_vfs = number; 3240 p->vf_base_id = logical_id; 3241 break; 3242 case I40E_AQ_CAP_ID_VMDQ: 3243 if (number == 1) 3244 p->vmdq = true; 3245 break; 3246 case I40E_AQ_CAP_ID_8021QBG: 3247 if (number == 1) 3248 p->evb_802_1_qbg = true; 3249 break; 3250 case I40E_AQ_CAP_ID_8021QBR: 3251 if (number == 1) 3252 p->evb_802_1_qbh = true; 3253 break; 3254 case I40E_AQ_CAP_ID_VSI: 3255 p->num_vsis = number; 3256 break; 3257 case I40E_AQ_CAP_ID_DCB: 3258 if (number == 1) { 3259 p->dcb = true; 3260 p->enabled_tcmap = logical_id; 3261 p->maxtc = phys_id; 3262 } 3263 break; 3264 case I40E_AQ_CAP_ID_FCOE: 3265 if (number == 1) 3266 p->fcoe = true; 3267 break; 3268 case I40E_AQ_CAP_ID_ISCSI: 3269 if (number == 1) 3270 p->iscsi = true; 3271 break; 3272 case I40E_AQ_CAP_ID_RSS: 3273 p->rss = true; 3274 p->rss_table_size = number; 3275 p->rss_table_entry_width = logical_id; 3276 break; 3277 case I40E_AQ_CAP_ID_RXQ: 3278 p->num_rx_qp = number; 3279 p->base_queue = phys_id; 3280 break; 3281 case I40E_AQ_CAP_ID_TXQ: 3282 p->num_tx_qp = number; 3283 p->base_queue = phys_id; 3284 break; 3285 case I40E_AQ_CAP_ID_MSIX: 3286 p->num_msix_vectors = number; 3287 i40e_debug(hw, I40E_DEBUG_INIT, 3288 "HW Capability: MSIX vector count = %d\n", 3289 p->num_msix_vectors); 3290 break; 3291 case I40E_AQ_CAP_ID_VF_MSIX: 3292 p->num_msix_vectors_vf = number; 3293 break; 3294 case I40E_AQ_CAP_ID_FLEX10: 3295 if (major_rev == 1) { 3296 if (number == 1) { 3297 p->flex10_enable = true; 3298 p->flex10_capable = true; 3299 } 3300 } else { 3301 /* Capability revision >= 2 */ 3302 if (number & 1) 3303 p->flex10_enable = true; 3304 if (number & 2) 3305 p->flex10_capable = true; 3306 } 3307 p->flex10_mode = logical_id; 3308 p->flex10_status = phys_id; 3309 break; 3310 case I40E_AQ_CAP_ID_CEM: 3311 if (number == 1) 3312 p->mgmt_cem = true; 3313 break; 3314 case I40E_AQ_CAP_ID_IWARP: 3315 if (number == 1) 3316 p->iwarp = true; 3317 break; 3318 case I40E_AQ_CAP_ID_LED: 3319 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3320 p->led[phys_id] = true; 3321 break; 3322 case I40E_AQ_CAP_ID_SDP: 3323 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3324 p->sdp[phys_id] = true; 3325 break; 3326 case I40E_AQ_CAP_ID_MDIO: 3327 if (number == 1) { 3328 p->mdio_port_num = phys_id; 3329 p->mdio_port_mode = logical_id; 3330 } 3331 break; 3332 case I40E_AQ_CAP_ID_1588: 3333 if (number == 1) 3334 p->ieee_1588 = true; 3335 break; 3336 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3337 p->fd = true; 3338 p->fd_filters_guaranteed = number; 3339 p->fd_filters_best_effort = logical_id; 3340 break; 3341 case I40E_AQ_CAP_ID_WSR_PROT: 3342 p->wr_csr_prot = (u64)number; 3343 p->wr_csr_prot |= (u64)logical_id << 32; 3344 break; 3345 case I40E_AQ_CAP_ID_NVM_MGMT: 3346 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3347 p->sec_rev_disabled = true; 3348 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3349 p->update_disabled = true; 3350 break; 3351 default: 3352 break; 3353 } 3354 } 3355 3356 if (p->fcoe) 3357 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3358 3359 /* Software override ensuring FCoE is disabled if npar or mfp 3360 * mode because it is not supported in these modes. 3361 */ 3362 if (p->npar_enable || p->flex10_enable) 3363 p->fcoe = false; 3364 3365 /* count the enabled ports (aka the "not disabled" ports) */ 3366 hw->num_ports = 0; 3367 for (i = 0; i < 4; i++) { 3368 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3369 u64 port_cfg = 0; 3370 3371 /* use AQ read to get the physical register offset instead 3372 * of the port relative offset 3373 */ 3374 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3375 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3376 hw->num_ports++; 3377 } 3378 3379 valid_functions = p->valid_functions; 3380 num_functions = 0; 3381 while (valid_functions) { 3382 if (valid_functions & 1) 3383 num_functions++; 3384 valid_functions >>= 1; 3385 } 3386 3387 /* partition id is 1-based, and functions are evenly spread 3388 * across the ports as partitions 3389 */ 3390 if (hw->num_ports != 0) { 3391 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3392 hw->num_partitions = num_functions / hw->num_ports; 3393 } 3394 3395 /* additional HW specific goodies that might 3396 * someday be HW version specific 3397 */ 3398 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3399 } 3400 3401 /** 3402 * i40e_aq_discover_capabilities 3403 * @hw: pointer to the hw struct 3404 * @buff: a virtual buffer to hold the capabilities 3405 * @buff_size: Size of the virtual buffer 3406 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3407 * @list_type_opc: capabilities type to discover - pass in the command opcode 3408 * @cmd_details: pointer to command details structure or NULL 3409 * 3410 * Get the device capabilities descriptions from the firmware 3411 **/ 3412 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3413 void *buff, u16 buff_size, u16 *data_size, 3414 enum i40e_admin_queue_opc list_type_opc, 3415 struct i40e_asq_cmd_details *cmd_details) 3416 { 3417 struct i40e_aqc_list_capabilites *cmd; 3418 struct i40e_aq_desc desc; 3419 i40e_status status = 0; 3420 3421 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3422 3423 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3424 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3425 status = I40E_ERR_PARAM; 3426 goto exit; 3427 } 3428 3429 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3430 3431 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3432 if (buff_size > I40E_AQ_LARGE_BUF) 3433 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3434 3435 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3436 *data_size = le16_to_cpu(desc.datalen); 3437 3438 if (status) 3439 goto exit; 3440 3441 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3442 list_type_opc); 3443 3444 exit: 3445 return status; 3446 } 3447 3448 /** 3449 * i40e_aq_update_nvm 3450 * @hw: pointer to the hw struct 3451 * @module_pointer: module pointer location in words from the NVM beginning 3452 * @offset: byte offset from the module beginning 3453 * @length: length of the section to be written (in bytes from the offset) 3454 * @data: command buffer (size [bytes] = length) 3455 * @last_command: tells if this is the last command in a series 3456 * @cmd_details: pointer to command details structure or NULL 3457 * 3458 * Update the NVM using the admin queue commands 3459 **/ 3460 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3461 u32 offset, u16 length, void *data, 3462 bool last_command, 3463 struct i40e_asq_cmd_details *cmd_details) 3464 { 3465 struct i40e_aq_desc desc; 3466 struct i40e_aqc_nvm_update *cmd = 3467 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3468 i40e_status status; 3469 3470 /* In offset the highest byte must be zeroed. */ 3471 if (offset & 0xFF000000) { 3472 status = I40E_ERR_PARAM; 3473 goto i40e_aq_update_nvm_exit; 3474 } 3475 3476 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3477 3478 /* If this is the last command in a series, set the proper flag. */ 3479 if (last_command) 3480 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3481 cmd->module_pointer = module_pointer; 3482 cmd->offset = cpu_to_le32(offset); 3483 cmd->length = cpu_to_le16(length); 3484 3485 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3486 if (length > I40E_AQ_LARGE_BUF) 3487 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3488 3489 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3490 3491 i40e_aq_update_nvm_exit: 3492 return status; 3493 } 3494 3495 /** 3496 * i40e_aq_get_lldp_mib 3497 * @hw: pointer to the hw struct 3498 * @bridge_type: type of bridge requested 3499 * @mib_type: Local, Remote or both Local and Remote MIBs 3500 * @buff: pointer to a user supplied buffer to store the MIB block 3501 * @buff_size: size of the buffer (in bytes) 3502 * @local_len : length of the returned Local LLDP MIB 3503 * @remote_len: length of the returned Remote LLDP MIB 3504 * @cmd_details: pointer to command details structure or NULL 3505 * 3506 * Requests the complete LLDP MIB (entire packet). 3507 **/ 3508 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3509 u8 mib_type, void *buff, u16 buff_size, 3510 u16 *local_len, u16 *remote_len, 3511 struct i40e_asq_cmd_details *cmd_details) 3512 { 3513 struct i40e_aq_desc desc; 3514 struct i40e_aqc_lldp_get_mib *cmd = 3515 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3516 struct i40e_aqc_lldp_get_mib *resp = 3517 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3518 i40e_status status; 3519 3520 if (buff_size == 0 || !buff) 3521 return I40E_ERR_PARAM; 3522 3523 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3524 /* Indirect Command */ 3525 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3526 3527 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3528 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3529 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3530 3531 desc.datalen = cpu_to_le16(buff_size); 3532 3533 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3534 if (buff_size > I40E_AQ_LARGE_BUF) 3535 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3536 3537 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3538 if (!status) { 3539 if (local_len != NULL) 3540 *local_len = le16_to_cpu(resp->local_len); 3541 if (remote_len != NULL) 3542 *remote_len = le16_to_cpu(resp->remote_len); 3543 } 3544 3545 return status; 3546 } 3547 3548 /** 3549 * i40e_aq_cfg_lldp_mib_change_event 3550 * @hw: pointer to the hw struct 3551 * @enable_update: Enable or Disable event posting 3552 * @cmd_details: pointer to command details structure or NULL 3553 * 3554 * Enable or Disable posting of an event on ARQ when LLDP MIB 3555 * associated with the interface changes 3556 **/ 3557 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3558 bool enable_update, 3559 struct i40e_asq_cmd_details *cmd_details) 3560 { 3561 struct i40e_aq_desc desc; 3562 struct i40e_aqc_lldp_update_mib *cmd = 3563 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3564 i40e_status status; 3565 3566 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3567 3568 if (!enable_update) 3569 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3570 3571 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3572 3573 return status; 3574 } 3575 3576 /** 3577 * i40e_aq_stop_lldp 3578 * @hw: pointer to the hw struct 3579 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3580 * @cmd_details: pointer to command details structure or NULL 3581 * 3582 * Stop or Shutdown the embedded LLDP Agent 3583 **/ 3584 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3585 struct i40e_asq_cmd_details *cmd_details) 3586 { 3587 struct i40e_aq_desc desc; 3588 struct i40e_aqc_lldp_stop *cmd = 3589 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3590 i40e_status status; 3591 3592 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3593 3594 if (shutdown_agent) 3595 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3596 3597 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3598 3599 return status; 3600 } 3601 3602 /** 3603 * i40e_aq_start_lldp 3604 * @hw: pointer to the hw struct 3605 * @cmd_details: pointer to command details structure or NULL 3606 * 3607 * Start the embedded LLDP Agent on all ports. 3608 **/ 3609 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 3610 struct i40e_asq_cmd_details *cmd_details) 3611 { 3612 struct i40e_aq_desc desc; 3613 struct i40e_aqc_lldp_start *cmd = 3614 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3615 i40e_status status; 3616 3617 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3618 3619 cmd->command = I40E_AQ_LLDP_AGENT_START; 3620 3621 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3622 3623 return status; 3624 } 3625 3626 /** 3627 * i40e_aq_get_cee_dcb_config 3628 * @hw: pointer to the hw struct 3629 * @buff: response buffer that stores CEE operational configuration 3630 * @buff_size: size of the buffer passed 3631 * @cmd_details: pointer to command details structure or NULL 3632 * 3633 * Get CEE DCBX mode operational configuration from firmware 3634 **/ 3635 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3636 void *buff, u16 buff_size, 3637 struct i40e_asq_cmd_details *cmd_details) 3638 { 3639 struct i40e_aq_desc desc; 3640 i40e_status status; 3641 3642 if (buff_size == 0 || !buff) 3643 return I40E_ERR_PARAM; 3644 3645 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3646 3647 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3648 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3649 cmd_details); 3650 3651 return status; 3652 } 3653 3654 /** 3655 * i40e_aq_add_udp_tunnel 3656 * @hw: pointer to the hw struct 3657 * @udp_port: the UDP port to add in Host byte order 3658 * @header_len: length of the tunneling header length in DWords 3659 * @protocol_index: protocol index type 3660 * @filter_index: pointer to filter index 3661 * @cmd_details: pointer to command details structure or NULL 3662 * 3663 * Note: Firmware expects the udp_port value to be in Little Endian format, 3664 * and this function will call cpu_to_le16 to convert from Host byte order to 3665 * Little Endian order. 3666 **/ 3667 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3668 u16 udp_port, u8 protocol_index, 3669 u8 *filter_index, 3670 struct i40e_asq_cmd_details *cmd_details) 3671 { 3672 struct i40e_aq_desc desc; 3673 struct i40e_aqc_add_udp_tunnel *cmd = 3674 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3675 struct i40e_aqc_del_udp_tunnel_completion *resp = 3676 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3677 i40e_status status; 3678 3679 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3680 3681 cmd->udp_port = cpu_to_le16(udp_port); 3682 cmd->protocol_type = protocol_index; 3683 3684 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3685 3686 if (!status && filter_index) 3687 *filter_index = resp->index; 3688 3689 return status; 3690 } 3691 3692 /** 3693 * i40e_aq_del_udp_tunnel 3694 * @hw: pointer to the hw struct 3695 * @index: filter index 3696 * @cmd_details: pointer to command details structure or NULL 3697 **/ 3698 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3699 struct i40e_asq_cmd_details *cmd_details) 3700 { 3701 struct i40e_aq_desc desc; 3702 struct i40e_aqc_remove_udp_tunnel *cmd = 3703 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3704 i40e_status status; 3705 3706 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3707 3708 cmd->index = index; 3709 3710 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3711 3712 return status; 3713 } 3714 3715 /** 3716 * i40e_aq_delete_element - Delete switch element 3717 * @hw: pointer to the hw struct 3718 * @seid: the SEID to delete from the switch 3719 * @cmd_details: pointer to command details structure or NULL 3720 * 3721 * This deletes a switch element from the switch. 3722 **/ 3723 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3724 struct i40e_asq_cmd_details *cmd_details) 3725 { 3726 struct i40e_aq_desc desc; 3727 struct i40e_aqc_switch_seid *cmd = 3728 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3729 i40e_status status; 3730 3731 if (seid == 0) 3732 return I40E_ERR_PARAM; 3733 3734 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3735 3736 cmd->seid = cpu_to_le16(seid); 3737 3738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3739 3740 return status; 3741 } 3742 3743 /** 3744 * i40e_aq_dcb_updated - DCB Updated Command 3745 * @hw: pointer to the hw struct 3746 * @cmd_details: pointer to command details structure or NULL 3747 * 3748 * EMP will return when the shared RPB settings have been 3749 * recomputed and modified. The retval field in the descriptor 3750 * will be set to 0 when RPB is modified. 3751 **/ 3752 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3753 struct i40e_asq_cmd_details *cmd_details) 3754 { 3755 struct i40e_aq_desc desc; 3756 i40e_status status; 3757 3758 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3759 3760 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3761 3762 return status; 3763 } 3764 3765 /** 3766 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3767 * @hw: pointer to the hw struct 3768 * @seid: seid for the physical port/switching component/vsi 3769 * @buff: Indirect buffer to hold data parameters and response 3770 * @buff_size: Indirect buffer size 3771 * @opcode: Tx scheduler AQ command opcode 3772 * @cmd_details: pointer to command details structure or NULL 3773 * 3774 * Generic command handler for Tx scheduler AQ commands 3775 **/ 3776 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3777 void *buff, u16 buff_size, 3778 enum i40e_admin_queue_opc opcode, 3779 struct i40e_asq_cmd_details *cmd_details) 3780 { 3781 struct i40e_aq_desc desc; 3782 struct i40e_aqc_tx_sched_ind *cmd = 3783 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3784 i40e_status status; 3785 bool cmd_param_flag = false; 3786 3787 switch (opcode) { 3788 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3789 case i40e_aqc_opc_configure_vsi_tc_bw: 3790 case i40e_aqc_opc_enable_switching_comp_ets: 3791 case i40e_aqc_opc_modify_switching_comp_ets: 3792 case i40e_aqc_opc_disable_switching_comp_ets: 3793 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3794 case i40e_aqc_opc_configure_switching_comp_bw_config: 3795 cmd_param_flag = true; 3796 break; 3797 case i40e_aqc_opc_query_vsi_bw_config: 3798 case i40e_aqc_opc_query_vsi_ets_sla_config: 3799 case i40e_aqc_opc_query_switching_comp_ets_config: 3800 case i40e_aqc_opc_query_port_ets_config: 3801 case i40e_aqc_opc_query_switching_comp_bw_config: 3802 cmd_param_flag = false; 3803 break; 3804 default: 3805 return I40E_ERR_PARAM; 3806 } 3807 3808 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3809 3810 /* Indirect command */ 3811 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3812 if (cmd_param_flag) 3813 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3814 if (buff_size > I40E_AQ_LARGE_BUF) 3815 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3816 3817 desc.datalen = cpu_to_le16(buff_size); 3818 3819 cmd->vsi_seid = cpu_to_le16(seid); 3820 3821 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3822 3823 return status; 3824 } 3825 3826 /** 3827 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3828 * @hw: pointer to the hw struct 3829 * @seid: VSI seid 3830 * @credit: BW limit credits (0 = disabled) 3831 * @max_credit: Max BW limit credits 3832 * @cmd_details: pointer to command details structure or NULL 3833 **/ 3834 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3835 u16 seid, u16 credit, u8 max_credit, 3836 struct i40e_asq_cmd_details *cmd_details) 3837 { 3838 struct i40e_aq_desc desc; 3839 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3840 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3841 i40e_status status; 3842 3843 i40e_fill_default_direct_cmd_desc(&desc, 3844 i40e_aqc_opc_configure_vsi_bw_limit); 3845 3846 cmd->vsi_seid = cpu_to_le16(seid); 3847 cmd->credit = cpu_to_le16(credit); 3848 cmd->max_credit = max_credit; 3849 3850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3851 3852 return status; 3853 } 3854 3855 /** 3856 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3857 * @hw: pointer to the hw struct 3858 * @seid: VSI seid 3859 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3860 * @cmd_details: pointer to command details structure or NULL 3861 **/ 3862 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3863 u16 seid, 3864 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3865 struct i40e_asq_cmd_details *cmd_details) 3866 { 3867 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3868 i40e_aqc_opc_configure_vsi_tc_bw, 3869 cmd_details); 3870 } 3871 3872 /** 3873 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3874 * @hw: pointer to the hw struct 3875 * @seid: seid of the switching component connected to Physical Port 3876 * @ets_data: Buffer holding ETS parameters 3877 * @cmd_details: pointer to command details structure or NULL 3878 **/ 3879 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3880 u16 seid, 3881 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3882 enum i40e_admin_queue_opc opcode, 3883 struct i40e_asq_cmd_details *cmd_details) 3884 { 3885 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3886 sizeof(*ets_data), opcode, cmd_details); 3887 } 3888 3889 /** 3890 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3891 * @hw: pointer to the hw struct 3892 * @seid: seid of the switching component 3893 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3894 * @cmd_details: pointer to command details structure or NULL 3895 **/ 3896 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3897 u16 seid, 3898 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3899 struct i40e_asq_cmd_details *cmd_details) 3900 { 3901 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3902 i40e_aqc_opc_configure_switching_comp_bw_config, 3903 cmd_details); 3904 } 3905 3906 /** 3907 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3908 * @hw: pointer to the hw struct 3909 * @seid: seid of the VSI 3910 * @bw_data: Buffer to hold VSI BW configuration 3911 * @cmd_details: pointer to command details structure or NULL 3912 **/ 3913 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3914 u16 seid, 3915 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3916 struct i40e_asq_cmd_details *cmd_details) 3917 { 3918 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3919 i40e_aqc_opc_query_vsi_bw_config, 3920 cmd_details); 3921 } 3922 3923 /** 3924 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3925 * @hw: pointer to the hw struct 3926 * @seid: seid of the VSI 3927 * @bw_data: Buffer to hold VSI BW configuration per TC 3928 * @cmd_details: pointer to command details structure or NULL 3929 **/ 3930 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3931 u16 seid, 3932 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3933 struct i40e_asq_cmd_details *cmd_details) 3934 { 3935 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3936 i40e_aqc_opc_query_vsi_ets_sla_config, 3937 cmd_details); 3938 } 3939 3940 /** 3941 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3942 * @hw: pointer to the hw struct 3943 * @seid: seid of the switching component 3944 * @bw_data: Buffer to hold switching component's per TC BW config 3945 * @cmd_details: pointer to command details structure or NULL 3946 **/ 3947 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3948 u16 seid, 3949 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3950 struct i40e_asq_cmd_details *cmd_details) 3951 { 3952 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3953 i40e_aqc_opc_query_switching_comp_ets_config, 3954 cmd_details); 3955 } 3956 3957 /** 3958 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3959 * @hw: pointer to the hw struct 3960 * @seid: seid of the VSI or switching component connected to Physical Port 3961 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3962 * @cmd_details: pointer to command details structure or NULL 3963 **/ 3964 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3965 u16 seid, 3966 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3967 struct i40e_asq_cmd_details *cmd_details) 3968 { 3969 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3970 i40e_aqc_opc_query_port_ets_config, 3971 cmd_details); 3972 } 3973 3974 /** 3975 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3976 * @hw: pointer to the hw struct 3977 * @seid: seid of the switching component 3978 * @bw_data: Buffer to hold switching component's BW configuration 3979 * @cmd_details: pointer to command details structure or NULL 3980 **/ 3981 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3982 u16 seid, 3983 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3984 struct i40e_asq_cmd_details *cmd_details) 3985 { 3986 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3987 i40e_aqc_opc_query_switching_comp_bw_config, 3988 cmd_details); 3989 } 3990 3991 /** 3992 * i40e_validate_filter_settings 3993 * @hw: pointer to the hardware structure 3994 * @settings: Filter control settings 3995 * 3996 * Check and validate the filter control settings passed. 3997 * The function checks for the valid filter/context sizes being 3998 * passed for FCoE and PE. 3999 * 4000 * Returns 0 if the values passed are valid and within 4001 * range else returns an error. 4002 **/ 4003 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 4004 struct i40e_filter_control_settings *settings) 4005 { 4006 u32 fcoe_cntx_size, fcoe_filt_size; 4007 u32 pe_cntx_size, pe_filt_size; 4008 u32 fcoe_fmax; 4009 u32 val; 4010 4011 /* Validate FCoE settings passed */ 4012 switch (settings->fcoe_filt_num) { 4013 case I40E_HASH_FILTER_SIZE_1K: 4014 case I40E_HASH_FILTER_SIZE_2K: 4015 case I40E_HASH_FILTER_SIZE_4K: 4016 case I40E_HASH_FILTER_SIZE_8K: 4017 case I40E_HASH_FILTER_SIZE_16K: 4018 case I40E_HASH_FILTER_SIZE_32K: 4019 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4020 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4021 break; 4022 default: 4023 return I40E_ERR_PARAM; 4024 } 4025 4026 switch (settings->fcoe_cntx_num) { 4027 case I40E_DMA_CNTX_SIZE_512: 4028 case I40E_DMA_CNTX_SIZE_1K: 4029 case I40E_DMA_CNTX_SIZE_2K: 4030 case I40E_DMA_CNTX_SIZE_4K: 4031 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4032 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4033 break; 4034 default: 4035 return I40E_ERR_PARAM; 4036 } 4037 4038 /* Validate PE settings passed */ 4039 switch (settings->pe_filt_num) { 4040 case I40E_HASH_FILTER_SIZE_1K: 4041 case I40E_HASH_FILTER_SIZE_2K: 4042 case I40E_HASH_FILTER_SIZE_4K: 4043 case I40E_HASH_FILTER_SIZE_8K: 4044 case I40E_HASH_FILTER_SIZE_16K: 4045 case I40E_HASH_FILTER_SIZE_32K: 4046 case I40E_HASH_FILTER_SIZE_64K: 4047 case I40E_HASH_FILTER_SIZE_128K: 4048 case I40E_HASH_FILTER_SIZE_256K: 4049 case I40E_HASH_FILTER_SIZE_512K: 4050 case I40E_HASH_FILTER_SIZE_1M: 4051 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4052 pe_filt_size <<= (u32)settings->pe_filt_num; 4053 break; 4054 default: 4055 return I40E_ERR_PARAM; 4056 } 4057 4058 switch (settings->pe_cntx_num) { 4059 case I40E_DMA_CNTX_SIZE_512: 4060 case I40E_DMA_CNTX_SIZE_1K: 4061 case I40E_DMA_CNTX_SIZE_2K: 4062 case I40E_DMA_CNTX_SIZE_4K: 4063 case I40E_DMA_CNTX_SIZE_8K: 4064 case I40E_DMA_CNTX_SIZE_16K: 4065 case I40E_DMA_CNTX_SIZE_32K: 4066 case I40E_DMA_CNTX_SIZE_64K: 4067 case I40E_DMA_CNTX_SIZE_128K: 4068 case I40E_DMA_CNTX_SIZE_256K: 4069 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4070 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4071 break; 4072 default: 4073 return I40E_ERR_PARAM; 4074 } 4075 4076 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4077 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4078 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4079 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4080 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4081 return I40E_ERR_INVALID_SIZE; 4082 4083 return 0; 4084 } 4085 4086 /** 4087 * i40e_set_filter_control 4088 * @hw: pointer to the hardware structure 4089 * @settings: Filter control settings 4090 * 4091 * Set the Queue Filters for PE/FCoE and enable filters required 4092 * for a single PF. It is expected that these settings are programmed 4093 * at the driver initialization time. 4094 **/ 4095 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4096 struct i40e_filter_control_settings *settings) 4097 { 4098 i40e_status ret = 0; 4099 u32 hash_lut_size = 0; 4100 u32 val; 4101 4102 if (!settings) 4103 return I40E_ERR_PARAM; 4104 4105 /* Validate the input settings */ 4106 ret = i40e_validate_filter_settings(hw, settings); 4107 if (ret) 4108 return ret; 4109 4110 /* Read the PF Queue Filter control register */ 4111 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4112 4113 /* Program required PE hash buckets for the PF */ 4114 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4115 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4116 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4117 /* Program required PE contexts for the PF */ 4118 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4119 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4120 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4121 4122 /* Program required FCoE hash buckets for the PF */ 4123 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4124 val |= ((u32)settings->fcoe_filt_num << 4125 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4126 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4127 /* Program required FCoE DDP contexts for the PF */ 4128 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4129 val |= ((u32)settings->fcoe_cntx_num << 4130 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4131 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4132 4133 /* Program Hash LUT size for the PF */ 4134 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4135 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4136 hash_lut_size = 1; 4137 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4138 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4139 4140 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4141 if (settings->enable_fdir) 4142 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4143 if (settings->enable_ethtype) 4144 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4145 if (settings->enable_macvlan) 4146 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4147 4148 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4149 4150 return 0; 4151 } 4152 4153 /** 4154 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4155 * @hw: pointer to the hw struct 4156 * @mac_addr: MAC address to use in the filter 4157 * @ethtype: Ethertype to use in the filter 4158 * @flags: Flags that needs to be applied to the filter 4159 * @vsi_seid: seid of the control VSI 4160 * @queue: VSI queue number to send the packet to 4161 * @is_add: Add control packet filter if True else remove 4162 * @stats: Structure to hold information on control filter counts 4163 * @cmd_details: pointer to command details structure or NULL 4164 * 4165 * This command will Add or Remove control packet filter for a control VSI. 4166 * In return it will update the total number of perfect filter count in 4167 * the stats member. 4168 **/ 4169 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4170 u8 *mac_addr, u16 ethtype, u16 flags, 4171 u16 vsi_seid, u16 queue, bool is_add, 4172 struct i40e_control_filter_stats *stats, 4173 struct i40e_asq_cmd_details *cmd_details) 4174 { 4175 struct i40e_aq_desc desc; 4176 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4177 (struct i40e_aqc_add_remove_control_packet_filter *) 4178 &desc.params.raw; 4179 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4180 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4181 &desc.params.raw; 4182 i40e_status status; 4183 4184 if (vsi_seid == 0) 4185 return I40E_ERR_PARAM; 4186 4187 if (is_add) { 4188 i40e_fill_default_direct_cmd_desc(&desc, 4189 i40e_aqc_opc_add_control_packet_filter); 4190 cmd->queue = cpu_to_le16(queue); 4191 } else { 4192 i40e_fill_default_direct_cmd_desc(&desc, 4193 i40e_aqc_opc_remove_control_packet_filter); 4194 } 4195 4196 if (mac_addr) 4197 ether_addr_copy(cmd->mac, mac_addr); 4198 4199 cmd->etype = cpu_to_le16(ethtype); 4200 cmd->flags = cpu_to_le16(flags); 4201 cmd->seid = cpu_to_le16(vsi_seid); 4202 4203 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4204 4205 if (!status && stats) { 4206 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4207 stats->etype_used = le16_to_cpu(resp->etype_used); 4208 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4209 stats->etype_free = le16_to_cpu(resp->etype_free); 4210 } 4211 4212 return status; 4213 } 4214 4215 /** 4216 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4217 * @hw: pointer to the hw struct 4218 * @seid: VSI seid to add ethertype filter from 4219 **/ 4220 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4221 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4222 u16 seid) 4223 { 4224 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4225 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4226 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4227 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4228 i40e_status status; 4229 4230 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4231 seid, 0, true, NULL, 4232 NULL); 4233 if (status) 4234 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4235 } 4236 4237 /** 4238 * i40e_aq_alternate_read 4239 * @hw: pointer to the hardware structure 4240 * @reg_addr0: address of first dword to be read 4241 * @reg_val0: pointer for data read from 'reg_addr0' 4242 * @reg_addr1: address of second dword to be read 4243 * @reg_val1: pointer for data read from 'reg_addr1' 4244 * 4245 * Read one or two dwords from alternate structure. Fields are indicated 4246 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4247 * is not passed then only register at 'reg_addr0' is read. 4248 * 4249 **/ 4250 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4251 u32 reg_addr0, u32 *reg_val0, 4252 u32 reg_addr1, u32 *reg_val1) 4253 { 4254 struct i40e_aq_desc desc; 4255 struct i40e_aqc_alternate_write *cmd_resp = 4256 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4257 i40e_status status; 4258 4259 if (!reg_val0) 4260 return I40E_ERR_PARAM; 4261 4262 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4263 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4264 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4265 4266 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4267 4268 if (!status) { 4269 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4270 4271 if (reg_val1) 4272 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4273 } 4274 4275 return status; 4276 } 4277 4278 /** 4279 * i40e_aq_resume_port_tx 4280 * @hw: pointer to the hardware structure 4281 * @cmd_details: pointer to command details structure or NULL 4282 * 4283 * Resume port's Tx traffic 4284 **/ 4285 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4286 struct i40e_asq_cmd_details *cmd_details) 4287 { 4288 struct i40e_aq_desc desc; 4289 i40e_status status; 4290 4291 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4292 4293 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4294 4295 return status; 4296 } 4297 4298 /** 4299 * i40e_set_pci_config_data - store PCI bus info 4300 * @hw: pointer to hardware structure 4301 * @link_status: the link status word from PCI config space 4302 * 4303 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4304 **/ 4305 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4306 { 4307 hw->bus.type = i40e_bus_type_pci_express; 4308 4309 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4310 case PCI_EXP_LNKSTA_NLW_X1: 4311 hw->bus.width = i40e_bus_width_pcie_x1; 4312 break; 4313 case PCI_EXP_LNKSTA_NLW_X2: 4314 hw->bus.width = i40e_bus_width_pcie_x2; 4315 break; 4316 case PCI_EXP_LNKSTA_NLW_X4: 4317 hw->bus.width = i40e_bus_width_pcie_x4; 4318 break; 4319 case PCI_EXP_LNKSTA_NLW_X8: 4320 hw->bus.width = i40e_bus_width_pcie_x8; 4321 break; 4322 default: 4323 hw->bus.width = i40e_bus_width_unknown; 4324 break; 4325 } 4326 4327 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4328 case PCI_EXP_LNKSTA_CLS_2_5GB: 4329 hw->bus.speed = i40e_bus_speed_2500; 4330 break; 4331 case PCI_EXP_LNKSTA_CLS_5_0GB: 4332 hw->bus.speed = i40e_bus_speed_5000; 4333 break; 4334 case PCI_EXP_LNKSTA_CLS_8_0GB: 4335 hw->bus.speed = i40e_bus_speed_8000; 4336 break; 4337 default: 4338 hw->bus.speed = i40e_bus_speed_unknown; 4339 break; 4340 } 4341 } 4342 4343 /** 4344 * i40e_aq_debug_dump 4345 * @hw: pointer to the hardware structure 4346 * @cluster_id: specific cluster to dump 4347 * @table_id: table id within cluster 4348 * @start_index: index of line in the block to read 4349 * @buff_size: dump buffer size 4350 * @buff: dump buffer 4351 * @ret_buff_size: actual buffer size returned 4352 * @ret_next_table: next block to read 4353 * @ret_next_index: next index to read 4354 * 4355 * Dump internal FW/HW data for debug purposes. 4356 * 4357 **/ 4358 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4359 u8 table_id, u32 start_index, u16 buff_size, 4360 void *buff, u16 *ret_buff_size, 4361 u8 *ret_next_table, u32 *ret_next_index, 4362 struct i40e_asq_cmd_details *cmd_details) 4363 { 4364 struct i40e_aq_desc desc; 4365 struct i40e_aqc_debug_dump_internals *cmd = 4366 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4367 struct i40e_aqc_debug_dump_internals *resp = 4368 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4369 i40e_status status; 4370 4371 if (buff_size == 0 || !buff) 4372 return I40E_ERR_PARAM; 4373 4374 i40e_fill_default_direct_cmd_desc(&desc, 4375 i40e_aqc_opc_debug_dump_internals); 4376 /* Indirect Command */ 4377 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4378 if (buff_size > I40E_AQ_LARGE_BUF) 4379 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4380 4381 cmd->cluster_id = cluster_id; 4382 cmd->table_id = table_id; 4383 cmd->idx = cpu_to_le32(start_index); 4384 4385 desc.datalen = cpu_to_le16(buff_size); 4386 4387 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4388 if (!status) { 4389 if (ret_buff_size) 4390 *ret_buff_size = le16_to_cpu(desc.datalen); 4391 if (ret_next_table) 4392 *ret_next_table = resp->table_id; 4393 if (ret_next_index) 4394 *ret_next_index = le32_to_cpu(resp->idx); 4395 } 4396 4397 return status; 4398 } 4399 4400 /** 4401 * i40e_read_bw_from_alt_ram 4402 * @hw: pointer to the hardware structure 4403 * @max_bw: pointer for max_bw read 4404 * @min_bw: pointer for min_bw read 4405 * @min_valid: pointer for bool that is true if min_bw is a valid value 4406 * @max_valid: pointer for bool that is true if max_bw is a valid value 4407 * 4408 * Read bw from the alternate ram for the given pf 4409 **/ 4410 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4411 u32 *max_bw, u32 *min_bw, 4412 bool *min_valid, bool *max_valid) 4413 { 4414 i40e_status status; 4415 u32 max_bw_addr, min_bw_addr; 4416 4417 /* Calculate the address of the min/max bw registers */ 4418 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4419 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4420 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4421 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4422 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4423 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4424 4425 /* Read the bandwidths from alt ram */ 4426 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4427 min_bw_addr, min_bw); 4428 4429 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4430 *min_valid = true; 4431 else 4432 *min_valid = false; 4433 4434 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4435 *max_valid = true; 4436 else 4437 *max_valid = false; 4438 4439 return status; 4440 } 4441 4442 /** 4443 * i40e_aq_configure_partition_bw 4444 * @hw: pointer to the hardware structure 4445 * @bw_data: Buffer holding valid pfs and bw limits 4446 * @cmd_details: pointer to command details 4447 * 4448 * Configure partitions guaranteed/max bw 4449 **/ 4450 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4451 struct i40e_aqc_configure_partition_bw_data *bw_data, 4452 struct i40e_asq_cmd_details *cmd_details) 4453 { 4454 i40e_status status; 4455 struct i40e_aq_desc desc; 4456 u16 bwd_size = sizeof(*bw_data); 4457 4458 i40e_fill_default_direct_cmd_desc(&desc, 4459 i40e_aqc_opc_configure_partition_bw); 4460 4461 /* Indirect command */ 4462 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4463 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4464 4465 if (bwd_size > I40E_AQ_LARGE_BUF) 4466 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4467 4468 desc.datalen = cpu_to_le16(bwd_size); 4469 4470 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4471 cmd_details); 4472 4473 return status; 4474 } 4475 4476 /** 4477 * i40e_read_phy_register_clause22 4478 * @hw: pointer to the HW structure 4479 * @reg: register address in the page 4480 * @phy_adr: PHY address on MDIO interface 4481 * @value: PHY register value 4482 * 4483 * Reads specified PHY register value 4484 **/ 4485 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw, 4486 u16 reg, u8 phy_addr, u16 *value) 4487 { 4488 i40e_status status = I40E_ERR_TIMEOUT; 4489 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4490 u32 command = 0; 4491 u16 retry = 1000; 4492 4493 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4494 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4495 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4496 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4497 (I40E_GLGEN_MSCA_MDICMD_MASK); 4498 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4499 do { 4500 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4501 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4502 status = 0; 4503 break; 4504 } 4505 udelay(10); 4506 retry--; 4507 } while (retry); 4508 4509 if (status) { 4510 i40e_debug(hw, I40E_DEBUG_PHY, 4511 "PHY: Can't write command to external PHY.\n"); 4512 } else { 4513 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4514 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4515 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4516 } 4517 4518 return status; 4519 } 4520 4521 /** 4522 * i40e_write_phy_register_clause22 4523 * @hw: pointer to the HW structure 4524 * @reg: register address in the page 4525 * @phy_adr: PHY address on MDIO interface 4526 * @value: PHY register value 4527 * 4528 * Writes specified PHY register value 4529 **/ 4530 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw, 4531 u16 reg, u8 phy_addr, u16 value) 4532 { 4533 i40e_status status = I40E_ERR_TIMEOUT; 4534 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4535 u32 command = 0; 4536 u16 retry = 1000; 4537 4538 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4539 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4540 4541 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4542 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4543 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4544 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4545 (I40E_GLGEN_MSCA_MDICMD_MASK); 4546 4547 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4548 do { 4549 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4550 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4551 status = 0; 4552 break; 4553 } 4554 udelay(10); 4555 retry--; 4556 } while (retry); 4557 4558 return status; 4559 } 4560 4561 /** 4562 * i40e_read_phy_register_clause45 4563 * @hw: pointer to the HW structure 4564 * @page: registers page number 4565 * @reg: register address in the page 4566 * @phy_adr: PHY address on MDIO interface 4567 * @value: PHY register value 4568 * 4569 * Reads specified PHY register value 4570 **/ 4571 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw, 4572 u8 page, u16 reg, u8 phy_addr, u16 *value) 4573 { 4574 i40e_status status = I40E_ERR_TIMEOUT; 4575 u32 command = 0; 4576 u16 retry = 1000; 4577 u8 port_num = hw->func_caps.mdio_port_num; 4578 4579 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4580 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4581 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4582 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4583 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4584 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4585 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4586 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4587 do { 4588 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4589 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4590 status = 0; 4591 break; 4592 } 4593 usleep_range(10, 20); 4594 retry--; 4595 } while (retry); 4596 4597 if (status) { 4598 i40e_debug(hw, I40E_DEBUG_PHY, 4599 "PHY: Can't write command to external PHY.\n"); 4600 goto phy_read_end; 4601 } 4602 4603 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4604 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4605 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4606 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4607 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4608 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4609 status = I40E_ERR_TIMEOUT; 4610 retry = 1000; 4611 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4612 do { 4613 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4614 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4615 status = 0; 4616 break; 4617 } 4618 usleep_range(10, 20); 4619 retry--; 4620 } while (retry); 4621 4622 if (!status) { 4623 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4624 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4625 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4626 } else { 4627 i40e_debug(hw, I40E_DEBUG_PHY, 4628 "PHY: Can't read register value from external PHY.\n"); 4629 } 4630 4631 phy_read_end: 4632 return status; 4633 } 4634 4635 /** 4636 * i40e_write_phy_register_clause45 4637 * @hw: pointer to the HW structure 4638 * @page: registers page number 4639 * @reg: register address in the page 4640 * @phy_adr: PHY address on MDIO interface 4641 * @value: PHY register value 4642 * 4643 * Writes value to specified PHY register 4644 **/ 4645 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, 4646 u8 page, u16 reg, u8 phy_addr, u16 value) 4647 { 4648 i40e_status status = I40E_ERR_TIMEOUT; 4649 u32 command = 0; 4650 u16 retry = 1000; 4651 u8 port_num = hw->func_caps.mdio_port_num; 4652 4653 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4654 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4655 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4656 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4657 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4658 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4659 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4660 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4661 do { 4662 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4663 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4664 status = 0; 4665 break; 4666 } 4667 usleep_range(10, 20); 4668 retry--; 4669 } while (retry); 4670 if (status) { 4671 i40e_debug(hw, I40E_DEBUG_PHY, 4672 "PHY: Can't write command to external PHY.\n"); 4673 goto phy_write_end; 4674 } 4675 4676 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4677 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4678 4679 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4680 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4681 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4682 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4683 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4684 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4685 status = I40E_ERR_TIMEOUT; 4686 retry = 1000; 4687 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4688 do { 4689 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4690 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4691 status = 0; 4692 break; 4693 } 4694 usleep_range(10, 20); 4695 retry--; 4696 } while (retry); 4697 4698 phy_write_end: 4699 return status; 4700 } 4701 4702 /** 4703 * i40e_write_phy_register 4704 * @hw: pointer to the HW structure 4705 * @page: registers page number 4706 * @reg: register address in the page 4707 * @phy_adr: PHY address on MDIO interface 4708 * @value: PHY register value 4709 * 4710 * Writes value to specified PHY register 4711 **/ 4712 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4713 u8 page, u16 reg, u8 phy_addr, u16 value) 4714 { 4715 i40e_status status; 4716 4717 switch (hw->device_id) { 4718 case I40E_DEV_ID_1G_BASE_T_X722: 4719 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4720 value); 4721 break; 4722 case I40E_DEV_ID_10G_BASE_T: 4723 case I40E_DEV_ID_10G_BASE_T4: 4724 case I40E_DEV_ID_10G_BASE_T_X722: 4725 case I40E_DEV_ID_25G_B: 4726 case I40E_DEV_ID_25G_SFP28: 4727 status = i40e_write_phy_register_clause45(hw, page, reg, 4728 phy_addr, value); 4729 break; 4730 default: 4731 status = I40E_ERR_UNKNOWN_PHY; 4732 break; 4733 } 4734 4735 return status; 4736 } 4737 4738 /** 4739 * i40e_read_phy_register 4740 * @hw: pointer to the HW structure 4741 * @page: registers page number 4742 * @reg: register address in the page 4743 * @phy_adr: PHY address on MDIO interface 4744 * @value: PHY register value 4745 * 4746 * Reads specified PHY register value 4747 **/ 4748 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4749 u8 page, u16 reg, u8 phy_addr, u16 *value) 4750 { 4751 i40e_status status; 4752 4753 switch (hw->device_id) { 4754 case I40E_DEV_ID_1G_BASE_T_X722: 4755 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4756 value); 4757 break; 4758 case I40E_DEV_ID_10G_BASE_T: 4759 case I40E_DEV_ID_10G_BASE_T4: 4760 case I40E_DEV_ID_10G_BASE_T_X722: 4761 case I40E_DEV_ID_25G_B: 4762 case I40E_DEV_ID_25G_SFP28: 4763 status = i40e_read_phy_register_clause45(hw, page, reg, 4764 phy_addr, value); 4765 break; 4766 default: 4767 status = I40E_ERR_UNKNOWN_PHY; 4768 break; 4769 } 4770 4771 return status; 4772 } 4773 4774 /** 4775 * i40e_get_phy_address 4776 * @hw: pointer to the HW structure 4777 * @dev_num: PHY port num that address we want 4778 * @phy_addr: Returned PHY address 4779 * 4780 * Gets PHY address for current port 4781 **/ 4782 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4783 { 4784 u8 port_num = hw->func_caps.mdio_port_num; 4785 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4786 4787 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4788 } 4789 4790 /** 4791 * i40e_blink_phy_led 4792 * @hw: pointer to the HW structure 4793 * @time: time how long led will blinks in secs 4794 * @interval: gap between LED on and off in msecs 4795 * 4796 * Blinks PHY link LED 4797 **/ 4798 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4799 u32 time, u32 interval) 4800 { 4801 i40e_status status = 0; 4802 u32 i; 4803 u16 led_ctl; 4804 u16 gpio_led_port; 4805 u16 led_reg; 4806 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4807 u8 phy_addr = 0; 4808 u8 port_num; 4809 4810 i = rd32(hw, I40E_PFGEN_PORTNUM); 4811 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4812 phy_addr = i40e_get_phy_address(hw, port_num); 4813 4814 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4815 led_addr++) { 4816 status = i40e_read_phy_register_clause45(hw, 4817 I40E_PHY_COM_REG_PAGE, 4818 led_addr, phy_addr, 4819 &led_reg); 4820 if (status) 4821 goto phy_blinking_end; 4822 led_ctl = led_reg; 4823 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4824 led_reg = 0; 4825 status = i40e_write_phy_register_clause45(hw, 4826 I40E_PHY_COM_REG_PAGE, 4827 led_addr, phy_addr, 4828 led_reg); 4829 if (status) 4830 goto phy_blinking_end; 4831 break; 4832 } 4833 } 4834 4835 if (time > 0 && interval > 0) { 4836 for (i = 0; i < time * 1000; i += interval) { 4837 status = i40e_read_phy_register_clause45(hw, 4838 I40E_PHY_COM_REG_PAGE, 4839 led_addr, phy_addr, &led_reg); 4840 if (status) 4841 goto restore_config; 4842 if (led_reg & I40E_PHY_LED_MANUAL_ON) 4843 led_reg = 0; 4844 else 4845 led_reg = I40E_PHY_LED_MANUAL_ON; 4846 status = i40e_write_phy_register_clause45(hw, 4847 I40E_PHY_COM_REG_PAGE, 4848 led_addr, phy_addr, led_reg); 4849 if (status) 4850 goto restore_config; 4851 msleep(interval); 4852 } 4853 } 4854 4855 restore_config: 4856 status = i40e_write_phy_register_clause45(hw, 4857 I40E_PHY_COM_REG_PAGE, 4858 led_addr, phy_addr, led_ctl); 4859 4860 phy_blinking_end: 4861 return status; 4862 } 4863 4864 /** 4865 * i40e_led_get_reg - read LED register 4866 * @hw: pointer to the HW structure 4867 * @led_addr: LED register address 4868 * @reg_val: read register value 4869 **/ 4870 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 4871 u32 *reg_val) 4872 { 4873 enum i40e_status_code status; 4874 u8 phy_addr = 0; 4875 u8 port_num; 4876 u32 i; 4877 4878 *reg_val = 0; 4879 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4880 status = 4881 i40e_aq_get_phy_register(hw, 4882 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4883 I40E_PHY_COM_REG_PAGE, 4884 I40E_PHY_LED_PROV_REG_1, 4885 reg_val, NULL); 4886 } else { 4887 i = rd32(hw, I40E_PFGEN_PORTNUM); 4888 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4889 phy_addr = i40e_get_phy_address(hw, port_num); 4890 status = i40e_read_phy_register_clause45(hw, 4891 I40E_PHY_COM_REG_PAGE, 4892 led_addr, phy_addr, 4893 (u16 *)reg_val); 4894 } 4895 return status; 4896 } 4897 4898 /** 4899 * i40e_led_set_reg - write LED register 4900 * @hw: pointer to the HW structure 4901 * @led_addr: LED register address 4902 * @reg_val: register value to write 4903 **/ 4904 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 4905 u32 reg_val) 4906 { 4907 enum i40e_status_code status; 4908 u8 phy_addr = 0; 4909 u8 port_num; 4910 u32 i; 4911 4912 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4913 status = 4914 i40e_aq_set_phy_register(hw, 4915 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4916 I40E_PHY_COM_REG_PAGE, 4917 I40E_PHY_LED_PROV_REG_1, 4918 reg_val, NULL); 4919 } else { 4920 i = rd32(hw, I40E_PFGEN_PORTNUM); 4921 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4922 phy_addr = i40e_get_phy_address(hw, port_num); 4923 status = i40e_write_phy_register_clause45(hw, 4924 I40E_PHY_COM_REG_PAGE, 4925 led_addr, phy_addr, 4926 (u16)reg_val); 4927 } 4928 4929 return status; 4930 } 4931 4932 /** 4933 * i40e_led_get_phy - return current on/off mode 4934 * @hw: pointer to the hw struct 4935 * @led_addr: address of led register to use 4936 * @val: original value of register to use 4937 * 4938 **/ 4939 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4940 u16 *val) 4941 { 4942 i40e_status status = 0; 4943 u16 gpio_led_port; 4944 u8 phy_addr = 0; 4945 u16 reg_val; 4946 u16 temp_addr; 4947 u8 port_num; 4948 u32 i; 4949 u32 reg_val_aq; 4950 4951 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4952 status = 4953 i40e_aq_get_phy_register(hw, 4954 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4955 I40E_PHY_COM_REG_PAGE, 4956 I40E_PHY_LED_PROV_REG_1, 4957 ®_val_aq, NULL); 4958 if (status == I40E_SUCCESS) 4959 *val = (u16)reg_val_aq; 4960 return status; 4961 } 4962 temp_addr = I40E_PHY_LED_PROV_REG_1; 4963 i = rd32(hw, I40E_PFGEN_PORTNUM); 4964 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4965 phy_addr = i40e_get_phy_address(hw, port_num); 4966 4967 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4968 temp_addr++) { 4969 status = i40e_read_phy_register_clause45(hw, 4970 I40E_PHY_COM_REG_PAGE, 4971 temp_addr, phy_addr, 4972 ®_val); 4973 if (status) 4974 return status; 4975 *val = reg_val; 4976 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4977 *led_addr = temp_addr; 4978 break; 4979 } 4980 } 4981 return status; 4982 } 4983 4984 /** 4985 * i40e_led_set_phy 4986 * @hw: pointer to the HW structure 4987 * @on: true or false 4988 * @mode: original val plus bit for set or ignore 4989 * Set led's on or off when controlled by the PHY 4990 * 4991 **/ 4992 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 4993 u16 led_addr, u32 mode) 4994 { 4995 i40e_status status = 0; 4996 u32 led_ctl = 0; 4997 u32 led_reg = 0; 4998 4999 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5000 if (status) 5001 return status; 5002 led_ctl = led_reg; 5003 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 5004 led_reg = 0; 5005 status = i40e_led_set_reg(hw, led_addr, led_reg); 5006 if (status) 5007 return status; 5008 } 5009 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5010 if (status) 5011 goto restore_config; 5012 if (on) 5013 led_reg = I40E_PHY_LED_MANUAL_ON; 5014 else 5015 led_reg = 0; 5016 5017 status = i40e_led_set_reg(hw, led_addr, led_reg); 5018 if (status) 5019 goto restore_config; 5020 if (mode & I40E_PHY_LED_MODE_ORIG) { 5021 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 5022 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5023 } 5024 return status; 5025 5026 restore_config: 5027 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5028 return status; 5029 } 5030 5031 /** 5032 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 5033 * @hw: pointer to the hw struct 5034 * @reg_addr: register address 5035 * @reg_val: ptr to register value 5036 * @cmd_details: pointer to command details structure or NULL 5037 * 5038 * Use the firmware to read the Rx control register, 5039 * especially useful if the Rx unit is under heavy pressure 5040 **/ 5041 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 5042 u32 reg_addr, u32 *reg_val, 5043 struct i40e_asq_cmd_details *cmd_details) 5044 { 5045 struct i40e_aq_desc desc; 5046 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 5047 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5048 i40e_status status; 5049 5050 if (!reg_val) 5051 return I40E_ERR_PARAM; 5052 5053 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 5054 5055 cmd_resp->address = cpu_to_le32(reg_addr); 5056 5057 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5058 5059 if (status == 0) 5060 *reg_val = le32_to_cpu(cmd_resp->value); 5061 5062 return status; 5063 } 5064 5065 /** 5066 * i40e_read_rx_ctl - read from an Rx control register 5067 * @hw: pointer to the hw struct 5068 * @reg_addr: register address 5069 **/ 5070 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 5071 { 5072 i40e_status status = 0; 5073 bool use_register; 5074 int retry = 5; 5075 u32 val = 0; 5076 5077 use_register = (((hw->aq.api_maj_ver == 1) && 5078 (hw->aq.api_min_ver < 5)) || 5079 (hw->mac.type == I40E_MAC_X722)); 5080 if (!use_register) { 5081 do_retry: 5082 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 5083 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5084 usleep_range(1000, 2000); 5085 retry--; 5086 goto do_retry; 5087 } 5088 } 5089 5090 /* if the AQ access failed, try the old-fashioned way */ 5091 if (status || use_register) 5092 val = rd32(hw, reg_addr); 5093 5094 return val; 5095 } 5096 5097 /** 5098 * i40e_aq_rx_ctl_write_register 5099 * @hw: pointer to the hw struct 5100 * @reg_addr: register address 5101 * @reg_val: register value 5102 * @cmd_details: pointer to command details structure or NULL 5103 * 5104 * Use the firmware to write to an Rx control register, 5105 * especially useful if the Rx unit is under heavy pressure 5106 **/ 5107 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 5108 u32 reg_addr, u32 reg_val, 5109 struct i40e_asq_cmd_details *cmd_details) 5110 { 5111 struct i40e_aq_desc desc; 5112 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 5113 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5114 i40e_status status; 5115 5116 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 5117 5118 cmd->address = cpu_to_le32(reg_addr); 5119 cmd->value = cpu_to_le32(reg_val); 5120 5121 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5122 5123 return status; 5124 } 5125 5126 /** 5127 * i40e_write_rx_ctl - write to an Rx control register 5128 * @hw: pointer to the hw struct 5129 * @reg_addr: register address 5130 * @reg_val: register value 5131 **/ 5132 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5133 { 5134 i40e_status status = 0; 5135 bool use_register; 5136 int retry = 5; 5137 5138 use_register = (((hw->aq.api_maj_ver == 1) && 5139 (hw->aq.api_min_ver < 5)) || 5140 (hw->mac.type == I40E_MAC_X722)); 5141 if (!use_register) { 5142 do_retry: 5143 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5144 reg_val, NULL); 5145 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5146 usleep_range(1000, 2000); 5147 retry--; 5148 goto do_retry; 5149 } 5150 } 5151 5152 /* if the AQ access failed, try the old-fashioned way */ 5153 if (status || use_register) 5154 wr32(hw, reg_addr, reg_val); 5155 } 5156 5157 /** 5158 * i40e_aq_set_phy_register 5159 * @hw: pointer to the hw struct 5160 * @phy_select: select which phy should be accessed 5161 * @dev_addr: PHY device address 5162 * @reg_addr: PHY register address 5163 * @reg_val: new register value 5164 * @cmd_details: pointer to command details structure or NULL 5165 * 5166 * Write the external PHY register. 5167 **/ 5168 i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw, 5169 u8 phy_select, u8 dev_addr, 5170 u32 reg_addr, u32 reg_val, 5171 struct i40e_asq_cmd_details *cmd_details) 5172 { 5173 struct i40e_aq_desc desc; 5174 struct i40e_aqc_phy_register_access *cmd = 5175 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5176 i40e_status status; 5177 5178 i40e_fill_default_direct_cmd_desc(&desc, 5179 i40e_aqc_opc_set_phy_register); 5180 5181 cmd->phy_interface = phy_select; 5182 cmd->dev_address = dev_addr; 5183 cmd->reg_address = cpu_to_le32(reg_addr); 5184 cmd->reg_value = cpu_to_le32(reg_val); 5185 5186 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5187 5188 return status; 5189 } 5190 5191 /** 5192 * i40e_aq_get_phy_register 5193 * @hw: pointer to the hw struct 5194 * @phy_select: select which phy should be accessed 5195 * @dev_addr: PHY device address 5196 * @reg_addr: PHY register address 5197 * @reg_val: read register value 5198 * @cmd_details: pointer to command details structure or NULL 5199 * 5200 * Read the external PHY register. 5201 **/ 5202 i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw, 5203 u8 phy_select, u8 dev_addr, 5204 u32 reg_addr, u32 *reg_val, 5205 struct i40e_asq_cmd_details *cmd_details) 5206 { 5207 struct i40e_aq_desc desc; 5208 struct i40e_aqc_phy_register_access *cmd = 5209 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5210 i40e_status status; 5211 5212 i40e_fill_default_direct_cmd_desc(&desc, 5213 i40e_aqc_opc_get_phy_register); 5214 5215 cmd->phy_interface = phy_select; 5216 cmd->dev_address = dev_addr; 5217 cmd->reg_address = cpu_to_le32(reg_addr); 5218 5219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5220 if (!status) 5221 *reg_val = le32_to_cpu(cmd->reg_value); 5222 5223 return status; 5224 } 5225 5226 /** 5227 * i40e_aq_write_ppp - Write pipeline personalization profile (ppp) 5228 * @hw: pointer to the hw struct 5229 * @buff: command buffer (size in bytes = buff_size) 5230 * @buff_size: buffer size in bytes 5231 * @track_id: package tracking id 5232 * @error_offset: returns error offset 5233 * @error_info: returns error information 5234 * @cmd_details: pointer to command details structure or NULL 5235 **/ 5236 enum 5237 i40e_status_code i40e_aq_write_ppp(struct i40e_hw *hw, void *buff, 5238 u16 buff_size, u32 track_id, 5239 u32 *error_offset, u32 *error_info, 5240 struct i40e_asq_cmd_details *cmd_details) 5241 { 5242 struct i40e_aq_desc desc; 5243 struct i40e_aqc_write_personalization_profile *cmd = 5244 (struct i40e_aqc_write_personalization_profile *) 5245 &desc.params.raw; 5246 struct i40e_aqc_write_ppp_resp *resp; 5247 i40e_status status; 5248 5249 i40e_fill_default_direct_cmd_desc(&desc, 5250 i40e_aqc_opc_write_personalization_profile); 5251 5252 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 5253 if (buff_size > I40E_AQ_LARGE_BUF) 5254 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5255 5256 desc.datalen = cpu_to_le16(buff_size); 5257 5258 cmd->profile_track_id = cpu_to_le32(track_id); 5259 5260 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5261 if (!status) { 5262 resp = (struct i40e_aqc_write_ppp_resp *)&desc.params.raw; 5263 if (error_offset) 5264 *error_offset = le32_to_cpu(resp->error_offset); 5265 if (error_info) 5266 *error_info = le32_to_cpu(resp->error_info); 5267 } 5268 5269 return status; 5270 } 5271 5272 /** 5273 * i40e_aq_get_ppp_list - Read pipeline personalization profile (ppp) 5274 * @hw: pointer to the hw struct 5275 * @buff: command buffer (size in bytes = buff_size) 5276 * @buff_size: buffer size in bytes 5277 * @cmd_details: pointer to command details structure or NULL 5278 **/ 5279 enum 5280 i40e_status_code i40e_aq_get_ppp_list(struct i40e_hw *hw, void *buff, 5281 u16 buff_size, u8 flags, 5282 struct i40e_asq_cmd_details *cmd_details) 5283 { 5284 struct i40e_aq_desc desc; 5285 struct i40e_aqc_get_applied_profiles *cmd = 5286 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 5287 i40e_status status; 5288 5289 i40e_fill_default_direct_cmd_desc(&desc, 5290 i40e_aqc_opc_get_personalization_profile_list); 5291 5292 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 5293 if (buff_size > I40E_AQ_LARGE_BUF) 5294 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5295 desc.datalen = cpu_to_le16(buff_size); 5296 5297 cmd->flags = flags; 5298 5299 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5300 5301 return status; 5302 } 5303 5304 /** 5305 * i40e_find_segment_in_package 5306 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 5307 * @pkg_hdr: pointer to the package header to be searched 5308 * 5309 * This function searches a package file for a particular segment type. On 5310 * success it returns a pointer to the segment header, otherwise it will 5311 * return NULL. 5312 **/ 5313 struct i40e_generic_seg_header * 5314 i40e_find_segment_in_package(u32 segment_type, 5315 struct i40e_package_header *pkg_hdr) 5316 { 5317 struct i40e_generic_seg_header *segment; 5318 u32 i; 5319 5320 /* Search all package segments for the requested segment type */ 5321 for (i = 0; i < pkg_hdr->segment_count; i++) { 5322 segment = 5323 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 5324 pkg_hdr->segment_offset[i]); 5325 5326 if (segment->type == segment_type) 5327 return segment; 5328 } 5329 5330 return NULL; 5331 } 5332 5333 /** 5334 * i40e_write_profile 5335 * @hw: pointer to the hardware structure 5336 * @profile: pointer to the profile segment of the package to be downloaded 5337 * @track_id: package tracking id 5338 * 5339 * Handles the download of a complete package. 5340 */ 5341 enum i40e_status_code 5342 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5343 u32 track_id) 5344 { 5345 i40e_status status = 0; 5346 struct i40e_section_table *sec_tbl; 5347 struct i40e_profile_section_header *sec = NULL; 5348 u32 dev_cnt; 5349 u32 vendor_dev_id; 5350 u32 *nvm; 5351 u32 section_size = 0; 5352 u32 offset = 0, info = 0; 5353 u32 i; 5354 5355 if (!track_id) { 5356 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0."); 5357 return I40E_NOT_SUPPORTED; 5358 } 5359 5360 dev_cnt = profile->device_table_count; 5361 5362 for (i = 0; i < dev_cnt; i++) { 5363 vendor_dev_id = profile->device_table[i].vendor_dev_id; 5364 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL) 5365 if (hw->device_id == (vendor_dev_id & 0xFFFF)) 5366 break; 5367 } 5368 if (i == dev_cnt) { 5369 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support PPP"); 5370 return I40E_ERR_DEVICE_NOT_SUPPORTED; 5371 } 5372 5373 nvm = (u32 *)&profile->device_table[dev_cnt]; 5374 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; 5375 5376 for (i = 0; i < sec_tbl->section_count; i++) { 5377 sec = (struct i40e_profile_section_header *)((u8 *)profile + 5378 sec_tbl->section_offset[i]); 5379 5380 /* Skip 'AQ', 'note' and 'name' sections */ 5381 if (sec->section.type != SECTION_TYPE_MMIO) 5382 continue; 5383 5384 section_size = sec->section.size + 5385 sizeof(struct i40e_profile_section_header); 5386 5387 /* Write profile */ 5388 status = i40e_aq_write_ppp(hw, (void *)sec, (u16)section_size, 5389 track_id, &offset, &info, NULL); 5390 if (status) { 5391 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5392 "Failed to write profile: offset %d, info %d", 5393 offset, info); 5394 break; 5395 } 5396 } 5397 return status; 5398 } 5399 5400 /** 5401 * i40e_add_pinfo_to_list 5402 * @hw: pointer to the hardware structure 5403 * @profile: pointer to the profile segment of the package 5404 * @profile_info_sec: buffer for information section 5405 * @track_id: package tracking id 5406 * 5407 * Register a profile to the list of loaded profiles. 5408 */ 5409 enum i40e_status_code 5410 i40e_add_pinfo_to_list(struct i40e_hw *hw, 5411 struct i40e_profile_segment *profile, 5412 u8 *profile_info_sec, u32 track_id) 5413 { 5414 i40e_status status = 0; 5415 struct i40e_profile_section_header *sec = NULL; 5416 struct i40e_profile_info *pinfo; 5417 u32 offset = 0, info = 0; 5418 5419 sec = (struct i40e_profile_section_header *)profile_info_sec; 5420 sec->tbl_size = 1; 5421 sec->data_end = sizeof(struct i40e_profile_section_header) + 5422 sizeof(struct i40e_profile_info); 5423 sec->section.type = SECTION_TYPE_INFO; 5424 sec->section.offset = sizeof(struct i40e_profile_section_header); 5425 sec->section.size = sizeof(struct i40e_profile_info); 5426 pinfo = (struct i40e_profile_info *)(profile_info_sec + 5427 sec->section.offset); 5428 pinfo->track_id = track_id; 5429 pinfo->version = profile->version; 5430 pinfo->op = I40E_PPP_ADD_TRACKID; 5431 memcpy(pinfo->name, profile->name, I40E_PPP_NAME_SIZE); 5432 5433 status = i40e_aq_write_ppp(hw, (void *)sec, sec->data_end, 5434 track_id, &offset, &info, NULL); 5435 return status; 5436 } 5437