1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #include <linux/avf/virtchnl.h> 5 #include <linux/bitfield.h> 6 #include <linux/delay.h> 7 #include <linux/etherdevice.h> 8 #include <linux/pci.h> 9 #include "i40e_adminq_cmd.h" 10 #include "i40e_devids.h" 11 #include "i40e_prototype.h" 12 #include "i40e_register.h" 13 14 /** 15 * i40e_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the mac type of the adapter based on the 19 * vendor ID and device ID stored in the hw structure. 20 **/ 21 int i40e_set_mac_type(struct i40e_hw *hw) 22 { 23 int status = 0; 24 25 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 26 switch (hw->device_id) { 27 case I40E_DEV_ID_SFP_XL710: 28 case I40E_DEV_ID_QEMU: 29 case I40E_DEV_ID_KX_B: 30 case I40E_DEV_ID_KX_C: 31 case I40E_DEV_ID_QSFP_A: 32 case I40E_DEV_ID_QSFP_B: 33 case I40E_DEV_ID_QSFP_C: 34 case I40E_DEV_ID_1G_BASE_T_BC: 35 case I40E_DEV_ID_5G_BASE_T_BC: 36 case I40E_DEV_ID_10G_BASE_T: 37 case I40E_DEV_ID_10G_BASE_T4: 38 case I40E_DEV_ID_10G_BASE_T_BC: 39 case I40E_DEV_ID_10G_B: 40 case I40E_DEV_ID_10G_SFP: 41 case I40E_DEV_ID_20G_KR2: 42 case I40E_DEV_ID_20G_KR2_A: 43 case I40E_DEV_ID_25G_B: 44 case I40E_DEV_ID_25G_SFP28: 45 case I40E_DEV_ID_X710_N3000: 46 case I40E_DEV_ID_XXV710_N3000: 47 hw->mac.type = I40E_MAC_XL710; 48 break; 49 case I40E_DEV_ID_KX_X722: 50 case I40E_DEV_ID_QSFP_X722: 51 case I40E_DEV_ID_SFP_X722: 52 case I40E_DEV_ID_1G_BASE_T_X722: 53 case I40E_DEV_ID_10G_BASE_T_X722: 54 case I40E_DEV_ID_SFP_I_X722: 55 case I40E_DEV_ID_SFP_X722_A: 56 hw->mac.type = I40E_MAC_X722; 57 break; 58 default: 59 hw->mac.type = I40E_MAC_GENERIC; 60 break; 61 } 62 } else { 63 status = -ENODEV; 64 } 65 66 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 67 hw->mac.type, status); 68 return status; 69 } 70 71 /** 72 * i40e_aq_str - convert AQ err code to a string 73 * @hw: pointer to the HW structure 74 * @aq_err: the AQ error code to convert 75 **/ 76 const char *i40e_aq_str(struct i40e_hw *hw, enum libie_aq_err aq_err) 77 { 78 switch (aq_err) { 79 case LIBIE_AQ_RC_OK: 80 return "OK"; 81 case LIBIE_AQ_RC_EPERM: 82 return "LIBIE_AQ_RC_EPERM"; 83 case LIBIE_AQ_RC_ENOENT: 84 return "LIBIE_AQ_RC_ENOENT"; 85 case LIBIE_AQ_RC_ESRCH: 86 return "LIBIE_AQ_RC_ESRCH"; 87 case LIBIE_AQ_RC_EIO: 88 return "LIBIE_AQ_RC_EIO"; 89 case LIBIE_AQ_RC_EAGAIN: 90 return "LIBIE_AQ_RC_EAGAIN"; 91 case LIBIE_AQ_RC_ENOMEM: 92 return "LIBIE_AQ_RC_ENOMEM"; 93 case LIBIE_AQ_RC_EACCES: 94 return "LIBIE_AQ_RC_EACCES"; 95 case LIBIE_AQ_RC_EBUSY: 96 return "LIBIE_AQ_RC_EBUSY"; 97 case LIBIE_AQ_RC_EEXIST: 98 return "LIBIE_AQ_RC_EEXIST"; 99 case LIBIE_AQ_RC_EINVAL: 100 return "LIBIE_AQ_RC_EINVAL"; 101 case LIBIE_AQ_RC_ENOSPC: 102 return "LIBIE_AQ_RC_ENOSPC"; 103 case LIBIE_AQ_RC_ENOSYS: 104 return "LIBIE_AQ_RC_ENOSYS"; 105 case LIBIE_AQ_RC_EMODE: 106 return "LIBIE_AQ_RC_EMODE"; 107 case LIBIE_AQ_RC_ENOSEC: 108 return "LIBIE_AQ_RC_ENOSEC"; 109 case LIBIE_AQ_RC_EBADSIG: 110 return "LIBIE_AQ_RC_EBADSIG"; 111 case LIBIE_AQ_RC_ESVN: 112 return "LIBIE_AQ_RC_ESVN"; 113 case LIBIE_AQ_RC_EBADMAN: 114 return "LIBIE_AQ_RC_EBADMAN"; 115 case LIBIE_AQ_RC_EBADBUF: 116 return "LIBIE_AQ_RC_EBADBUF"; 117 } 118 119 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 120 return hw->err_str; 121 } 122 123 /** 124 * i40e_debug_aq 125 * @hw: debug mask related to admin queue 126 * @mask: debug mask 127 * @desc: pointer to admin queue descriptor 128 * @buffer: pointer to command buffer 129 * @buf_len: max length of buffer 130 * 131 * Dumps debug log about adminq command with descriptor contents. 132 **/ 133 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 134 void *buffer, u16 buf_len) 135 { 136 struct libie_aq_desc *aq_desc = (struct libie_aq_desc *)desc; 137 u32 effective_mask = hw->debug_mask & mask; 138 char prefix[27]; 139 u16 len; 140 u8 *buf = (u8 *)buffer; 141 142 if (!effective_mask || !desc) 143 return; 144 145 len = le16_to_cpu(aq_desc->datalen); 146 147 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 148 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 149 le16_to_cpu(aq_desc->opcode), 150 le16_to_cpu(aq_desc->flags), 151 le16_to_cpu(aq_desc->datalen), 152 le16_to_cpu(aq_desc->retval)); 153 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 154 "\tcookie (h,l) 0x%08X 0x%08X\n", 155 le32_to_cpu(aq_desc->cookie_high), 156 le32_to_cpu(aq_desc->cookie_low)); 157 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 158 "\tparam (0,1) 0x%08X 0x%08X\n", 159 le32_to_cpu(aq_desc->params.generic.param0), 160 le32_to_cpu(aq_desc->params.generic.param1)); 161 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 162 "\taddr (h,l) 0x%08X 0x%08X\n", 163 le32_to_cpu(aq_desc->params.generic.addr_high), 164 le32_to_cpu(aq_desc->params.generic.addr_low)); 165 166 if (buffer && buf_len != 0 && len != 0 && 167 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { 168 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 169 if (buf_len < len) 170 len = buf_len; 171 172 snprintf(prefix, sizeof(prefix), 173 "i40e %02x:%02x.%x: \t0x", 174 hw->bus.bus_id, 175 hw->bus.device, 176 hw->bus.func); 177 178 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 179 16, 1, buf, len, false); 180 } 181 } 182 183 /** 184 * i40e_check_asq_alive 185 * @hw: pointer to the hw struct 186 * 187 * Returns true if Queue is enabled else false. 188 **/ 189 bool i40e_check_asq_alive(struct i40e_hw *hw) 190 { 191 /* Check if the queue is initialized */ 192 if (!hw->aq.asq.count) 193 return false; 194 195 return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK); 196 } 197 198 /** 199 * i40e_aq_queue_shutdown 200 * @hw: pointer to the hw struct 201 * @unloading: is the driver unloading itself 202 * 203 * Tell the Firmware that we're shutting down the AdminQ and whether 204 * or not the driver is unloading as well. 205 **/ 206 int i40e_aq_queue_shutdown(struct i40e_hw *hw, 207 bool unloading) 208 { 209 struct i40e_aqc_queue_shutdown *cmd; 210 struct libie_aq_desc desc; 211 int status; 212 213 i40e_fill_default_direct_cmd_desc(&desc, 214 i40e_aqc_opc_queue_shutdown); 215 216 cmd = libie_aq_raw(&desc); 217 if (unloading) 218 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 219 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 220 221 return status; 222 } 223 224 /** 225 * i40e_aq_get_set_rss_lut 226 * @hw: pointer to the hardware structure 227 * @vsi_id: vsi fw index 228 * @pf_lut: for PF table set true, for VSI table set false 229 * @lut: pointer to the lut buffer provided by the caller 230 * @lut_size: size of the lut buffer 231 * @set: set true to set the table, false to get the table 232 * 233 * Internal function to get or set RSS look up table 234 **/ 235 static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 236 u16 vsi_id, bool pf_lut, 237 u8 *lut, u16 lut_size, 238 bool set) 239 { 240 struct i40e_aqc_get_set_rss_lut *cmd_resp; 241 struct libie_aq_desc desc; 242 int status; 243 u16 flags; 244 245 if (set) 246 i40e_fill_default_direct_cmd_desc(&desc, 247 i40e_aqc_opc_set_rss_lut); 248 else 249 i40e_fill_default_direct_cmd_desc(&desc, 250 i40e_aqc_opc_get_rss_lut); 251 252 cmd_resp = libie_aq_raw(&desc); 253 /* Indirect command */ 254 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 255 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 256 257 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) | 258 FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1); 259 cmd_resp->vsi_id = cpu_to_le16(vsi_id); 260 261 if (pf_lut) 262 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 263 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF); 264 else 265 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 266 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI); 267 268 cmd_resp->flags = cpu_to_le16(flags); 269 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 270 271 return status; 272 } 273 274 /** 275 * i40e_aq_get_rss_lut 276 * @hw: pointer to the hardware structure 277 * @vsi_id: vsi fw index 278 * @pf_lut: for PF table set true, for VSI table set false 279 * @lut: pointer to the lut buffer provided by the caller 280 * @lut_size: size of the lut buffer 281 * 282 * get the RSS lookup table, PF or VSI type 283 **/ 284 int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 285 bool pf_lut, u8 *lut, u16 lut_size) 286 { 287 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 288 false); 289 } 290 291 /** 292 * i40e_aq_set_rss_lut 293 * @hw: pointer to the hardware structure 294 * @vsi_id: vsi fw index 295 * @pf_lut: for PF table set true, for VSI table set false 296 * @lut: pointer to the lut buffer provided by the caller 297 * @lut_size: size of the lut buffer 298 * 299 * set the RSS lookup table, PF or VSI type 300 **/ 301 int i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 302 bool pf_lut, u8 *lut, u16 lut_size) 303 { 304 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 305 } 306 307 /** 308 * i40e_aq_get_set_rss_key 309 * @hw: pointer to the hw struct 310 * @vsi_id: vsi fw index 311 * @key: pointer to key info struct 312 * @set: set true to set the key, false to get the key 313 * 314 * get the RSS key per VSI 315 **/ 316 static int i40e_aq_get_set_rss_key(struct i40e_hw *hw, 317 u16 vsi_id, 318 struct i40e_aqc_get_set_rss_key_data *key, 319 bool set) 320 { 321 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 322 struct i40e_aqc_get_set_rss_key *cmd_resp; 323 struct libie_aq_desc desc; 324 int status; 325 326 if (set) 327 i40e_fill_default_direct_cmd_desc(&desc, 328 i40e_aqc_opc_set_rss_key); 329 else 330 i40e_fill_default_direct_cmd_desc(&desc, 331 i40e_aqc_opc_get_rss_key); 332 333 cmd_resp = libie_aq_raw(&desc); 334 /* Indirect command */ 335 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 336 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 337 338 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) | 339 FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1); 340 cmd_resp->vsi_id = cpu_to_le16(vsi_id); 341 342 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 343 344 return status; 345 } 346 347 /** 348 * i40e_aq_get_rss_key 349 * @hw: pointer to the hw struct 350 * @vsi_id: vsi fw index 351 * @key: pointer to key info struct 352 * 353 **/ 354 int i40e_aq_get_rss_key(struct i40e_hw *hw, 355 u16 vsi_id, 356 struct i40e_aqc_get_set_rss_key_data *key) 357 { 358 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 359 } 360 361 /** 362 * i40e_aq_set_rss_key 363 * @hw: pointer to the hw struct 364 * @vsi_id: vsi fw index 365 * @key: pointer to key info struct 366 * 367 * set the RSS key per VSI 368 **/ 369 int i40e_aq_set_rss_key(struct i40e_hw *hw, 370 u16 vsi_id, 371 struct i40e_aqc_get_set_rss_key_data *key) 372 { 373 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 374 } 375 376 /** 377 * i40e_init_shared_code - Initialize the shared code 378 * @hw: pointer to hardware structure 379 * 380 * This assigns the MAC type and PHY code and inits the NVM. 381 * Does not touch the hardware. This function must be called prior to any 382 * other function in the shared code. The i40e_hw structure should be 383 * memset to 0 prior to calling this function. The following fields in 384 * hw structure should be filled in prior to calling this function: 385 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 386 * subsystem_vendor_id, and revision_id 387 **/ 388 int i40e_init_shared_code(struct i40e_hw *hw) 389 { 390 u32 port, ari, func_rid; 391 int status = 0; 392 393 i40e_set_mac_type(hw); 394 395 switch (hw->mac.type) { 396 case I40E_MAC_XL710: 397 case I40E_MAC_X722: 398 break; 399 default: 400 return -ENODEV; 401 } 402 403 hw->phy.get_link_info = true; 404 405 /* Determine port number and PF number*/ 406 port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK, 407 rd32(hw, I40E_PFGEN_PORTNUM)); 408 hw->port = (u8)port; 409 ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK, 410 rd32(hw, I40E_GLPCI_CAPSUP)); 411 func_rid = rd32(hw, I40E_PF_FUNC_RID); 412 if (ari) 413 hw->pf_id = (u8)(func_rid & 0xff); 414 else 415 hw->pf_id = (u8)(func_rid & 0x7); 416 417 status = i40e_init_nvm(hw); 418 return status; 419 } 420 421 /** 422 * i40e_aq_mac_address_read - Retrieve the MAC addresses 423 * @hw: pointer to the hw struct 424 * @flags: a return indicator of what addresses were added to the addr store 425 * @addrs: the requestor's mac addr store 426 * @cmd_details: pointer to command details structure or NULL 427 **/ 428 static int 429 i40e_aq_mac_address_read(struct i40e_hw *hw, 430 u16 *flags, 431 struct i40e_aqc_mac_address_read_data *addrs, 432 struct i40e_asq_cmd_details *cmd_details) 433 { 434 struct i40e_aqc_mac_address_read *cmd_data; 435 struct libie_aq_desc desc; 436 int status; 437 438 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 439 cmd_data = libie_aq_raw(&desc); 440 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF); 441 442 status = i40e_asq_send_command(hw, &desc, addrs, 443 sizeof(*addrs), cmd_details); 444 *flags = le16_to_cpu(cmd_data->command_flags); 445 446 return status; 447 } 448 449 /** 450 * i40e_aq_mac_address_write - Change the MAC addresses 451 * @hw: pointer to the hw struct 452 * @flags: indicates which MAC to be written 453 * @mac_addr: address to write 454 * @cmd_details: pointer to command details structure or NULL 455 **/ 456 int i40e_aq_mac_address_write(struct i40e_hw *hw, 457 u16 flags, u8 *mac_addr, 458 struct i40e_asq_cmd_details *cmd_details) 459 { 460 struct i40e_aqc_mac_address_write *cmd_data; 461 struct libie_aq_desc desc; 462 int status; 463 464 i40e_fill_default_direct_cmd_desc(&desc, 465 i40e_aqc_opc_mac_address_write); 466 cmd_data = libie_aq_raw(&desc); 467 cmd_data->command_flags = cpu_to_le16(flags); 468 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 469 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 470 ((u32)mac_addr[3] << 16) | 471 ((u32)mac_addr[4] << 8) | 472 mac_addr[5]); 473 474 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 475 476 return status; 477 } 478 479 /** 480 * i40e_get_mac_addr - get MAC address 481 * @hw: pointer to the HW structure 482 * @mac_addr: pointer to MAC address 483 * 484 * Reads the adapter's MAC address from register 485 **/ 486 int i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 487 { 488 struct i40e_aqc_mac_address_read_data addrs; 489 u16 flags = 0; 490 int status; 491 492 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 493 494 if (flags & I40E_AQC_LAN_ADDR_VALID) 495 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 496 497 return status; 498 } 499 500 /** 501 * i40e_get_port_mac_addr - get Port MAC address 502 * @hw: pointer to the HW structure 503 * @mac_addr: pointer to Port MAC address 504 * 505 * Reads the adapter's Port MAC address 506 **/ 507 int i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 508 { 509 struct i40e_aqc_mac_address_read_data addrs; 510 u16 flags = 0; 511 int status; 512 513 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 514 if (status) 515 return status; 516 517 if (flags & I40E_AQC_PORT_ADDR_VALID) 518 ether_addr_copy(mac_addr, addrs.port_mac); 519 else 520 status = -EINVAL; 521 522 return status; 523 } 524 525 /** 526 * i40e_pre_tx_queue_cfg - pre tx queue configure 527 * @hw: pointer to the HW structure 528 * @queue: target PF queue index 529 * @enable: state change request 530 * 531 * Handles hw requirement to indicate intention to enable 532 * or disable target queue. 533 **/ 534 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 535 { 536 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 537 u32 reg_block = 0; 538 u32 reg_val; 539 540 if (abs_queue_idx >= 128) { 541 reg_block = abs_queue_idx / 128; 542 abs_queue_idx %= 128; 543 } 544 545 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 546 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 547 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 548 549 if (enable) 550 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 551 else 552 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 553 554 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 555 } 556 557 /** 558 * i40e_get_pba_string - Reads part number string from EEPROM 559 * @hw: pointer to hardware structure 560 * 561 * Reads the part number string from the EEPROM and stores it 562 * into newly allocated buffer and saves resulting pointer 563 * to i40e_hw->pba_id field. 564 **/ 565 void i40e_get_pba_string(struct i40e_hw *hw) 566 { 567 #define I40E_NVM_PBA_FLAGS_BLK_PRESENT 0xFAFA 568 u16 pba_word = 0; 569 u16 pba_size = 0; 570 u16 pba_ptr = 0; 571 int status; 572 char *ptr; 573 u16 i; 574 575 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 576 if (status) { 577 hw_dbg(hw, "Failed to read PBA flags.\n"); 578 return; 579 } 580 if (pba_word != I40E_NVM_PBA_FLAGS_BLK_PRESENT) { 581 hw_dbg(hw, "PBA block is not present.\n"); 582 return; 583 } 584 585 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 586 if (status) { 587 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 588 return; 589 } 590 591 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 592 if (status) { 593 hw_dbg(hw, "Failed to read PBA Block size.\n"); 594 return; 595 } 596 597 /* Subtract one to get PBA word count (PBA Size word is included in 598 * total size) and advance pointer to first PBA word. 599 */ 600 pba_size--; 601 pba_ptr++; 602 if (!pba_size) { 603 hw_dbg(hw, "PBA ID is empty.\n"); 604 return; 605 } 606 607 ptr = devm_kzalloc(i40e_hw_to_dev(hw), pba_size * 2 + 1, GFP_KERNEL); 608 if (!ptr) 609 return; 610 hw->pba_id = ptr; 611 612 for (i = 0; i < pba_size; i++) { 613 status = i40e_read_nvm_word(hw, pba_ptr + i, &pba_word); 614 if (status) { 615 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 616 devm_kfree(i40e_hw_to_dev(hw), hw->pba_id); 617 hw->pba_id = NULL; 618 return; 619 } 620 621 *ptr++ = (pba_word >> 8) & 0xFF; 622 *ptr++ = pba_word & 0xFF; 623 } 624 } 625 626 /** 627 * i40e_get_media_type - Gets media type 628 * @hw: pointer to the hardware structure 629 **/ 630 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 631 { 632 enum i40e_media_type media; 633 634 switch (hw->phy.link_info.phy_type) { 635 case I40E_PHY_TYPE_10GBASE_SR: 636 case I40E_PHY_TYPE_10GBASE_LR: 637 case I40E_PHY_TYPE_1000BASE_SX: 638 case I40E_PHY_TYPE_1000BASE_LX: 639 case I40E_PHY_TYPE_40GBASE_SR4: 640 case I40E_PHY_TYPE_40GBASE_LR4: 641 case I40E_PHY_TYPE_25GBASE_LR: 642 case I40E_PHY_TYPE_25GBASE_SR: 643 media = I40E_MEDIA_TYPE_FIBER; 644 break; 645 case I40E_PHY_TYPE_100BASE_TX: 646 case I40E_PHY_TYPE_1000BASE_T: 647 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS: 648 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS: 649 case I40E_PHY_TYPE_10GBASE_T: 650 media = I40E_MEDIA_TYPE_BASET; 651 break; 652 case I40E_PHY_TYPE_10GBASE_CR1_CU: 653 case I40E_PHY_TYPE_40GBASE_CR4_CU: 654 case I40E_PHY_TYPE_10GBASE_CR1: 655 case I40E_PHY_TYPE_40GBASE_CR4: 656 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 657 case I40E_PHY_TYPE_40GBASE_AOC: 658 case I40E_PHY_TYPE_10GBASE_AOC: 659 case I40E_PHY_TYPE_25GBASE_CR: 660 case I40E_PHY_TYPE_25GBASE_AOC: 661 case I40E_PHY_TYPE_25GBASE_ACC: 662 media = I40E_MEDIA_TYPE_DA; 663 break; 664 case I40E_PHY_TYPE_1000BASE_KX: 665 case I40E_PHY_TYPE_10GBASE_KX4: 666 case I40E_PHY_TYPE_10GBASE_KR: 667 case I40E_PHY_TYPE_40GBASE_KR4: 668 case I40E_PHY_TYPE_20GBASE_KR2: 669 case I40E_PHY_TYPE_25GBASE_KR: 670 media = I40E_MEDIA_TYPE_BACKPLANE; 671 break; 672 case I40E_PHY_TYPE_SGMII: 673 case I40E_PHY_TYPE_XAUI: 674 case I40E_PHY_TYPE_XFI: 675 case I40E_PHY_TYPE_XLAUI: 676 case I40E_PHY_TYPE_XLPPI: 677 default: 678 media = I40E_MEDIA_TYPE_UNKNOWN; 679 break; 680 } 681 682 return media; 683 } 684 685 /** 686 * i40e_poll_globr - Poll for Global Reset completion 687 * @hw: pointer to the hardware structure 688 * @retry_limit: how many times to retry before failure 689 **/ 690 static int i40e_poll_globr(struct i40e_hw *hw, 691 u32 retry_limit) 692 { 693 u32 cnt, reg = 0; 694 695 for (cnt = 0; cnt < retry_limit; cnt++) { 696 reg = rd32(hw, I40E_GLGEN_RSTAT); 697 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 698 return 0; 699 msleep(100); 700 } 701 702 hw_dbg(hw, "Global reset failed.\n"); 703 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg); 704 705 return -EIO; 706 } 707 708 #define I40E_PF_RESET_WAIT_COUNT_A0 200 709 #define I40E_PF_RESET_WAIT_COUNT 200 710 /** 711 * i40e_pf_reset - Reset the PF 712 * @hw: pointer to the hardware structure 713 * 714 * Assuming someone else has triggered a global reset, 715 * assure the global reset is complete and then reset the PF 716 **/ 717 int i40e_pf_reset(struct i40e_hw *hw) 718 { 719 u32 cnt = 0; 720 u32 cnt1 = 0; 721 u32 reg = 0; 722 u32 grst_del; 723 724 /* Poll for Global Reset steady state in case of recent GRST. 725 * The grst delay value is in 100ms units, and we'll wait a 726 * couple counts longer to be sure we don't just miss the end. 727 */ 728 grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK, 729 rd32(hw, I40E_GLGEN_RSTCTL)); 730 731 /* It can take upto 15 secs for GRST steady state. 732 * Bump it to 16 secs max to be safe. 733 */ 734 grst_del = grst_del * 20; 735 736 for (cnt = 0; cnt < grst_del; cnt++) { 737 reg = rd32(hw, I40E_GLGEN_RSTAT); 738 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 739 break; 740 msleep(100); 741 } 742 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 743 hw_dbg(hw, "Global reset polling failed to complete.\n"); 744 return -EIO; 745 } 746 747 /* Now Wait for the FW to be ready */ 748 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 749 reg = rd32(hw, I40E_GLNVM_ULD); 750 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 751 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 752 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 753 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 754 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 755 break; 756 } 757 usleep_range(10000, 20000); 758 } 759 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 760 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 761 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 762 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 763 return -EIO; 764 } 765 766 /* If there was a Global Reset in progress when we got here, 767 * we don't need to do the PF Reset 768 */ 769 if (!cnt) { 770 u32 reg2 = 0; 771 if (hw->revision_id == 0) 772 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 773 else 774 cnt = I40E_PF_RESET_WAIT_COUNT; 775 reg = rd32(hw, I40E_PFGEN_CTRL); 776 wr32(hw, I40E_PFGEN_CTRL, 777 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 778 for (; cnt; cnt--) { 779 reg = rd32(hw, I40E_PFGEN_CTRL); 780 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 781 break; 782 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 783 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 784 break; 785 usleep_range(1000, 2000); 786 } 787 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 788 if (i40e_poll_globr(hw, grst_del)) 789 return -EIO; 790 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 791 hw_dbg(hw, "PF reset polling failed to complete.\n"); 792 return -EIO; 793 } 794 } 795 796 i40e_clear_pxe_mode(hw); 797 798 return 0; 799 } 800 801 /** 802 * i40e_clear_hw - clear out any left over hw state 803 * @hw: pointer to the hw struct 804 * 805 * Clear queues and interrupts, typically called at init time, 806 * but after the capabilities have been found so we know how many 807 * queues and msix vectors have been allocated. 808 **/ 809 void i40e_clear_hw(struct i40e_hw *hw) 810 { 811 u32 num_queues, base_queue; 812 s32 num_pf_int; 813 s32 num_vf_int; 814 u32 num_vfs; 815 s32 i; 816 u32 j; 817 u32 val; 818 u32 eol = 0x7ff; 819 820 /* get number of interrupts, queues, and VFs */ 821 val = rd32(hw, I40E_GLPCI_CNF2); 822 num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val); 823 num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val); 824 825 val = rd32(hw, I40E_PFLAN_QALLOC); 826 base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val); 827 j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val); 828 if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue) 829 num_queues = (j - base_queue) + 1; 830 else 831 num_queues = 0; 832 833 val = rd32(hw, I40E_PF_VT_PFALLOC); 834 i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val); 835 j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val); 836 if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i) 837 num_vfs = (j - i) + 1; 838 else 839 num_vfs = 0; 840 841 /* stop all the interrupts */ 842 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 843 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 844 for (i = 0; i < num_pf_int - 2; i++) 845 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 846 847 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 848 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 849 wr32(hw, I40E_PFINT_LNKLST0, val); 850 for (i = 0; i < num_pf_int - 2; i++) 851 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 852 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 853 for (i = 0; i < num_vfs; i++) 854 wr32(hw, I40E_VPINT_LNKLST0(i), val); 855 for (i = 0; i < num_vf_int - 2; i++) 856 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 857 858 /* warn the HW of the coming Tx disables */ 859 for (i = 0; i < num_queues; i++) { 860 u32 abs_queue_idx = base_queue + i; 861 u32 reg_block = 0; 862 863 if (abs_queue_idx >= 128) { 864 reg_block = abs_queue_idx / 128; 865 abs_queue_idx %= 128; 866 } 867 868 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 869 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 870 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 871 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 872 873 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 874 } 875 udelay(400); 876 877 /* stop all the queues */ 878 for (i = 0; i < num_queues; i++) { 879 wr32(hw, I40E_QINT_TQCTL(i), 0); 880 wr32(hw, I40E_QTX_ENA(i), 0); 881 wr32(hw, I40E_QINT_RQCTL(i), 0); 882 wr32(hw, I40E_QRX_ENA(i), 0); 883 } 884 885 /* short wait for all queue disables to settle */ 886 udelay(50); 887 } 888 889 /** 890 * i40e_clear_pxe_mode - clear pxe operations mode 891 * @hw: pointer to the hw struct 892 * 893 * Make sure all PXE mode settings are cleared, including things 894 * like descriptor fetch/write-back mode. 895 **/ 896 void i40e_clear_pxe_mode(struct i40e_hw *hw) 897 { 898 u32 reg; 899 900 if (i40e_check_asq_alive(hw)) 901 i40e_aq_clear_pxe_mode(hw, NULL); 902 903 /* Clear single descriptor fetch/write-back mode */ 904 reg = rd32(hw, I40E_GLLAN_RCTL_0); 905 906 if (hw->revision_id == 0) { 907 /* As a work around clear PXE_MODE instead of setting it */ 908 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 909 } else { 910 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 911 } 912 } 913 914 /** 915 * i40e_led_is_mine - helper to find matching led 916 * @hw: pointer to the hw struct 917 * @idx: index into GPIO registers 918 * 919 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 920 */ 921 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 922 { 923 u32 gpio_val = 0; 924 u32 port; 925 926 if (!I40E_IS_X710TL_DEVICE(hw->device_id) && 927 !hw->func_caps.led[idx]) 928 return 0; 929 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 930 port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val); 931 932 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 933 * if it is not our port then ignore 934 */ 935 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 936 (port != hw->port)) 937 return 0; 938 939 return gpio_val; 940 } 941 942 #define I40E_FW_LED BIT(4) 943 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \ 944 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 945 946 #define I40E_LED0 22 947 948 #define I40E_PIN_FUNC_SDP 0x0 949 #define I40E_PIN_FUNC_LED 0x1 950 951 /** 952 * i40e_led_get - return current on/off mode 953 * @hw: pointer to the hw struct 954 * 955 * The value returned is the 'mode' field as defined in the 956 * GPIO register definitions: 0x0 = off, 0xf = on, and other 957 * values are variations of possible behaviors relating to 958 * blink, link, and wire. 959 **/ 960 u32 i40e_led_get(struct i40e_hw *hw) 961 { 962 u32 mode = 0; 963 int i; 964 965 /* as per the documentation GPIO 22-29 are the LED 966 * GPIO pins named LED0..LED7 967 */ 968 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 969 u32 gpio_val = i40e_led_is_mine(hw, i); 970 971 if (!gpio_val) 972 continue; 973 974 mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val); 975 break; 976 } 977 978 return mode; 979 } 980 981 /** 982 * i40e_led_set - set new on/off mode 983 * @hw: pointer to the hw struct 984 * @mode: 0=off, 0xf=on (else see manual for mode details) 985 * @blink: true if the LED should blink when on, false if steady 986 * 987 * if this function is used to turn on the blink it should 988 * be used to disable the blink when restoring the original state. 989 **/ 990 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 991 { 992 int i; 993 994 if (mode & ~I40E_LED_MODE_VALID) { 995 hw_dbg(hw, "invalid mode passed in %X\n", mode); 996 return; 997 } 998 999 /* as per the documentation GPIO 22-29 are the LED 1000 * GPIO pins named LED0..LED7 1001 */ 1002 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1003 u32 gpio_val = i40e_led_is_mine(hw, i); 1004 1005 if (!gpio_val) 1006 continue; 1007 1008 if (I40E_IS_X710TL_DEVICE(hw->device_id)) { 1009 u32 pin_func = 0; 1010 1011 if (mode & I40E_FW_LED) 1012 pin_func = I40E_PIN_FUNC_SDP; 1013 else 1014 pin_func = I40E_PIN_FUNC_LED; 1015 1016 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK; 1017 gpio_val |= 1018 FIELD_PREP(I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK, 1019 pin_func); 1020 } 1021 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1022 /* this & is a bit of paranoia, but serves as a range check */ 1023 gpio_val |= FIELD_PREP(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, 1024 mode); 1025 1026 if (blink) 1027 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1028 else 1029 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1030 1031 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1032 break; 1033 } 1034 } 1035 1036 /* Admin command wrappers */ 1037 1038 /** 1039 * i40e_aq_get_phy_capabilities 1040 * @hw: pointer to the hw struct 1041 * @abilities: structure for PHY capabilities to be filled 1042 * @qualified_modules: report Qualified Modules 1043 * @report_init: report init capabilities (active are default) 1044 * @cmd_details: pointer to command details structure or NULL 1045 * 1046 * Returns the various PHY abilities supported on the Port. 1047 **/ 1048 int 1049 i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1050 bool qualified_modules, bool report_init, 1051 struct i40e_aq_get_phy_abilities_resp *abilities, 1052 struct i40e_asq_cmd_details *cmd_details) 1053 { 1054 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1055 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1056 struct libie_aq_desc desc; 1057 int status; 1058 1059 if (!abilities) 1060 return -EINVAL; 1061 1062 do { 1063 i40e_fill_default_direct_cmd_desc(&desc, 1064 i40e_aqc_opc_get_phy_abilities); 1065 1066 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1067 if (abilities_size > I40E_AQ_LARGE_BUF) 1068 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 1069 1070 if (qualified_modules) 1071 desc.params.generic.param0 |= 1072 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1073 1074 if (report_init) 1075 desc.params.generic.param0 |= 1076 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1077 1078 status = i40e_asq_send_command(hw, &desc, abilities, 1079 abilities_size, cmd_details); 1080 1081 switch (hw->aq.asq_last_status) { 1082 case LIBIE_AQ_RC_EIO: 1083 status = -EIO; 1084 break; 1085 case LIBIE_AQ_RC_EAGAIN: 1086 usleep_range(1000, 2000); 1087 total_delay++; 1088 status = -EIO; 1089 break; 1090 /* also covers LIBIE_AQ_RC_OK */ 1091 default: 1092 break; 1093 } 1094 1095 } while ((hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN) && 1096 (total_delay < max_delay)); 1097 1098 if (status) 1099 return status; 1100 1101 if (report_init) { 1102 if (hw->mac.type == I40E_MAC_XL710 && 1103 i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR, 1104 I40E_MINOR_VER_GET_LINK_INFO_XL710)) { 1105 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1106 } else { 1107 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1108 hw->phy.phy_types |= 1109 ((u64)abilities->phy_type_ext << 32); 1110 } 1111 } 1112 1113 return status; 1114 } 1115 1116 /** 1117 * i40e_aq_set_phy_config 1118 * @hw: pointer to the hw struct 1119 * @config: structure with PHY configuration to be set 1120 * @cmd_details: pointer to command details structure or NULL 1121 * 1122 * Set the various PHY configuration parameters 1123 * supported on the Port.One or more of the Set PHY config parameters may be 1124 * ignored in an MFP mode as the PF may not have the privilege to set some 1125 * of the PHY Config parameters. This status will be indicated by the 1126 * command response. 1127 **/ 1128 int i40e_aq_set_phy_config(struct i40e_hw *hw, 1129 struct i40e_aq_set_phy_config *config, 1130 struct i40e_asq_cmd_details *cmd_details) 1131 { 1132 struct i40e_aq_set_phy_config *cmd; 1133 struct libie_aq_desc desc; 1134 int status; 1135 1136 if (!config) 1137 return -EINVAL; 1138 1139 i40e_fill_default_direct_cmd_desc(&desc, 1140 i40e_aqc_opc_set_phy_config); 1141 1142 cmd = libie_aq_raw(&desc); 1143 *cmd = *config; 1144 1145 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1146 1147 return status; 1148 } 1149 1150 static noinline_for_stack int 1151 i40e_set_fc_status(struct i40e_hw *hw, 1152 struct i40e_aq_get_phy_abilities_resp *abilities, 1153 bool atomic_restart) 1154 { 1155 struct i40e_aq_set_phy_config config; 1156 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1157 u8 pause_mask = 0x0; 1158 1159 switch (fc_mode) { 1160 case I40E_FC_FULL: 1161 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1162 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1163 break; 1164 case I40E_FC_RX_PAUSE: 1165 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1166 break; 1167 case I40E_FC_TX_PAUSE: 1168 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1169 break; 1170 default: 1171 break; 1172 } 1173 1174 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1175 /* clear the old pause settings */ 1176 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1177 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1178 /* set the new abilities */ 1179 config.abilities |= pause_mask; 1180 /* If the abilities have changed, then set the new config */ 1181 if (config.abilities == abilities->abilities) 1182 return 0; 1183 1184 /* Auto restart link so settings take effect */ 1185 if (atomic_restart) 1186 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1187 /* Copy over all the old settings */ 1188 config.phy_type = abilities->phy_type; 1189 config.phy_type_ext = abilities->phy_type_ext; 1190 config.link_speed = abilities->link_speed; 1191 config.eee_capability = abilities->eee_capability; 1192 config.eeer = abilities->eeer_val; 1193 config.low_power_ctrl = abilities->d3_lpan; 1194 config.fec_config = abilities->fec_cfg_curr_mod_ext_info & 1195 I40E_AQ_PHY_FEC_CONFIG_MASK; 1196 1197 return i40e_aq_set_phy_config(hw, &config, NULL); 1198 } 1199 1200 /** 1201 * i40e_set_fc 1202 * @hw: pointer to the hw struct 1203 * @aq_failures: buffer to return AdminQ failure information 1204 * @atomic_restart: whether to enable atomic link restart 1205 * 1206 * Set the requested flow control mode using set_phy_config. 1207 **/ 1208 int i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1209 bool atomic_restart) 1210 { 1211 struct i40e_aq_get_phy_abilities_resp abilities; 1212 int status; 1213 1214 *aq_failures = 0x0; 1215 1216 /* Get the current phy config */ 1217 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1218 NULL); 1219 if (status) { 1220 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1221 return status; 1222 } 1223 1224 status = i40e_set_fc_status(hw, &abilities, atomic_restart); 1225 if (status) 1226 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1227 1228 /* Update the link info */ 1229 status = i40e_update_link_info(hw); 1230 if (status) { 1231 /* Wait a little bit (on 40G cards it sometimes takes a really 1232 * long time for link to come back from the atomic reset) 1233 * and try once more 1234 */ 1235 msleep(1000); 1236 status = i40e_update_link_info(hw); 1237 } 1238 if (status) 1239 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1240 1241 return status; 1242 } 1243 1244 /** 1245 * i40e_aq_clear_pxe_mode 1246 * @hw: pointer to the hw struct 1247 * @cmd_details: pointer to command details structure or NULL 1248 * 1249 * Tell the firmware that the driver is taking over from PXE 1250 **/ 1251 int i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1252 struct i40e_asq_cmd_details *cmd_details) 1253 { 1254 struct i40e_aqc_clear_pxe *cmd; 1255 struct libie_aq_desc desc; 1256 int status; 1257 1258 i40e_fill_default_direct_cmd_desc(&desc, 1259 i40e_aqc_opc_clear_pxe_mode); 1260 1261 cmd = libie_aq_raw(&desc); 1262 cmd->rx_cnt = 0x2; 1263 1264 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1265 1266 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1267 1268 return status; 1269 } 1270 1271 /** 1272 * i40e_aq_set_link_restart_an 1273 * @hw: pointer to the hw struct 1274 * @enable_link: if true: enable link, if false: disable link 1275 * @cmd_details: pointer to command details structure or NULL 1276 * 1277 * Sets up the link and restarts the Auto-Negotiation over the link. 1278 **/ 1279 int i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1280 bool enable_link, 1281 struct i40e_asq_cmd_details *cmd_details) 1282 { 1283 struct i40e_aqc_set_link_restart_an *cmd; 1284 struct libie_aq_desc desc; 1285 int status; 1286 1287 i40e_fill_default_direct_cmd_desc(&desc, 1288 i40e_aqc_opc_set_link_restart_an); 1289 1290 cmd = libie_aq_raw(&desc); 1291 cmd->command = I40E_AQ_PHY_RESTART_AN; 1292 if (enable_link) 1293 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1294 else 1295 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1296 1297 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1298 1299 return status; 1300 } 1301 1302 /** 1303 * i40e_aq_get_link_info 1304 * @hw: pointer to the hw struct 1305 * @enable_lse: enable/disable LinkStatusEvent reporting 1306 * @link: pointer to link status structure - optional 1307 * @cmd_details: pointer to command details structure or NULL 1308 * 1309 * Returns the link status of the adapter. 1310 **/ 1311 int i40e_aq_get_link_info(struct i40e_hw *hw, 1312 bool enable_lse, struct i40e_link_status *link, 1313 struct i40e_asq_cmd_details *cmd_details) 1314 { 1315 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1316 struct i40e_aqc_get_link_status *resp; 1317 struct libie_aq_desc desc; 1318 bool tx_pause, rx_pause; 1319 u16 command_flags; 1320 int status; 1321 1322 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1323 1324 resp = libie_aq_raw(&desc); 1325 if (enable_lse) 1326 command_flags = I40E_AQ_LSE_ENABLE; 1327 else 1328 command_flags = I40E_AQ_LSE_DISABLE; 1329 resp->command_flags = cpu_to_le16(command_flags); 1330 1331 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1332 1333 if (status) 1334 goto aq_get_link_info_exit; 1335 1336 /* save off old link status information */ 1337 hw->phy.link_info_old = *hw_link_info; 1338 1339 /* update link status */ 1340 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1341 hw->phy.media_type = i40e_get_media_type(hw); 1342 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1343 hw_link_info->link_info = resp->link_info; 1344 hw_link_info->an_info = resp->an_info; 1345 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1346 I40E_AQ_CONFIG_FEC_RS_ENA); 1347 hw_link_info->ext_info = resp->ext_info; 1348 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1349 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1350 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1351 1352 /* update fc info */ 1353 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1354 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1355 if (tx_pause & rx_pause) 1356 hw->fc.current_mode = I40E_FC_FULL; 1357 else if (tx_pause) 1358 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1359 else if (rx_pause) 1360 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1361 else 1362 hw->fc.current_mode = I40E_FC_NONE; 1363 1364 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1365 hw_link_info->crc_enable = true; 1366 else 1367 hw_link_info->crc_enable = false; 1368 1369 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1370 hw_link_info->lse_enable = true; 1371 else 1372 hw_link_info->lse_enable = false; 1373 1374 if (hw->mac.type == I40E_MAC_XL710 && i40e_is_fw_ver_lt(hw, 4, 40) && 1375 hw_link_info->phy_type == 0xE) 1376 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1377 1378 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps) && 1379 hw->mac.type != I40E_MAC_X722) { 1380 __le32 tmp; 1381 1382 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1383 hw->phy.phy_types = le32_to_cpu(tmp); 1384 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1385 } 1386 1387 /* save link status information */ 1388 if (link) 1389 *link = *hw_link_info; 1390 1391 /* flag cleared so helper functions don't call AQ again */ 1392 hw->phy.get_link_info = false; 1393 1394 aq_get_link_info_exit: 1395 return status; 1396 } 1397 1398 /** 1399 * i40e_aq_set_phy_int_mask 1400 * @hw: pointer to the hw struct 1401 * @mask: interrupt mask to be set 1402 * @cmd_details: pointer to command details structure or NULL 1403 * 1404 * Set link interrupt mask. 1405 **/ 1406 int i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1407 u16 mask, 1408 struct i40e_asq_cmd_details *cmd_details) 1409 { 1410 struct i40e_aqc_set_phy_int_mask *cmd; 1411 struct libie_aq_desc desc; 1412 int status; 1413 1414 i40e_fill_default_direct_cmd_desc(&desc, 1415 i40e_aqc_opc_set_phy_int_mask); 1416 1417 cmd = libie_aq_raw(&desc); 1418 cmd->event_mask = cpu_to_le16(mask); 1419 1420 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1421 1422 return status; 1423 } 1424 1425 /** 1426 * i40e_aq_set_mac_loopback 1427 * @hw: pointer to the HW struct 1428 * @ena_lpbk: Enable or Disable loopback 1429 * @cmd_details: pointer to command details structure or NULL 1430 * 1431 * Enable/disable loopback on a given port 1432 */ 1433 int i40e_aq_set_mac_loopback(struct i40e_hw *hw, bool ena_lpbk, 1434 struct i40e_asq_cmd_details *cmd_details) 1435 { 1436 struct i40e_aqc_set_lb_mode *cmd; 1437 struct libie_aq_desc desc; 1438 1439 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_lb_modes); 1440 cmd = libie_aq_raw(&desc); 1441 if (ena_lpbk) { 1442 if (hw->nvm.version <= I40E_LEGACY_LOOPBACK_NVM_VER) 1443 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL_LEGACY); 1444 else 1445 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL); 1446 } 1447 1448 return i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1449 } 1450 1451 /** 1452 * i40e_aq_set_phy_debug 1453 * @hw: pointer to the hw struct 1454 * @cmd_flags: debug command flags 1455 * @cmd_details: pointer to command details structure or NULL 1456 * 1457 * Reset the external PHY. 1458 **/ 1459 int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1460 struct i40e_asq_cmd_details *cmd_details) 1461 { 1462 struct i40e_aqc_set_phy_debug *cmd; 1463 struct libie_aq_desc desc; 1464 int status; 1465 1466 i40e_fill_default_direct_cmd_desc(&desc, 1467 i40e_aqc_opc_set_phy_debug); 1468 1469 cmd = libie_aq_raw(&desc); 1470 cmd->command_flags = cmd_flags; 1471 1472 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1473 1474 return status; 1475 } 1476 1477 /** 1478 * i40e_aq_add_vsi 1479 * @hw: pointer to the hw struct 1480 * @vsi_ctx: pointer to a vsi context struct 1481 * @cmd_details: pointer to command details structure or NULL 1482 * 1483 * Add a VSI context to the hardware. 1484 **/ 1485 int i40e_aq_add_vsi(struct i40e_hw *hw, 1486 struct i40e_vsi_context *vsi_ctx, 1487 struct i40e_asq_cmd_details *cmd_details) 1488 { 1489 struct i40e_aqc_add_get_update_vsi_completion *resp; 1490 struct i40e_aqc_add_get_update_vsi *cmd; 1491 struct libie_aq_desc desc; 1492 int status; 1493 1494 i40e_fill_default_direct_cmd_desc(&desc, 1495 i40e_aqc_opc_add_vsi); 1496 1497 resp = libie_aq_raw(&desc); 1498 cmd = libie_aq_raw(&desc); 1499 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1500 cmd->connection_type = vsi_ctx->connection_type; 1501 cmd->vf_id = vsi_ctx->vf_num; 1502 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1503 1504 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 1505 1506 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1507 sizeof(vsi_ctx->info), 1508 cmd_details, true); 1509 1510 if (status) 1511 goto aq_add_vsi_exit; 1512 1513 vsi_ctx->seid = le16_to_cpu(resp->seid); 1514 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1515 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1516 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1517 1518 aq_add_vsi_exit: 1519 return status; 1520 } 1521 1522 /** 1523 * i40e_aq_set_default_vsi 1524 * @hw: pointer to the hw struct 1525 * @seid: vsi number 1526 * @cmd_details: pointer to command details structure or NULL 1527 **/ 1528 int i40e_aq_set_default_vsi(struct i40e_hw *hw, 1529 u16 seid, 1530 struct i40e_asq_cmd_details *cmd_details) 1531 { 1532 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1533 struct libie_aq_desc desc; 1534 int status; 1535 1536 i40e_fill_default_direct_cmd_desc(&desc, 1537 i40e_aqc_opc_set_vsi_promiscuous_modes); 1538 1539 cmd = libie_aq_raw(&desc); 1540 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1541 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1542 cmd->seid = cpu_to_le16(seid); 1543 1544 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1545 1546 return status; 1547 } 1548 1549 /** 1550 * i40e_aq_clear_default_vsi 1551 * @hw: pointer to the hw struct 1552 * @seid: vsi number 1553 * @cmd_details: pointer to command details structure or NULL 1554 **/ 1555 int i40e_aq_clear_default_vsi(struct i40e_hw *hw, 1556 u16 seid, 1557 struct i40e_asq_cmd_details *cmd_details) 1558 { 1559 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1560 struct libie_aq_desc desc; 1561 int status; 1562 1563 i40e_fill_default_direct_cmd_desc(&desc, 1564 i40e_aqc_opc_set_vsi_promiscuous_modes); 1565 1566 cmd = libie_aq_raw(&desc); 1567 cmd->promiscuous_flags = cpu_to_le16(0); 1568 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1569 cmd->seid = cpu_to_le16(seid); 1570 1571 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1572 1573 return status; 1574 } 1575 1576 /** 1577 * i40e_aq_set_vsi_unicast_promiscuous 1578 * @hw: pointer to the hw struct 1579 * @seid: vsi number 1580 * @set: set unicast promiscuous enable/disable 1581 * @cmd_details: pointer to command details structure or NULL 1582 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 1583 **/ 1584 int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1585 u16 seid, bool set, 1586 struct i40e_asq_cmd_details *cmd_details, 1587 bool rx_only_promisc) 1588 { 1589 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1590 struct libie_aq_desc desc; 1591 u16 flags = 0; 1592 int status; 1593 1594 i40e_fill_default_direct_cmd_desc(&desc, 1595 i40e_aqc_opc_set_vsi_promiscuous_modes); 1596 1597 cmd = libie_aq_raw(&desc); 1598 if (set) { 1599 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1600 if (rx_only_promisc && i40e_is_aq_api_ver_ge(hw, 1, 5)) 1601 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1602 } 1603 1604 cmd->promiscuous_flags = cpu_to_le16(flags); 1605 1606 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1607 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1608 cmd->valid_flags |= 1609 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 1610 1611 cmd->seid = cpu_to_le16(seid); 1612 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1613 1614 return status; 1615 } 1616 1617 /** 1618 * i40e_aq_set_vsi_multicast_promiscuous 1619 * @hw: pointer to the hw struct 1620 * @seid: vsi number 1621 * @set: set multicast promiscuous enable/disable 1622 * @cmd_details: pointer to command details structure or NULL 1623 **/ 1624 int i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1625 u16 seid, bool set, 1626 struct i40e_asq_cmd_details *cmd_details) 1627 { 1628 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1629 struct libie_aq_desc desc; 1630 u16 flags = 0; 1631 int status; 1632 1633 i40e_fill_default_direct_cmd_desc(&desc, 1634 i40e_aqc_opc_set_vsi_promiscuous_modes); 1635 1636 cmd = libie_aq_raw(&desc); 1637 if (set) 1638 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1639 1640 cmd->promiscuous_flags = cpu_to_le16(flags); 1641 1642 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1643 1644 cmd->seid = cpu_to_le16(seid); 1645 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1646 1647 return status; 1648 } 1649 1650 /** 1651 * i40e_aq_set_vsi_mc_promisc_on_vlan 1652 * @hw: pointer to the hw struct 1653 * @seid: vsi number 1654 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1655 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 1656 * @cmd_details: pointer to command details structure or NULL 1657 **/ 1658 int i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 1659 u16 seid, bool enable, 1660 u16 vid, 1661 struct i40e_asq_cmd_details *cmd_details) 1662 { 1663 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1664 struct libie_aq_desc desc; 1665 u16 flags = 0; 1666 int status; 1667 1668 i40e_fill_default_direct_cmd_desc(&desc, 1669 i40e_aqc_opc_set_vsi_promiscuous_modes); 1670 1671 cmd = libie_aq_raw(&desc); 1672 if (enable) 1673 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1674 1675 cmd->promiscuous_flags = cpu_to_le16(flags); 1676 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1677 cmd->seid = cpu_to_le16(seid); 1678 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1679 1680 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 1681 cmd_details, true); 1682 1683 return status; 1684 } 1685 1686 /** 1687 * i40e_aq_set_vsi_uc_promisc_on_vlan 1688 * @hw: pointer to the hw struct 1689 * @seid: vsi number 1690 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1691 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 1692 * @cmd_details: pointer to command details structure or NULL 1693 **/ 1694 int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 1695 u16 seid, bool enable, 1696 u16 vid, 1697 struct i40e_asq_cmd_details *cmd_details) 1698 { 1699 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1700 struct libie_aq_desc desc; 1701 u16 flags = 0; 1702 int status; 1703 1704 i40e_fill_default_direct_cmd_desc(&desc, 1705 i40e_aqc_opc_set_vsi_promiscuous_modes); 1706 1707 cmd = libie_aq_raw(&desc); 1708 if (enable) { 1709 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1710 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1711 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1712 } 1713 1714 cmd->promiscuous_flags = cpu_to_le16(flags); 1715 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1716 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1717 cmd->valid_flags |= 1718 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 1719 cmd->seid = cpu_to_le16(seid); 1720 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1721 1722 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 1723 cmd_details, true); 1724 1725 return status; 1726 } 1727 1728 /** 1729 * i40e_aq_set_vsi_bc_promisc_on_vlan 1730 * @hw: pointer to the hw struct 1731 * @seid: vsi number 1732 * @enable: set broadcast promiscuous enable/disable for a given VLAN 1733 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 1734 * @cmd_details: pointer to command details structure or NULL 1735 **/ 1736 int i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 1737 u16 seid, bool enable, u16 vid, 1738 struct i40e_asq_cmd_details *cmd_details) 1739 { 1740 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1741 struct libie_aq_desc desc; 1742 u16 flags = 0; 1743 int status; 1744 1745 i40e_fill_default_direct_cmd_desc(&desc, 1746 i40e_aqc_opc_set_vsi_promiscuous_modes); 1747 1748 if (enable) 1749 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 1750 1751 cmd = libie_aq_raw(&desc); 1752 cmd->promiscuous_flags = cpu_to_le16(flags); 1753 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1754 cmd->seid = cpu_to_le16(seid); 1755 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1756 1757 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1758 1759 return status; 1760 } 1761 1762 /** 1763 * i40e_aq_set_vsi_broadcast 1764 * @hw: pointer to the hw struct 1765 * @seid: vsi number 1766 * @set_filter: true to set filter, false to clear filter 1767 * @cmd_details: pointer to command details structure or NULL 1768 * 1769 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1770 **/ 1771 int i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1772 u16 seid, bool set_filter, 1773 struct i40e_asq_cmd_details *cmd_details) 1774 { 1775 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1776 struct libie_aq_desc desc; 1777 int status; 1778 1779 i40e_fill_default_direct_cmd_desc(&desc, 1780 i40e_aqc_opc_set_vsi_promiscuous_modes); 1781 1782 cmd = libie_aq_raw(&desc); 1783 if (set_filter) 1784 cmd->promiscuous_flags 1785 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1786 else 1787 cmd->promiscuous_flags 1788 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1789 1790 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1791 cmd->seid = cpu_to_le16(seid); 1792 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1793 1794 return status; 1795 } 1796 1797 /** 1798 * i40e_aq_get_vsi_params - get VSI configuration info 1799 * @hw: pointer to the hw struct 1800 * @vsi_ctx: pointer to a vsi context struct 1801 * @cmd_details: pointer to command details structure or NULL 1802 **/ 1803 int i40e_aq_get_vsi_params(struct i40e_hw *hw, 1804 struct i40e_vsi_context *vsi_ctx, 1805 struct i40e_asq_cmd_details *cmd_details) 1806 { 1807 struct i40e_aqc_add_get_update_vsi_completion *resp; 1808 struct i40e_aqc_add_get_update_vsi *cmd; 1809 struct libie_aq_desc desc; 1810 int status; 1811 1812 i40e_fill_default_direct_cmd_desc(&desc, 1813 i40e_aqc_opc_get_vsi_parameters); 1814 1815 resp = libie_aq_raw(&desc); 1816 cmd = libie_aq_raw(&desc); 1817 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1818 1819 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1820 1821 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1822 sizeof(vsi_ctx->info), NULL); 1823 1824 if (status) 1825 goto aq_get_vsi_params_exit; 1826 1827 vsi_ctx->seid = le16_to_cpu(resp->seid); 1828 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1829 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1830 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1831 1832 aq_get_vsi_params_exit: 1833 return status; 1834 } 1835 1836 /** 1837 * i40e_aq_update_vsi_params 1838 * @hw: pointer to the hw struct 1839 * @vsi_ctx: pointer to a vsi context struct 1840 * @cmd_details: pointer to command details structure or NULL 1841 * 1842 * Update a VSI context. 1843 **/ 1844 int i40e_aq_update_vsi_params(struct i40e_hw *hw, 1845 struct i40e_vsi_context *vsi_ctx, 1846 struct i40e_asq_cmd_details *cmd_details) 1847 { 1848 struct i40e_aqc_add_get_update_vsi_completion *resp; 1849 struct i40e_aqc_add_get_update_vsi *cmd; 1850 struct libie_aq_desc desc; 1851 int status; 1852 1853 i40e_fill_default_direct_cmd_desc(&desc, 1854 i40e_aqc_opc_update_vsi_parameters); 1855 resp = libie_aq_raw(&desc); 1856 cmd = libie_aq_raw(&desc); 1857 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1858 1859 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 1860 1861 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1862 sizeof(vsi_ctx->info), 1863 cmd_details, true); 1864 1865 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1866 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1867 1868 return status; 1869 } 1870 1871 /** 1872 * i40e_aq_get_switch_config 1873 * @hw: pointer to the hardware structure 1874 * @buf: pointer to the result buffer 1875 * @buf_size: length of input buffer 1876 * @start_seid: seid to start for the report, 0 == beginning 1877 * @cmd_details: pointer to command details structure or NULL 1878 * 1879 * Fill the buf with switch configuration returned from AdminQ command 1880 **/ 1881 int i40e_aq_get_switch_config(struct i40e_hw *hw, 1882 struct i40e_aqc_get_switch_config_resp *buf, 1883 u16 buf_size, u16 *start_seid, 1884 struct i40e_asq_cmd_details *cmd_details) 1885 { 1886 struct i40e_aqc_switch_seid *scfg; 1887 struct libie_aq_desc desc; 1888 int status; 1889 1890 i40e_fill_default_direct_cmd_desc(&desc, 1891 i40e_aqc_opc_get_switch_config); 1892 scfg = libie_aq_raw(&desc); 1893 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1894 if (buf_size > I40E_AQ_LARGE_BUF) 1895 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 1896 scfg->seid = cpu_to_le16(*start_seid); 1897 1898 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1899 *start_seid = le16_to_cpu(scfg->seid); 1900 1901 return status; 1902 } 1903 1904 /** 1905 * i40e_aq_set_switch_config 1906 * @hw: pointer to the hardware structure 1907 * @flags: bit flag values to set 1908 * @mode: cloud filter mode 1909 * @valid_flags: which bit flags to set 1910 * @mode: cloud filter mode 1911 * @cmd_details: pointer to command details structure or NULL 1912 * 1913 * Set switch configuration bits 1914 **/ 1915 int i40e_aq_set_switch_config(struct i40e_hw *hw, 1916 u16 flags, 1917 u16 valid_flags, u8 mode, 1918 struct i40e_asq_cmd_details *cmd_details) 1919 { 1920 struct i40e_aqc_set_switch_config *scfg; 1921 struct libie_aq_desc desc; 1922 int status; 1923 1924 i40e_fill_default_direct_cmd_desc(&desc, 1925 i40e_aqc_opc_set_switch_config); 1926 scfg = libie_aq_raw(&desc); 1927 scfg->flags = cpu_to_le16(flags); 1928 scfg->valid_flags = cpu_to_le16(valid_flags); 1929 scfg->mode = mode; 1930 if (test_bit(I40E_HW_CAP_802_1AD, hw->caps)) { 1931 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 1932 scfg->first_tag = cpu_to_le16(hw->first_tag); 1933 scfg->second_tag = cpu_to_le16(hw->second_tag); 1934 } 1935 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1936 1937 return status; 1938 } 1939 1940 /** 1941 * i40e_aq_get_firmware_version 1942 * @hw: pointer to the hw struct 1943 * @fw_major_version: firmware major version 1944 * @fw_minor_version: firmware minor version 1945 * @fw_build: firmware build number 1946 * @api_major_version: major queue version 1947 * @api_minor_version: minor queue version 1948 * @cmd_details: pointer to command details structure or NULL 1949 * 1950 * Get the firmware version from the admin queue commands 1951 **/ 1952 int i40e_aq_get_firmware_version(struct i40e_hw *hw, 1953 u16 *fw_major_version, u16 *fw_minor_version, 1954 u32 *fw_build, 1955 u16 *api_major_version, u16 *api_minor_version, 1956 struct i40e_asq_cmd_details *cmd_details) 1957 { 1958 struct i40e_aqc_get_version *resp; 1959 struct libie_aq_desc desc; 1960 int status; 1961 1962 resp = libie_aq_raw(&desc); 1963 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1964 1965 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1966 1967 if (!status) { 1968 if (fw_major_version) 1969 *fw_major_version = le16_to_cpu(resp->fw_major); 1970 if (fw_minor_version) 1971 *fw_minor_version = le16_to_cpu(resp->fw_minor); 1972 if (fw_build) 1973 *fw_build = le32_to_cpu(resp->fw_build); 1974 if (api_major_version) 1975 *api_major_version = le16_to_cpu(resp->api_major); 1976 if (api_minor_version) 1977 *api_minor_version = le16_to_cpu(resp->api_minor); 1978 } 1979 1980 return status; 1981 } 1982 1983 /** 1984 * i40e_aq_send_driver_version 1985 * @hw: pointer to the hw struct 1986 * @dv: driver's major, minor version 1987 * @cmd_details: pointer to command details structure or NULL 1988 * 1989 * Send the driver version to the firmware 1990 **/ 1991 int i40e_aq_send_driver_version(struct i40e_hw *hw, 1992 struct i40e_driver_version *dv, 1993 struct i40e_asq_cmd_details *cmd_details) 1994 { 1995 struct libie_aqc_driver_ver *cmd; 1996 struct libie_aq_desc desc; 1997 int status; 1998 u16 len; 1999 2000 if (dv == NULL) 2001 return -EINVAL; 2002 2003 cmd = libie_aq_raw(&desc); 2004 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2005 2006 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD); 2007 cmd->major_ver = dv->major_version; 2008 cmd->minor_ver = dv->minor_version; 2009 cmd->build_ver = dv->build_version; 2010 cmd->subbuild_ver = dv->subbuild_version; 2011 2012 len = 0; 2013 while (len < sizeof(dv->driver_string) && 2014 (dv->driver_string[len] < 0x80) && 2015 dv->driver_string[len]) 2016 len++; 2017 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2018 len, cmd_details); 2019 2020 return status; 2021 } 2022 2023 /** 2024 * i40e_get_link_status - get status of the HW network link 2025 * @hw: pointer to the hw struct 2026 * @link_up: pointer to bool (true/false = linkup/linkdown) 2027 * 2028 * Variable link_up true if link is up, false if link is down. 2029 * The variable link_up is invalid if returned value of status != 0 2030 * 2031 * Side effect: LinkStatusEvent reporting becomes enabled 2032 **/ 2033 int i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2034 { 2035 int status = 0; 2036 2037 if (hw->phy.get_link_info) { 2038 status = i40e_update_link_info(hw); 2039 2040 if (status) 2041 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2042 status); 2043 } 2044 2045 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2046 2047 return status; 2048 } 2049 2050 /** 2051 * i40e_update_link_info - update status of the HW network link 2052 * @hw: pointer to the hw struct 2053 **/ 2054 noinline_for_stack int i40e_update_link_info(struct i40e_hw *hw) 2055 { 2056 struct i40e_aq_get_phy_abilities_resp abilities; 2057 int status = 0; 2058 2059 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2060 if (status) 2061 return status; 2062 2063 /* extra checking needed to ensure link info to user is timely */ 2064 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2065 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2066 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2067 status = i40e_aq_get_phy_capabilities(hw, false, false, 2068 &abilities, NULL); 2069 if (status) 2070 return status; 2071 2072 if (abilities.fec_cfg_curr_mod_ext_info & 2073 I40E_AQ_ENABLE_FEC_AUTO) 2074 hw->phy.link_info.req_fec_info = 2075 (I40E_AQ_REQUEST_FEC_KR | 2076 I40E_AQ_REQUEST_FEC_RS); 2077 else 2078 hw->phy.link_info.req_fec_info = 2079 abilities.fec_cfg_curr_mod_ext_info & 2080 (I40E_AQ_REQUEST_FEC_KR | 2081 I40E_AQ_REQUEST_FEC_RS); 2082 2083 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2084 sizeof(hw->phy.link_info.module_type)); 2085 } 2086 2087 return status; 2088 } 2089 2090 /** 2091 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2092 * @hw: pointer to the hw struct 2093 * @uplink_seid: the MAC or other gizmo SEID 2094 * @downlink_seid: the VSI SEID 2095 * @enabled_tc: bitmap of TCs to be enabled 2096 * @default_port: true for default port VSI, false for control port 2097 * @veb_seid: pointer to where to put the resulting VEB SEID 2098 * @enable_stats: true to turn on VEB stats 2099 * @cmd_details: pointer to command details structure or NULL 2100 * 2101 * This asks the FW to add a VEB between the uplink and downlink 2102 * elements. If the uplink SEID is 0, this will be a floating VEB. 2103 **/ 2104 int i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2105 u16 downlink_seid, u8 enabled_tc, 2106 bool default_port, u16 *veb_seid, 2107 bool enable_stats, 2108 struct i40e_asq_cmd_details *cmd_details) 2109 { 2110 struct i40e_aqc_add_veb_completion *resp; 2111 struct i40e_aqc_add_veb *cmd; 2112 struct libie_aq_desc desc; 2113 u16 veb_flags = 0; 2114 int status; 2115 2116 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2117 if (!!uplink_seid != !!downlink_seid) 2118 return -EINVAL; 2119 2120 resp = libie_aq_raw(&desc); 2121 cmd = libie_aq_raw(&desc); 2122 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2123 2124 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2125 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2126 cmd->enable_tcs = enabled_tc; 2127 if (!uplink_seid) 2128 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2129 if (default_port) 2130 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2131 else 2132 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2133 2134 /* reverse logic here: set the bitflag to disable the stats */ 2135 if (!enable_stats) 2136 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2137 2138 cmd->veb_flags = cpu_to_le16(veb_flags); 2139 2140 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2141 2142 if (!status && veb_seid) 2143 *veb_seid = le16_to_cpu(resp->veb_seid); 2144 2145 return status; 2146 } 2147 2148 /** 2149 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2150 * @hw: pointer to the hw struct 2151 * @veb_seid: the SEID of the VEB to query 2152 * @switch_id: the uplink switch id 2153 * @floating: set to true if the VEB is floating 2154 * @statistic_index: index of the stats counter block for this VEB 2155 * @vebs_used: number of VEB's used by function 2156 * @vebs_free: total VEB's not reserved by any function 2157 * @cmd_details: pointer to command details structure or NULL 2158 * 2159 * This retrieves the parameters for a particular VEB, specified by 2160 * uplink_seid, and returns them to the caller. 2161 **/ 2162 int i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2163 u16 veb_seid, u16 *switch_id, 2164 bool *floating, u16 *statistic_index, 2165 u16 *vebs_used, u16 *vebs_free, 2166 struct i40e_asq_cmd_details *cmd_details) 2167 { 2168 struct i40e_aqc_get_veb_parameters_completion *cmd_resp; 2169 struct libie_aq_desc desc; 2170 int status; 2171 2172 if (veb_seid == 0) 2173 return -EINVAL; 2174 2175 cmd_resp = libie_aq_raw(&desc); 2176 i40e_fill_default_direct_cmd_desc(&desc, 2177 i40e_aqc_opc_get_veb_parameters); 2178 cmd_resp->seid = cpu_to_le16(veb_seid); 2179 2180 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2181 if (status) 2182 goto get_veb_exit; 2183 2184 if (switch_id) 2185 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2186 if (statistic_index) 2187 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2188 if (vebs_used) 2189 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2190 if (vebs_free) 2191 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2192 if (floating) { 2193 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2194 2195 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2196 *floating = true; 2197 else 2198 *floating = false; 2199 } 2200 2201 get_veb_exit: 2202 return status; 2203 } 2204 2205 /** 2206 * i40e_prepare_add_macvlan 2207 * @mv_list: list of macvlans to be added 2208 * @desc: pointer to AQ descriptor structure 2209 * @count: length of the list 2210 * @seid: VSI for the mac address 2211 * 2212 * Internal helper function that prepares the add macvlan request 2213 * and returns the buffer size. 2214 **/ 2215 static u16 2216 i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list, 2217 struct libie_aq_desc *desc, u16 count, u16 seid) 2218 { 2219 struct i40e_aqc_macvlan *cmd = libie_aq_raw(desc); 2220 u16 buf_size; 2221 int i; 2222 2223 buf_size = count * sizeof(*mv_list); 2224 2225 /* prep the rest of the request */ 2226 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan); 2227 cmd->num_addresses = cpu_to_le16(count); 2228 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2229 cmd->seid[1] = 0; 2230 cmd->seid[2] = 0; 2231 2232 for (i = 0; i < count; i++) 2233 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2234 mv_list[i].flags |= 2235 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2236 2237 desc->flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2238 if (buf_size > I40E_AQ_LARGE_BUF) 2239 desc->flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2240 2241 return buf_size; 2242 } 2243 2244 /** 2245 * i40e_aq_add_macvlan 2246 * @hw: pointer to the hw struct 2247 * @seid: VSI for the mac address 2248 * @mv_list: list of macvlans to be added 2249 * @count: length of the list 2250 * @cmd_details: pointer to command details structure or NULL 2251 * 2252 * Add MAC/VLAN addresses to the HW filtering 2253 **/ 2254 int 2255 i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2256 struct i40e_aqc_add_macvlan_element_data *mv_list, 2257 u16 count, struct i40e_asq_cmd_details *cmd_details) 2258 { 2259 struct libie_aq_desc desc; 2260 u16 buf_size; 2261 2262 if (count == 0 || !mv_list || !hw) 2263 return -EINVAL; 2264 2265 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 2266 2267 return i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2268 cmd_details, true); 2269 } 2270 2271 /** 2272 * i40e_aq_add_macvlan_v2 2273 * @hw: pointer to the hw struct 2274 * @seid: VSI for the mac address 2275 * @mv_list: list of macvlans to be added 2276 * @count: length of the list 2277 * @cmd_details: pointer to command details structure or NULL 2278 * @aq_status: pointer to Admin Queue status return value 2279 * 2280 * Add MAC/VLAN addresses to the HW filtering. 2281 * The _v2 version returns the last Admin Queue status in aq_status 2282 * to avoid race conditions in access to hw->aq.asq_last_status. 2283 * It also calls _v2 versions of asq_send_command functions to 2284 * get the aq_status on the stack. 2285 **/ 2286 int 2287 i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid, 2288 struct i40e_aqc_add_macvlan_element_data *mv_list, 2289 u16 count, struct i40e_asq_cmd_details *cmd_details, 2290 enum libie_aq_err *aq_status) 2291 { 2292 struct libie_aq_desc desc; 2293 u16 buf_size; 2294 2295 if (count == 0 || !mv_list || !hw) 2296 return -EINVAL; 2297 2298 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 2299 2300 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2301 cmd_details, true, aq_status); 2302 } 2303 2304 /** 2305 * i40e_aq_remove_macvlan 2306 * @hw: pointer to the hw struct 2307 * @seid: VSI for the mac address 2308 * @mv_list: list of macvlans to be removed 2309 * @count: length of the list 2310 * @cmd_details: pointer to command details structure or NULL 2311 * 2312 * Remove MAC/VLAN addresses from the HW filtering 2313 **/ 2314 int 2315 i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2316 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2317 u16 count, struct i40e_asq_cmd_details *cmd_details) 2318 { 2319 struct i40e_aqc_macvlan *cmd; 2320 struct libie_aq_desc desc; 2321 u16 buf_size; 2322 int status; 2323 2324 if (count == 0 || !mv_list || !hw) 2325 return -EINVAL; 2326 2327 buf_size = count * sizeof(*mv_list); 2328 2329 /* prep the rest of the request */ 2330 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2331 cmd = libie_aq_raw(&desc); 2332 cmd->num_addresses = cpu_to_le16(count); 2333 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2334 cmd->seid[1] = 0; 2335 cmd->seid[2] = 0; 2336 2337 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2338 if (buf_size > I40E_AQ_LARGE_BUF) 2339 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2340 2341 status = i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2342 cmd_details, true); 2343 2344 return status; 2345 } 2346 2347 /** 2348 * i40e_aq_remove_macvlan_v2 2349 * @hw: pointer to the hw struct 2350 * @seid: VSI for the mac address 2351 * @mv_list: list of macvlans to be removed 2352 * @count: length of the list 2353 * @cmd_details: pointer to command details structure or NULL 2354 * @aq_status: pointer to Admin Queue status return value 2355 * 2356 * Remove MAC/VLAN addresses from the HW filtering. 2357 * The _v2 version returns the last Admin Queue status in aq_status 2358 * to avoid race conditions in access to hw->aq.asq_last_status. 2359 * It also calls _v2 versions of asq_send_command functions to 2360 * get the aq_status on the stack. 2361 **/ 2362 int 2363 i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid, 2364 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2365 u16 count, struct i40e_asq_cmd_details *cmd_details, 2366 enum libie_aq_err *aq_status) 2367 { 2368 struct i40e_aqc_macvlan *cmd; 2369 struct libie_aq_desc desc; 2370 u16 buf_size; 2371 2372 if (count == 0 || !mv_list || !hw) 2373 return -EINVAL; 2374 2375 buf_size = count * sizeof(*mv_list); 2376 2377 /* prep the rest of the request */ 2378 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2379 cmd = libie_aq_raw(&desc); 2380 cmd->num_addresses = cpu_to_le16(count); 2381 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2382 cmd->seid[1] = 0; 2383 cmd->seid[2] = 0; 2384 2385 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2386 if (buf_size > I40E_AQ_LARGE_BUF) 2387 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2388 2389 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2390 cmd_details, true, aq_status); 2391 } 2392 2393 /** 2394 * i40e_aq_send_msg_to_vf 2395 * @hw: pointer to the hardware structure 2396 * @vfid: VF id to send msg 2397 * @v_opcode: opcodes for VF-PF communication 2398 * @v_retval: return error code 2399 * @msg: pointer to the msg buffer 2400 * @msglen: msg length 2401 * @cmd_details: pointer to command details 2402 * 2403 * send msg to vf 2404 **/ 2405 int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2406 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2407 struct i40e_asq_cmd_details *cmd_details) 2408 { 2409 struct i40e_aqc_pf_vf_message *cmd; 2410 struct libie_aq_desc desc; 2411 int status; 2412 2413 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2414 cmd = libie_aq_raw(&desc); 2415 cmd->id = cpu_to_le32(vfid); 2416 desc.cookie_high = cpu_to_le32(v_opcode); 2417 desc.cookie_low = cpu_to_le32(v_retval); 2418 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_SI); 2419 if (msglen) { 2420 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | 2421 LIBIE_AQ_FLAG_RD)); 2422 if (msglen > I40E_AQ_LARGE_BUF) 2423 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2424 desc.datalen = cpu_to_le16(msglen); 2425 } 2426 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2427 2428 return status; 2429 } 2430 2431 /** 2432 * i40e_aq_debug_read_register 2433 * @hw: pointer to the hw struct 2434 * @reg_addr: register address 2435 * @reg_val: register value 2436 * @cmd_details: pointer to command details structure or NULL 2437 * 2438 * Read the register using the admin queue commands 2439 **/ 2440 int i40e_aq_debug_read_register(struct i40e_hw *hw, 2441 u32 reg_addr, u64 *reg_val, 2442 struct i40e_asq_cmd_details *cmd_details) 2443 { 2444 struct i40e_aqc_debug_reg_read_write *cmd_resp; 2445 struct libie_aq_desc desc; 2446 int status; 2447 2448 if (reg_val == NULL) 2449 return -EINVAL; 2450 2451 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2452 2453 cmd_resp = libie_aq_raw(&desc); 2454 cmd_resp->address = cpu_to_le32(reg_addr); 2455 2456 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2457 2458 if (!status) { 2459 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2460 (u64)le32_to_cpu(cmd_resp->value_low); 2461 } 2462 2463 return status; 2464 } 2465 2466 /** 2467 * i40e_aq_debug_write_register 2468 * @hw: pointer to the hw struct 2469 * @reg_addr: register address 2470 * @reg_val: register value 2471 * @cmd_details: pointer to command details structure or NULL 2472 * 2473 * Write to a register using the admin queue commands 2474 **/ 2475 int i40e_aq_debug_write_register(struct i40e_hw *hw, 2476 u32 reg_addr, u64 reg_val, 2477 struct i40e_asq_cmd_details *cmd_details) 2478 { 2479 struct i40e_aqc_debug_reg_read_write *cmd; 2480 struct libie_aq_desc desc; 2481 int status; 2482 2483 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2484 2485 cmd = libie_aq_raw(&desc); 2486 cmd->address = cpu_to_le32(reg_addr); 2487 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2488 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2489 2490 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2491 2492 return status; 2493 } 2494 2495 /** 2496 * i40e_aq_request_resource 2497 * @hw: pointer to the hw struct 2498 * @resource: resource id 2499 * @access: access type 2500 * @sdp_number: resource number 2501 * @timeout: the maximum time in ms that the driver may hold the resource 2502 * @cmd_details: pointer to command details structure or NULL 2503 * 2504 * requests common resource using the admin queue commands 2505 **/ 2506 int i40e_aq_request_resource(struct i40e_hw *hw, 2507 enum i40e_aq_resources_ids resource, 2508 enum i40e_aq_resource_access_type access, 2509 u8 sdp_number, u64 *timeout, 2510 struct i40e_asq_cmd_details *cmd_details) 2511 { 2512 struct libie_aqc_req_res *cmd_resp; 2513 struct libie_aq_desc desc; 2514 int status; 2515 2516 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2517 2518 cmd_resp = libie_aq_raw(&desc); 2519 cmd_resp->res_id = cpu_to_le16(resource); 2520 cmd_resp->access_type = cpu_to_le16(access); 2521 cmd_resp->res_number = cpu_to_le32(sdp_number); 2522 2523 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2524 /* The completion specifies the maximum time in ms that the driver 2525 * may hold the resource in the Timeout field. 2526 * If the resource is held by someone else, the command completes with 2527 * busy return value and the timeout field indicates the maximum time 2528 * the current owner of the resource has to free it. 2529 */ 2530 if (!status || hw->aq.asq_last_status == LIBIE_AQ_RC_EBUSY) 2531 *timeout = le32_to_cpu(cmd_resp->timeout); 2532 2533 return status; 2534 } 2535 2536 /** 2537 * i40e_aq_release_resource 2538 * @hw: pointer to the hw struct 2539 * @resource: resource id 2540 * @sdp_number: resource number 2541 * @cmd_details: pointer to command details structure or NULL 2542 * 2543 * release common resource using the admin queue commands 2544 **/ 2545 int i40e_aq_release_resource(struct i40e_hw *hw, 2546 enum i40e_aq_resources_ids resource, 2547 u8 sdp_number, 2548 struct i40e_asq_cmd_details *cmd_details) 2549 { 2550 struct libie_aqc_req_res *cmd; 2551 struct libie_aq_desc desc; 2552 int status; 2553 2554 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2555 2556 cmd = libie_aq_raw(&desc); 2557 cmd->res_id = cpu_to_le16(resource); 2558 cmd->res_number = cpu_to_le32(sdp_number); 2559 2560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2561 2562 return status; 2563 } 2564 2565 /** 2566 * i40e_aq_read_nvm 2567 * @hw: pointer to the hw struct 2568 * @module_pointer: module pointer location in words from the NVM beginning 2569 * @offset: byte offset from the module beginning 2570 * @length: length of the section to be read (in bytes from the offset) 2571 * @data: command buffer (size [bytes] = length) 2572 * @last_command: tells if this is the last command in a series 2573 * @cmd_details: pointer to command details structure or NULL 2574 * 2575 * Read the NVM using the admin queue commands 2576 **/ 2577 int i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2578 u32 offset, u16 length, void *data, 2579 bool last_command, 2580 struct i40e_asq_cmd_details *cmd_details) 2581 { 2582 struct i40e_aqc_nvm_update *cmd; 2583 struct libie_aq_desc desc; 2584 int status; 2585 2586 /* In offset the highest byte must be zeroed. */ 2587 if (offset & 0xFF000000) { 2588 status = -EINVAL; 2589 goto i40e_aq_read_nvm_exit; 2590 } 2591 2592 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2593 2594 cmd = libie_aq_raw(&desc); 2595 /* If this is the last command in a series, set the proper flag. */ 2596 if (last_command) 2597 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2598 cmd->module_pointer = module_pointer; 2599 cmd->offset = cpu_to_le32(offset); 2600 cmd->length = cpu_to_le16(length); 2601 2602 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2603 if (length > I40E_AQ_LARGE_BUF) 2604 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2605 2606 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2607 2608 i40e_aq_read_nvm_exit: 2609 return status; 2610 } 2611 2612 /** 2613 * i40e_aq_erase_nvm 2614 * @hw: pointer to the hw struct 2615 * @module_pointer: module pointer location in words from the NVM beginning 2616 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2617 * @length: length of the section to be erased (expressed in 4 KB) 2618 * @last_command: tells if this is the last command in a series 2619 * @cmd_details: pointer to command details structure or NULL 2620 * 2621 * Erase the NVM sector using the admin queue commands 2622 **/ 2623 int i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2624 u32 offset, u16 length, bool last_command, 2625 struct i40e_asq_cmd_details *cmd_details) 2626 { 2627 struct i40e_aqc_nvm_update *cmd; 2628 struct libie_aq_desc desc; 2629 int status; 2630 2631 /* In offset the highest byte must be zeroed. */ 2632 if (offset & 0xFF000000) { 2633 status = -EINVAL; 2634 goto i40e_aq_erase_nvm_exit; 2635 } 2636 2637 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2638 2639 cmd = libie_aq_raw(&desc); 2640 /* If this is the last command in a series, set the proper flag. */ 2641 if (last_command) 2642 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2643 cmd->module_pointer = module_pointer; 2644 cmd->offset = cpu_to_le32(offset); 2645 cmd->length = cpu_to_le16(length); 2646 2647 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2648 2649 i40e_aq_erase_nvm_exit: 2650 return status; 2651 } 2652 2653 /** 2654 * i40e_parse_discover_capabilities 2655 * @hw: pointer to the hw struct 2656 * @buff: pointer to a buffer containing device/function capability records 2657 * @cap_count: number of capability records in the list 2658 * @list_type_opc: type of capabilities list to parse 2659 * 2660 * Parse the device/function capabilities list. 2661 **/ 2662 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2663 u32 cap_count, 2664 enum i40e_admin_queue_opc list_type_opc) 2665 { 2666 struct libie_aqc_list_caps_elem *cap; 2667 u32 valid_functions, num_functions; 2668 u32 number, logical_id, phys_id; 2669 struct i40e_hw_capabilities *p; 2670 u16 id, ocp_cfg_word0; 2671 u8 major_rev; 2672 int status; 2673 u32 i = 0; 2674 2675 cap = (struct libie_aqc_list_caps_elem *)buff; 2676 2677 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2678 p = &hw->dev_caps; 2679 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2680 p = &hw->func_caps; 2681 else 2682 return; 2683 2684 for (i = 0; i < cap_count; i++, cap++) { 2685 id = le16_to_cpu(cap->cap); 2686 number = le32_to_cpu(cap->number); 2687 logical_id = le32_to_cpu(cap->logical_id); 2688 phys_id = le32_to_cpu(cap->phys_id); 2689 major_rev = cap->major_ver; 2690 2691 switch (id) { 2692 case LIBIE_AQC_CAPS_SWITCH_MODE: 2693 p->switch_mode = number; 2694 break; 2695 case LIBIE_AQC_CAPS_MNG_MODE: 2696 p->management_mode = number; 2697 if (major_rev > 1) { 2698 p->mng_protocols_over_mctp = logical_id; 2699 i40e_debug(hw, I40E_DEBUG_INIT, 2700 "HW Capability: Protocols over MCTP = %d\n", 2701 p->mng_protocols_over_mctp); 2702 } else { 2703 p->mng_protocols_over_mctp = 0; 2704 } 2705 break; 2706 case LIBIE_AQC_CAPS_NPAR_ACTIVE: 2707 p->npar_enable = number; 2708 break; 2709 case LIBIE_AQC_CAPS_OS2BMC_CAP: 2710 p->os2bmc = number; 2711 break; 2712 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2713 p->valid_functions = number; 2714 break; 2715 case LIBIE_AQC_CAPS_SRIOV: 2716 if (number == 1) 2717 p->sr_iov_1_1 = true; 2718 break; 2719 case LIBIE_AQC_CAPS_VF: 2720 p->num_vfs = number; 2721 p->vf_base_id = logical_id; 2722 break; 2723 case LIBIE_AQC_CAPS_VMDQ: 2724 if (number == 1) 2725 p->vmdq = true; 2726 break; 2727 case LIBIE_AQC_CAPS_8021QBG: 2728 if (number == 1) 2729 p->evb_802_1_qbg = true; 2730 break; 2731 case LIBIE_AQC_CAPS_8021QBR: 2732 if (number == 1) 2733 p->evb_802_1_qbh = true; 2734 break; 2735 case LIBIE_AQC_CAPS_VSI: 2736 p->num_vsis = number; 2737 break; 2738 case LIBIE_AQC_CAPS_DCB: 2739 if (number == 1) { 2740 p->dcb = true; 2741 p->enabled_tcmap = logical_id; 2742 p->maxtc = phys_id; 2743 } 2744 break; 2745 case LIBIE_AQC_CAPS_FCOE: 2746 if (number == 1) 2747 p->fcoe = true; 2748 break; 2749 case LIBIE_AQC_CAPS_ISCSI: 2750 if (number == 1) 2751 p->iscsi = true; 2752 break; 2753 case LIBIE_AQC_CAPS_RSS: 2754 p->rss = true; 2755 p->rss_table_size = number; 2756 p->rss_table_entry_width = logical_id; 2757 break; 2758 case LIBIE_AQC_CAPS_RXQS: 2759 p->num_rx_qp = number; 2760 p->base_queue = phys_id; 2761 break; 2762 case LIBIE_AQC_CAPS_TXQS: 2763 p->num_tx_qp = number; 2764 p->base_queue = phys_id; 2765 break; 2766 case LIBIE_AQC_CAPS_MSIX: 2767 p->num_msix_vectors = number; 2768 i40e_debug(hw, I40E_DEBUG_INIT, 2769 "HW Capability: MSIX vector count = %d\n", 2770 p->num_msix_vectors); 2771 break; 2772 case LIBIE_AQC_CAPS_VF_MSIX: 2773 p->num_msix_vectors_vf = number; 2774 break; 2775 case LIBIE_AQC_CAPS_FLEX10: 2776 if (major_rev == 1) { 2777 if (number == 1) { 2778 p->flex10_enable = true; 2779 p->flex10_capable = true; 2780 } 2781 } else { 2782 /* Capability revision >= 2 */ 2783 if (number & 1) 2784 p->flex10_enable = true; 2785 if (number & 2) 2786 p->flex10_capable = true; 2787 } 2788 p->flex10_mode = logical_id; 2789 p->flex10_status = phys_id; 2790 break; 2791 case LIBIE_AQC_CAPS_CEM: 2792 if (number == 1) 2793 p->mgmt_cem = true; 2794 break; 2795 case LIBIE_AQC_CAPS_RDMA: 2796 if (number == 1) 2797 p->iwarp = true; 2798 break; 2799 case LIBIE_AQC_CAPS_LED: 2800 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2801 p->led[phys_id] = true; 2802 break; 2803 case LIBIE_AQC_CAPS_SDP: 2804 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2805 p->sdp[phys_id] = true; 2806 break; 2807 case LIBIE_AQC_CAPS_MDIO: 2808 if (number == 1) { 2809 p->mdio_port_num = phys_id; 2810 p->mdio_port_mode = logical_id; 2811 } 2812 break; 2813 case LIBIE_AQC_CAPS_1588: 2814 if (number == 1) 2815 p->ieee_1588 = true; 2816 break; 2817 case LIBIE_AQC_CAPS_FD: 2818 p->fd = true; 2819 p->fd_filters_guaranteed = number; 2820 p->fd_filters_best_effort = logical_id; 2821 break; 2822 case LIBIE_AQC_CAPS_WSR_PROT: 2823 p->wr_csr_prot = (u64)number; 2824 p->wr_csr_prot |= (u64)logical_id << 32; 2825 break; 2826 case LIBIE_AQC_CAPS_NVM_MGMT: 2827 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 2828 p->sec_rev_disabled = true; 2829 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 2830 p->update_disabled = true; 2831 break; 2832 default: 2833 break; 2834 } 2835 } 2836 2837 if (p->fcoe) 2838 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 2839 2840 /* Software override ensuring FCoE is disabled if npar or mfp 2841 * mode because it is not supported in these modes. 2842 */ 2843 if (p->npar_enable || p->flex10_enable) 2844 p->fcoe = false; 2845 2846 /* count the enabled ports (aka the "not disabled" ports) */ 2847 hw->num_ports = 0; 2848 for (i = 0; i < 4; i++) { 2849 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 2850 u64 port_cfg = 0; 2851 2852 /* use AQ read to get the physical register offset instead 2853 * of the port relative offset 2854 */ 2855 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 2856 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 2857 hw->num_ports++; 2858 } 2859 2860 /* OCP cards case: if a mezz is removed the Ethernet port is at 2861 * disabled state in PRTGEN_CNF register. Additional NVM read is 2862 * needed in order to check if we are dealing with OCP card. 2863 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 2864 * physical ports results in wrong partition id calculation and thus 2865 * not supporting WoL. 2866 */ 2867 if (hw->mac.type == I40E_MAC_X722) { 2868 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) { 2869 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 2870 2 * I40E_SR_OCP_CFG_WORD0, 2871 sizeof(ocp_cfg_word0), 2872 &ocp_cfg_word0, true, NULL); 2873 if (!status && 2874 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 2875 hw->num_ports = 4; 2876 i40e_release_nvm(hw); 2877 } 2878 } 2879 2880 valid_functions = p->valid_functions; 2881 num_functions = 0; 2882 while (valid_functions) { 2883 if (valid_functions & 1) 2884 num_functions++; 2885 valid_functions >>= 1; 2886 } 2887 2888 /* partition id is 1-based, and functions are evenly spread 2889 * across the ports as partitions 2890 */ 2891 if (hw->num_ports != 0) { 2892 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 2893 hw->num_partitions = num_functions / hw->num_ports; 2894 } 2895 2896 /* additional HW specific goodies that might 2897 * someday be HW version specific 2898 */ 2899 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 2900 } 2901 2902 /** 2903 * i40e_aq_discover_capabilities 2904 * @hw: pointer to the hw struct 2905 * @buff: a virtual buffer to hold the capabilities 2906 * @buff_size: Size of the virtual buffer 2907 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 2908 * @list_type_opc: capabilities type to discover - pass in the command opcode 2909 * @cmd_details: pointer to command details structure or NULL 2910 * 2911 * Get the device capabilities descriptions from the firmware 2912 **/ 2913 int i40e_aq_discover_capabilities(struct i40e_hw *hw, 2914 void *buff, u16 buff_size, u16 *data_size, 2915 enum i40e_admin_queue_opc list_type_opc, 2916 struct i40e_asq_cmd_details *cmd_details) 2917 { 2918 struct libie_aqc_list_caps *cmd; 2919 struct libie_aq_desc desc; 2920 int status = 0; 2921 2922 cmd = libie_aq_raw(&desc); 2923 2924 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 2925 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 2926 status = -EINVAL; 2927 goto exit; 2928 } 2929 2930 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 2931 2932 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2933 if (buff_size > I40E_AQ_LARGE_BUF) 2934 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2935 2936 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2937 *data_size = le16_to_cpu(desc.datalen); 2938 2939 if (status) 2940 goto exit; 2941 2942 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 2943 list_type_opc); 2944 2945 exit: 2946 return status; 2947 } 2948 2949 /** 2950 * i40e_aq_update_nvm 2951 * @hw: pointer to the hw struct 2952 * @module_pointer: module pointer location in words from the NVM beginning 2953 * @offset: byte offset from the module beginning 2954 * @length: length of the section to be written (in bytes from the offset) 2955 * @data: command buffer (size [bytes] = length) 2956 * @last_command: tells if this is the last command in a series 2957 * @preservation_flags: Preservation mode flags 2958 * @cmd_details: pointer to command details structure or NULL 2959 * 2960 * Update the NVM using the admin queue commands 2961 **/ 2962 int i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 2963 u32 offset, u16 length, void *data, 2964 bool last_command, u8 preservation_flags, 2965 struct i40e_asq_cmd_details *cmd_details) 2966 { 2967 struct i40e_aqc_nvm_update *cmd; 2968 struct libie_aq_desc desc; 2969 int status; 2970 2971 /* In offset the highest byte must be zeroed. */ 2972 if (offset & 0xFF000000) { 2973 status = -EINVAL; 2974 goto i40e_aq_update_nvm_exit; 2975 } 2976 2977 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 2978 2979 cmd = libie_aq_raw(&desc); 2980 /* If this is the last command in a series, set the proper flag. */ 2981 if (last_command) 2982 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2983 if (hw->mac.type == I40E_MAC_X722) { 2984 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 2985 cmd->command_flags |= 2986 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 2987 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 2988 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 2989 cmd->command_flags |= 2990 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 2991 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 2992 } 2993 cmd->module_pointer = module_pointer; 2994 cmd->offset = cpu_to_le32(offset); 2995 cmd->length = cpu_to_le16(length); 2996 2997 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2998 if (length > I40E_AQ_LARGE_BUF) 2999 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3000 3001 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3002 3003 i40e_aq_update_nvm_exit: 3004 return status; 3005 } 3006 3007 /** 3008 * i40e_aq_get_lldp_mib 3009 * @hw: pointer to the hw struct 3010 * @bridge_type: type of bridge requested 3011 * @mib_type: Local, Remote or both Local and Remote MIBs 3012 * @buff: pointer to a user supplied buffer to store the MIB block 3013 * @buff_size: size of the buffer (in bytes) 3014 * @local_len : length of the returned Local LLDP MIB 3015 * @remote_len: length of the returned Remote LLDP MIB 3016 * @cmd_details: pointer to command details structure or NULL 3017 * 3018 * Requests the complete LLDP MIB (entire packet). 3019 **/ 3020 int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3021 u8 mib_type, void *buff, u16 buff_size, 3022 u16 *local_len, u16 *remote_len, 3023 struct i40e_asq_cmd_details *cmd_details) 3024 { 3025 struct i40e_aqc_lldp_get_mib *resp; 3026 struct i40e_aqc_lldp_get_mib *cmd; 3027 struct libie_aq_desc desc; 3028 int status; 3029 3030 if (buff_size == 0 || !buff) 3031 return -EINVAL; 3032 3033 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3034 /* Indirect Command */ 3035 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3036 3037 resp = libie_aq_raw(&desc); 3038 cmd = libie_aq_raw(&desc); 3039 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3040 cmd->type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type); 3041 3042 desc.datalen = cpu_to_le16(buff_size); 3043 3044 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3045 if (buff_size > I40E_AQ_LARGE_BUF) 3046 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3047 3048 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3049 if (!status) { 3050 if (local_len != NULL) 3051 *local_len = le16_to_cpu(resp->local_len); 3052 if (remote_len != NULL) 3053 *remote_len = le16_to_cpu(resp->remote_len); 3054 } 3055 3056 return status; 3057 } 3058 3059 /** 3060 * i40e_aq_set_lldp_mib - Set the LLDP MIB 3061 * @hw: pointer to the hw struct 3062 * @mib_type: Local, Remote or both Local and Remote MIBs 3063 * @buff: pointer to a user supplied buffer to store the MIB block 3064 * @buff_size: size of the buffer (in bytes) 3065 * @cmd_details: pointer to command details structure or NULL 3066 * 3067 * Set the LLDP MIB. 3068 **/ 3069 int 3070 i40e_aq_set_lldp_mib(struct i40e_hw *hw, 3071 u8 mib_type, void *buff, u16 buff_size, 3072 struct i40e_asq_cmd_details *cmd_details) 3073 { 3074 struct i40e_aqc_lldp_set_local_mib *cmd; 3075 struct libie_aq_desc desc; 3076 int status; 3077 3078 cmd = libie_aq_raw(&desc); 3079 if (buff_size == 0 || !buff) 3080 return -EINVAL; 3081 3082 i40e_fill_default_direct_cmd_desc(&desc, 3083 i40e_aqc_opc_lldp_set_local_mib); 3084 /* Indirect Command */ 3085 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 3086 if (buff_size > I40E_AQ_LARGE_BUF) 3087 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3088 desc.datalen = cpu_to_le16(buff_size); 3089 3090 cmd->type = mib_type; 3091 cmd->length = cpu_to_le16(buff_size); 3092 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff)); 3093 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff)); 3094 3095 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3096 return status; 3097 } 3098 3099 /** 3100 * i40e_aq_cfg_lldp_mib_change_event 3101 * @hw: pointer to the hw struct 3102 * @enable_update: Enable or Disable event posting 3103 * @cmd_details: pointer to command details structure or NULL 3104 * 3105 * Enable or Disable posting of an event on ARQ when LLDP MIB 3106 * associated with the interface changes 3107 **/ 3108 int i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3109 bool enable_update, 3110 struct i40e_asq_cmd_details *cmd_details) 3111 { 3112 struct i40e_aqc_lldp_update_mib *cmd; 3113 struct libie_aq_desc desc; 3114 int status; 3115 3116 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3117 3118 cmd = libie_aq_raw(&desc); 3119 if (!enable_update) 3120 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3121 3122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3123 3124 return status; 3125 } 3126 3127 /** 3128 * i40e_aq_stop_lldp 3129 * @hw: pointer to the hw struct 3130 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3131 * @persist: True if stop of LLDP should be persistent across power cycles 3132 * @cmd_details: pointer to command details structure or NULL 3133 * 3134 * Stop or Shutdown the embedded LLDP Agent 3135 **/ 3136 int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3137 bool persist, 3138 struct i40e_asq_cmd_details *cmd_details) 3139 { 3140 struct i40e_aqc_lldp_stop *cmd; 3141 struct libie_aq_desc desc; 3142 int status; 3143 3144 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3145 3146 cmd = libie_aq_raw(&desc); 3147 if (shutdown_agent) 3148 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3149 3150 if (persist) { 3151 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) 3152 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST; 3153 else 3154 i40e_debug(hw, I40E_DEBUG_ALL, 3155 "Persistent Stop LLDP not supported by current FW version.\n"); 3156 } 3157 3158 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3159 3160 return status; 3161 } 3162 3163 /** 3164 * i40e_aq_start_lldp 3165 * @hw: pointer to the hw struct 3166 * @persist: True if start of LLDP should be persistent across power cycles 3167 * @cmd_details: pointer to command details structure or NULL 3168 * 3169 * Start the embedded LLDP Agent on all ports. 3170 **/ 3171 int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist, 3172 struct i40e_asq_cmd_details *cmd_details) 3173 { 3174 struct i40e_aqc_lldp_start *cmd; 3175 struct libie_aq_desc desc; 3176 int status; 3177 3178 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3179 3180 cmd = libie_aq_raw(&desc); 3181 cmd->command = I40E_AQ_LLDP_AGENT_START; 3182 3183 if (persist) { 3184 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) 3185 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST; 3186 else 3187 i40e_debug(hw, I40E_DEBUG_ALL, 3188 "Persistent Start LLDP not supported by current FW version.\n"); 3189 } 3190 3191 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3192 3193 return status; 3194 } 3195 3196 /** 3197 * i40e_aq_set_dcb_parameters 3198 * @hw: pointer to the hw struct 3199 * @cmd_details: pointer to command details structure or NULL 3200 * @dcb_enable: True if DCB configuration needs to be applied 3201 * 3202 **/ 3203 int 3204 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 3205 struct i40e_asq_cmd_details *cmd_details) 3206 { 3207 struct i40e_aqc_set_dcb_parameters *cmd; 3208 struct libie_aq_desc desc; 3209 int status; 3210 3211 if (!test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps)) 3212 return -ENODEV; 3213 3214 i40e_fill_default_direct_cmd_desc(&desc, 3215 i40e_aqc_opc_set_dcb_parameters); 3216 3217 cmd = libie_aq_raw(&desc); 3218 if (dcb_enable) { 3219 cmd->valid_flags = I40E_DCB_VALID; 3220 cmd->command = I40E_AQ_DCB_SET_AGENT; 3221 } 3222 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3223 3224 return status; 3225 } 3226 3227 /** 3228 * i40e_aq_get_cee_dcb_config 3229 * @hw: pointer to the hw struct 3230 * @buff: response buffer that stores CEE operational configuration 3231 * @buff_size: size of the buffer passed 3232 * @cmd_details: pointer to command details structure or NULL 3233 * 3234 * Get CEE DCBX mode operational configuration from firmware 3235 **/ 3236 int i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3237 void *buff, u16 buff_size, 3238 struct i40e_asq_cmd_details *cmd_details) 3239 { 3240 struct libie_aq_desc desc; 3241 int status; 3242 3243 if (buff_size == 0 || !buff) 3244 return -EINVAL; 3245 3246 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3247 3248 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3249 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3250 cmd_details); 3251 3252 return status; 3253 } 3254 3255 /** 3256 * i40e_aq_add_udp_tunnel 3257 * @hw: pointer to the hw struct 3258 * @udp_port: the UDP port to add in Host byte order 3259 * @protocol_index: protocol index type 3260 * @filter_index: pointer to filter index 3261 * @cmd_details: pointer to command details structure or NULL 3262 * 3263 * Note: Firmware expects the udp_port value to be in Little Endian format, 3264 * and this function will call cpu_to_le16 to convert from Host byte order to 3265 * Little Endian order. 3266 **/ 3267 int i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3268 u16 udp_port, u8 protocol_index, 3269 u8 *filter_index, 3270 struct i40e_asq_cmd_details *cmd_details) 3271 { 3272 struct i40e_aqc_del_udp_tunnel_completion *resp; 3273 struct i40e_aqc_add_udp_tunnel *cmd; 3274 struct libie_aq_desc desc; 3275 int status; 3276 3277 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3278 3279 resp = libie_aq_raw(&desc); 3280 cmd = libie_aq_raw(&desc); 3281 cmd->udp_port = cpu_to_le16(udp_port); 3282 cmd->protocol_type = protocol_index; 3283 3284 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3285 3286 if (!status && filter_index) 3287 *filter_index = resp->index; 3288 3289 return status; 3290 } 3291 3292 /** 3293 * i40e_aq_del_udp_tunnel 3294 * @hw: pointer to the hw struct 3295 * @index: filter index 3296 * @cmd_details: pointer to command details structure or NULL 3297 **/ 3298 int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3299 struct i40e_asq_cmd_details *cmd_details) 3300 { 3301 struct i40e_aqc_remove_udp_tunnel *cmd; 3302 struct libie_aq_desc desc; 3303 int status; 3304 3305 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3306 3307 cmd = libie_aq_raw(&desc); 3308 cmd->index = index; 3309 3310 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3311 3312 return status; 3313 } 3314 3315 /** 3316 * i40e_aq_delete_element - Delete switch element 3317 * @hw: pointer to the hw struct 3318 * @seid: the SEID to delete from the switch 3319 * @cmd_details: pointer to command details structure or NULL 3320 * 3321 * This deletes a switch element from the switch. 3322 **/ 3323 int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3324 struct i40e_asq_cmd_details *cmd_details) 3325 { 3326 struct i40e_aqc_switch_seid *cmd; 3327 struct libie_aq_desc desc; 3328 int status; 3329 3330 if (seid == 0) 3331 return -EINVAL; 3332 3333 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3334 3335 cmd = libie_aq_raw(&desc); 3336 cmd->seid = cpu_to_le16(seid); 3337 3338 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 3339 cmd_details, true); 3340 3341 return status; 3342 } 3343 3344 /** 3345 * i40e_aq_dcb_updated - DCB Updated Command 3346 * @hw: pointer to the hw struct 3347 * @cmd_details: pointer to command details structure or NULL 3348 * 3349 * EMP will return when the shared RPB settings have been 3350 * recomputed and modified. The retval field in the descriptor 3351 * will be set to 0 when RPB is modified. 3352 **/ 3353 int i40e_aq_dcb_updated(struct i40e_hw *hw, 3354 struct i40e_asq_cmd_details *cmd_details) 3355 { 3356 struct libie_aq_desc desc; 3357 int status; 3358 3359 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3360 3361 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3362 3363 return status; 3364 } 3365 3366 /** 3367 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3368 * @hw: pointer to the hw struct 3369 * @seid: seid for the physical port/switching component/vsi 3370 * @buff: Indirect buffer to hold data parameters and response 3371 * @buff_size: Indirect buffer size 3372 * @opcode: Tx scheduler AQ command opcode 3373 * @cmd_details: pointer to command details structure or NULL 3374 * 3375 * Generic command handler for Tx scheduler AQ commands 3376 **/ 3377 static int i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3378 void *buff, u16 buff_size, 3379 enum i40e_admin_queue_opc opcode, 3380 struct i40e_asq_cmd_details *cmd_details) 3381 { 3382 struct i40e_aqc_tx_sched_ind *cmd; 3383 struct libie_aq_desc desc; 3384 int status; 3385 bool cmd_param_flag = false; 3386 3387 switch (opcode) { 3388 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3389 case i40e_aqc_opc_configure_vsi_tc_bw: 3390 case i40e_aqc_opc_enable_switching_comp_ets: 3391 case i40e_aqc_opc_modify_switching_comp_ets: 3392 case i40e_aqc_opc_disable_switching_comp_ets: 3393 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3394 case i40e_aqc_opc_configure_switching_comp_bw_config: 3395 cmd_param_flag = true; 3396 break; 3397 case i40e_aqc_opc_query_vsi_bw_config: 3398 case i40e_aqc_opc_query_vsi_ets_sla_config: 3399 case i40e_aqc_opc_query_switching_comp_ets_config: 3400 case i40e_aqc_opc_query_port_ets_config: 3401 case i40e_aqc_opc_query_switching_comp_bw_config: 3402 cmd_param_flag = false; 3403 break; 3404 default: 3405 return -EINVAL; 3406 } 3407 3408 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3409 3410 cmd = libie_aq_raw(&desc); 3411 /* Indirect command */ 3412 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3413 if (cmd_param_flag) 3414 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 3415 if (buff_size > I40E_AQ_LARGE_BUF) 3416 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3417 3418 desc.datalen = cpu_to_le16(buff_size); 3419 3420 cmd->vsi_seid = cpu_to_le16(seid); 3421 3422 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3423 3424 return status; 3425 } 3426 3427 /** 3428 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3429 * @hw: pointer to the hw struct 3430 * @seid: VSI seid 3431 * @credit: BW limit credits (0 = disabled) 3432 * @max_credit: Max BW limit credits 3433 * @cmd_details: pointer to command details structure or NULL 3434 **/ 3435 int i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3436 u16 seid, u16 credit, u8 max_credit, 3437 struct i40e_asq_cmd_details *cmd_details) 3438 { 3439 struct i40e_aqc_configure_vsi_bw_limit *cmd; 3440 struct libie_aq_desc desc; 3441 int status; 3442 3443 i40e_fill_default_direct_cmd_desc(&desc, 3444 i40e_aqc_opc_configure_vsi_bw_limit); 3445 3446 cmd = libie_aq_raw(&desc); 3447 cmd->vsi_seid = cpu_to_le16(seid); 3448 cmd->credit = cpu_to_le16(credit); 3449 cmd->max_credit = max_credit; 3450 3451 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3452 3453 return status; 3454 } 3455 3456 /** 3457 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3458 * @hw: pointer to the hw struct 3459 * @seid: VSI seid 3460 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3461 * @cmd_details: pointer to command details structure or NULL 3462 **/ 3463 int i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3464 u16 seid, 3465 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3466 struct i40e_asq_cmd_details *cmd_details) 3467 { 3468 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3469 i40e_aqc_opc_configure_vsi_tc_bw, 3470 cmd_details); 3471 } 3472 3473 /** 3474 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3475 * @hw: pointer to the hw struct 3476 * @seid: seid of the switching component connected to Physical Port 3477 * @ets_data: Buffer holding ETS parameters 3478 * @opcode: Tx scheduler AQ command opcode 3479 * @cmd_details: pointer to command details structure or NULL 3480 **/ 3481 int 3482 i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3483 u16 seid, 3484 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3485 enum i40e_admin_queue_opc opcode, 3486 struct i40e_asq_cmd_details *cmd_details) 3487 { 3488 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3489 sizeof(*ets_data), opcode, cmd_details); 3490 } 3491 3492 /** 3493 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3494 * @hw: pointer to the hw struct 3495 * @seid: seid of the switching component 3496 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3497 * @cmd_details: pointer to command details structure or NULL 3498 **/ 3499 int 3500 i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3501 u16 seid, 3502 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3503 struct i40e_asq_cmd_details *cmd_details) 3504 { 3505 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3506 i40e_aqc_opc_configure_switching_comp_bw_config, 3507 cmd_details); 3508 } 3509 3510 /** 3511 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3512 * @hw: pointer to the hw struct 3513 * @seid: seid of the VSI 3514 * @bw_data: Buffer to hold VSI BW configuration 3515 * @cmd_details: pointer to command details structure or NULL 3516 **/ 3517 int 3518 i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3519 u16 seid, 3520 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3521 struct i40e_asq_cmd_details *cmd_details) 3522 { 3523 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3524 i40e_aqc_opc_query_vsi_bw_config, 3525 cmd_details); 3526 } 3527 3528 /** 3529 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3530 * @hw: pointer to the hw struct 3531 * @seid: seid of the VSI 3532 * @bw_data: Buffer to hold VSI BW configuration per TC 3533 * @cmd_details: pointer to command details structure or NULL 3534 **/ 3535 int 3536 i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3537 u16 seid, 3538 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3539 struct i40e_asq_cmd_details *cmd_details) 3540 { 3541 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3542 i40e_aqc_opc_query_vsi_ets_sla_config, 3543 cmd_details); 3544 } 3545 3546 /** 3547 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3548 * @hw: pointer to the hw struct 3549 * @seid: seid of the switching component 3550 * @bw_data: Buffer to hold switching component's per TC BW config 3551 * @cmd_details: pointer to command details structure or NULL 3552 **/ 3553 int 3554 i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3555 u16 seid, 3556 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3557 struct i40e_asq_cmd_details *cmd_details) 3558 { 3559 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3560 i40e_aqc_opc_query_switching_comp_ets_config, 3561 cmd_details); 3562 } 3563 3564 /** 3565 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3566 * @hw: pointer to the hw struct 3567 * @seid: seid of the VSI or switching component connected to Physical Port 3568 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3569 * @cmd_details: pointer to command details structure or NULL 3570 **/ 3571 int 3572 i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3573 u16 seid, 3574 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3575 struct i40e_asq_cmd_details *cmd_details) 3576 { 3577 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3578 i40e_aqc_opc_query_port_ets_config, 3579 cmd_details); 3580 } 3581 3582 /** 3583 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3584 * @hw: pointer to the hw struct 3585 * @seid: seid of the switching component 3586 * @bw_data: Buffer to hold switching component's BW configuration 3587 * @cmd_details: pointer to command details structure or NULL 3588 **/ 3589 int 3590 i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3591 u16 seid, 3592 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3593 struct i40e_asq_cmd_details *cmd_details) 3594 { 3595 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3596 i40e_aqc_opc_query_switching_comp_bw_config, 3597 cmd_details); 3598 } 3599 3600 /** 3601 * i40e_validate_filter_settings 3602 * @hw: pointer to the hardware structure 3603 * @settings: Filter control settings 3604 * 3605 * Check and validate the filter control settings passed. 3606 * The function checks for the valid filter/context sizes being 3607 * passed for FCoE and PE. 3608 * 3609 * Returns 0 if the values passed are valid and within 3610 * range else returns an error. 3611 **/ 3612 static int 3613 i40e_validate_filter_settings(struct i40e_hw *hw, 3614 struct i40e_filter_control_settings *settings) 3615 { 3616 u32 fcoe_cntx_size, fcoe_filt_size; 3617 u32 fcoe_fmax; 3618 u32 val; 3619 3620 /* Validate FCoE settings passed */ 3621 switch (settings->fcoe_filt_num) { 3622 case I40E_HASH_FILTER_SIZE_1K: 3623 case I40E_HASH_FILTER_SIZE_2K: 3624 case I40E_HASH_FILTER_SIZE_4K: 3625 case I40E_HASH_FILTER_SIZE_8K: 3626 case I40E_HASH_FILTER_SIZE_16K: 3627 case I40E_HASH_FILTER_SIZE_32K: 3628 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3629 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3630 break; 3631 default: 3632 return -EINVAL; 3633 } 3634 3635 switch (settings->fcoe_cntx_num) { 3636 case I40E_DMA_CNTX_SIZE_512: 3637 case I40E_DMA_CNTX_SIZE_1K: 3638 case I40E_DMA_CNTX_SIZE_2K: 3639 case I40E_DMA_CNTX_SIZE_4K: 3640 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3641 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3642 break; 3643 default: 3644 return -EINVAL; 3645 } 3646 3647 /* Validate PE settings passed */ 3648 switch (settings->pe_filt_num) { 3649 case I40E_HASH_FILTER_SIZE_1K: 3650 case I40E_HASH_FILTER_SIZE_2K: 3651 case I40E_HASH_FILTER_SIZE_4K: 3652 case I40E_HASH_FILTER_SIZE_8K: 3653 case I40E_HASH_FILTER_SIZE_16K: 3654 case I40E_HASH_FILTER_SIZE_32K: 3655 case I40E_HASH_FILTER_SIZE_64K: 3656 case I40E_HASH_FILTER_SIZE_128K: 3657 case I40E_HASH_FILTER_SIZE_256K: 3658 case I40E_HASH_FILTER_SIZE_512K: 3659 case I40E_HASH_FILTER_SIZE_1M: 3660 break; 3661 default: 3662 return -EINVAL; 3663 } 3664 3665 switch (settings->pe_cntx_num) { 3666 case I40E_DMA_CNTX_SIZE_512: 3667 case I40E_DMA_CNTX_SIZE_1K: 3668 case I40E_DMA_CNTX_SIZE_2K: 3669 case I40E_DMA_CNTX_SIZE_4K: 3670 case I40E_DMA_CNTX_SIZE_8K: 3671 case I40E_DMA_CNTX_SIZE_16K: 3672 case I40E_DMA_CNTX_SIZE_32K: 3673 case I40E_DMA_CNTX_SIZE_64K: 3674 case I40E_DMA_CNTX_SIZE_128K: 3675 case I40E_DMA_CNTX_SIZE_256K: 3676 break; 3677 default: 3678 return -EINVAL; 3679 } 3680 3681 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3682 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3683 fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val); 3684 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3685 return -EINVAL; 3686 3687 return 0; 3688 } 3689 3690 /** 3691 * i40e_set_filter_control 3692 * @hw: pointer to the hardware structure 3693 * @settings: Filter control settings 3694 * 3695 * Set the Queue Filters for PE/FCoE and enable filters required 3696 * for a single PF. It is expected that these settings are programmed 3697 * at the driver initialization time. 3698 **/ 3699 int i40e_set_filter_control(struct i40e_hw *hw, 3700 struct i40e_filter_control_settings *settings) 3701 { 3702 u32 hash_lut_size = 0; 3703 int ret = 0; 3704 u32 val; 3705 3706 if (!settings) 3707 return -EINVAL; 3708 3709 /* Validate the input settings */ 3710 ret = i40e_validate_filter_settings(hw, settings); 3711 if (ret) 3712 return ret; 3713 3714 /* Read the PF Queue Filter control register */ 3715 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 3716 3717 /* Program required PE hash buckets for the PF */ 3718 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 3719 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEHSIZE_MASK, settings->pe_filt_num); 3720 /* Program required PE contexts for the PF */ 3721 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 3722 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEDSIZE_MASK, settings->pe_cntx_num); 3723 3724 /* Program required FCoE hash buckets for the PF */ 3725 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3726 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCHSIZE_MASK, 3727 settings->fcoe_filt_num); 3728 /* Program required FCoE DDP contexts for the PF */ 3729 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3730 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCDSIZE_MASK, 3731 settings->fcoe_cntx_num); 3732 3733 /* Program Hash LUT size for the PF */ 3734 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3735 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 3736 hash_lut_size = 1; 3737 val |= FIELD_PREP(I40E_PFQF_CTL_0_HASHLUTSIZE_MASK, hash_lut_size); 3738 3739 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 3740 if (settings->enable_fdir) 3741 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 3742 if (settings->enable_ethtype) 3743 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 3744 if (settings->enable_macvlan) 3745 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 3746 3747 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 3748 3749 return 0; 3750 } 3751 3752 /** 3753 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 3754 * @hw: pointer to the hw struct 3755 * @mac_addr: MAC address to use in the filter 3756 * @ethtype: Ethertype to use in the filter 3757 * @flags: Flags that needs to be applied to the filter 3758 * @vsi_seid: seid of the control VSI 3759 * @queue: VSI queue number to send the packet to 3760 * @is_add: Add control packet filter if True else remove 3761 * @stats: Structure to hold information on control filter counts 3762 * @cmd_details: pointer to command details structure or NULL 3763 * 3764 * This command will Add or Remove control packet filter for a control VSI. 3765 * In return it will update the total number of perfect filter count in 3766 * the stats member. 3767 **/ 3768 int i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 3769 u8 *mac_addr, u16 ethtype, u16 flags, 3770 u16 vsi_seid, u16 queue, bool is_add, 3771 struct i40e_control_filter_stats *stats, 3772 struct i40e_asq_cmd_details *cmd_details) 3773 { 3774 struct i40e_aqc_add_remove_control_packet_filter_completion *resp; 3775 struct i40e_aqc_add_remove_control_packet_filter *cmd; 3776 struct libie_aq_desc desc; 3777 int status; 3778 3779 if (vsi_seid == 0) 3780 return -EINVAL; 3781 3782 resp = libie_aq_raw(&desc); 3783 cmd = libie_aq_raw(&desc); 3784 if (is_add) { 3785 i40e_fill_default_direct_cmd_desc(&desc, 3786 i40e_aqc_opc_add_control_packet_filter); 3787 cmd->queue = cpu_to_le16(queue); 3788 } else { 3789 i40e_fill_default_direct_cmd_desc(&desc, 3790 i40e_aqc_opc_remove_control_packet_filter); 3791 } 3792 3793 if (mac_addr) 3794 ether_addr_copy(cmd->mac, mac_addr); 3795 3796 cmd->etype = cpu_to_le16(ethtype); 3797 cmd->flags = cpu_to_le16(flags); 3798 cmd->seid = cpu_to_le16(vsi_seid); 3799 3800 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3801 3802 if (!status && stats) { 3803 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 3804 stats->etype_used = le16_to_cpu(resp->etype_used); 3805 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 3806 stats->etype_free = le16_to_cpu(resp->etype_free); 3807 } 3808 3809 return status; 3810 } 3811 3812 /** 3813 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 3814 * @hw: pointer to the hw struct 3815 * @seid: VSI seid to add ethertype filter from 3816 **/ 3817 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 3818 u16 seid) 3819 { 3820 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 3821 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 3822 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 3823 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 3824 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 3825 int status; 3826 3827 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 3828 seid, 0, true, NULL, 3829 NULL); 3830 if (status) 3831 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 3832 } 3833 3834 /** 3835 * i40e_aq_alternate_read 3836 * @hw: pointer to the hardware structure 3837 * @reg_addr0: address of first dword to be read 3838 * @reg_val0: pointer for data read from 'reg_addr0' 3839 * @reg_addr1: address of second dword to be read 3840 * @reg_val1: pointer for data read from 'reg_addr1' 3841 * 3842 * Read one or two dwords from alternate structure. Fields are indicated 3843 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 3844 * is not passed then only register at 'reg_addr0' is read. 3845 * 3846 **/ 3847 static int i40e_aq_alternate_read(struct i40e_hw *hw, 3848 u32 reg_addr0, u32 *reg_val0, 3849 u32 reg_addr1, u32 *reg_val1) 3850 { 3851 struct i40e_aqc_alternate_write *cmd_resp; 3852 struct libie_aq_desc desc; 3853 int status; 3854 3855 if (!reg_val0) 3856 return -EINVAL; 3857 3858 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 3859 cmd_resp = libie_aq_raw(&desc); 3860 cmd_resp->address0 = cpu_to_le32(reg_addr0); 3861 cmd_resp->address1 = cpu_to_le32(reg_addr1); 3862 3863 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3864 3865 if (!status) { 3866 *reg_val0 = le32_to_cpu(cmd_resp->data0); 3867 3868 if (reg_val1) 3869 *reg_val1 = le32_to_cpu(cmd_resp->data1); 3870 } 3871 3872 return status; 3873 } 3874 3875 /** 3876 * i40e_aq_suspend_port_tx 3877 * @hw: pointer to the hardware structure 3878 * @seid: port seid 3879 * @cmd_details: pointer to command details structure or NULL 3880 * 3881 * Suspend port's Tx traffic 3882 **/ 3883 int i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, 3884 struct i40e_asq_cmd_details *cmd_details) 3885 { 3886 struct i40e_aqc_tx_sched_ind *cmd; 3887 struct libie_aq_desc desc; 3888 int status; 3889 3890 cmd = libie_aq_raw(&desc); 3891 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx); 3892 cmd->vsi_seid = cpu_to_le16(seid); 3893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3894 3895 return status; 3896 } 3897 3898 /** 3899 * i40e_aq_resume_port_tx 3900 * @hw: pointer to the hardware structure 3901 * @cmd_details: pointer to command details structure or NULL 3902 * 3903 * Resume port's Tx traffic 3904 **/ 3905 int i40e_aq_resume_port_tx(struct i40e_hw *hw, 3906 struct i40e_asq_cmd_details *cmd_details) 3907 { 3908 struct libie_aq_desc desc; 3909 int status; 3910 3911 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 3912 3913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3914 3915 return status; 3916 } 3917 3918 /** 3919 * i40e_set_pci_config_data - store PCI bus info 3920 * @hw: pointer to hardware structure 3921 * @link_status: the link status word from PCI config space 3922 * 3923 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 3924 **/ 3925 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 3926 { 3927 hw->bus.type = i40e_bus_type_pci_express; 3928 3929 switch (link_status & PCI_EXP_LNKSTA_NLW) { 3930 case PCI_EXP_LNKSTA_NLW_X1: 3931 hw->bus.width = i40e_bus_width_pcie_x1; 3932 break; 3933 case PCI_EXP_LNKSTA_NLW_X2: 3934 hw->bus.width = i40e_bus_width_pcie_x2; 3935 break; 3936 case PCI_EXP_LNKSTA_NLW_X4: 3937 hw->bus.width = i40e_bus_width_pcie_x4; 3938 break; 3939 case PCI_EXP_LNKSTA_NLW_X8: 3940 hw->bus.width = i40e_bus_width_pcie_x8; 3941 break; 3942 default: 3943 hw->bus.width = i40e_bus_width_unknown; 3944 break; 3945 } 3946 3947 switch (link_status & PCI_EXP_LNKSTA_CLS) { 3948 case PCI_EXP_LNKSTA_CLS_2_5GB: 3949 hw->bus.speed = i40e_bus_speed_2500; 3950 break; 3951 case PCI_EXP_LNKSTA_CLS_5_0GB: 3952 hw->bus.speed = i40e_bus_speed_5000; 3953 break; 3954 case PCI_EXP_LNKSTA_CLS_8_0GB: 3955 hw->bus.speed = i40e_bus_speed_8000; 3956 break; 3957 default: 3958 hw->bus.speed = i40e_bus_speed_unknown; 3959 break; 3960 } 3961 } 3962 3963 /** 3964 * i40e_aq_debug_dump 3965 * @hw: pointer to the hardware structure 3966 * @cluster_id: specific cluster to dump 3967 * @table_id: table id within cluster 3968 * @start_index: index of line in the block to read 3969 * @buff_size: dump buffer size 3970 * @buff: dump buffer 3971 * @ret_buff_size: actual buffer size returned 3972 * @ret_next_table: next block to read 3973 * @ret_next_index: next index to read 3974 * @cmd_details: pointer to command details structure or NULL 3975 * 3976 * Dump internal FW/HW data for debug purposes. 3977 * 3978 **/ 3979 int i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 3980 u8 table_id, u32 start_index, u16 buff_size, 3981 void *buff, u16 *ret_buff_size, 3982 u8 *ret_next_table, u32 *ret_next_index, 3983 struct i40e_asq_cmd_details *cmd_details) 3984 { 3985 struct i40e_aqc_debug_dump_internals *resp; 3986 struct i40e_aqc_debug_dump_internals *cmd; 3987 struct libie_aq_desc desc; 3988 int status; 3989 3990 if (buff_size == 0 || !buff) 3991 return -EINVAL; 3992 3993 i40e_fill_default_direct_cmd_desc(&desc, 3994 i40e_aqc_opc_debug_dump_internals); 3995 resp = libie_aq_raw(&desc); 3996 cmd = libie_aq_raw(&desc); 3997 /* Indirect Command */ 3998 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3999 if (buff_size > I40E_AQ_LARGE_BUF) 4000 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4001 4002 cmd->cluster_id = cluster_id; 4003 cmd->table_id = table_id; 4004 cmd->idx = cpu_to_le32(start_index); 4005 4006 desc.datalen = cpu_to_le16(buff_size); 4007 4008 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4009 if (!status) { 4010 if (ret_buff_size) 4011 *ret_buff_size = le16_to_cpu(desc.datalen); 4012 if (ret_next_table) 4013 *ret_next_table = resp->table_id; 4014 if (ret_next_index) 4015 *ret_next_index = le32_to_cpu(resp->idx); 4016 } 4017 4018 return status; 4019 } 4020 4021 /** 4022 * i40e_read_bw_from_alt_ram 4023 * @hw: pointer to the hardware structure 4024 * @max_bw: pointer for max_bw read 4025 * @min_bw: pointer for min_bw read 4026 * @min_valid: pointer for bool that is true if min_bw is a valid value 4027 * @max_valid: pointer for bool that is true if max_bw is a valid value 4028 * 4029 * Read bw from the alternate ram for the given pf 4030 **/ 4031 int i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4032 u32 *max_bw, u32 *min_bw, 4033 bool *min_valid, bool *max_valid) 4034 { 4035 u32 max_bw_addr, min_bw_addr; 4036 int status; 4037 4038 /* Calculate the address of the min/max bw registers */ 4039 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4040 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4041 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4042 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4043 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4044 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4045 4046 /* Read the bandwidths from alt ram */ 4047 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4048 min_bw_addr, min_bw); 4049 4050 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4051 *min_valid = true; 4052 else 4053 *min_valid = false; 4054 4055 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4056 *max_valid = true; 4057 else 4058 *max_valid = false; 4059 4060 return status; 4061 } 4062 4063 /** 4064 * i40e_aq_configure_partition_bw 4065 * @hw: pointer to the hardware structure 4066 * @bw_data: Buffer holding valid pfs and bw limits 4067 * @cmd_details: pointer to command details 4068 * 4069 * Configure partitions guaranteed/max bw 4070 **/ 4071 int 4072 i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4073 struct i40e_aqc_configure_partition_bw_data *bw_data, 4074 struct i40e_asq_cmd_details *cmd_details) 4075 { 4076 u16 bwd_size = sizeof(*bw_data); 4077 struct libie_aq_desc desc; 4078 int status; 4079 4080 i40e_fill_default_direct_cmd_desc(&desc, 4081 i40e_aqc_opc_configure_partition_bw); 4082 4083 /* Indirect command */ 4084 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 4085 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 4086 4087 if (bwd_size > I40E_AQ_LARGE_BUF) 4088 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4089 4090 desc.datalen = cpu_to_le16(bwd_size); 4091 4092 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4093 cmd_details); 4094 4095 return status; 4096 } 4097 4098 /** 4099 * i40e_read_phy_register_clause22 4100 * @hw: pointer to the HW structure 4101 * @reg: register address in the page 4102 * @phy_addr: PHY address on MDIO interface 4103 * @value: PHY register value 4104 * 4105 * Reads specified PHY register value 4106 **/ 4107 int i40e_read_phy_register_clause22(struct i40e_hw *hw, 4108 u16 reg, u8 phy_addr, u16 *value) 4109 { 4110 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4111 int status = -EIO; 4112 u32 command = 0; 4113 u16 retry = 1000; 4114 4115 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4116 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4117 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4118 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4119 (I40E_GLGEN_MSCA_MDICMD_MASK); 4120 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4121 do { 4122 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4123 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4124 status = 0; 4125 break; 4126 } 4127 udelay(10); 4128 retry--; 4129 } while (retry); 4130 4131 if (status) { 4132 i40e_debug(hw, I40E_DEBUG_PHY, 4133 "PHY: Can't write command to external PHY.\n"); 4134 } else { 4135 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4136 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4137 } 4138 4139 return status; 4140 } 4141 4142 /** 4143 * i40e_write_phy_register_clause22 4144 * @hw: pointer to the HW structure 4145 * @reg: register address in the page 4146 * @phy_addr: PHY address on MDIO interface 4147 * @value: PHY register value 4148 * 4149 * Writes specified PHY register value 4150 **/ 4151 int i40e_write_phy_register_clause22(struct i40e_hw *hw, 4152 u16 reg, u8 phy_addr, u16 value) 4153 { 4154 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4155 int status = -EIO; 4156 u32 command = 0; 4157 u16 retry = 1000; 4158 4159 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4160 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4161 4162 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4163 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4164 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4165 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4166 (I40E_GLGEN_MSCA_MDICMD_MASK); 4167 4168 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4169 do { 4170 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4171 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4172 status = 0; 4173 break; 4174 } 4175 udelay(10); 4176 retry--; 4177 } while (retry); 4178 4179 return status; 4180 } 4181 4182 /** 4183 * i40e_read_phy_register_clause45 4184 * @hw: pointer to the HW structure 4185 * @page: registers page number 4186 * @reg: register address in the page 4187 * @phy_addr: PHY address on MDIO interface 4188 * @value: PHY register value 4189 * 4190 * Reads specified PHY register value 4191 **/ 4192 int i40e_read_phy_register_clause45(struct i40e_hw *hw, 4193 u8 page, u16 reg, u8 phy_addr, u16 *value) 4194 { 4195 u8 port_num = hw->func_caps.mdio_port_num; 4196 int status = -EIO; 4197 u32 command = 0; 4198 u16 retry = 1000; 4199 4200 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4201 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4202 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4203 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4204 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4205 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4206 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4207 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4208 do { 4209 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4210 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4211 status = 0; 4212 break; 4213 } 4214 usleep_range(10, 20); 4215 retry--; 4216 } while (retry); 4217 4218 if (status) { 4219 i40e_debug(hw, I40E_DEBUG_PHY, 4220 "PHY: Can't write command to external PHY.\n"); 4221 goto phy_read_end; 4222 } 4223 4224 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4225 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4226 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4227 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4228 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4229 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4230 status = -EIO; 4231 retry = 1000; 4232 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4233 do { 4234 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4235 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4236 status = 0; 4237 break; 4238 } 4239 usleep_range(10, 20); 4240 retry--; 4241 } while (retry); 4242 4243 if (!status) { 4244 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4245 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4246 } else { 4247 i40e_debug(hw, I40E_DEBUG_PHY, 4248 "PHY: Can't read register value from external PHY.\n"); 4249 } 4250 4251 phy_read_end: 4252 return status; 4253 } 4254 4255 /** 4256 * i40e_write_phy_register_clause45 4257 * @hw: pointer to the HW structure 4258 * @page: registers page number 4259 * @reg: register address in the page 4260 * @phy_addr: PHY address on MDIO interface 4261 * @value: PHY register value 4262 * 4263 * Writes value to specified PHY register 4264 **/ 4265 int i40e_write_phy_register_clause45(struct i40e_hw *hw, 4266 u8 page, u16 reg, u8 phy_addr, u16 value) 4267 { 4268 u8 port_num = hw->func_caps.mdio_port_num; 4269 int status = -EIO; 4270 u16 retry = 1000; 4271 u32 command = 0; 4272 4273 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4274 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4275 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4276 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4277 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4278 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4279 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4280 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4281 do { 4282 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4283 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4284 status = 0; 4285 break; 4286 } 4287 usleep_range(10, 20); 4288 retry--; 4289 } while (retry); 4290 if (status) { 4291 i40e_debug(hw, I40E_DEBUG_PHY, 4292 "PHY: Can't write command to external PHY.\n"); 4293 goto phy_write_end; 4294 } 4295 4296 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4297 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4298 4299 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4300 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4301 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4302 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4303 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4304 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4305 status = -EIO; 4306 retry = 1000; 4307 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4308 do { 4309 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4310 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4311 status = 0; 4312 break; 4313 } 4314 usleep_range(10, 20); 4315 retry--; 4316 } while (retry); 4317 4318 phy_write_end: 4319 return status; 4320 } 4321 4322 /** 4323 * i40e_get_phy_address 4324 * @hw: pointer to the HW structure 4325 * @dev_num: PHY port num that address we want 4326 * 4327 * Gets PHY address for current port 4328 **/ 4329 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4330 { 4331 u8 port_num = hw->func_caps.mdio_port_num; 4332 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4333 4334 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4335 } 4336 4337 /** 4338 * i40e_led_get_reg - read LED register 4339 * @hw: pointer to the HW structure 4340 * @led_addr: LED register address 4341 * @reg_val: read register value 4342 **/ 4343 static int i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 4344 u32 *reg_val) 4345 { 4346 u8 phy_addr = 0; 4347 u8 port_num; 4348 int status; 4349 u32 i; 4350 4351 *reg_val = 0; 4352 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4353 status = 4354 i40e_aq_get_phy_register(hw, 4355 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4356 I40E_PHY_COM_REG_PAGE, true, 4357 I40E_PHY_LED_PROV_REG_1, 4358 reg_val, NULL); 4359 } else { 4360 i = rd32(hw, I40E_PFGEN_PORTNUM); 4361 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4362 phy_addr = i40e_get_phy_address(hw, port_num); 4363 status = i40e_read_phy_register_clause45(hw, 4364 I40E_PHY_COM_REG_PAGE, 4365 led_addr, phy_addr, 4366 (u16 *)reg_val); 4367 } 4368 return status; 4369 } 4370 4371 /** 4372 * i40e_led_set_reg - write LED register 4373 * @hw: pointer to the HW structure 4374 * @led_addr: LED register address 4375 * @reg_val: register value to write 4376 **/ 4377 static int i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 4378 u32 reg_val) 4379 { 4380 u8 phy_addr = 0; 4381 u8 port_num; 4382 int status; 4383 u32 i; 4384 4385 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4386 status = 4387 i40e_aq_set_phy_register(hw, 4388 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4389 I40E_PHY_COM_REG_PAGE, true, 4390 I40E_PHY_LED_PROV_REG_1, 4391 reg_val, NULL); 4392 } else { 4393 i = rd32(hw, I40E_PFGEN_PORTNUM); 4394 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4395 phy_addr = i40e_get_phy_address(hw, port_num); 4396 status = i40e_write_phy_register_clause45(hw, 4397 I40E_PHY_COM_REG_PAGE, 4398 led_addr, phy_addr, 4399 (u16)reg_val); 4400 } 4401 4402 return status; 4403 } 4404 4405 /** 4406 * i40e_led_get_phy - return current on/off mode 4407 * @hw: pointer to the hw struct 4408 * @led_addr: address of led register to use 4409 * @val: original value of register to use 4410 * 4411 **/ 4412 int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4413 u16 *val) 4414 { 4415 u16 gpio_led_port; 4416 u8 phy_addr = 0; 4417 u32 reg_val_aq; 4418 int status = 0; 4419 u16 temp_addr; 4420 u16 reg_val; 4421 u8 port_num; 4422 u32 i; 4423 4424 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4425 status = 4426 i40e_aq_get_phy_register(hw, 4427 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4428 I40E_PHY_COM_REG_PAGE, true, 4429 I40E_PHY_LED_PROV_REG_1, 4430 ®_val_aq, NULL); 4431 if (status == 0) 4432 *val = (u16)reg_val_aq; 4433 return status; 4434 } 4435 temp_addr = I40E_PHY_LED_PROV_REG_1; 4436 i = rd32(hw, I40E_PFGEN_PORTNUM); 4437 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4438 phy_addr = i40e_get_phy_address(hw, port_num); 4439 4440 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4441 temp_addr++) { 4442 status = i40e_read_phy_register_clause45(hw, 4443 I40E_PHY_COM_REG_PAGE, 4444 temp_addr, phy_addr, 4445 ®_val); 4446 if (status) 4447 return status; 4448 *val = reg_val; 4449 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4450 *led_addr = temp_addr; 4451 break; 4452 } 4453 } 4454 return status; 4455 } 4456 4457 /** 4458 * i40e_led_set_phy 4459 * @hw: pointer to the HW structure 4460 * @on: true or false 4461 * @led_addr: address of led register to use 4462 * @mode: original val plus bit for set or ignore 4463 * 4464 * Set led's on or off when controlled by the PHY 4465 * 4466 **/ 4467 int i40e_led_set_phy(struct i40e_hw *hw, bool on, 4468 u16 led_addr, u32 mode) 4469 { 4470 u32 led_ctl = 0; 4471 u32 led_reg = 0; 4472 int status = 0; 4473 4474 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4475 if (status) 4476 return status; 4477 led_ctl = led_reg; 4478 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4479 led_reg = 0; 4480 status = i40e_led_set_reg(hw, led_addr, led_reg); 4481 if (status) 4482 return status; 4483 } 4484 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4485 if (status) 4486 goto restore_config; 4487 if (on) 4488 led_reg = I40E_PHY_LED_MANUAL_ON; 4489 else 4490 led_reg = 0; 4491 4492 status = i40e_led_set_reg(hw, led_addr, led_reg); 4493 if (status) 4494 goto restore_config; 4495 if (mode & I40E_PHY_LED_MODE_ORIG) { 4496 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 4497 status = i40e_led_set_reg(hw, led_addr, led_ctl); 4498 } 4499 return status; 4500 4501 restore_config: 4502 status = i40e_led_set_reg(hw, led_addr, led_ctl); 4503 return status; 4504 } 4505 4506 /** 4507 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 4508 * @hw: pointer to the hw struct 4509 * @reg_addr: register address 4510 * @reg_val: ptr to register value 4511 * @cmd_details: pointer to command details structure or NULL 4512 * 4513 * Use the firmware to read the Rx control register, 4514 * especially useful if the Rx unit is under heavy pressure 4515 **/ 4516 int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 4517 u32 reg_addr, u32 *reg_val, 4518 struct i40e_asq_cmd_details *cmd_details) 4519 { 4520 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp; 4521 struct libie_aq_desc desc; 4522 int status; 4523 4524 if (!reg_val) 4525 return -EINVAL; 4526 4527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 4528 4529 cmd_resp = libie_aq_raw(&desc); 4530 cmd_resp->address = cpu_to_le32(reg_addr); 4531 4532 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4533 4534 if (status == 0) 4535 *reg_val = le32_to_cpu(cmd_resp->value); 4536 4537 return status; 4538 } 4539 4540 /** 4541 * i40e_read_rx_ctl - read from an Rx control register 4542 * @hw: pointer to the hw struct 4543 * @reg_addr: register address 4544 **/ 4545 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 4546 { 4547 bool use_register = false; 4548 int status = 0; 4549 int retry = 5; 4550 u32 val = 0; 4551 4552 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722) 4553 use_register = true; 4554 4555 if (!use_register) { 4556 do_retry: 4557 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 4558 if (hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN && retry) { 4559 usleep_range(1000, 2000); 4560 retry--; 4561 goto do_retry; 4562 } 4563 } 4564 4565 /* if the AQ access failed, try the old-fashioned way */ 4566 if (status || use_register) 4567 val = rd32(hw, reg_addr); 4568 4569 return val; 4570 } 4571 4572 /** 4573 * i40e_aq_rx_ctl_write_register 4574 * @hw: pointer to the hw struct 4575 * @reg_addr: register address 4576 * @reg_val: register value 4577 * @cmd_details: pointer to command details structure or NULL 4578 * 4579 * Use the firmware to write to an Rx control register, 4580 * especially useful if the Rx unit is under heavy pressure 4581 **/ 4582 int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 4583 u32 reg_addr, u32 reg_val, 4584 struct i40e_asq_cmd_details *cmd_details) 4585 { 4586 struct i40e_aqc_rx_ctl_reg_read_write *cmd; 4587 struct libie_aq_desc desc; 4588 int status; 4589 4590 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 4591 4592 cmd = libie_aq_raw(&desc); 4593 cmd->address = cpu_to_le32(reg_addr); 4594 cmd->value = cpu_to_le32(reg_val); 4595 4596 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4597 4598 return status; 4599 } 4600 4601 /** 4602 * i40e_write_rx_ctl - write to an Rx control register 4603 * @hw: pointer to the hw struct 4604 * @reg_addr: register address 4605 * @reg_val: register value 4606 **/ 4607 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 4608 { 4609 bool use_register = false; 4610 int status = 0; 4611 int retry = 5; 4612 4613 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722) 4614 use_register = true; 4615 4616 if (!use_register) { 4617 do_retry: 4618 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 4619 reg_val, NULL); 4620 if (hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN && retry) { 4621 usleep_range(1000, 2000); 4622 retry--; 4623 goto do_retry; 4624 } 4625 } 4626 4627 /* if the AQ access failed, try the old-fashioned way */ 4628 if (status || use_register) 4629 wr32(hw, reg_addr, reg_val); 4630 } 4631 4632 /** 4633 * i40e_mdio_if_number_selection - MDIO I/F number selection 4634 * @hw: pointer to the hw struct 4635 * @set_mdio: use MDIO I/F number specified by mdio_num 4636 * @mdio_num: MDIO I/F number 4637 * @cmd: pointer to PHY Register command structure 4638 **/ 4639 static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, 4640 u8 mdio_num, 4641 struct i40e_aqc_phy_register_access *cmd) 4642 { 4643 if (!set_mdio || 4644 cmd->phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL) 4645 return; 4646 4647 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps)) { 4648 cmd->cmd_flags |= 4649 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 4650 FIELD_PREP(I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK, 4651 mdio_num); 4652 } else { 4653 i40e_debug(hw, I40E_DEBUG_PHY, "MDIO I/F number selection not supported by current FW version.\n"); 4654 } 4655 } 4656 4657 /** 4658 * i40e_aq_set_phy_register_ext 4659 * @hw: pointer to the hw struct 4660 * @phy_select: select which phy should be accessed 4661 * @dev_addr: PHY device address 4662 * @page_change: flag to indicate if phy page should be updated 4663 * @set_mdio: use MDIO I/F number specified by mdio_num 4664 * @mdio_num: MDIO I/F number 4665 * @reg_addr: PHY register address 4666 * @reg_val: new register value 4667 * @cmd_details: pointer to command details structure or NULL 4668 * 4669 * Write the external PHY register. 4670 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 4671 * may use simple wrapper i40e_aq_set_phy_register. 4672 **/ 4673 int i40e_aq_set_phy_register_ext(struct i40e_hw *hw, 4674 u8 phy_select, u8 dev_addr, bool page_change, 4675 bool set_mdio, u8 mdio_num, 4676 u32 reg_addr, u32 reg_val, 4677 struct i40e_asq_cmd_details *cmd_details) 4678 { 4679 struct i40e_aqc_phy_register_access *cmd; 4680 struct libie_aq_desc desc; 4681 int status; 4682 4683 i40e_fill_default_direct_cmd_desc(&desc, 4684 i40e_aqc_opc_set_phy_register); 4685 4686 cmd = libie_aq_raw(&desc); 4687 cmd->phy_interface = phy_select; 4688 cmd->dev_address = dev_addr; 4689 cmd->reg_address = cpu_to_le32(reg_addr); 4690 cmd->reg_value = cpu_to_le32(reg_val); 4691 4692 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 4693 4694 if (!page_change) 4695 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 4696 4697 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4698 4699 return status; 4700 } 4701 4702 /** 4703 * i40e_aq_get_phy_register_ext 4704 * @hw: pointer to the hw struct 4705 * @phy_select: select which phy should be accessed 4706 * @dev_addr: PHY device address 4707 * @page_change: flag to indicate if phy page should be updated 4708 * @set_mdio: use MDIO I/F number specified by mdio_num 4709 * @mdio_num: MDIO I/F number 4710 * @reg_addr: PHY register address 4711 * @reg_val: read register value 4712 * @cmd_details: pointer to command details structure or NULL 4713 * 4714 * Read the external PHY register. 4715 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 4716 * may use simple wrapper i40e_aq_get_phy_register. 4717 **/ 4718 int i40e_aq_get_phy_register_ext(struct i40e_hw *hw, 4719 u8 phy_select, u8 dev_addr, bool page_change, 4720 bool set_mdio, u8 mdio_num, 4721 u32 reg_addr, u32 *reg_val, 4722 struct i40e_asq_cmd_details *cmd_details) 4723 { 4724 struct i40e_aqc_phy_register_access *cmd; 4725 struct libie_aq_desc desc; 4726 int status; 4727 4728 i40e_fill_default_direct_cmd_desc(&desc, 4729 i40e_aqc_opc_get_phy_register); 4730 4731 cmd = libie_aq_raw(&desc); 4732 cmd->phy_interface = phy_select; 4733 cmd->dev_address = dev_addr; 4734 cmd->reg_address = cpu_to_le32(reg_addr); 4735 4736 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 4737 4738 if (!page_change) 4739 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 4740 4741 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4742 if (!status) 4743 *reg_val = le32_to_cpu(cmd->reg_value); 4744 4745 return status; 4746 } 4747 4748 /** 4749 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 4750 * @hw: pointer to the hw struct 4751 * @buff: command buffer (size in bytes = buff_size) 4752 * @buff_size: buffer size in bytes 4753 * @track_id: package tracking id 4754 * @error_offset: returns error offset 4755 * @error_info: returns error information 4756 * @cmd_details: pointer to command details structure or NULL 4757 **/ 4758 int i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 4759 u16 buff_size, u32 track_id, 4760 u32 *error_offset, u32 *error_info, 4761 struct i40e_asq_cmd_details *cmd_details) 4762 { 4763 struct i40e_aqc_write_personalization_profile *cmd; 4764 struct i40e_aqc_write_ddp_resp *resp; 4765 struct libie_aq_desc desc; 4766 int status; 4767 4768 i40e_fill_default_direct_cmd_desc(&desc, 4769 i40e_aqc_opc_write_personalization_profile); 4770 4771 cmd = libie_aq_raw(&desc); 4772 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD); 4773 if (buff_size > I40E_AQ_LARGE_BUF) 4774 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4775 4776 desc.datalen = cpu_to_le16(buff_size); 4777 4778 cmd->profile_track_id = cpu_to_le32(track_id); 4779 4780 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4781 if (!status) { 4782 resp = libie_aq_raw(&desc); 4783 if (error_offset) 4784 *error_offset = le32_to_cpu(resp->error_offset); 4785 if (error_info) 4786 *error_info = le32_to_cpu(resp->error_info); 4787 } 4788 4789 return status; 4790 } 4791 4792 /** 4793 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 4794 * @hw: pointer to the hw struct 4795 * @buff: command buffer (size in bytes = buff_size) 4796 * @buff_size: buffer size in bytes 4797 * @flags: AdminQ command flags 4798 * @cmd_details: pointer to command details structure or NULL 4799 **/ 4800 int i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 4801 u16 buff_size, u8 flags, 4802 struct i40e_asq_cmd_details *cmd_details) 4803 { 4804 struct i40e_aqc_get_applied_profiles *cmd; 4805 struct libie_aq_desc desc; 4806 int status; 4807 4808 i40e_fill_default_direct_cmd_desc(&desc, 4809 i40e_aqc_opc_get_personalization_profile_list); 4810 4811 cmd = libie_aq_raw(&desc); 4812 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 4813 if (buff_size > I40E_AQ_LARGE_BUF) 4814 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4815 desc.datalen = cpu_to_le16(buff_size); 4816 4817 cmd->flags = flags; 4818 4819 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4820 4821 return status; 4822 } 4823 4824 /** 4825 * i40e_find_segment_in_package 4826 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 4827 * @pkg_hdr: pointer to the package header to be searched 4828 * 4829 * This function searches a package file for a particular segment type. On 4830 * success it returns a pointer to the segment header, otherwise it will 4831 * return NULL. 4832 **/ 4833 struct i40e_generic_seg_header * 4834 i40e_find_segment_in_package(u32 segment_type, 4835 struct i40e_package_header *pkg_hdr) 4836 { 4837 struct i40e_generic_seg_header *segment; 4838 u32 i; 4839 4840 /* Search all package segments for the requested segment type */ 4841 for (i = 0; i < pkg_hdr->segment_count; i++) { 4842 segment = 4843 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 4844 pkg_hdr->segment_offset[i]); 4845 4846 if (segment->type == segment_type) 4847 return segment; 4848 } 4849 4850 return NULL; 4851 } 4852 4853 /* Get section table in profile */ 4854 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 4855 do { \ 4856 struct i40e_profile_segment *p = (profile); \ 4857 u32 count; \ 4858 u32 *nvm; \ 4859 count = p->device_table_count; \ 4860 nvm = (u32 *)&p->device_table[count]; \ 4861 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 4862 } while (0) 4863 4864 /* Get section header in profile */ 4865 #define I40E_SECTION_HEADER(profile, offset) \ 4866 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 4867 4868 /** 4869 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 4870 * @hw: pointer to the hw struct 4871 * @aq: command buffer containing all data to execute AQ 4872 **/ 4873 static int i40e_ddp_exec_aq_section(struct i40e_hw *hw, 4874 struct i40e_profile_aq_section *aq) 4875 { 4876 struct libie_aq_desc desc; 4877 u8 *msg = NULL; 4878 u16 msglen; 4879 int status; 4880 4881 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 4882 desc.flags |= cpu_to_le16(aq->flags); 4883 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw)); 4884 4885 msglen = aq->datalen; 4886 if (msglen) { 4887 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | 4888 LIBIE_AQ_FLAG_RD)); 4889 if (msglen > I40E_AQ_LARGE_BUF) 4890 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4891 desc.datalen = cpu_to_le16(msglen); 4892 msg = &aq->data[0]; 4893 } 4894 4895 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 4896 4897 if (status) { 4898 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4899 "unable to exec DDP AQ opcode %u, error %d\n", 4900 aq->opcode, status); 4901 return status; 4902 } 4903 4904 /* copy returned desc to aq_buf */ 4905 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw)); 4906 4907 return 0; 4908 } 4909 4910 /** 4911 * i40e_validate_profile 4912 * @hw: pointer to the hardware structure 4913 * @profile: pointer to the profile segment of the package to be validated 4914 * @track_id: package tracking id 4915 * @rollback: flag if the profile is for rollback. 4916 * 4917 * Validates supported devices and profile's sections. 4918 */ 4919 static int 4920 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 4921 u32 track_id, bool rollback) 4922 { 4923 struct i40e_profile_section_header *sec = NULL; 4924 struct i40e_section_table *sec_tbl; 4925 u32 vendor_dev_id; 4926 int status = 0; 4927 u32 dev_cnt; 4928 u32 sec_off; 4929 u32 i; 4930 4931 if (track_id == I40E_DDP_TRACKID_INVALID) { 4932 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 4933 return -EOPNOTSUPP; 4934 } 4935 4936 dev_cnt = profile->device_table_count; 4937 for (i = 0; i < dev_cnt; i++) { 4938 vendor_dev_id = profile->device_table[i].vendor_dev_id; 4939 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL && 4940 hw->device_id == (vendor_dev_id & 0xFFFF)) 4941 break; 4942 } 4943 if (dev_cnt && i == dev_cnt) { 4944 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4945 "Device doesn't support DDP\n"); 4946 return -ENODEV; 4947 } 4948 4949 I40E_SECTION_TABLE(profile, sec_tbl); 4950 4951 /* Validate sections types */ 4952 for (i = 0; i < sec_tbl->section_count; i++) { 4953 sec_off = sec_tbl->section_offset[i]; 4954 sec = I40E_SECTION_HEADER(profile, sec_off); 4955 if (rollback) { 4956 if (sec->section.type == SECTION_TYPE_MMIO || 4957 sec->section.type == SECTION_TYPE_AQ || 4958 sec->section.type == SECTION_TYPE_RB_AQ) { 4959 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4960 "Not a roll-back package\n"); 4961 return -EOPNOTSUPP; 4962 } 4963 } else { 4964 if (sec->section.type == SECTION_TYPE_RB_AQ || 4965 sec->section.type == SECTION_TYPE_RB_MMIO) { 4966 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4967 "Not an original package\n"); 4968 return -EOPNOTSUPP; 4969 } 4970 } 4971 } 4972 4973 return status; 4974 } 4975 4976 /** 4977 * i40e_write_profile 4978 * @hw: pointer to the hardware structure 4979 * @profile: pointer to the profile segment of the package to be downloaded 4980 * @track_id: package tracking id 4981 * 4982 * Handles the download of a complete package. 4983 */ 4984 int 4985 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 4986 u32 track_id) 4987 { 4988 struct i40e_profile_section_header *sec = NULL; 4989 struct i40e_profile_aq_section *ddp_aq; 4990 struct i40e_section_table *sec_tbl; 4991 u32 offset = 0, info = 0; 4992 u32 section_size = 0; 4993 int status = 0; 4994 u32 sec_off; 4995 u32 i; 4996 4997 status = i40e_validate_profile(hw, profile, track_id, false); 4998 if (status) 4999 return status; 5000 5001 I40E_SECTION_TABLE(profile, sec_tbl); 5002 5003 for (i = 0; i < sec_tbl->section_count; i++) { 5004 sec_off = sec_tbl->section_offset[i]; 5005 sec = I40E_SECTION_HEADER(profile, sec_off); 5006 /* Process generic admin command */ 5007 if (sec->section.type == SECTION_TYPE_AQ) { 5008 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 5009 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 5010 if (status) { 5011 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5012 "Failed to execute aq: section %d, opcode %u\n", 5013 i, ddp_aq->opcode); 5014 break; 5015 } 5016 sec->section.type = SECTION_TYPE_RB_AQ; 5017 } 5018 5019 /* Skip any non-mmio sections */ 5020 if (sec->section.type != SECTION_TYPE_MMIO) 5021 continue; 5022 5023 section_size = sec->section.size + 5024 sizeof(struct i40e_profile_section_header); 5025 5026 /* Write MMIO section */ 5027 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5028 track_id, &offset, &info, NULL); 5029 if (status) { 5030 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5031 "Failed to write profile: section %d, offset %d, info %d\n", 5032 i, offset, info); 5033 break; 5034 } 5035 } 5036 return status; 5037 } 5038 5039 /** 5040 * i40e_rollback_profile 5041 * @hw: pointer to the hardware structure 5042 * @profile: pointer to the profile segment of the package to be removed 5043 * @track_id: package tracking id 5044 * 5045 * Rolls back previously loaded package. 5046 */ 5047 int 5048 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5049 u32 track_id) 5050 { 5051 struct i40e_profile_section_header *sec = NULL; 5052 struct i40e_section_table *sec_tbl; 5053 u32 offset = 0, info = 0; 5054 u32 section_size = 0; 5055 int status = 0; 5056 u32 sec_off; 5057 int i; 5058 5059 status = i40e_validate_profile(hw, profile, track_id, true); 5060 if (status) 5061 return status; 5062 5063 I40E_SECTION_TABLE(profile, sec_tbl); 5064 5065 /* For rollback write sections in reverse */ 5066 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 5067 sec_off = sec_tbl->section_offset[i]; 5068 sec = I40E_SECTION_HEADER(profile, sec_off); 5069 5070 /* Skip any non-rollback sections */ 5071 if (sec->section.type != SECTION_TYPE_RB_MMIO) 5072 continue; 5073 5074 section_size = sec->section.size + 5075 sizeof(struct i40e_profile_section_header); 5076 5077 /* Write roll-back MMIO section */ 5078 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5079 track_id, &offset, &info, NULL); 5080 if (status) { 5081 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5082 "Failed to write profile: section %d, offset %d, info %d\n", 5083 i, offset, info); 5084 break; 5085 } 5086 } 5087 return status; 5088 } 5089 5090 /** 5091 * i40e_aq_add_cloud_filters 5092 * @hw: pointer to the hardware structure 5093 * @seid: VSI seid to add cloud filters from 5094 * @filters: Buffer which contains the filters to be added 5095 * @filter_count: number of filters contained in the buffer 5096 * 5097 * Set the cloud filters for a given VSI. The contents of the 5098 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5099 * of the function. 5100 * 5101 **/ 5102 int 5103 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5104 struct i40e_aqc_cloud_filters_element_data *filters, 5105 u8 filter_count) 5106 { 5107 struct i40e_aqc_add_remove_cloud_filters *cmd; 5108 struct libie_aq_desc desc; 5109 u16 buff_len; 5110 int status; 5111 5112 i40e_fill_default_direct_cmd_desc(&desc, 5113 i40e_aqc_opc_add_cloud_filters); 5114 5115 cmd = libie_aq_raw(&desc); 5116 buff_len = filter_count * sizeof(*filters); 5117 desc.datalen = cpu_to_le16(buff_len); 5118 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5119 cmd->num_filters = filter_count; 5120 cmd->seid = cpu_to_le16(seid); 5121 5122 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5123 5124 return status; 5125 } 5126 5127 /** 5128 * i40e_aq_add_cloud_filters_bb 5129 * @hw: pointer to the hardware structure 5130 * @seid: VSI seid to add cloud filters from 5131 * @filters: Buffer which contains the filters in big buffer to be added 5132 * @filter_count: number of filters contained in the buffer 5133 * 5134 * Set the big buffer cloud filters for a given VSI. The contents of the 5135 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5136 * function. 5137 * 5138 **/ 5139 int 5140 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5141 struct i40e_aqc_cloud_filters_element_bb *filters, 5142 u8 filter_count) 5143 { 5144 struct i40e_aqc_add_remove_cloud_filters *cmd; 5145 struct libie_aq_desc desc; 5146 u16 buff_len; 5147 int status; 5148 int i; 5149 5150 i40e_fill_default_direct_cmd_desc(&desc, 5151 i40e_aqc_opc_add_cloud_filters); 5152 5153 cmd = libie_aq_raw(&desc); 5154 buff_len = filter_count * sizeof(*filters); 5155 desc.datalen = cpu_to_le16(buff_len); 5156 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5157 cmd->num_filters = filter_count; 5158 cmd->seid = cpu_to_le16(seid); 5159 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5160 5161 for (i = 0; i < filter_count; i++) { 5162 u16 tnl_type; 5163 u32 ti; 5164 5165 tnl_type = le16_get_bits(filters[i].element.flags, 5166 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5167 5168 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5169 * one more byte further than normally used for Tenant ID in 5170 * other tunnel types. 5171 */ 5172 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5173 ti = le32_to_cpu(filters[i].element.tenant_id); 5174 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5175 } 5176 } 5177 5178 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5179 5180 return status; 5181 } 5182 5183 /** 5184 * i40e_aq_rem_cloud_filters 5185 * @hw: pointer to the hardware structure 5186 * @seid: VSI seid to remove cloud filters from 5187 * @filters: Buffer which contains the filters to be removed 5188 * @filter_count: number of filters contained in the buffer 5189 * 5190 * Remove the cloud filters for a given VSI. The contents of the 5191 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5192 * of the function. 5193 * 5194 **/ 5195 int 5196 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5197 struct i40e_aqc_cloud_filters_element_data *filters, 5198 u8 filter_count) 5199 { 5200 struct i40e_aqc_add_remove_cloud_filters *cmd; 5201 struct libie_aq_desc desc; 5202 u16 buff_len; 5203 int status; 5204 5205 i40e_fill_default_direct_cmd_desc(&desc, 5206 i40e_aqc_opc_remove_cloud_filters); 5207 5208 cmd = libie_aq_raw(&desc); 5209 buff_len = filter_count * sizeof(*filters); 5210 desc.datalen = cpu_to_le16(buff_len); 5211 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5212 cmd->num_filters = filter_count; 5213 cmd->seid = cpu_to_le16(seid); 5214 5215 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5216 5217 return status; 5218 } 5219 5220 /** 5221 * i40e_aq_rem_cloud_filters_bb 5222 * @hw: pointer to the hardware structure 5223 * @seid: VSI seid to remove cloud filters from 5224 * @filters: Buffer which contains the filters in big buffer to be removed 5225 * @filter_count: number of filters contained in the buffer 5226 * 5227 * Remove the big buffer cloud filters for a given VSI. The contents of the 5228 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5229 * function. 5230 * 5231 **/ 5232 int 5233 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5234 struct i40e_aqc_cloud_filters_element_bb *filters, 5235 u8 filter_count) 5236 { 5237 struct i40e_aqc_add_remove_cloud_filters *cmd; 5238 struct libie_aq_desc desc; 5239 u16 buff_len; 5240 int status; 5241 int i; 5242 5243 i40e_fill_default_direct_cmd_desc(&desc, 5244 i40e_aqc_opc_remove_cloud_filters); 5245 5246 cmd = libie_aq_raw(&desc); 5247 buff_len = filter_count * sizeof(*filters); 5248 desc.datalen = cpu_to_le16(buff_len); 5249 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5250 cmd->num_filters = filter_count; 5251 cmd->seid = cpu_to_le16(seid); 5252 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5253 5254 for (i = 0; i < filter_count; i++) { 5255 u16 tnl_type; 5256 u32 ti; 5257 5258 tnl_type = le16_get_bits(filters[i].element.flags, 5259 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5260 5261 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5262 * one more byte further than normally used for Tenant ID in 5263 * other tunnel types. 5264 */ 5265 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5266 ti = le32_to_cpu(filters[i].element.tenant_id); 5267 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5268 } 5269 } 5270 5271 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5272 5273 return status; 5274 } 5275