1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #include <linux/avf/virtchnl.h> 5 #include <linux/bitfield.h> 6 #include <linux/delay.h> 7 #include <linux/etherdevice.h> 8 #include <linux/pci.h> 9 #include "i40e_adminq_cmd.h" 10 #include "i40e_devids.h" 11 #include "i40e_prototype.h" 12 #include "i40e_register.h" 13 14 /** 15 * i40e_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the mac type of the adapter based on the 19 * vendor ID and device ID stored in the hw structure. 20 **/ 21 int i40e_set_mac_type(struct i40e_hw *hw) 22 { 23 int status = 0; 24 25 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 26 switch (hw->device_id) { 27 case I40E_DEV_ID_SFP_XL710: 28 case I40E_DEV_ID_QEMU: 29 case I40E_DEV_ID_KX_B: 30 case I40E_DEV_ID_KX_C: 31 case I40E_DEV_ID_QSFP_A: 32 case I40E_DEV_ID_QSFP_B: 33 case I40E_DEV_ID_QSFP_C: 34 case I40E_DEV_ID_1G_BASE_T_BC: 35 case I40E_DEV_ID_5G_BASE_T_BC: 36 case I40E_DEV_ID_10G_BASE_T: 37 case I40E_DEV_ID_10G_BASE_T4: 38 case I40E_DEV_ID_10G_BASE_T_BC: 39 case I40E_DEV_ID_10G_B: 40 case I40E_DEV_ID_10G_SFP: 41 case I40E_DEV_ID_20G_KR2: 42 case I40E_DEV_ID_20G_KR2_A: 43 case I40E_DEV_ID_25G_B: 44 case I40E_DEV_ID_25G_SFP28: 45 case I40E_DEV_ID_X710_N3000: 46 case I40E_DEV_ID_XXV710_N3000: 47 hw->mac.type = I40E_MAC_XL710; 48 break; 49 case I40E_DEV_ID_KX_X722: 50 case I40E_DEV_ID_QSFP_X722: 51 case I40E_DEV_ID_SFP_X722: 52 case I40E_DEV_ID_1G_BASE_T_X722: 53 case I40E_DEV_ID_10G_BASE_T_X722: 54 case I40E_DEV_ID_SFP_I_X722: 55 case I40E_DEV_ID_SFP_X722_A: 56 hw->mac.type = I40E_MAC_X722; 57 break; 58 default: 59 hw->mac.type = I40E_MAC_GENERIC; 60 break; 61 } 62 } else { 63 status = -ENODEV; 64 } 65 66 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 67 hw->mac.type, status); 68 return status; 69 } 70 71 /** 72 * i40e_aq_str - convert AQ err code to a string 73 * @hw: pointer to the HW structure 74 * @aq_err: the AQ error code to convert 75 **/ 76 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 77 { 78 switch (aq_err) { 79 case I40E_AQ_RC_OK: 80 return "OK"; 81 case I40E_AQ_RC_EPERM: 82 return "I40E_AQ_RC_EPERM"; 83 case I40E_AQ_RC_ENOENT: 84 return "I40E_AQ_RC_ENOENT"; 85 case I40E_AQ_RC_ESRCH: 86 return "I40E_AQ_RC_ESRCH"; 87 case I40E_AQ_RC_EINTR: 88 return "I40E_AQ_RC_EINTR"; 89 case I40E_AQ_RC_EIO: 90 return "I40E_AQ_RC_EIO"; 91 case I40E_AQ_RC_ENXIO: 92 return "I40E_AQ_RC_ENXIO"; 93 case I40E_AQ_RC_E2BIG: 94 return "I40E_AQ_RC_E2BIG"; 95 case I40E_AQ_RC_EAGAIN: 96 return "I40E_AQ_RC_EAGAIN"; 97 case I40E_AQ_RC_ENOMEM: 98 return "I40E_AQ_RC_ENOMEM"; 99 case I40E_AQ_RC_EACCES: 100 return "I40E_AQ_RC_EACCES"; 101 case I40E_AQ_RC_EFAULT: 102 return "I40E_AQ_RC_EFAULT"; 103 case I40E_AQ_RC_EBUSY: 104 return "I40E_AQ_RC_EBUSY"; 105 case I40E_AQ_RC_EEXIST: 106 return "I40E_AQ_RC_EEXIST"; 107 case I40E_AQ_RC_EINVAL: 108 return "I40E_AQ_RC_EINVAL"; 109 case I40E_AQ_RC_ENOTTY: 110 return "I40E_AQ_RC_ENOTTY"; 111 case I40E_AQ_RC_ENOSPC: 112 return "I40E_AQ_RC_ENOSPC"; 113 case I40E_AQ_RC_ENOSYS: 114 return "I40E_AQ_RC_ENOSYS"; 115 case I40E_AQ_RC_ERANGE: 116 return "I40E_AQ_RC_ERANGE"; 117 case I40E_AQ_RC_EFLUSHED: 118 return "I40E_AQ_RC_EFLUSHED"; 119 case I40E_AQ_RC_BAD_ADDR: 120 return "I40E_AQ_RC_BAD_ADDR"; 121 case I40E_AQ_RC_EMODE: 122 return "I40E_AQ_RC_EMODE"; 123 case I40E_AQ_RC_EFBIG: 124 return "I40E_AQ_RC_EFBIG"; 125 } 126 127 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 128 return hw->err_str; 129 } 130 131 /** 132 * i40e_debug_aq 133 * @hw: debug mask related to admin queue 134 * @mask: debug mask 135 * @desc: pointer to admin queue descriptor 136 * @buffer: pointer to command buffer 137 * @buf_len: max length of buffer 138 * 139 * Dumps debug log about adminq command with descriptor contents. 140 **/ 141 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 142 void *buffer, u16 buf_len) 143 { 144 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 145 u32 effective_mask = hw->debug_mask & mask; 146 char prefix[27]; 147 u16 len; 148 u8 *buf = (u8 *)buffer; 149 150 if (!effective_mask || !desc) 151 return; 152 153 len = le16_to_cpu(aq_desc->datalen); 154 155 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 156 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 157 le16_to_cpu(aq_desc->opcode), 158 le16_to_cpu(aq_desc->flags), 159 le16_to_cpu(aq_desc->datalen), 160 le16_to_cpu(aq_desc->retval)); 161 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 162 "\tcookie (h,l) 0x%08X 0x%08X\n", 163 le32_to_cpu(aq_desc->cookie_high), 164 le32_to_cpu(aq_desc->cookie_low)); 165 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 166 "\tparam (0,1) 0x%08X 0x%08X\n", 167 le32_to_cpu(aq_desc->params.internal.param0), 168 le32_to_cpu(aq_desc->params.internal.param1)); 169 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 170 "\taddr (h,l) 0x%08X 0x%08X\n", 171 le32_to_cpu(aq_desc->params.external.addr_high), 172 le32_to_cpu(aq_desc->params.external.addr_low)); 173 174 if (buffer && buf_len != 0 && len != 0 && 175 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { 176 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 177 if (buf_len < len) 178 len = buf_len; 179 180 snprintf(prefix, sizeof(prefix), 181 "i40e %02x:%02x.%x: \t0x", 182 hw->bus.bus_id, 183 hw->bus.device, 184 hw->bus.func); 185 186 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 187 16, 1, buf, len, false); 188 } 189 } 190 191 /** 192 * i40e_check_asq_alive 193 * @hw: pointer to the hw struct 194 * 195 * Returns true if Queue is enabled else false. 196 **/ 197 bool i40e_check_asq_alive(struct i40e_hw *hw) 198 { 199 /* Check if the queue is initialized */ 200 if (!hw->aq.asq.count) 201 return false; 202 203 return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK); 204 } 205 206 /** 207 * i40e_aq_queue_shutdown 208 * @hw: pointer to the hw struct 209 * @unloading: is the driver unloading itself 210 * 211 * Tell the Firmware that we're shutting down the AdminQ and whether 212 * or not the driver is unloading as well. 213 **/ 214 int i40e_aq_queue_shutdown(struct i40e_hw *hw, 215 bool unloading) 216 { 217 struct i40e_aq_desc desc; 218 struct i40e_aqc_queue_shutdown *cmd = 219 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 220 int status; 221 222 i40e_fill_default_direct_cmd_desc(&desc, 223 i40e_aqc_opc_queue_shutdown); 224 225 if (unloading) 226 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 227 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 228 229 return status; 230 } 231 232 /** 233 * i40e_aq_get_set_rss_lut 234 * @hw: pointer to the hardware structure 235 * @vsi_id: vsi fw index 236 * @pf_lut: for PF table set true, for VSI table set false 237 * @lut: pointer to the lut buffer provided by the caller 238 * @lut_size: size of the lut buffer 239 * @set: set true to set the table, false to get the table 240 * 241 * Internal function to get or set RSS look up table 242 **/ 243 static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 244 u16 vsi_id, bool pf_lut, 245 u8 *lut, u16 lut_size, 246 bool set) 247 { 248 struct i40e_aq_desc desc; 249 struct i40e_aqc_get_set_rss_lut *cmd_resp = 250 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 251 int status; 252 u16 flags; 253 254 if (set) 255 i40e_fill_default_direct_cmd_desc(&desc, 256 i40e_aqc_opc_set_rss_lut); 257 else 258 i40e_fill_default_direct_cmd_desc(&desc, 259 i40e_aqc_opc_get_rss_lut); 260 261 /* Indirect command */ 262 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 263 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 264 265 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) | 266 FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1); 267 cmd_resp->vsi_id = cpu_to_le16(vsi_id); 268 269 if (pf_lut) 270 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 271 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF); 272 else 273 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 274 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI); 275 276 cmd_resp->flags = cpu_to_le16(flags); 277 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 278 279 return status; 280 } 281 282 /** 283 * i40e_aq_get_rss_lut 284 * @hw: pointer to the hardware structure 285 * @vsi_id: vsi fw index 286 * @pf_lut: for PF table set true, for VSI table set false 287 * @lut: pointer to the lut buffer provided by the caller 288 * @lut_size: size of the lut buffer 289 * 290 * get the RSS lookup table, PF or VSI type 291 **/ 292 int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 293 bool pf_lut, u8 *lut, u16 lut_size) 294 { 295 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 296 false); 297 } 298 299 /** 300 * i40e_aq_set_rss_lut 301 * @hw: pointer to the hardware structure 302 * @vsi_id: vsi fw index 303 * @pf_lut: for PF table set true, for VSI table set false 304 * @lut: pointer to the lut buffer provided by the caller 305 * @lut_size: size of the lut buffer 306 * 307 * set the RSS lookup table, PF or VSI type 308 **/ 309 int i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 310 bool pf_lut, u8 *lut, u16 lut_size) 311 { 312 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 313 } 314 315 /** 316 * i40e_aq_get_set_rss_key 317 * @hw: pointer to the hw struct 318 * @vsi_id: vsi fw index 319 * @key: pointer to key info struct 320 * @set: set true to set the key, false to get the key 321 * 322 * get the RSS key per VSI 323 **/ 324 static int i40e_aq_get_set_rss_key(struct i40e_hw *hw, 325 u16 vsi_id, 326 struct i40e_aqc_get_set_rss_key_data *key, 327 bool set) 328 { 329 struct i40e_aq_desc desc; 330 struct i40e_aqc_get_set_rss_key *cmd_resp = 331 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 332 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 333 int status; 334 335 if (set) 336 i40e_fill_default_direct_cmd_desc(&desc, 337 i40e_aqc_opc_set_rss_key); 338 else 339 i40e_fill_default_direct_cmd_desc(&desc, 340 i40e_aqc_opc_get_rss_key); 341 342 /* Indirect command */ 343 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 344 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 345 346 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) | 347 FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1); 348 cmd_resp->vsi_id = cpu_to_le16(vsi_id); 349 350 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 351 352 return status; 353 } 354 355 /** 356 * i40e_aq_get_rss_key 357 * @hw: pointer to the hw struct 358 * @vsi_id: vsi fw index 359 * @key: pointer to key info struct 360 * 361 **/ 362 int i40e_aq_get_rss_key(struct i40e_hw *hw, 363 u16 vsi_id, 364 struct i40e_aqc_get_set_rss_key_data *key) 365 { 366 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 367 } 368 369 /** 370 * i40e_aq_set_rss_key 371 * @hw: pointer to the hw struct 372 * @vsi_id: vsi fw index 373 * @key: pointer to key info struct 374 * 375 * set the RSS key per VSI 376 **/ 377 int i40e_aq_set_rss_key(struct i40e_hw *hw, 378 u16 vsi_id, 379 struct i40e_aqc_get_set_rss_key_data *key) 380 { 381 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 382 } 383 384 /** 385 * i40e_init_shared_code - Initialize the shared code 386 * @hw: pointer to hardware structure 387 * 388 * This assigns the MAC type and PHY code and inits the NVM. 389 * Does not touch the hardware. This function must be called prior to any 390 * other function in the shared code. The i40e_hw structure should be 391 * memset to 0 prior to calling this function. The following fields in 392 * hw structure should be filled in prior to calling this function: 393 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 394 * subsystem_vendor_id, and revision_id 395 **/ 396 int i40e_init_shared_code(struct i40e_hw *hw) 397 { 398 u32 port, ari, func_rid; 399 int status = 0; 400 401 i40e_set_mac_type(hw); 402 403 switch (hw->mac.type) { 404 case I40E_MAC_XL710: 405 case I40E_MAC_X722: 406 break; 407 default: 408 return -ENODEV; 409 } 410 411 hw->phy.get_link_info = true; 412 413 /* Determine port number and PF number*/ 414 port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK, 415 rd32(hw, I40E_PFGEN_PORTNUM)); 416 hw->port = (u8)port; 417 ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK, 418 rd32(hw, I40E_GLPCI_CAPSUP)); 419 func_rid = rd32(hw, I40E_PF_FUNC_RID); 420 if (ari) 421 hw->pf_id = (u8)(func_rid & 0xff); 422 else 423 hw->pf_id = (u8)(func_rid & 0x7); 424 425 status = i40e_init_nvm(hw); 426 return status; 427 } 428 429 /** 430 * i40e_aq_mac_address_read - Retrieve the MAC addresses 431 * @hw: pointer to the hw struct 432 * @flags: a return indicator of what addresses were added to the addr store 433 * @addrs: the requestor's mac addr store 434 * @cmd_details: pointer to command details structure or NULL 435 **/ 436 static int 437 i40e_aq_mac_address_read(struct i40e_hw *hw, 438 u16 *flags, 439 struct i40e_aqc_mac_address_read_data *addrs, 440 struct i40e_asq_cmd_details *cmd_details) 441 { 442 struct i40e_aq_desc desc; 443 struct i40e_aqc_mac_address_read *cmd_data = 444 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 445 int status; 446 447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 448 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 449 450 status = i40e_asq_send_command(hw, &desc, addrs, 451 sizeof(*addrs), cmd_details); 452 *flags = le16_to_cpu(cmd_data->command_flags); 453 454 return status; 455 } 456 457 /** 458 * i40e_aq_mac_address_write - Change the MAC addresses 459 * @hw: pointer to the hw struct 460 * @flags: indicates which MAC to be written 461 * @mac_addr: address to write 462 * @cmd_details: pointer to command details structure or NULL 463 **/ 464 int i40e_aq_mac_address_write(struct i40e_hw *hw, 465 u16 flags, u8 *mac_addr, 466 struct i40e_asq_cmd_details *cmd_details) 467 { 468 struct i40e_aq_desc desc; 469 struct i40e_aqc_mac_address_write *cmd_data = 470 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 471 int status; 472 473 i40e_fill_default_direct_cmd_desc(&desc, 474 i40e_aqc_opc_mac_address_write); 475 cmd_data->command_flags = cpu_to_le16(flags); 476 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 477 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 478 ((u32)mac_addr[3] << 16) | 479 ((u32)mac_addr[4] << 8) | 480 mac_addr[5]); 481 482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 483 484 return status; 485 } 486 487 /** 488 * i40e_get_mac_addr - get MAC address 489 * @hw: pointer to the HW structure 490 * @mac_addr: pointer to MAC address 491 * 492 * Reads the adapter's MAC address from register 493 **/ 494 int i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 495 { 496 struct i40e_aqc_mac_address_read_data addrs; 497 u16 flags = 0; 498 int status; 499 500 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 501 502 if (flags & I40E_AQC_LAN_ADDR_VALID) 503 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 504 505 return status; 506 } 507 508 /** 509 * i40e_get_port_mac_addr - get Port MAC address 510 * @hw: pointer to the HW structure 511 * @mac_addr: pointer to Port MAC address 512 * 513 * Reads the adapter's Port MAC address 514 **/ 515 int i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 516 { 517 struct i40e_aqc_mac_address_read_data addrs; 518 u16 flags = 0; 519 int status; 520 521 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 522 if (status) 523 return status; 524 525 if (flags & I40E_AQC_PORT_ADDR_VALID) 526 ether_addr_copy(mac_addr, addrs.port_mac); 527 else 528 status = -EINVAL; 529 530 return status; 531 } 532 533 /** 534 * i40e_pre_tx_queue_cfg - pre tx queue configure 535 * @hw: pointer to the HW structure 536 * @queue: target PF queue index 537 * @enable: state change request 538 * 539 * Handles hw requirement to indicate intention to enable 540 * or disable target queue. 541 **/ 542 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 543 { 544 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 545 u32 reg_block = 0; 546 u32 reg_val; 547 548 if (abs_queue_idx >= 128) { 549 reg_block = abs_queue_idx / 128; 550 abs_queue_idx %= 128; 551 } 552 553 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 554 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 555 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 556 557 if (enable) 558 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 559 else 560 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 561 562 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 563 } 564 565 /** 566 * i40e_get_pba_string - Reads part number string from EEPROM 567 * @hw: pointer to hardware structure 568 * 569 * Reads the part number string from the EEPROM and stores it 570 * into newly allocated buffer and saves resulting pointer 571 * to i40e_hw->pba_id field. 572 **/ 573 void i40e_get_pba_string(struct i40e_hw *hw) 574 { 575 #define I40E_NVM_PBA_FLAGS_BLK_PRESENT 0xFAFA 576 u16 pba_word = 0; 577 u16 pba_size = 0; 578 u16 pba_ptr = 0; 579 int status; 580 char *ptr; 581 u16 i; 582 583 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 584 if (status) { 585 hw_dbg(hw, "Failed to read PBA flags.\n"); 586 return; 587 } 588 if (pba_word != I40E_NVM_PBA_FLAGS_BLK_PRESENT) { 589 hw_dbg(hw, "PBA block is not present.\n"); 590 return; 591 } 592 593 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 594 if (status) { 595 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 596 return; 597 } 598 599 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 600 if (status) { 601 hw_dbg(hw, "Failed to read PBA Block size.\n"); 602 return; 603 } 604 605 /* Subtract one to get PBA word count (PBA Size word is included in 606 * total size) and advance pointer to first PBA word. 607 */ 608 pba_size--; 609 pba_ptr++; 610 if (!pba_size) { 611 hw_dbg(hw, "PBA ID is empty.\n"); 612 return; 613 } 614 615 ptr = devm_kzalloc(i40e_hw_to_dev(hw), pba_size * 2 + 1, GFP_KERNEL); 616 if (!ptr) 617 return; 618 hw->pba_id = ptr; 619 620 for (i = 0; i < pba_size; i++) { 621 status = i40e_read_nvm_word(hw, pba_ptr + i, &pba_word); 622 if (status) { 623 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 624 devm_kfree(i40e_hw_to_dev(hw), hw->pba_id); 625 hw->pba_id = NULL; 626 return; 627 } 628 629 *ptr++ = (pba_word >> 8) & 0xFF; 630 *ptr++ = pba_word & 0xFF; 631 } 632 } 633 634 /** 635 * i40e_get_media_type - Gets media type 636 * @hw: pointer to the hardware structure 637 **/ 638 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 639 { 640 enum i40e_media_type media; 641 642 switch (hw->phy.link_info.phy_type) { 643 case I40E_PHY_TYPE_10GBASE_SR: 644 case I40E_PHY_TYPE_10GBASE_LR: 645 case I40E_PHY_TYPE_1000BASE_SX: 646 case I40E_PHY_TYPE_1000BASE_LX: 647 case I40E_PHY_TYPE_40GBASE_SR4: 648 case I40E_PHY_TYPE_40GBASE_LR4: 649 case I40E_PHY_TYPE_25GBASE_LR: 650 case I40E_PHY_TYPE_25GBASE_SR: 651 media = I40E_MEDIA_TYPE_FIBER; 652 break; 653 case I40E_PHY_TYPE_100BASE_TX: 654 case I40E_PHY_TYPE_1000BASE_T: 655 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS: 656 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS: 657 case I40E_PHY_TYPE_10GBASE_T: 658 media = I40E_MEDIA_TYPE_BASET; 659 break; 660 case I40E_PHY_TYPE_10GBASE_CR1_CU: 661 case I40E_PHY_TYPE_40GBASE_CR4_CU: 662 case I40E_PHY_TYPE_10GBASE_CR1: 663 case I40E_PHY_TYPE_40GBASE_CR4: 664 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 665 case I40E_PHY_TYPE_40GBASE_AOC: 666 case I40E_PHY_TYPE_10GBASE_AOC: 667 case I40E_PHY_TYPE_25GBASE_CR: 668 case I40E_PHY_TYPE_25GBASE_AOC: 669 case I40E_PHY_TYPE_25GBASE_ACC: 670 media = I40E_MEDIA_TYPE_DA; 671 break; 672 case I40E_PHY_TYPE_1000BASE_KX: 673 case I40E_PHY_TYPE_10GBASE_KX4: 674 case I40E_PHY_TYPE_10GBASE_KR: 675 case I40E_PHY_TYPE_40GBASE_KR4: 676 case I40E_PHY_TYPE_20GBASE_KR2: 677 case I40E_PHY_TYPE_25GBASE_KR: 678 media = I40E_MEDIA_TYPE_BACKPLANE; 679 break; 680 case I40E_PHY_TYPE_SGMII: 681 case I40E_PHY_TYPE_XAUI: 682 case I40E_PHY_TYPE_XFI: 683 case I40E_PHY_TYPE_XLAUI: 684 case I40E_PHY_TYPE_XLPPI: 685 default: 686 media = I40E_MEDIA_TYPE_UNKNOWN; 687 break; 688 } 689 690 return media; 691 } 692 693 /** 694 * i40e_poll_globr - Poll for Global Reset completion 695 * @hw: pointer to the hardware structure 696 * @retry_limit: how many times to retry before failure 697 **/ 698 static int i40e_poll_globr(struct i40e_hw *hw, 699 u32 retry_limit) 700 { 701 u32 cnt, reg = 0; 702 703 for (cnt = 0; cnt < retry_limit; cnt++) { 704 reg = rd32(hw, I40E_GLGEN_RSTAT); 705 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 706 return 0; 707 msleep(100); 708 } 709 710 hw_dbg(hw, "Global reset failed.\n"); 711 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg); 712 713 return -EIO; 714 } 715 716 #define I40E_PF_RESET_WAIT_COUNT_A0 200 717 #define I40E_PF_RESET_WAIT_COUNT 200 718 /** 719 * i40e_pf_reset - Reset the PF 720 * @hw: pointer to the hardware structure 721 * 722 * Assuming someone else has triggered a global reset, 723 * assure the global reset is complete and then reset the PF 724 **/ 725 int i40e_pf_reset(struct i40e_hw *hw) 726 { 727 u32 cnt = 0; 728 u32 cnt1 = 0; 729 u32 reg = 0; 730 u32 grst_del; 731 732 /* Poll for Global Reset steady state in case of recent GRST. 733 * The grst delay value is in 100ms units, and we'll wait a 734 * couple counts longer to be sure we don't just miss the end. 735 */ 736 grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK, 737 rd32(hw, I40E_GLGEN_RSTCTL)); 738 739 /* It can take upto 15 secs for GRST steady state. 740 * Bump it to 16 secs max to be safe. 741 */ 742 grst_del = grst_del * 20; 743 744 for (cnt = 0; cnt < grst_del; cnt++) { 745 reg = rd32(hw, I40E_GLGEN_RSTAT); 746 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 747 break; 748 msleep(100); 749 } 750 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 751 hw_dbg(hw, "Global reset polling failed to complete.\n"); 752 return -EIO; 753 } 754 755 /* Now Wait for the FW to be ready */ 756 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 757 reg = rd32(hw, I40E_GLNVM_ULD); 758 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 759 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 760 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 761 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 762 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 763 break; 764 } 765 usleep_range(10000, 20000); 766 } 767 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 768 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 769 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 770 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 771 return -EIO; 772 } 773 774 /* If there was a Global Reset in progress when we got here, 775 * we don't need to do the PF Reset 776 */ 777 if (!cnt) { 778 u32 reg2 = 0; 779 if (hw->revision_id == 0) 780 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 781 else 782 cnt = I40E_PF_RESET_WAIT_COUNT; 783 reg = rd32(hw, I40E_PFGEN_CTRL); 784 wr32(hw, I40E_PFGEN_CTRL, 785 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 786 for (; cnt; cnt--) { 787 reg = rd32(hw, I40E_PFGEN_CTRL); 788 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 789 break; 790 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 791 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 792 break; 793 usleep_range(1000, 2000); 794 } 795 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 796 if (i40e_poll_globr(hw, grst_del)) 797 return -EIO; 798 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 799 hw_dbg(hw, "PF reset polling failed to complete.\n"); 800 return -EIO; 801 } 802 } 803 804 i40e_clear_pxe_mode(hw); 805 806 return 0; 807 } 808 809 /** 810 * i40e_clear_hw - clear out any left over hw state 811 * @hw: pointer to the hw struct 812 * 813 * Clear queues and interrupts, typically called at init time, 814 * but after the capabilities have been found so we know how many 815 * queues and msix vectors have been allocated. 816 **/ 817 void i40e_clear_hw(struct i40e_hw *hw) 818 { 819 u32 num_queues, base_queue; 820 u32 num_pf_int; 821 u32 num_vf_int; 822 u32 num_vfs; 823 u32 i, j; 824 u32 val; 825 u32 eol = 0x7ff; 826 827 /* get number of interrupts, queues, and VFs */ 828 val = rd32(hw, I40E_GLPCI_CNF2); 829 num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val); 830 num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val); 831 832 val = rd32(hw, I40E_PFLAN_QALLOC); 833 base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val); 834 j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val); 835 if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue) 836 num_queues = (j - base_queue) + 1; 837 else 838 num_queues = 0; 839 840 val = rd32(hw, I40E_PF_VT_PFALLOC); 841 i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val); 842 j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val); 843 if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i) 844 num_vfs = (j - i) + 1; 845 else 846 num_vfs = 0; 847 848 /* stop all the interrupts */ 849 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 850 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 851 for (i = 0; i < num_pf_int - 2; i++) 852 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 853 854 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 855 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 856 wr32(hw, I40E_PFINT_LNKLST0, val); 857 for (i = 0; i < num_pf_int - 2; i++) 858 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 859 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 860 for (i = 0; i < num_vfs; i++) 861 wr32(hw, I40E_VPINT_LNKLST0(i), val); 862 for (i = 0; i < num_vf_int - 2; i++) 863 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 864 865 /* warn the HW of the coming Tx disables */ 866 for (i = 0; i < num_queues; i++) { 867 u32 abs_queue_idx = base_queue + i; 868 u32 reg_block = 0; 869 870 if (abs_queue_idx >= 128) { 871 reg_block = abs_queue_idx / 128; 872 abs_queue_idx %= 128; 873 } 874 875 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 876 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 877 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 878 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 879 880 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 881 } 882 udelay(400); 883 884 /* stop all the queues */ 885 for (i = 0; i < num_queues; i++) { 886 wr32(hw, I40E_QINT_TQCTL(i), 0); 887 wr32(hw, I40E_QTX_ENA(i), 0); 888 wr32(hw, I40E_QINT_RQCTL(i), 0); 889 wr32(hw, I40E_QRX_ENA(i), 0); 890 } 891 892 /* short wait for all queue disables to settle */ 893 udelay(50); 894 } 895 896 /** 897 * i40e_clear_pxe_mode - clear pxe operations mode 898 * @hw: pointer to the hw struct 899 * 900 * Make sure all PXE mode settings are cleared, including things 901 * like descriptor fetch/write-back mode. 902 **/ 903 void i40e_clear_pxe_mode(struct i40e_hw *hw) 904 { 905 u32 reg; 906 907 if (i40e_check_asq_alive(hw)) 908 i40e_aq_clear_pxe_mode(hw, NULL); 909 910 /* Clear single descriptor fetch/write-back mode */ 911 reg = rd32(hw, I40E_GLLAN_RCTL_0); 912 913 if (hw->revision_id == 0) { 914 /* As a work around clear PXE_MODE instead of setting it */ 915 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 916 } else { 917 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 918 } 919 } 920 921 /** 922 * i40e_led_is_mine - helper to find matching led 923 * @hw: pointer to the hw struct 924 * @idx: index into GPIO registers 925 * 926 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 927 */ 928 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 929 { 930 u32 gpio_val = 0; 931 u32 port; 932 933 if (!I40E_IS_X710TL_DEVICE(hw->device_id) && 934 !hw->func_caps.led[idx]) 935 return 0; 936 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 937 port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val); 938 939 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 940 * if it is not our port then ignore 941 */ 942 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 943 (port != hw->port)) 944 return 0; 945 946 return gpio_val; 947 } 948 949 #define I40E_FW_LED BIT(4) 950 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \ 951 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 952 953 #define I40E_LED0 22 954 955 #define I40E_PIN_FUNC_SDP 0x0 956 #define I40E_PIN_FUNC_LED 0x1 957 958 /** 959 * i40e_led_get - return current on/off mode 960 * @hw: pointer to the hw struct 961 * 962 * The value returned is the 'mode' field as defined in the 963 * GPIO register definitions: 0x0 = off, 0xf = on, and other 964 * values are variations of possible behaviors relating to 965 * blink, link, and wire. 966 **/ 967 u32 i40e_led_get(struct i40e_hw *hw) 968 { 969 u32 mode = 0; 970 int i; 971 972 /* as per the documentation GPIO 22-29 are the LED 973 * GPIO pins named LED0..LED7 974 */ 975 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 976 u32 gpio_val = i40e_led_is_mine(hw, i); 977 978 if (!gpio_val) 979 continue; 980 981 mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val); 982 break; 983 } 984 985 return mode; 986 } 987 988 /** 989 * i40e_led_set - set new on/off mode 990 * @hw: pointer to the hw struct 991 * @mode: 0=off, 0xf=on (else see manual for mode details) 992 * @blink: true if the LED should blink when on, false if steady 993 * 994 * if this function is used to turn on the blink it should 995 * be used to disable the blink when restoring the original state. 996 **/ 997 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 998 { 999 int i; 1000 1001 if (mode & ~I40E_LED_MODE_VALID) { 1002 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1003 return; 1004 } 1005 1006 /* as per the documentation GPIO 22-29 are the LED 1007 * GPIO pins named LED0..LED7 1008 */ 1009 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1010 u32 gpio_val = i40e_led_is_mine(hw, i); 1011 1012 if (!gpio_val) 1013 continue; 1014 1015 if (I40E_IS_X710TL_DEVICE(hw->device_id)) { 1016 u32 pin_func = 0; 1017 1018 if (mode & I40E_FW_LED) 1019 pin_func = I40E_PIN_FUNC_SDP; 1020 else 1021 pin_func = I40E_PIN_FUNC_LED; 1022 1023 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK; 1024 gpio_val |= 1025 FIELD_PREP(I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK, 1026 pin_func); 1027 } 1028 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1029 /* this & is a bit of paranoia, but serves as a range check */ 1030 gpio_val |= FIELD_PREP(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, 1031 mode); 1032 1033 if (blink) 1034 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1035 else 1036 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1037 1038 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1039 break; 1040 } 1041 } 1042 1043 /* Admin command wrappers */ 1044 1045 /** 1046 * i40e_aq_get_phy_capabilities 1047 * @hw: pointer to the hw struct 1048 * @abilities: structure for PHY capabilities to be filled 1049 * @qualified_modules: report Qualified Modules 1050 * @report_init: report init capabilities (active are default) 1051 * @cmd_details: pointer to command details structure or NULL 1052 * 1053 * Returns the various PHY abilities supported on the Port. 1054 **/ 1055 int 1056 i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1057 bool qualified_modules, bool report_init, 1058 struct i40e_aq_get_phy_abilities_resp *abilities, 1059 struct i40e_asq_cmd_details *cmd_details) 1060 { 1061 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1062 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1063 struct i40e_aq_desc desc; 1064 int status; 1065 1066 if (!abilities) 1067 return -EINVAL; 1068 1069 do { 1070 i40e_fill_default_direct_cmd_desc(&desc, 1071 i40e_aqc_opc_get_phy_abilities); 1072 1073 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1074 if (abilities_size > I40E_AQ_LARGE_BUF) 1075 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1076 1077 if (qualified_modules) 1078 desc.params.external.param0 |= 1079 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1080 1081 if (report_init) 1082 desc.params.external.param0 |= 1083 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1084 1085 status = i40e_asq_send_command(hw, &desc, abilities, 1086 abilities_size, cmd_details); 1087 1088 switch (hw->aq.asq_last_status) { 1089 case I40E_AQ_RC_EIO: 1090 status = -EIO; 1091 break; 1092 case I40E_AQ_RC_EAGAIN: 1093 usleep_range(1000, 2000); 1094 total_delay++; 1095 status = -EIO; 1096 break; 1097 /* also covers I40E_AQ_RC_OK */ 1098 default: 1099 break; 1100 } 1101 1102 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) && 1103 (total_delay < max_delay)); 1104 1105 if (status) 1106 return status; 1107 1108 if (report_init) { 1109 if (hw->mac.type == I40E_MAC_XL710 && 1110 i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR, 1111 I40E_MINOR_VER_GET_LINK_INFO_XL710)) { 1112 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1113 } else { 1114 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1115 hw->phy.phy_types |= 1116 ((u64)abilities->phy_type_ext << 32); 1117 } 1118 } 1119 1120 return status; 1121 } 1122 1123 /** 1124 * i40e_aq_set_phy_config 1125 * @hw: pointer to the hw struct 1126 * @config: structure with PHY configuration to be set 1127 * @cmd_details: pointer to command details structure or NULL 1128 * 1129 * Set the various PHY configuration parameters 1130 * supported on the Port.One or more of the Set PHY config parameters may be 1131 * ignored in an MFP mode as the PF may not have the privilege to set some 1132 * of the PHY Config parameters. This status will be indicated by the 1133 * command response. 1134 **/ 1135 int i40e_aq_set_phy_config(struct i40e_hw *hw, 1136 struct i40e_aq_set_phy_config *config, 1137 struct i40e_asq_cmd_details *cmd_details) 1138 { 1139 struct i40e_aq_desc desc; 1140 struct i40e_aq_set_phy_config *cmd = 1141 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1142 int status; 1143 1144 if (!config) 1145 return -EINVAL; 1146 1147 i40e_fill_default_direct_cmd_desc(&desc, 1148 i40e_aqc_opc_set_phy_config); 1149 1150 *cmd = *config; 1151 1152 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1153 1154 return status; 1155 } 1156 1157 static noinline_for_stack int 1158 i40e_set_fc_status(struct i40e_hw *hw, 1159 struct i40e_aq_get_phy_abilities_resp *abilities, 1160 bool atomic_restart) 1161 { 1162 struct i40e_aq_set_phy_config config; 1163 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1164 u8 pause_mask = 0x0; 1165 1166 switch (fc_mode) { 1167 case I40E_FC_FULL: 1168 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1169 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1170 break; 1171 case I40E_FC_RX_PAUSE: 1172 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1173 break; 1174 case I40E_FC_TX_PAUSE: 1175 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1176 break; 1177 default: 1178 break; 1179 } 1180 1181 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1182 /* clear the old pause settings */ 1183 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1184 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1185 /* set the new abilities */ 1186 config.abilities |= pause_mask; 1187 /* If the abilities have changed, then set the new config */ 1188 if (config.abilities == abilities->abilities) 1189 return 0; 1190 1191 /* Auto restart link so settings take effect */ 1192 if (atomic_restart) 1193 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1194 /* Copy over all the old settings */ 1195 config.phy_type = abilities->phy_type; 1196 config.phy_type_ext = abilities->phy_type_ext; 1197 config.link_speed = abilities->link_speed; 1198 config.eee_capability = abilities->eee_capability; 1199 config.eeer = abilities->eeer_val; 1200 config.low_power_ctrl = abilities->d3_lpan; 1201 config.fec_config = abilities->fec_cfg_curr_mod_ext_info & 1202 I40E_AQ_PHY_FEC_CONFIG_MASK; 1203 1204 return i40e_aq_set_phy_config(hw, &config, NULL); 1205 } 1206 1207 /** 1208 * i40e_set_fc 1209 * @hw: pointer to the hw struct 1210 * @aq_failures: buffer to return AdminQ failure information 1211 * @atomic_restart: whether to enable atomic link restart 1212 * 1213 * Set the requested flow control mode using set_phy_config. 1214 **/ 1215 int i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1216 bool atomic_restart) 1217 { 1218 struct i40e_aq_get_phy_abilities_resp abilities; 1219 int status; 1220 1221 *aq_failures = 0x0; 1222 1223 /* Get the current phy config */ 1224 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1225 NULL); 1226 if (status) { 1227 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1228 return status; 1229 } 1230 1231 status = i40e_set_fc_status(hw, &abilities, atomic_restart); 1232 if (status) 1233 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1234 1235 /* Update the link info */ 1236 status = i40e_update_link_info(hw); 1237 if (status) { 1238 /* Wait a little bit (on 40G cards it sometimes takes a really 1239 * long time for link to come back from the atomic reset) 1240 * and try once more 1241 */ 1242 msleep(1000); 1243 status = i40e_update_link_info(hw); 1244 } 1245 if (status) 1246 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1247 1248 return status; 1249 } 1250 1251 /** 1252 * i40e_aq_clear_pxe_mode 1253 * @hw: pointer to the hw struct 1254 * @cmd_details: pointer to command details structure or NULL 1255 * 1256 * Tell the firmware that the driver is taking over from PXE 1257 **/ 1258 int i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1259 struct i40e_asq_cmd_details *cmd_details) 1260 { 1261 struct i40e_aq_desc desc; 1262 struct i40e_aqc_clear_pxe *cmd = 1263 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1264 int status; 1265 1266 i40e_fill_default_direct_cmd_desc(&desc, 1267 i40e_aqc_opc_clear_pxe_mode); 1268 1269 cmd->rx_cnt = 0x2; 1270 1271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1272 1273 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1274 1275 return status; 1276 } 1277 1278 /** 1279 * i40e_aq_set_link_restart_an 1280 * @hw: pointer to the hw struct 1281 * @enable_link: if true: enable link, if false: disable link 1282 * @cmd_details: pointer to command details structure or NULL 1283 * 1284 * Sets up the link and restarts the Auto-Negotiation over the link. 1285 **/ 1286 int i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1287 bool enable_link, 1288 struct i40e_asq_cmd_details *cmd_details) 1289 { 1290 struct i40e_aq_desc desc; 1291 struct i40e_aqc_set_link_restart_an *cmd = 1292 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1293 int status; 1294 1295 i40e_fill_default_direct_cmd_desc(&desc, 1296 i40e_aqc_opc_set_link_restart_an); 1297 1298 cmd->command = I40E_AQ_PHY_RESTART_AN; 1299 if (enable_link) 1300 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1301 else 1302 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1303 1304 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1305 1306 return status; 1307 } 1308 1309 /** 1310 * i40e_aq_get_link_info 1311 * @hw: pointer to the hw struct 1312 * @enable_lse: enable/disable LinkStatusEvent reporting 1313 * @link: pointer to link status structure - optional 1314 * @cmd_details: pointer to command details structure or NULL 1315 * 1316 * Returns the link status of the adapter. 1317 **/ 1318 int i40e_aq_get_link_info(struct i40e_hw *hw, 1319 bool enable_lse, struct i40e_link_status *link, 1320 struct i40e_asq_cmd_details *cmd_details) 1321 { 1322 struct i40e_aq_desc desc; 1323 struct i40e_aqc_get_link_status *resp = 1324 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1325 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1326 bool tx_pause, rx_pause; 1327 u16 command_flags; 1328 int status; 1329 1330 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1331 1332 if (enable_lse) 1333 command_flags = I40E_AQ_LSE_ENABLE; 1334 else 1335 command_flags = I40E_AQ_LSE_DISABLE; 1336 resp->command_flags = cpu_to_le16(command_flags); 1337 1338 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1339 1340 if (status) 1341 goto aq_get_link_info_exit; 1342 1343 /* save off old link status information */ 1344 hw->phy.link_info_old = *hw_link_info; 1345 1346 /* update link status */ 1347 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1348 hw->phy.media_type = i40e_get_media_type(hw); 1349 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1350 hw_link_info->link_info = resp->link_info; 1351 hw_link_info->an_info = resp->an_info; 1352 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1353 I40E_AQ_CONFIG_FEC_RS_ENA); 1354 hw_link_info->ext_info = resp->ext_info; 1355 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1356 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1357 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1358 1359 /* update fc info */ 1360 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1361 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1362 if (tx_pause & rx_pause) 1363 hw->fc.current_mode = I40E_FC_FULL; 1364 else if (tx_pause) 1365 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1366 else if (rx_pause) 1367 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1368 else 1369 hw->fc.current_mode = I40E_FC_NONE; 1370 1371 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1372 hw_link_info->crc_enable = true; 1373 else 1374 hw_link_info->crc_enable = false; 1375 1376 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1377 hw_link_info->lse_enable = true; 1378 else 1379 hw_link_info->lse_enable = false; 1380 1381 if (hw->mac.type == I40E_MAC_XL710 && i40e_is_fw_ver_lt(hw, 4, 40) && 1382 hw_link_info->phy_type == 0xE) 1383 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1384 1385 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps) && 1386 hw->mac.type != I40E_MAC_X722) { 1387 __le32 tmp; 1388 1389 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1390 hw->phy.phy_types = le32_to_cpu(tmp); 1391 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1392 } 1393 1394 /* save link status information */ 1395 if (link) 1396 *link = *hw_link_info; 1397 1398 /* flag cleared so helper functions don't call AQ again */ 1399 hw->phy.get_link_info = false; 1400 1401 aq_get_link_info_exit: 1402 return status; 1403 } 1404 1405 /** 1406 * i40e_aq_set_phy_int_mask 1407 * @hw: pointer to the hw struct 1408 * @mask: interrupt mask to be set 1409 * @cmd_details: pointer to command details structure or NULL 1410 * 1411 * Set link interrupt mask. 1412 **/ 1413 int i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1414 u16 mask, 1415 struct i40e_asq_cmd_details *cmd_details) 1416 { 1417 struct i40e_aq_desc desc; 1418 struct i40e_aqc_set_phy_int_mask *cmd = 1419 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1420 int status; 1421 1422 i40e_fill_default_direct_cmd_desc(&desc, 1423 i40e_aqc_opc_set_phy_int_mask); 1424 1425 cmd->event_mask = cpu_to_le16(mask); 1426 1427 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1428 1429 return status; 1430 } 1431 1432 /** 1433 * i40e_aq_set_mac_loopback 1434 * @hw: pointer to the HW struct 1435 * @ena_lpbk: Enable or Disable loopback 1436 * @cmd_details: pointer to command details structure or NULL 1437 * 1438 * Enable/disable loopback on a given port 1439 */ 1440 int i40e_aq_set_mac_loopback(struct i40e_hw *hw, bool ena_lpbk, 1441 struct i40e_asq_cmd_details *cmd_details) 1442 { 1443 struct i40e_aq_desc desc; 1444 struct i40e_aqc_set_lb_mode *cmd = 1445 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 1446 1447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_lb_modes); 1448 if (ena_lpbk) { 1449 if (hw->nvm.version <= I40E_LEGACY_LOOPBACK_NVM_VER) 1450 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL_LEGACY); 1451 else 1452 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL); 1453 } 1454 1455 return i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1456 } 1457 1458 /** 1459 * i40e_aq_set_phy_debug 1460 * @hw: pointer to the hw struct 1461 * @cmd_flags: debug command flags 1462 * @cmd_details: pointer to command details structure or NULL 1463 * 1464 * Reset the external PHY. 1465 **/ 1466 int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1467 struct i40e_asq_cmd_details *cmd_details) 1468 { 1469 struct i40e_aq_desc desc; 1470 struct i40e_aqc_set_phy_debug *cmd = 1471 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1472 int status; 1473 1474 i40e_fill_default_direct_cmd_desc(&desc, 1475 i40e_aqc_opc_set_phy_debug); 1476 1477 cmd->command_flags = cmd_flags; 1478 1479 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1480 1481 return status; 1482 } 1483 1484 /** 1485 * i40e_aq_add_vsi 1486 * @hw: pointer to the hw struct 1487 * @vsi_ctx: pointer to a vsi context struct 1488 * @cmd_details: pointer to command details structure or NULL 1489 * 1490 * Add a VSI context to the hardware. 1491 **/ 1492 int i40e_aq_add_vsi(struct i40e_hw *hw, 1493 struct i40e_vsi_context *vsi_ctx, 1494 struct i40e_asq_cmd_details *cmd_details) 1495 { 1496 struct i40e_aq_desc desc; 1497 struct i40e_aqc_add_get_update_vsi *cmd = 1498 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1499 struct i40e_aqc_add_get_update_vsi_completion *resp = 1500 (struct i40e_aqc_add_get_update_vsi_completion *) 1501 &desc.params.raw; 1502 int status; 1503 1504 i40e_fill_default_direct_cmd_desc(&desc, 1505 i40e_aqc_opc_add_vsi); 1506 1507 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1508 cmd->connection_type = vsi_ctx->connection_type; 1509 cmd->vf_id = vsi_ctx->vf_num; 1510 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1511 1512 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1513 1514 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1515 sizeof(vsi_ctx->info), 1516 cmd_details, true); 1517 1518 if (status) 1519 goto aq_add_vsi_exit; 1520 1521 vsi_ctx->seid = le16_to_cpu(resp->seid); 1522 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1523 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1524 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1525 1526 aq_add_vsi_exit: 1527 return status; 1528 } 1529 1530 /** 1531 * i40e_aq_set_default_vsi 1532 * @hw: pointer to the hw struct 1533 * @seid: vsi number 1534 * @cmd_details: pointer to command details structure or NULL 1535 **/ 1536 int i40e_aq_set_default_vsi(struct i40e_hw *hw, 1537 u16 seid, 1538 struct i40e_asq_cmd_details *cmd_details) 1539 { 1540 struct i40e_aq_desc desc; 1541 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1542 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1543 &desc.params.raw; 1544 int status; 1545 1546 i40e_fill_default_direct_cmd_desc(&desc, 1547 i40e_aqc_opc_set_vsi_promiscuous_modes); 1548 1549 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1550 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1551 cmd->seid = cpu_to_le16(seid); 1552 1553 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1554 1555 return status; 1556 } 1557 1558 /** 1559 * i40e_aq_clear_default_vsi 1560 * @hw: pointer to the hw struct 1561 * @seid: vsi number 1562 * @cmd_details: pointer to command details structure or NULL 1563 **/ 1564 int i40e_aq_clear_default_vsi(struct i40e_hw *hw, 1565 u16 seid, 1566 struct i40e_asq_cmd_details *cmd_details) 1567 { 1568 struct i40e_aq_desc desc; 1569 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1570 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1571 &desc.params.raw; 1572 int status; 1573 1574 i40e_fill_default_direct_cmd_desc(&desc, 1575 i40e_aqc_opc_set_vsi_promiscuous_modes); 1576 1577 cmd->promiscuous_flags = cpu_to_le16(0); 1578 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1579 cmd->seid = cpu_to_le16(seid); 1580 1581 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1582 1583 return status; 1584 } 1585 1586 /** 1587 * i40e_aq_set_vsi_unicast_promiscuous 1588 * @hw: pointer to the hw struct 1589 * @seid: vsi number 1590 * @set: set unicast promiscuous enable/disable 1591 * @cmd_details: pointer to command details structure or NULL 1592 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 1593 **/ 1594 int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1595 u16 seid, bool set, 1596 struct i40e_asq_cmd_details *cmd_details, 1597 bool rx_only_promisc) 1598 { 1599 struct i40e_aq_desc desc; 1600 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1601 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1602 u16 flags = 0; 1603 int status; 1604 1605 i40e_fill_default_direct_cmd_desc(&desc, 1606 i40e_aqc_opc_set_vsi_promiscuous_modes); 1607 1608 if (set) { 1609 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1610 if (rx_only_promisc && i40e_is_aq_api_ver_ge(hw, 1, 5)) 1611 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1612 } 1613 1614 cmd->promiscuous_flags = cpu_to_le16(flags); 1615 1616 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1617 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1618 cmd->valid_flags |= 1619 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 1620 1621 cmd->seid = cpu_to_le16(seid); 1622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1623 1624 return status; 1625 } 1626 1627 /** 1628 * i40e_aq_set_vsi_multicast_promiscuous 1629 * @hw: pointer to the hw struct 1630 * @seid: vsi number 1631 * @set: set multicast promiscuous enable/disable 1632 * @cmd_details: pointer to command details structure or NULL 1633 **/ 1634 int i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1635 u16 seid, bool set, 1636 struct i40e_asq_cmd_details *cmd_details) 1637 { 1638 struct i40e_aq_desc desc; 1639 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1640 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1641 u16 flags = 0; 1642 int status; 1643 1644 i40e_fill_default_direct_cmd_desc(&desc, 1645 i40e_aqc_opc_set_vsi_promiscuous_modes); 1646 1647 if (set) 1648 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1649 1650 cmd->promiscuous_flags = cpu_to_le16(flags); 1651 1652 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1653 1654 cmd->seid = cpu_to_le16(seid); 1655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1656 1657 return status; 1658 } 1659 1660 /** 1661 * i40e_aq_set_vsi_mc_promisc_on_vlan 1662 * @hw: pointer to the hw struct 1663 * @seid: vsi number 1664 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1665 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 1666 * @cmd_details: pointer to command details structure or NULL 1667 **/ 1668 int i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 1669 u16 seid, bool enable, 1670 u16 vid, 1671 struct i40e_asq_cmd_details *cmd_details) 1672 { 1673 struct i40e_aq_desc desc; 1674 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1675 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1676 u16 flags = 0; 1677 int status; 1678 1679 i40e_fill_default_direct_cmd_desc(&desc, 1680 i40e_aqc_opc_set_vsi_promiscuous_modes); 1681 1682 if (enable) 1683 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1684 1685 cmd->promiscuous_flags = cpu_to_le16(flags); 1686 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1687 cmd->seid = cpu_to_le16(seid); 1688 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1689 1690 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 1691 cmd_details, true); 1692 1693 return status; 1694 } 1695 1696 /** 1697 * i40e_aq_set_vsi_uc_promisc_on_vlan 1698 * @hw: pointer to the hw struct 1699 * @seid: vsi number 1700 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1701 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 1702 * @cmd_details: pointer to command details structure or NULL 1703 **/ 1704 int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 1705 u16 seid, bool enable, 1706 u16 vid, 1707 struct i40e_asq_cmd_details *cmd_details) 1708 { 1709 struct i40e_aq_desc desc; 1710 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1711 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1712 u16 flags = 0; 1713 int status; 1714 1715 i40e_fill_default_direct_cmd_desc(&desc, 1716 i40e_aqc_opc_set_vsi_promiscuous_modes); 1717 1718 if (enable) { 1719 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1720 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1721 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1722 } 1723 1724 cmd->promiscuous_flags = cpu_to_le16(flags); 1725 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1726 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1727 cmd->valid_flags |= 1728 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 1729 cmd->seid = cpu_to_le16(seid); 1730 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1731 1732 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 1733 cmd_details, true); 1734 1735 return status; 1736 } 1737 1738 /** 1739 * i40e_aq_set_vsi_bc_promisc_on_vlan 1740 * @hw: pointer to the hw struct 1741 * @seid: vsi number 1742 * @enable: set broadcast promiscuous enable/disable for a given VLAN 1743 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 1744 * @cmd_details: pointer to command details structure or NULL 1745 **/ 1746 int i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 1747 u16 seid, bool enable, u16 vid, 1748 struct i40e_asq_cmd_details *cmd_details) 1749 { 1750 struct i40e_aq_desc desc; 1751 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1752 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1753 u16 flags = 0; 1754 int status; 1755 1756 i40e_fill_default_direct_cmd_desc(&desc, 1757 i40e_aqc_opc_set_vsi_promiscuous_modes); 1758 1759 if (enable) 1760 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 1761 1762 cmd->promiscuous_flags = cpu_to_le16(flags); 1763 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1764 cmd->seid = cpu_to_le16(seid); 1765 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1766 1767 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1768 1769 return status; 1770 } 1771 1772 /** 1773 * i40e_aq_set_vsi_broadcast 1774 * @hw: pointer to the hw struct 1775 * @seid: vsi number 1776 * @set_filter: true to set filter, false to clear filter 1777 * @cmd_details: pointer to command details structure or NULL 1778 * 1779 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1780 **/ 1781 int i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1782 u16 seid, bool set_filter, 1783 struct i40e_asq_cmd_details *cmd_details) 1784 { 1785 struct i40e_aq_desc desc; 1786 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1787 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1788 int status; 1789 1790 i40e_fill_default_direct_cmd_desc(&desc, 1791 i40e_aqc_opc_set_vsi_promiscuous_modes); 1792 1793 if (set_filter) 1794 cmd->promiscuous_flags 1795 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1796 else 1797 cmd->promiscuous_flags 1798 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1799 1800 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1801 cmd->seid = cpu_to_le16(seid); 1802 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1803 1804 return status; 1805 } 1806 1807 /** 1808 * i40e_aq_get_vsi_params - get VSI configuration info 1809 * @hw: pointer to the hw struct 1810 * @vsi_ctx: pointer to a vsi context struct 1811 * @cmd_details: pointer to command details structure or NULL 1812 **/ 1813 int i40e_aq_get_vsi_params(struct i40e_hw *hw, 1814 struct i40e_vsi_context *vsi_ctx, 1815 struct i40e_asq_cmd_details *cmd_details) 1816 { 1817 struct i40e_aq_desc desc; 1818 struct i40e_aqc_add_get_update_vsi *cmd = 1819 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1820 struct i40e_aqc_add_get_update_vsi_completion *resp = 1821 (struct i40e_aqc_add_get_update_vsi_completion *) 1822 &desc.params.raw; 1823 int status; 1824 1825 i40e_fill_default_direct_cmd_desc(&desc, 1826 i40e_aqc_opc_get_vsi_parameters); 1827 1828 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1829 1830 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1831 1832 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1833 sizeof(vsi_ctx->info), NULL); 1834 1835 if (status) 1836 goto aq_get_vsi_params_exit; 1837 1838 vsi_ctx->seid = le16_to_cpu(resp->seid); 1839 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1840 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1841 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1842 1843 aq_get_vsi_params_exit: 1844 return status; 1845 } 1846 1847 /** 1848 * i40e_aq_update_vsi_params 1849 * @hw: pointer to the hw struct 1850 * @vsi_ctx: pointer to a vsi context struct 1851 * @cmd_details: pointer to command details structure or NULL 1852 * 1853 * Update a VSI context. 1854 **/ 1855 int i40e_aq_update_vsi_params(struct i40e_hw *hw, 1856 struct i40e_vsi_context *vsi_ctx, 1857 struct i40e_asq_cmd_details *cmd_details) 1858 { 1859 struct i40e_aq_desc desc; 1860 struct i40e_aqc_add_get_update_vsi *cmd = 1861 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1862 struct i40e_aqc_add_get_update_vsi_completion *resp = 1863 (struct i40e_aqc_add_get_update_vsi_completion *) 1864 &desc.params.raw; 1865 int status; 1866 1867 i40e_fill_default_direct_cmd_desc(&desc, 1868 i40e_aqc_opc_update_vsi_parameters); 1869 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1870 1871 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1872 1873 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1874 sizeof(vsi_ctx->info), 1875 cmd_details, true); 1876 1877 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1878 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1879 1880 return status; 1881 } 1882 1883 /** 1884 * i40e_aq_get_switch_config 1885 * @hw: pointer to the hardware structure 1886 * @buf: pointer to the result buffer 1887 * @buf_size: length of input buffer 1888 * @start_seid: seid to start for the report, 0 == beginning 1889 * @cmd_details: pointer to command details structure or NULL 1890 * 1891 * Fill the buf with switch configuration returned from AdminQ command 1892 **/ 1893 int i40e_aq_get_switch_config(struct i40e_hw *hw, 1894 struct i40e_aqc_get_switch_config_resp *buf, 1895 u16 buf_size, u16 *start_seid, 1896 struct i40e_asq_cmd_details *cmd_details) 1897 { 1898 struct i40e_aq_desc desc; 1899 struct i40e_aqc_switch_seid *scfg = 1900 (struct i40e_aqc_switch_seid *)&desc.params.raw; 1901 int status; 1902 1903 i40e_fill_default_direct_cmd_desc(&desc, 1904 i40e_aqc_opc_get_switch_config); 1905 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1906 if (buf_size > I40E_AQ_LARGE_BUF) 1907 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1908 scfg->seid = cpu_to_le16(*start_seid); 1909 1910 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1911 *start_seid = le16_to_cpu(scfg->seid); 1912 1913 return status; 1914 } 1915 1916 /** 1917 * i40e_aq_set_switch_config 1918 * @hw: pointer to the hardware structure 1919 * @flags: bit flag values to set 1920 * @mode: cloud filter mode 1921 * @valid_flags: which bit flags to set 1922 * @mode: cloud filter mode 1923 * @cmd_details: pointer to command details structure or NULL 1924 * 1925 * Set switch configuration bits 1926 **/ 1927 int i40e_aq_set_switch_config(struct i40e_hw *hw, 1928 u16 flags, 1929 u16 valid_flags, u8 mode, 1930 struct i40e_asq_cmd_details *cmd_details) 1931 { 1932 struct i40e_aq_desc desc; 1933 struct i40e_aqc_set_switch_config *scfg = 1934 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 1935 int status; 1936 1937 i40e_fill_default_direct_cmd_desc(&desc, 1938 i40e_aqc_opc_set_switch_config); 1939 scfg->flags = cpu_to_le16(flags); 1940 scfg->valid_flags = cpu_to_le16(valid_flags); 1941 scfg->mode = mode; 1942 if (test_bit(I40E_HW_CAP_802_1AD, hw->caps)) { 1943 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 1944 scfg->first_tag = cpu_to_le16(hw->first_tag); 1945 scfg->second_tag = cpu_to_le16(hw->second_tag); 1946 } 1947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1948 1949 return status; 1950 } 1951 1952 /** 1953 * i40e_aq_get_firmware_version 1954 * @hw: pointer to the hw struct 1955 * @fw_major_version: firmware major version 1956 * @fw_minor_version: firmware minor version 1957 * @fw_build: firmware build number 1958 * @api_major_version: major queue version 1959 * @api_minor_version: minor queue version 1960 * @cmd_details: pointer to command details structure or NULL 1961 * 1962 * Get the firmware version from the admin queue commands 1963 **/ 1964 int i40e_aq_get_firmware_version(struct i40e_hw *hw, 1965 u16 *fw_major_version, u16 *fw_minor_version, 1966 u32 *fw_build, 1967 u16 *api_major_version, u16 *api_minor_version, 1968 struct i40e_asq_cmd_details *cmd_details) 1969 { 1970 struct i40e_aq_desc desc; 1971 struct i40e_aqc_get_version *resp = 1972 (struct i40e_aqc_get_version *)&desc.params.raw; 1973 int status; 1974 1975 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1976 1977 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1978 1979 if (!status) { 1980 if (fw_major_version) 1981 *fw_major_version = le16_to_cpu(resp->fw_major); 1982 if (fw_minor_version) 1983 *fw_minor_version = le16_to_cpu(resp->fw_minor); 1984 if (fw_build) 1985 *fw_build = le32_to_cpu(resp->fw_build); 1986 if (api_major_version) 1987 *api_major_version = le16_to_cpu(resp->api_major); 1988 if (api_minor_version) 1989 *api_minor_version = le16_to_cpu(resp->api_minor); 1990 } 1991 1992 return status; 1993 } 1994 1995 /** 1996 * i40e_aq_send_driver_version 1997 * @hw: pointer to the hw struct 1998 * @dv: driver's major, minor version 1999 * @cmd_details: pointer to command details structure or NULL 2000 * 2001 * Send the driver version to the firmware 2002 **/ 2003 int i40e_aq_send_driver_version(struct i40e_hw *hw, 2004 struct i40e_driver_version *dv, 2005 struct i40e_asq_cmd_details *cmd_details) 2006 { 2007 struct i40e_aq_desc desc; 2008 struct i40e_aqc_driver_version *cmd = 2009 (struct i40e_aqc_driver_version *)&desc.params.raw; 2010 int status; 2011 u16 len; 2012 2013 if (dv == NULL) 2014 return -EINVAL; 2015 2016 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2017 2018 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2019 cmd->driver_major_ver = dv->major_version; 2020 cmd->driver_minor_ver = dv->minor_version; 2021 cmd->driver_build_ver = dv->build_version; 2022 cmd->driver_subbuild_ver = dv->subbuild_version; 2023 2024 len = 0; 2025 while (len < sizeof(dv->driver_string) && 2026 (dv->driver_string[len] < 0x80) && 2027 dv->driver_string[len]) 2028 len++; 2029 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2030 len, cmd_details); 2031 2032 return status; 2033 } 2034 2035 /** 2036 * i40e_get_link_status - get status of the HW network link 2037 * @hw: pointer to the hw struct 2038 * @link_up: pointer to bool (true/false = linkup/linkdown) 2039 * 2040 * Variable link_up true if link is up, false if link is down. 2041 * The variable link_up is invalid if returned value of status != 0 2042 * 2043 * Side effect: LinkStatusEvent reporting becomes enabled 2044 **/ 2045 int i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2046 { 2047 int status = 0; 2048 2049 if (hw->phy.get_link_info) { 2050 status = i40e_update_link_info(hw); 2051 2052 if (status) 2053 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2054 status); 2055 } 2056 2057 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2058 2059 return status; 2060 } 2061 2062 /** 2063 * i40e_update_link_info - update status of the HW network link 2064 * @hw: pointer to the hw struct 2065 **/ 2066 noinline_for_stack int i40e_update_link_info(struct i40e_hw *hw) 2067 { 2068 struct i40e_aq_get_phy_abilities_resp abilities; 2069 int status = 0; 2070 2071 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2072 if (status) 2073 return status; 2074 2075 /* extra checking needed to ensure link info to user is timely */ 2076 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2077 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2078 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2079 status = i40e_aq_get_phy_capabilities(hw, false, false, 2080 &abilities, NULL); 2081 if (status) 2082 return status; 2083 2084 if (abilities.fec_cfg_curr_mod_ext_info & 2085 I40E_AQ_ENABLE_FEC_AUTO) 2086 hw->phy.link_info.req_fec_info = 2087 (I40E_AQ_REQUEST_FEC_KR | 2088 I40E_AQ_REQUEST_FEC_RS); 2089 else 2090 hw->phy.link_info.req_fec_info = 2091 abilities.fec_cfg_curr_mod_ext_info & 2092 (I40E_AQ_REQUEST_FEC_KR | 2093 I40E_AQ_REQUEST_FEC_RS); 2094 2095 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2096 sizeof(hw->phy.link_info.module_type)); 2097 } 2098 2099 return status; 2100 } 2101 2102 /** 2103 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2104 * @hw: pointer to the hw struct 2105 * @uplink_seid: the MAC or other gizmo SEID 2106 * @downlink_seid: the VSI SEID 2107 * @enabled_tc: bitmap of TCs to be enabled 2108 * @default_port: true for default port VSI, false for control port 2109 * @veb_seid: pointer to where to put the resulting VEB SEID 2110 * @enable_stats: true to turn on VEB stats 2111 * @cmd_details: pointer to command details structure or NULL 2112 * 2113 * This asks the FW to add a VEB between the uplink and downlink 2114 * elements. If the uplink SEID is 0, this will be a floating VEB. 2115 **/ 2116 int i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2117 u16 downlink_seid, u8 enabled_tc, 2118 bool default_port, u16 *veb_seid, 2119 bool enable_stats, 2120 struct i40e_asq_cmd_details *cmd_details) 2121 { 2122 struct i40e_aq_desc desc; 2123 struct i40e_aqc_add_veb *cmd = 2124 (struct i40e_aqc_add_veb *)&desc.params.raw; 2125 struct i40e_aqc_add_veb_completion *resp = 2126 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2127 u16 veb_flags = 0; 2128 int status; 2129 2130 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2131 if (!!uplink_seid != !!downlink_seid) 2132 return -EINVAL; 2133 2134 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2135 2136 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2137 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2138 cmd->enable_tcs = enabled_tc; 2139 if (!uplink_seid) 2140 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2141 if (default_port) 2142 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2143 else 2144 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2145 2146 /* reverse logic here: set the bitflag to disable the stats */ 2147 if (!enable_stats) 2148 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2149 2150 cmd->veb_flags = cpu_to_le16(veb_flags); 2151 2152 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2153 2154 if (!status && veb_seid) 2155 *veb_seid = le16_to_cpu(resp->veb_seid); 2156 2157 return status; 2158 } 2159 2160 /** 2161 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2162 * @hw: pointer to the hw struct 2163 * @veb_seid: the SEID of the VEB to query 2164 * @switch_id: the uplink switch id 2165 * @floating: set to true if the VEB is floating 2166 * @statistic_index: index of the stats counter block for this VEB 2167 * @vebs_used: number of VEB's used by function 2168 * @vebs_free: total VEB's not reserved by any function 2169 * @cmd_details: pointer to command details structure or NULL 2170 * 2171 * This retrieves the parameters for a particular VEB, specified by 2172 * uplink_seid, and returns them to the caller. 2173 **/ 2174 int i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2175 u16 veb_seid, u16 *switch_id, 2176 bool *floating, u16 *statistic_index, 2177 u16 *vebs_used, u16 *vebs_free, 2178 struct i40e_asq_cmd_details *cmd_details) 2179 { 2180 struct i40e_aq_desc desc; 2181 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2182 (struct i40e_aqc_get_veb_parameters_completion *) 2183 &desc.params.raw; 2184 int status; 2185 2186 if (veb_seid == 0) 2187 return -EINVAL; 2188 2189 i40e_fill_default_direct_cmd_desc(&desc, 2190 i40e_aqc_opc_get_veb_parameters); 2191 cmd_resp->seid = cpu_to_le16(veb_seid); 2192 2193 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2194 if (status) 2195 goto get_veb_exit; 2196 2197 if (switch_id) 2198 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2199 if (statistic_index) 2200 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2201 if (vebs_used) 2202 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2203 if (vebs_free) 2204 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2205 if (floating) { 2206 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2207 2208 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2209 *floating = true; 2210 else 2211 *floating = false; 2212 } 2213 2214 get_veb_exit: 2215 return status; 2216 } 2217 2218 /** 2219 * i40e_prepare_add_macvlan 2220 * @mv_list: list of macvlans to be added 2221 * @desc: pointer to AQ descriptor structure 2222 * @count: length of the list 2223 * @seid: VSI for the mac address 2224 * 2225 * Internal helper function that prepares the add macvlan request 2226 * and returns the buffer size. 2227 **/ 2228 static u16 2229 i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list, 2230 struct i40e_aq_desc *desc, u16 count, u16 seid) 2231 { 2232 struct i40e_aqc_macvlan *cmd = 2233 (struct i40e_aqc_macvlan *)&desc->params.raw; 2234 u16 buf_size; 2235 int i; 2236 2237 buf_size = count * sizeof(*mv_list); 2238 2239 /* prep the rest of the request */ 2240 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan); 2241 cmd->num_addresses = cpu_to_le16(count); 2242 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2243 cmd->seid[1] = 0; 2244 cmd->seid[2] = 0; 2245 2246 for (i = 0; i < count; i++) 2247 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2248 mv_list[i].flags |= 2249 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2250 2251 desc->flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2252 if (buf_size > I40E_AQ_LARGE_BUF) 2253 desc->flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2254 2255 return buf_size; 2256 } 2257 2258 /** 2259 * i40e_aq_add_macvlan 2260 * @hw: pointer to the hw struct 2261 * @seid: VSI for the mac address 2262 * @mv_list: list of macvlans to be added 2263 * @count: length of the list 2264 * @cmd_details: pointer to command details structure or NULL 2265 * 2266 * Add MAC/VLAN addresses to the HW filtering 2267 **/ 2268 int 2269 i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2270 struct i40e_aqc_add_macvlan_element_data *mv_list, 2271 u16 count, struct i40e_asq_cmd_details *cmd_details) 2272 { 2273 struct i40e_aq_desc desc; 2274 u16 buf_size; 2275 2276 if (count == 0 || !mv_list || !hw) 2277 return -EINVAL; 2278 2279 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 2280 2281 return i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2282 cmd_details, true); 2283 } 2284 2285 /** 2286 * i40e_aq_add_macvlan_v2 2287 * @hw: pointer to the hw struct 2288 * @seid: VSI for the mac address 2289 * @mv_list: list of macvlans to be added 2290 * @count: length of the list 2291 * @cmd_details: pointer to command details structure or NULL 2292 * @aq_status: pointer to Admin Queue status return value 2293 * 2294 * Add MAC/VLAN addresses to the HW filtering. 2295 * The _v2 version returns the last Admin Queue status in aq_status 2296 * to avoid race conditions in access to hw->aq.asq_last_status. 2297 * It also calls _v2 versions of asq_send_command functions to 2298 * get the aq_status on the stack. 2299 **/ 2300 int 2301 i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid, 2302 struct i40e_aqc_add_macvlan_element_data *mv_list, 2303 u16 count, struct i40e_asq_cmd_details *cmd_details, 2304 enum i40e_admin_queue_err *aq_status) 2305 { 2306 struct i40e_aq_desc desc; 2307 u16 buf_size; 2308 2309 if (count == 0 || !mv_list || !hw) 2310 return -EINVAL; 2311 2312 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 2313 2314 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2315 cmd_details, true, aq_status); 2316 } 2317 2318 /** 2319 * i40e_aq_remove_macvlan 2320 * @hw: pointer to the hw struct 2321 * @seid: VSI for the mac address 2322 * @mv_list: list of macvlans to be removed 2323 * @count: length of the list 2324 * @cmd_details: pointer to command details structure or NULL 2325 * 2326 * Remove MAC/VLAN addresses from the HW filtering 2327 **/ 2328 int 2329 i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2330 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2331 u16 count, struct i40e_asq_cmd_details *cmd_details) 2332 { 2333 struct i40e_aq_desc desc; 2334 struct i40e_aqc_macvlan *cmd = 2335 (struct i40e_aqc_macvlan *)&desc.params.raw; 2336 u16 buf_size; 2337 int status; 2338 2339 if (count == 0 || !mv_list || !hw) 2340 return -EINVAL; 2341 2342 buf_size = count * sizeof(*mv_list); 2343 2344 /* prep the rest of the request */ 2345 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2346 cmd->num_addresses = cpu_to_le16(count); 2347 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2348 cmd->seid[1] = 0; 2349 cmd->seid[2] = 0; 2350 2351 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2352 if (buf_size > I40E_AQ_LARGE_BUF) 2353 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2354 2355 status = i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2356 cmd_details, true); 2357 2358 return status; 2359 } 2360 2361 /** 2362 * i40e_aq_remove_macvlan_v2 2363 * @hw: pointer to the hw struct 2364 * @seid: VSI for the mac address 2365 * @mv_list: list of macvlans to be removed 2366 * @count: length of the list 2367 * @cmd_details: pointer to command details structure or NULL 2368 * @aq_status: pointer to Admin Queue status return value 2369 * 2370 * Remove MAC/VLAN addresses from the HW filtering. 2371 * The _v2 version returns the last Admin Queue status in aq_status 2372 * to avoid race conditions in access to hw->aq.asq_last_status. 2373 * It also calls _v2 versions of asq_send_command functions to 2374 * get the aq_status on the stack. 2375 **/ 2376 int 2377 i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid, 2378 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2379 u16 count, struct i40e_asq_cmd_details *cmd_details, 2380 enum i40e_admin_queue_err *aq_status) 2381 { 2382 struct i40e_aqc_macvlan *cmd; 2383 struct i40e_aq_desc desc; 2384 u16 buf_size; 2385 2386 if (count == 0 || !mv_list || !hw) 2387 return -EINVAL; 2388 2389 buf_size = count * sizeof(*mv_list); 2390 2391 /* prep the rest of the request */ 2392 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2393 cmd = (struct i40e_aqc_macvlan *)&desc.params.raw; 2394 cmd->num_addresses = cpu_to_le16(count); 2395 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2396 cmd->seid[1] = 0; 2397 cmd->seid[2] = 0; 2398 2399 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2400 if (buf_size > I40E_AQ_LARGE_BUF) 2401 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2402 2403 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2404 cmd_details, true, aq_status); 2405 } 2406 2407 /** 2408 * i40e_aq_send_msg_to_vf 2409 * @hw: pointer to the hardware structure 2410 * @vfid: VF id to send msg 2411 * @v_opcode: opcodes for VF-PF communication 2412 * @v_retval: return error code 2413 * @msg: pointer to the msg buffer 2414 * @msglen: msg length 2415 * @cmd_details: pointer to command details 2416 * 2417 * send msg to vf 2418 **/ 2419 int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2420 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2421 struct i40e_asq_cmd_details *cmd_details) 2422 { 2423 struct i40e_aq_desc desc; 2424 struct i40e_aqc_pf_vf_message *cmd = 2425 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2426 int status; 2427 2428 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2429 cmd->id = cpu_to_le32(vfid); 2430 desc.cookie_high = cpu_to_le32(v_opcode); 2431 desc.cookie_low = cpu_to_le32(v_retval); 2432 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2433 if (msglen) { 2434 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2435 I40E_AQ_FLAG_RD)); 2436 if (msglen > I40E_AQ_LARGE_BUF) 2437 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2438 desc.datalen = cpu_to_le16(msglen); 2439 } 2440 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2441 2442 return status; 2443 } 2444 2445 /** 2446 * i40e_aq_debug_read_register 2447 * @hw: pointer to the hw struct 2448 * @reg_addr: register address 2449 * @reg_val: register value 2450 * @cmd_details: pointer to command details structure or NULL 2451 * 2452 * Read the register using the admin queue commands 2453 **/ 2454 int i40e_aq_debug_read_register(struct i40e_hw *hw, 2455 u32 reg_addr, u64 *reg_val, 2456 struct i40e_asq_cmd_details *cmd_details) 2457 { 2458 struct i40e_aq_desc desc; 2459 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2460 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2461 int status; 2462 2463 if (reg_val == NULL) 2464 return -EINVAL; 2465 2466 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2467 2468 cmd_resp->address = cpu_to_le32(reg_addr); 2469 2470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2471 2472 if (!status) { 2473 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2474 (u64)le32_to_cpu(cmd_resp->value_low); 2475 } 2476 2477 return status; 2478 } 2479 2480 /** 2481 * i40e_aq_debug_write_register 2482 * @hw: pointer to the hw struct 2483 * @reg_addr: register address 2484 * @reg_val: register value 2485 * @cmd_details: pointer to command details structure or NULL 2486 * 2487 * Write to a register using the admin queue commands 2488 **/ 2489 int i40e_aq_debug_write_register(struct i40e_hw *hw, 2490 u32 reg_addr, u64 reg_val, 2491 struct i40e_asq_cmd_details *cmd_details) 2492 { 2493 struct i40e_aq_desc desc; 2494 struct i40e_aqc_debug_reg_read_write *cmd = 2495 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2496 int status; 2497 2498 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2499 2500 cmd->address = cpu_to_le32(reg_addr); 2501 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2502 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2503 2504 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2505 2506 return status; 2507 } 2508 2509 /** 2510 * i40e_aq_request_resource 2511 * @hw: pointer to the hw struct 2512 * @resource: resource id 2513 * @access: access type 2514 * @sdp_number: resource number 2515 * @timeout: the maximum time in ms that the driver may hold the resource 2516 * @cmd_details: pointer to command details structure or NULL 2517 * 2518 * requests common resource using the admin queue commands 2519 **/ 2520 int i40e_aq_request_resource(struct i40e_hw *hw, 2521 enum i40e_aq_resources_ids resource, 2522 enum i40e_aq_resource_access_type access, 2523 u8 sdp_number, u64 *timeout, 2524 struct i40e_asq_cmd_details *cmd_details) 2525 { 2526 struct i40e_aq_desc desc; 2527 struct i40e_aqc_request_resource *cmd_resp = 2528 (struct i40e_aqc_request_resource *)&desc.params.raw; 2529 int status; 2530 2531 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2532 2533 cmd_resp->resource_id = cpu_to_le16(resource); 2534 cmd_resp->access_type = cpu_to_le16(access); 2535 cmd_resp->resource_number = cpu_to_le32(sdp_number); 2536 2537 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2538 /* The completion specifies the maximum time in ms that the driver 2539 * may hold the resource in the Timeout field. 2540 * If the resource is held by someone else, the command completes with 2541 * busy return value and the timeout field indicates the maximum time 2542 * the current owner of the resource has to free it. 2543 */ 2544 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2545 *timeout = le32_to_cpu(cmd_resp->timeout); 2546 2547 return status; 2548 } 2549 2550 /** 2551 * i40e_aq_release_resource 2552 * @hw: pointer to the hw struct 2553 * @resource: resource id 2554 * @sdp_number: resource number 2555 * @cmd_details: pointer to command details structure or NULL 2556 * 2557 * release common resource using the admin queue commands 2558 **/ 2559 int i40e_aq_release_resource(struct i40e_hw *hw, 2560 enum i40e_aq_resources_ids resource, 2561 u8 sdp_number, 2562 struct i40e_asq_cmd_details *cmd_details) 2563 { 2564 struct i40e_aq_desc desc; 2565 struct i40e_aqc_request_resource *cmd = 2566 (struct i40e_aqc_request_resource *)&desc.params.raw; 2567 int status; 2568 2569 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2570 2571 cmd->resource_id = cpu_to_le16(resource); 2572 cmd->resource_number = cpu_to_le32(sdp_number); 2573 2574 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2575 2576 return status; 2577 } 2578 2579 /** 2580 * i40e_aq_read_nvm 2581 * @hw: pointer to the hw struct 2582 * @module_pointer: module pointer location in words from the NVM beginning 2583 * @offset: byte offset from the module beginning 2584 * @length: length of the section to be read (in bytes from the offset) 2585 * @data: command buffer (size [bytes] = length) 2586 * @last_command: tells if this is the last command in a series 2587 * @cmd_details: pointer to command details structure or NULL 2588 * 2589 * Read the NVM using the admin queue commands 2590 **/ 2591 int i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2592 u32 offset, u16 length, void *data, 2593 bool last_command, 2594 struct i40e_asq_cmd_details *cmd_details) 2595 { 2596 struct i40e_aq_desc desc; 2597 struct i40e_aqc_nvm_update *cmd = 2598 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2599 int status; 2600 2601 /* In offset the highest byte must be zeroed. */ 2602 if (offset & 0xFF000000) { 2603 status = -EINVAL; 2604 goto i40e_aq_read_nvm_exit; 2605 } 2606 2607 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2608 2609 /* If this is the last command in a series, set the proper flag. */ 2610 if (last_command) 2611 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2612 cmd->module_pointer = module_pointer; 2613 cmd->offset = cpu_to_le32(offset); 2614 cmd->length = cpu_to_le16(length); 2615 2616 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2617 if (length > I40E_AQ_LARGE_BUF) 2618 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2619 2620 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2621 2622 i40e_aq_read_nvm_exit: 2623 return status; 2624 } 2625 2626 /** 2627 * i40e_aq_erase_nvm 2628 * @hw: pointer to the hw struct 2629 * @module_pointer: module pointer location in words from the NVM beginning 2630 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2631 * @length: length of the section to be erased (expressed in 4 KB) 2632 * @last_command: tells if this is the last command in a series 2633 * @cmd_details: pointer to command details structure or NULL 2634 * 2635 * Erase the NVM sector using the admin queue commands 2636 **/ 2637 int i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2638 u32 offset, u16 length, bool last_command, 2639 struct i40e_asq_cmd_details *cmd_details) 2640 { 2641 struct i40e_aq_desc desc; 2642 struct i40e_aqc_nvm_update *cmd = 2643 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2644 int status; 2645 2646 /* In offset the highest byte must be zeroed. */ 2647 if (offset & 0xFF000000) { 2648 status = -EINVAL; 2649 goto i40e_aq_erase_nvm_exit; 2650 } 2651 2652 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2653 2654 /* If this is the last command in a series, set the proper flag. */ 2655 if (last_command) 2656 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2657 cmd->module_pointer = module_pointer; 2658 cmd->offset = cpu_to_le32(offset); 2659 cmd->length = cpu_to_le16(length); 2660 2661 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2662 2663 i40e_aq_erase_nvm_exit: 2664 return status; 2665 } 2666 2667 /** 2668 * i40e_parse_discover_capabilities 2669 * @hw: pointer to the hw struct 2670 * @buff: pointer to a buffer containing device/function capability records 2671 * @cap_count: number of capability records in the list 2672 * @list_type_opc: type of capabilities list to parse 2673 * 2674 * Parse the device/function capabilities list. 2675 **/ 2676 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2677 u32 cap_count, 2678 enum i40e_admin_queue_opc list_type_opc) 2679 { 2680 struct i40e_aqc_list_capabilities_element_resp *cap; 2681 u32 valid_functions, num_functions; 2682 u32 number, logical_id, phys_id; 2683 struct i40e_hw_capabilities *p; 2684 u16 id, ocp_cfg_word0; 2685 u8 major_rev; 2686 int status; 2687 u32 i = 0; 2688 2689 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2690 2691 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2692 p = &hw->dev_caps; 2693 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2694 p = &hw->func_caps; 2695 else 2696 return; 2697 2698 for (i = 0; i < cap_count; i++, cap++) { 2699 id = le16_to_cpu(cap->id); 2700 number = le32_to_cpu(cap->number); 2701 logical_id = le32_to_cpu(cap->logical_id); 2702 phys_id = le32_to_cpu(cap->phys_id); 2703 major_rev = cap->major_rev; 2704 2705 switch (id) { 2706 case I40E_AQ_CAP_ID_SWITCH_MODE: 2707 p->switch_mode = number; 2708 break; 2709 case I40E_AQ_CAP_ID_MNG_MODE: 2710 p->management_mode = number; 2711 if (major_rev > 1) { 2712 p->mng_protocols_over_mctp = logical_id; 2713 i40e_debug(hw, I40E_DEBUG_INIT, 2714 "HW Capability: Protocols over MCTP = %d\n", 2715 p->mng_protocols_over_mctp); 2716 } else { 2717 p->mng_protocols_over_mctp = 0; 2718 } 2719 break; 2720 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 2721 p->npar_enable = number; 2722 break; 2723 case I40E_AQ_CAP_ID_OS2BMC_CAP: 2724 p->os2bmc = number; 2725 break; 2726 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 2727 p->valid_functions = number; 2728 break; 2729 case I40E_AQ_CAP_ID_SRIOV: 2730 if (number == 1) 2731 p->sr_iov_1_1 = true; 2732 break; 2733 case I40E_AQ_CAP_ID_VF: 2734 p->num_vfs = number; 2735 p->vf_base_id = logical_id; 2736 break; 2737 case I40E_AQ_CAP_ID_VMDQ: 2738 if (number == 1) 2739 p->vmdq = true; 2740 break; 2741 case I40E_AQ_CAP_ID_8021QBG: 2742 if (number == 1) 2743 p->evb_802_1_qbg = true; 2744 break; 2745 case I40E_AQ_CAP_ID_8021QBR: 2746 if (number == 1) 2747 p->evb_802_1_qbh = true; 2748 break; 2749 case I40E_AQ_CAP_ID_VSI: 2750 p->num_vsis = number; 2751 break; 2752 case I40E_AQ_CAP_ID_DCB: 2753 if (number == 1) { 2754 p->dcb = true; 2755 p->enabled_tcmap = logical_id; 2756 p->maxtc = phys_id; 2757 } 2758 break; 2759 case I40E_AQ_CAP_ID_FCOE: 2760 if (number == 1) 2761 p->fcoe = true; 2762 break; 2763 case I40E_AQ_CAP_ID_ISCSI: 2764 if (number == 1) 2765 p->iscsi = true; 2766 break; 2767 case I40E_AQ_CAP_ID_RSS: 2768 p->rss = true; 2769 p->rss_table_size = number; 2770 p->rss_table_entry_width = logical_id; 2771 break; 2772 case I40E_AQ_CAP_ID_RXQ: 2773 p->num_rx_qp = number; 2774 p->base_queue = phys_id; 2775 break; 2776 case I40E_AQ_CAP_ID_TXQ: 2777 p->num_tx_qp = number; 2778 p->base_queue = phys_id; 2779 break; 2780 case I40E_AQ_CAP_ID_MSIX: 2781 p->num_msix_vectors = number; 2782 i40e_debug(hw, I40E_DEBUG_INIT, 2783 "HW Capability: MSIX vector count = %d\n", 2784 p->num_msix_vectors); 2785 break; 2786 case I40E_AQ_CAP_ID_VF_MSIX: 2787 p->num_msix_vectors_vf = number; 2788 break; 2789 case I40E_AQ_CAP_ID_FLEX10: 2790 if (major_rev == 1) { 2791 if (number == 1) { 2792 p->flex10_enable = true; 2793 p->flex10_capable = true; 2794 } 2795 } else { 2796 /* Capability revision >= 2 */ 2797 if (number & 1) 2798 p->flex10_enable = true; 2799 if (number & 2) 2800 p->flex10_capable = true; 2801 } 2802 p->flex10_mode = logical_id; 2803 p->flex10_status = phys_id; 2804 break; 2805 case I40E_AQ_CAP_ID_CEM: 2806 if (number == 1) 2807 p->mgmt_cem = true; 2808 break; 2809 case I40E_AQ_CAP_ID_IWARP: 2810 if (number == 1) 2811 p->iwarp = true; 2812 break; 2813 case I40E_AQ_CAP_ID_LED: 2814 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2815 p->led[phys_id] = true; 2816 break; 2817 case I40E_AQ_CAP_ID_SDP: 2818 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2819 p->sdp[phys_id] = true; 2820 break; 2821 case I40E_AQ_CAP_ID_MDIO: 2822 if (number == 1) { 2823 p->mdio_port_num = phys_id; 2824 p->mdio_port_mode = logical_id; 2825 } 2826 break; 2827 case I40E_AQ_CAP_ID_1588: 2828 if (number == 1) 2829 p->ieee_1588 = true; 2830 break; 2831 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 2832 p->fd = true; 2833 p->fd_filters_guaranteed = number; 2834 p->fd_filters_best_effort = logical_id; 2835 break; 2836 case I40E_AQ_CAP_ID_WSR_PROT: 2837 p->wr_csr_prot = (u64)number; 2838 p->wr_csr_prot |= (u64)logical_id << 32; 2839 break; 2840 case I40E_AQ_CAP_ID_NVM_MGMT: 2841 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 2842 p->sec_rev_disabled = true; 2843 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 2844 p->update_disabled = true; 2845 break; 2846 default: 2847 break; 2848 } 2849 } 2850 2851 if (p->fcoe) 2852 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 2853 2854 /* Software override ensuring FCoE is disabled if npar or mfp 2855 * mode because it is not supported in these modes. 2856 */ 2857 if (p->npar_enable || p->flex10_enable) 2858 p->fcoe = false; 2859 2860 /* count the enabled ports (aka the "not disabled" ports) */ 2861 hw->num_ports = 0; 2862 for (i = 0; i < 4; i++) { 2863 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 2864 u64 port_cfg = 0; 2865 2866 /* use AQ read to get the physical register offset instead 2867 * of the port relative offset 2868 */ 2869 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 2870 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 2871 hw->num_ports++; 2872 } 2873 2874 /* OCP cards case: if a mezz is removed the Ethernet port is at 2875 * disabled state in PRTGEN_CNF register. Additional NVM read is 2876 * needed in order to check if we are dealing with OCP card. 2877 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 2878 * physical ports results in wrong partition id calculation and thus 2879 * not supporting WoL. 2880 */ 2881 if (hw->mac.type == I40E_MAC_X722) { 2882 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) { 2883 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 2884 2 * I40E_SR_OCP_CFG_WORD0, 2885 sizeof(ocp_cfg_word0), 2886 &ocp_cfg_word0, true, NULL); 2887 if (!status && 2888 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 2889 hw->num_ports = 4; 2890 i40e_release_nvm(hw); 2891 } 2892 } 2893 2894 valid_functions = p->valid_functions; 2895 num_functions = 0; 2896 while (valid_functions) { 2897 if (valid_functions & 1) 2898 num_functions++; 2899 valid_functions >>= 1; 2900 } 2901 2902 /* partition id is 1-based, and functions are evenly spread 2903 * across the ports as partitions 2904 */ 2905 if (hw->num_ports != 0) { 2906 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 2907 hw->num_partitions = num_functions / hw->num_ports; 2908 } 2909 2910 /* additional HW specific goodies that might 2911 * someday be HW version specific 2912 */ 2913 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 2914 } 2915 2916 /** 2917 * i40e_aq_discover_capabilities 2918 * @hw: pointer to the hw struct 2919 * @buff: a virtual buffer to hold the capabilities 2920 * @buff_size: Size of the virtual buffer 2921 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 2922 * @list_type_opc: capabilities type to discover - pass in the command opcode 2923 * @cmd_details: pointer to command details structure or NULL 2924 * 2925 * Get the device capabilities descriptions from the firmware 2926 **/ 2927 int i40e_aq_discover_capabilities(struct i40e_hw *hw, 2928 void *buff, u16 buff_size, u16 *data_size, 2929 enum i40e_admin_queue_opc list_type_opc, 2930 struct i40e_asq_cmd_details *cmd_details) 2931 { 2932 struct i40e_aqc_list_capabilites *cmd; 2933 struct i40e_aq_desc desc; 2934 int status = 0; 2935 2936 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 2937 2938 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 2939 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 2940 status = -EINVAL; 2941 goto exit; 2942 } 2943 2944 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 2945 2946 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2947 if (buff_size > I40E_AQ_LARGE_BUF) 2948 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2949 2950 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2951 *data_size = le16_to_cpu(desc.datalen); 2952 2953 if (status) 2954 goto exit; 2955 2956 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 2957 list_type_opc); 2958 2959 exit: 2960 return status; 2961 } 2962 2963 /** 2964 * i40e_aq_update_nvm 2965 * @hw: pointer to the hw struct 2966 * @module_pointer: module pointer location in words from the NVM beginning 2967 * @offset: byte offset from the module beginning 2968 * @length: length of the section to be written (in bytes from the offset) 2969 * @data: command buffer (size [bytes] = length) 2970 * @last_command: tells if this is the last command in a series 2971 * @preservation_flags: Preservation mode flags 2972 * @cmd_details: pointer to command details structure or NULL 2973 * 2974 * Update the NVM using the admin queue commands 2975 **/ 2976 int i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 2977 u32 offset, u16 length, void *data, 2978 bool last_command, u8 preservation_flags, 2979 struct i40e_asq_cmd_details *cmd_details) 2980 { 2981 struct i40e_aq_desc desc; 2982 struct i40e_aqc_nvm_update *cmd = 2983 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2984 int status; 2985 2986 /* In offset the highest byte must be zeroed. */ 2987 if (offset & 0xFF000000) { 2988 status = -EINVAL; 2989 goto i40e_aq_update_nvm_exit; 2990 } 2991 2992 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 2993 2994 /* If this is the last command in a series, set the proper flag. */ 2995 if (last_command) 2996 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2997 if (hw->mac.type == I40E_MAC_X722) { 2998 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 2999 cmd->command_flags |= 3000 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 3001 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3002 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 3003 cmd->command_flags |= 3004 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 3005 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3006 } 3007 cmd->module_pointer = module_pointer; 3008 cmd->offset = cpu_to_le32(offset); 3009 cmd->length = cpu_to_le16(length); 3010 3011 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3012 if (length > I40E_AQ_LARGE_BUF) 3013 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3014 3015 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3016 3017 i40e_aq_update_nvm_exit: 3018 return status; 3019 } 3020 3021 /** 3022 * i40e_aq_get_lldp_mib 3023 * @hw: pointer to the hw struct 3024 * @bridge_type: type of bridge requested 3025 * @mib_type: Local, Remote or both Local and Remote MIBs 3026 * @buff: pointer to a user supplied buffer to store the MIB block 3027 * @buff_size: size of the buffer (in bytes) 3028 * @local_len : length of the returned Local LLDP MIB 3029 * @remote_len: length of the returned Remote LLDP MIB 3030 * @cmd_details: pointer to command details structure or NULL 3031 * 3032 * Requests the complete LLDP MIB (entire packet). 3033 **/ 3034 int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3035 u8 mib_type, void *buff, u16 buff_size, 3036 u16 *local_len, u16 *remote_len, 3037 struct i40e_asq_cmd_details *cmd_details) 3038 { 3039 struct i40e_aq_desc desc; 3040 struct i40e_aqc_lldp_get_mib *cmd = 3041 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3042 struct i40e_aqc_lldp_get_mib *resp = 3043 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3044 int status; 3045 3046 if (buff_size == 0 || !buff) 3047 return -EINVAL; 3048 3049 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3050 /* Indirect Command */ 3051 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3052 3053 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3054 cmd->type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type); 3055 3056 desc.datalen = cpu_to_le16(buff_size); 3057 3058 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3059 if (buff_size > I40E_AQ_LARGE_BUF) 3060 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3061 3062 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3063 if (!status) { 3064 if (local_len != NULL) 3065 *local_len = le16_to_cpu(resp->local_len); 3066 if (remote_len != NULL) 3067 *remote_len = le16_to_cpu(resp->remote_len); 3068 } 3069 3070 return status; 3071 } 3072 3073 /** 3074 * i40e_aq_set_lldp_mib - Set the LLDP MIB 3075 * @hw: pointer to the hw struct 3076 * @mib_type: Local, Remote or both Local and Remote MIBs 3077 * @buff: pointer to a user supplied buffer to store the MIB block 3078 * @buff_size: size of the buffer (in bytes) 3079 * @cmd_details: pointer to command details structure or NULL 3080 * 3081 * Set the LLDP MIB. 3082 **/ 3083 int 3084 i40e_aq_set_lldp_mib(struct i40e_hw *hw, 3085 u8 mib_type, void *buff, u16 buff_size, 3086 struct i40e_asq_cmd_details *cmd_details) 3087 { 3088 struct i40e_aqc_lldp_set_local_mib *cmd; 3089 struct i40e_aq_desc desc; 3090 int status; 3091 3092 cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 3093 if (buff_size == 0 || !buff) 3094 return -EINVAL; 3095 3096 i40e_fill_default_direct_cmd_desc(&desc, 3097 i40e_aqc_opc_lldp_set_local_mib); 3098 /* Indirect Command */ 3099 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3100 if (buff_size > I40E_AQ_LARGE_BUF) 3101 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3102 desc.datalen = cpu_to_le16(buff_size); 3103 3104 cmd->type = mib_type; 3105 cmd->length = cpu_to_le16(buff_size); 3106 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff)); 3107 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff)); 3108 3109 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3110 return status; 3111 } 3112 3113 /** 3114 * i40e_aq_cfg_lldp_mib_change_event 3115 * @hw: pointer to the hw struct 3116 * @enable_update: Enable or Disable event posting 3117 * @cmd_details: pointer to command details structure or NULL 3118 * 3119 * Enable or Disable posting of an event on ARQ when LLDP MIB 3120 * associated with the interface changes 3121 **/ 3122 int i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3123 bool enable_update, 3124 struct i40e_asq_cmd_details *cmd_details) 3125 { 3126 struct i40e_aq_desc desc; 3127 struct i40e_aqc_lldp_update_mib *cmd = 3128 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3129 int status; 3130 3131 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3132 3133 if (!enable_update) 3134 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3135 3136 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3137 3138 return status; 3139 } 3140 3141 /** 3142 * i40e_aq_stop_lldp 3143 * @hw: pointer to the hw struct 3144 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3145 * @persist: True if stop of LLDP should be persistent across power cycles 3146 * @cmd_details: pointer to command details structure or NULL 3147 * 3148 * Stop or Shutdown the embedded LLDP Agent 3149 **/ 3150 int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3151 bool persist, 3152 struct i40e_asq_cmd_details *cmd_details) 3153 { 3154 struct i40e_aq_desc desc; 3155 struct i40e_aqc_lldp_stop *cmd = 3156 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3157 int status; 3158 3159 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3160 3161 if (shutdown_agent) 3162 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3163 3164 if (persist) { 3165 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) 3166 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST; 3167 else 3168 i40e_debug(hw, I40E_DEBUG_ALL, 3169 "Persistent Stop LLDP not supported by current FW version.\n"); 3170 } 3171 3172 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3173 3174 return status; 3175 } 3176 3177 /** 3178 * i40e_aq_start_lldp 3179 * @hw: pointer to the hw struct 3180 * @persist: True if start of LLDP should be persistent across power cycles 3181 * @cmd_details: pointer to command details structure or NULL 3182 * 3183 * Start the embedded LLDP Agent on all ports. 3184 **/ 3185 int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist, 3186 struct i40e_asq_cmd_details *cmd_details) 3187 { 3188 struct i40e_aq_desc desc; 3189 struct i40e_aqc_lldp_start *cmd = 3190 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3191 int status; 3192 3193 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3194 3195 cmd->command = I40E_AQ_LLDP_AGENT_START; 3196 3197 if (persist) { 3198 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) 3199 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST; 3200 else 3201 i40e_debug(hw, I40E_DEBUG_ALL, 3202 "Persistent Start LLDP not supported by current FW version.\n"); 3203 } 3204 3205 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3206 3207 return status; 3208 } 3209 3210 /** 3211 * i40e_aq_set_dcb_parameters 3212 * @hw: pointer to the hw struct 3213 * @cmd_details: pointer to command details structure or NULL 3214 * @dcb_enable: True if DCB configuration needs to be applied 3215 * 3216 **/ 3217 int 3218 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 3219 struct i40e_asq_cmd_details *cmd_details) 3220 { 3221 struct i40e_aq_desc desc; 3222 struct i40e_aqc_set_dcb_parameters *cmd = 3223 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 3224 int status; 3225 3226 if (!test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps)) 3227 return -ENODEV; 3228 3229 i40e_fill_default_direct_cmd_desc(&desc, 3230 i40e_aqc_opc_set_dcb_parameters); 3231 3232 if (dcb_enable) { 3233 cmd->valid_flags = I40E_DCB_VALID; 3234 cmd->command = I40E_AQ_DCB_SET_AGENT; 3235 } 3236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3237 3238 return status; 3239 } 3240 3241 /** 3242 * i40e_aq_get_cee_dcb_config 3243 * @hw: pointer to the hw struct 3244 * @buff: response buffer that stores CEE operational configuration 3245 * @buff_size: size of the buffer passed 3246 * @cmd_details: pointer to command details structure or NULL 3247 * 3248 * Get CEE DCBX mode operational configuration from firmware 3249 **/ 3250 int i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3251 void *buff, u16 buff_size, 3252 struct i40e_asq_cmd_details *cmd_details) 3253 { 3254 struct i40e_aq_desc desc; 3255 int status; 3256 3257 if (buff_size == 0 || !buff) 3258 return -EINVAL; 3259 3260 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3261 3262 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3263 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3264 cmd_details); 3265 3266 return status; 3267 } 3268 3269 /** 3270 * i40e_aq_add_udp_tunnel 3271 * @hw: pointer to the hw struct 3272 * @udp_port: the UDP port to add in Host byte order 3273 * @protocol_index: protocol index type 3274 * @filter_index: pointer to filter index 3275 * @cmd_details: pointer to command details structure or NULL 3276 * 3277 * Note: Firmware expects the udp_port value to be in Little Endian format, 3278 * and this function will call cpu_to_le16 to convert from Host byte order to 3279 * Little Endian order. 3280 **/ 3281 int i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3282 u16 udp_port, u8 protocol_index, 3283 u8 *filter_index, 3284 struct i40e_asq_cmd_details *cmd_details) 3285 { 3286 struct i40e_aq_desc desc; 3287 struct i40e_aqc_add_udp_tunnel *cmd = 3288 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3289 struct i40e_aqc_del_udp_tunnel_completion *resp = 3290 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3291 int status; 3292 3293 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3294 3295 cmd->udp_port = cpu_to_le16(udp_port); 3296 cmd->protocol_type = protocol_index; 3297 3298 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3299 3300 if (!status && filter_index) 3301 *filter_index = resp->index; 3302 3303 return status; 3304 } 3305 3306 /** 3307 * i40e_aq_del_udp_tunnel 3308 * @hw: pointer to the hw struct 3309 * @index: filter index 3310 * @cmd_details: pointer to command details structure or NULL 3311 **/ 3312 int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3313 struct i40e_asq_cmd_details *cmd_details) 3314 { 3315 struct i40e_aq_desc desc; 3316 struct i40e_aqc_remove_udp_tunnel *cmd = 3317 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3318 int status; 3319 3320 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3321 3322 cmd->index = index; 3323 3324 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3325 3326 return status; 3327 } 3328 3329 /** 3330 * i40e_aq_delete_element - Delete switch element 3331 * @hw: pointer to the hw struct 3332 * @seid: the SEID to delete from the switch 3333 * @cmd_details: pointer to command details structure or NULL 3334 * 3335 * This deletes a switch element from the switch. 3336 **/ 3337 int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3338 struct i40e_asq_cmd_details *cmd_details) 3339 { 3340 struct i40e_aq_desc desc; 3341 struct i40e_aqc_switch_seid *cmd = 3342 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3343 int status; 3344 3345 if (seid == 0) 3346 return -EINVAL; 3347 3348 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3349 3350 cmd->seid = cpu_to_le16(seid); 3351 3352 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 3353 cmd_details, true); 3354 3355 return status; 3356 } 3357 3358 /** 3359 * i40e_aq_dcb_updated - DCB Updated Command 3360 * @hw: pointer to the hw struct 3361 * @cmd_details: pointer to command details structure or NULL 3362 * 3363 * EMP will return when the shared RPB settings have been 3364 * recomputed and modified. The retval field in the descriptor 3365 * will be set to 0 when RPB is modified. 3366 **/ 3367 int i40e_aq_dcb_updated(struct i40e_hw *hw, 3368 struct i40e_asq_cmd_details *cmd_details) 3369 { 3370 struct i40e_aq_desc desc; 3371 int status; 3372 3373 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3374 3375 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3376 3377 return status; 3378 } 3379 3380 /** 3381 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3382 * @hw: pointer to the hw struct 3383 * @seid: seid for the physical port/switching component/vsi 3384 * @buff: Indirect buffer to hold data parameters and response 3385 * @buff_size: Indirect buffer size 3386 * @opcode: Tx scheduler AQ command opcode 3387 * @cmd_details: pointer to command details structure or NULL 3388 * 3389 * Generic command handler for Tx scheduler AQ commands 3390 **/ 3391 static int i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3392 void *buff, u16 buff_size, 3393 enum i40e_admin_queue_opc opcode, 3394 struct i40e_asq_cmd_details *cmd_details) 3395 { 3396 struct i40e_aq_desc desc; 3397 struct i40e_aqc_tx_sched_ind *cmd = 3398 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3399 int status; 3400 bool cmd_param_flag = false; 3401 3402 switch (opcode) { 3403 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3404 case i40e_aqc_opc_configure_vsi_tc_bw: 3405 case i40e_aqc_opc_enable_switching_comp_ets: 3406 case i40e_aqc_opc_modify_switching_comp_ets: 3407 case i40e_aqc_opc_disable_switching_comp_ets: 3408 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3409 case i40e_aqc_opc_configure_switching_comp_bw_config: 3410 cmd_param_flag = true; 3411 break; 3412 case i40e_aqc_opc_query_vsi_bw_config: 3413 case i40e_aqc_opc_query_vsi_ets_sla_config: 3414 case i40e_aqc_opc_query_switching_comp_ets_config: 3415 case i40e_aqc_opc_query_port_ets_config: 3416 case i40e_aqc_opc_query_switching_comp_bw_config: 3417 cmd_param_flag = false; 3418 break; 3419 default: 3420 return -EINVAL; 3421 } 3422 3423 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3424 3425 /* Indirect command */ 3426 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3427 if (cmd_param_flag) 3428 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3429 if (buff_size > I40E_AQ_LARGE_BUF) 3430 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3431 3432 desc.datalen = cpu_to_le16(buff_size); 3433 3434 cmd->vsi_seid = cpu_to_le16(seid); 3435 3436 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3437 3438 return status; 3439 } 3440 3441 /** 3442 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3443 * @hw: pointer to the hw struct 3444 * @seid: VSI seid 3445 * @credit: BW limit credits (0 = disabled) 3446 * @max_credit: Max BW limit credits 3447 * @cmd_details: pointer to command details structure or NULL 3448 **/ 3449 int i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3450 u16 seid, u16 credit, u8 max_credit, 3451 struct i40e_asq_cmd_details *cmd_details) 3452 { 3453 struct i40e_aq_desc desc; 3454 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3455 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3456 int status; 3457 3458 i40e_fill_default_direct_cmd_desc(&desc, 3459 i40e_aqc_opc_configure_vsi_bw_limit); 3460 3461 cmd->vsi_seid = cpu_to_le16(seid); 3462 cmd->credit = cpu_to_le16(credit); 3463 cmd->max_credit = max_credit; 3464 3465 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3466 3467 return status; 3468 } 3469 3470 /** 3471 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3472 * @hw: pointer to the hw struct 3473 * @seid: VSI seid 3474 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3475 * @cmd_details: pointer to command details structure or NULL 3476 **/ 3477 int i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3478 u16 seid, 3479 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3480 struct i40e_asq_cmd_details *cmd_details) 3481 { 3482 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3483 i40e_aqc_opc_configure_vsi_tc_bw, 3484 cmd_details); 3485 } 3486 3487 /** 3488 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3489 * @hw: pointer to the hw struct 3490 * @seid: seid of the switching component connected to Physical Port 3491 * @ets_data: Buffer holding ETS parameters 3492 * @opcode: Tx scheduler AQ command opcode 3493 * @cmd_details: pointer to command details structure or NULL 3494 **/ 3495 int 3496 i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3497 u16 seid, 3498 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3499 enum i40e_admin_queue_opc opcode, 3500 struct i40e_asq_cmd_details *cmd_details) 3501 { 3502 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3503 sizeof(*ets_data), opcode, cmd_details); 3504 } 3505 3506 /** 3507 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3508 * @hw: pointer to the hw struct 3509 * @seid: seid of the switching component 3510 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3511 * @cmd_details: pointer to command details structure or NULL 3512 **/ 3513 int 3514 i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3515 u16 seid, 3516 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3517 struct i40e_asq_cmd_details *cmd_details) 3518 { 3519 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3520 i40e_aqc_opc_configure_switching_comp_bw_config, 3521 cmd_details); 3522 } 3523 3524 /** 3525 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3526 * @hw: pointer to the hw struct 3527 * @seid: seid of the VSI 3528 * @bw_data: Buffer to hold VSI BW configuration 3529 * @cmd_details: pointer to command details structure or NULL 3530 **/ 3531 int 3532 i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3533 u16 seid, 3534 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3535 struct i40e_asq_cmd_details *cmd_details) 3536 { 3537 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3538 i40e_aqc_opc_query_vsi_bw_config, 3539 cmd_details); 3540 } 3541 3542 /** 3543 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3544 * @hw: pointer to the hw struct 3545 * @seid: seid of the VSI 3546 * @bw_data: Buffer to hold VSI BW configuration per TC 3547 * @cmd_details: pointer to command details structure or NULL 3548 **/ 3549 int 3550 i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3551 u16 seid, 3552 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3553 struct i40e_asq_cmd_details *cmd_details) 3554 { 3555 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3556 i40e_aqc_opc_query_vsi_ets_sla_config, 3557 cmd_details); 3558 } 3559 3560 /** 3561 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3562 * @hw: pointer to the hw struct 3563 * @seid: seid of the switching component 3564 * @bw_data: Buffer to hold switching component's per TC BW config 3565 * @cmd_details: pointer to command details structure or NULL 3566 **/ 3567 int 3568 i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3569 u16 seid, 3570 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3571 struct i40e_asq_cmd_details *cmd_details) 3572 { 3573 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3574 i40e_aqc_opc_query_switching_comp_ets_config, 3575 cmd_details); 3576 } 3577 3578 /** 3579 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3580 * @hw: pointer to the hw struct 3581 * @seid: seid of the VSI or switching component connected to Physical Port 3582 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3583 * @cmd_details: pointer to command details structure or NULL 3584 **/ 3585 int 3586 i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3587 u16 seid, 3588 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3589 struct i40e_asq_cmd_details *cmd_details) 3590 { 3591 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3592 i40e_aqc_opc_query_port_ets_config, 3593 cmd_details); 3594 } 3595 3596 /** 3597 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3598 * @hw: pointer to the hw struct 3599 * @seid: seid of the switching component 3600 * @bw_data: Buffer to hold switching component's BW configuration 3601 * @cmd_details: pointer to command details structure or NULL 3602 **/ 3603 int 3604 i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3605 u16 seid, 3606 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3607 struct i40e_asq_cmd_details *cmd_details) 3608 { 3609 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3610 i40e_aqc_opc_query_switching_comp_bw_config, 3611 cmd_details); 3612 } 3613 3614 /** 3615 * i40e_validate_filter_settings 3616 * @hw: pointer to the hardware structure 3617 * @settings: Filter control settings 3618 * 3619 * Check and validate the filter control settings passed. 3620 * The function checks for the valid filter/context sizes being 3621 * passed for FCoE and PE. 3622 * 3623 * Returns 0 if the values passed are valid and within 3624 * range else returns an error. 3625 **/ 3626 static int 3627 i40e_validate_filter_settings(struct i40e_hw *hw, 3628 struct i40e_filter_control_settings *settings) 3629 { 3630 u32 fcoe_cntx_size, fcoe_filt_size; 3631 u32 fcoe_fmax; 3632 u32 val; 3633 3634 /* Validate FCoE settings passed */ 3635 switch (settings->fcoe_filt_num) { 3636 case I40E_HASH_FILTER_SIZE_1K: 3637 case I40E_HASH_FILTER_SIZE_2K: 3638 case I40E_HASH_FILTER_SIZE_4K: 3639 case I40E_HASH_FILTER_SIZE_8K: 3640 case I40E_HASH_FILTER_SIZE_16K: 3641 case I40E_HASH_FILTER_SIZE_32K: 3642 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3643 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3644 break; 3645 default: 3646 return -EINVAL; 3647 } 3648 3649 switch (settings->fcoe_cntx_num) { 3650 case I40E_DMA_CNTX_SIZE_512: 3651 case I40E_DMA_CNTX_SIZE_1K: 3652 case I40E_DMA_CNTX_SIZE_2K: 3653 case I40E_DMA_CNTX_SIZE_4K: 3654 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3655 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3656 break; 3657 default: 3658 return -EINVAL; 3659 } 3660 3661 /* Validate PE settings passed */ 3662 switch (settings->pe_filt_num) { 3663 case I40E_HASH_FILTER_SIZE_1K: 3664 case I40E_HASH_FILTER_SIZE_2K: 3665 case I40E_HASH_FILTER_SIZE_4K: 3666 case I40E_HASH_FILTER_SIZE_8K: 3667 case I40E_HASH_FILTER_SIZE_16K: 3668 case I40E_HASH_FILTER_SIZE_32K: 3669 case I40E_HASH_FILTER_SIZE_64K: 3670 case I40E_HASH_FILTER_SIZE_128K: 3671 case I40E_HASH_FILTER_SIZE_256K: 3672 case I40E_HASH_FILTER_SIZE_512K: 3673 case I40E_HASH_FILTER_SIZE_1M: 3674 break; 3675 default: 3676 return -EINVAL; 3677 } 3678 3679 switch (settings->pe_cntx_num) { 3680 case I40E_DMA_CNTX_SIZE_512: 3681 case I40E_DMA_CNTX_SIZE_1K: 3682 case I40E_DMA_CNTX_SIZE_2K: 3683 case I40E_DMA_CNTX_SIZE_4K: 3684 case I40E_DMA_CNTX_SIZE_8K: 3685 case I40E_DMA_CNTX_SIZE_16K: 3686 case I40E_DMA_CNTX_SIZE_32K: 3687 case I40E_DMA_CNTX_SIZE_64K: 3688 case I40E_DMA_CNTX_SIZE_128K: 3689 case I40E_DMA_CNTX_SIZE_256K: 3690 break; 3691 default: 3692 return -EINVAL; 3693 } 3694 3695 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3696 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3697 fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val); 3698 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3699 return -EINVAL; 3700 3701 return 0; 3702 } 3703 3704 /** 3705 * i40e_set_filter_control 3706 * @hw: pointer to the hardware structure 3707 * @settings: Filter control settings 3708 * 3709 * Set the Queue Filters for PE/FCoE and enable filters required 3710 * for a single PF. It is expected that these settings are programmed 3711 * at the driver initialization time. 3712 **/ 3713 int i40e_set_filter_control(struct i40e_hw *hw, 3714 struct i40e_filter_control_settings *settings) 3715 { 3716 u32 hash_lut_size = 0; 3717 int ret = 0; 3718 u32 val; 3719 3720 if (!settings) 3721 return -EINVAL; 3722 3723 /* Validate the input settings */ 3724 ret = i40e_validate_filter_settings(hw, settings); 3725 if (ret) 3726 return ret; 3727 3728 /* Read the PF Queue Filter control register */ 3729 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 3730 3731 /* Program required PE hash buckets for the PF */ 3732 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 3733 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEHSIZE_MASK, settings->pe_filt_num); 3734 /* Program required PE contexts for the PF */ 3735 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 3736 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEDSIZE_MASK, settings->pe_cntx_num); 3737 3738 /* Program required FCoE hash buckets for the PF */ 3739 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3740 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCHSIZE_MASK, 3741 settings->fcoe_filt_num); 3742 /* Program required FCoE DDP contexts for the PF */ 3743 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3744 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCDSIZE_MASK, 3745 settings->fcoe_cntx_num); 3746 3747 /* Program Hash LUT size for the PF */ 3748 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3749 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 3750 hash_lut_size = 1; 3751 val |= FIELD_PREP(I40E_PFQF_CTL_0_HASHLUTSIZE_MASK, hash_lut_size); 3752 3753 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 3754 if (settings->enable_fdir) 3755 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 3756 if (settings->enable_ethtype) 3757 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 3758 if (settings->enable_macvlan) 3759 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 3760 3761 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 3762 3763 return 0; 3764 } 3765 3766 /** 3767 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 3768 * @hw: pointer to the hw struct 3769 * @mac_addr: MAC address to use in the filter 3770 * @ethtype: Ethertype to use in the filter 3771 * @flags: Flags that needs to be applied to the filter 3772 * @vsi_seid: seid of the control VSI 3773 * @queue: VSI queue number to send the packet to 3774 * @is_add: Add control packet filter if True else remove 3775 * @stats: Structure to hold information on control filter counts 3776 * @cmd_details: pointer to command details structure or NULL 3777 * 3778 * This command will Add or Remove control packet filter for a control VSI. 3779 * In return it will update the total number of perfect filter count in 3780 * the stats member. 3781 **/ 3782 int i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 3783 u8 *mac_addr, u16 ethtype, u16 flags, 3784 u16 vsi_seid, u16 queue, bool is_add, 3785 struct i40e_control_filter_stats *stats, 3786 struct i40e_asq_cmd_details *cmd_details) 3787 { 3788 struct i40e_aq_desc desc; 3789 struct i40e_aqc_add_remove_control_packet_filter *cmd = 3790 (struct i40e_aqc_add_remove_control_packet_filter *) 3791 &desc.params.raw; 3792 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 3793 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 3794 &desc.params.raw; 3795 int status; 3796 3797 if (vsi_seid == 0) 3798 return -EINVAL; 3799 3800 if (is_add) { 3801 i40e_fill_default_direct_cmd_desc(&desc, 3802 i40e_aqc_opc_add_control_packet_filter); 3803 cmd->queue = cpu_to_le16(queue); 3804 } else { 3805 i40e_fill_default_direct_cmd_desc(&desc, 3806 i40e_aqc_opc_remove_control_packet_filter); 3807 } 3808 3809 if (mac_addr) 3810 ether_addr_copy(cmd->mac, mac_addr); 3811 3812 cmd->etype = cpu_to_le16(ethtype); 3813 cmd->flags = cpu_to_le16(flags); 3814 cmd->seid = cpu_to_le16(vsi_seid); 3815 3816 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3817 3818 if (!status && stats) { 3819 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 3820 stats->etype_used = le16_to_cpu(resp->etype_used); 3821 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 3822 stats->etype_free = le16_to_cpu(resp->etype_free); 3823 } 3824 3825 return status; 3826 } 3827 3828 /** 3829 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 3830 * @hw: pointer to the hw struct 3831 * @seid: VSI seid to add ethertype filter from 3832 **/ 3833 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 3834 u16 seid) 3835 { 3836 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 3837 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 3838 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 3839 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 3840 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 3841 int status; 3842 3843 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 3844 seid, 0, true, NULL, 3845 NULL); 3846 if (status) 3847 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 3848 } 3849 3850 /** 3851 * i40e_aq_alternate_read 3852 * @hw: pointer to the hardware structure 3853 * @reg_addr0: address of first dword to be read 3854 * @reg_val0: pointer for data read from 'reg_addr0' 3855 * @reg_addr1: address of second dword to be read 3856 * @reg_val1: pointer for data read from 'reg_addr1' 3857 * 3858 * Read one or two dwords from alternate structure. Fields are indicated 3859 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 3860 * is not passed then only register at 'reg_addr0' is read. 3861 * 3862 **/ 3863 static int i40e_aq_alternate_read(struct i40e_hw *hw, 3864 u32 reg_addr0, u32 *reg_val0, 3865 u32 reg_addr1, u32 *reg_val1) 3866 { 3867 struct i40e_aq_desc desc; 3868 struct i40e_aqc_alternate_write *cmd_resp = 3869 (struct i40e_aqc_alternate_write *)&desc.params.raw; 3870 int status; 3871 3872 if (!reg_val0) 3873 return -EINVAL; 3874 3875 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 3876 cmd_resp->address0 = cpu_to_le32(reg_addr0); 3877 cmd_resp->address1 = cpu_to_le32(reg_addr1); 3878 3879 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3880 3881 if (!status) { 3882 *reg_val0 = le32_to_cpu(cmd_resp->data0); 3883 3884 if (reg_val1) 3885 *reg_val1 = le32_to_cpu(cmd_resp->data1); 3886 } 3887 3888 return status; 3889 } 3890 3891 /** 3892 * i40e_aq_suspend_port_tx 3893 * @hw: pointer to the hardware structure 3894 * @seid: port seid 3895 * @cmd_details: pointer to command details structure or NULL 3896 * 3897 * Suspend port's Tx traffic 3898 **/ 3899 int i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, 3900 struct i40e_asq_cmd_details *cmd_details) 3901 { 3902 struct i40e_aqc_tx_sched_ind *cmd; 3903 struct i40e_aq_desc desc; 3904 int status; 3905 3906 cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3907 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx); 3908 cmd->vsi_seid = cpu_to_le16(seid); 3909 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3910 3911 return status; 3912 } 3913 3914 /** 3915 * i40e_aq_resume_port_tx 3916 * @hw: pointer to the hardware structure 3917 * @cmd_details: pointer to command details structure or NULL 3918 * 3919 * Resume port's Tx traffic 3920 **/ 3921 int i40e_aq_resume_port_tx(struct i40e_hw *hw, 3922 struct i40e_asq_cmd_details *cmd_details) 3923 { 3924 struct i40e_aq_desc desc; 3925 int status; 3926 3927 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 3928 3929 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3930 3931 return status; 3932 } 3933 3934 /** 3935 * i40e_set_pci_config_data - store PCI bus info 3936 * @hw: pointer to hardware structure 3937 * @link_status: the link status word from PCI config space 3938 * 3939 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 3940 **/ 3941 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 3942 { 3943 hw->bus.type = i40e_bus_type_pci_express; 3944 3945 switch (link_status & PCI_EXP_LNKSTA_NLW) { 3946 case PCI_EXP_LNKSTA_NLW_X1: 3947 hw->bus.width = i40e_bus_width_pcie_x1; 3948 break; 3949 case PCI_EXP_LNKSTA_NLW_X2: 3950 hw->bus.width = i40e_bus_width_pcie_x2; 3951 break; 3952 case PCI_EXP_LNKSTA_NLW_X4: 3953 hw->bus.width = i40e_bus_width_pcie_x4; 3954 break; 3955 case PCI_EXP_LNKSTA_NLW_X8: 3956 hw->bus.width = i40e_bus_width_pcie_x8; 3957 break; 3958 default: 3959 hw->bus.width = i40e_bus_width_unknown; 3960 break; 3961 } 3962 3963 switch (link_status & PCI_EXP_LNKSTA_CLS) { 3964 case PCI_EXP_LNKSTA_CLS_2_5GB: 3965 hw->bus.speed = i40e_bus_speed_2500; 3966 break; 3967 case PCI_EXP_LNKSTA_CLS_5_0GB: 3968 hw->bus.speed = i40e_bus_speed_5000; 3969 break; 3970 case PCI_EXP_LNKSTA_CLS_8_0GB: 3971 hw->bus.speed = i40e_bus_speed_8000; 3972 break; 3973 default: 3974 hw->bus.speed = i40e_bus_speed_unknown; 3975 break; 3976 } 3977 } 3978 3979 /** 3980 * i40e_aq_debug_dump 3981 * @hw: pointer to the hardware structure 3982 * @cluster_id: specific cluster to dump 3983 * @table_id: table id within cluster 3984 * @start_index: index of line in the block to read 3985 * @buff_size: dump buffer size 3986 * @buff: dump buffer 3987 * @ret_buff_size: actual buffer size returned 3988 * @ret_next_table: next block to read 3989 * @ret_next_index: next index to read 3990 * @cmd_details: pointer to command details structure or NULL 3991 * 3992 * Dump internal FW/HW data for debug purposes. 3993 * 3994 **/ 3995 int i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 3996 u8 table_id, u32 start_index, u16 buff_size, 3997 void *buff, u16 *ret_buff_size, 3998 u8 *ret_next_table, u32 *ret_next_index, 3999 struct i40e_asq_cmd_details *cmd_details) 4000 { 4001 struct i40e_aq_desc desc; 4002 struct i40e_aqc_debug_dump_internals *cmd = 4003 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4004 struct i40e_aqc_debug_dump_internals *resp = 4005 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4006 int status; 4007 4008 if (buff_size == 0 || !buff) 4009 return -EINVAL; 4010 4011 i40e_fill_default_direct_cmd_desc(&desc, 4012 i40e_aqc_opc_debug_dump_internals); 4013 /* Indirect Command */ 4014 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4015 if (buff_size > I40E_AQ_LARGE_BUF) 4016 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4017 4018 cmd->cluster_id = cluster_id; 4019 cmd->table_id = table_id; 4020 cmd->idx = cpu_to_le32(start_index); 4021 4022 desc.datalen = cpu_to_le16(buff_size); 4023 4024 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4025 if (!status) { 4026 if (ret_buff_size) 4027 *ret_buff_size = le16_to_cpu(desc.datalen); 4028 if (ret_next_table) 4029 *ret_next_table = resp->table_id; 4030 if (ret_next_index) 4031 *ret_next_index = le32_to_cpu(resp->idx); 4032 } 4033 4034 return status; 4035 } 4036 4037 /** 4038 * i40e_read_bw_from_alt_ram 4039 * @hw: pointer to the hardware structure 4040 * @max_bw: pointer for max_bw read 4041 * @min_bw: pointer for min_bw read 4042 * @min_valid: pointer for bool that is true if min_bw is a valid value 4043 * @max_valid: pointer for bool that is true if max_bw is a valid value 4044 * 4045 * Read bw from the alternate ram for the given pf 4046 **/ 4047 int i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4048 u32 *max_bw, u32 *min_bw, 4049 bool *min_valid, bool *max_valid) 4050 { 4051 u32 max_bw_addr, min_bw_addr; 4052 int status; 4053 4054 /* Calculate the address of the min/max bw registers */ 4055 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4056 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4057 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4058 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4059 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4060 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4061 4062 /* Read the bandwidths from alt ram */ 4063 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4064 min_bw_addr, min_bw); 4065 4066 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4067 *min_valid = true; 4068 else 4069 *min_valid = false; 4070 4071 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4072 *max_valid = true; 4073 else 4074 *max_valid = false; 4075 4076 return status; 4077 } 4078 4079 /** 4080 * i40e_aq_configure_partition_bw 4081 * @hw: pointer to the hardware structure 4082 * @bw_data: Buffer holding valid pfs and bw limits 4083 * @cmd_details: pointer to command details 4084 * 4085 * Configure partitions guaranteed/max bw 4086 **/ 4087 int 4088 i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4089 struct i40e_aqc_configure_partition_bw_data *bw_data, 4090 struct i40e_asq_cmd_details *cmd_details) 4091 { 4092 u16 bwd_size = sizeof(*bw_data); 4093 struct i40e_aq_desc desc; 4094 int status; 4095 4096 i40e_fill_default_direct_cmd_desc(&desc, 4097 i40e_aqc_opc_configure_partition_bw); 4098 4099 /* Indirect command */ 4100 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4101 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4102 4103 if (bwd_size > I40E_AQ_LARGE_BUF) 4104 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4105 4106 desc.datalen = cpu_to_le16(bwd_size); 4107 4108 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4109 cmd_details); 4110 4111 return status; 4112 } 4113 4114 /** 4115 * i40e_read_phy_register_clause22 4116 * @hw: pointer to the HW structure 4117 * @reg: register address in the page 4118 * @phy_addr: PHY address on MDIO interface 4119 * @value: PHY register value 4120 * 4121 * Reads specified PHY register value 4122 **/ 4123 int i40e_read_phy_register_clause22(struct i40e_hw *hw, 4124 u16 reg, u8 phy_addr, u16 *value) 4125 { 4126 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4127 int status = -EIO; 4128 u32 command = 0; 4129 u16 retry = 1000; 4130 4131 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4132 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4133 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4134 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4135 (I40E_GLGEN_MSCA_MDICMD_MASK); 4136 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4137 do { 4138 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4139 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4140 status = 0; 4141 break; 4142 } 4143 udelay(10); 4144 retry--; 4145 } while (retry); 4146 4147 if (status) { 4148 i40e_debug(hw, I40E_DEBUG_PHY, 4149 "PHY: Can't write command to external PHY.\n"); 4150 } else { 4151 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4152 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4153 } 4154 4155 return status; 4156 } 4157 4158 /** 4159 * i40e_write_phy_register_clause22 4160 * @hw: pointer to the HW structure 4161 * @reg: register address in the page 4162 * @phy_addr: PHY address on MDIO interface 4163 * @value: PHY register value 4164 * 4165 * Writes specified PHY register value 4166 **/ 4167 int i40e_write_phy_register_clause22(struct i40e_hw *hw, 4168 u16 reg, u8 phy_addr, u16 value) 4169 { 4170 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4171 int status = -EIO; 4172 u32 command = 0; 4173 u16 retry = 1000; 4174 4175 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4176 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4177 4178 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4179 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4180 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4181 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4182 (I40E_GLGEN_MSCA_MDICMD_MASK); 4183 4184 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4185 do { 4186 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4187 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4188 status = 0; 4189 break; 4190 } 4191 udelay(10); 4192 retry--; 4193 } while (retry); 4194 4195 return status; 4196 } 4197 4198 /** 4199 * i40e_read_phy_register_clause45 4200 * @hw: pointer to the HW structure 4201 * @page: registers page number 4202 * @reg: register address in the page 4203 * @phy_addr: PHY address on MDIO interface 4204 * @value: PHY register value 4205 * 4206 * Reads specified PHY register value 4207 **/ 4208 int i40e_read_phy_register_clause45(struct i40e_hw *hw, 4209 u8 page, u16 reg, u8 phy_addr, u16 *value) 4210 { 4211 u8 port_num = hw->func_caps.mdio_port_num; 4212 int status = -EIO; 4213 u32 command = 0; 4214 u16 retry = 1000; 4215 4216 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4217 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4218 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4219 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4220 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4221 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4222 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4223 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4224 do { 4225 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4226 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4227 status = 0; 4228 break; 4229 } 4230 usleep_range(10, 20); 4231 retry--; 4232 } while (retry); 4233 4234 if (status) { 4235 i40e_debug(hw, I40E_DEBUG_PHY, 4236 "PHY: Can't write command to external PHY.\n"); 4237 goto phy_read_end; 4238 } 4239 4240 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4241 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4242 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4243 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4244 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4245 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4246 status = -EIO; 4247 retry = 1000; 4248 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4249 do { 4250 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4251 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4252 status = 0; 4253 break; 4254 } 4255 usleep_range(10, 20); 4256 retry--; 4257 } while (retry); 4258 4259 if (!status) { 4260 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4261 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4262 } else { 4263 i40e_debug(hw, I40E_DEBUG_PHY, 4264 "PHY: Can't read register value from external PHY.\n"); 4265 } 4266 4267 phy_read_end: 4268 return status; 4269 } 4270 4271 /** 4272 * i40e_write_phy_register_clause45 4273 * @hw: pointer to the HW structure 4274 * @page: registers page number 4275 * @reg: register address in the page 4276 * @phy_addr: PHY address on MDIO interface 4277 * @value: PHY register value 4278 * 4279 * Writes value to specified PHY register 4280 **/ 4281 int i40e_write_phy_register_clause45(struct i40e_hw *hw, 4282 u8 page, u16 reg, u8 phy_addr, u16 value) 4283 { 4284 u8 port_num = hw->func_caps.mdio_port_num; 4285 int status = -EIO; 4286 u16 retry = 1000; 4287 u32 command = 0; 4288 4289 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4290 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4291 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4292 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4293 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4294 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4295 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4296 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4297 do { 4298 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4299 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4300 status = 0; 4301 break; 4302 } 4303 usleep_range(10, 20); 4304 retry--; 4305 } while (retry); 4306 if (status) { 4307 i40e_debug(hw, I40E_DEBUG_PHY, 4308 "PHY: Can't write command to external PHY.\n"); 4309 goto phy_write_end; 4310 } 4311 4312 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4313 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4314 4315 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4316 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4317 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4318 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4319 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4320 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4321 status = -EIO; 4322 retry = 1000; 4323 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4324 do { 4325 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4326 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4327 status = 0; 4328 break; 4329 } 4330 usleep_range(10, 20); 4331 retry--; 4332 } while (retry); 4333 4334 phy_write_end: 4335 return status; 4336 } 4337 4338 /** 4339 * i40e_get_phy_address 4340 * @hw: pointer to the HW structure 4341 * @dev_num: PHY port num that address we want 4342 * 4343 * Gets PHY address for current port 4344 **/ 4345 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4346 { 4347 u8 port_num = hw->func_caps.mdio_port_num; 4348 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4349 4350 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4351 } 4352 4353 /** 4354 * i40e_led_get_reg - read LED register 4355 * @hw: pointer to the HW structure 4356 * @led_addr: LED register address 4357 * @reg_val: read register value 4358 **/ 4359 static int i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 4360 u32 *reg_val) 4361 { 4362 u8 phy_addr = 0; 4363 u8 port_num; 4364 int status; 4365 u32 i; 4366 4367 *reg_val = 0; 4368 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4369 status = 4370 i40e_aq_get_phy_register(hw, 4371 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4372 I40E_PHY_COM_REG_PAGE, true, 4373 I40E_PHY_LED_PROV_REG_1, 4374 reg_val, NULL); 4375 } else { 4376 i = rd32(hw, I40E_PFGEN_PORTNUM); 4377 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4378 phy_addr = i40e_get_phy_address(hw, port_num); 4379 status = i40e_read_phy_register_clause45(hw, 4380 I40E_PHY_COM_REG_PAGE, 4381 led_addr, phy_addr, 4382 (u16 *)reg_val); 4383 } 4384 return status; 4385 } 4386 4387 /** 4388 * i40e_led_set_reg - write LED register 4389 * @hw: pointer to the HW structure 4390 * @led_addr: LED register address 4391 * @reg_val: register value to write 4392 **/ 4393 static int i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 4394 u32 reg_val) 4395 { 4396 u8 phy_addr = 0; 4397 u8 port_num; 4398 int status; 4399 u32 i; 4400 4401 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4402 status = 4403 i40e_aq_set_phy_register(hw, 4404 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4405 I40E_PHY_COM_REG_PAGE, true, 4406 I40E_PHY_LED_PROV_REG_1, 4407 reg_val, NULL); 4408 } else { 4409 i = rd32(hw, I40E_PFGEN_PORTNUM); 4410 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4411 phy_addr = i40e_get_phy_address(hw, port_num); 4412 status = i40e_write_phy_register_clause45(hw, 4413 I40E_PHY_COM_REG_PAGE, 4414 led_addr, phy_addr, 4415 (u16)reg_val); 4416 } 4417 4418 return status; 4419 } 4420 4421 /** 4422 * i40e_led_get_phy - return current on/off mode 4423 * @hw: pointer to the hw struct 4424 * @led_addr: address of led register to use 4425 * @val: original value of register to use 4426 * 4427 **/ 4428 int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4429 u16 *val) 4430 { 4431 u16 gpio_led_port; 4432 u8 phy_addr = 0; 4433 u32 reg_val_aq; 4434 int status = 0; 4435 u16 temp_addr; 4436 u16 reg_val; 4437 u8 port_num; 4438 u32 i; 4439 4440 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4441 status = 4442 i40e_aq_get_phy_register(hw, 4443 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4444 I40E_PHY_COM_REG_PAGE, true, 4445 I40E_PHY_LED_PROV_REG_1, 4446 ®_val_aq, NULL); 4447 if (status == 0) 4448 *val = (u16)reg_val_aq; 4449 return status; 4450 } 4451 temp_addr = I40E_PHY_LED_PROV_REG_1; 4452 i = rd32(hw, I40E_PFGEN_PORTNUM); 4453 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4454 phy_addr = i40e_get_phy_address(hw, port_num); 4455 4456 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4457 temp_addr++) { 4458 status = i40e_read_phy_register_clause45(hw, 4459 I40E_PHY_COM_REG_PAGE, 4460 temp_addr, phy_addr, 4461 ®_val); 4462 if (status) 4463 return status; 4464 *val = reg_val; 4465 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4466 *led_addr = temp_addr; 4467 break; 4468 } 4469 } 4470 return status; 4471 } 4472 4473 /** 4474 * i40e_led_set_phy 4475 * @hw: pointer to the HW structure 4476 * @on: true or false 4477 * @led_addr: address of led register to use 4478 * @mode: original val plus bit for set or ignore 4479 * 4480 * Set led's on or off when controlled by the PHY 4481 * 4482 **/ 4483 int i40e_led_set_phy(struct i40e_hw *hw, bool on, 4484 u16 led_addr, u32 mode) 4485 { 4486 u32 led_ctl = 0; 4487 u32 led_reg = 0; 4488 int status = 0; 4489 4490 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4491 if (status) 4492 return status; 4493 led_ctl = led_reg; 4494 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4495 led_reg = 0; 4496 status = i40e_led_set_reg(hw, led_addr, led_reg); 4497 if (status) 4498 return status; 4499 } 4500 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4501 if (status) 4502 goto restore_config; 4503 if (on) 4504 led_reg = I40E_PHY_LED_MANUAL_ON; 4505 else 4506 led_reg = 0; 4507 4508 status = i40e_led_set_reg(hw, led_addr, led_reg); 4509 if (status) 4510 goto restore_config; 4511 if (mode & I40E_PHY_LED_MODE_ORIG) { 4512 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 4513 status = i40e_led_set_reg(hw, led_addr, led_ctl); 4514 } 4515 return status; 4516 4517 restore_config: 4518 status = i40e_led_set_reg(hw, led_addr, led_ctl); 4519 return status; 4520 } 4521 4522 /** 4523 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 4524 * @hw: pointer to the hw struct 4525 * @reg_addr: register address 4526 * @reg_val: ptr to register value 4527 * @cmd_details: pointer to command details structure or NULL 4528 * 4529 * Use the firmware to read the Rx control register, 4530 * especially useful if the Rx unit is under heavy pressure 4531 **/ 4532 int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 4533 u32 reg_addr, u32 *reg_val, 4534 struct i40e_asq_cmd_details *cmd_details) 4535 { 4536 struct i40e_aq_desc desc; 4537 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 4538 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 4539 int status; 4540 4541 if (!reg_val) 4542 return -EINVAL; 4543 4544 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 4545 4546 cmd_resp->address = cpu_to_le32(reg_addr); 4547 4548 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4549 4550 if (status == 0) 4551 *reg_val = le32_to_cpu(cmd_resp->value); 4552 4553 return status; 4554 } 4555 4556 /** 4557 * i40e_read_rx_ctl - read from an Rx control register 4558 * @hw: pointer to the hw struct 4559 * @reg_addr: register address 4560 **/ 4561 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 4562 { 4563 bool use_register = false; 4564 int status = 0; 4565 int retry = 5; 4566 u32 val = 0; 4567 4568 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722) 4569 use_register = true; 4570 4571 if (!use_register) { 4572 do_retry: 4573 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 4574 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 4575 usleep_range(1000, 2000); 4576 retry--; 4577 goto do_retry; 4578 } 4579 } 4580 4581 /* if the AQ access failed, try the old-fashioned way */ 4582 if (status || use_register) 4583 val = rd32(hw, reg_addr); 4584 4585 return val; 4586 } 4587 4588 /** 4589 * i40e_aq_rx_ctl_write_register 4590 * @hw: pointer to the hw struct 4591 * @reg_addr: register address 4592 * @reg_val: register value 4593 * @cmd_details: pointer to command details structure or NULL 4594 * 4595 * Use the firmware to write to an Rx control register, 4596 * especially useful if the Rx unit is under heavy pressure 4597 **/ 4598 int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 4599 u32 reg_addr, u32 reg_val, 4600 struct i40e_asq_cmd_details *cmd_details) 4601 { 4602 struct i40e_aq_desc desc; 4603 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 4604 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 4605 int status; 4606 4607 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 4608 4609 cmd->address = cpu_to_le32(reg_addr); 4610 cmd->value = cpu_to_le32(reg_val); 4611 4612 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4613 4614 return status; 4615 } 4616 4617 /** 4618 * i40e_write_rx_ctl - write to an Rx control register 4619 * @hw: pointer to the hw struct 4620 * @reg_addr: register address 4621 * @reg_val: register value 4622 **/ 4623 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 4624 { 4625 bool use_register = false; 4626 int status = 0; 4627 int retry = 5; 4628 4629 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722) 4630 use_register = true; 4631 4632 if (!use_register) { 4633 do_retry: 4634 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 4635 reg_val, NULL); 4636 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 4637 usleep_range(1000, 2000); 4638 retry--; 4639 goto do_retry; 4640 } 4641 } 4642 4643 /* if the AQ access failed, try the old-fashioned way */ 4644 if (status || use_register) 4645 wr32(hw, reg_addr, reg_val); 4646 } 4647 4648 /** 4649 * i40e_mdio_if_number_selection - MDIO I/F number selection 4650 * @hw: pointer to the hw struct 4651 * @set_mdio: use MDIO I/F number specified by mdio_num 4652 * @mdio_num: MDIO I/F number 4653 * @cmd: pointer to PHY Register command structure 4654 **/ 4655 static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, 4656 u8 mdio_num, 4657 struct i40e_aqc_phy_register_access *cmd) 4658 { 4659 if (!set_mdio || 4660 cmd->phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL) 4661 return; 4662 4663 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps)) { 4664 cmd->cmd_flags |= 4665 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 4666 FIELD_PREP(I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK, 4667 mdio_num); 4668 } else { 4669 i40e_debug(hw, I40E_DEBUG_PHY, "MDIO I/F number selection not supported by current FW version.\n"); 4670 } 4671 } 4672 4673 /** 4674 * i40e_aq_set_phy_register_ext 4675 * @hw: pointer to the hw struct 4676 * @phy_select: select which phy should be accessed 4677 * @dev_addr: PHY device address 4678 * @page_change: flag to indicate if phy page should be updated 4679 * @set_mdio: use MDIO I/F number specified by mdio_num 4680 * @mdio_num: MDIO I/F number 4681 * @reg_addr: PHY register address 4682 * @reg_val: new register value 4683 * @cmd_details: pointer to command details structure or NULL 4684 * 4685 * Write the external PHY register. 4686 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 4687 * may use simple wrapper i40e_aq_set_phy_register. 4688 **/ 4689 int i40e_aq_set_phy_register_ext(struct i40e_hw *hw, 4690 u8 phy_select, u8 dev_addr, bool page_change, 4691 bool set_mdio, u8 mdio_num, 4692 u32 reg_addr, u32 reg_val, 4693 struct i40e_asq_cmd_details *cmd_details) 4694 { 4695 struct i40e_aq_desc desc; 4696 struct i40e_aqc_phy_register_access *cmd = 4697 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 4698 int status; 4699 4700 i40e_fill_default_direct_cmd_desc(&desc, 4701 i40e_aqc_opc_set_phy_register); 4702 4703 cmd->phy_interface = phy_select; 4704 cmd->dev_address = dev_addr; 4705 cmd->reg_address = cpu_to_le32(reg_addr); 4706 cmd->reg_value = cpu_to_le32(reg_val); 4707 4708 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 4709 4710 if (!page_change) 4711 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 4712 4713 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4714 4715 return status; 4716 } 4717 4718 /** 4719 * i40e_aq_get_phy_register_ext 4720 * @hw: pointer to the hw struct 4721 * @phy_select: select which phy should be accessed 4722 * @dev_addr: PHY device address 4723 * @page_change: flag to indicate if phy page should be updated 4724 * @set_mdio: use MDIO I/F number specified by mdio_num 4725 * @mdio_num: MDIO I/F number 4726 * @reg_addr: PHY register address 4727 * @reg_val: read register value 4728 * @cmd_details: pointer to command details structure or NULL 4729 * 4730 * Read the external PHY register. 4731 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 4732 * may use simple wrapper i40e_aq_get_phy_register. 4733 **/ 4734 int i40e_aq_get_phy_register_ext(struct i40e_hw *hw, 4735 u8 phy_select, u8 dev_addr, bool page_change, 4736 bool set_mdio, u8 mdio_num, 4737 u32 reg_addr, u32 *reg_val, 4738 struct i40e_asq_cmd_details *cmd_details) 4739 { 4740 struct i40e_aq_desc desc; 4741 struct i40e_aqc_phy_register_access *cmd = 4742 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 4743 int status; 4744 4745 i40e_fill_default_direct_cmd_desc(&desc, 4746 i40e_aqc_opc_get_phy_register); 4747 4748 cmd->phy_interface = phy_select; 4749 cmd->dev_address = dev_addr; 4750 cmd->reg_address = cpu_to_le32(reg_addr); 4751 4752 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 4753 4754 if (!page_change) 4755 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 4756 4757 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4758 if (!status) 4759 *reg_val = le32_to_cpu(cmd->reg_value); 4760 4761 return status; 4762 } 4763 4764 /** 4765 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 4766 * @hw: pointer to the hw struct 4767 * @buff: command buffer (size in bytes = buff_size) 4768 * @buff_size: buffer size in bytes 4769 * @track_id: package tracking id 4770 * @error_offset: returns error offset 4771 * @error_info: returns error information 4772 * @cmd_details: pointer to command details structure or NULL 4773 **/ 4774 int i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 4775 u16 buff_size, u32 track_id, 4776 u32 *error_offset, u32 *error_info, 4777 struct i40e_asq_cmd_details *cmd_details) 4778 { 4779 struct i40e_aq_desc desc; 4780 struct i40e_aqc_write_personalization_profile *cmd = 4781 (struct i40e_aqc_write_personalization_profile *) 4782 &desc.params.raw; 4783 struct i40e_aqc_write_ddp_resp *resp; 4784 int status; 4785 4786 i40e_fill_default_direct_cmd_desc(&desc, 4787 i40e_aqc_opc_write_personalization_profile); 4788 4789 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 4790 if (buff_size > I40E_AQ_LARGE_BUF) 4791 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4792 4793 desc.datalen = cpu_to_le16(buff_size); 4794 4795 cmd->profile_track_id = cpu_to_le32(track_id); 4796 4797 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4798 if (!status) { 4799 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 4800 if (error_offset) 4801 *error_offset = le32_to_cpu(resp->error_offset); 4802 if (error_info) 4803 *error_info = le32_to_cpu(resp->error_info); 4804 } 4805 4806 return status; 4807 } 4808 4809 /** 4810 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 4811 * @hw: pointer to the hw struct 4812 * @buff: command buffer (size in bytes = buff_size) 4813 * @buff_size: buffer size in bytes 4814 * @flags: AdminQ command flags 4815 * @cmd_details: pointer to command details structure or NULL 4816 **/ 4817 int i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 4818 u16 buff_size, u8 flags, 4819 struct i40e_asq_cmd_details *cmd_details) 4820 { 4821 struct i40e_aq_desc desc; 4822 struct i40e_aqc_get_applied_profiles *cmd = 4823 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 4824 int status; 4825 4826 i40e_fill_default_direct_cmd_desc(&desc, 4827 i40e_aqc_opc_get_personalization_profile_list); 4828 4829 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4830 if (buff_size > I40E_AQ_LARGE_BUF) 4831 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4832 desc.datalen = cpu_to_le16(buff_size); 4833 4834 cmd->flags = flags; 4835 4836 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4837 4838 return status; 4839 } 4840 4841 /** 4842 * i40e_find_segment_in_package 4843 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 4844 * @pkg_hdr: pointer to the package header to be searched 4845 * 4846 * This function searches a package file for a particular segment type. On 4847 * success it returns a pointer to the segment header, otherwise it will 4848 * return NULL. 4849 **/ 4850 struct i40e_generic_seg_header * 4851 i40e_find_segment_in_package(u32 segment_type, 4852 struct i40e_package_header *pkg_hdr) 4853 { 4854 struct i40e_generic_seg_header *segment; 4855 u32 i; 4856 4857 /* Search all package segments for the requested segment type */ 4858 for (i = 0; i < pkg_hdr->segment_count; i++) { 4859 segment = 4860 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 4861 pkg_hdr->segment_offset[i]); 4862 4863 if (segment->type == segment_type) 4864 return segment; 4865 } 4866 4867 return NULL; 4868 } 4869 4870 /* Get section table in profile */ 4871 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 4872 do { \ 4873 struct i40e_profile_segment *p = (profile); \ 4874 u32 count; \ 4875 u32 *nvm; \ 4876 count = p->device_table_count; \ 4877 nvm = (u32 *)&p->device_table[count]; \ 4878 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 4879 } while (0) 4880 4881 /* Get section header in profile */ 4882 #define I40E_SECTION_HEADER(profile, offset) \ 4883 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 4884 4885 /** 4886 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 4887 * @hw: pointer to the hw struct 4888 * @aq: command buffer containing all data to execute AQ 4889 **/ 4890 static int i40e_ddp_exec_aq_section(struct i40e_hw *hw, 4891 struct i40e_profile_aq_section *aq) 4892 { 4893 struct i40e_aq_desc desc; 4894 u8 *msg = NULL; 4895 u16 msglen; 4896 int status; 4897 4898 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 4899 desc.flags |= cpu_to_le16(aq->flags); 4900 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw)); 4901 4902 msglen = aq->datalen; 4903 if (msglen) { 4904 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 4905 I40E_AQ_FLAG_RD)); 4906 if (msglen > I40E_AQ_LARGE_BUF) 4907 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4908 desc.datalen = cpu_to_le16(msglen); 4909 msg = &aq->data[0]; 4910 } 4911 4912 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 4913 4914 if (status) { 4915 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4916 "unable to exec DDP AQ opcode %u, error %d\n", 4917 aq->opcode, status); 4918 return status; 4919 } 4920 4921 /* copy returned desc to aq_buf */ 4922 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw)); 4923 4924 return 0; 4925 } 4926 4927 /** 4928 * i40e_validate_profile 4929 * @hw: pointer to the hardware structure 4930 * @profile: pointer to the profile segment of the package to be validated 4931 * @track_id: package tracking id 4932 * @rollback: flag if the profile is for rollback. 4933 * 4934 * Validates supported devices and profile's sections. 4935 */ 4936 static int 4937 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 4938 u32 track_id, bool rollback) 4939 { 4940 struct i40e_profile_section_header *sec = NULL; 4941 struct i40e_section_table *sec_tbl; 4942 u32 vendor_dev_id; 4943 int status = 0; 4944 u32 dev_cnt; 4945 u32 sec_off; 4946 u32 i; 4947 4948 if (track_id == I40E_DDP_TRACKID_INVALID) { 4949 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 4950 return -EOPNOTSUPP; 4951 } 4952 4953 dev_cnt = profile->device_table_count; 4954 for (i = 0; i < dev_cnt; i++) { 4955 vendor_dev_id = profile->device_table[i].vendor_dev_id; 4956 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL && 4957 hw->device_id == (vendor_dev_id & 0xFFFF)) 4958 break; 4959 } 4960 if (dev_cnt && i == dev_cnt) { 4961 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4962 "Device doesn't support DDP\n"); 4963 return -ENODEV; 4964 } 4965 4966 I40E_SECTION_TABLE(profile, sec_tbl); 4967 4968 /* Validate sections types */ 4969 for (i = 0; i < sec_tbl->section_count; i++) { 4970 sec_off = sec_tbl->section_offset[i]; 4971 sec = I40E_SECTION_HEADER(profile, sec_off); 4972 if (rollback) { 4973 if (sec->section.type == SECTION_TYPE_MMIO || 4974 sec->section.type == SECTION_TYPE_AQ || 4975 sec->section.type == SECTION_TYPE_RB_AQ) { 4976 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4977 "Not a roll-back package\n"); 4978 return -EOPNOTSUPP; 4979 } 4980 } else { 4981 if (sec->section.type == SECTION_TYPE_RB_AQ || 4982 sec->section.type == SECTION_TYPE_RB_MMIO) { 4983 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4984 "Not an original package\n"); 4985 return -EOPNOTSUPP; 4986 } 4987 } 4988 } 4989 4990 return status; 4991 } 4992 4993 /** 4994 * i40e_write_profile 4995 * @hw: pointer to the hardware structure 4996 * @profile: pointer to the profile segment of the package to be downloaded 4997 * @track_id: package tracking id 4998 * 4999 * Handles the download of a complete package. 5000 */ 5001 int 5002 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5003 u32 track_id) 5004 { 5005 struct i40e_profile_section_header *sec = NULL; 5006 struct i40e_profile_aq_section *ddp_aq; 5007 struct i40e_section_table *sec_tbl; 5008 u32 offset = 0, info = 0; 5009 u32 section_size = 0; 5010 int status = 0; 5011 u32 sec_off; 5012 u32 i; 5013 5014 status = i40e_validate_profile(hw, profile, track_id, false); 5015 if (status) 5016 return status; 5017 5018 I40E_SECTION_TABLE(profile, sec_tbl); 5019 5020 for (i = 0; i < sec_tbl->section_count; i++) { 5021 sec_off = sec_tbl->section_offset[i]; 5022 sec = I40E_SECTION_HEADER(profile, sec_off); 5023 /* Process generic admin command */ 5024 if (sec->section.type == SECTION_TYPE_AQ) { 5025 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 5026 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 5027 if (status) { 5028 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5029 "Failed to execute aq: section %d, opcode %u\n", 5030 i, ddp_aq->opcode); 5031 break; 5032 } 5033 sec->section.type = SECTION_TYPE_RB_AQ; 5034 } 5035 5036 /* Skip any non-mmio sections */ 5037 if (sec->section.type != SECTION_TYPE_MMIO) 5038 continue; 5039 5040 section_size = sec->section.size + 5041 sizeof(struct i40e_profile_section_header); 5042 5043 /* Write MMIO section */ 5044 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5045 track_id, &offset, &info, NULL); 5046 if (status) { 5047 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5048 "Failed to write profile: section %d, offset %d, info %d\n", 5049 i, offset, info); 5050 break; 5051 } 5052 } 5053 return status; 5054 } 5055 5056 /** 5057 * i40e_rollback_profile 5058 * @hw: pointer to the hardware structure 5059 * @profile: pointer to the profile segment of the package to be removed 5060 * @track_id: package tracking id 5061 * 5062 * Rolls back previously loaded package. 5063 */ 5064 int 5065 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5066 u32 track_id) 5067 { 5068 struct i40e_profile_section_header *sec = NULL; 5069 struct i40e_section_table *sec_tbl; 5070 u32 offset = 0, info = 0; 5071 u32 section_size = 0; 5072 int status = 0; 5073 u32 sec_off; 5074 int i; 5075 5076 status = i40e_validate_profile(hw, profile, track_id, true); 5077 if (status) 5078 return status; 5079 5080 I40E_SECTION_TABLE(profile, sec_tbl); 5081 5082 /* For rollback write sections in reverse */ 5083 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 5084 sec_off = sec_tbl->section_offset[i]; 5085 sec = I40E_SECTION_HEADER(profile, sec_off); 5086 5087 /* Skip any non-rollback sections */ 5088 if (sec->section.type != SECTION_TYPE_RB_MMIO) 5089 continue; 5090 5091 section_size = sec->section.size + 5092 sizeof(struct i40e_profile_section_header); 5093 5094 /* Write roll-back MMIO section */ 5095 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5096 track_id, &offset, &info, NULL); 5097 if (status) { 5098 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5099 "Failed to write profile: section %d, offset %d, info %d\n", 5100 i, offset, info); 5101 break; 5102 } 5103 } 5104 return status; 5105 } 5106 5107 /** 5108 * i40e_aq_add_cloud_filters 5109 * @hw: pointer to the hardware structure 5110 * @seid: VSI seid to add cloud filters from 5111 * @filters: Buffer which contains the filters to be added 5112 * @filter_count: number of filters contained in the buffer 5113 * 5114 * Set the cloud filters for a given VSI. The contents of the 5115 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5116 * of the function. 5117 * 5118 **/ 5119 int 5120 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5121 struct i40e_aqc_cloud_filters_element_data *filters, 5122 u8 filter_count) 5123 { 5124 struct i40e_aq_desc desc; 5125 struct i40e_aqc_add_remove_cloud_filters *cmd = 5126 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5127 u16 buff_len; 5128 int status; 5129 5130 i40e_fill_default_direct_cmd_desc(&desc, 5131 i40e_aqc_opc_add_cloud_filters); 5132 5133 buff_len = filter_count * sizeof(*filters); 5134 desc.datalen = cpu_to_le16(buff_len); 5135 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5136 cmd->num_filters = filter_count; 5137 cmd->seid = cpu_to_le16(seid); 5138 5139 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5140 5141 return status; 5142 } 5143 5144 /** 5145 * i40e_aq_add_cloud_filters_bb 5146 * @hw: pointer to the hardware structure 5147 * @seid: VSI seid to add cloud filters from 5148 * @filters: Buffer which contains the filters in big buffer to be added 5149 * @filter_count: number of filters contained in the buffer 5150 * 5151 * Set the big buffer cloud filters for a given VSI. The contents of the 5152 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5153 * function. 5154 * 5155 **/ 5156 int 5157 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5158 struct i40e_aqc_cloud_filters_element_bb *filters, 5159 u8 filter_count) 5160 { 5161 struct i40e_aq_desc desc; 5162 struct i40e_aqc_add_remove_cloud_filters *cmd = 5163 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5164 u16 buff_len; 5165 int status; 5166 int i; 5167 5168 i40e_fill_default_direct_cmd_desc(&desc, 5169 i40e_aqc_opc_add_cloud_filters); 5170 5171 buff_len = filter_count * sizeof(*filters); 5172 desc.datalen = cpu_to_le16(buff_len); 5173 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5174 cmd->num_filters = filter_count; 5175 cmd->seid = cpu_to_le16(seid); 5176 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5177 5178 for (i = 0; i < filter_count; i++) { 5179 u16 tnl_type; 5180 u32 ti; 5181 5182 tnl_type = le16_get_bits(filters[i].element.flags, 5183 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5184 5185 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5186 * one more byte further than normally used for Tenant ID in 5187 * other tunnel types. 5188 */ 5189 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5190 ti = le32_to_cpu(filters[i].element.tenant_id); 5191 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5192 } 5193 } 5194 5195 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5196 5197 return status; 5198 } 5199 5200 /** 5201 * i40e_aq_rem_cloud_filters 5202 * @hw: pointer to the hardware structure 5203 * @seid: VSI seid to remove cloud filters from 5204 * @filters: Buffer which contains the filters to be removed 5205 * @filter_count: number of filters contained in the buffer 5206 * 5207 * Remove the cloud filters for a given VSI. The contents of the 5208 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5209 * of the function. 5210 * 5211 **/ 5212 int 5213 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5214 struct i40e_aqc_cloud_filters_element_data *filters, 5215 u8 filter_count) 5216 { 5217 struct i40e_aq_desc desc; 5218 struct i40e_aqc_add_remove_cloud_filters *cmd = 5219 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5220 u16 buff_len; 5221 int status; 5222 5223 i40e_fill_default_direct_cmd_desc(&desc, 5224 i40e_aqc_opc_remove_cloud_filters); 5225 5226 buff_len = filter_count * sizeof(*filters); 5227 desc.datalen = cpu_to_le16(buff_len); 5228 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5229 cmd->num_filters = filter_count; 5230 cmd->seid = cpu_to_le16(seid); 5231 5232 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5233 5234 return status; 5235 } 5236 5237 /** 5238 * i40e_aq_rem_cloud_filters_bb 5239 * @hw: pointer to the hardware structure 5240 * @seid: VSI seid to remove cloud filters from 5241 * @filters: Buffer which contains the filters in big buffer to be removed 5242 * @filter_count: number of filters contained in the buffer 5243 * 5244 * Remove the big buffer cloud filters for a given VSI. The contents of the 5245 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5246 * function. 5247 * 5248 **/ 5249 int 5250 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5251 struct i40e_aqc_cloud_filters_element_bb *filters, 5252 u8 filter_count) 5253 { 5254 struct i40e_aq_desc desc; 5255 struct i40e_aqc_add_remove_cloud_filters *cmd = 5256 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5257 u16 buff_len; 5258 int status; 5259 int i; 5260 5261 i40e_fill_default_direct_cmd_desc(&desc, 5262 i40e_aqc_opc_remove_cloud_filters); 5263 5264 buff_len = filter_count * sizeof(*filters); 5265 desc.datalen = cpu_to_le16(buff_len); 5266 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5267 cmd->num_filters = filter_count; 5268 cmd->seid = cpu_to_le16(seid); 5269 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5270 5271 for (i = 0; i < filter_count; i++) { 5272 u16 tnl_type; 5273 u32 ti; 5274 5275 tnl_type = le16_get_bits(filters[i].element.flags, 5276 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5277 5278 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5279 * one more byte further than normally used for Tenant ID in 5280 * other tunnel types. 5281 */ 5282 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5283 ti = le32_to_cpu(filters[i].element.tenant_id); 5284 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5285 } 5286 } 5287 5288 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5289 5290 return status; 5291 } 5292