1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include "i40e.h" 5 #include "i40e_type.h" 6 #include "i40e_adminq.h" 7 #include "i40e_prototype.h" 8 #include <linux/avf/virtchnl.h> 9 10 /** 11 * i40e_set_mac_type - Sets MAC type 12 * @hw: pointer to the HW structure 13 * 14 * This function sets the mac type of the adapter based on the 15 * vendor ID and device ID stored in the hw structure. 16 **/ 17 i40e_status i40e_set_mac_type(struct i40e_hw *hw) 18 { 19 i40e_status status = 0; 20 21 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 22 switch (hw->device_id) { 23 case I40E_DEV_ID_SFP_XL710: 24 case I40E_DEV_ID_QEMU: 25 case I40E_DEV_ID_KX_B: 26 case I40E_DEV_ID_KX_C: 27 case I40E_DEV_ID_QSFP_A: 28 case I40E_DEV_ID_QSFP_B: 29 case I40E_DEV_ID_QSFP_C: 30 case I40E_DEV_ID_10G_BASE_T: 31 case I40E_DEV_ID_10G_BASE_T4: 32 case I40E_DEV_ID_10G_BASE_T_BC: 33 case I40E_DEV_ID_10G_B: 34 case I40E_DEV_ID_10G_SFP: 35 case I40E_DEV_ID_20G_KR2: 36 case I40E_DEV_ID_20G_KR2_A: 37 case I40E_DEV_ID_25G_B: 38 case I40E_DEV_ID_25G_SFP28: 39 case I40E_DEV_ID_X710_N3000: 40 case I40E_DEV_ID_XXV710_N3000: 41 hw->mac.type = I40E_MAC_XL710; 42 break; 43 case I40E_DEV_ID_KX_X722: 44 case I40E_DEV_ID_QSFP_X722: 45 case I40E_DEV_ID_SFP_X722: 46 case I40E_DEV_ID_1G_BASE_T_X722: 47 case I40E_DEV_ID_10G_BASE_T_X722: 48 case I40E_DEV_ID_SFP_I_X722: 49 hw->mac.type = I40E_MAC_X722; 50 break; 51 default: 52 hw->mac.type = I40E_MAC_GENERIC; 53 break; 54 } 55 } else { 56 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 57 } 58 59 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 60 hw->mac.type, status); 61 return status; 62 } 63 64 /** 65 * i40e_aq_str - convert AQ err code to a string 66 * @hw: pointer to the HW structure 67 * @aq_err: the AQ error code to convert 68 **/ 69 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 70 { 71 switch (aq_err) { 72 case I40E_AQ_RC_OK: 73 return "OK"; 74 case I40E_AQ_RC_EPERM: 75 return "I40E_AQ_RC_EPERM"; 76 case I40E_AQ_RC_ENOENT: 77 return "I40E_AQ_RC_ENOENT"; 78 case I40E_AQ_RC_ESRCH: 79 return "I40E_AQ_RC_ESRCH"; 80 case I40E_AQ_RC_EINTR: 81 return "I40E_AQ_RC_EINTR"; 82 case I40E_AQ_RC_EIO: 83 return "I40E_AQ_RC_EIO"; 84 case I40E_AQ_RC_ENXIO: 85 return "I40E_AQ_RC_ENXIO"; 86 case I40E_AQ_RC_E2BIG: 87 return "I40E_AQ_RC_E2BIG"; 88 case I40E_AQ_RC_EAGAIN: 89 return "I40E_AQ_RC_EAGAIN"; 90 case I40E_AQ_RC_ENOMEM: 91 return "I40E_AQ_RC_ENOMEM"; 92 case I40E_AQ_RC_EACCES: 93 return "I40E_AQ_RC_EACCES"; 94 case I40E_AQ_RC_EFAULT: 95 return "I40E_AQ_RC_EFAULT"; 96 case I40E_AQ_RC_EBUSY: 97 return "I40E_AQ_RC_EBUSY"; 98 case I40E_AQ_RC_EEXIST: 99 return "I40E_AQ_RC_EEXIST"; 100 case I40E_AQ_RC_EINVAL: 101 return "I40E_AQ_RC_EINVAL"; 102 case I40E_AQ_RC_ENOTTY: 103 return "I40E_AQ_RC_ENOTTY"; 104 case I40E_AQ_RC_ENOSPC: 105 return "I40E_AQ_RC_ENOSPC"; 106 case I40E_AQ_RC_ENOSYS: 107 return "I40E_AQ_RC_ENOSYS"; 108 case I40E_AQ_RC_ERANGE: 109 return "I40E_AQ_RC_ERANGE"; 110 case I40E_AQ_RC_EFLUSHED: 111 return "I40E_AQ_RC_EFLUSHED"; 112 case I40E_AQ_RC_BAD_ADDR: 113 return "I40E_AQ_RC_BAD_ADDR"; 114 case I40E_AQ_RC_EMODE: 115 return "I40E_AQ_RC_EMODE"; 116 case I40E_AQ_RC_EFBIG: 117 return "I40E_AQ_RC_EFBIG"; 118 } 119 120 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 121 return hw->err_str; 122 } 123 124 /** 125 * i40e_stat_str - convert status err code to a string 126 * @hw: pointer to the HW structure 127 * @stat_err: the status error code to convert 128 **/ 129 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 130 { 131 switch (stat_err) { 132 case 0: 133 return "OK"; 134 case I40E_ERR_NVM: 135 return "I40E_ERR_NVM"; 136 case I40E_ERR_NVM_CHECKSUM: 137 return "I40E_ERR_NVM_CHECKSUM"; 138 case I40E_ERR_PHY: 139 return "I40E_ERR_PHY"; 140 case I40E_ERR_CONFIG: 141 return "I40E_ERR_CONFIG"; 142 case I40E_ERR_PARAM: 143 return "I40E_ERR_PARAM"; 144 case I40E_ERR_MAC_TYPE: 145 return "I40E_ERR_MAC_TYPE"; 146 case I40E_ERR_UNKNOWN_PHY: 147 return "I40E_ERR_UNKNOWN_PHY"; 148 case I40E_ERR_LINK_SETUP: 149 return "I40E_ERR_LINK_SETUP"; 150 case I40E_ERR_ADAPTER_STOPPED: 151 return "I40E_ERR_ADAPTER_STOPPED"; 152 case I40E_ERR_INVALID_MAC_ADDR: 153 return "I40E_ERR_INVALID_MAC_ADDR"; 154 case I40E_ERR_DEVICE_NOT_SUPPORTED: 155 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 156 case I40E_ERR_MASTER_REQUESTS_PENDING: 157 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 158 case I40E_ERR_INVALID_LINK_SETTINGS: 159 return "I40E_ERR_INVALID_LINK_SETTINGS"; 160 case I40E_ERR_AUTONEG_NOT_COMPLETE: 161 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 162 case I40E_ERR_RESET_FAILED: 163 return "I40E_ERR_RESET_FAILED"; 164 case I40E_ERR_SWFW_SYNC: 165 return "I40E_ERR_SWFW_SYNC"; 166 case I40E_ERR_NO_AVAILABLE_VSI: 167 return "I40E_ERR_NO_AVAILABLE_VSI"; 168 case I40E_ERR_NO_MEMORY: 169 return "I40E_ERR_NO_MEMORY"; 170 case I40E_ERR_BAD_PTR: 171 return "I40E_ERR_BAD_PTR"; 172 case I40E_ERR_RING_FULL: 173 return "I40E_ERR_RING_FULL"; 174 case I40E_ERR_INVALID_PD_ID: 175 return "I40E_ERR_INVALID_PD_ID"; 176 case I40E_ERR_INVALID_QP_ID: 177 return "I40E_ERR_INVALID_QP_ID"; 178 case I40E_ERR_INVALID_CQ_ID: 179 return "I40E_ERR_INVALID_CQ_ID"; 180 case I40E_ERR_INVALID_CEQ_ID: 181 return "I40E_ERR_INVALID_CEQ_ID"; 182 case I40E_ERR_INVALID_AEQ_ID: 183 return "I40E_ERR_INVALID_AEQ_ID"; 184 case I40E_ERR_INVALID_SIZE: 185 return "I40E_ERR_INVALID_SIZE"; 186 case I40E_ERR_INVALID_ARP_INDEX: 187 return "I40E_ERR_INVALID_ARP_INDEX"; 188 case I40E_ERR_INVALID_FPM_FUNC_ID: 189 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 190 case I40E_ERR_QP_INVALID_MSG_SIZE: 191 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 192 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 193 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 194 case I40E_ERR_INVALID_FRAG_COUNT: 195 return "I40E_ERR_INVALID_FRAG_COUNT"; 196 case I40E_ERR_QUEUE_EMPTY: 197 return "I40E_ERR_QUEUE_EMPTY"; 198 case I40E_ERR_INVALID_ALIGNMENT: 199 return "I40E_ERR_INVALID_ALIGNMENT"; 200 case I40E_ERR_FLUSHED_QUEUE: 201 return "I40E_ERR_FLUSHED_QUEUE"; 202 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 203 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 204 case I40E_ERR_INVALID_IMM_DATA_SIZE: 205 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 206 case I40E_ERR_TIMEOUT: 207 return "I40E_ERR_TIMEOUT"; 208 case I40E_ERR_OPCODE_MISMATCH: 209 return "I40E_ERR_OPCODE_MISMATCH"; 210 case I40E_ERR_CQP_COMPL_ERROR: 211 return "I40E_ERR_CQP_COMPL_ERROR"; 212 case I40E_ERR_INVALID_VF_ID: 213 return "I40E_ERR_INVALID_VF_ID"; 214 case I40E_ERR_INVALID_HMCFN_ID: 215 return "I40E_ERR_INVALID_HMCFN_ID"; 216 case I40E_ERR_BACKING_PAGE_ERROR: 217 return "I40E_ERR_BACKING_PAGE_ERROR"; 218 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 219 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 220 case I40E_ERR_INVALID_PBLE_INDEX: 221 return "I40E_ERR_INVALID_PBLE_INDEX"; 222 case I40E_ERR_INVALID_SD_INDEX: 223 return "I40E_ERR_INVALID_SD_INDEX"; 224 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 225 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 226 case I40E_ERR_INVALID_SD_TYPE: 227 return "I40E_ERR_INVALID_SD_TYPE"; 228 case I40E_ERR_MEMCPY_FAILED: 229 return "I40E_ERR_MEMCPY_FAILED"; 230 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 231 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 232 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 233 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 234 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 235 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 236 case I40E_ERR_SRQ_ENABLED: 237 return "I40E_ERR_SRQ_ENABLED"; 238 case I40E_ERR_ADMIN_QUEUE_ERROR: 239 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 240 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 241 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 242 case I40E_ERR_BUF_TOO_SHORT: 243 return "I40E_ERR_BUF_TOO_SHORT"; 244 case I40E_ERR_ADMIN_QUEUE_FULL: 245 return "I40E_ERR_ADMIN_QUEUE_FULL"; 246 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 247 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 248 case I40E_ERR_BAD_IWARP_CQE: 249 return "I40E_ERR_BAD_IWARP_CQE"; 250 case I40E_ERR_NVM_BLANK_MODE: 251 return "I40E_ERR_NVM_BLANK_MODE"; 252 case I40E_ERR_NOT_IMPLEMENTED: 253 return "I40E_ERR_NOT_IMPLEMENTED"; 254 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 255 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 256 case I40E_ERR_DIAG_TEST_FAILED: 257 return "I40E_ERR_DIAG_TEST_FAILED"; 258 case I40E_ERR_NOT_READY: 259 return "I40E_ERR_NOT_READY"; 260 case I40E_NOT_SUPPORTED: 261 return "I40E_NOT_SUPPORTED"; 262 case I40E_ERR_FIRMWARE_API_VERSION: 263 return "I40E_ERR_FIRMWARE_API_VERSION"; 264 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 265 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 266 } 267 268 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 269 return hw->err_str; 270 } 271 272 /** 273 * i40e_debug_aq 274 * @hw: debug mask related to admin queue 275 * @mask: debug mask 276 * @desc: pointer to admin queue descriptor 277 * @buffer: pointer to command buffer 278 * @buf_len: max length of buffer 279 * 280 * Dumps debug log about adminq command with descriptor contents. 281 **/ 282 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 283 void *buffer, u16 buf_len) 284 { 285 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 286 u32 effective_mask = hw->debug_mask & mask; 287 char prefix[27]; 288 u16 len; 289 u8 *buf = (u8 *)buffer; 290 291 if (!effective_mask || !desc) 292 return; 293 294 len = le16_to_cpu(aq_desc->datalen); 295 296 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 297 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 298 le16_to_cpu(aq_desc->opcode), 299 le16_to_cpu(aq_desc->flags), 300 le16_to_cpu(aq_desc->datalen), 301 le16_to_cpu(aq_desc->retval)); 302 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 303 "\tcookie (h,l) 0x%08X 0x%08X\n", 304 le32_to_cpu(aq_desc->cookie_high), 305 le32_to_cpu(aq_desc->cookie_low)); 306 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 307 "\tparam (0,1) 0x%08X 0x%08X\n", 308 le32_to_cpu(aq_desc->params.internal.param0), 309 le32_to_cpu(aq_desc->params.internal.param1)); 310 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 311 "\taddr (h,l) 0x%08X 0x%08X\n", 312 le32_to_cpu(aq_desc->params.external.addr_high), 313 le32_to_cpu(aq_desc->params.external.addr_low)); 314 315 if (buffer && buf_len != 0 && len != 0 && 316 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { 317 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 318 if (buf_len < len) 319 len = buf_len; 320 321 snprintf(prefix, sizeof(prefix), 322 "i40e %02x:%02x.%x: \t0x", 323 hw->bus.bus_id, 324 hw->bus.device, 325 hw->bus.func); 326 327 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 328 16, 1, buf, len, false); 329 } 330 } 331 332 /** 333 * i40e_check_asq_alive 334 * @hw: pointer to the hw struct 335 * 336 * Returns true if Queue is enabled else false. 337 **/ 338 bool i40e_check_asq_alive(struct i40e_hw *hw) 339 { 340 if (hw->aq.asq.len) 341 return !!(rd32(hw, hw->aq.asq.len) & 342 I40E_PF_ATQLEN_ATQENABLE_MASK); 343 else 344 return false; 345 } 346 347 /** 348 * i40e_aq_queue_shutdown 349 * @hw: pointer to the hw struct 350 * @unloading: is the driver unloading itself 351 * 352 * Tell the Firmware that we're shutting down the AdminQ and whether 353 * or not the driver is unloading as well. 354 **/ 355 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 356 bool unloading) 357 { 358 struct i40e_aq_desc desc; 359 struct i40e_aqc_queue_shutdown *cmd = 360 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 361 i40e_status status; 362 363 i40e_fill_default_direct_cmd_desc(&desc, 364 i40e_aqc_opc_queue_shutdown); 365 366 if (unloading) 367 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 368 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 369 370 return status; 371 } 372 373 /** 374 * i40e_aq_get_set_rss_lut 375 * @hw: pointer to the hardware structure 376 * @vsi_id: vsi fw index 377 * @pf_lut: for PF table set true, for VSI table set false 378 * @lut: pointer to the lut buffer provided by the caller 379 * @lut_size: size of the lut buffer 380 * @set: set true to set the table, false to get the table 381 * 382 * Internal function to get or set RSS look up table 383 **/ 384 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 385 u16 vsi_id, bool pf_lut, 386 u8 *lut, u16 lut_size, 387 bool set) 388 { 389 i40e_status status; 390 struct i40e_aq_desc desc; 391 struct i40e_aqc_get_set_rss_lut *cmd_resp = 392 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 393 394 if (set) 395 i40e_fill_default_direct_cmd_desc(&desc, 396 i40e_aqc_opc_set_rss_lut); 397 else 398 i40e_fill_default_direct_cmd_desc(&desc, 399 i40e_aqc_opc_get_rss_lut); 400 401 /* Indirect command */ 402 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 403 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 404 405 cmd_resp->vsi_id = 406 cpu_to_le16((u16)((vsi_id << 407 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 408 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 409 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 410 411 if (pf_lut) 412 cmd_resp->flags |= cpu_to_le16((u16) 413 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 414 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 415 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 416 else 417 cmd_resp->flags |= cpu_to_le16((u16) 418 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 419 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 420 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 421 422 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 423 424 return status; 425 } 426 427 /** 428 * i40e_aq_get_rss_lut 429 * @hw: pointer to the hardware structure 430 * @vsi_id: vsi fw index 431 * @pf_lut: for PF table set true, for VSI table set false 432 * @lut: pointer to the lut buffer provided by the caller 433 * @lut_size: size of the lut buffer 434 * 435 * get the RSS lookup table, PF or VSI type 436 **/ 437 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 438 bool pf_lut, u8 *lut, u16 lut_size) 439 { 440 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 441 false); 442 } 443 444 /** 445 * i40e_aq_set_rss_lut 446 * @hw: pointer to the hardware structure 447 * @vsi_id: vsi fw index 448 * @pf_lut: for PF table set true, for VSI table set false 449 * @lut: pointer to the lut buffer provided by the caller 450 * @lut_size: size of the lut buffer 451 * 452 * set the RSS lookup table, PF or VSI type 453 **/ 454 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 455 bool pf_lut, u8 *lut, u16 lut_size) 456 { 457 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 458 } 459 460 /** 461 * i40e_aq_get_set_rss_key 462 * @hw: pointer to the hw struct 463 * @vsi_id: vsi fw index 464 * @key: pointer to key info struct 465 * @set: set true to set the key, false to get the key 466 * 467 * get the RSS key per VSI 468 **/ 469 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 470 u16 vsi_id, 471 struct i40e_aqc_get_set_rss_key_data *key, 472 bool set) 473 { 474 i40e_status status; 475 struct i40e_aq_desc desc; 476 struct i40e_aqc_get_set_rss_key *cmd_resp = 477 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 478 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 479 480 if (set) 481 i40e_fill_default_direct_cmd_desc(&desc, 482 i40e_aqc_opc_set_rss_key); 483 else 484 i40e_fill_default_direct_cmd_desc(&desc, 485 i40e_aqc_opc_get_rss_key); 486 487 /* Indirect command */ 488 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 489 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 490 491 cmd_resp->vsi_id = 492 cpu_to_le16((u16)((vsi_id << 493 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 494 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 495 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 496 497 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 498 499 return status; 500 } 501 502 /** 503 * i40e_aq_get_rss_key 504 * @hw: pointer to the hw struct 505 * @vsi_id: vsi fw index 506 * @key: pointer to key info struct 507 * 508 **/ 509 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 510 u16 vsi_id, 511 struct i40e_aqc_get_set_rss_key_data *key) 512 { 513 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 514 } 515 516 /** 517 * i40e_aq_set_rss_key 518 * @hw: pointer to the hw struct 519 * @vsi_id: vsi fw index 520 * @key: pointer to key info struct 521 * 522 * set the RSS key per VSI 523 **/ 524 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 525 u16 vsi_id, 526 struct i40e_aqc_get_set_rss_key_data *key) 527 { 528 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 529 } 530 531 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 532 * hardware to a bit-field that can be used by SW to more easily determine the 533 * packet type. 534 * 535 * Macros are used to shorten the table lines and make this table human 536 * readable. 537 * 538 * We store the PTYPE in the top byte of the bit field - this is just so that 539 * we can check that the table doesn't have a row missing, as the index into 540 * the table should be the PTYPE. 541 * 542 * Typical work flow: 543 * 544 * IF NOT i40e_ptype_lookup[ptype].known 545 * THEN 546 * Packet is unknown 547 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 548 * Use the rest of the fields to look at the tunnels, inner protocols, etc 549 * ELSE 550 * Use the enum i40e_rx_l2_ptype to decode the packet type 551 * ENDIF 552 */ 553 554 /* macro to make the table lines short */ 555 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 556 { PTYPE, \ 557 1, \ 558 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 559 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 560 I40E_RX_PTYPE_##OUTER_FRAG, \ 561 I40E_RX_PTYPE_TUNNEL_##T, \ 562 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 563 I40E_RX_PTYPE_##TEF, \ 564 I40E_RX_PTYPE_INNER_PROT_##I, \ 565 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 566 567 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 568 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 569 570 /* shorter macros makes the table fit but are terse */ 571 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 572 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 573 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 574 575 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 576 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 577 /* L2 Packet types */ 578 I40E_PTT_UNUSED_ENTRY(0), 579 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 580 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 581 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 582 I40E_PTT_UNUSED_ENTRY(4), 583 I40E_PTT_UNUSED_ENTRY(5), 584 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 585 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 586 I40E_PTT_UNUSED_ENTRY(8), 587 I40E_PTT_UNUSED_ENTRY(9), 588 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 589 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 590 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 591 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 592 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 593 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 594 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 595 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 596 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 597 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 598 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 599 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 600 601 /* Non Tunneled IPv4 */ 602 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 603 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 604 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 605 I40E_PTT_UNUSED_ENTRY(25), 606 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 607 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 608 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 609 610 /* IPv4 --> IPv4 */ 611 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 612 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 613 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 614 I40E_PTT_UNUSED_ENTRY(32), 615 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 616 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 617 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 618 619 /* IPv4 --> IPv6 */ 620 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 621 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 622 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 623 I40E_PTT_UNUSED_ENTRY(39), 624 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 625 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 626 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 627 628 /* IPv4 --> GRE/NAT */ 629 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 630 631 /* IPv4 --> GRE/NAT --> IPv4 */ 632 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 633 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 634 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 635 I40E_PTT_UNUSED_ENTRY(47), 636 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 637 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 638 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 639 640 /* IPv4 --> GRE/NAT --> IPv6 */ 641 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 642 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 643 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 644 I40E_PTT_UNUSED_ENTRY(54), 645 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 646 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 647 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 648 649 /* IPv4 --> GRE/NAT --> MAC */ 650 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 651 652 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 653 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 654 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 655 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 656 I40E_PTT_UNUSED_ENTRY(62), 657 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 658 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 659 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 660 661 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 662 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 663 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 664 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 665 I40E_PTT_UNUSED_ENTRY(69), 666 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 667 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 668 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 669 670 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 671 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 672 673 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 674 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 675 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 676 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 677 I40E_PTT_UNUSED_ENTRY(77), 678 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 679 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 680 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 681 682 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 683 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 684 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 685 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 686 I40E_PTT_UNUSED_ENTRY(84), 687 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 688 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 689 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 690 691 /* Non Tunneled IPv6 */ 692 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 693 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 694 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 695 I40E_PTT_UNUSED_ENTRY(91), 696 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 697 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 698 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 699 700 /* IPv6 --> IPv4 */ 701 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 702 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 703 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 704 I40E_PTT_UNUSED_ENTRY(98), 705 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 706 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 707 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 708 709 /* IPv6 --> IPv6 */ 710 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 711 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 712 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 713 I40E_PTT_UNUSED_ENTRY(105), 714 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 715 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 716 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 717 718 /* IPv6 --> GRE/NAT */ 719 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 720 721 /* IPv6 --> GRE/NAT -> IPv4 */ 722 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 723 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 724 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 725 I40E_PTT_UNUSED_ENTRY(113), 726 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 727 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 728 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 729 730 /* IPv6 --> GRE/NAT -> IPv6 */ 731 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 732 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 733 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 734 I40E_PTT_UNUSED_ENTRY(120), 735 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 736 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 737 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 738 739 /* IPv6 --> GRE/NAT -> MAC */ 740 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 741 742 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 743 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 744 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 745 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 746 I40E_PTT_UNUSED_ENTRY(128), 747 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 748 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 749 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 750 751 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 752 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 753 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 754 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 755 I40E_PTT_UNUSED_ENTRY(135), 756 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 757 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 758 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 759 760 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 761 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 762 763 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 764 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 765 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 766 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 767 I40E_PTT_UNUSED_ENTRY(143), 768 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 769 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 770 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 771 772 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 773 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 774 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 775 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 776 I40E_PTT_UNUSED_ENTRY(150), 777 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 778 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 779 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 780 781 /* unused entries */ 782 I40E_PTT_UNUSED_ENTRY(154), 783 I40E_PTT_UNUSED_ENTRY(155), 784 I40E_PTT_UNUSED_ENTRY(156), 785 I40E_PTT_UNUSED_ENTRY(157), 786 I40E_PTT_UNUSED_ENTRY(158), 787 I40E_PTT_UNUSED_ENTRY(159), 788 789 I40E_PTT_UNUSED_ENTRY(160), 790 I40E_PTT_UNUSED_ENTRY(161), 791 I40E_PTT_UNUSED_ENTRY(162), 792 I40E_PTT_UNUSED_ENTRY(163), 793 I40E_PTT_UNUSED_ENTRY(164), 794 I40E_PTT_UNUSED_ENTRY(165), 795 I40E_PTT_UNUSED_ENTRY(166), 796 I40E_PTT_UNUSED_ENTRY(167), 797 I40E_PTT_UNUSED_ENTRY(168), 798 I40E_PTT_UNUSED_ENTRY(169), 799 800 I40E_PTT_UNUSED_ENTRY(170), 801 I40E_PTT_UNUSED_ENTRY(171), 802 I40E_PTT_UNUSED_ENTRY(172), 803 I40E_PTT_UNUSED_ENTRY(173), 804 I40E_PTT_UNUSED_ENTRY(174), 805 I40E_PTT_UNUSED_ENTRY(175), 806 I40E_PTT_UNUSED_ENTRY(176), 807 I40E_PTT_UNUSED_ENTRY(177), 808 I40E_PTT_UNUSED_ENTRY(178), 809 I40E_PTT_UNUSED_ENTRY(179), 810 811 I40E_PTT_UNUSED_ENTRY(180), 812 I40E_PTT_UNUSED_ENTRY(181), 813 I40E_PTT_UNUSED_ENTRY(182), 814 I40E_PTT_UNUSED_ENTRY(183), 815 I40E_PTT_UNUSED_ENTRY(184), 816 I40E_PTT_UNUSED_ENTRY(185), 817 I40E_PTT_UNUSED_ENTRY(186), 818 I40E_PTT_UNUSED_ENTRY(187), 819 I40E_PTT_UNUSED_ENTRY(188), 820 I40E_PTT_UNUSED_ENTRY(189), 821 822 I40E_PTT_UNUSED_ENTRY(190), 823 I40E_PTT_UNUSED_ENTRY(191), 824 I40E_PTT_UNUSED_ENTRY(192), 825 I40E_PTT_UNUSED_ENTRY(193), 826 I40E_PTT_UNUSED_ENTRY(194), 827 I40E_PTT_UNUSED_ENTRY(195), 828 I40E_PTT_UNUSED_ENTRY(196), 829 I40E_PTT_UNUSED_ENTRY(197), 830 I40E_PTT_UNUSED_ENTRY(198), 831 I40E_PTT_UNUSED_ENTRY(199), 832 833 I40E_PTT_UNUSED_ENTRY(200), 834 I40E_PTT_UNUSED_ENTRY(201), 835 I40E_PTT_UNUSED_ENTRY(202), 836 I40E_PTT_UNUSED_ENTRY(203), 837 I40E_PTT_UNUSED_ENTRY(204), 838 I40E_PTT_UNUSED_ENTRY(205), 839 I40E_PTT_UNUSED_ENTRY(206), 840 I40E_PTT_UNUSED_ENTRY(207), 841 I40E_PTT_UNUSED_ENTRY(208), 842 I40E_PTT_UNUSED_ENTRY(209), 843 844 I40E_PTT_UNUSED_ENTRY(210), 845 I40E_PTT_UNUSED_ENTRY(211), 846 I40E_PTT_UNUSED_ENTRY(212), 847 I40E_PTT_UNUSED_ENTRY(213), 848 I40E_PTT_UNUSED_ENTRY(214), 849 I40E_PTT_UNUSED_ENTRY(215), 850 I40E_PTT_UNUSED_ENTRY(216), 851 I40E_PTT_UNUSED_ENTRY(217), 852 I40E_PTT_UNUSED_ENTRY(218), 853 I40E_PTT_UNUSED_ENTRY(219), 854 855 I40E_PTT_UNUSED_ENTRY(220), 856 I40E_PTT_UNUSED_ENTRY(221), 857 I40E_PTT_UNUSED_ENTRY(222), 858 I40E_PTT_UNUSED_ENTRY(223), 859 I40E_PTT_UNUSED_ENTRY(224), 860 I40E_PTT_UNUSED_ENTRY(225), 861 I40E_PTT_UNUSED_ENTRY(226), 862 I40E_PTT_UNUSED_ENTRY(227), 863 I40E_PTT_UNUSED_ENTRY(228), 864 I40E_PTT_UNUSED_ENTRY(229), 865 866 I40E_PTT_UNUSED_ENTRY(230), 867 I40E_PTT_UNUSED_ENTRY(231), 868 I40E_PTT_UNUSED_ENTRY(232), 869 I40E_PTT_UNUSED_ENTRY(233), 870 I40E_PTT_UNUSED_ENTRY(234), 871 I40E_PTT_UNUSED_ENTRY(235), 872 I40E_PTT_UNUSED_ENTRY(236), 873 I40E_PTT_UNUSED_ENTRY(237), 874 I40E_PTT_UNUSED_ENTRY(238), 875 I40E_PTT_UNUSED_ENTRY(239), 876 877 I40E_PTT_UNUSED_ENTRY(240), 878 I40E_PTT_UNUSED_ENTRY(241), 879 I40E_PTT_UNUSED_ENTRY(242), 880 I40E_PTT_UNUSED_ENTRY(243), 881 I40E_PTT_UNUSED_ENTRY(244), 882 I40E_PTT_UNUSED_ENTRY(245), 883 I40E_PTT_UNUSED_ENTRY(246), 884 I40E_PTT_UNUSED_ENTRY(247), 885 I40E_PTT_UNUSED_ENTRY(248), 886 I40E_PTT_UNUSED_ENTRY(249), 887 888 I40E_PTT_UNUSED_ENTRY(250), 889 I40E_PTT_UNUSED_ENTRY(251), 890 I40E_PTT_UNUSED_ENTRY(252), 891 I40E_PTT_UNUSED_ENTRY(253), 892 I40E_PTT_UNUSED_ENTRY(254), 893 I40E_PTT_UNUSED_ENTRY(255) 894 }; 895 896 /** 897 * i40e_init_shared_code - Initialize the shared code 898 * @hw: pointer to hardware structure 899 * 900 * This assigns the MAC type and PHY code and inits the NVM. 901 * Does not touch the hardware. This function must be called prior to any 902 * other function in the shared code. The i40e_hw structure should be 903 * memset to 0 prior to calling this function. The following fields in 904 * hw structure should be filled in prior to calling this function: 905 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 906 * subsystem_vendor_id, and revision_id 907 **/ 908 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 909 { 910 i40e_status status = 0; 911 u32 port, ari, func_rid; 912 913 i40e_set_mac_type(hw); 914 915 switch (hw->mac.type) { 916 case I40E_MAC_XL710: 917 case I40E_MAC_X722: 918 break; 919 default: 920 return I40E_ERR_DEVICE_NOT_SUPPORTED; 921 } 922 923 hw->phy.get_link_info = true; 924 925 /* Determine port number and PF number*/ 926 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 927 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 928 hw->port = (u8)port; 929 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 930 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 931 func_rid = rd32(hw, I40E_PF_FUNC_RID); 932 if (ari) 933 hw->pf_id = (u8)(func_rid & 0xff); 934 else 935 hw->pf_id = (u8)(func_rid & 0x7); 936 937 status = i40e_init_nvm(hw); 938 return status; 939 } 940 941 /** 942 * i40e_aq_mac_address_read - Retrieve the MAC addresses 943 * @hw: pointer to the hw struct 944 * @flags: a return indicator of what addresses were added to the addr store 945 * @addrs: the requestor's mac addr store 946 * @cmd_details: pointer to command details structure or NULL 947 **/ 948 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 949 u16 *flags, 950 struct i40e_aqc_mac_address_read_data *addrs, 951 struct i40e_asq_cmd_details *cmd_details) 952 { 953 struct i40e_aq_desc desc; 954 struct i40e_aqc_mac_address_read *cmd_data = 955 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 956 i40e_status status; 957 958 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 959 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 960 961 status = i40e_asq_send_command(hw, &desc, addrs, 962 sizeof(*addrs), cmd_details); 963 *flags = le16_to_cpu(cmd_data->command_flags); 964 965 return status; 966 } 967 968 /** 969 * i40e_aq_mac_address_write - Change the MAC addresses 970 * @hw: pointer to the hw struct 971 * @flags: indicates which MAC to be written 972 * @mac_addr: address to write 973 * @cmd_details: pointer to command details structure or NULL 974 **/ 975 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 976 u16 flags, u8 *mac_addr, 977 struct i40e_asq_cmd_details *cmd_details) 978 { 979 struct i40e_aq_desc desc; 980 struct i40e_aqc_mac_address_write *cmd_data = 981 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 982 i40e_status status; 983 984 i40e_fill_default_direct_cmd_desc(&desc, 985 i40e_aqc_opc_mac_address_write); 986 cmd_data->command_flags = cpu_to_le16(flags); 987 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 988 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 989 ((u32)mac_addr[3] << 16) | 990 ((u32)mac_addr[4] << 8) | 991 mac_addr[5]); 992 993 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 994 995 return status; 996 } 997 998 /** 999 * i40e_get_mac_addr - get MAC address 1000 * @hw: pointer to the HW structure 1001 * @mac_addr: pointer to MAC address 1002 * 1003 * Reads the adapter's MAC address from register 1004 **/ 1005 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1006 { 1007 struct i40e_aqc_mac_address_read_data addrs; 1008 i40e_status status; 1009 u16 flags = 0; 1010 1011 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1012 1013 if (flags & I40E_AQC_LAN_ADDR_VALID) 1014 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1015 1016 return status; 1017 } 1018 1019 /** 1020 * i40e_get_port_mac_addr - get Port MAC address 1021 * @hw: pointer to the HW structure 1022 * @mac_addr: pointer to Port MAC address 1023 * 1024 * Reads the adapter's Port MAC address 1025 **/ 1026 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1027 { 1028 struct i40e_aqc_mac_address_read_data addrs; 1029 i40e_status status; 1030 u16 flags = 0; 1031 1032 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1033 if (status) 1034 return status; 1035 1036 if (flags & I40E_AQC_PORT_ADDR_VALID) 1037 ether_addr_copy(mac_addr, addrs.port_mac); 1038 else 1039 status = I40E_ERR_INVALID_MAC_ADDR; 1040 1041 return status; 1042 } 1043 1044 /** 1045 * i40e_pre_tx_queue_cfg - pre tx queue configure 1046 * @hw: pointer to the HW structure 1047 * @queue: target PF queue index 1048 * @enable: state change request 1049 * 1050 * Handles hw requirement to indicate intention to enable 1051 * or disable target queue. 1052 **/ 1053 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1054 { 1055 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1056 u32 reg_block = 0; 1057 u32 reg_val; 1058 1059 if (abs_queue_idx >= 128) { 1060 reg_block = abs_queue_idx / 128; 1061 abs_queue_idx %= 128; 1062 } 1063 1064 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1065 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1066 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1067 1068 if (enable) 1069 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1070 else 1071 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1072 1073 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1074 } 1075 1076 /** 1077 * i40e_read_pba_string - Reads part number string from EEPROM 1078 * @hw: pointer to hardware structure 1079 * @pba_num: stores the part number string from the EEPROM 1080 * @pba_num_size: part number string buffer length 1081 * 1082 * Reads the part number string from the EEPROM. 1083 **/ 1084 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1085 u32 pba_num_size) 1086 { 1087 i40e_status status = 0; 1088 u16 pba_word = 0; 1089 u16 pba_size = 0; 1090 u16 pba_ptr = 0; 1091 u16 i = 0; 1092 1093 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1094 if (status || (pba_word != 0xFAFA)) { 1095 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1096 return status; 1097 } 1098 1099 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1100 if (status) { 1101 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1102 return status; 1103 } 1104 1105 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1106 if (status) { 1107 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1108 return status; 1109 } 1110 1111 /* Subtract one to get PBA word count (PBA Size word is included in 1112 * total size) 1113 */ 1114 pba_size--; 1115 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1116 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1117 return I40E_ERR_PARAM; 1118 } 1119 1120 for (i = 0; i < pba_size; i++) { 1121 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1122 if (status) { 1123 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1124 return status; 1125 } 1126 1127 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1128 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1129 } 1130 pba_num[(pba_size * 2)] = '\0'; 1131 1132 return status; 1133 } 1134 1135 /** 1136 * i40e_get_media_type - Gets media type 1137 * @hw: pointer to the hardware structure 1138 **/ 1139 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1140 { 1141 enum i40e_media_type media; 1142 1143 switch (hw->phy.link_info.phy_type) { 1144 case I40E_PHY_TYPE_10GBASE_SR: 1145 case I40E_PHY_TYPE_10GBASE_LR: 1146 case I40E_PHY_TYPE_1000BASE_SX: 1147 case I40E_PHY_TYPE_1000BASE_LX: 1148 case I40E_PHY_TYPE_40GBASE_SR4: 1149 case I40E_PHY_TYPE_40GBASE_LR4: 1150 case I40E_PHY_TYPE_25GBASE_LR: 1151 case I40E_PHY_TYPE_25GBASE_SR: 1152 media = I40E_MEDIA_TYPE_FIBER; 1153 break; 1154 case I40E_PHY_TYPE_100BASE_TX: 1155 case I40E_PHY_TYPE_1000BASE_T: 1156 case I40E_PHY_TYPE_2_5GBASE_T: 1157 case I40E_PHY_TYPE_5GBASE_T: 1158 case I40E_PHY_TYPE_10GBASE_T: 1159 media = I40E_MEDIA_TYPE_BASET; 1160 break; 1161 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1162 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1163 case I40E_PHY_TYPE_10GBASE_CR1: 1164 case I40E_PHY_TYPE_40GBASE_CR4: 1165 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1166 case I40E_PHY_TYPE_40GBASE_AOC: 1167 case I40E_PHY_TYPE_10GBASE_AOC: 1168 case I40E_PHY_TYPE_25GBASE_CR: 1169 case I40E_PHY_TYPE_25GBASE_AOC: 1170 case I40E_PHY_TYPE_25GBASE_ACC: 1171 media = I40E_MEDIA_TYPE_DA; 1172 break; 1173 case I40E_PHY_TYPE_1000BASE_KX: 1174 case I40E_PHY_TYPE_10GBASE_KX4: 1175 case I40E_PHY_TYPE_10GBASE_KR: 1176 case I40E_PHY_TYPE_40GBASE_KR4: 1177 case I40E_PHY_TYPE_20GBASE_KR2: 1178 case I40E_PHY_TYPE_25GBASE_KR: 1179 media = I40E_MEDIA_TYPE_BACKPLANE; 1180 break; 1181 case I40E_PHY_TYPE_SGMII: 1182 case I40E_PHY_TYPE_XAUI: 1183 case I40E_PHY_TYPE_XFI: 1184 case I40E_PHY_TYPE_XLAUI: 1185 case I40E_PHY_TYPE_XLPPI: 1186 default: 1187 media = I40E_MEDIA_TYPE_UNKNOWN; 1188 break; 1189 } 1190 1191 return media; 1192 } 1193 1194 /** 1195 * i40e_poll_globr - Poll for Global Reset completion 1196 * @hw: pointer to the hardware structure 1197 * @retry_limit: how many times to retry before failure 1198 **/ 1199 static i40e_status i40e_poll_globr(struct i40e_hw *hw, 1200 u32 retry_limit) 1201 { 1202 u32 cnt, reg = 0; 1203 1204 for (cnt = 0; cnt < retry_limit; cnt++) { 1205 reg = rd32(hw, I40E_GLGEN_RSTAT); 1206 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1207 return 0; 1208 msleep(100); 1209 } 1210 1211 hw_dbg(hw, "Global reset failed.\n"); 1212 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg); 1213 1214 return I40E_ERR_RESET_FAILED; 1215 } 1216 1217 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1218 #define I40E_PF_RESET_WAIT_COUNT 200 1219 /** 1220 * i40e_pf_reset - Reset the PF 1221 * @hw: pointer to the hardware structure 1222 * 1223 * Assuming someone else has triggered a global reset, 1224 * assure the global reset is complete and then reset the PF 1225 **/ 1226 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1227 { 1228 u32 cnt = 0; 1229 u32 cnt1 = 0; 1230 u32 reg = 0; 1231 u32 grst_del; 1232 1233 /* Poll for Global Reset steady state in case of recent GRST. 1234 * The grst delay value is in 100ms units, and we'll wait a 1235 * couple counts longer to be sure we don't just miss the end. 1236 */ 1237 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1238 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1239 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1240 1241 /* It can take upto 15 secs for GRST steady state. 1242 * Bump it to 16 secs max to be safe. 1243 */ 1244 grst_del = grst_del * 20; 1245 1246 for (cnt = 0; cnt < grst_del; cnt++) { 1247 reg = rd32(hw, I40E_GLGEN_RSTAT); 1248 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1249 break; 1250 msleep(100); 1251 } 1252 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1253 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1254 return I40E_ERR_RESET_FAILED; 1255 } 1256 1257 /* Now Wait for the FW to be ready */ 1258 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1259 reg = rd32(hw, I40E_GLNVM_ULD); 1260 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1261 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1262 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1263 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1264 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1265 break; 1266 } 1267 usleep_range(10000, 20000); 1268 } 1269 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1270 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1271 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1272 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1273 return I40E_ERR_RESET_FAILED; 1274 } 1275 1276 /* If there was a Global Reset in progress when we got here, 1277 * we don't need to do the PF Reset 1278 */ 1279 if (!cnt) { 1280 u32 reg2 = 0; 1281 if (hw->revision_id == 0) 1282 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1283 else 1284 cnt = I40E_PF_RESET_WAIT_COUNT; 1285 reg = rd32(hw, I40E_PFGEN_CTRL); 1286 wr32(hw, I40E_PFGEN_CTRL, 1287 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1288 for (; cnt; cnt--) { 1289 reg = rd32(hw, I40E_PFGEN_CTRL); 1290 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1291 break; 1292 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1293 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 1294 break; 1295 usleep_range(1000, 2000); 1296 } 1297 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1298 if (i40e_poll_globr(hw, grst_del)) 1299 return I40E_ERR_RESET_FAILED; 1300 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1301 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1302 return I40E_ERR_RESET_FAILED; 1303 } 1304 } 1305 1306 i40e_clear_pxe_mode(hw); 1307 1308 return 0; 1309 } 1310 1311 /** 1312 * i40e_clear_hw - clear out any left over hw state 1313 * @hw: pointer to the hw struct 1314 * 1315 * Clear queues and interrupts, typically called at init time, 1316 * but after the capabilities have been found so we know how many 1317 * queues and msix vectors have been allocated. 1318 **/ 1319 void i40e_clear_hw(struct i40e_hw *hw) 1320 { 1321 u32 num_queues, base_queue; 1322 u32 num_pf_int; 1323 u32 num_vf_int; 1324 u32 num_vfs; 1325 u32 i, j; 1326 u32 val; 1327 u32 eol = 0x7ff; 1328 1329 /* get number of interrupts, queues, and VFs */ 1330 val = rd32(hw, I40E_GLPCI_CNF2); 1331 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1332 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1333 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1334 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1335 1336 val = rd32(hw, I40E_PFLAN_QALLOC); 1337 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1338 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1339 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1340 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1341 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1342 num_queues = (j - base_queue) + 1; 1343 else 1344 num_queues = 0; 1345 1346 val = rd32(hw, I40E_PF_VT_PFALLOC); 1347 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1348 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1349 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1350 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1351 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1352 num_vfs = (j - i) + 1; 1353 else 1354 num_vfs = 0; 1355 1356 /* stop all the interrupts */ 1357 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1358 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1359 for (i = 0; i < num_pf_int - 2; i++) 1360 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1361 1362 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1363 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1364 wr32(hw, I40E_PFINT_LNKLST0, val); 1365 for (i = 0; i < num_pf_int - 2; i++) 1366 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1367 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1368 for (i = 0; i < num_vfs; i++) 1369 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1370 for (i = 0; i < num_vf_int - 2; i++) 1371 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1372 1373 /* warn the HW of the coming Tx disables */ 1374 for (i = 0; i < num_queues; i++) { 1375 u32 abs_queue_idx = base_queue + i; 1376 u32 reg_block = 0; 1377 1378 if (abs_queue_idx >= 128) { 1379 reg_block = abs_queue_idx / 128; 1380 abs_queue_idx %= 128; 1381 } 1382 1383 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1384 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1385 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1386 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1387 1388 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1389 } 1390 udelay(400); 1391 1392 /* stop all the queues */ 1393 for (i = 0; i < num_queues; i++) { 1394 wr32(hw, I40E_QINT_TQCTL(i), 0); 1395 wr32(hw, I40E_QTX_ENA(i), 0); 1396 wr32(hw, I40E_QINT_RQCTL(i), 0); 1397 wr32(hw, I40E_QRX_ENA(i), 0); 1398 } 1399 1400 /* short wait for all queue disables to settle */ 1401 udelay(50); 1402 } 1403 1404 /** 1405 * i40e_clear_pxe_mode - clear pxe operations mode 1406 * @hw: pointer to the hw struct 1407 * 1408 * Make sure all PXE mode settings are cleared, including things 1409 * like descriptor fetch/write-back mode. 1410 **/ 1411 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1412 { 1413 u32 reg; 1414 1415 if (i40e_check_asq_alive(hw)) 1416 i40e_aq_clear_pxe_mode(hw, NULL); 1417 1418 /* Clear single descriptor fetch/write-back mode */ 1419 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1420 1421 if (hw->revision_id == 0) { 1422 /* As a work around clear PXE_MODE instead of setting it */ 1423 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1424 } else { 1425 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1426 } 1427 } 1428 1429 /** 1430 * i40e_led_is_mine - helper to find matching led 1431 * @hw: pointer to the hw struct 1432 * @idx: index into GPIO registers 1433 * 1434 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1435 */ 1436 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1437 { 1438 u32 gpio_val = 0; 1439 u32 port; 1440 1441 if (!I40E_IS_X710TL_DEVICE(hw->device_id) && 1442 !hw->func_caps.led[idx]) 1443 return 0; 1444 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1445 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1446 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1447 1448 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1449 * if it is not our port then ignore 1450 */ 1451 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1452 (port != hw->port)) 1453 return 0; 1454 1455 return gpio_val; 1456 } 1457 1458 #define I40E_COMBINED_ACTIVITY 0xA 1459 #define I40E_FILTER_ACTIVITY 0xE 1460 #define I40E_LINK_ACTIVITY 0xC 1461 #define I40E_MAC_ACTIVITY 0xD 1462 #define I40E_FW_LED BIT(4) 1463 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \ 1464 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 1465 1466 #define I40E_LED0 22 1467 1468 #define I40E_PIN_FUNC_SDP 0x0 1469 #define I40E_PIN_FUNC_LED 0x1 1470 1471 /** 1472 * i40e_led_get - return current on/off mode 1473 * @hw: pointer to the hw struct 1474 * 1475 * The value returned is the 'mode' field as defined in the 1476 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1477 * values are variations of possible behaviors relating to 1478 * blink, link, and wire. 1479 **/ 1480 u32 i40e_led_get(struct i40e_hw *hw) 1481 { 1482 u32 mode = 0; 1483 int i; 1484 1485 /* as per the documentation GPIO 22-29 are the LED 1486 * GPIO pins named LED0..LED7 1487 */ 1488 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1489 u32 gpio_val = i40e_led_is_mine(hw, i); 1490 1491 if (!gpio_val) 1492 continue; 1493 1494 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1495 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1496 break; 1497 } 1498 1499 return mode; 1500 } 1501 1502 /** 1503 * i40e_led_set - set new on/off mode 1504 * @hw: pointer to the hw struct 1505 * @mode: 0=off, 0xf=on (else see manual for mode details) 1506 * @blink: true if the LED should blink when on, false if steady 1507 * 1508 * if this function is used to turn on the blink it should 1509 * be used to disable the blink when restoring the original state. 1510 **/ 1511 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1512 { 1513 int i; 1514 1515 if (mode & ~I40E_LED_MODE_VALID) { 1516 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1517 return; 1518 } 1519 1520 /* as per the documentation GPIO 22-29 are the LED 1521 * GPIO pins named LED0..LED7 1522 */ 1523 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1524 u32 gpio_val = i40e_led_is_mine(hw, i); 1525 1526 if (!gpio_val) 1527 continue; 1528 1529 if (I40E_IS_X710TL_DEVICE(hw->device_id)) { 1530 u32 pin_func = 0; 1531 1532 if (mode & I40E_FW_LED) 1533 pin_func = I40E_PIN_FUNC_SDP; 1534 else 1535 pin_func = I40E_PIN_FUNC_LED; 1536 1537 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK; 1538 gpio_val |= ((pin_func << 1539 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) & 1540 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK); 1541 } 1542 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1543 /* this & is a bit of paranoia, but serves as a range check */ 1544 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1545 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1546 1547 if (blink) 1548 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1549 else 1550 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1551 1552 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1553 break; 1554 } 1555 } 1556 1557 /* Admin command wrappers */ 1558 1559 /** 1560 * i40e_aq_get_phy_capabilities 1561 * @hw: pointer to the hw struct 1562 * @abilities: structure for PHY capabilities to be filled 1563 * @qualified_modules: report Qualified Modules 1564 * @report_init: report init capabilities (active are default) 1565 * @cmd_details: pointer to command details structure or NULL 1566 * 1567 * Returns the various PHY abilities supported on the Port. 1568 **/ 1569 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1570 bool qualified_modules, bool report_init, 1571 struct i40e_aq_get_phy_abilities_resp *abilities, 1572 struct i40e_asq_cmd_details *cmd_details) 1573 { 1574 struct i40e_aq_desc desc; 1575 i40e_status status; 1576 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1577 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1578 1579 if (!abilities) 1580 return I40E_ERR_PARAM; 1581 1582 do { 1583 i40e_fill_default_direct_cmd_desc(&desc, 1584 i40e_aqc_opc_get_phy_abilities); 1585 1586 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1587 if (abilities_size > I40E_AQ_LARGE_BUF) 1588 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1589 1590 if (qualified_modules) 1591 desc.params.external.param0 |= 1592 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1593 1594 if (report_init) 1595 desc.params.external.param0 |= 1596 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1597 1598 status = i40e_asq_send_command(hw, &desc, abilities, 1599 abilities_size, cmd_details); 1600 1601 switch (hw->aq.asq_last_status) { 1602 case I40E_AQ_RC_EIO: 1603 status = I40E_ERR_UNKNOWN_PHY; 1604 break; 1605 case I40E_AQ_RC_EAGAIN: 1606 usleep_range(1000, 2000); 1607 total_delay++; 1608 status = I40E_ERR_TIMEOUT; 1609 break; 1610 /* also covers I40E_AQ_RC_OK */ 1611 default: 1612 break; 1613 } 1614 1615 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) && 1616 (total_delay < max_delay)); 1617 1618 if (status) 1619 return status; 1620 1621 if (report_init) { 1622 if (hw->mac.type == I40E_MAC_XL710 && 1623 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1624 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1625 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1626 } else { 1627 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1628 hw->phy.phy_types |= 1629 ((u64)abilities->phy_type_ext << 32); 1630 } 1631 } 1632 1633 return status; 1634 } 1635 1636 /** 1637 * i40e_aq_set_phy_config 1638 * @hw: pointer to the hw struct 1639 * @config: structure with PHY configuration to be set 1640 * @cmd_details: pointer to command details structure or NULL 1641 * 1642 * Set the various PHY configuration parameters 1643 * supported on the Port.One or more of the Set PHY config parameters may be 1644 * ignored in an MFP mode as the PF may not have the privilege to set some 1645 * of the PHY Config parameters. This status will be indicated by the 1646 * command response. 1647 **/ 1648 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1649 struct i40e_aq_set_phy_config *config, 1650 struct i40e_asq_cmd_details *cmd_details) 1651 { 1652 struct i40e_aq_desc desc; 1653 struct i40e_aq_set_phy_config *cmd = 1654 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1655 enum i40e_status_code status; 1656 1657 if (!config) 1658 return I40E_ERR_PARAM; 1659 1660 i40e_fill_default_direct_cmd_desc(&desc, 1661 i40e_aqc_opc_set_phy_config); 1662 1663 *cmd = *config; 1664 1665 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1666 1667 return status; 1668 } 1669 1670 static noinline_for_stack enum i40e_status_code 1671 i40e_set_fc_status(struct i40e_hw *hw, 1672 struct i40e_aq_get_phy_abilities_resp *abilities, 1673 bool atomic_restart) 1674 { 1675 struct i40e_aq_set_phy_config config; 1676 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1677 u8 pause_mask = 0x0; 1678 1679 switch (fc_mode) { 1680 case I40E_FC_FULL: 1681 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1682 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1683 break; 1684 case I40E_FC_RX_PAUSE: 1685 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1686 break; 1687 case I40E_FC_TX_PAUSE: 1688 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1689 break; 1690 default: 1691 break; 1692 } 1693 1694 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1695 /* clear the old pause settings */ 1696 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1697 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1698 /* set the new abilities */ 1699 config.abilities |= pause_mask; 1700 /* If the abilities have changed, then set the new config */ 1701 if (config.abilities == abilities->abilities) 1702 return 0; 1703 1704 /* Auto restart link so settings take effect */ 1705 if (atomic_restart) 1706 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1707 /* Copy over all the old settings */ 1708 config.phy_type = abilities->phy_type; 1709 config.phy_type_ext = abilities->phy_type_ext; 1710 config.link_speed = abilities->link_speed; 1711 config.eee_capability = abilities->eee_capability; 1712 config.eeer = abilities->eeer_val; 1713 config.low_power_ctrl = abilities->d3_lpan; 1714 config.fec_config = abilities->fec_cfg_curr_mod_ext_info & 1715 I40E_AQ_PHY_FEC_CONFIG_MASK; 1716 1717 return i40e_aq_set_phy_config(hw, &config, NULL); 1718 } 1719 1720 /** 1721 * i40e_set_fc 1722 * @hw: pointer to the hw struct 1723 * @aq_failures: buffer to return AdminQ failure information 1724 * @atomic_restart: whether to enable atomic link restart 1725 * 1726 * Set the requested flow control mode using set_phy_config. 1727 **/ 1728 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1729 bool atomic_restart) 1730 { 1731 struct i40e_aq_get_phy_abilities_resp abilities; 1732 enum i40e_status_code status; 1733 1734 *aq_failures = 0x0; 1735 1736 /* Get the current phy config */ 1737 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1738 NULL); 1739 if (status) { 1740 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1741 return status; 1742 } 1743 1744 status = i40e_set_fc_status(hw, &abilities, atomic_restart); 1745 if (status) 1746 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1747 1748 /* Update the link info */ 1749 status = i40e_update_link_info(hw); 1750 if (status) { 1751 /* Wait a little bit (on 40G cards it sometimes takes a really 1752 * long time for link to come back from the atomic reset) 1753 * and try once more 1754 */ 1755 msleep(1000); 1756 status = i40e_update_link_info(hw); 1757 } 1758 if (status) 1759 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1760 1761 return status; 1762 } 1763 1764 /** 1765 * i40e_aq_clear_pxe_mode 1766 * @hw: pointer to the hw struct 1767 * @cmd_details: pointer to command details structure or NULL 1768 * 1769 * Tell the firmware that the driver is taking over from PXE 1770 **/ 1771 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1772 struct i40e_asq_cmd_details *cmd_details) 1773 { 1774 i40e_status status; 1775 struct i40e_aq_desc desc; 1776 struct i40e_aqc_clear_pxe *cmd = 1777 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1778 1779 i40e_fill_default_direct_cmd_desc(&desc, 1780 i40e_aqc_opc_clear_pxe_mode); 1781 1782 cmd->rx_cnt = 0x2; 1783 1784 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1785 1786 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1787 1788 return status; 1789 } 1790 1791 /** 1792 * i40e_aq_set_link_restart_an 1793 * @hw: pointer to the hw struct 1794 * @enable_link: if true: enable link, if false: disable link 1795 * @cmd_details: pointer to command details structure or NULL 1796 * 1797 * Sets up the link and restarts the Auto-Negotiation over the link. 1798 **/ 1799 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1800 bool enable_link, 1801 struct i40e_asq_cmd_details *cmd_details) 1802 { 1803 struct i40e_aq_desc desc; 1804 struct i40e_aqc_set_link_restart_an *cmd = 1805 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1806 i40e_status status; 1807 1808 i40e_fill_default_direct_cmd_desc(&desc, 1809 i40e_aqc_opc_set_link_restart_an); 1810 1811 cmd->command = I40E_AQ_PHY_RESTART_AN; 1812 if (enable_link) 1813 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1814 else 1815 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1816 1817 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1818 1819 return status; 1820 } 1821 1822 /** 1823 * i40e_aq_get_link_info 1824 * @hw: pointer to the hw struct 1825 * @enable_lse: enable/disable LinkStatusEvent reporting 1826 * @link: pointer to link status structure - optional 1827 * @cmd_details: pointer to command details structure or NULL 1828 * 1829 * Returns the link status of the adapter. 1830 **/ 1831 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1832 bool enable_lse, struct i40e_link_status *link, 1833 struct i40e_asq_cmd_details *cmd_details) 1834 { 1835 struct i40e_aq_desc desc; 1836 struct i40e_aqc_get_link_status *resp = 1837 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1838 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1839 i40e_status status; 1840 bool tx_pause, rx_pause; 1841 u16 command_flags; 1842 1843 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1844 1845 if (enable_lse) 1846 command_flags = I40E_AQ_LSE_ENABLE; 1847 else 1848 command_flags = I40E_AQ_LSE_DISABLE; 1849 resp->command_flags = cpu_to_le16(command_flags); 1850 1851 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1852 1853 if (status) 1854 goto aq_get_link_info_exit; 1855 1856 /* save off old link status information */ 1857 hw->phy.link_info_old = *hw_link_info; 1858 1859 /* update link status */ 1860 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1861 hw->phy.media_type = i40e_get_media_type(hw); 1862 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1863 hw_link_info->link_info = resp->link_info; 1864 hw_link_info->an_info = resp->an_info; 1865 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1866 I40E_AQ_CONFIG_FEC_RS_ENA); 1867 hw_link_info->ext_info = resp->ext_info; 1868 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1869 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1870 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1871 1872 /* update fc info */ 1873 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1874 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1875 if (tx_pause & rx_pause) 1876 hw->fc.current_mode = I40E_FC_FULL; 1877 else if (tx_pause) 1878 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1879 else if (rx_pause) 1880 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1881 else 1882 hw->fc.current_mode = I40E_FC_NONE; 1883 1884 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1885 hw_link_info->crc_enable = true; 1886 else 1887 hw_link_info->crc_enable = false; 1888 1889 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1890 hw_link_info->lse_enable = true; 1891 else 1892 hw_link_info->lse_enable = false; 1893 1894 if ((hw->mac.type == I40E_MAC_XL710) && 1895 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1896 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1897 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1898 1899 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 1900 __le32 tmp; 1901 1902 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1903 hw->phy.phy_types = le32_to_cpu(tmp); 1904 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1905 } 1906 1907 /* save link status information */ 1908 if (link) 1909 *link = *hw_link_info; 1910 1911 /* flag cleared so helper functions don't call AQ again */ 1912 hw->phy.get_link_info = false; 1913 1914 aq_get_link_info_exit: 1915 return status; 1916 } 1917 1918 /** 1919 * i40e_aq_set_phy_int_mask 1920 * @hw: pointer to the hw struct 1921 * @mask: interrupt mask to be set 1922 * @cmd_details: pointer to command details structure or NULL 1923 * 1924 * Set link interrupt mask. 1925 **/ 1926 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1927 u16 mask, 1928 struct i40e_asq_cmd_details *cmd_details) 1929 { 1930 struct i40e_aq_desc desc; 1931 struct i40e_aqc_set_phy_int_mask *cmd = 1932 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1933 i40e_status status; 1934 1935 i40e_fill_default_direct_cmd_desc(&desc, 1936 i40e_aqc_opc_set_phy_int_mask); 1937 1938 cmd->event_mask = cpu_to_le16(mask); 1939 1940 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1941 1942 return status; 1943 } 1944 1945 /** 1946 * i40e_aq_set_phy_debug 1947 * @hw: pointer to the hw struct 1948 * @cmd_flags: debug command flags 1949 * @cmd_details: pointer to command details structure or NULL 1950 * 1951 * Reset the external PHY. 1952 **/ 1953 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1954 struct i40e_asq_cmd_details *cmd_details) 1955 { 1956 struct i40e_aq_desc desc; 1957 struct i40e_aqc_set_phy_debug *cmd = 1958 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1959 i40e_status status; 1960 1961 i40e_fill_default_direct_cmd_desc(&desc, 1962 i40e_aqc_opc_set_phy_debug); 1963 1964 cmd->command_flags = cmd_flags; 1965 1966 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1967 1968 return status; 1969 } 1970 1971 /** 1972 * i40e_aq_add_vsi 1973 * @hw: pointer to the hw struct 1974 * @vsi_ctx: pointer to a vsi context struct 1975 * @cmd_details: pointer to command details structure or NULL 1976 * 1977 * Add a VSI context to the hardware. 1978 **/ 1979 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1980 struct i40e_vsi_context *vsi_ctx, 1981 struct i40e_asq_cmd_details *cmd_details) 1982 { 1983 struct i40e_aq_desc desc; 1984 struct i40e_aqc_add_get_update_vsi *cmd = 1985 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1986 struct i40e_aqc_add_get_update_vsi_completion *resp = 1987 (struct i40e_aqc_add_get_update_vsi_completion *) 1988 &desc.params.raw; 1989 i40e_status status; 1990 1991 i40e_fill_default_direct_cmd_desc(&desc, 1992 i40e_aqc_opc_add_vsi); 1993 1994 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1995 cmd->connection_type = vsi_ctx->connection_type; 1996 cmd->vf_id = vsi_ctx->vf_num; 1997 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1998 1999 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2000 2001 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2002 sizeof(vsi_ctx->info), cmd_details); 2003 2004 if (status) 2005 goto aq_add_vsi_exit; 2006 2007 vsi_ctx->seid = le16_to_cpu(resp->seid); 2008 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2009 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2010 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2011 2012 aq_add_vsi_exit: 2013 return status; 2014 } 2015 2016 /** 2017 * i40e_aq_set_default_vsi 2018 * @hw: pointer to the hw struct 2019 * @seid: vsi number 2020 * @cmd_details: pointer to command details structure or NULL 2021 **/ 2022 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 2023 u16 seid, 2024 struct i40e_asq_cmd_details *cmd_details) 2025 { 2026 struct i40e_aq_desc desc; 2027 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2028 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2029 &desc.params.raw; 2030 i40e_status status; 2031 2032 i40e_fill_default_direct_cmd_desc(&desc, 2033 i40e_aqc_opc_set_vsi_promiscuous_modes); 2034 2035 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2036 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2037 cmd->seid = cpu_to_le16(seid); 2038 2039 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2040 2041 return status; 2042 } 2043 2044 /** 2045 * i40e_aq_clear_default_vsi 2046 * @hw: pointer to the hw struct 2047 * @seid: vsi number 2048 * @cmd_details: pointer to command details structure or NULL 2049 **/ 2050 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2051 u16 seid, 2052 struct i40e_asq_cmd_details *cmd_details) 2053 { 2054 struct i40e_aq_desc desc; 2055 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2056 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2057 &desc.params.raw; 2058 i40e_status status; 2059 2060 i40e_fill_default_direct_cmd_desc(&desc, 2061 i40e_aqc_opc_set_vsi_promiscuous_modes); 2062 2063 cmd->promiscuous_flags = cpu_to_le16(0); 2064 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2065 cmd->seid = cpu_to_le16(seid); 2066 2067 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2068 2069 return status; 2070 } 2071 2072 /** 2073 * i40e_aq_set_vsi_unicast_promiscuous 2074 * @hw: pointer to the hw struct 2075 * @seid: vsi number 2076 * @set: set unicast promiscuous enable/disable 2077 * @cmd_details: pointer to command details structure or NULL 2078 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2079 **/ 2080 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2081 u16 seid, bool set, 2082 struct i40e_asq_cmd_details *cmd_details, 2083 bool rx_only_promisc) 2084 { 2085 struct i40e_aq_desc desc; 2086 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2087 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2088 i40e_status status; 2089 u16 flags = 0; 2090 2091 i40e_fill_default_direct_cmd_desc(&desc, 2092 i40e_aqc_opc_set_vsi_promiscuous_modes); 2093 2094 if (set) { 2095 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2096 if (rx_only_promisc && 2097 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2098 (hw->aq.api_maj_ver > 1))) 2099 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2100 } 2101 2102 cmd->promiscuous_flags = cpu_to_le16(flags); 2103 2104 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2105 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2106 (hw->aq.api_maj_ver > 1)) 2107 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX); 2108 2109 cmd->seid = cpu_to_le16(seid); 2110 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2111 2112 return status; 2113 } 2114 2115 /** 2116 * i40e_aq_set_vsi_multicast_promiscuous 2117 * @hw: pointer to the hw struct 2118 * @seid: vsi number 2119 * @set: set multicast promiscuous enable/disable 2120 * @cmd_details: pointer to command details structure or NULL 2121 **/ 2122 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2123 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2124 { 2125 struct i40e_aq_desc desc; 2126 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2127 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2128 i40e_status status; 2129 u16 flags = 0; 2130 2131 i40e_fill_default_direct_cmd_desc(&desc, 2132 i40e_aqc_opc_set_vsi_promiscuous_modes); 2133 2134 if (set) 2135 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2136 2137 cmd->promiscuous_flags = cpu_to_le16(flags); 2138 2139 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2140 2141 cmd->seid = cpu_to_le16(seid); 2142 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2143 2144 return status; 2145 } 2146 2147 /** 2148 * i40e_aq_set_vsi_mc_promisc_on_vlan 2149 * @hw: pointer to the hw struct 2150 * @seid: vsi number 2151 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2152 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2153 * @cmd_details: pointer to command details structure or NULL 2154 **/ 2155 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2156 u16 seid, bool enable, 2157 u16 vid, 2158 struct i40e_asq_cmd_details *cmd_details) 2159 { 2160 struct i40e_aq_desc desc; 2161 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2162 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2163 enum i40e_status_code status; 2164 u16 flags = 0; 2165 2166 i40e_fill_default_direct_cmd_desc(&desc, 2167 i40e_aqc_opc_set_vsi_promiscuous_modes); 2168 2169 if (enable) 2170 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2171 2172 cmd->promiscuous_flags = cpu_to_le16(flags); 2173 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2174 cmd->seid = cpu_to_le16(seid); 2175 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2176 2177 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2178 2179 return status; 2180 } 2181 2182 /** 2183 * i40e_aq_set_vsi_uc_promisc_on_vlan 2184 * @hw: pointer to the hw struct 2185 * @seid: vsi number 2186 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2187 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2188 * @cmd_details: pointer to command details structure or NULL 2189 **/ 2190 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2191 u16 seid, bool enable, 2192 u16 vid, 2193 struct i40e_asq_cmd_details *cmd_details) 2194 { 2195 struct i40e_aq_desc desc; 2196 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2197 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2198 enum i40e_status_code status; 2199 u16 flags = 0; 2200 2201 i40e_fill_default_direct_cmd_desc(&desc, 2202 i40e_aqc_opc_set_vsi_promiscuous_modes); 2203 2204 if (enable) 2205 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2206 2207 cmd->promiscuous_flags = cpu_to_le16(flags); 2208 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2209 cmd->seid = cpu_to_le16(seid); 2210 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2211 2212 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2213 2214 return status; 2215 } 2216 2217 /** 2218 * i40e_aq_set_vsi_bc_promisc_on_vlan 2219 * @hw: pointer to the hw struct 2220 * @seid: vsi number 2221 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2222 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2223 * @cmd_details: pointer to command details structure or NULL 2224 **/ 2225 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2226 u16 seid, bool enable, u16 vid, 2227 struct i40e_asq_cmd_details *cmd_details) 2228 { 2229 struct i40e_aq_desc desc; 2230 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2231 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2232 i40e_status status; 2233 u16 flags = 0; 2234 2235 i40e_fill_default_direct_cmd_desc(&desc, 2236 i40e_aqc_opc_set_vsi_promiscuous_modes); 2237 2238 if (enable) 2239 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2240 2241 cmd->promiscuous_flags = cpu_to_le16(flags); 2242 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2243 cmd->seid = cpu_to_le16(seid); 2244 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2245 2246 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2247 2248 return status; 2249 } 2250 2251 /** 2252 * i40e_aq_set_vsi_broadcast 2253 * @hw: pointer to the hw struct 2254 * @seid: vsi number 2255 * @set_filter: true to set filter, false to clear filter 2256 * @cmd_details: pointer to command details structure or NULL 2257 * 2258 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2259 **/ 2260 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2261 u16 seid, bool set_filter, 2262 struct i40e_asq_cmd_details *cmd_details) 2263 { 2264 struct i40e_aq_desc desc; 2265 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2266 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2267 i40e_status status; 2268 2269 i40e_fill_default_direct_cmd_desc(&desc, 2270 i40e_aqc_opc_set_vsi_promiscuous_modes); 2271 2272 if (set_filter) 2273 cmd->promiscuous_flags 2274 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2275 else 2276 cmd->promiscuous_flags 2277 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2278 2279 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2280 cmd->seid = cpu_to_le16(seid); 2281 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2282 2283 return status; 2284 } 2285 2286 /** 2287 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2288 * @hw: pointer to the hw struct 2289 * @seid: vsi number 2290 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2291 * @cmd_details: pointer to command details structure or NULL 2292 **/ 2293 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2294 u16 seid, bool enable, 2295 struct i40e_asq_cmd_details *cmd_details) 2296 { 2297 struct i40e_aq_desc desc; 2298 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2299 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2300 i40e_status status; 2301 u16 flags = 0; 2302 2303 i40e_fill_default_direct_cmd_desc(&desc, 2304 i40e_aqc_opc_set_vsi_promiscuous_modes); 2305 if (enable) 2306 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2307 2308 cmd->promiscuous_flags = cpu_to_le16(flags); 2309 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2310 cmd->seid = cpu_to_le16(seid); 2311 2312 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2313 2314 return status; 2315 } 2316 2317 /** 2318 * i40e_get_vsi_params - get VSI configuration info 2319 * @hw: pointer to the hw struct 2320 * @vsi_ctx: pointer to a vsi context struct 2321 * @cmd_details: pointer to command details structure or NULL 2322 **/ 2323 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2324 struct i40e_vsi_context *vsi_ctx, 2325 struct i40e_asq_cmd_details *cmd_details) 2326 { 2327 struct i40e_aq_desc desc; 2328 struct i40e_aqc_add_get_update_vsi *cmd = 2329 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2330 struct i40e_aqc_add_get_update_vsi_completion *resp = 2331 (struct i40e_aqc_add_get_update_vsi_completion *) 2332 &desc.params.raw; 2333 i40e_status status; 2334 2335 i40e_fill_default_direct_cmd_desc(&desc, 2336 i40e_aqc_opc_get_vsi_parameters); 2337 2338 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2339 2340 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2341 2342 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2343 sizeof(vsi_ctx->info), NULL); 2344 2345 if (status) 2346 goto aq_get_vsi_params_exit; 2347 2348 vsi_ctx->seid = le16_to_cpu(resp->seid); 2349 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2350 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2351 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2352 2353 aq_get_vsi_params_exit: 2354 return status; 2355 } 2356 2357 /** 2358 * i40e_aq_update_vsi_params 2359 * @hw: pointer to the hw struct 2360 * @vsi_ctx: pointer to a vsi context struct 2361 * @cmd_details: pointer to command details structure or NULL 2362 * 2363 * Update a VSI context. 2364 **/ 2365 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2366 struct i40e_vsi_context *vsi_ctx, 2367 struct i40e_asq_cmd_details *cmd_details) 2368 { 2369 struct i40e_aq_desc desc; 2370 struct i40e_aqc_add_get_update_vsi *cmd = 2371 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2372 struct i40e_aqc_add_get_update_vsi_completion *resp = 2373 (struct i40e_aqc_add_get_update_vsi_completion *) 2374 &desc.params.raw; 2375 i40e_status status; 2376 2377 i40e_fill_default_direct_cmd_desc(&desc, 2378 i40e_aqc_opc_update_vsi_parameters); 2379 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2380 2381 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2382 2383 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2384 sizeof(vsi_ctx->info), cmd_details); 2385 2386 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2387 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2388 2389 return status; 2390 } 2391 2392 /** 2393 * i40e_aq_get_switch_config 2394 * @hw: pointer to the hardware structure 2395 * @buf: pointer to the result buffer 2396 * @buf_size: length of input buffer 2397 * @start_seid: seid to start for the report, 0 == beginning 2398 * @cmd_details: pointer to command details structure or NULL 2399 * 2400 * Fill the buf with switch configuration returned from AdminQ command 2401 **/ 2402 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2403 struct i40e_aqc_get_switch_config_resp *buf, 2404 u16 buf_size, u16 *start_seid, 2405 struct i40e_asq_cmd_details *cmd_details) 2406 { 2407 struct i40e_aq_desc desc; 2408 struct i40e_aqc_switch_seid *scfg = 2409 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2410 i40e_status status; 2411 2412 i40e_fill_default_direct_cmd_desc(&desc, 2413 i40e_aqc_opc_get_switch_config); 2414 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2415 if (buf_size > I40E_AQ_LARGE_BUF) 2416 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2417 scfg->seid = cpu_to_le16(*start_seid); 2418 2419 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2420 *start_seid = le16_to_cpu(scfg->seid); 2421 2422 return status; 2423 } 2424 2425 /** 2426 * i40e_aq_set_switch_config 2427 * @hw: pointer to the hardware structure 2428 * @flags: bit flag values to set 2429 * @mode: cloud filter mode 2430 * @valid_flags: which bit flags to set 2431 * @mode: cloud filter mode 2432 * @cmd_details: pointer to command details structure or NULL 2433 * 2434 * Set switch configuration bits 2435 **/ 2436 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2437 u16 flags, 2438 u16 valid_flags, u8 mode, 2439 struct i40e_asq_cmd_details *cmd_details) 2440 { 2441 struct i40e_aq_desc desc; 2442 struct i40e_aqc_set_switch_config *scfg = 2443 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2444 enum i40e_status_code status; 2445 2446 i40e_fill_default_direct_cmd_desc(&desc, 2447 i40e_aqc_opc_set_switch_config); 2448 scfg->flags = cpu_to_le16(flags); 2449 scfg->valid_flags = cpu_to_le16(valid_flags); 2450 scfg->mode = mode; 2451 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2452 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 2453 scfg->first_tag = cpu_to_le16(hw->first_tag); 2454 scfg->second_tag = cpu_to_le16(hw->second_tag); 2455 } 2456 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2457 2458 return status; 2459 } 2460 2461 /** 2462 * i40e_aq_get_firmware_version 2463 * @hw: pointer to the hw struct 2464 * @fw_major_version: firmware major version 2465 * @fw_minor_version: firmware minor version 2466 * @fw_build: firmware build number 2467 * @api_major_version: major queue version 2468 * @api_minor_version: minor queue version 2469 * @cmd_details: pointer to command details structure or NULL 2470 * 2471 * Get the firmware version from the admin queue commands 2472 **/ 2473 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2474 u16 *fw_major_version, u16 *fw_minor_version, 2475 u32 *fw_build, 2476 u16 *api_major_version, u16 *api_minor_version, 2477 struct i40e_asq_cmd_details *cmd_details) 2478 { 2479 struct i40e_aq_desc desc; 2480 struct i40e_aqc_get_version *resp = 2481 (struct i40e_aqc_get_version *)&desc.params.raw; 2482 i40e_status status; 2483 2484 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2485 2486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2487 2488 if (!status) { 2489 if (fw_major_version) 2490 *fw_major_version = le16_to_cpu(resp->fw_major); 2491 if (fw_minor_version) 2492 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2493 if (fw_build) 2494 *fw_build = le32_to_cpu(resp->fw_build); 2495 if (api_major_version) 2496 *api_major_version = le16_to_cpu(resp->api_major); 2497 if (api_minor_version) 2498 *api_minor_version = le16_to_cpu(resp->api_minor); 2499 } 2500 2501 return status; 2502 } 2503 2504 /** 2505 * i40e_aq_send_driver_version 2506 * @hw: pointer to the hw struct 2507 * @dv: driver's major, minor version 2508 * @cmd_details: pointer to command details structure or NULL 2509 * 2510 * Send the driver version to the firmware 2511 **/ 2512 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2513 struct i40e_driver_version *dv, 2514 struct i40e_asq_cmd_details *cmd_details) 2515 { 2516 struct i40e_aq_desc desc; 2517 struct i40e_aqc_driver_version *cmd = 2518 (struct i40e_aqc_driver_version *)&desc.params.raw; 2519 i40e_status status; 2520 u16 len; 2521 2522 if (dv == NULL) 2523 return I40E_ERR_PARAM; 2524 2525 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2526 2527 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2528 cmd->driver_major_ver = dv->major_version; 2529 cmd->driver_minor_ver = dv->minor_version; 2530 cmd->driver_build_ver = dv->build_version; 2531 cmd->driver_subbuild_ver = dv->subbuild_version; 2532 2533 len = 0; 2534 while (len < sizeof(dv->driver_string) && 2535 (dv->driver_string[len] < 0x80) && 2536 dv->driver_string[len]) 2537 len++; 2538 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2539 len, cmd_details); 2540 2541 return status; 2542 } 2543 2544 /** 2545 * i40e_get_link_status - get status of the HW network link 2546 * @hw: pointer to the hw struct 2547 * @link_up: pointer to bool (true/false = linkup/linkdown) 2548 * 2549 * Variable link_up true if link is up, false if link is down. 2550 * The variable link_up is invalid if returned value of status != 0 2551 * 2552 * Side effect: LinkStatusEvent reporting becomes enabled 2553 **/ 2554 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2555 { 2556 i40e_status status = 0; 2557 2558 if (hw->phy.get_link_info) { 2559 status = i40e_update_link_info(hw); 2560 2561 if (status) 2562 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2563 status); 2564 } 2565 2566 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2567 2568 return status; 2569 } 2570 2571 /** 2572 * i40e_updatelink_status - update status of the HW network link 2573 * @hw: pointer to the hw struct 2574 **/ 2575 noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw) 2576 { 2577 struct i40e_aq_get_phy_abilities_resp abilities; 2578 i40e_status status = 0; 2579 2580 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2581 if (status) 2582 return status; 2583 2584 /* extra checking needed to ensure link info to user is timely */ 2585 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2586 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2587 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2588 status = i40e_aq_get_phy_capabilities(hw, false, false, 2589 &abilities, NULL); 2590 if (status) 2591 return status; 2592 2593 if (abilities.fec_cfg_curr_mod_ext_info & 2594 I40E_AQ_ENABLE_FEC_AUTO) 2595 hw->phy.link_info.req_fec_info = 2596 (I40E_AQ_REQUEST_FEC_KR | 2597 I40E_AQ_REQUEST_FEC_RS); 2598 else 2599 hw->phy.link_info.req_fec_info = 2600 abilities.fec_cfg_curr_mod_ext_info & 2601 (I40E_AQ_REQUEST_FEC_KR | 2602 I40E_AQ_REQUEST_FEC_RS); 2603 2604 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2605 sizeof(hw->phy.link_info.module_type)); 2606 } 2607 2608 return status; 2609 } 2610 2611 /** 2612 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2613 * @hw: pointer to the hw struct 2614 * @uplink_seid: the MAC or other gizmo SEID 2615 * @downlink_seid: the VSI SEID 2616 * @enabled_tc: bitmap of TCs to be enabled 2617 * @default_port: true for default port VSI, false for control port 2618 * @veb_seid: pointer to where to put the resulting VEB SEID 2619 * @enable_stats: true to turn on VEB stats 2620 * @cmd_details: pointer to command details structure or NULL 2621 * 2622 * This asks the FW to add a VEB between the uplink and downlink 2623 * elements. If the uplink SEID is 0, this will be a floating VEB. 2624 **/ 2625 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2626 u16 downlink_seid, u8 enabled_tc, 2627 bool default_port, u16 *veb_seid, 2628 bool enable_stats, 2629 struct i40e_asq_cmd_details *cmd_details) 2630 { 2631 struct i40e_aq_desc desc; 2632 struct i40e_aqc_add_veb *cmd = 2633 (struct i40e_aqc_add_veb *)&desc.params.raw; 2634 struct i40e_aqc_add_veb_completion *resp = 2635 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2636 i40e_status status; 2637 u16 veb_flags = 0; 2638 2639 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2640 if (!!uplink_seid != !!downlink_seid) 2641 return I40E_ERR_PARAM; 2642 2643 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2644 2645 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2646 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2647 cmd->enable_tcs = enabled_tc; 2648 if (!uplink_seid) 2649 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2650 if (default_port) 2651 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2652 else 2653 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2654 2655 /* reverse logic here: set the bitflag to disable the stats */ 2656 if (!enable_stats) 2657 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2658 2659 cmd->veb_flags = cpu_to_le16(veb_flags); 2660 2661 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2662 2663 if (!status && veb_seid) 2664 *veb_seid = le16_to_cpu(resp->veb_seid); 2665 2666 return status; 2667 } 2668 2669 /** 2670 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2671 * @hw: pointer to the hw struct 2672 * @veb_seid: the SEID of the VEB to query 2673 * @switch_id: the uplink switch id 2674 * @floating: set to true if the VEB is floating 2675 * @statistic_index: index of the stats counter block for this VEB 2676 * @vebs_used: number of VEB's used by function 2677 * @vebs_free: total VEB's not reserved by any function 2678 * @cmd_details: pointer to command details structure or NULL 2679 * 2680 * This retrieves the parameters for a particular VEB, specified by 2681 * uplink_seid, and returns them to the caller. 2682 **/ 2683 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2684 u16 veb_seid, u16 *switch_id, 2685 bool *floating, u16 *statistic_index, 2686 u16 *vebs_used, u16 *vebs_free, 2687 struct i40e_asq_cmd_details *cmd_details) 2688 { 2689 struct i40e_aq_desc desc; 2690 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2691 (struct i40e_aqc_get_veb_parameters_completion *) 2692 &desc.params.raw; 2693 i40e_status status; 2694 2695 if (veb_seid == 0) 2696 return I40E_ERR_PARAM; 2697 2698 i40e_fill_default_direct_cmd_desc(&desc, 2699 i40e_aqc_opc_get_veb_parameters); 2700 cmd_resp->seid = cpu_to_le16(veb_seid); 2701 2702 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2703 if (status) 2704 goto get_veb_exit; 2705 2706 if (switch_id) 2707 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2708 if (statistic_index) 2709 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2710 if (vebs_used) 2711 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2712 if (vebs_free) 2713 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2714 if (floating) { 2715 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2716 2717 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2718 *floating = true; 2719 else 2720 *floating = false; 2721 } 2722 2723 get_veb_exit: 2724 return status; 2725 } 2726 2727 /** 2728 * i40e_aq_add_macvlan 2729 * @hw: pointer to the hw struct 2730 * @seid: VSI for the mac address 2731 * @mv_list: list of macvlans to be added 2732 * @count: length of the list 2733 * @cmd_details: pointer to command details structure or NULL 2734 * 2735 * Add MAC/VLAN addresses to the HW filtering 2736 **/ 2737 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2738 struct i40e_aqc_add_macvlan_element_data *mv_list, 2739 u16 count, struct i40e_asq_cmd_details *cmd_details) 2740 { 2741 struct i40e_aq_desc desc; 2742 struct i40e_aqc_macvlan *cmd = 2743 (struct i40e_aqc_macvlan *)&desc.params.raw; 2744 i40e_status status; 2745 u16 buf_size; 2746 int i; 2747 2748 if (count == 0 || !mv_list || !hw) 2749 return I40E_ERR_PARAM; 2750 2751 buf_size = count * sizeof(*mv_list); 2752 2753 /* prep the rest of the request */ 2754 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2755 cmd->num_addresses = cpu_to_le16(count); 2756 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2757 cmd->seid[1] = 0; 2758 cmd->seid[2] = 0; 2759 2760 for (i = 0; i < count; i++) 2761 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2762 mv_list[i].flags |= 2763 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2764 2765 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2766 if (buf_size > I40E_AQ_LARGE_BUF) 2767 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2768 2769 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2770 cmd_details); 2771 2772 return status; 2773 } 2774 2775 /** 2776 * i40e_aq_remove_macvlan 2777 * @hw: pointer to the hw struct 2778 * @seid: VSI for the mac address 2779 * @mv_list: list of macvlans to be removed 2780 * @count: length of the list 2781 * @cmd_details: pointer to command details structure or NULL 2782 * 2783 * Remove MAC/VLAN addresses from the HW filtering 2784 **/ 2785 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2786 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2787 u16 count, struct i40e_asq_cmd_details *cmd_details) 2788 { 2789 struct i40e_aq_desc desc; 2790 struct i40e_aqc_macvlan *cmd = 2791 (struct i40e_aqc_macvlan *)&desc.params.raw; 2792 i40e_status status; 2793 u16 buf_size; 2794 2795 if (count == 0 || !mv_list || !hw) 2796 return I40E_ERR_PARAM; 2797 2798 buf_size = count * sizeof(*mv_list); 2799 2800 /* prep the rest of the request */ 2801 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2802 cmd->num_addresses = cpu_to_le16(count); 2803 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2804 cmd->seid[1] = 0; 2805 cmd->seid[2] = 0; 2806 2807 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2808 if (buf_size > I40E_AQ_LARGE_BUF) 2809 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2810 2811 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2812 cmd_details); 2813 2814 return status; 2815 } 2816 2817 /** 2818 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2819 * @hw: pointer to the hw struct 2820 * @opcode: AQ opcode for add or delete mirror rule 2821 * @sw_seid: Switch SEID (to which rule refers) 2822 * @rule_type: Rule Type (ingress/egress/VLAN) 2823 * @id: Destination VSI SEID or Rule ID 2824 * @count: length of the list 2825 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2826 * @cmd_details: pointer to command details structure or NULL 2827 * @rule_id: Rule ID returned from FW 2828 * @rules_used: Number of rules used in internal switch 2829 * @rules_free: Number of rules free in internal switch 2830 * 2831 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2832 * VEBs/VEPA elements only 2833 **/ 2834 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2835 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2836 u16 count, __le16 *mr_list, 2837 struct i40e_asq_cmd_details *cmd_details, 2838 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2839 { 2840 struct i40e_aq_desc desc; 2841 struct i40e_aqc_add_delete_mirror_rule *cmd = 2842 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2843 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2844 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2845 i40e_status status; 2846 u16 buf_size; 2847 2848 buf_size = count * sizeof(*mr_list); 2849 2850 /* prep the rest of the request */ 2851 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2852 cmd->seid = cpu_to_le16(sw_seid); 2853 cmd->rule_type = cpu_to_le16(rule_type & 2854 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2855 cmd->num_entries = cpu_to_le16(count); 2856 /* Dest VSI for add, rule_id for delete */ 2857 cmd->destination = cpu_to_le16(id); 2858 if (mr_list) { 2859 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2860 I40E_AQ_FLAG_RD)); 2861 if (buf_size > I40E_AQ_LARGE_BUF) 2862 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2863 } 2864 2865 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2866 cmd_details); 2867 if (!status || 2868 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2869 if (rule_id) 2870 *rule_id = le16_to_cpu(resp->rule_id); 2871 if (rules_used) 2872 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2873 if (rules_free) 2874 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2875 } 2876 return status; 2877 } 2878 2879 /** 2880 * i40e_aq_add_mirrorrule - add a mirror rule 2881 * @hw: pointer to the hw struct 2882 * @sw_seid: Switch SEID (to which rule refers) 2883 * @rule_type: Rule Type (ingress/egress/VLAN) 2884 * @dest_vsi: SEID of VSI to which packets will be mirrored 2885 * @count: length of the list 2886 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2887 * @cmd_details: pointer to command details structure or NULL 2888 * @rule_id: Rule ID returned from FW 2889 * @rules_used: Number of rules used in internal switch 2890 * @rules_free: Number of rules free in internal switch 2891 * 2892 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2893 **/ 2894 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2895 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2896 struct i40e_asq_cmd_details *cmd_details, 2897 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2898 { 2899 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2900 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2901 if (count == 0 || !mr_list) 2902 return I40E_ERR_PARAM; 2903 } 2904 2905 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2906 rule_type, dest_vsi, count, mr_list, 2907 cmd_details, rule_id, rules_used, rules_free); 2908 } 2909 2910 /** 2911 * i40e_aq_delete_mirrorrule - delete a mirror rule 2912 * @hw: pointer to the hw struct 2913 * @sw_seid: Switch SEID (to which rule refers) 2914 * @rule_type: Rule Type (ingress/egress/VLAN) 2915 * @count: length of the list 2916 * @rule_id: Rule ID that is returned in the receive desc as part of 2917 * add_mirrorrule. 2918 * @mr_list: list of mirrored VLAN IDs to be removed 2919 * @cmd_details: pointer to command details structure or NULL 2920 * @rules_used: Number of rules used in internal switch 2921 * @rules_free: Number of rules free in internal switch 2922 * 2923 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2924 **/ 2925 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2926 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2927 struct i40e_asq_cmd_details *cmd_details, 2928 u16 *rules_used, u16 *rules_free) 2929 { 2930 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2931 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2932 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2933 * mirroring. For other rule_type, count and rule_type should 2934 * not matter. 2935 */ 2936 if (count == 0 || !mr_list) 2937 return I40E_ERR_PARAM; 2938 } 2939 2940 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2941 rule_type, rule_id, count, mr_list, 2942 cmd_details, NULL, rules_used, rules_free); 2943 } 2944 2945 /** 2946 * i40e_aq_send_msg_to_vf 2947 * @hw: pointer to the hardware structure 2948 * @vfid: VF id to send msg 2949 * @v_opcode: opcodes for VF-PF communication 2950 * @v_retval: return error code 2951 * @msg: pointer to the msg buffer 2952 * @msglen: msg length 2953 * @cmd_details: pointer to command details 2954 * 2955 * send msg to vf 2956 **/ 2957 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2958 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2959 struct i40e_asq_cmd_details *cmd_details) 2960 { 2961 struct i40e_aq_desc desc; 2962 struct i40e_aqc_pf_vf_message *cmd = 2963 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2964 i40e_status status; 2965 2966 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2967 cmd->id = cpu_to_le32(vfid); 2968 desc.cookie_high = cpu_to_le32(v_opcode); 2969 desc.cookie_low = cpu_to_le32(v_retval); 2970 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2971 if (msglen) { 2972 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2973 I40E_AQ_FLAG_RD)); 2974 if (msglen > I40E_AQ_LARGE_BUF) 2975 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2976 desc.datalen = cpu_to_le16(msglen); 2977 } 2978 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2979 2980 return status; 2981 } 2982 2983 /** 2984 * i40e_aq_debug_read_register 2985 * @hw: pointer to the hw struct 2986 * @reg_addr: register address 2987 * @reg_val: register value 2988 * @cmd_details: pointer to command details structure or NULL 2989 * 2990 * Read the register using the admin queue commands 2991 **/ 2992 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2993 u32 reg_addr, u64 *reg_val, 2994 struct i40e_asq_cmd_details *cmd_details) 2995 { 2996 struct i40e_aq_desc desc; 2997 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2998 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2999 i40e_status status; 3000 3001 if (reg_val == NULL) 3002 return I40E_ERR_PARAM; 3003 3004 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3005 3006 cmd_resp->address = cpu_to_le32(reg_addr); 3007 3008 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3009 3010 if (!status) { 3011 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 3012 (u64)le32_to_cpu(cmd_resp->value_low); 3013 } 3014 3015 return status; 3016 } 3017 3018 /** 3019 * i40e_aq_debug_write_register 3020 * @hw: pointer to the hw struct 3021 * @reg_addr: register address 3022 * @reg_val: register value 3023 * @cmd_details: pointer to command details structure or NULL 3024 * 3025 * Write to a register using the admin queue commands 3026 **/ 3027 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 3028 u32 reg_addr, u64 reg_val, 3029 struct i40e_asq_cmd_details *cmd_details) 3030 { 3031 struct i40e_aq_desc desc; 3032 struct i40e_aqc_debug_reg_read_write *cmd = 3033 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3034 i40e_status status; 3035 3036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3037 3038 cmd->address = cpu_to_le32(reg_addr); 3039 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 3040 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 3041 3042 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3043 3044 return status; 3045 } 3046 3047 /** 3048 * i40e_aq_request_resource 3049 * @hw: pointer to the hw struct 3050 * @resource: resource id 3051 * @access: access type 3052 * @sdp_number: resource number 3053 * @timeout: the maximum time in ms that the driver may hold the resource 3054 * @cmd_details: pointer to command details structure or NULL 3055 * 3056 * requests common resource using the admin queue commands 3057 **/ 3058 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 3059 enum i40e_aq_resources_ids resource, 3060 enum i40e_aq_resource_access_type access, 3061 u8 sdp_number, u64 *timeout, 3062 struct i40e_asq_cmd_details *cmd_details) 3063 { 3064 struct i40e_aq_desc desc; 3065 struct i40e_aqc_request_resource *cmd_resp = 3066 (struct i40e_aqc_request_resource *)&desc.params.raw; 3067 i40e_status status; 3068 3069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3070 3071 cmd_resp->resource_id = cpu_to_le16(resource); 3072 cmd_resp->access_type = cpu_to_le16(access); 3073 cmd_resp->resource_number = cpu_to_le32(sdp_number); 3074 3075 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3076 /* The completion specifies the maximum time in ms that the driver 3077 * may hold the resource in the Timeout field. 3078 * If the resource is held by someone else, the command completes with 3079 * busy return value and the timeout field indicates the maximum time 3080 * the current owner of the resource has to free it. 3081 */ 3082 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3083 *timeout = le32_to_cpu(cmd_resp->timeout); 3084 3085 return status; 3086 } 3087 3088 /** 3089 * i40e_aq_release_resource 3090 * @hw: pointer to the hw struct 3091 * @resource: resource id 3092 * @sdp_number: resource number 3093 * @cmd_details: pointer to command details structure or NULL 3094 * 3095 * release common resource using the admin queue commands 3096 **/ 3097 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 3098 enum i40e_aq_resources_ids resource, 3099 u8 sdp_number, 3100 struct i40e_asq_cmd_details *cmd_details) 3101 { 3102 struct i40e_aq_desc desc; 3103 struct i40e_aqc_request_resource *cmd = 3104 (struct i40e_aqc_request_resource *)&desc.params.raw; 3105 i40e_status status; 3106 3107 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3108 3109 cmd->resource_id = cpu_to_le16(resource); 3110 cmd->resource_number = cpu_to_le32(sdp_number); 3111 3112 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3113 3114 return status; 3115 } 3116 3117 /** 3118 * i40e_aq_read_nvm 3119 * @hw: pointer to the hw struct 3120 * @module_pointer: module pointer location in words from the NVM beginning 3121 * @offset: byte offset from the module beginning 3122 * @length: length of the section to be read (in bytes from the offset) 3123 * @data: command buffer (size [bytes] = length) 3124 * @last_command: tells if this is the last command in a series 3125 * @cmd_details: pointer to command details structure or NULL 3126 * 3127 * Read the NVM using the admin queue commands 3128 **/ 3129 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3130 u32 offset, u16 length, void *data, 3131 bool last_command, 3132 struct i40e_asq_cmd_details *cmd_details) 3133 { 3134 struct i40e_aq_desc desc; 3135 struct i40e_aqc_nvm_update *cmd = 3136 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3137 i40e_status status; 3138 3139 /* In offset the highest byte must be zeroed. */ 3140 if (offset & 0xFF000000) { 3141 status = I40E_ERR_PARAM; 3142 goto i40e_aq_read_nvm_exit; 3143 } 3144 3145 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3146 3147 /* If this is the last command in a series, set the proper flag. */ 3148 if (last_command) 3149 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3150 cmd->module_pointer = module_pointer; 3151 cmd->offset = cpu_to_le32(offset); 3152 cmd->length = cpu_to_le16(length); 3153 3154 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3155 if (length > I40E_AQ_LARGE_BUF) 3156 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3157 3158 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3159 3160 i40e_aq_read_nvm_exit: 3161 return status; 3162 } 3163 3164 /** 3165 * i40e_aq_erase_nvm 3166 * @hw: pointer to the hw struct 3167 * @module_pointer: module pointer location in words from the NVM beginning 3168 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3169 * @length: length of the section to be erased (expressed in 4 KB) 3170 * @last_command: tells if this is the last command in a series 3171 * @cmd_details: pointer to command details structure or NULL 3172 * 3173 * Erase the NVM sector using the admin queue commands 3174 **/ 3175 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3176 u32 offset, u16 length, bool last_command, 3177 struct i40e_asq_cmd_details *cmd_details) 3178 { 3179 struct i40e_aq_desc desc; 3180 struct i40e_aqc_nvm_update *cmd = 3181 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3182 i40e_status status; 3183 3184 /* In offset the highest byte must be zeroed. */ 3185 if (offset & 0xFF000000) { 3186 status = I40E_ERR_PARAM; 3187 goto i40e_aq_erase_nvm_exit; 3188 } 3189 3190 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3191 3192 /* If this is the last command in a series, set the proper flag. */ 3193 if (last_command) 3194 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3195 cmd->module_pointer = module_pointer; 3196 cmd->offset = cpu_to_le32(offset); 3197 cmd->length = cpu_to_le16(length); 3198 3199 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3200 3201 i40e_aq_erase_nvm_exit: 3202 return status; 3203 } 3204 3205 /** 3206 * i40e_parse_discover_capabilities 3207 * @hw: pointer to the hw struct 3208 * @buff: pointer to a buffer containing device/function capability records 3209 * @cap_count: number of capability records in the list 3210 * @list_type_opc: type of capabilities list to parse 3211 * 3212 * Parse the device/function capabilities list. 3213 **/ 3214 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3215 u32 cap_count, 3216 enum i40e_admin_queue_opc list_type_opc) 3217 { 3218 struct i40e_aqc_list_capabilities_element_resp *cap; 3219 u32 valid_functions, num_functions; 3220 u32 number, logical_id, phys_id; 3221 struct i40e_hw_capabilities *p; 3222 u16 id, ocp_cfg_word0; 3223 i40e_status status; 3224 u8 major_rev; 3225 u32 i = 0; 3226 3227 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3228 3229 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3230 p = &hw->dev_caps; 3231 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3232 p = &hw->func_caps; 3233 else 3234 return; 3235 3236 for (i = 0; i < cap_count; i++, cap++) { 3237 id = le16_to_cpu(cap->id); 3238 number = le32_to_cpu(cap->number); 3239 logical_id = le32_to_cpu(cap->logical_id); 3240 phys_id = le32_to_cpu(cap->phys_id); 3241 major_rev = cap->major_rev; 3242 3243 switch (id) { 3244 case I40E_AQ_CAP_ID_SWITCH_MODE: 3245 p->switch_mode = number; 3246 break; 3247 case I40E_AQ_CAP_ID_MNG_MODE: 3248 p->management_mode = number; 3249 if (major_rev > 1) { 3250 p->mng_protocols_over_mctp = logical_id; 3251 i40e_debug(hw, I40E_DEBUG_INIT, 3252 "HW Capability: Protocols over MCTP = %d\n", 3253 p->mng_protocols_over_mctp); 3254 } else { 3255 p->mng_protocols_over_mctp = 0; 3256 } 3257 break; 3258 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3259 p->npar_enable = number; 3260 break; 3261 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3262 p->os2bmc = number; 3263 break; 3264 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3265 p->valid_functions = number; 3266 break; 3267 case I40E_AQ_CAP_ID_SRIOV: 3268 if (number == 1) 3269 p->sr_iov_1_1 = true; 3270 break; 3271 case I40E_AQ_CAP_ID_VF: 3272 p->num_vfs = number; 3273 p->vf_base_id = logical_id; 3274 break; 3275 case I40E_AQ_CAP_ID_VMDQ: 3276 if (number == 1) 3277 p->vmdq = true; 3278 break; 3279 case I40E_AQ_CAP_ID_8021QBG: 3280 if (number == 1) 3281 p->evb_802_1_qbg = true; 3282 break; 3283 case I40E_AQ_CAP_ID_8021QBR: 3284 if (number == 1) 3285 p->evb_802_1_qbh = true; 3286 break; 3287 case I40E_AQ_CAP_ID_VSI: 3288 p->num_vsis = number; 3289 break; 3290 case I40E_AQ_CAP_ID_DCB: 3291 if (number == 1) { 3292 p->dcb = true; 3293 p->enabled_tcmap = logical_id; 3294 p->maxtc = phys_id; 3295 } 3296 break; 3297 case I40E_AQ_CAP_ID_FCOE: 3298 if (number == 1) 3299 p->fcoe = true; 3300 break; 3301 case I40E_AQ_CAP_ID_ISCSI: 3302 if (number == 1) 3303 p->iscsi = true; 3304 break; 3305 case I40E_AQ_CAP_ID_RSS: 3306 p->rss = true; 3307 p->rss_table_size = number; 3308 p->rss_table_entry_width = logical_id; 3309 break; 3310 case I40E_AQ_CAP_ID_RXQ: 3311 p->num_rx_qp = number; 3312 p->base_queue = phys_id; 3313 break; 3314 case I40E_AQ_CAP_ID_TXQ: 3315 p->num_tx_qp = number; 3316 p->base_queue = phys_id; 3317 break; 3318 case I40E_AQ_CAP_ID_MSIX: 3319 p->num_msix_vectors = number; 3320 i40e_debug(hw, I40E_DEBUG_INIT, 3321 "HW Capability: MSIX vector count = %d\n", 3322 p->num_msix_vectors); 3323 break; 3324 case I40E_AQ_CAP_ID_VF_MSIX: 3325 p->num_msix_vectors_vf = number; 3326 break; 3327 case I40E_AQ_CAP_ID_FLEX10: 3328 if (major_rev == 1) { 3329 if (number == 1) { 3330 p->flex10_enable = true; 3331 p->flex10_capable = true; 3332 } 3333 } else { 3334 /* Capability revision >= 2 */ 3335 if (number & 1) 3336 p->flex10_enable = true; 3337 if (number & 2) 3338 p->flex10_capable = true; 3339 } 3340 p->flex10_mode = logical_id; 3341 p->flex10_status = phys_id; 3342 break; 3343 case I40E_AQ_CAP_ID_CEM: 3344 if (number == 1) 3345 p->mgmt_cem = true; 3346 break; 3347 case I40E_AQ_CAP_ID_IWARP: 3348 if (number == 1) 3349 p->iwarp = true; 3350 break; 3351 case I40E_AQ_CAP_ID_LED: 3352 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3353 p->led[phys_id] = true; 3354 break; 3355 case I40E_AQ_CAP_ID_SDP: 3356 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3357 p->sdp[phys_id] = true; 3358 break; 3359 case I40E_AQ_CAP_ID_MDIO: 3360 if (number == 1) { 3361 p->mdio_port_num = phys_id; 3362 p->mdio_port_mode = logical_id; 3363 } 3364 break; 3365 case I40E_AQ_CAP_ID_1588: 3366 if (number == 1) 3367 p->ieee_1588 = true; 3368 break; 3369 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3370 p->fd = true; 3371 p->fd_filters_guaranteed = number; 3372 p->fd_filters_best_effort = logical_id; 3373 break; 3374 case I40E_AQ_CAP_ID_WSR_PROT: 3375 p->wr_csr_prot = (u64)number; 3376 p->wr_csr_prot |= (u64)logical_id << 32; 3377 break; 3378 case I40E_AQ_CAP_ID_NVM_MGMT: 3379 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3380 p->sec_rev_disabled = true; 3381 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3382 p->update_disabled = true; 3383 break; 3384 default: 3385 break; 3386 } 3387 } 3388 3389 if (p->fcoe) 3390 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3391 3392 /* Software override ensuring FCoE is disabled if npar or mfp 3393 * mode because it is not supported in these modes. 3394 */ 3395 if (p->npar_enable || p->flex10_enable) 3396 p->fcoe = false; 3397 3398 /* count the enabled ports (aka the "not disabled" ports) */ 3399 hw->num_ports = 0; 3400 for (i = 0; i < 4; i++) { 3401 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3402 u64 port_cfg = 0; 3403 3404 /* use AQ read to get the physical register offset instead 3405 * of the port relative offset 3406 */ 3407 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3408 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3409 hw->num_ports++; 3410 } 3411 3412 /* OCP cards case: if a mezz is removed the Ethernet port is at 3413 * disabled state in PRTGEN_CNF register. Additional NVM read is 3414 * needed in order to check if we are dealing with OCP card. 3415 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 3416 * physical ports results in wrong partition id calculation and thus 3417 * not supporting WoL. 3418 */ 3419 if (hw->mac.type == I40E_MAC_X722) { 3420 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) { 3421 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 3422 2 * I40E_SR_OCP_CFG_WORD0, 3423 sizeof(ocp_cfg_word0), 3424 &ocp_cfg_word0, true, NULL); 3425 if (!status && 3426 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 3427 hw->num_ports = 4; 3428 i40e_release_nvm(hw); 3429 } 3430 } 3431 3432 valid_functions = p->valid_functions; 3433 num_functions = 0; 3434 while (valid_functions) { 3435 if (valid_functions & 1) 3436 num_functions++; 3437 valid_functions >>= 1; 3438 } 3439 3440 /* partition id is 1-based, and functions are evenly spread 3441 * across the ports as partitions 3442 */ 3443 if (hw->num_ports != 0) { 3444 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3445 hw->num_partitions = num_functions / hw->num_ports; 3446 } 3447 3448 /* additional HW specific goodies that might 3449 * someday be HW version specific 3450 */ 3451 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3452 } 3453 3454 /** 3455 * i40e_aq_discover_capabilities 3456 * @hw: pointer to the hw struct 3457 * @buff: a virtual buffer to hold the capabilities 3458 * @buff_size: Size of the virtual buffer 3459 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3460 * @list_type_opc: capabilities type to discover - pass in the command opcode 3461 * @cmd_details: pointer to command details structure or NULL 3462 * 3463 * Get the device capabilities descriptions from the firmware 3464 **/ 3465 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3466 void *buff, u16 buff_size, u16 *data_size, 3467 enum i40e_admin_queue_opc list_type_opc, 3468 struct i40e_asq_cmd_details *cmd_details) 3469 { 3470 struct i40e_aqc_list_capabilites *cmd; 3471 struct i40e_aq_desc desc; 3472 i40e_status status = 0; 3473 3474 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3475 3476 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3477 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3478 status = I40E_ERR_PARAM; 3479 goto exit; 3480 } 3481 3482 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3483 3484 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3485 if (buff_size > I40E_AQ_LARGE_BUF) 3486 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3487 3488 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3489 *data_size = le16_to_cpu(desc.datalen); 3490 3491 if (status) 3492 goto exit; 3493 3494 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3495 list_type_opc); 3496 3497 exit: 3498 return status; 3499 } 3500 3501 /** 3502 * i40e_aq_update_nvm 3503 * @hw: pointer to the hw struct 3504 * @module_pointer: module pointer location in words from the NVM beginning 3505 * @offset: byte offset from the module beginning 3506 * @length: length of the section to be written (in bytes from the offset) 3507 * @data: command buffer (size [bytes] = length) 3508 * @last_command: tells if this is the last command in a series 3509 * @preservation_flags: Preservation mode flags 3510 * @cmd_details: pointer to command details structure or NULL 3511 * 3512 * Update the NVM using the admin queue commands 3513 **/ 3514 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3515 u32 offset, u16 length, void *data, 3516 bool last_command, u8 preservation_flags, 3517 struct i40e_asq_cmd_details *cmd_details) 3518 { 3519 struct i40e_aq_desc desc; 3520 struct i40e_aqc_nvm_update *cmd = 3521 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3522 i40e_status status; 3523 3524 /* In offset the highest byte must be zeroed. */ 3525 if (offset & 0xFF000000) { 3526 status = I40E_ERR_PARAM; 3527 goto i40e_aq_update_nvm_exit; 3528 } 3529 3530 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3531 3532 /* If this is the last command in a series, set the proper flag. */ 3533 if (last_command) 3534 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3535 if (hw->mac.type == I40E_MAC_X722) { 3536 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 3537 cmd->command_flags |= 3538 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 3539 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3540 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 3541 cmd->command_flags |= 3542 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 3543 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3544 } 3545 cmd->module_pointer = module_pointer; 3546 cmd->offset = cpu_to_le32(offset); 3547 cmd->length = cpu_to_le16(length); 3548 3549 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3550 if (length > I40E_AQ_LARGE_BUF) 3551 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3552 3553 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3554 3555 i40e_aq_update_nvm_exit: 3556 return status; 3557 } 3558 3559 /** 3560 * i40e_aq_rearrange_nvm 3561 * @hw: pointer to the hw struct 3562 * @rearrange_nvm: defines direction of rearrangement 3563 * @cmd_details: pointer to command details structure or NULL 3564 * 3565 * Rearrange NVM structure, available only for transition FW 3566 **/ 3567 i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw, 3568 u8 rearrange_nvm, 3569 struct i40e_asq_cmd_details *cmd_details) 3570 { 3571 struct i40e_aqc_nvm_update *cmd; 3572 i40e_status status; 3573 struct i40e_aq_desc desc; 3574 3575 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw; 3576 3577 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3578 3579 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT | 3580 I40E_AQ_NVM_REARRANGE_TO_STRUCT); 3581 3582 if (!rearrange_nvm) { 3583 status = I40E_ERR_PARAM; 3584 goto i40e_aq_rearrange_nvm_exit; 3585 } 3586 3587 cmd->command_flags |= rearrange_nvm; 3588 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3589 3590 i40e_aq_rearrange_nvm_exit: 3591 return status; 3592 } 3593 3594 /** 3595 * i40e_aq_get_lldp_mib 3596 * @hw: pointer to the hw struct 3597 * @bridge_type: type of bridge requested 3598 * @mib_type: Local, Remote or both Local and Remote MIBs 3599 * @buff: pointer to a user supplied buffer to store the MIB block 3600 * @buff_size: size of the buffer (in bytes) 3601 * @local_len : length of the returned Local LLDP MIB 3602 * @remote_len: length of the returned Remote LLDP MIB 3603 * @cmd_details: pointer to command details structure or NULL 3604 * 3605 * Requests the complete LLDP MIB (entire packet). 3606 **/ 3607 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3608 u8 mib_type, void *buff, u16 buff_size, 3609 u16 *local_len, u16 *remote_len, 3610 struct i40e_asq_cmd_details *cmd_details) 3611 { 3612 struct i40e_aq_desc desc; 3613 struct i40e_aqc_lldp_get_mib *cmd = 3614 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3615 struct i40e_aqc_lldp_get_mib *resp = 3616 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3617 i40e_status status; 3618 3619 if (buff_size == 0 || !buff) 3620 return I40E_ERR_PARAM; 3621 3622 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3623 /* Indirect Command */ 3624 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3625 3626 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3627 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3628 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3629 3630 desc.datalen = cpu_to_le16(buff_size); 3631 3632 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3633 if (buff_size > I40E_AQ_LARGE_BUF) 3634 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3635 3636 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3637 if (!status) { 3638 if (local_len != NULL) 3639 *local_len = le16_to_cpu(resp->local_len); 3640 if (remote_len != NULL) 3641 *remote_len = le16_to_cpu(resp->remote_len); 3642 } 3643 3644 return status; 3645 } 3646 3647 /** 3648 * i40e_aq_cfg_lldp_mib_change_event 3649 * @hw: pointer to the hw struct 3650 * @enable_update: Enable or Disable event posting 3651 * @cmd_details: pointer to command details structure or NULL 3652 * 3653 * Enable or Disable posting of an event on ARQ when LLDP MIB 3654 * associated with the interface changes 3655 **/ 3656 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3657 bool enable_update, 3658 struct i40e_asq_cmd_details *cmd_details) 3659 { 3660 struct i40e_aq_desc desc; 3661 struct i40e_aqc_lldp_update_mib *cmd = 3662 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3663 i40e_status status; 3664 3665 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3666 3667 if (!enable_update) 3668 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3669 3670 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3671 3672 return status; 3673 } 3674 3675 /** 3676 * i40e_aq_restore_lldp 3677 * @hw: pointer to the hw struct 3678 * @setting: pointer to factory setting variable or NULL 3679 * @restore: True if factory settings should be restored 3680 * @cmd_details: pointer to command details structure or NULL 3681 * 3682 * Restore LLDP Agent factory settings if @restore set to True. In other case 3683 * only returns factory setting in AQ response. 3684 **/ 3685 enum i40e_status_code 3686 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore, 3687 struct i40e_asq_cmd_details *cmd_details) 3688 { 3689 struct i40e_aq_desc desc; 3690 struct i40e_aqc_lldp_restore *cmd = 3691 (struct i40e_aqc_lldp_restore *)&desc.params.raw; 3692 i40e_status status; 3693 3694 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) { 3695 i40e_debug(hw, I40E_DEBUG_ALL, 3696 "Restore LLDP not supported by current FW version.\n"); 3697 return I40E_ERR_DEVICE_NOT_SUPPORTED; 3698 } 3699 3700 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore); 3701 3702 if (restore) 3703 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE; 3704 3705 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3706 3707 if (setting) 3708 *setting = cmd->command & 1; 3709 3710 return status; 3711 } 3712 3713 /** 3714 * i40e_aq_stop_lldp 3715 * @hw: pointer to the hw struct 3716 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3717 * @persist: True if stop of LLDP should be persistent across power cycles 3718 * @cmd_details: pointer to command details structure or NULL 3719 * 3720 * Stop or Shutdown the embedded LLDP Agent 3721 **/ 3722 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3723 bool persist, 3724 struct i40e_asq_cmd_details *cmd_details) 3725 { 3726 struct i40e_aq_desc desc; 3727 struct i40e_aqc_lldp_stop *cmd = 3728 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3729 i40e_status status; 3730 3731 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3732 3733 if (shutdown_agent) 3734 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3735 3736 if (persist) { 3737 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) 3738 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST; 3739 else 3740 i40e_debug(hw, I40E_DEBUG_ALL, 3741 "Persistent Stop LLDP not supported by current FW version.\n"); 3742 } 3743 3744 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3745 3746 return status; 3747 } 3748 3749 /** 3750 * i40e_aq_start_lldp 3751 * @hw: pointer to the hw struct 3752 * @buff: buffer for result 3753 * @persist: True if start of LLDP should be persistent across power cycles 3754 * @buff_size: buffer size 3755 * @cmd_details: pointer to command details structure or NULL 3756 * 3757 * Start the embedded LLDP Agent on all ports. 3758 **/ 3759 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, bool persist, 3760 struct i40e_asq_cmd_details *cmd_details) 3761 { 3762 struct i40e_aq_desc desc; 3763 struct i40e_aqc_lldp_start *cmd = 3764 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3765 i40e_status status; 3766 3767 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3768 3769 cmd->command = I40E_AQ_LLDP_AGENT_START; 3770 3771 if (persist) { 3772 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) 3773 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST; 3774 else 3775 i40e_debug(hw, I40E_DEBUG_ALL, 3776 "Persistent Start LLDP not supported by current FW version.\n"); 3777 } 3778 3779 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3780 3781 return status; 3782 } 3783 3784 /** 3785 * i40e_aq_set_dcb_parameters 3786 * @hw: pointer to the hw struct 3787 * @cmd_details: pointer to command details structure or NULL 3788 * @dcb_enable: True if DCB configuration needs to be applied 3789 * 3790 **/ 3791 enum i40e_status_code 3792 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 3793 struct i40e_asq_cmd_details *cmd_details) 3794 { 3795 struct i40e_aq_desc desc; 3796 struct i40e_aqc_set_dcb_parameters *cmd = 3797 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 3798 i40e_status status; 3799 3800 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) 3801 return I40E_ERR_DEVICE_NOT_SUPPORTED; 3802 3803 i40e_fill_default_direct_cmd_desc(&desc, 3804 i40e_aqc_opc_set_dcb_parameters); 3805 3806 if (dcb_enable) { 3807 cmd->valid_flags = I40E_DCB_VALID; 3808 cmd->command = I40E_AQ_DCB_SET_AGENT; 3809 } 3810 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3811 3812 return status; 3813 } 3814 3815 /** 3816 * i40e_aq_get_cee_dcb_config 3817 * @hw: pointer to the hw struct 3818 * @buff: response buffer that stores CEE operational configuration 3819 * @buff_size: size of the buffer passed 3820 * @cmd_details: pointer to command details structure or NULL 3821 * 3822 * Get CEE DCBX mode operational configuration from firmware 3823 **/ 3824 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3825 void *buff, u16 buff_size, 3826 struct i40e_asq_cmd_details *cmd_details) 3827 { 3828 struct i40e_aq_desc desc; 3829 i40e_status status; 3830 3831 if (buff_size == 0 || !buff) 3832 return I40E_ERR_PARAM; 3833 3834 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3835 3836 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3837 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3838 cmd_details); 3839 3840 return status; 3841 } 3842 3843 /** 3844 * i40e_aq_add_udp_tunnel 3845 * @hw: pointer to the hw struct 3846 * @udp_port: the UDP port to add in Host byte order 3847 * @protocol_index: protocol index type 3848 * @filter_index: pointer to filter index 3849 * @cmd_details: pointer to command details structure or NULL 3850 * 3851 * Note: Firmware expects the udp_port value to be in Little Endian format, 3852 * and this function will call cpu_to_le16 to convert from Host byte order to 3853 * Little Endian order. 3854 **/ 3855 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3856 u16 udp_port, u8 protocol_index, 3857 u8 *filter_index, 3858 struct i40e_asq_cmd_details *cmd_details) 3859 { 3860 struct i40e_aq_desc desc; 3861 struct i40e_aqc_add_udp_tunnel *cmd = 3862 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3863 struct i40e_aqc_del_udp_tunnel_completion *resp = 3864 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3865 i40e_status status; 3866 3867 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3868 3869 cmd->udp_port = cpu_to_le16(udp_port); 3870 cmd->protocol_type = protocol_index; 3871 3872 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3873 3874 if (!status && filter_index) 3875 *filter_index = resp->index; 3876 3877 return status; 3878 } 3879 3880 /** 3881 * i40e_aq_del_udp_tunnel 3882 * @hw: pointer to the hw struct 3883 * @index: filter index 3884 * @cmd_details: pointer to command details structure or NULL 3885 **/ 3886 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3887 struct i40e_asq_cmd_details *cmd_details) 3888 { 3889 struct i40e_aq_desc desc; 3890 struct i40e_aqc_remove_udp_tunnel *cmd = 3891 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3892 i40e_status status; 3893 3894 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3895 3896 cmd->index = index; 3897 3898 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3899 3900 return status; 3901 } 3902 3903 /** 3904 * i40e_aq_delete_element - Delete switch element 3905 * @hw: pointer to the hw struct 3906 * @seid: the SEID to delete from the switch 3907 * @cmd_details: pointer to command details structure or NULL 3908 * 3909 * This deletes a switch element from the switch. 3910 **/ 3911 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3912 struct i40e_asq_cmd_details *cmd_details) 3913 { 3914 struct i40e_aq_desc desc; 3915 struct i40e_aqc_switch_seid *cmd = 3916 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3917 i40e_status status; 3918 3919 if (seid == 0) 3920 return I40E_ERR_PARAM; 3921 3922 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3923 3924 cmd->seid = cpu_to_le16(seid); 3925 3926 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3927 3928 return status; 3929 } 3930 3931 /** 3932 * i40e_aq_dcb_updated - DCB Updated Command 3933 * @hw: pointer to the hw struct 3934 * @cmd_details: pointer to command details structure or NULL 3935 * 3936 * EMP will return when the shared RPB settings have been 3937 * recomputed and modified. The retval field in the descriptor 3938 * will be set to 0 when RPB is modified. 3939 **/ 3940 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3941 struct i40e_asq_cmd_details *cmd_details) 3942 { 3943 struct i40e_aq_desc desc; 3944 i40e_status status; 3945 3946 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3947 3948 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3949 3950 return status; 3951 } 3952 3953 /** 3954 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3955 * @hw: pointer to the hw struct 3956 * @seid: seid for the physical port/switching component/vsi 3957 * @buff: Indirect buffer to hold data parameters and response 3958 * @buff_size: Indirect buffer size 3959 * @opcode: Tx scheduler AQ command opcode 3960 * @cmd_details: pointer to command details structure or NULL 3961 * 3962 * Generic command handler for Tx scheduler AQ commands 3963 **/ 3964 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3965 void *buff, u16 buff_size, 3966 enum i40e_admin_queue_opc opcode, 3967 struct i40e_asq_cmd_details *cmd_details) 3968 { 3969 struct i40e_aq_desc desc; 3970 struct i40e_aqc_tx_sched_ind *cmd = 3971 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3972 i40e_status status; 3973 bool cmd_param_flag = false; 3974 3975 switch (opcode) { 3976 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3977 case i40e_aqc_opc_configure_vsi_tc_bw: 3978 case i40e_aqc_opc_enable_switching_comp_ets: 3979 case i40e_aqc_opc_modify_switching_comp_ets: 3980 case i40e_aqc_opc_disable_switching_comp_ets: 3981 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3982 case i40e_aqc_opc_configure_switching_comp_bw_config: 3983 cmd_param_flag = true; 3984 break; 3985 case i40e_aqc_opc_query_vsi_bw_config: 3986 case i40e_aqc_opc_query_vsi_ets_sla_config: 3987 case i40e_aqc_opc_query_switching_comp_ets_config: 3988 case i40e_aqc_opc_query_port_ets_config: 3989 case i40e_aqc_opc_query_switching_comp_bw_config: 3990 cmd_param_flag = false; 3991 break; 3992 default: 3993 return I40E_ERR_PARAM; 3994 } 3995 3996 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3997 3998 /* Indirect command */ 3999 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4000 if (cmd_param_flag) 4001 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4002 if (buff_size > I40E_AQ_LARGE_BUF) 4003 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4004 4005 desc.datalen = cpu_to_le16(buff_size); 4006 4007 cmd->vsi_seid = cpu_to_le16(seid); 4008 4009 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4010 4011 return status; 4012 } 4013 4014 /** 4015 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 4016 * @hw: pointer to the hw struct 4017 * @seid: VSI seid 4018 * @credit: BW limit credits (0 = disabled) 4019 * @max_credit: Max BW limit credits 4020 * @cmd_details: pointer to command details structure or NULL 4021 **/ 4022 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 4023 u16 seid, u16 credit, u8 max_credit, 4024 struct i40e_asq_cmd_details *cmd_details) 4025 { 4026 struct i40e_aq_desc desc; 4027 struct i40e_aqc_configure_vsi_bw_limit *cmd = 4028 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 4029 i40e_status status; 4030 4031 i40e_fill_default_direct_cmd_desc(&desc, 4032 i40e_aqc_opc_configure_vsi_bw_limit); 4033 4034 cmd->vsi_seid = cpu_to_le16(seid); 4035 cmd->credit = cpu_to_le16(credit); 4036 cmd->max_credit = max_credit; 4037 4038 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4039 4040 return status; 4041 } 4042 4043 /** 4044 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 4045 * @hw: pointer to the hw struct 4046 * @seid: VSI seid 4047 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 4048 * @cmd_details: pointer to command details structure or NULL 4049 **/ 4050 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 4051 u16 seid, 4052 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 4053 struct i40e_asq_cmd_details *cmd_details) 4054 { 4055 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4056 i40e_aqc_opc_configure_vsi_tc_bw, 4057 cmd_details); 4058 } 4059 4060 /** 4061 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 4062 * @hw: pointer to the hw struct 4063 * @seid: seid of the switching component connected to Physical Port 4064 * @ets_data: Buffer holding ETS parameters 4065 * @opcode: Tx scheduler AQ command opcode 4066 * @cmd_details: pointer to command details structure or NULL 4067 **/ 4068 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 4069 u16 seid, 4070 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 4071 enum i40e_admin_queue_opc opcode, 4072 struct i40e_asq_cmd_details *cmd_details) 4073 { 4074 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 4075 sizeof(*ets_data), opcode, cmd_details); 4076 } 4077 4078 /** 4079 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 4080 * @hw: pointer to the hw struct 4081 * @seid: seid of the switching component 4082 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 4083 * @cmd_details: pointer to command details structure or NULL 4084 **/ 4085 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 4086 u16 seid, 4087 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 4088 struct i40e_asq_cmd_details *cmd_details) 4089 { 4090 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4091 i40e_aqc_opc_configure_switching_comp_bw_config, 4092 cmd_details); 4093 } 4094 4095 /** 4096 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 4097 * @hw: pointer to the hw struct 4098 * @seid: seid of the VSI 4099 * @bw_data: Buffer to hold VSI BW configuration 4100 * @cmd_details: pointer to command details structure or NULL 4101 **/ 4102 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 4103 u16 seid, 4104 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 4105 struct i40e_asq_cmd_details *cmd_details) 4106 { 4107 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4108 i40e_aqc_opc_query_vsi_bw_config, 4109 cmd_details); 4110 } 4111 4112 /** 4113 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 4114 * @hw: pointer to the hw struct 4115 * @seid: seid of the VSI 4116 * @bw_data: Buffer to hold VSI BW configuration per TC 4117 * @cmd_details: pointer to command details structure or NULL 4118 **/ 4119 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 4120 u16 seid, 4121 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 4122 struct i40e_asq_cmd_details *cmd_details) 4123 { 4124 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4125 i40e_aqc_opc_query_vsi_ets_sla_config, 4126 cmd_details); 4127 } 4128 4129 /** 4130 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 4131 * @hw: pointer to the hw struct 4132 * @seid: seid of the switching component 4133 * @bw_data: Buffer to hold switching component's per TC BW config 4134 * @cmd_details: pointer to command details structure or NULL 4135 **/ 4136 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 4137 u16 seid, 4138 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 4139 struct i40e_asq_cmd_details *cmd_details) 4140 { 4141 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4142 i40e_aqc_opc_query_switching_comp_ets_config, 4143 cmd_details); 4144 } 4145 4146 /** 4147 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 4148 * @hw: pointer to the hw struct 4149 * @seid: seid of the VSI or switching component connected to Physical Port 4150 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 4151 * @cmd_details: pointer to command details structure or NULL 4152 **/ 4153 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 4154 u16 seid, 4155 struct i40e_aqc_query_port_ets_config_resp *bw_data, 4156 struct i40e_asq_cmd_details *cmd_details) 4157 { 4158 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4159 i40e_aqc_opc_query_port_ets_config, 4160 cmd_details); 4161 } 4162 4163 /** 4164 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 4165 * @hw: pointer to the hw struct 4166 * @seid: seid of the switching component 4167 * @bw_data: Buffer to hold switching component's BW configuration 4168 * @cmd_details: pointer to command details structure or NULL 4169 **/ 4170 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 4171 u16 seid, 4172 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 4173 struct i40e_asq_cmd_details *cmd_details) 4174 { 4175 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4176 i40e_aqc_opc_query_switching_comp_bw_config, 4177 cmd_details); 4178 } 4179 4180 /** 4181 * i40e_validate_filter_settings 4182 * @hw: pointer to the hardware structure 4183 * @settings: Filter control settings 4184 * 4185 * Check and validate the filter control settings passed. 4186 * The function checks for the valid filter/context sizes being 4187 * passed for FCoE and PE. 4188 * 4189 * Returns 0 if the values passed are valid and within 4190 * range else returns an error. 4191 **/ 4192 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 4193 struct i40e_filter_control_settings *settings) 4194 { 4195 u32 fcoe_cntx_size, fcoe_filt_size; 4196 u32 pe_cntx_size, pe_filt_size; 4197 u32 fcoe_fmax; 4198 u32 val; 4199 4200 /* Validate FCoE settings passed */ 4201 switch (settings->fcoe_filt_num) { 4202 case I40E_HASH_FILTER_SIZE_1K: 4203 case I40E_HASH_FILTER_SIZE_2K: 4204 case I40E_HASH_FILTER_SIZE_4K: 4205 case I40E_HASH_FILTER_SIZE_8K: 4206 case I40E_HASH_FILTER_SIZE_16K: 4207 case I40E_HASH_FILTER_SIZE_32K: 4208 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4209 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4210 break; 4211 default: 4212 return I40E_ERR_PARAM; 4213 } 4214 4215 switch (settings->fcoe_cntx_num) { 4216 case I40E_DMA_CNTX_SIZE_512: 4217 case I40E_DMA_CNTX_SIZE_1K: 4218 case I40E_DMA_CNTX_SIZE_2K: 4219 case I40E_DMA_CNTX_SIZE_4K: 4220 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4221 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4222 break; 4223 default: 4224 return I40E_ERR_PARAM; 4225 } 4226 4227 /* Validate PE settings passed */ 4228 switch (settings->pe_filt_num) { 4229 case I40E_HASH_FILTER_SIZE_1K: 4230 case I40E_HASH_FILTER_SIZE_2K: 4231 case I40E_HASH_FILTER_SIZE_4K: 4232 case I40E_HASH_FILTER_SIZE_8K: 4233 case I40E_HASH_FILTER_SIZE_16K: 4234 case I40E_HASH_FILTER_SIZE_32K: 4235 case I40E_HASH_FILTER_SIZE_64K: 4236 case I40E_HASH_FILTER_SIZE_128K: 4237 case I40E_HASH_FILTER_SIZE_256K: 4238 case I40E_HASH_FILTER_SIZE_512K: 4239 case I40E_HASH_FILTER_SIZE_1M: 4240 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4241 pe_filt_size <<= (u32)settings->pe_filt_num; 4242 break; 4243 default: 4244 return I40E_ERR_PARAM; 4245 } 4246 4247 switch (settings->pe_cntx_num) { 4248 case I40E_DMA_CNTX_SIZE_512: 4249 case I40E_DMA_CNTX_SIZE_1K: 4250 case I40E_DMA_CNTX_SIZE_2K: 4251 case I40E_DMA_CNTX_SIZE_4K: 4252 case I40E_DMA_CNTX_SIZE_8K: 4253 case I40E_DMA_CNTX_SIZE_16K: 4254 case I40E_DMA_CNTX_SIZE_32K: 4255 case I40E_DMA_CNTX_SIZE_64K: 4256 case I40E_DMA_CNTX_SIZE_128K: 4257 case I40E_DMA_CNTX_SIZE_256K: 4258 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4259 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4260 break; 4261 default: 4262 return I40E_ERR_PARAM; 4263 } 4264 4265 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4266 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4267 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4268 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4269 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4270 return I40E_ERR_INVALID_SIZE; 4271 4272 return 0; 4273 } 4274 4275 /** 4276 * i40e_set_filter_control 4277 * @hw: pointer to the hardware structure 4278 * @settings: Filter control settings 4279 * 4280 * Set the Queue Filters for PE/FCoE and enable filters required 4281 * for a single PF. It is expected that these settings are programmed 4282 * at the driver initialization time. 4283 **/ 4284 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4285 struct i40e_filter_control_settings *settings) 4286 { 4287 i40e_status ret = 0; 4288 u32 hash_lut_size = 0; 4289 u32 val; 4290 4291 if (!settings) 4292 return I40E_ERR_PARAM; 4293 4294 /* Validate the input settings */ 4295 ret = i40e_validate_filter_settings(hw, settings); 4296 if (ret) 4297 return ret; 4298 4299 /* Read the PF Queue Filter control register */ 4300 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4301 4302 /* Program required PE hash buckets for the PF */ 4303 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4304 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4305 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4306 /* Program required PE contexts for the PF */ 4307 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4308 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4309 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4310 4311 /* Program required FCoE hash buckets for the PF */ 4312 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4313 val |= ((u32)settings->fcoe_filt_num << 4314 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4315 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4316 /* Program required FCoE DDP contexts for the PF */ 4317 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4318 val |= ((u32)settings->fcoe_cntx_num << 4319 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4320 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4321 4322 /* Program Hash LUT size for the PF */ 4323 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4324 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4325 hash_lut_size = 1; 4326 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4327 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4328 4329 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4330 if (settings->enable_fdir) 4331 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4332 if (settings->enable_ethtype) 4333 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4334 if (settings->enable_macvlan) 4335 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4336 4337 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4338 4339 return 0; 4340 } 4341 4342 /** 4343 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4344 * @hw: pointer to the hw struct 4345 * @mac_addr: MAC address to use in the filter 4346 * @ethtype: Ethertype to use in the filter 4347 * @flags: Flags that needs to be applied to the filter 4348 * @vsi_seid: seid of the control VSI 4349 * @queue: VSI queue number to send the packet to 4350 * @is_add: Add control packet filter if True else remove 4351 * @stats: Structure to hold information on control filter counts 4352 * @cmd_details: pointer to command details structure or NULL 4353 * 4354 * This command will Add or Remove control packet filter for a control VSI. 4355 * In return it will update the total number of perfect filter count in 4356 * the stats member. 4357 **/ 4358 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4359 u8 *mac_addr, u16 ethtype, u16 flags, 4360 u16 vsi_seid, u16 queue, bool is_add, 4361 struct i40e_control_filter_stats *stats, 4362 struct i40e_asq_cmd_details *cmd_details) 4363 { 4364 struct i40e_aq_desc desc; 4365 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4366 (struct i40e_aqc_add_remove_control_packet_filter *) 4367 &desc.params.raw; 4368 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4369 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4370 &desc.params.raw; 4371 i40e_status status; 4372 4373 if (vsi_seid == 0) 4374 return I40E_ERR_PARAM; 4375 4376 if (is_add) { 4377 i40e_fill_default_direct_cmd_desc(&desc, 4378 i40e_aqc_opc_add_control_packet_filter); 4379 cmd->queue = cpu_to_le16(queue); 4380 } else { 4381 i40e_fill_default_direct_cmd_desc(&desc, 4382 i40e_aqc_opc_remove_control_packet_filter); 4383 } 4384 4385 if (mac_addr) 4386 ether_addr_copy(cmd->mac, mac_addr); 4387 4388 cmd->etype = cpu_to_le16(ethtype); 4389 cmd->flags = cpu_to_le16(flags); 4390 cmd->seid = cpu_to_le16(vsi_seid); 4391 4392 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4393 4394 if (!status && stats) { 4395 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4396 stats->etype_used = le16_to_cpu(resp->etype_used); 4397 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4398 stats->etype_free = le16_to_cpu(resp->etype_free); 4399 } 4400 4401 return status; 4402 } 4403 4404 /** 4405 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4406 * @hw: pointer to the hw struct 4407 * @seid: VSI seid to add ethertype filter from 4408 **/ 4409 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4410 u16 seid) 4411 { 4412 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4413 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4414 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4415 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4416 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4417 i40e_status status; 4418 4419 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4420 seid, 0, true, NULL, 4421 NULL); 4422 if (status) 4423 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4424 } 4425 4426 /** 4427 * i40e_aq_alternate_read 4428 * @hw: pointer to the hardware structure 4429 * @reg_addr0: address of first dword to be read 4430 * @reg_val0: pointer for data read from 'reg_addr0' 4431 * @reg_addr1: address of second dword to be read 4432 * @reg_val1: pointer for data read from 'reg_addr1' 4433 * 4434 * Read one or two dwords from alternate structure. Fields are indicated 4435 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4436 * is not passed then only register at 'reg_addr0' is read. 4437 * 4438 **/ 4439 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4440 u32 reg_addr0, u32 *reg_val0, 4441 u32 reg_addr1, u32 *reg_val1) 4442 { 4443 struct i40e_aq_desc desc; 4444 struct i40e_aqc_alternate_write *cmd_resp = 4445 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4446 i40e_status status; 4447 4448 if (!reg_val0) 4449 return I40E_ERR_PARAM; 4450 4451 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4452 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4453 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4454 4455 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4456 4457 if (!status) { 4458 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4459 4460 if (reg_val1) 4461 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4462 } 4463 4464 return status; 4465 } 4466 4467 /** 4468 * i40e_aq_resume_port_tx 4469 * @hw: pointer to the hardware structure 4470 * @cmd_details: pointer to command details structure or NULL 4471 * 4472 * Resume port's Tx traffic 4473 **/ 4474 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4475 struct i40e_asq_cmd_details *cmd_details) 4476 { 4477 struct i40e_aq_desc desc; 4478 i40e_status status; 4479 4480 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4481 4482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4483 4484 return status; 4485 } 4486 4487 /** 4488 * i40e_set_pci_config_data - store PCI bus info 4489 * @hw: pointer to hardware structure 4490 * @link_status: the link status word from PCI config space 4491 * 4492 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4493 **/ 4494 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4495 { 4496 hw->bus.type = i40e_bus_type_pci_express; 4497 4498 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4499 case PCI_EXP_LNKSTA_NLW_X1: 4500 hw->bus.width = i40e_bus_width_pcie_x1; 4501 break; 4502 case PCI_EXP_LNKSTA_NLW_X2: 4503 hw->bus.width = i40e_bus_width_pcie_x2; 4504 break; 4505 case PCI_EXP_LNKSTA_NLW_X4: 4506 hw->bus.width = i40e_bus_width_pcie_x4; 4507 break; 4508 case PCI_EXP_LNKSTA_NLW_X8: 4509 hw->bus.width = i40e_bus_width_pcie_x8; 4510 break; 4511 default: 4512 hw->bus.width = i40e_bus_width_unknown; 4513 break; 4514 } 4515 4516 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4517 case PCI_EXP_LNKSTA_CLS_2_5GB: 4518 hw->bus.speed = i40e_bus_speed_2500; 4519 break; 4520 case PCI_EXP_LNKSTA_CLS_5_0GB: 4521 hw->bus.speed = i40e_bus_speed_5000; 4522 break; 4523 case PCI_EXP_LNKSTA_CLS_8_0GB: 4524 hw->bus.speed = i40e_bus_speed_8000; 4525 break; 4526 default: 4527 hw->bus.speed = i40e_bus_speed_unknown; 4528 break; 4529 } 4530 } 4531 4532 /** 4533 * i40e_aq_debug_dump 4534 * @hw: pointer to the hardware structure 4535 * @cluster_id: specific cluster to dump 4536 * @table_id: table id within cluster 4537 * @start_index: index of line in the block to read 4538 * @buff_size: dump buffer size 4539 * @buff: dump buffer 4540 * @ret_buff_size: actual buffer size returned 4541 * @ret_next_table: next block to read 4542 * @ret_next_index: next index to read 4543 * @cmd_details: pointer to command details structure or NULL 4544 * 4545 * Dump internal FW/HW data for debug purposes. 4546 * 4547 **/ 4548 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4549 u8 table_id, u32 start_index, u16 buff_size, 4550 void *buff, u16 *ret_buff_size, 4551 u8 *ret_next_table, u32 *ret_next_index, 4552 struct i40e_asq_cmd_details *cmd_details) 4553 { 4554 struct i40e_aq_desc desc; 4555 struct i40e_aqc_debug_dump_internals *cmd = 4556 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4557 struct i40e_aqc_debug_dump_internals *resp = 4558 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4559 i40e_status status; 4560 4561 if (buff_size == 0 || !buff) 4562 return I40E_ERR_PARAM; 4563 4564 i40e_fill_default_direct_cmd_desc(&desc, 4565 i40e_aqc_opc_debug_dump_internals); 4566 /* Indirect Command */ 4567 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4568 if (buff_size > I40E_AQ_LARGE_BUF) 4569 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4570 4571 cmd->cluster_id = cluster_id; 4572 cmd->table_id = table_id; 4573 cmd->idx = cpu_to_le32(start_index); 4574 4575 desc.datalen = cpu_to_le16(buff_size); 4576 4577 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4578 if (!status) { 4579 if (ret_buff_size) 4580 *ret_buff_size = le16_to_cpu(desc.datalen); 4581 if (ret_next_table) 4582 *ret_next_table = resp->table_id; 4583 if (ret_next_index) 4584 *ret_next_index = le32_to_cpu(resp->idx); 4585 } 4586 4587 return status; 4588 } 4589 4590 /** 4591 * i40e_read_bw_from_alt_ram 4592 * @hw: pointer to the hardware structure 4593 * @max_bw: pointer for max_bw read 4594 * @min_bw: pointer for min_bw read 4595 * @min_valid: pointer for bool that is true if min_bw is a valid value 4596 * @max_valid: pointer for bool that is true if max_bw is a valid value 4597 * 4598 * Read bw from the alternate ram for the given pf 4599 **/ 4600 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4601 u32 *max_bw, u32 *min_bw, 4602 bool *min_valid, bool *max_valid) 4603 { 4604 i40e_status status; 4605 u32 max_bw_addr, min_bw_addr; 4606 4607 /* Calculate the address of the min/max bw registers */ 4608 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4609 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4610 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4611 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4612 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4613 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4614 4615 /* Read the bandwidths from alt ram */ 4616 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4617 min_bw_addr, min_bw); 4618 4619 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4620 *min_valid = true; 4621 else 4622 *min_valid = false; 4623 4624 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4625 *max_valid = true; 4626 else 4627 *max_valid = false; 4628 4629 return status; 4630 } 4631 4632 /** 4633 * i40e_aq_configure_partition_bw 4634 * @hw: pointer to the hardware structure 4635 * @bw_data: Buffer holding valid pfs and bw limits 4636 * @cmd_details: pointer to command details 4637 * 4638 * Configure partitions guaranteed/max bw 4639 **/ 4640 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4641 struct i40e_aqc_configure_partition_bw_data *bw_data, 4642 struct i40e_asq_cmd_details *cmd_details) 4643 { 4644 i40e_status status; 4645 struct i40e_aq_desc desc; 4646 u16 bwd_size = sizeof(*bw_data); 4647 4648 i40e_fill_default_direct_cmd_desc(&desc, 4649 i40e_aqc_opc_configure_partition_bw); 4650 4651 /* Indirect command */ 4652 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4653 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4654 4655 if (bwd_size > I40E_AQ_LARGE_BUF) 4656 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4657 4658 desc.datalen = cpu_to_le16(bwd_size); 4659 4660 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4661 cmd_details); 4662 4663 return status; 4664 } 4665 4666 /** 4667 * i40e_read_phy_register_clause22 4668 * @hw: pointer to the HW structure 4669 * @reg: register address in the page 4670 * @phy_addr: PHY address on MDIO interface 4671 * @value: PHY register value 4672 * 4673 * Reads specified PHY register value 4674 **/ 4675 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw, 4676 u16 reg, u8 phy_addr, u16 *value) 4677 { 4678 i40e_status status = I40E_ERR_TIMEOUT; 4679 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4680 u32 command = 0; 4681 u16 retry = 1000; 4682 4683 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4684 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4685 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4686 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4687 (I40E_GLGEN_MSCA_MDICMD_MASK); 4688 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4689 do { 4690 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4691 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4692 status = 0; 4693 break; 4694 } 4695 udelay(10); 4696 retry--; 4697 } while (retry); 4698 4699 if (status) { 4700 i40e_debug(hw, I40E_DEBUG_PHY, 4701 "PHY: Can't write command to external PHY.\n"); 4702 } else { 4703 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4704 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4705 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4706 } 4707 4708 return status; 4709 } 4710 4711 /** 4712 * i40e_write_phy_register_clause22 4713 * @hw: pointer to the HW structure 4714 * @reg: register address in the page 4715 * @phy_addr: PHY address on MDIO interface 4716 * @value: PHY register value 4717 * 4718 * Writes specified PHY register value 4719 **/ 4720 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw, 4721 u16 reg, u8 phy_addr, u16 value) 4722 { 4723 i40e_status status = I40E_ERR_TIMEOUT; 4724 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4725 u32 command = 0; 4726 u16 retry = 1000; 4727 4728 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4729 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4730 4731 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4732 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4733 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4734 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4735 (I40E_GLGEN_MSCA_MDICMD_MASK); 4736 4737 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4738 do { 4739 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4740 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4741 status = 0; 4742 break; 4743 } 4744 udelay(10); 4745 retry--; 4746 } while (retry); 4747 4748 return status; 4749 } 4750 4751 /** 4752 * i40e_read_phy_register_clause45 4753 * @hw: pointer to the HW structure 4754 * @page: registers page number 4755 * @reg: register address in the page 4756 * @phy_addr: PHY address on MDIO interface 4757 * @value: PHY register value 4758 * 4759 * Reads specified PHY register value 4760 **/ 4761 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw, 4762 u8 page, u16 reg, u8 phy_addr, u16 *value) 4763 { 4764 i40e_status status = I40E_ERR_TIMEOUT; 4765 u32 command = 0; 4766 u16 retry = 1000; 4767 u8 port_num = hw->func_caps.mdio_port_num; 4768 4769 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4770 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4771 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4772 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4773 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4774 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4775 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4776 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4777 do { 4778 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4779 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4780 status = 0; 4781 break; 4782 } 4783 usleep_range(10, 20); 4784 retry--; 4785 } while (retry); 4786 4787 if (status) { 4788 i40e_debug(hw, I40E_DEBUG_PHY, 4789 "PHY: Can't write command to external PHY.\n"); 4790 goto phy_read_end; 4791 } 4792 4793 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4794 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4795 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4796 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4797 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4798 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4799 status = I40E_ERR_TIMEOUT; 4800 retry = 1000; 4801 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4802 do { 4803 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4804 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4805 status = 0; 4806 break; 4807 } 4808 usleep_range(10, 20); 4809 retry--; 4810 } while (retry); 4811 4812 if (!status) { 4813 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4814 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4815 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4816 } else { 4817 i40e_debug(hw, I40E_DEBUG_PHY, 4818 "PHY: Can't read register value from external PHY.\n"); 4819 } 4820 4821 phy_read_end: 4822 return status; 4823 } 4824 4825 /** 4826 * i40e_write_phy_register_clause45 4827 * @hw: pointer to the HW structure 4828 * @page: registers page number 4829 * @reg: register address in the page 4830 * @phy_addr: PHY address on MDIO interface 4831 * @value: PHY register value 4832 * 4833 * Writes value to specified PHY register 4834 **/ 4835 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, 4836 u8 page, u16 reg, u8 phy_addr, u16 value) 4837 { 4838 i40e_status status = I40E_ERR_TIMEOUT; 4839 u32 command = 0; 4840 u16 retry = 1000; 4841 u8 port_num = hw->func_caps.mdio_port_num; 4842 4843 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4844 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4845 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4846 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4847 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4848 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4849 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4850 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4851 do { 4852 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4853 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4854 status = 0; 4855 break; 4856 } 4857 usleep_range(10, 20); 4858 retry--; 4859 } while (retry); 4860 if (status) { 4861 i40e_debug(hw, I40E_DEBUG_PHY, 4862 "PHY: Can't write command to external PHY.\n"); 4863 goto phy_write_end; 4864 } 4865 4866 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4867 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4868 4869 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4870 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4871 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4872 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4873 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4874 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4875 status = I40E_ERR_TIMEOUT; 4876 retry = 1000; 4877 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4878 do { 4879 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4880 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4881 status = 0; 4882 break; 4883 } 4884 usleep_range(10, 20); 4885 retry--; 4886 } while (retry); 4887 4888 phy_write_end: 4889 return status; 4890 } 4891 4892 /** 4893 * i40e_write_phy_register 4894 * @hw: pointer to the HW structure 4895 * @page: registers page number 4896 * @reg: register address in the page 4897 * @phy_addr: PHY address on MDIO interface 4898 * @value: PHY register value 4899 * 4900 * Writes value to specified PHY register 4901 **/ 4902 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4903 u8 page, u16 reg, u8 phy_addr, u16 value) 4904 { 4905 i40e_status status; 4906 4907 switch (hw->device_id) { 4908 case I40E_DEV_ID_1G_BASE_T_X722: 4909 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4910 value); 4911 break; 4912 case I40E_DEV_ID_10G_BASE_T: 4913 case I40E_DEV_ID_10G_BASE_T4: 4914 case I40E_DEV_ID_10G_BASE_T_BC: 4915 case I40E_DEV_ID_10G_BASE_T_X722: 4916 case I40E_DEV_ID_25G_B: 4917 case I40E_DEV_ID_25G_SFP28: 4918 status = i40e_write_phy_register_clause45(hw, page, reg, 4919 phy_addr, value); 4920 break; 4921 default: 4922 status = I40E_ERR_UNKNOWN_PHY; 4923 break; 4924 } 4925 4926 return status; 4927 } 4928 4929 /** 4930 * i40e_read_phy_register 4931 * @hw: pointer to the HW structure 4932 * @page: registers page number 4933 * @reg: register address in the page 4934 * @phy_addr: PHY address on MDIO interface 4935 * @value: PHY register value 4936 * 4937 * Reads specified PHY register value 4938 **/ 4939 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4940 u8 page, u16 reg, u8 phy_addr, u16 *value) 4941 { 4942 i40e_status status; 4943 4944 switch (hw->device_id) { 4945 case I40E_DEV_ID_1G_BASE_T_X722: 4946 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4947 value); 4948 break; 4949 case I40E_DEV_ID_10G_BASE_T: 4950 case I40E_DEV_ID_10G_BASE_T4: 4951 case I40E_DEV_ID_10G_BASE_T_BC: 4952 case I40E_DEV_ID_10G_BASE_T_X722: 4953 case I40E_DEV_ID_25G_B: 4954 case I40E_DEV_ID_25G_SFP28: 4955 status = i40e_read_phy_register_clause45(hw, page, reg, 4956 phy_addr, value); 4957 break; 4958 default: 4959 status = I40E_ERR_UNKNOWN_PHY; 4960 break; 4961 } 4962 4963 return status; 4964 } 4965 4966 /** 4967 * i40e_get_phy_address 4968 * @hw: pointer to the HW structure 4969 * @dev_num: PHY port num that address we want 4970 * 4971 * Gets PHY address for current port 4972 **/ 4973 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4974 { 4975 u8 port_num = hw->func_caps.mdio_port_num; 4976 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4977 4978 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4979 } 4980 4981 /** 4982 * i40e_blink_phy_led 4983 * @hw: pointer to the HW structure 4984 * @time: time how long led will blinks in secs 4985 * @interval: gap between LED on and off in msecs 4986 * 4987 * Blinks PHY link LED 4988 **/ 4989 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4990 u32 time, u32 interval) 4991 { 4992 i40e_status status = 0; 4993 u32 i; 4994 u16 led_ctl; 4995 u16 gpio_led_port; 4996 u16 led_reg; 4997 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4998 u8 phy_addr = 0; 4999 u8 port_num; 5000 5001 i = rd32(hw, I40E_PFGEN_PORTNUM); 5002 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5003 phy_addr = i40e_get_phy_address(hw, port_num); 5004 5005 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 5006 led_addr++) { 5007 status = i40e_read_phy_register_clause45(hw, 5008 I40E_PHY_COM_REG_PAGE, 5009 led_addr, phy_addr, 5010 &led_reg); 5011 if (status) 5012 goto phy_blinking_end; 5013 led_ctl = led_reg; 5014 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 5015 led_reg = 0; 5016 status = i40e_write_phy_register_clause45(hw, 5017 I40E_PHY_COM_REG_PAGE, 5018 led_addr, phy_addr, 5019 led_reg); 5020 if (status) 5021 goto phy_blinking_end; 5022 break; 5023 } 5024 } 5025 5026 if (time > 0 && interval > 0) { 5027 for (i = 0; i < time * 1000; i += interval) { 5028 status = i40e_read_phy_register_clause45(hw, 5029 I40E_PHY_COM_REG_PAGE, 5030 led_addr, phy_addr, &led_reg); 5031 if (status) 5032 goto restore_config; 5033 if (led_reg & I40E_PHY_LED_MANUAL_ON) 5034 led_reg = 0; 5035 else 5036 led_reg = I40E_PHY_LED_MANUAL_ON; 5037 status = i40e_write_phy_register_clause45(hw, 5038 I40E_PHY_COM_REG_PAGE, 5039 led_addr, phy_addr, led_reg); 5040 if (status) 5041 goto restore_config; 5042 msleep(interval); 5043 } 5044 } 5045 5046 restore_config: 5047 status = i40e_write_phy_register_clause45(hw, 5048 I40E_PHY_COM_REG_PAGE, 5049 led_addr, phy_addr, led_ctl); 5050 5051 phy_blinking_end: 5052 return status; 5053 } 5054 5055 /** 5056 * i40e_led_get_reg - read LED register 5057 * @hw: pointer to the HW structure 5058 * @led_addr: LED register address 5059 * @reg_val: read register value 5060 **/ 5061 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 5062 u32 *reg_val) 5063 { 5064 enum i40e_status_code status; 5065 u8 phy_addr = 0; 5066 u8 port_num; 5067 u32 i; 5068 5069 *reg_val = 0; 5070 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5071 status = 5072 i40e_aq_get_phy_register(hw, 5073 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5074 I40E_PHY_COM_REG_PAGE, true, 5075 I40E_PHY_LED_PROV_REG_1, 5076 reg_val, NULL); 5077 } else { 5078 i = rd32(hw, I40E_PFGEN_PORTNUM); 5079 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5080 phy_addr = i40e_get_phy_address(hw, port_num); 5081 status = i40e_read_phy_register_clause45(hw, 5082 I40E_PHY_COM_REG_PAGE, 5083 led_addr, phy_addr, 5084 (u16 *)reg_val); 5085 } 5086 return status; 5087 } 5088 5089 /** 5090 * i40e_led_set_reg - write LED register 5091 * @hw: pointer to the HW structure 5092 * @led_addr: LED register address 5093 * @reg_val: register value to write 5094 **/ 5095 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 5096 u32 reg_val) 5097 { 5098 enum i40e_status_code status; 5099 u8 phy_addr = 0; 5100 u8 port_num; 5101 u32 i; 5102 5103 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5104 status = 5105 i40e_aq_set_phy_register(hw, 5106 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5107 I40E_PHY_COM_REG_PAGE, true, 5108 I40E_PHY_LED_PROV_REG_1, 5109 reg_val, NULL); 5110 } else { 5111 i = rd32(hw, I40E_PFGEN_PORTNUM); 5112 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5113 phy_addr = i40e_get_phy_address(hw, port_num); 5114 status = i40e_write_phy_register_clause45(hw, 5115 I40E_PHY_COM_REG_PAGE, 5116 led_addr, phy_addr, 5117 (u16)reg_val); 5118 } 5119 5120 return status; 5121 } 5122 5123 /** 5124 * i40e_led_get_phy - return current on/off mode 5125 * @hw: pointer to the hw struct 5126 * @led_addr: address of led register to use 5127 * @val: original value of register to use 5128 * 5129 **/ 5130 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 5131 u16 *val) 5132 { 5133 i40e_status status = 0; 5134 u16 gpio_led_port; 5135 u8 phy_addr = 0; 5136 u16 reg_val; 5137 u16 temp_addr; 5138 u8 port_num; 5139 u32 i; 5140 u32 reg_val_aq; 5141 5142 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5143 status = 5144 i40e_aq_get_phy_register(hw, 5145 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5146 I40E_PHY_COM_REG_PAGE, true, 5147 I40E_PHY_LED_PROV_REG_1, 5148 ®_val_aq, NULL); 5149 if (status == I40E_SUCCESS) 5150 *val = (u16)reg_val_aq; 5151 return status; 5152 } 5153 temp_addr = I40E_PHY_LED_PROV_REG_1; 5154 i = rd32(hw, I40E_PFGEN_PORTNUM); 5155 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5156 phy_addr = i40e_get_phy_address(hw, port_num); 5157 5158 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 5159 temp_addr++) { 5160 status = i40e_read_phy_register_clause45(hw, 5161 I40E_PHY_COM_REG_PAGE, 5162 temp_addr, phy_addr, 5163 ®_val); 5164 if (status) 5165 return status; 5166 *val = reg_val; 5167 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 5168 *led_addr = temp_addr; 5169 break; 5170 } 5171 } 5172 return status; 5173 } 5174 5175 /** 5176 * i40e_led_set_phy 5177 * @hw: pointer to the HW structure 5178 * @on: true or false 5179 * @led_addr: address of led register to use 5180 * @mode: original val plus bit for set or ignore 5181 * 5182 * Set led's on or off when controlled by the PHY 5183 * 5184 **/ 5185 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 5186 u16 led_addr, u32 mode) 5187 { 5188 i40e_status status = 0; 5189 u32 led_ctl = 0; 5190 u32 led_reg = 0; 5191 5192 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5193 if (status) 5194 return status; 5195 led_ctl = led_reg; 5196 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 5197 led_reg = 0; 5198 status = i40e_led_set_reg(hw, led_addr, led_reg); 5199 if (status) 5200 return status; 5201 } 5202 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5203 if (status) 5204 goto restore_config; 5205 if (on) 5206 led_reg = I40E_PHY_LED_MANUAL_ON; 5207 else 5208 led_reg = 0; 5209 5210 status = i40e_led_set_reg(hw, led_addr, led_reg); 5211 if (status) 5212 goto restore_config; 5213 if (mode & I40E_PHY_LED_MODE_ORIG) { 5214 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 5215 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5216 } 5217 return status; 5218 5219 restore_config: 5220 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5221 return status; 5222 } 5223 5224 /** 5225 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 5226 * @hw: pointer to the hw struct 5227 * @reg_addr: register address 5228 * @reg_val: ptr to register value 5229 * @cmd_details: pointer to command details structure or NULL 5230 * 5231 * Use the firmware to read the Rx control register, 5232 * especially useful if the Rx unit is under heavy pressure 5233 **/ 5234 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 5235 u32 reg_addr, u32 *reg_val, 5236 struct i40e_asq_cmd_details *cmd_details) 5237 { 5238 struct i40e_aq_desc desc; 5239 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 5240 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5241 i40e_status status; 5242 5243 if (!reg_val) 5244 return I40E_ERR_PARAM; 5245 5246 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 5247 5248 cmd_resp->address = cpu_to_le32(reg_addr); 5249 5250 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5251 5252 if (status == 0) 5253 *reg_val = le32_to_cpu(cmd_resp->value); 5254 5255 return status; 5256 } 5257 5258 /** 5259 * i40e_read_rx_ctl - read from an Rx control register 5260 * @hw: pointer to the hw struct 5261 * @reg_addr: register address 5262 **/ 5263 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 5264 { 5265 i40e_status status = 0; 5266 bool use_register; 5267 int retry = 5; 5268 u32 val = 0; 5269 5270 use_register = (((hw->aq.api_maj_ver == 1) && 5271 (hw->aq.api_min_ver < 5)) || 5272 (hw->mac.type == I40E_MAC_X722)); 5273 if (!use_register) { 5274 do_retry: 5275 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 5276 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5277 usleep_range(1000, 2000); 5278 retry--; 5279 goto do_retry; 5280 } 5281 } 5282 5283 /* if the AQ access failed, try the old-fashioned way */ 5284 if (status || use_register) 5285 val = rd32(hw, reg_addr); 5286 5287 return val; 5288 } 5289 5290 /** 5291 * i40e_aq_rx_ctl_write_register 5292 * @hw: pointer to the hw struct 5293 * @reg_addr: register address 5294 * @reg_val: register value 5295 * @cmd_details: pointer to command details structure or NULL 5296 * 5297 * Use the firmware to write to an Rx control register, 5298 * especially useful if the Rx unit is under heavy pressure 5299 **/ 5300 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 5301 u32 reg_addr, u32 reg_val, 5302 struct i40e_asq_cmd_details *cmd_details) 5303 { 5304 struct i40e_aq_desc desc; 5305 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 5306 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5307 i40e_status status; 5308 5309 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 5310 5311 cmd->address = cpu_to_le32(reg_addr); 5312 cmd->value = cpu_to_le32(reg_val); 5313 5314 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5315 5316 return status; 5317 } 5318 5319 /** 5320 * i40e_write_rx_ctl - write to an Rx control register 5321 * @hw: pointer to the hw struct 5322 * @reg_addr: register address 5323 * @reg_val: register value 5324 **/ 5325 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5326 { 5327 i40e_status status = 0; 5328 bool use_register; 5329 int retry = 5; 5330 5331 use_register = (((hw->aq.api_maj_ver == 1) && 5332 (hw->aq.api_min_ver < 5)) || 5333 (hw->mac.type == I40E_MAC_X722)); 5334 if (!use_register) { 5335 do_retry: 5336 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5337 reg_val, NULL); 5338 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5339 usleep_range(1000, 2000); 5340 retry--; 5341 goto do_retry; 5342 } 5343 } 5344 5345 /* if the AQ access failed, try the old-fashioned way */ 5346 if (status || use_register) 5347 wr32(hw, reg_addr, reg_val); 5348 } 5349 5350 /** 5351 * i40e_mdio_if_number_selection - MDIO I/F number selection 5352 * @hw: pointer to the hw struct 5353 * @set_mdio: use MDIO I/F number specified by mdio_num 5354 * @mdio_num: MDIO I/F number 5355 * @cmd: pointer to PHY Register command structure 5356 **/ 5357 static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, 5358 u8 mdio_num, 5359 struct i40e_aqc_phy_register_access *cmd) 5360 { 5361 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) { 5362 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED) 5363 cmd->cmd_flags |= 5364 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 5365 ((mdio_num << 5366 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) & 5367 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK); 5368 else 5369 i40e_debug(hw, I40E_DEBUG_PHY, 5370 "MDIO I/F number selection not supported by current FW version.\n"); 5371 } 5372 } 5373 5374 /** 5375 * i40e_aq_set_phy_register_ext 5376 * @hw: pointer to the hw struct 5377 * @phy_select: select which phy should be accessed 5378 * @dev_addr: PHY device address 5379 * @set_mdio: use MDIO I/F number specified by mdio_num 5380 * @mdio_num: MDIO I/F number 5381 * @reg_addr: PHY register address 5382 * @reg_val: new register value 5383 * @cmd_details: pointer to command details structure or NULL 5384 * 5385 * Write the external PHY register. 5386 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 5387 * may use simple wrapper i40e_aq_set_phy_register. 5388 **/ 5389 enum i40e_status_code i40e_aq_set_phy_register_ext(struct i40e_hw *hw, 5390 u8 phy_select, u8 dev_addr, bool page_change, 5391 bool set_mdio, u8 mdio_num, 5392 u32 reg_addr, u32 reg_val, 5393 struct i40e_asq_cmd_details *cmd_details) 5394 { 5395 struct i40e_aq_desc desc; 5396 struct i40e_aqc_phy_register_access *cmd = 5397 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5398 i40e_status status; 5399 5400 i40e_fill_default_direct_cmd_desc(&desc, 5401 i40e_aqc_opc_set_phy_register); 5402 5403 cmd->phy_interface = phy_select; 5404 cmd->dev_address = dev_addr; 5405 cmd->reg_address = cpu_to_le32(reg_addr); 5406 cmd->reg_value = cpu_to_le32(reg_val); 5407 5408 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 5409 5410 if (!page_change) 5411 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 5412 5413 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5414 5415 return status; 5416 } 5417 5418 /** 5419 * i40e_aq_get_phy_register_ext 5420 * @hw: pointer to the hw struct 5421 * @phy_select: select which phy should be accessed 5422 * @dev_addr: PHY device address 5423 * @set_mdio: use MDIO I/F number specified by mdio_num 5424 * @mdio_num: MDIO I/F number 5425 * @reg_addr: PHY register address 5426 * @reg_val: read register value 5427 * @cmd_details: pointer to command details structure or NULL 5428 * 5429 * Read the external PHY register. 5430 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 5431 * may use simple wrapper i40e_aq_get_phy_register. 5432 **/ 5433 enum i40e_status_code i40e_aq_get_phy_register_ext(struct i40e_hw *hw, 5434 u8 phy_select, u8 dev_addr, bool page_change, 5435 bool set_mdio, u8 mdio_num, 5436 u32 reg_addr, u32 *reg_val, 5437 struct i40e_asq_cmd_details *cmd_details) 5438 { 5439 struct i40e_aq_desc desc; 5440 struct i40e_aqc_phy_register_access *cmd = 5441 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5442 i40e_status status; 5443 5444 i40e_fill_default_direct_cmd_desc(&desc, 5445 i40e_aqc_opc_get_phy_register); 5446 5447 cmd->phy_interface = phy_select; 5448 cmd->dev_address = dev_addr; 5449 cmd->reg_address = cpu_to_le32(reg_addr); 5450 5451 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 5452 5453 if (!page_change) 5454 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 5455 5456 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5457 if (!status) 5458 *reg_val = le32_to_cpu(cmd->reg_value); 5459 5460 return status; 5461 } 5462 5463 /** 5464 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 5465 * @hw: pointer to the hw struct 5466 * @buff: command buffer (size in bytes = buff_size) 5467 * @buff_size: buffer size in bytes 5468 * @track_id: package tracking id 5469 * @error_offset: returns error offset 5470 * @error_info: returns error information 5471 * @cmd_details: pointer to command details structure or NULL 5472 **/ 5473 enum 5474 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 5475 u16 buff_size, u32 track_id, 5476 u32 *error_offset, u32 *error_info, 5477 struct i40e_asq_cmd_details *cmd_details) 5478 { 5479 struct i40e_aq_desc desc; 5480 struct i40e_aqc_write_personalization_profile *cmd = 5481 (struct i40e_aqc_write_personalization_profile *) 5482 &desc.params.raw; 5483 struct i40e_aqc_write_ddp_resp *resp; 5484 i40e_status status; 5485 5486 i40e_fill_default_direct_cmd_desc(&desc, 5487 i40e_aqc_opc_write_personalization_profile); 5488 5489 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 5490 if (buff_size > I40E_AQ_LARGE_BUF) 5491 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5492 5493 desc.datalen = cpu_to_le16(buff_size); 5494 5495 cmd->profile_track_id = cpu_to_le32(track_id); 5496 5497 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5498 if (!status) { 5499 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 5500 if (error_offset) 5501 *error_offset = le32_to_cpu(resp->error_offset); 5502 if (error_info) 5503 *error_info = le32_to_cpu(resp->error_info); 5504 } 5505 5506 return status; 5507 } 5508 5509 /** 5510 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 5511 * @hw: pointer to the hw struct 5512 * @buff: command buffer (size in bytes = buff_size) 5513 * @buff_size: buffer size in bytes 5514 * @flags: AdminQ command flags 5515 * @cmd_details: pointer to command details structure or NULL 5516 **/ 5517 enum 5518 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 5519 u16 buff_size, u8 flags, 5520 struct i40e_asq_cmd_details *cmd_details) 5521 { 5522 struct i40e_aq_desc desc; 5523 struct i40e_aqc_get_applied_profiles *cmd = 5524 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 5525 i40e_status status; 5526 5527 i40e_fill_default_direct_cmd_desc(&desc, 5528 i40e_aqc_opc_get_personalization_profile_list); 5529 5530 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 5531 if (buff_size > I40E_AQ_LARGE_BUF) 5532 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5533 desc.datalen = cpu_to_le16(buff_size); 5534 5535 cmd->flags = flags; 5536 5537 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5538 5539 return status; 5540 } 5541 5542 /** 5543 * i40e_find_segment_in_package 5544 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 5545 * @pkg_hdr: pointer to the package header to be searched 5546 * 5547 * This function searches a package file for a particular segment type. On 5548 * success it returns a pointer to the segment header, otherwise it will 5549 * return NULL. 5550 **/ 5551 struct i40e_generic_seg_header * 5552 i40e_find_segment_in_package(u32 segment_type, 5553 struct i40e_package_header *pkg_hdr) 5554 { 5555 struct i40e_generic_seg_header *segment; 5556 u32 i; 5557 5558 /* Search all package segments for the requested segment type */ 5559 for (i = 0; i < pkg_hdr->segment_count; i++) { 5560 segment = 5561 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 5562 pkg_hdr->segment_offset[i]); 5563 5564 if (segment->type == segment_type) 5565 return segment; 5566 } 5567 5568 return NULL; 5569 } 5570 5571 /* Get section table in profile */ 5572 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 5573 do { \ 5574 struct i40e_profile_segment *p = (profile); \ 5575 u32 count; \ 5576 u32 *nvm; \ 5577 count = p->device_table_count; \ 5578 nvm = (u32 *)&p->device_table[count]; \ 5579 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 5580 } while (0) 5581 5582 /* Get section header in profile */ 5583 #define I40E_SECTION_HEADER(profile, offset) \ 5584 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 5585 5586 /** 5587 * i40e_find_section_in_profile 5588 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE) 5589 * @profile: pointer to the i40e segment header to be searched 5590 * 5591 * This function searches i40e segment for a particular section type. On 5592 * success it returns a pointer to the section header, otherwise it will 5593 * return NULL. 5594 **/ 5595 struct i40e_profile_section_header * 5596 i40e_find_section_in_profile(u32 section_type, 5597 struct i40e_profile_segment *profile) 5598 { 5599 struct i40e_profile_section_header *sec; 5600 struct i40e_section_table *sec_tbl; 5601 u32 sec_off; 5602 u32 i; 5603 5604 if (profile->header.type != SEGMENT_TYPE_I40E) 5605 return NULL; 5606 5607 I40E_SECTION_TABLE(profile, sec_tbl); 5608 5609 for (i = 0; i < sec_tbl->section_count; i++) { 5610 sec_off = sec_tbl->section_offset[i]; 5611 sec = I40E_SECTION_HEADER(profile, sec_off); 5612 if (sec->section.type == section_type) 5613 return sec; 5614 } 5615 5616 return NULL; 5617 } 5618 5619 /** 5620 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 5621 * @hw: pointer to the hw struct 5622 * @aq: command buffer containing all data to execute AQ 5623 **/ 5624 static enum 5625 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw, 5626 struct i40e_profile_aq_section *aq) 5627 { 5628 i40e_status status; 5629 struct i40e_aq_desc desc; 5630 u8 *msg = NULL; 5631 u16 msglen; 5632 5633 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 5634 desc.flags |= cpu_to_le16(aq->flags); 5635 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw)); 5636 5637 msglen = aq->datalen; 5638 if (msglen) { 5639 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 5640 I40E_AQ_FLAG_RD)); 5641 if (msglen > I40E_AQ_LARGE_BUF) 5642 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5643 desc.datalen = cpu_to_le16(msglen); 5644 msg = &aq->data[0]; 5645 } 5646 5647 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 5648 5649 if (status) { 5650 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5651 "unable to exec DDP AQ opcode %u, error %d\n", 5652 aq->opcode, status); 5653 return status; 5654 } 5655 5656 /* copy returned desc to aq_buf */ 5657 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw)); 5658 5659 return 0; 5660 } 5661 5662 /** 5663 * i40e_validate_profile 5664 * @hw: pointer to the hardware structure 5665 * @profile: pointer to the profile segment of the package to be validated 5666 * @track_id: package tracking id 5667 * @rollback: flag if the profile is for rollback. 5668 * 5669 * Validates supported devices and profile's sections. 5670 */ 5671 static enum i40e_status_code 5672 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5673 u32 track_id, bool rollback) 5674 { 5675 struct i40e_profile_section_header *sec = NULL; 5676 i40e_status status = 0; 5677 struct i40e_section_table *sec_tbl; 5678 u32 vendor_dev_id; 5679 u32 dev_cnt; 5680 u32 sec_off; 5681 u32 i; 5682 5683 if (track_id == I40E_DDP_TRACKID_INVALID) { 5684 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 5685 return I40E_NOT_SUPPORTED; 5686 } 5687 5688 dev_cnt = profile->device_table_count; 5689 for (i = 0; i < dev_cnt; i++) { 5690 vendor_dev_id = profile->device_table[i].vendor_dev_id; 5691 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL && 5692 hw->device_id == (vendor_dev_id & 0xFFFF)) 5693 break; 5694 } 5695 if (dev_cnt && i == dev_cnt) { 5696 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5697 "Device doesn't support DDP\n"); 5698 return I40E_ERR_DEVICE_NOT_SUPPORTED; 5699 } 5700 5701 I40E_SECTION_TABLE(profile, sec_tbl); 5702 5703 /* Validate sections types */ 5704 for (i = 0; i < sec_tbl->section_count; i++) { 5705 sec_off = sec_tbl->section_offset[i]; 5706 sec = I40E_SECTION_HEADER(profile, sec_off); 5707 if (rollback) { 5708 if (sec->section.type == SECTION_TYPE_MMIO || 5709 sec->section.type == SECTION_TYPE_AQ || 5710 sec->section.type == SECTION_TYPE_RB_AQ) { 5711 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5712 "Not a roll-back package\n"); 5713 return I40E_NOT_SUPPORTED; 5714 } 5715 } else { 5716 if (sec->section.type == SECTION_TYPE_RB_AQ || 5717 sec->section.type == SECTION_TYPE_RB_MMIO) { 5718 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5719 "Not an original package\n"); 5720 return I40E_NOT_SUPPORTED; 5721 } 5722 } 5723 } 5724 5725 return status; 5726 } 5727 5728 /** 5729 * i40e_write_profile 5730 * @hw: pointer to the hardware structure 5731 * @profile: pointer to the profile segment of the package to be downloaded 5732 * @track_id: package tracking id 5733 * 5734 * Handles the download of a complete package. 5735 */ 5736 enum i40e_status_code 5737 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5738 u32 track_id) 5739 { 5740 i40e_status status = 0; 5741 struct i40e_section_table *sec_tbl; 5742 struct i40e_profile_section_header *sec = NULL; 5743 struct i40e_profile_aq_section *ddp_aq; 5744 u32 section_size = 0; 5745 u32 offset = 0, info = 0; 5746 u32 sec_off; 5747 u32 i; 5748 5749 status = i40e_validate_profile(hw, profile, track_id, false); 5750 if (status) 5751 return status; 5752 5753 I40E_SECTION_TABLE(profile, sec_tbl); 5754 5755 for (i = 0; i < sec_tbl->section_count; i++) { 5756 sec_off = sec_tbl->section_offset[i]; 5757 sec = I40E_SECTION_HEADER(profile, sec_off); 5758 /* Process generic admin command */ 5759 if (sec->section.type == SECTION_TYPE_AQ) { 5760 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 5761 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 5762 if (status) { 5763 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5764 "Failed to execute aq: section %d, opcode %u\n", 5765 i, ddp_aq->opcode); 5766 break; 5767 } 5768 sec->section.type = SECTION_TYPE_RB_AQ; 5769 } 5770 5771 /* Skip any non-mmio sections */ 5772 if (sec->section.type != SECTION_TYPE_MMIO) 5773 continue; 5774 5775 section_size = sec->section.size + 5776 sizeof(struct i40e_profile_section_header); 5777 5778 /* Write MMIO section */ 5779 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5780 track_id, &offset, &info, NULL); 5781 if (status) { 5782 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5783 "Failed to write profile: section %d, offset %d, info %d\n", 5784 i, offset, info); 5785 break; 5786 } 5787 } 5788 return status; 5789 } 5790 5791 /** 5792 * i40e_rollback_profile 5793 * @hw: pointer to the hardware structure 5794 * @profile: pointer to the profile segment of the package to be removed 5795 * @track_id: package tracking id 5796 * 5797 * Rolls back previously loaded package. 5798 */ 5799 enum i40e_status_code 5800 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5801 u32 track_id) 5802 { 5803 struct i40e_profile_section_header *sec = NULL; 5804 i40e_status status = 0; 5805 struct i40e_section_table *sec_tbl; 5806 u32 offset = 0, info = 0; 5807 u32 section_size = 0; 5808 u32 sec_off; 5809 int i; 5810 5811 status = i40e_validate_profile(hw, profile, track_id, true); 5812 if (status) 5813 return status; 5814 5815 I40E_SECTION_TABLE(profile, sec_tbl); 5816 5817 /* For rollback write sections in reverse */ 5818 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 5819 sec_off = sec_tbl->section_offset[i]; 5820 sec = I40E_SECTION_HEADER(profile, sec_off); 5821 5822 /* Skip any non-rollback sections */ 5823 if (sec->section.type != SECTION_TYPE_RB_MMIO) 5824 continue; 5825 5826 section_size = sec->section.size + 5827 sizeof(struct i40e_profile_section_header); 5828 5829 /* Write roll-back MMIO section */ 5830 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5831 track_id, &offset, &info, NULL); 5832 if (status) { 5833 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5834 "Failed to write profile: section %d, offset %d, info %d\n", 5835 i, offset, info); 5836 break; 5837 } 5838 } 5839 return status; 5840 } 5841 5842 /** 5843 * i40e_add_pinfo_to_list 5844 * @hw: pointer to the hardware structure 5845 * @profile: pointer to the profile segment of the package 5846 * @profile_info_sec: buffer for information section 5847 * @track_id: package tracking id 5848 * 5849 * Register a profile to the list of loaded profiles. 5850 */ 5851 enum i40e_status_code 5852 i40e_add_pinfo_to_list(struct i40e_hw *hw, 5853 struct i40e_profile_segment *profile, 5854 u8 *profile_info_sec, u32 track_id) 5855 { 5856 i40e_status status = 0; 5857 struct i40e_profile_section_header *sec = NULL; 5858 struct i40e_profile_info *pinfo; 5859 u32 offset = 0, info = 0; 5860 5861 sec = (struct i40e_profile_section_header *)profile_info_sec; 5862 sec->tbl_size = 1; 5863 sec->data_end = sizeof(struct i40e_profile_section_header) + 5864 sizeof(struct i40e_profile_info); 5865 sec->section.type = SECTION_TYPE_INFO; 5866 sec->section.offset = sizeof(struct i40e_profile_section_header); 5867 sec->section.size = sizeof(struct i40e_profile_info); 5868 pinfo = (struct i40e_profile_info *)(profile_info_sec + 5869 sec->section.offset); 5870 pinfo->track_id = track_id; 5871 pinfo->version = profile->version; 5872 pinfo->op = I40E_DDP_ADD_TRACKID; 5873 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE); 5874 5875 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end, 5876 track_id, &offset, &info, NULL); 5877 5878 return status; 5879 } 5880 5881 /** 5882 * i40e_aq_add_cloud_filters 5883 * @hw: pointer to the hardware structure 5884 * @seid: VSI seid to add cloud filters from 5885 * @filters: Buffer which contains the filters to be added 5886 * @filter_count: number of filters contained in the buffer 5887 * 5888 * Set the cloud filters for a given VSI. The contents of the 5889 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5890 * of the function. 5891 * 5892 **/ 5893 enum i40e_status_code 5894 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5895 struct i40e_aqc_cloud_filters_element_data *filters, 5896 u8 filter_count) 5897 { 5898 struct i40e_aq_desc desc; 5899 struct i40e_aqc_add_remove_cloud_filters *cmd = 5900 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5901 enum i40e_status_code status; 5902 u16 buff_len; 5903 5904 i40e_fill_default_direct_cmd_desc(&desc, 5905 i40e_aqc_opc_add_cloud_filters); 5906 5907 buff_len = filter_count * sizeof(*filters); 5908 desc.datalen = cpu_to_le16(buff_len); 5909 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5910 cmd->num_filters = filter_count; 5911 cmd->seid = cpu_to_le16(seid); 5912 5913 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5914 5915 return status; 5916 } 5917 5918 /** 5919 * i40e_aq_add_cloud_filters_bb 5920 * @hw: pointer to the hardware structure 5921 * @seid: VSI seid to add cloud filters from 5922 * @filters: Buffer which contains the filters in big buffer to be added 5923 * @filter_count: number of filters contained in the buffer 5924 * 5925 * Set the big buffer cloud filters for a given VSI. The contents of the 5926 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5927 * function. 5928 * 5929 **/ 5930 enum i40e_status_code 5931 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5932 struct i40e_aqc_cloud_filters_element_bb *filters, 5933 u8 filter_count) 5934 { 5935 struct i40e_aq_desc desc; 5936 struct i40e_aqc_add_remove_cloud_filters *cmd = 5937 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5938 i40e_status status; 5939 u16 buff_len; 5940 int i; 5941 5942 i40e_fill_default_direct_cmd_desc(&desc, 5943 i40e_aqc_opc_add_cloud_filters); 5944 5945 buff_len = filter_count * sizeof(*filters); 5946 desc.datalen = cpu_to_le16(buff_len); 5947 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5948 cmd->num_filters = filter_count; 5949 cmd->seid = cpu_to_le16(seid); 5950 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5951 5952 for (i = 0; i < filter_count; i++) { 5953 u16 tnl_type; 5954 u32 ti; 5955 5956 tnl_type = (le16_to_cpu(filters[i].element.flags) & 5957 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5958 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5959 5960 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5961 * one more byte further than normally used for Tenant ID in 5962 * other tunnel types. 5963 */ 5964 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5965 ti = le32_to_cpu(filters[i].element.tenant_id); 5966 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5967 } 5968 } 5969 5970 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5971 5972 return status; 5973 } 5974 5975 /** 5976 * i40e_aq_rem_cloud_filters 5977 * @hw: pointer to the hardware structure 5978 * @seid: VSI seid to remove cloud filters from 5979 * @filters: Buffer which contains the filters to be removed 5980 * @filter_count: number of filters contained in the buffer 5981 * 5982 * Remove the cloud filters for a given VSI. The contents of the 5983 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5984 * of the function. 5985 * 5986 **/ 5987 enum i40e_status_code 5988 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5989 struct i40e_aqc_cloud_filters_element_data *filters, 5990 u8 filter_count) 5991 { 5992 struct i40e_aq_desc desc; 5993 struct i40e_aqc_add_remove_cloud_filters *cmd = 5994 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5995 enum i40e_status_code status; 5996 u16 buff_len; 5997 5998 i40e_fill_default_direct_cmd_desc(&desc, 5999 i40e_aqc_opc_remove_cloud_filters); 6000 6001 buff_len = filter_count * sizeof(*filters); 6002 desc.datalen = cpu_to_le16(buff_len); 6003 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 6004 cmd->num_filters = filter_count; 6005 cmd->seid = cpu_to_le16(seid); 6006 6007 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 6008 6009 return status; 6010 } 6011 6012 /** 6013 * i40e_aq_rem_cloud_filters_bb 6014 * @hw: pointer to the hardware structure 6015 * @seid: VSI seid to remove cloud filters from 6016 * @filters: Buffer which contains the filters in big buffer to be removed 6017 * @filter_count: number of filters contained in the buffer 6018 * 6019 * Remove the big buffer cloud filters for a given VSI. The contents of the 6020 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 6021 * function. 6022 * 6023 **/ 6024 enum i40e_status_code 6025 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 6026 struct i40e_aqc_cloud_filters_element_bb *filters, 6027 u8 filter_count) 6028 { 6029 struct i40e_aq_desc desc; 6030 struct i40e_aqc_add_remove_cloud_filters *cmd = 6031 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 6032 i40e_status status; 6033 u16 buff_len; 6034 int i; 6035 6036 i40e_fill_default_direct_cmd_desc(&desc, 6037 i40e_aqc_opc_remove_cloud_filters); 6038 6039 buff_len = filter_count * sizeof(*filters); 6040 desc.datalen = cpu_to_le16(buff_len); 6041 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 6042 cmd->num_filters = filter_count; 6043 cmd->seid = cpu_to_le16(seid); 6044 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 6045 6046 for (i = 0; i < filter_count; i++) { 6047 u16 tnl_type; 6048 u32 ti; 6049 6050 tnl_type = (le16_to_cpu(filters[i].element.flags) & 6051 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 6052 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 6053 6054 /* Due to hardware eccentricities, the VNI for Geneve is shifted 6055 * one more byte further than normally used for Tenant ID in 6056 * other tunnel types. 6057 */ 6058 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 6059 ti = le32_to_cpu(filters[i].element.tenant_id); 6060 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 6061 } 6062 } 6063 6064 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 6065 6066 return status; 6067 } 6068