1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #include <linux/avf/virtchnl.h> 5 #include <linux/bitfield.h> 6 #include <linux/delay.h> 7 #include <linux/etherdevice.h> 8 #include <linux/pci.h> 9 #include "i40e_adminq_cmd.h" 10 #include "i40e_devids.h" 11 #include "i40e_prototype.h" 12 #include "i40e_register.h" 13 14 /** 15 * i40e_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the mac type of the adapter based on the 19 * vendor ID and device ID stored in the hw structure. 20 **/ 21 int i40e_set_mac_type(struct i40e_hw *hw) 22 { 23 int status = 0; 24 25 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 26 switch (hw->device_id) { 27 case I40E_DEV_ID_SFP_XL710: 28 case I40E_DEV_ID_QEMU: 29 case I40E_DEV_ID_KX_B: 30 case I40E_DEV_ID_KX_C: 31 case I40E_DEV_ID_QSFP_A: 32 case I40E_DEV_ID_QSFP_B: 33 case I40E_DEV_ID_QSFP_C: 34 case I40E_DEV_ID_1G_BASE_T_BC: 35 case I40E_DEV_ID_5G_BASE_T_BC: 36 case I40E_DEV_ID_10G_BASE_T: 37 case I40E_DEV_ID_10G_BASE_T4: 38 case I40E_DEV_ID_10G_BASE_T_BC: 39 case I40E_DEV_ID_10G_B: 40 case I40E_DEV_ID_10G_SFP: 41 case I40E_DEV_ID_20G_KR2: 42 case I40E_DEV_ID_20G_KR2_A: 43 case I40E_DEV_ID_25G_B: 44 case I40E_DEV_ID_25G_SFP28: 45 case I40E_DEV_ID_X710_N3000: 46 case I40E_DEV_ID_XXV710_N3000: 47 hw->mac.type = I40E_MAC_XL710; 48 break; 49 case I40E_DEV_ID_KX_X722: 50 case I40E_DEV_ID_QSFP_X722: 51 case I40E_DEV_ID_SFP_X722: 52 case I40E_DEV_ID_1G_BASE_T_X722: 53 case I40E_DEV_ID_10G_BASE_T_X722: 54 case I40E_DEV_ID_SFP_I_X722: 55 case I40E_DEV_ID_SFP_X722_A: 56 hw->mac.type = I40E_MAC_X722; 57 break; 58 default: 59 hw->mac.type = I40E_MAC_GENERIC; 60 break; 61 } 62 } else { 63 status = -ENODEV; 64 } 65 66 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 67 hw->mac.type, status); 68 return status; 69 } 70 71 /** 72 * i40e_debug_aq 73 * @hw: debug mask related to admin queue 74 * @mask: debug mask 75 * @desc: pointer to admin queue descriptor 76 * @buffer: pointer to command buffer 77 * @buf_len: max length of buffer 78 * 79 * Dumps debug log about adminq command with descriptor contents. 80 **/ 81 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 82 void *buffer, u16 buf_len) 83 { 84 struct libie_aq_desc *aq_desc = (struct libie_aq_desc *)desc; 85 u32 effective_mask = hw->debug_mask & mask; 86 char prefix[27]; 87 u16 len; 88 u8 *buf = (u8 *)buffer; 89 90 if (!effective_mask || !desc) 91 return; 92 93 len = le16_to_cpu(aq_desc->datalen); 94 95 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 96 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 97 le16_to_cpu(aq_desc->opcode), 98 le16_to_cpu(aq_desc->flags), 99 le16_to_cpu(aq_desc->datalen), 100 le16_to_cpu(aq_desc->retval)); 101 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 102 "\tcookie (h,l) 0x%08X 0x%08X\n", 103 le32_to_cpu(aq_desc->cookie_high), 104 le32_to_cpu(aq_desc->cookie_low)); 105 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 106 "\tparam (0,1) 0x%08X 0x%08X\n", 107 le32_to_cpu(aq_desc->params.generic.param0), 108 le32_to_cpu(aq_desc->params.generic.param1)); 109 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 110 "\taddr (h,l) 0x%08X 0x%08X\n", 111 le32_to_cpu(aq_desc->params.generic.addr_high), 112 le32_to_cpu(aq_desc->params.generic.addr_low)); 113 114 if (buffer && buf_len != 0 && len != 0 && 115 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { 116 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 117 if (buf_len < len) 118 len = buf_len; 119 120 snprintf(prefix, sizeof(prefix), 121 "i40e %02x:%02x.%x: \t0x", 122 hw->bus.bus_id, 123 hw->bus.device, 124 hw->bus.func); 125 126 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 127 16, 1, buf, len, false); 128 } 129 } 130 131 /** 132 * i40e_check_asq_alive 133 * @hw: pointer to the hw struct 134 * 135 * Returns true if Queue is enabled else false. 136 **/ 137 bool i40e_check_asq_alive(struct i40e_hw *hw) 138 { 139 /* Check if the queue is initialized */ 140 if (!hw->aq.asq.count) 141 return false; 142 143 return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK); 144 } 145 146 /** 147 * i40e_aq_queue_shutdown 148 * @hw: pointer to the hw struct 149 * @unloading: is the driver unloading itself 150 * 151 * Tell the Firmware that we're shutting down the AdminQ and whether 152 * or not the driver is unloading as well. 153 **/ 154 int i40e_aq_queue_shutdown(struct i40e_hw *hw, 155 bool unloading) 156 { 157 struct i40e_aqc_queue_shutdown *cmd; 158 struct libie_aq_desc desc; 159 int status; 160 161 i40e_fill_default_direct_cmd_desc(&desc, 162 i40e_aqc_opc_queue_shutdown); 163 164 cmd = libie_aq_raw(&desc); 165 if (unloading) 166 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 167 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 168 169 return status; 170 } 171 172 /** 173 * i40e_aq_get_set_rss_lut 174 * @hw: pointer to the hardware structure 175 * @vsi_id: vsi fw index 176 * @pf_lut: for PF table set true, for VSI table set false 177 * @lut: pointer to the lut buffer provided by the caller 178 * @lut_size: size of the lut buffer 179 * @set: set true to set the table, false to get the table 180 * 181 * Internal function to get or set RSS look up table 182 **/ 183 static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 184 u16 vsi_id, bool pf_lut, 185 u8 *lut, u16 lut_size, 186 bool set) 187 { 188 struct i40e_aqc_get_set_rss_lut *cmd_resp; 189 struct libie_aq_desc desc; 190 int status; 191 u16 flags; 192 193 if (set) 194 i40e_fill_default_direct_cmd_desc(&desc, 195 i40e_aqc_opc_set_rss_lut); 196 else 197 i40e_fill_default_direct_cmd_desc(&desc, 198 i40e_aqc_opc_get_rss_lut); 199 200 cmd_resp = libie_aq_raw(&desc); 201 /* Indirect command */ 202 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 203 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 204 205 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) | 206 FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1); 207 cmd_resp->vsi_id = cpu_to_le16(vsi_id); 208 209 if (pf_lut) 210 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 211 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF); 212 else 213 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 214 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI); 215 216 cmd_resp->flags = cpu_to_le16(flags); 217 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 218 219 return status; 220 } 221 222 /** 223 * i40e_aq_get_rss_lut 224 * @hw: pointer to the hardware structure 225 * @vsi_id: vsi fw index 226 * @pf_lut: for PF table set true, for VSI table set false 227 * @lut: pointer to the lut buffer provided by the caller 228 * @lut_size: size of the lut buffer 229 * 230 * get the RSS lookup table, PF or VSI type 231 **/ 232 int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 233 bool pf_lut, u8 *lut, u16 lut_size) 234 { 235 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 236 false); 237 } 238 239 /** 240 * i40e_aq_set_rss_lut 241 * @hw: pointer to the hardware structure 242 * @vsi_id: vsi fw index 243 * @pf_lut: for PF table set true, for VSI table set false 244 * @lut: pointer to the lut buffer provided by the caller 245 * @lut_size: size of the lut buffer 246 * 247 * set the RSS lookup table, PF or VSI type 248 **/ 249 int i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 250 bool pf_lut, u8 *lut, u16 lut_size) 251 { 252 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 253 } 254 255 /** 256 * i40e_aq_get_set_rss_key 257 * @hw: pointer to the hw struct 258 * @vsi_id: vsi fw index 259 * @key: pointer to key info struct 260 * @set: set true to set the key, false to get the key 261 * 262 * get the RSS key per VSI 263 **/ 264 static int i40e_aq_get_set_rss_key(struct i40e_hw *hw, 265 u16 vsi_id, 266 struct i40e_aqc_get_set_rss_key_data *key, 267 bool set) 268 { 269 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 270 struct i40e_aqc_get_set_rss_key *cmd_resp; 271 struct libie_aq_desc desc; 272 int status; 273 274 if (set) 275 i40e_fill_default_direct_cmd_desc(&desc, 276 i40e_aqc_opc_set_rss_key); 277 else 278 i40e_fill_default_direct_cmd_desc(&desc, 279 i40e_aqc_opc_get_rss_key); 280 281 cmd_resp = libie_aq_raw(&desc); 282 /* Indirect command */ 283 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 284 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 285 286 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) | 287 FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1); 288 cmd_resp->vsi_id = cpu_to_le16(vsi_id); 289 290 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 291 292 return status; 293 } 294 295 /** 296 * i40e_aq_get_rss_key 297 * @hw: pointer to the hw struct 298 * @vsi_id: vsi fw index 299 * @key: pointer to key info struct 300 * 301 **/ 302 int i40e_aq_get_rss_key(struct i40e_hw *hw, 303 u16 vsi_id, 304 struct i40e_aqc_get_set_rss_key_data *key) 305 { 306 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 307 } 308 309 /** 310 * i40e_aq_set_rss_key 311 * @hw: pointer to the hw struct 312 * @vsi_id: vsi fw index 313 * @key: pointer to key info struct 314 * 315 * set the RSS key per VSI 316 **/ 317 int i40e_aq_set_rss_key(struct i40e_hw *hw, 318 u16 vsi_id, 319 struct i40e_aqc_get_set_rss_key_data *key) 320 { 321 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 322 } 323 324 /** 325 * i40e_init_shared_code - Initialize the shared code 326 * @hw: pointer to hardware structure 327 * 328 * This assigns the MAC type and PHY code and inits the NVM. 329 * Does not touch the hardware. This function must be called prior to any 330 * other function in the shared code. The i40e_hw structure should be 331 * memset to 0 prior to calling this function. The following fields in 332 * hw structure should be filled in prior to calling this function: 333 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 334 * subsystem_vendor_id, and revision_id 335 **/ 336 int i40e_init_shared_code(struct i40e_hw *hw) 337 { 338 u32 port, ari, func_rid; 339 int status = 0; 340 341 i40e_set_mac_type(hw); 342 343 switch (hw->mac.type) { 344 case I40E_MAC_XL710: 345 case I40E_MAC_X722: 346 break; 347 default: 348 return -ENODEV; 349 } 350 351 hw->phy.get_link_info = true; 352 353 /* Determine port number and PF number*/ 354 port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK, 355 rd32(hw, I40E_PFGEN_PORTNUM)); 356 hw->port = (u8)port; 357 ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK, 358 rd32(hw, I40E_GLPCI_CAPSUP)); 359 func_rid = rd32(hw, I40E_PF_FUNC_RID); 360 if (ari) 361 hw->pf_id = (u8)(func_rid & 0xff); 362 else 363 hw->pf_id = (u8)(func_rid & 0x7); 364 365 status = i40e_init_nvm(hw); 366 return status; 367 } 368 369 /** 370 * i40e_aq_mac_address_read - Retrieve the MAC addresses 371 * @hw: pointer to the hw struct 372 * @flags: a return indicator of what addresses were added to the addr store 373 * @addrs: the requestor's mac addr store 374 * @cmd_details: pointer to command details structure or NULL 375 **/ 376 static int 377 i40e_aq_mac_address_read(struct i40e_hw *hw, 378 u16 *flags, 379 struct i40e_aqc_mac_address_read_data *addrs, 380 struct i40e_asq_cmd_details *cmd_details) 381 { 382 struct i40e_aqc_mac_address_read *cmd_data; 383 struct libie_aq_desc desc; 384 int status; 385 386 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 387 cmd_data = libie_aq_raw(&desc); 388 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF); 389 390 status = i40e_asq_send_command(hw, &desc, addrs, 391 sizeof(*addrs), cmd_details); 392 *flags = le16_to_cpu(cmd_data->command_flags); 393 394 return status; 395 } 396 397 /** 398 * i40e_aq_mac_address_write - Change the MAC addresses 399 * @hw: pointer to the hw struct 400 * @flags: indicates which MAC to be written 401 * @mac_addr: address to write 402 * @cmd_details: pointer to command details structure or NULL 403 **/ 404 int i40e_aq_mac_address_write(struct i40e_hw *hw, 405 u16 flags, u8 *mac_addr, 406 struct i40e_asq_cmd_details *cmd_details) 407 { 408 struct i40e_aqc_mac_address_write *cmd_data; 409 struct libie_aq_desc desc; 410 int status; 411 412 i40e_fill_default_direct_cmd_desc(&desc, 413 i40e_aqc_opc_mac_address_write); 414 cmd_data = libie_aq_raw(&desc); 415 cmd_data->command_flags = cpu_to_le16(flags); 416 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 417 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 418 ((u32)mac_addr[3] << 16) | 419 ((u32)mac_addr[4] << 8) | 420 mac_addr[5]); 421 422 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 423 424 return status; 425 } 426 427 /** 428 * i40e_get_mac_addr - get MAC address 429 * @hw: pointer to the HW structure 430 * @mac_addr: pointer to MAC address 431 * 432 * Reads the adapter's MAC address from register 433 **/ 434 int i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 435 { 436 struct i40e_aqc_mac_address_read_data addrs; 437 u16 flags = 0; 438 int status; 439 440 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 441 442 if (flags & I40E_AQC_LAN_ADDR_VALID) 443 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 444 445 return status; 446 } 447 448 /** 449 * i40e_get_port_mac_addr - get Port MAC address 450 * @hw: pointer to the HW structure 451 * @mac_addr: pointer to Port MAC address 452 * 453 * Reads the adapter's Port MAC address 454 **/ 455 int i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 456 { 457 struct i40e_aqc_mac_address_read_data addrs; 458 u16 flags = 0; 459 int status; 460 461 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 462 if (status) 463 return status; 464 465 if (flags & I40E_AQC_PORT_ADDR_VALID) 466 ether_addr_copy(mac_addr, addrs.port_mac); 467 else 468 status = -EINVAL; 469 470 return status; 471 } 472 473 /** 474 * i40e_pre_tx_queue_cfg - pre tx queue configure 475 * @hw: pointer to the HW structure 476 * @queue: target PF queue index 477 * @enable: state change request 478 * 479 * Handles hw requirement to indicate intention to enable 480 * or disable target queue. 481 **/ 482 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 483 { 484 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 485 u32 reg_block = 0; 486 u32 reg_val; 487 488 if (abs_queue_idx >= 128) { 489 reg_block = abs_queue_idx / 128; 490 abs_queue_idx %= 128; 491 } 492 493 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 494 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 495 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 496 497 if (enable) 498 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 499 else 500 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 501 502 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 503 } 504 505 /** 506 * i40e_get_pba_string - Reads part number string from EEPROM 507 * @hw: pointer to hardware structure 508 * 509 * Reads the part number string from the EEPROM and stores it 510 * into newly allocated buffer and saves resulting pointer 511 * to i40e_hw->pba_id field. 512 **/ 513 void i40e_get_pba_string(struct i40e_hw *hw) 514 { 515 #define I40E_NVM_PBA_FLAGS_BLK_PRESENT 0xFAFA 516 u16 pba_word = 0; 517 u16 pba_size = 0; 518 u16 pba_ptr = 0; 519 int status; 520 char *ptr; 521 u16 i; 522 523 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 524 if (status) { 525 hw_dbg(hw, "Failed to read PBA flags.\n"); 526 return; 527 } 528 if (pba_word != I40E_NVM_PBA_FLAGS_BLK_PRESENT) { 529 hw_dbg(hw, "PBA block is not present.\n"); 530 return; 531 } 532 533 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 534 if (status) { 535 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 536 return; 537 } 538 539 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 540 if (status) { 541 hw_dbg(hw, "Failed to read PBA Block size.\n"); 542 return; 543 } 544 545 /* Subtract one to get PBA word count (PBA Size word is included in 546 * total size) and advance pointer to first PBA word. 547 */ 548 pba_size--; 549 pba_ptr++; 550 if (!pba_size) { 551 hw_dbg(hw, "PBA ID is empty.\n"); 552 return; 553 } 554 555 ptr = devm_kzalloc(i40e_hw_to_dev(hw), pba_size * 2 + 1, GFP_KERNEL); 556 if (!ptr) 557 return; 558 hw->pba_id = ptr; 559 560 for (i = 0; i < pba_size; i++) { 561 status = i40e_read_nvm_word(hw, pba_ptr + i, &pba_word); 562 if (status) { 563 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 564 devm_kfree(i40e_hw_to_dev(hw), hw->pba_id); 565 hw->pba_id = NULL; 566 return; 567 } 568 569 *ptr++ = (pba_word >> 8) & 0xFF; 570 *ptr++ = pba_word & 0xFF; 571 } 572 } 573 574 /** 575 * i40e_get_media_type - Gets media type 576 * @hw: pointer to the hardware structure 577 **/ 578 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 579 { 580 enum i40e_media_type media; 581 582 switch (hw->phy.link_info.phy_type) { 583 case I40E_PHY_TYPE_10GBASE_SR: 584 case I40E_PHY_TYPE_10GBASE_LR: 585 case I40E_PHY_TYPE_1000BASE_SX: 586 case I40E_PHY_TYPE_1000BASE_LX: 587 case I40E_PHY_TYPE_40GBASE_SR4: 588 case I40E_PHY_TYPE_40GBASE_LR4: 589 case I40E_PHY_TYPE_25GBASE_LR: 590 case I40E_PHY_TYPE_25GBASE_SR: 591 media = I40E_MEDIA_TYPE_FIBER; 592 break; 593 case I40E_PHY_TYPE_100BASE_TX: 594 case I40E_PHY_TYPE_1000BASE_T: 595 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS: 596 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS: 597 case I40E_PHY_TYPE_10GBASE_T: 598 media = I40E_MEDIA_TYPE_BASET; 599 break; 600 case I40E_PHY_TYPE_10GBASE_CR1_CU: 601 case I40E_PHY_TYPE_40GBASE_CR4_CU: 602 case I40E_PHY_TYPE_10GBASE_CR1: 603 case I40E_PHY_TYPE_40GBASE_CR4: 604 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 605 case I40E_PHY_TYPE_40GBASE_AOC: 606 case I40E_PHY_TYPE_10GBASE_AOC: 607 case I40E_PHY_TYPE_25GBASE_CR: 608 case I40E_PHY_TYPE_25GBASE_AOC: 609 case I40E_PHY_TYPE_25GBASE_ACC: 610 media = I40E_MEDIA_TYPE_DA; 611 break; 612 case I40E_PHY_TYPE_1000BASE_KX: 613 case I40E_PHY_TYPE_10GBASE_KX4: 614 case I40E_PHY_TYPE_10GBASE_KR: 615 case I40E_PHY_TYPE_40GBASE_KR4: 616 case I40E_PHY_TYPE_20GBASE_KR2: 617 case I40E_PHY_TYPE_25GBASE_KR: 618 media = I40E_MEDIA_TYPE_BACKPLANE; 619 break; 620 case I40E_PHY_TYPE_SGMII: 621 case I40E_PHY_TYPE_XAUI: 622 case I40E_PHY_TYPE_XFI: 623 case I40E_PHY_TYPE_XLAUI: 624 case I40E_PHY_TYPE_XLPPI: 625 default: 626 media = I40E_MEDIA_TYPE_UNKNOWN; 627 break; 628 } 629 630 return media; 631 } 632 633 /** 634 * i40e_poll_globr - Poll for Global Reset completion 635 * @hw: pointer to the hardware structure 636 * @retry_limit: how many times to retry before failure 637 **/ 638 static int i40e_poll_globr(struct i40e_hw *hw, 639 u32 retry_limit) 640 { 641 u32 cnt, reg = 0; 642 643 for (cnt = 0; cnt < retry_limit; cnt++) { 644 reg = rd32(hw, I40E_GLGEN_RSTAT); 645 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 646 return 0; 647 msleep(100); 648 } 649 650 hw_dbg(hw, "Global reset failed.\n"); 651 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg); 652 653 return -EIO; 654 } 655 656 #define I40E_PF_RESET_WAIT_COUNT_A0 200 657 #define I40E_PF_RESET_WAIT_COUNT 200 658 /** 659 * i40e_pf_reset - Reset the PF 660 * @hw: pointer to the hardware structure 661 * 662 * Assuming someone else has triggered a global reset, 663 * assure the global reset is complete and then reset the PF 664 **/ 665 int i40e_pf_reset(struct i40e_hw *hw) 666 { 667 u32 cnt = 0; 668 u32 cnt1 = 0; 669 u32 reg = 0; 670 u32 grst_del; 671 672 /* Poll for Global Reset steady state in case of recent GRST. 673 * The grst delay value is in 100ms units, and we'll wait a 674 * couple counts longer to be sure we don't just miss the end. 675 */ 676 grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK, 677 rd32(hw, I40E_GLGEN_RSTCTL)); 678 679 /* It can take upto 15 secs for GRST steady state. 680 * Bump it to 16 secs max to be safe. 681 */ 682 grst_del = grst_del * 20; 683 684 for (cnt = 0; cnt < grst_del; cnt++) { 685 reg = rd32(hw, I40E_GLGEN_RSTAT); 686 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 687 break; 688 msleep(100); 689 } 690 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 691 hw_dbg(hw, "Global reset polling failed to complete.\n"); 692 return -EIO; 693 } 694 695 /* Now Wait for the FW to be ready */ 696 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 697 reg = rd32(hw, I40E_GLNVM_ULD); 698 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 699 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 700 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 701 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 702 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 703 break; 704 } 705 usleep_range(10000, 20000); 706 } 707 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 708 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 709 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 710 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 711 return -EIO; 712 } 713 714 /* If there was a Global Reset in progress when we got here, 715 * we don't need to do the PF Reset 716 */ 717 if (!cnt) { 718 u32 reg2 = 0; 719 if (hw->revision_id == 0) 720 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 721 else 722 cnt = I40E_PF_RESET_WAIT_COUNT; 723 reg = rd32(hw, I40E_PFGEN_CTRL); 724 wr32(hw, I40E_PFGEN_CTRL, 725 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 726 for (; cnt; cnt--) { 727 reg = rd32(hw, I40E_PFGEN_CTRL); 728 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 729 break; 730 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 731 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 732 break; 733 usleep_range(1000, 2000); 734 } 735 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 736 if (i40e_poll_globr(hw, grst_del)) 737 return -EIO; 738 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 739 hw_dbg(hw, "PF reset polling failed to complete.\n"); 740 return -EIO; 741 } 742 } 743 744 i40e_clear_pxe_mode(hw); 745 746 return 0; 747 } 748 749 /** 750 * i40e_clear_hw - clear out any left over hw state 751 * @hw: pointer to the hw struct 752 * 753 * Clear queues and interrupts, typically called at init time, 754 * but after the capabilities have been found so we know how many 755 * queues and msix vectors have been allocated. 756 **/ 757 void i40e_clear_hw(struct i40e_hw *hw) 758 { 759 u32 num_queues, base_queue; 760 s32 num_pf_int; 761 s32 num_vf_int; 762 u32 num_vfs; 763 s32 i; 764 u32 j; 765 u32 val; 766 u32 eol = 0x7ff; 767 768 /* get number of interrupts, queues, and VFs */ 769 val = rd32(hw, I40E_GLPCI_CNF2); 770 num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val); 771 num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val); 772 773 val = rd32(hw, I40E_PFLAN_QALLOC); 774 base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val); 775 j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val); 776 if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue) 777 num_queues = (j - base_queue) + 1; 778 else 779 num_queues = 0; 780 781 val = rd32(hw, I40E_PF_VT_PFALLOC); 782 i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val); 783 j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val); 784 if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i) 785 num_vfs = (j - i) + 1; 786 else 787 num_vfs = 0; 788 789 /* stop all the interrupts */ 790 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 791 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 792 for (i = 0; i < num_pf_int - 2; i++) 793 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 794 795 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 796 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 797 wr32(hw, I40E_PFINT_LNKLST0, val); 798 for (i = 0; i < num_pf_int - 2; i++) 799 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 800 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 801 for (i = 0; i < num_vfs; i++) 802 wr32(hw, I40E_VPINT_LNKLST0(i), val); 803 for (i = 0; i < num_vf_int - 2; i++) 804 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 805 806 /* warn the HW of the coming Tx disables */ 807 for (i = 0; i < num_queues; i++) { 808 u32 abs_queue_idx = base_queue + i; 809 u32 reg_block = 0; 810 811 if (abs_queue_idx >= 128) { 812 reg_block = abs_queue_idx / 128; 813 abs_queue_idx %= 128; 814 } 815 816 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 817 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 818 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 819 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 820 821 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 822 } 823 udelay(400); 824 825 /* stop all the queues */ 826 for (i = 0; i < num_queues; i++) { 827 wr32(hw, I40E_QINT_TQCTL(i), 0); 828 wr32(hw, I40E_QTX_ENA(i), 0); 829 wr32(hw, I40E_QINT_RQCTL(i), 0); 830 wr32(hw, I40E_QRX_ENA(i), 0); 831 } 832 833 /* short wait for all queue disables to settle */ 834 udelay(50); 835 } 836 837 /** 838 * i40e_clear_pxe_mode - clear pxe operations mode 839 * @hw: pointer to the hw struct 840 * 841 * Make sure all PXE mode settings are cleared, including things 842 * like descriptor fetch/write-back mode. 843 **/ 844 void i40e_clear_pxe_mode(struct i40e_hw *hw) 845 { 846 u32 reg; 847 848 if (i40e_check_asq_alive(hw)) 849 i40e_aq_clear_pxe_mode(hw, NULL); 850 851 /* Clear single descriptor fetch/write-back mode */ 852 reg = rd32(hw, I40E_GLLAN_RCTL_0); 853 854 if (hw->revision_id == 0) { 855 /* As a work around clear PXE_MODE instead of setting it */ 856 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 857 } else { 858 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 859 } 860 } 861 862 /** 863 * i40e_led_is_mine - helper to find matching led 864 * @hw: pointer to the hw struct 865 * @idx: index into GPIO registers 866 * 867 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 868 */ 869 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 870 { 871 u32 gpio_val = 0; 872 u32 port; 873 874 if (!I40E_IS_X710TL_DEVICE(hw->device_id) && 875 !hw->func_caps.led[idx]) 876 return 0; 877 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 878 port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val); 879 880 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 881 * if it is not our port then ignore 882 */ 883 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 884 (port != hw->port)) 885 return 0; 886 887 return gpio_val; 888 } 889 890 #define I40E_FW_LED BIT(4) 891 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \ 892 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 893 894 #define I40E_LED0 22 895 896 #define I40E_PIN_FUNC_SDP 0x0 897 #define I40E_PIN_FUNC_LED 0x1 898 899 /** 900 * i40e_led_get - return current on/off mode 901 * @hw: pointer to the hw struct 902 * 903 * The value returned is the 'mode' field as defined in the 904 * GPIO register definitions: 0x0 = off, 0xf = on, and other 905 * values are variations of possible behaviors relating to 906 * blink, link, and wire. 907 **/ 908 u32 i40e_led_get(struct i40e_hw *hw) 909 { 910 u32 mode = 0; 911 int i; 912 913 /* as per the documentation GPIO 22-29 are the LED 914 * GPIO pins named LED0..LED7 915 */ 916 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 917 u32 gpio_val = i40e_led_is_mine(hw, i); 918 919 if (!gpio_val) 920 continue; 921 922 mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val); 923 break; 924 } 925 926 return mode; 927 } 928 929 /** 930 * i40e_led_set - set new on/off mode 931 * @hw: pointer to the hw struct 932 * @mode: 0=off, 0xf=on (else see manual for mode details) 933 * @blink: true if the LED should blink when on, false if steady 934 * 935 * if this function is used to turn on the blink it should 936 * be used to disable the blink when restoring the original state. 937 **/ 938 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 939 { 940 int i; 941 942 if (mode & ~I40E_LED_MODE_VALID) { 943 hw_dbg(hw, "invalid mode passed in %X\n", mode); 944 return; 945 } 946 947 /* as per the documentation GPIO 22-29 are the LED 948 * GPIO pins named LED0..LED7 949 */ 950 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 951 u32 gpio_val = i40e_led_is_mine(hw, i); 952 953 if (!gpio_val) 954 continue; 955 956 if (I40E_IS_X710TL_DEVICE(hw->device_id)) { 957 u32 pin_func = 0; 958 959 if (mode & I40E_FW_LED) 960 pin_func = I40E_PIN_FUNC_SDP; 961 else 962 pin_func = I40E_PIN_FUNC_LED; 963 964 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK; 965 gpio_val |= 966 FIELD_PREP(I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK, 967 pin_func); 968 } 969 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 970 /* this & is a bit of paranoia, but serves as a range check */ 971 gpio_val |= FIELD_PREP(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, 972 mode); 973 974 if (blink) 975 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 976 else 977 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 978 979 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 980 break; 981 } 982 } 983 984 /* Admin command wrappers */ 985 986 /** 987 * i40e_aq_get_phy_capabilities 988 * @hw: pointer to the hw struct 989 * @abilities: structure for PHY capabilities to be filled 990 * @qualified_modules: report Qualified Modules 991 * @report_init: report init capabilities (active are default) 992 * @cmd_details: pointer to command details structure or NULL 993 * 994 * Returns the various PHY abilities supported on the Port. 995 **/ 996 int 997 i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 998 bool qualified_modules, bool report_init, 999 struct i40e_aq_get_phy_abilities_resp *abilities, 1000 struct i40e_asq_cmd_details *cmd_details) 1001 { 1002 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1003 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1004 struct libie_aq_desc desc; 1005 int status; 1006 1007 if (!abilities) 1008 return -EINVAL; 1009 1010 do { 1011 i40e_fill_default_direct_cmd_desc(&desc, 1012 i40e_aqc_opc_get_phy_abilities); 1013 1014 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1015 if (abilities_size > I40E_AQ_LARGE_BUF) 1016 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 1017 1018 if (qualified_modules) 1019 desc.params.generic.param0 |= 1020 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1021 1022 if (report_init) 1023 desc.params.generic.param0 |= 1024 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1025 1026 status = i40e_asq_send_command(hw, &desc, abilities, 1027 abilities_size, cmd_details); 1028 1029 switch (hw->aq.asq_last_status) { 1030 case LIBIE_AQ_RC_EIO: 1031 status = -EIO; 1032 break; 1033 case LIBIE_AQ_RC_EAGAIN: 1034 usleep_range(1000, 2000); 1035 total_delay++; 1036 status = -EIO; 1037 break; 1038 /* also covers LIBIE_AQ_RC_OK */ 1039 default: 1040 break; 1041 } 1042 1043 } while ((hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN) && 1044 (total_delay < max_delay)); 1045 1046 if (status) 1047 return status; 1048 1049 if (report_init) { 1050 if (hw->mac.type == I40E_MAC_XL710 && 1051 i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR, 1052 I40E_MINOR_VER_GET_LINK_INFO_XL710)) { 1053 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1054 } else { 1055 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1056 hw->phy.phy_types |= 1057 ((u64)abilities->phy_type_ext << 32); 1058 } 1059 } 1060 1061 return status; 1062 } 1063 1064 /** 1065 * i40e_aq_set_phy_config 1066 * @hw: pointer to the hw struct 1067 * @config: structure with PHY configuration to be set 1068 * @cmd_details: pointer to command details structure or NULL 1069 * 1070 * Set the various PHY configuration parameters 1071 * supported on the Port.One or more of the Set PHY config parameters may be 1072 * ignored in an MFP mode as the PF may not have the privilege to set some 1073 * of the PHY Config parameters. This status will be indicated by the 1074 * command response. 1075 **/ 1076 int i40e_aq_set_phy_config(struct i40e_hw *hw, 1077 struct i40e_aq_set_phy_config *config, 1078 struct i40e_asq_cmd_details *cmd_details) 1079 { 1080 struct i40e_aq_set_phy_config *cmd; 1081 struct libie_aq_desc desc; 1082 int status; 1083 1084 if (!config) 1085 return -EINVAL; 1086 1087 i40e_fill_default_direct_cmd_desc(&desc, 1088 i40e_aqc_opc_set_phy_config); 1089 1090 cmd = libie_aq_raw(&desc); 1091 *cmd = *config; 1092 1093 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1094 1095 return status; 1096 } 1097 1098 static noinline_for_stack int 1099 i40e_set_fc_status(struct i40e_hw *hw, 1100 struct i40e_aq_get_phy_abilities_resp *abilities, 1101 bool atomic_restart) 1102 { 1103 struct i40e_aq_set_phy_config config; 1104 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1105 u8 pause_mask = 0x0; 1106 1107 switch (fc_mode) { 1108 case I40E_FC_FULL: 1109 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1110 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1111 break; 1112 case I40E_FC_RX_PAUSE: 1113 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1114 break; 1115 case I40E_FC_TX_PAUSE: 1116 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1117 break; 1118 default: 1119 break; 1120 } 1121 1122 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1123 /* clear the old pause settings */ 1124 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1125 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1126 /* set the new abilities */ 1127 config.abilities |= pause_mask; 1128 /* If the abilities have changed, then set the new config */ 1129 if (config.abilities == abilities->abilities) 1130 return 0; 1131 1132 /* Auto restart link so settings take effect */ 1133 if (atomic_restart) 1134 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1135 /* Copy over all the old settings */ 1136 config.phy_type = abilities->phy_type; 1137 config.phy_type_ext = abilities->phy_type_ext; 1138 config.link_speed = abilities->link_speed; 1139 config.eee_capability = abilities->eee_capability; 1140 config.eeer = abilities->eeer_val; 1141 config.low_power_ctrl = abilities->d3_lpan; 1142 config.fec_config = abilities->fec_cfg_curr_mod_ext_info & 1143 I40E_AQ_PHY_FEC_CONFIG_MASK; 1144 1145 return i40e_aq_set_phy_config(hw, &config, NULL); 1146 } 1147 1148 /** 1149 * i40e_set_fc 1150 * @hw: pointer to the hw struct 1151 * @aq_failures: buffer to return AdminQ failure information 1152 * @atomic_restart: whether to enable atomic link restart 1153 * 1154 * Set the requested flow control mode using set_phy_config. 1155 **/ 1156 int i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1157 bool atomic_restart) 1158 { 1159 struct i40e_aq_get_phy_abilities_resp abilities; 1160 int status; 1161 1162 *aq_failures = 0x0; 1163 1164 /* Get the current phy config */ 1165 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1166 NULL); 1167 if (status) { 1168 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1169 return status; 1170 } 1171 1172 status = i40e_set_fc_status(hw, &abilities, atomic_restart); 1173 if (status) 1174 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1175 1176 /* Update the link info */ 1177 status = i40e_update_link_info(hw); 1178 if (status) { 1179 /* Wait a little bit (on 40G cards it sometimes takes a really 1180 * long time for link to come back from the atomic reset) 1181 * and try once more 1182 */ 1183 msleep(1000); 1184 status = i40e_update_link_info(hw); 1185 } 1186 if (status) 1187 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1188 1189 return status; 1190 } 1191 1192 /** 1193 * i40e_aq_clear_pxe_mode 1194 * @hw: pointer to the hw struct 1195 * @cmd_details: pointer to command details structure or NULL 1196 * 1197 * Tell the firmware that the driver is taking over from PXE 1198 **/ 1199 int i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1200 struct i40e_asq_cmd_details *cmd_details) 1201 { 1202 struct i40e_aqc_clear_pxe *cmd; 1203 struct libie_aq_desc desc; 1204 int status; 1205 1206 i40e_fill_default_direct_cmd_desc(&desc, 1207 i40e_aqc_opc_clear_pxe_mode); 1208 1209 cmd = libie_aq_raw(&desc); 1210 cmd->rx_cnt = 0x2; 1211 1212 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1213 1214 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1215 1216 return status; 1217 } 1218 1219 /** 1220 * i40e_aq_set_link_restart_an 1221 * @hw: pointer to the hw struct 1222 * @enable_link: if true: enable link, if false: disable link 1223 * @cmd_details: pointer to command details structure or NULL 1224 * 1225 * Sets up the link and restarts the Auto-Negotiation over the link. 1226 **/ 1227 int i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1228 bool enable_link, 1229 struct i40e_asq_cmd_details *cmd_details) 1230 { 1231 struct i40e_aqc_set_link_restart_an *cmd; 1232 struct libie_aq_desc desc; 1233 int status; 1234 1235 i40e_fill_default_direct_cmd_desc(&desc, 1236 i40e_aqc_opc_set_link_restart_an); 1237 1238 cmd = libie_aq_raw(&desc); 1239 cmd->command = I40E_AQ_PHY_RESTART_AN; 1240 if (enable_link) 1241 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1242 else 1243 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1244 1245 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1246 1247 return status; 1248 } 1249 1250 /** 1251 * i40e_aq_get_link_info 1252 * @hw: pointer to the hw struct 1253 * @enable_lse: enable/disable LinkStatusEvent reporting 1254 * @link: pointer to link status structure - optional 1255 * @cmd_details: pointer to command details structure or NULL 1256 * 1257 * Returns the link status of the adapter. 1258 **/ 1259 int i40e_aq_get_link_info(struct i40e_hw *hw, 1260 bool enable_lse, struct i40e_link_status *link, 1261 struct i40e_asq_cmd_details *cmd_details) 1262 { 1263 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1264 struct i40e_aqc_get_link_status *resp; 1265 struct libie_aq_desc desc; 1266 bool tx_pause, rx_pause; 1267 u16 command_flags; 1268 int status; 1269 1270 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1271 1272 resp = libie_aq_raw(&desc); 1273 if (enable_lse) 1274 command_flags = I40E_AQ_LSE_ENABLE; 1275 else 1276 command_flags = I40E_AQ_LSE_DISABLE; 1277 resp->command_flags = cpu_to_le16(command_flags); 1278 1279 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1280 1281 if (status) 1282 goto aq_get_link_info_exit; 1283 1284 /* save off old link status information */ 1285 hw->phy.link_info_old = *hw_link_info; 1286 1287 /* update link status */ 1288 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1289 hw->phy.media_type = i40e_get_media_type(hw); 1290 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1291 hw_link_info->link_info = resp->link_info; 1292 hw_link_info->an_info = resp->an_info; 1293 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1294 I40E_AQ_CONFIG_FEC_RS_ENA); 1295 hw_link_info->ext_info = resp->ext_info; 1296 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1297 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1298 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1299 1300 /* update fc info */ 1301 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1302 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1303 if (tx_pause & rx_pause) 1304 hw->fc.current_mode = I40E_FC_FULL; 1305 else if (tx_pause) 1306 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1307 else if (rx_pause) 1308 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1309 else 1310 hw->fc.current_mode = I40E_FC_NONE; 1311 1312 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1313 hw_link_info->crc_enable = true; 1314 else 1315 hw_link_info->crc_enable = false; 1316 1317 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1318 hw_link_info->lse_enable = true; 1319 else 1320 hw_link_info->lse_enable = false; 1321 1322 if (hw->mac.type == I40E_MAC_XL710 && i40e_is_fw_ver_lt(hw, 4, 40) && 1323 hw_link_info->phy_type == 0xE) 1324 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1325 1326 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps) && 1327 hw->mac.type != I40E_MAC_X722) { 1328 __le32 tmp; 1329 1330 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1331 hw->phy.phy_types = le32_to_cpu(tmp); 1332 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1333 } 1334 1335 /* save link status information */ 1336 if (link) 1337 *link = *hw_link_info; 1338 1339 /* flag cleared so helper functions don't call AQ again */ 1340 hw->phy.get_link_info = false; 1341 1342 aq_get_link_info_exit: 1343 return status; 1344 } 1345 1346 /** 1347 * i40e_aq_set_phy_int_mask 1348 * @hw: pointer to the hw struct 1349 * @mask: interrupt mask to be set 1350 * @cmd_details: pointer to command details structure or NULL 1351 * 1352 * Set link interrupt mask. 1353 **/ 1354 int i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1355 u16 mask, 1356 struct i40e_asq_cmd_details *cmd_details) 1357 { 1358 struct i40e_aqc_set_phy_int_mask *cmd; 1359 struct libie_aq_desc desc; 1360 int status; 1361 1362 i40e_fill_default_direct_cmd_desc(&desc, 1363 i40e_aqc_opc_set_phy_int_mask); 1364 1365 cmd = libie_aq_raw(&desc); 1366 cmd->event_mask = cpu_to_le16(mask); 1367 1368 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1369 1370 return status; 1371 } 1372 1373 /** 1374 * i40e_aq_set_mac_loopback 1375 * @hw: pointer to the HW struct 1376 * @ena_lpbk: Enable or Disable loopback 1377 * @cmd_details: pointer to command details structure or NULL 1378 * 1379 * Enable/disable loopback on a given port 1380 */ 1381 int i40e_aq_set_mac_loopback(struct i40e_hw *hw, bool ena_lpbk, 1382 struct i40e_asq_cmd_details *cmd_details) 1383 { 1384 struct i40e_aqc_set_lb_mode *cmd; 1385 struct libie_aq_desc desc; 1386 1387 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_lb_modes); 1388 cmd = libie_aq_raw(&desc); 1389 if (ena_lpbk) { 1390 if (hw->nvm.version <= I40E_LEGACY_LOOPBACK_NVM_VER) 1391 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL_LEGACY); 1392 else 1393 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL); 1394 } 1395 1396 return i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1397 } 1398 1399 /** 1400 * i40e_aq_set_phy_debug 1401 * @hw: pointer to the hw struct 1402 * @cmd_flags: debug command flags 1403 * @cmd_details: pointer to command details structure or NULL 1404 * 1405 * Reset the external PHY. 1406 **/ 1407 int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1408 struct i40e_asq_cmd_details *cmd_details) 1409 { 1410 struct i40e_aqc_set_phy_debug *cmd; 1411 struct libie_aq_desc desc; 1412 int status; 1413 1414 i40e_fill_default_direct_cmd_desc(&desc, 1415 i40e_aqc_opc_set_phy_debug); 1416 1417 cmd = libie_aq_raw(&desc); 1418 cmd->command_flags = cmd_flags; 1419 1420 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1421 1422 return status; 1423 } 1424 1425 /** 1426 * i40e_aq_add_vsi 1427 * @hw: pointer to the hw struct 1428 * @vsi_ctx: pointer to a vsi context struct 1429 * @cmd_details: pointer to command details structure or NULL 1430 * 1431 * Add a VSI context to the hardware. 1432 **/ 1433 int i40e_aq_add_vsi(struct i40e_hw *hw, 1434 struct i40e_vsi_context *vsi_ctx, 1435 struct i40e_asq_cmd_details *cmd_details) 1436 { 1437 struct i40e_aqc_add_get_update_vsi_completion *resp; 1438 struct i40e_aqc_add_get_update_vsi *cmd; 1439 struct libie_aq_desc desc; 1440 int status; 1441 1442 i40e_fill_default_direct_cmd_desc(&desc, 1443 i40e_aqc_opc_add_vsi); 1444 1445 resp = libie_aq_raw(&desc); 1446 cmd = libie_aq_raw(&desc); 1447 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1448 cmd->connection_type = vsi_ctx->connection_type; 1449 cmd->vf_id = vsi_ctx->vf_num; 1450 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1451 1452 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 1453 1454 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1455 sizeof(vsi_ctx->info), 1456 cmd_details, true); 1457 1458 if (status) 1459 goto aq_add_vsi_exit; 1460 1461 vsi_ctx->seid = le16_to_cpu(resp->seid); 1462 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1463 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1464 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1465 1466 aq_add_vsi_exit: 1467 return status; 1468 } 1469 1470 /** 1471 * i40e_aq_set_default_vsi 1472 * @hw: pointer to the hw struct 1473 * @seid: vsi number 1474 * @cmd_details: pointer to command details structure or NULL 1475 **/ 1476 int i40e_aq_set_default_vsi(struct i40e_hw *hw, 1477 u16 seid, 1478 struct i40e_asq_cmd_details *cmd_details) 1479 { 1480 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1481 struct libie_aq_desc desc; 1482 int status; 1483 1484 i40e_fill_default_direct_cmd_desc(&desc, 1485 i40e_aqc_opc_set_vsi_promiscuous_modes); 1486 1487 cmd = libie_aq_raw(&desc); 1488 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1489 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1490 cmd->seid = cpu_to_le16(seid); 1491 1492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1493 1494 return status; 1495 } 1496 1497 /** 1498 * i40e_aq_clear_default_vsi 1499 * @hw: pointer to the hw struct 1500 * @seid: vsi number 1501 * @cmd_details: pointer to command details structure or NULL 1502 **/ 1503 int i40e_aq_clear_default_vsi(struct i40e_hw *hw, 1504 u16 seid, 1505 struct i40e_asq_cmd_details *cmd_details) 1506 { 1507 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1508 struct libie_aq_desc desc; 1509 int status; 1510 1511 i40e_fill_default_direct_cmd_desc(&desc, 1512 i40e_aqc_opc_set_vsi_promiscuous_modes); 1513 1514 cmd = libie_aq_raw(&desc); 1515 cmd->promiscuous_flags = cpu_to_le16(0); 1516 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1517 cmd->seid = cpu_to_le16(seid); 1518 1519 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1520 1521 return status; 1522 } 1523 1524 /** 1525 * i40e_aq_set_vsi_unicast_promiscuous 1526 * @hw: pointer to the hw struct 1527 * @seid: vsi number 1528 * @set: set unicast promiscuous enable/disable 1529 * @cmd_details: pointer to command details structure or NULL 1530 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 1531 **/ 1532 int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1533 u16 seid, bool set, 1534 struct i40e_asq_cmd_details *cmd_details, 1535 bool rx_only_promisc) 1536 { 1537 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1538 struct libie_aq_desc desc; 1539 u16 flags = 0; 1540 int status; 1541 1542 i40e_fill_default_direct_cmd_desc(&desc, 1543 i40e_aqc_opc_set_vsi_promiscuous_modes); 1544 1545 cmd = libie_aq_raw(&desc); 1546 if (set) { 1547 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1548 if (rx_only_promisc && i40e_is_aq_api_ver_ge(hw, 1, 5)) 1549 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1550 } 1551 1552 cmd->promiscuous_flags = cpu_to_le16(flags); 1553 1554 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1555 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1556 cmd->valid_flags |= 1557 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 1558 1559 cmd->seid = cpu_to_le16(seid); 1560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1561 1562 return status; 1563 } 1564 1565 /** 1566 * i40e_aq_set_vsi_multicast_promiscuous 1567 * @hw: pointer to the hw struct 1568 * @seid: vsi number 1569 * @set: set multicast promiscuous enable/disable 1570 * @cmd_details: pointer to command details structure or NULL 1571 **/ 1572 int i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1573 u16 seid, bool set, 1574 struct i40e_asq_cmd_details *cmd_details) 1575 { 1576 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1577 struct libie_aq_desc desc; 1578 u16 flags = 0; 1579 int status; 1580 1581 i40e_fill_default_direct_cmd_desc(&desc, 1582 i40e_aqc_opc_set_vsi_promiscuous_modes); 1583 1584 cmd = libie_aq_raw(&desc); 1585 if (set) 1586 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1587 1588 cmd->promiscuous_flags = cpu_to_le16(flags); 1589 1590 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1591 1592 cmd->seid = cpu_to_le16(seid); 1593 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1594 1595 return status; 1596 } 1597 1598 /** 1599 * i40e_aq_set_vsi_mc_promisc_on_vlan 1600 * @hw: pointer to the hw struct 1601 * @seid: vsi number 1602 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1603 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 1604 * @cmd_details: pointer to command details structure or NULL 1605 **/ 1606 int i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 1607 u16 seid, bool enable, 1608 u16 vid, 1609 struct i40e_asq_cmd_details *cmd_details) 1610 { 1611 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1612 struct libie_aq_desc desc; 1613 u16 flags = 0; 1614 int status; 1615 1616 i40e_fill_default_direct_cmd_desc(&desc, 1617 i40e_aqc_opc_set_vsi_promiscuous_modes); 1618 1619 cmd = libie_aq_raw(&desc); 1620 if (enable) 1621 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1622 1623 cmd->promiscuous_flags = cpu_to_le16(flags); 1624 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1625 cmd->seid = cpu_to_le16(seid); 1626 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1627 1628 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 1629 cmd_details, true); 1630 1631 return status; 1632 } 1633 1634 /** 1635 * i40e_aq_set_vsi_uc_promisc_on_vlan 1636 * @hw: pointer to the hw struct 1637 * @seid: vsi number 1638 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1639 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 1640 * @cmd_details: pointer to command details structure or NULL 1641 **/ 1642 int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 1643 u16 seid, bool enable, 1644 u16 vid, 1645 struct i40e_asq_cmd_details *cmd_details) 1646 { 1647 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1648 struct libie_aq_desc desc; 1649 u16 flags = 0; 1650 int status; 1651 1652 i40e_fill_default_direct_cmd_desc(&desc, 1653 i40e_aqc_opc_set_vsi_promiscuous_modes); 1654 1655 cmd = libie_aq_raw(&desc); 1656 if (enable) { 1657 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1658 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1659 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1660 } 1661 1662 cmd->promiscuous_flags = cpu_to_le16(flags); 1663 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1664 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1665 cmd->valid_flags |= 1666 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 1667 cmd->seid = cpu_to_le16(seid); 1668 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1669 1670 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 1671 cmd_details, true); 1672 1673 return status; 1674 } 1675 1676 /** 1677 * i40e_aq_set_vsi_bc_promisc_on_vlan 1678 * @hw: pointer to the hw struct 1679 * @seid: vsi number 1680 * @enable: set broadcast promiscuous enable/disable for a given VLAN 1681 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 1682 * @cmd_details: pointer to command details structure or NULL 1683 **/ 1684 int i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 1685 u16 seid, bool enable, u16 vid, 1686 struct i40e_asq_cmd_details *cmd_details) 1687 { 1688 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1689 struct libie_aq_desc desc; 1690 u16 flags = 0; 1691 int status; 1692 1693 i40e_fill_default_direct_cmd_desc(&desc, 1694 i40e_aqc_opc_set_vsi_promiscuous_modes); 1695 1696 if (enable) 1697 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 1698 1699 cmd = libie_aq_raw(&desc); 1700 cmd->promiscuous_flags = cpu_to_le16(flags); 1701 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1702 cmd->seid = cpu_to_le16(seid); 1703 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1704 1705 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1706 1707 return status; 1708 } 1709 1710 /** 1711 * i40e_aq_set_vsi_broadcast 1712 * @hw: pointer to the hw struct 1713 * @seid: vsi number 1714 * @set_filter: true to set filter, false to clear filter 1715 * @cmd_details: pointer to command details structure or NULL 1716 * 1717 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1718 **/ 1719 int i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1720 u16 seid, bool set_filter, 1721 struct i40e_asq_cmd_details *cmd_details) 1722 { 1723 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1724 struct libie_aq_desc desc; 1725 int status; 1726 1727 i40e_fill_default_direct_cmd_desc(&desc, 1728 i40e_aqc_opc_set_vsi_promiscuous_modes); 1729 1730 cmd = libie_aq_raw(&desc); 1731 if (set_filter) 1732 cmd->promiscuous_flags 1733 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1734 else 1735 cmd->promiscuous_flags 1736 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1737 1738 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1739 cmd->seid = cpu_to_le16(seid); 1740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1741 1742 return status; 1743 } 1744 1745 /** 1746 * i40e_aq_get_vsi_params - get VSI configuration info 1747 * @hw: pointer to the hw struct 1748 * @vsi_ctx: pointer to a vsi context struct 1749 * @cmd_details: pointer to command details structure or NULL 1750 **/ 1751 int i40e_aq_get_vsi_params(struct i40e_hw *hw, 1752 struct i40e_vsi_context *vsi_ctx, 1753 struct i40e_asq_cmd_details *cmd_details) 1754 { 1755 struct i40e_aqc_add_get_update_vsi_completion *resp; 1756 struct i40e_aqc_add_get_update_vsi *cmd; 1757 struct libie_aq_desc desc; 1758 int status; 1759 1760 i40e_fill_default_direct_cmd_desc(&desc, 1761 i40e_aqc_opc_get_vsi_parameters); 1762 1763 resp = libie_aq_raw(&desc); 1764 cmd = libie_aq_raw(&desc); 1765 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1766 1767 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1768 1769 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1770 sizeof(vsi_ctx->info), NULL); 1771 1772 if (status) 1773 goto aq_get_vsi_params_exit; 1774 1775 vsi_ctx->seid = le16_to_cpu(resp->seid); 1776 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1777 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1778 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1779 1780 aq_get_vsi_params_exit: 1781 return status; 1782 } 1783 1784 /** 1785 * i40e_aq_update_vsi_params 1786 * @hw: pointer to the hw struct 1787 * @vsi_ctx: pointer to a vsi context struct 1788 * @cmd_details: pointer to command details structure or NULL 1789 * 1790 * Update a VSI context. 1791 **/ 1792 int i40e_aq_update_vsi_params(struct i40e_hw *hw, 1793 struct i40e_vsi_context *vsi_ctx, 1794 struct i40e_asq_cmd_details *cmd_details) 1795 { 1796 struct i40e_aqc_add_get_update_vsi_completion *resp; 1797 struct i40e_aqc_add_get_update_vsi *cmd; 1798 struct libie_aq_desc desc; 1799 int status; 1800 1801 i40e_fill_default_direct_cmd_desc(&desc, 1802 i40e_aqc_opc_update_vsi_parameters); 1803 resp = libie_aq_raw(&desc); 1804 cmd = libie_aq_raw(&desc); 1805 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1806 1807 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 1808 1809 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1810 sizeof(vsi_ctx->info), 1811 cmd_details, true); 1812 1813 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1814 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1815 1816 return status; 1817 } 1818 1819 /** 1820 * i40e_aq_get_switch_config 1821 * @hw: pointer to the hardware structure 1822 * @buf: pointer to the result buffer 1823 * @buf_size: length of input buffer 1824 * @start_seid: seid to start for the report, 0 == beginning 1825 * @cmd_details: pointer to command details structure or NULL 1826 * 1827 * Fill the buf with switch configuration returned from AdminQ command 1828 **/ 1829 int i40e_aq_get_switch_config(struct i40e_hw *hw, 1830 struct i40e_aqc_get_switch_config_resp *buf, 1831 u16 buf_size, u16 *start_seid, 1832 struct i40e_asq_cmd_details *cmd_details) 1833 { 1834 struct i40e_aqc_switch_seid *scfg; 1835 struct libie_aq_desc desc; 1836 int status; 1837 1838 i40e_fill_default_direct_cmd_desc(&desc, 1839 i40e_aqc_opc_get_switch_config); 1840 scfg = libie_aq_raw(&desc); 1841 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1842 if (buf_size > I40E_AQ_LARGE_BUF) 1843 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 1844 scfg->seid = cpu_to_le16(*start_seid); 1845 1846 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1847 *start_seid = le16_to_cpu(scfg->seid); 1848 1849 return status; 1850 } 1851 1852 /** 1853 * i40e_aq_set_switch_config 1854 * @hw: pointer to the hardware structure 1855 * @flags: bit flag values to set 1856 * @mode: cloud filter mode 1857 * @valid_flags: which bit flags to set 1858 * @mode: cloud filter mode 1859 * @cmd_details: pointer to command details structure or NULL 1860 * 1861 * Set switch configuration bits 1862 **/ 1863 int i40e_aq_set_switch_config(struct i40e_hw *hw, 1864 u16 flags, 1865 u16 valid_flags, u8 mode, 1866 struct i40e_asq_cmd_details *cmd_details) 1867 { 1868 struct i40e_aqc_set_switch_config *scfg; 1869 struct libie_aq_desc desc; 1870 int status; 1871 1872 i40e_fill_default_direct_cmd_desc(&desc, 1873 i40e_aqc_opc_set_switch_config); 1874 scfg = libie_aq_raw(&desc); 1875 scfg->flags = cpu_to_le16(flags); 1876 scfg->valid_flags = cpu_to_le16(valid_flags); 1877 scfg->mode = mode; 1878 if (test_bit(I40E_HW_CAP_802_1AD, hw->caps)) { 1879 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 1880 scfg->first_tag = cpu_to_le16(hw->first_tag); 1881 scfg->second_tag = cpu_to_le16(hw->second_tag); 1882 } 1883 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1884 1885 return status; 1886 } 1887 1888 /** 1889 * i40e_aq_get_firmware_version 1890 * @hw: pointer to the hw struct 1891 * @fw_major_version: firmware major version 1892 * @fw_minor_version: firmware minor version 1893 * @fw_build: firmware build number 1894 * @api_major_version: major queue version 1895 * @api_minor_version: minor queue version 1896 * @cmd_details: pointer to command details structure or NULL 1897 * 1898 * Get the firmware version from the admin queue commands 1899 **/ 1900 int i40e_aq_get_firmware_version(struct i40e_hw *hw, 1901 u16 *fw_major_version, u16 *fw_minor_version, 1902 u32 *fw_build, 1903 u16 *api_major_version, u16 *api_minor_version, 1904 struct i40e_asq_cmd_details *cmd_details) 1905 { 1906 struct i40e_aqc_get_version *resp; 1907 struct libie_aq_desc desc; 1908 int status; 1909 1910 resp = libie_aq_raw(&desc); 1911 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1912 1913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1914 1915 if (!status) { 1916 if (fw_major_version) 1917 *fw_major_version = le16_to_cpu(resp->fw_major); 1918 if (fw_minor_version) 1919 *fw_minor_version = le16_to_cpu(resp->fw_minor); 1920 if (fw_build) 1921 *fw_build = le32_to_cpu(resp->fw_build); 1922 if (api_major_version) 1923 *api_major_version = le16_to_cpu(resp->api_major); 1924 if (api_minor_version) 1925 *api_minor_version = le16_to_cpu(resp->api_minor); 1926 } 1927 1928 return status; 1929 } 1930 1931 /** 1932 * i40e_aq_send_driver_version 1933 * @hw: pointer to the hw struct 1934 * @dv: driver's major, minor version 1935 * @cmd_details: pointer to command details structure or NULL 1936 * 1937 * Send the driver version to the firmware 1938 **/ 1939 int i40e_aq_send_driver_version(struct i40e_hw *hw, 1940 struct i40e_driver_version *dv, 1941 struct i40e_asq_cmd_details *cmd_details) 1942 { 1943 struct libie_aqc_driver_ver *cmd; 1944 struct libie_aq_desc desc; 1945 int status; 1946 u16 len; 1947 1948 if (dv == NULL) 1949 return -EINVAL; 1950 1951 cmd = libie_aq_raw(&desc); 1952 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 1953 1954 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD); 1955 cmd->major_ver = dv->major_version; 1956 cmd->minor_ver = dv->minor_version; 1957 cmd->build_ver = dv->build_version; 1958 cmd->subbuild_ver = dv->subbuild_version; 1959 1960 len = 0; 1961 while (len < sizeof(dv->driver_string) && 1962 (dv->driver_string[len] < 0x80) && 1963 dv->driver_string[len]) 1964 len++; 1965 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 1966 len, cmd_details); 1967 1968 return status; 1969 } 1970 1971 /** 1972 * i40e_get_link_status - get status of the HW network link 1973 * @hw: pointer to the hw struct 1974 * @link_up: pointer to bool (true/false = linkup/linkdown) 1975 * 1976 * Variable link_up true if link is up, false if link is down. 1977 * The variable link_up is invalid if returned value of status != 0 1978 * 1979 * Side effect: LinkStatusEvent reporting becomes enabled 1980 **/ 1981 int i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 1982 { 1983 int status = 0; 1984 1985 if (hw->phy.get_link_info) { 1986 status = i40e_update_link_info(hw); 1987 1988 if (status) 1989 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 1990 status); 1991 } 1992 1993 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 1994 1995 return status; 1996 } 1997 1998 /** 1999 * i40e_update_link_info - update status of the HW network link 2000 * @hw: pointer to the hw struct 2001 **/ 2002 noinline_for_stack int i40e_update_link_info(struct i40e_hw *hw) 2003 { 2004 struct i40e_aq_get_phy_abilities_resp abilities; 2005 int status = 0; 2006 2007 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2008 if (status) 2009 return status; 2010 2011 /* extra checking needed to ensure link info to user is timely */ 2012 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2013 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2014 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2015 status = i40e_aq_get_phy_capabilities(hw, false, false, 2016 &abilities, NULL); 2017 if (status) 2018 return status; 2019 2020 if (abilities.fec_cfg_curr_mod_ext_info & 2021 I40E_AQ_ENABLE_FEC_AUTO) 2022 hw->phy.link_info.req_fec_info = 2023 (I40E_AQ_REQUEST_FEC_KR | 2024 I40E_AQ_REQUEST_FEC_RS); 2025 else 2026 hw->phy.link_info.req_fec_info = 2027 abilities.fec_cfg_curr_mod_ext_info & 2028 (I40E_AQ_REQUEST_FEC_KR | 2029 I40E_AQ_REQUEST_FEC_RS); 2030 2031 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2032 sizeof(hw->phy.link_info.module_type)); 2033 } 2034 2035 return status; 2036 } 2037 2038 /** 2039 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2040 * @hw: pointer to the hw struct 2041 * @uplink_seid: the MAC or other gizmo SEID 2042 * @downlink_seid: the VSI SEID 2043 * @enabled_tc: bitmap of TCs to be enabled 2044 * @default_port: true for default port VSI, false for control port 2045 * @veb_seid: pointer to where to put the resulting VEB SEID 2046 * @enable_stats: true to turn on VEB stats 2047 * @cmd_details: pointer to command details structure or NULL 2048 * 2049 * This asks the FW to add a VEB between the uplink and downlink 2050 * elements. If the uplink SEID is 0, this will be a floating VEB. 2051 **/ 2052 int i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2053 u16 downlink_seid, u8 enabled_tc, 2054 bool default_port, u16 *veb_seid, 2055 bool enable_stats, 2056 struct i40e_asq_cmd_details *cmd_details) 2057 { 2058 struct i40e_aqc_add_veb_completion *resp; 2059 struct i40e_aqc_add_veb *cmd; 2060 struct libie_aq_desc desc; 2061 u16 veb_flags = 0; 2062 int status; 2063 2064 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2065 if (!!uplink_seid != !!downlink_seid) 2066 return -EINVAL; 2067 2068 resp = libie_aq_raw(&desc); 2069 cmd = libie_aq_raw(&desc); 2070 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2071 2072 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2073 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2074 cmd->enable_tcs = enabled_tc; 2075 if (!uplink_seid) 2076 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2077 if (default_port) 2078 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2079 else 2080 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2081 2082 /* reverse logic here: set the bitflag to disable the stats */ 2083 if (!enable_stats) 2084 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2085 2086 cmd->veb_flags = cpu_to_le16(veb_flags); 2087 2088 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2089 2090 if (!status && veb_seid) 2091 *veb_seid = le16_to_cpu(resp->veb_seid); 2092 2093 return status; 2094 } 2095 2096 /** 2097 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2098 * @hw: pointer to the hw struct 2099 * @veb_seid: the SEID of the VEB to query 2100 * @switch_id: the uplink switch id 2101 * @floating: set to true if the VEB is floating 2102 * @statistic_index: index of the stats counter block for this VEB 2103 * @vebs_used: number of VEB's used by function 2104 * @vebs_free: total VEB's not reserved by any function 2105 * @cmd_details: pointer to command details structure or NULL 2106 * 2107 * This retrieves the parameters for a particular VEB, specified by 2108 * uplink_seid, and returns them to the caller. 2109 **/ 2110 int i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2111 u16 veb_seid, u16 *switch_id, 2112 bool *floating, u16 *statistic_index, 2113 u16 *vebs_used, u16 *vebs_free, 2114 struct i40e_asq_cmd_details *cmd_details) 2115 { 2116 struct i40e_aqc_get_veb_parameters_completion *cmd_resp; 2117 struct libie_aq_desc desc; 2118 int status; 2119 2120 if (veb_seid == 0) 2121 return -EINVAL; 2122 2123 cmd_resp = libie_aq_raw(&desc); 2124 i40e_fill_default_direct_cmd_desc(&desc, 2125 i40e_aqc_opc_get_veb_parameters); 2126 cmd_resp->seid = cpu_to_le16(veb_seid); 2127 2128 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2129 if (status) 2130 goto get_veb_exit; 2131 2132 if (switch_id) 2133 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2134 if (statistic_index) 2135 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2136 if (vebs_used) 2137 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2138 if (vebs_free) 2139 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2140 if (floating) { 2141 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2142 2143 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2144 *floating = true; 2145 else 2146 *floating = false; 2147 } 2148 2149 get_veb_exit: 2150 return status; 2151 } 2152 2153 /** 2154 * i40e_prepare_add_macvlan 2155 * @mv_list: list of macvlans to be added 2156 * @desc: pointer to AQ descriptor structure 2157 * @count: length of the list 2158 * @seid: VSI for the mac address 2159 * 2160 * Internal helper function that prepares the add macvlan request 2161 * and returns the buffer size. 2162 **/ 2163 static u16 2164 i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list, 2165 struct libie_aq_desc *desc, u16 count, u16 seid) 2166 { 2167 struct i40e_aqc_macvlan *cmd = libie_aq_raw(desc); 2168 u16 buf_size; 2169 int i; 2170 2171 buf_size = count * sizeof(*mv_list); 2172 2173 /* prep the rest of the request */ 2174 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan); 2175 cmd->num_addresses = cpu_to_le16(count); 2176 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2177 cmd->seid[1] = 0; 2178 cmd->seid[2] = 0; 2179 2180 for (i = 0; i < count; i++) 2181 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2182 mv_list[i].flags |= 2183 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2184 2185 desc->flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2186 if (buf_size > I40E_AQ_LARGE_BUF) 2187 desc->flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2188 2189 return buf_size; 2190 } 2191 2192 /** 2193 * i40e_aq_add_macvlan 2194 * @hw: pointer to the hw struct 2195 * @seid: VSI for the mac address 2196 * @mv_list: list of macvlans to be added 2197 * @count: length of the list 2198 * @cmd_details: pointer to command details structure or NULL 2199 * 2200 * Add MAC/VLAN addresses to the HW filtering 2201 **/ 2202 int 2203 i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2204 struct i40e_aqc_add_macvlan_element_data *mv_list, 2205 u16 count, struct i40e_asq_cmd_details *cmd_details) 2206 { 2207 struct libie_aq_desc desc; 2208 u16 buf_size; 2209 2210 if (count == 0 || !mv_list || !hw) 2211 return -EINVAL; 2212 2213 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 2214 2215 return i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2216 cmd_details, true); 2217 } 2218 2219 /** 2220 * i40e_aq_add_macvlan_v2 2221 * @hw: pointer to the hw struct 2222 * @seid: VSI for the mac address 2223 * @mv_list: list of macvlans to be added 2224 * @count: length of the list 2225 * @cmd_details: pointer to command details structure or NULL 2226 * @aq_status: pointer to Admin Queue status return value 2227 * 2228 * Add MAC/VLAN addresses to the HW filtering. 2229 * The _v2 version returns the last Admin Queue status in aq_status 2230 * to avoid race conditions in access to hw->aq.asq_last_status. 2231 * It also calls _v2 versions of asq_send_command functions to 2232 * get the aq_status on the stack. 2233 **/ 2234 int 2235 i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid, 2236 struct i40e_aqc_add_macvlan_element_data *mv_list, 2237 u16 count, struct i40e_asq_cmd_details *cmd_details, 2238 enum libie_aq_err *aq_status) 2239 { 2240 struct libie_aq_desc desc; 2241 u16 buf_size; 2242 2243 if (count == 0 || !mv_list || !hw) 2244 return -EINVAL; 2245 2246 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 2247 2248 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2249 cmd_details, true, aq_status); 2250 } 2251 2252 /** 2253 * i40e_aq_remove_macvlan 2254 * @hw: pointer to the hw struct 2255 * @seid: VSI for the mac address 2256 * @mv_list: list of macvlans to be removed 2257 * @count: length of the list 2258 * @cmd_details: pointer to command details structure or NULL 2259 * 2260 * Remove MAC/VLAN addresses from the HW filtering 2261 **/ 2262 int 2263 i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2264 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2265 u16 count, struct i40e_asq_cmd_details *cmd_details) 2266 { 2267 struct i40e_aqc_macvlan *cmd; 2268 struct libie_aq_desc desc; 2269 u16 buf_size; 2270 int status; 2271 2272 if (count == 0 || !mv_list || !hw) 2273 return -EINVAL; 2274 2275 buf_size = count * sizeof(*mv_list); 2276 2277 /* prep the rest of the request */ 2278 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2279 cmd = libie_aq_raw(&desc); 2280 cmd->num_addresses = cpu_to_le16(count); 2281 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2282 cmd->seid[1] = 0; 2283 cmd->seid[2] = 0; 2284 2285 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2286 if (buf_size > I40E_AQ_LARGE_BUF) 2287 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2288 2289 status = i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2290 cmd_details, true); 2291 2292 return status; 2293 } 2294 2295 /** 2296 * i40e_aq_remove_macvlan_v2 2297 * @hw: pointer to the hw struct 2298 * @seid: VSI for the mac address 2299 * @mv_list: list of macvlans to be removed 2300 * @count: length of the list 2301 * @cmd_details: pointer to command details structure or NULL 2302 * @aq_status: pointer to Admin Queue status return value 2303 * 2304 * Remove MAC/VLAN addresses from the HW filtering. 2305 * The _v2 version returns the last Admin Queue status in aq_status 2306 * to avoid race conditions in access to hw->aq.asq_last_status. 2307 * It also calls _v2 versions of asq_send_command functions to 2308 * get the aq_status on the stack. 2309 **/ 2310 int 2311 i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid, 2312 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2313 u16 count, struct i40e_asq_cmd_details *cmd_details, 2314 enum libie_aq_err *aq_status) 2315 { 2316 struct i40e_aqc_macvlan *cmd; 2317 struct libie_aq_desc desc; 2318 u16 buf_size; 2319 2320 if (count == 0 || !mv_list || !hw) 2321 return -EINVAL; 2322 2323 buf_size = count * sizeof(*mv_list); 2324 2325 /* prep the rest of the request */ 2326 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2327 cmd = libie_aq_raw(&desc); 2328 cmd->num_addresses = cpu_to_le16(count); 2329 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2330 cmd->seid[1] = 0; 2331 cmd->seid[2] = 0; 2332 2333 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2334 if (buf_size > I40E_AQ_LARGE_BUF) 2335 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2336 2337 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2338 cmd_details, true, aq_status); 2339 } 2340 2341 /** 2342 * i40e_aq_send_msg_to_vf 2343 * @hw: pointer to the hardware structure 2344 * @vfid: VF id to send msg 2345 * @v_opcode: opcodes for VF-PF communication 2346 * @v_retval: return error code 2347 * @msg: pointer to the msg buffer 2348 * @msglen: msg length 2349 * @cmd_details: pointer to command details 2350 * 2351 * send msg to vf 2352 **/ 2353 int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2354 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2355 struct i40e_asq_cmd_details *cmd_details) 2356 { 2357 struct i40e_aqc_pf_vf_message *cmd; 2358 struct libie_aq_desc desc; 2359 int status; 2360 2361 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2362 cmd = libie_aq_raw(&desc); 2363 cmd->id = cpu_to_le32(vfid); 2364 desc.cookie_high = cpu_to_le32(v_opcode); 2365 desc.cookie_low = cpu_to_le32(v_retval); 2366 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_SI); 2367 if (msglen) { 2368 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | 2369 LIBIE_AQ_FLAG_RD)); 2370 if (msglen > I40E_AQ_LARGE_BUF) 2371 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2372 desc.datalen = cpu_to_le16(msglen); 2373 } 2374 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2375 2376 return status; 2377 } 2378 2379 /** 2380 * i40e_aq_debug_read_register 2381 * @hw: pointer to the hw struct 2382 * @reg_addr: register address 2383 * @reg_val: register value 2384 * @cmd_details: pointer to command details structure or NULL 2385 * 2386 * Read the register using the admin queue commands 2387 **/ 2388 int i40e_aq_debug_read_register(struct i40e_hw *hw, 2389 u32 reg_addr, u64 *reg_val, 2390 struct i40e_asq_cmd_details *cmd_details) 2391 { 2392 struct i40e_aqc_debug_reg_read_write *cmd_resp; 2393 struct libie_aq_desc desc; 2394 int status; 2395 2396 if (reg_val == NULL) 2397 return -EINVAL; 2398 2399 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2400 2401 cmd_resp = libie_aq_raw(&desc); 2402 cmd_resp->address = cpu_to_le32(reg_addr); 2403 2404 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2405 2406 if (!status) { 2407 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2408 (u64)le32_to_cpu(cmd_resp->value_low); 2409 } 2410 2411 return status; 2412 } 2413 2414 /** 2415 * i40e_aq_debug_write_register 2416 * @hw: pointer to the hw struct 2417 * @reg_addr: register address 2418 * @reg_val: register value 2419 * @cmd_details: pointer to command details structure or NULL 2420 * 2421 * Write to a register using the admin queue commands 2422 **/ 2423 int i40e_aq_debug_write_register(struct i40e_hw *hw, 2424 u32 reg_addr, u64 reg_val, 2425 struct i40e_asq_cmd_details *cmd_details) 2426 { 2427 struct i40e_aqc_debug_reg_read_write *cmd; 2428 struct libie_aq_desc desc; 2429 int status; 2430 2431 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2432 2433 cmd = libie_aq_raw(&desc); 2434 cmd->address = cpu_to_le32(reg_addr); 2435 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2436 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2437 2438 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2439 2440 return status; 2441 } 2442 2443 /** 2444 * i40e_aq_request_resource 2445 * @hw: pointer to the hw struct 2446 * @resource: resource id 2447 * @access: access type 2448 * @sdp_number: resource number 2449 * @timeout: the maximum time in ms that the driver may hold the resource 2450 * @cmd_details: pointer to command details structure or NULL 2451 * 2452 * requests common resource using the admin queue commands 2453 **/ 2454 int i40e_aq_request_resource(struct i40e_hw *hw, 2455 enum i40e_aq_resources_ids resource, 2456 enum i40e_aq_resource_access_type access, 2457 u8 sdp_number, u64 *timeout, 2458 struct i40e_asq_cmd_details *cmd_details) 2459 { 2460 struct libie_aqc_req_res *cmd_resp; 2461 struct libie_aq_desc desc; 2462 int status; 2463 2464 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2465 2466 cmd_resp = libie_aq_raw(&desc); 2467 cmd_resp->res_id = cpu_to_le16(resource); 2468 cmd_resp->access_type = cpu_to_le16(access); 2469 cmd_resp->res_number = cpu_to_le32(sdp_number); 2470 2471 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2472 /* The completion specifies the maximum time in ms that the driver 2473 * may hold the resource in the Timeout field. 2474 * If the resource is held by someone else, the command completes with 2475 * busy return value and the timeout field indicates the maximum time 2476 * the current owner of the resource has to free it. 2477 */ 2478 if (!status || hw->aq.asq_last_status == LIBIE_AQ_RC_EBUSY) 2479 *timeout = le32_to_cpu(cmd_resp->timeout); 2480 2481 return status; 2482 } 2483 2484 /** 2485 * i40e_aq_release_resource 2486 * @hw: pointer to the hw struct 2487 * @resource: resource id 2488 * @sdp_number: resource number 2489 * @cmd_details: pointer to command details structure or NULL 2490 * 2491 * release common resource using the admin queue commands 2492 **/ 2493 int i40e_aq_release_resource(struct i40e_hw *hw, 2494 enum i40e_aq_resources_ids resource, 2495 u8 sdp_number, 2496 struct i40e_asq_cmd_details *cmd_details) 2497 { 2498 struct libie_aqc_req_res *cmd; 2499 struct libie_aq_desc desc; 2500 int status; 2501 2502 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2503 2504 cmd = libie_aq_raw(&desc); 2505 cmd->res_id = cpu_to_le16(resource); 2506 cmd->res_number = cpu_to_le32(sdp_number); 2507 2508 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2509 2510 return status; 2511 } 2512 2513 /** 2514 * i40e_aq_read_nvm 2515 * @hw: pointer to the hw struct 2516 * @module_pointer: module pointer location in words from the NVM beginning 2517 * @offset: byte offset from the module beginning 2518 * @length: length of the section to be read (in bytes from the offset) 2519 * @data: command buffer (size [bytes] = length) 2520 * @last_command: tells if this is the last command in a series 2521 * @cmd_details: pointer to command details structure or NULL 2522 * 2523 * Read the NVM using the admin queue commands 2524 **/ 2525 int i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2526 u32 offset, u16 length, void *data, 2527 bool last_command, 2528 struct i40e_asq_cmd_details *cmd_details) 2529 { 2530 struct i40e_aqc_nvm_update *cmd; 2531 struct libie_aq_desc desc; 2532 int status; 2533 2534 /* In offset the highest byte must be zeroed. */ 2535 if (offset & 0xFF000000) { 2536 status = -EINVAL; 2537 goto i40e_aq_read_nvm_exit; 2538 } 2539 2540 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2541 2542 cmd = libie_aq_raw(&desc); 2543 /* If this is the last command in a series, set the proper flag. */ 2544 if (last_command) 2545 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2546 cmd->module_pointer = module_pointer; 2547 cmd->offset = cpu_to_le32(offset); 2548 cmd->length = cpu_to_le16(length); 2549 2550 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2551 if (length > I40E_AQ_LARGE_BUF) 2552 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2553 2554 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2555 2556 i40e_aq_read_nvm_exit: 2557 return status; 2558 } 2559 2560 /** 2561 * i40e_aq_erase_nvm 2562 * @hw: pointer to the hw struct 2563 * @module_pointer: module pointer location in words from the NVM beginning 2564 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2565 * @length: length of the section to be erased (expressed in 4 KB) 2566 * @last_command: tells if this is the last command in a series 2567 * @cmd_details: pointer to command details structure or NULL 2568 * 2569 * Erase the NVM sector using the admin queue commands 2570 **/ 2571 int i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2572 u32 offset, u16 length, bool last_command, 2573 struct i40e_asq_cmd_details *cmd_details) 2574 { 2575 struct i40e_aqc_nvm_update *cmd; 2576 struct libie_aq_desc desc; 2577 int status; 2578 2579 /* In offset the highest byte must be zeroed. */ 2580 if (offset & 0xFF000000) { 2581 status = -EINVAL; 2582 goto i40e_aq_erase_nvm_exit; 2583 } 2584 2585 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2586 2587 cmd = libie_aq_raw(&desc); 2588 /* If this is the last command in a series, set the proper flag. */ 2589 if (last_command) 2590 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2591 cmd->module_pointer = module_pointer; 2592 cmd->offset = cpu_to_le32(offset); 2593 cmd->length = cpu_to_le16(length); 2594 2595 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2596 2597 i40e_aq_erase_nvm_exit: 2598 return status; 2599 } 2600 2601 /** 2602 * i40e_parse_discover_capabilities 2603 * @hw: pointer to the hw struct 2604 * @buff: pointer to a buffer containing device/function capability records 2605 * @cap_count: number of capability records in the list 2606 * @list_type_opc: type of capabilities list to parse 2607 * 2608 * Parse the device/function capabilities list. 2609 **/ 2610 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2611 u32 cap_count, 2612 enum i40e_admin_queue_opc list_type_opc) 2613 { 2614 struct libie_aqc_list_caps_elem *cap; 2615 u32 valid_functions, num_functions; 2616 u32 number, logical_id, phys_id; 2617 struct i40e_hw_capabilities *p; 2618 u16 id, ocp_cfg_word0; 2619 u8 major_rev; 2620 int status; 2621 u32 i = 0; 2622 2623 cap = (struct libie_aqc_list_caps_elem *)buff; 2624 2625 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2626 p = &hw->dev_caps; 2627 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2628 p = &hw->func_caps; 2629 else 2630 return; 2631 2632 for (i = 0; i < cap_count; i++, cap++) { 2633 id = le16_to_cpu(cap->cap); 2634 number = le32_to_cpu(cap->number); 2635 logical_id = le32_to_cpu(cap->logical_id); 2636 phys_id = le32_to_cpu(cap->phys_id); 2637 major_rev = cap->major_ver; 2638 2639 switch (id) { 2640 case LIBIE_AQC_CAPS_SWITCH_MODE: 2641 p->switch_mode = number; 2642 break; 2643 case LIBIE_AQC_CAPS_MNG_MODE: 2644 p->management_mode = number; 2645 if (major_rev > 1) { 2646 p->mng_protocols_over_mctp = logical_id; 2647 i40e_debug(hw, I40E_DEBUG_INIT, 2648 "HW Capability: Protocols over MCTP = %d\n", 2649 p->mng_protocols_over_mctp); 2650 } else { 2651 p->mng_protocols_over_mctp = 0; 2652 } 2653 break; 2654 case LIBIE_AQC_CAPS_NPAR_ACTIVE: 2655 p->npar_enable = number; 2656 break; 2657 case LIBIE_AQC_CAPS_OS2BMC_CAP: 2658 p->os2bmc = number; 2659 break; 2660 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2661 p->valid_functions = number; 2662 break; 2663 case LIBIE_AQC_CAPS_SRIOV: 2664 if (number == 1) 2665 p->sr_iov_1_1 = true; 2666 break; 2667 case LIBIE_AQC_CAPS_VF: 2668 p->num_vfs = number; 2669 p->vf_base_id = logical_id; 2670 break; 2671 case LIBIE_AQC_CAPS_VMDQ: 2672 if (number == 1) 2673 p->vmdq = true; 2674 break; 2675 case LIBIE_AQC_CAPS_8021QBG: 2676 if (number == 1) 2677 p->evb_802_1_qbg = true; 2678 break; 2679 case LIBIE_AQC_CAPS_8021QBR: 2680 if (number == 1) 2681 p->evb_802_1_qbh = true; 2682 break; 2683 case LIBIE_AQC_CAPS_VSI: 2684 p->num_vsis = number; 2685 break; 2686 case LIBIE_AQC_CAPS_DCB: 2687 if (number == 1) { 2688 p->dcb = true; 2689 p->enabled_tcmap = logical_id; 2690 p->maxtc = phys_id; 2691 } 2692 break; 2693 case LIBIE_AQC_CAPS_FCOE: 2694 if (number == 1) 2695 p->fcoe = true; 2696 break; 2697 case LIBIE_AQC_CAPS_ISCSI: 2698 if (number == 1) 2699 p->iscsi = true; 2700 break; 2701 case LIBIE_AQC_CAPS_RSS: 2702 p->rss = true; 2703 p->rss_table_size = number; 2704 p->rss_table_entry_width = logical_id; 2705 break; 2706 case LIBIE_AQC_CAPS_RXQS: 2707 p->num_rx_qp = number; 2708 p->base_queue = phys_id; 2709 break; 2710 case LIBIE_AQC_CAPS_TXQS: 2711 p->num_tx_qp = number; 2712 p->base_queue = phys_id; 2713 break; 2714 case LIBIE_AQC_CAPS_MSIX: 2715 p->num_msix_vectors = number; 2716 i40e_debug(hw, I40E_DEBUG_INIT, 2717 "HW Capability: MSIX vector count = %d\n", 2718 p->num_msix_vectors); 2719 break; 2720 case LIBIE_AQC_CAPS_VF_MSIX: 2721 p->num_msix_vectors_vf = number; 2722 break; 2723 case LIBIE_AQC_CAPS_FLEX10: 2724 if (major_rev == 1) { 2725 if (number == 1) { 2726 p->flex10_enable = true; 2727 p->flex10_capable = true; 2728 } 2729 } else { 2730 /* Capability revision >= 2 */ 2731 if (number & 1) 2732 p->flex10_enable = true; 2733 if (number & 2) 2734 p->flex10_capable = true; 2735 } 2736 p->flex10_mode = logical_id; 2737 p->flex10_status = phys_id; 2738 break; 2739 case LIBIE_AQC_CAPS_CEM: 2740 if (number == 1) 2741 p->mgmt_cem = true; 2742 break; 2743 case LIBIE_AQC_CAPS_RDMA: 2744 if (number == 1) 2745 p->iwarp = true; 2746 break; 2747 case LIBIE_AQC_CAPS_LED: 2748 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2749 p->led[phys_id] = true; 2750 break; 2751 case LIBIE_AQC_CAPS_SDP: 2752 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2753 p->sdp[phys_id] = true; 2754 break; 2755 case LIBIE_AQC_CAPS_MDIO: 2756 if (number == 1) { 2757 p->mdio_port_num = phys_id; 2758 p->mdio_port_mode = logical_id; 2759 } 2760 break; 2761 case LIBIE_AQC_CAPS_1588: 2762 if (number == 1) 2763 p->ieee_1588 = true; 2764 break; 2765 case LIBIE_AQC_CAPS_FD: 2766 p->fd = true; 2767 p->fd_filters_guaranteed = number; 2768 p->fd_filters_best_effort = logical_id; 2769 break; 2770 case LIBIE_AQC_CAPS_WSR_PROT: 2771 p->wr_csr_prot = (u64)number; 2772 p->wr_csr_prot |= (u64)logical_id << 32; 2773 break; 2774 case LIBIE_AQC_CAPS_NVM_MGMT: 2775 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 2776 p->sec_rev_disabled = true; 2777 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 2778 p->update_disabled = true; 2779 break; 2780 default: 2781 break; 2782 } 2783 } 2784 2785 if (p->fcoe) 2786 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 2787 2788 /* Software override ensuring FCoE is disabled if npar or mfp 2789 * mode because it is not supported in these modes. 2790 */ 2791 if (p->npar_enable || p->flex10_enable) 2792 p->fcoe = false; 2793 2794 /* count the enabled ports (aka the "not disabled" ports) */ 2795 hw->num_ports = 0; 2796 for (i = 0; i < 4; i++) { 2797 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 2798 u64 port_cfg = 0; 2799 2800 /* use AQ read to get the physical register offset instead 2801 * of the port relative offset 2802 */ 2803 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 2804 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 2805 hw->num_ports++; 2806 } 2807 2808 /* OCP cards case: if a mezz is removed the Ethernet port is at 2809 * disabled state in PRTGEN_CNF register. Additional NVM read is 2810 * needed in order to check if we are dealing with OCP card. 2811 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 2812 * physical ports results in wrong partition id calculation and thus 2813 * not supporting WoL. 2814 */ 2815 if (hw->mac.type == I40E_MAC_X722) { 2816 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) { 2817 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 2818 2 * I40E_SR_OCP_CFG_WORD0, 2819 sizeof(ocp_cfg_word0), 2820 &ocp_cfg_word0, true, NULL); 2821 if (!status && 2822 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 2823 hw->num_ports = 4; 2824 i40e_release_nvm(hw); 2825 } 2826 } 2827 2828 valid_functions = p->valid_functions; 2829 num_functions = 0; 2830 while (valid_functions) { 2831 if (valid_functions & 1) 2832 num_functions++; 2833 valid_functions >>= 1; 2834 } 2835 2836 /* partition id is 1-based, and functions are evenly spread 2837 * across the ports as partitions 2838 */ 2839 if (hw->num_ports != 0) { 2840 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 2841 hw->num_partitions = num_functions / hw->num_ports; 2842 } 2843 2844 /* additional HW specific goodies that might 2845 * someday be HW version specific 2846 */ 2847 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 2848 } 2849 2850 /** 2851 * i40e_aq_discover_capabilities 2852 * @hw: pointer to the hw struct 2853 * @buff: a virtual buffer to hold the capabilities 2854 * @buff_size: Size of the virtual buffer 2855 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 2856 * @list_type_opc: capabilities type to discover - pass in the command opcode 2857 * @cmd_details: pointer to command details structure or NULL 2858 * 2859 * Get the device capabilities descriptions from the firmware 2860 **/ 2861 int i40e_aq_discover_capabilities(struct i40e_hw *hw, 2862 void *buff, u16 buff_size, u16 *data_size, 2863 enum i40e_admin_queue_opc list_type_opc, 2864 struct i40e_asq_cmd_details *cmd_details) 2865 { 2866 struct libie_aqc_list_caps *cmd; 2867 struct libie_aq_desc desc; 2868 int status = 0; 2869 2870 cmd = libie_aq_raw(&desc); 2871 2872 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 2873 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 2874 status = -EINVAL; 2875 goto exit; 2876 } 2877 2878 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 2879 2880 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2881 if (buff_size > I40E_AQ_LARGE_BUF) 2882 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2883 2884 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2885 *data_size = le16_to_cpu(desc.datalen); 2886 2887 if (status) 2888 goto exit; 2889 2890 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 2891 list_type_opc); 2892 2893 exit: 2894 return status; 2895 } 2896 2897 /** 2898 * i40e_aq_update_nvm 2899 * @hw: pointer to the hw struct 2900 * @module_pointer: module pointer location in words from the NVM beginning 2901 * @offset: byte offset from the module beginning 2902 * @length: length of the section to be written (in bytes from the offset) 2903 * @data: command buffer (size [bytes] = length) 2904 * @last_command: tells if this is the last command in a series 2905 * @preservation_flags: Preservation mode flags 2906 * @cmd_details: pointer to command details structure or NULL 2907 * 2908 * Update the NVM using the admin queue commands 2909 **/ 2910 int i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 2911 u32 offset, u16 length, void *data, 2912 bool last_command, u8 preservation_flags, 2913 struct i40e_asq_cmd_details *cmd_details) 2914 { 2915 struct i40e_aqc_nvm_update *cmd; 2916 struct libie_aq_desc desc; 2917 int status; 2918 2919 /* In offset the highest byte must be zeroed. */ 2920 if (offset & 0xFF000000) { 2921 status = -EINVAL; 2922 goto i40e_aq_update_nvm_exit; 2923 } 2924 2925 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 2926 2927 cmd = libie_aq_raw(&desc); 2928 /* If this is the last command in a series, set the proper flag. */ 2929 if (last_command) 2930 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2931 if (hw->mac.type == I40E_MAC_X722) { 2932 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 2933 cmd->command_flags |= 2934 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 2935 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 2936 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 2937 cmd->command_flags |= 2938 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 2939 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 2940 } 2941 cmd->module_pointer = module_pointer; 2942 cmd->offset = cpu_to_le32(offset); 2943 cmd->length = cpu_to_le16(length); 2944 2945 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2946 if (length > I40E_AQ_LARGE_BUF) 2947 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2948 2949 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2950 2951 i40e_aq_update_nvm_exit: 2952 return status; 2953 } 2954 2955 /** 2956 * i40e_aq_get_lldp_mib 2957 * @hw: pointer to the hw struct 2958 * @bridge_type: type of bridge requested 2959 * @mib_type: Local, Remote or both Local and Remote MIBs 2960 * @buff: pointer to a user supplied buffer to store the MIB block 2961 * @buff_size: size of the buffer (in bytes) 2962 * @local_len : length of the returned Local LLDP MIB 2963 * @remote_len: length of the returned Remote LLDP MIB 2964 * @cmd_details: pointer to command details structure or NULL 2965 * 2966 * Requests the complete LLDP MIB (entire packet). 2967 **/ 2968 int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 2969 u8 mib_type, void *buff, u16 buff_size, 2970 u16 *local_len, u16 *remote_len, 2971 struct i40e_asq_cmd_details *cmd_details) 2972 { 2973 struct i40e_aqc_lldp_get_mib *resp; 2974 struct i40e_aqc_lldp_get_mib *cmd; 2975 struct libie_aq_desc desc; 2976 int status; 2977 2978 if (buff_size == 0 || !buff) 2979 return -EINVAL; 2980 2981 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 2982 /* Indirect Command */ 2983 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2984 2985 resp = libie_aq_raw(&desc); 2986 cmd = libie_aq_raw(&desc); 2987 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 2988 cmd->type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type); 2989 2990 desc.datalen = cpu_to_le16(buff_size); 2991 2992 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2993 if (buff_size > I40E_AQ_LARGE_BUF) 2994 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2995 2996 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2997 if (!status) { 2998 if (local_len != NULL) 2999 *local_len = le16_to_cpu(resp->local_len); 3000 if (remote_len != NULL) 3001 *remote_len = le16_to_cpu(resp->remote_len); 3002 } 3003 3004 return status; 3005 } 3006 3007 /** 3008 * i40e_aq_set_lldp_mib - Set the LLDP MIB 3009 * @hw: pointer to the hw struct 3010 * @mib_type: Local, Remote or both Local and Remote MIBs 3011 * @buff: pointer to a user supplied buffer to store the MIB block 3012 * @buff_size: size of the buffer (in bytes) 3013 * @cmd_details: pointer to command details structure or NULL 3014 * 3015 * Set the LLDP MIB. 3016 **/ 3017 int 3018 i40e_aq_set_lldp_mib(struct i40e_hw *hw, 3019 u8 mib_type, void *buff, u16 buff_size, 3020 struct i40e_asq_cmd_details *cmd_details) 3021 { 3022 struct i40e_aqc_lldp_set_local_mib *cmd; 3023 struct libie_aq_desc desc; 3024 int status; 3025 3026 cmd = libie_aq_raw(&desc); 3027 if (buff_size == 0 || !buff) 3028 return -EINVAL; 3029 3030 i40e_fill_default_direct_cmd_desc(&desc, 3031 i40e_aqc_opc_lldp_set_local_mib); 3032 /* Indirect Command */ 3033 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 3034 if (buff_size > I40E_AQ_LARGE_BUF) 3035 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3036 desc.datalen = cpu_to_le16(buff_size); 3037 3038 cmd->type = mib_type; 3039 cmd->length = cpu_to_le16(buff_size); 3040 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff)); 3041 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff)); 3042 3043 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3044 return status; 3045 } 3046 3047 /** 3048 * i40e_aq_cfg_lldp_mib_change_event 3049 * @hw: pointer to the hw struct 3050 * @enable_update: Enable or Disable event posting 3051 * @cmd_details: pointer to command details structure or NULL 3052 * 3053 * Enable or Disable posting of an event on ARQ when LLDP MIB 3054 * associated with the interface changes 3055 **/ 3056 int i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3057 bool enable_update, 3058 struct i40e_asq_cmd_details *cmd_details) 3059 { 3060 struct i40e_aqc_lldp_update_mib *cmd; 3061 struct libie_aq_desc desc; 3062 int status; 3063 3064 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3065 3066 cmd = libie_aq_raw(&desc); 3067 if (!enable_update) 3068 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3069 3070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3071 3072 return status; 3073 } 3074 3075 /** 3076 * i40e_aq_stop_lldp 3077 * @hw: pointer to the hw struct 3078 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3079 * @persist: True if stop of LLDP should be persistent across power cycles 3080 * @cmd_details: pointer to command details structure or NULL 3081 * 3082 * Stop or Shutdown the embedded LLDP Agent 3083 **/ 3084 int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3085 bool persist, 3086 struct i40e_asq_cmd_details *cmd_details) 3087 { 3088 struct i40e_aqc_lldp_stop *cmd; 3089 struct libie_aq_desc desc; 3090 int status; 3091 3092 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3093 3094 cmd = libie_aq_raw(&desc); 3095 if (shutdown_agent) 3096 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3097 3098 if (persist) { 3099 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) 3100 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST; 3101 else 3102 i40e_debug(hw, I40E_DEBUG_ALL, 3103 "Persistent Stop LLDP not supported by current FW version.\n"); 3104 } 3105 3106 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3107 3108 return status; 3109 } 3110 3111 /** 3112 * i40e_aq_start_lldp 3113 * @hw: pointer to the hw struct 3114 * @persist: True if start of LLDP should be persistent across power cycles 3115 * @cmd_details: pointer to command details structure or NULL 3116 * 3117 * Start the embedded LLDP Agent on all ports. 3118 **/ 3119 int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist, 3120 struct i40e_asq_cmd_details *cmd_details) 3121 { 3122 struct i40e_aqc_lldp_start *cmd; 3123 struct libie_aq_desc desc; 3124 int status; 3125 3126 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3127 3128 cmd = libie_aq_raw(&desc); 3129 cmd->command = I40E_AQ_LLDP_AGENT_START; 3130 3131 if (persist) { 3132 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) 3133 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST; 3134 else 3135 i40e_debug(hw, I40E_DEBUG_ALL, 3136 "Persistent Start LLDP not supported by current FW version.\n"); 3137 } 3138 3139 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3140 3141 return status; 3142 } 3143 3144 /** 3145 * i40e_aq_set_dcb_parameters 3146 * @hw: pointer to the hw struct 3147 * @cmd_details: pointer to command details structure or NULL 3148 * @dcb_enable: True if DCB configuration needs to be applied 3149 * 3150 **/ 3151 int 3152 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 3153 struct i40e_asq_cmd_details *cmd_details) 3154 { 3155 struct i40e_aqc_set_dcb_parameters *cmd; 3156 struct libie_aq_desc desc; 3157 int status; 3158 3159 if (!test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps)) 3160 return -ENODEV; 3161 3162 i40e_fill_default_direct_cmd_desc(&desc, 3163 i40e_aqc_opc_set_dcb_parameters); 3164 3165 cmd = libie_aq_raw(&desc); 3166 if (dcb_enable) { 3167 cmd->valid_flags = I40E_DCB_VALID; 3168 cmd->command = I40E_AQ_DCB_SET_AGENT; 3169 } 3170 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3171 3172 return status; 3173 } 3174 3175 /** 3176 * i40e_aq_get_cee_dcb_config 3177 * @hw: pointer to the hw struct 3178 * @buff: response buffer that stores CEE operational configuration 3179 * @buff_size: size of the buffer passed 3180 * @cmd_details: pointer to command details structure or NULL 3181 * 3182 * Get CEE DCBX mode operational configuration from firmware 3183 **/ 3184 int i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3185 void *buff, u16 buff_size, 3186 struct i40e_asq_cmd_details *cmd_details) 3187 { 3188 struct libie_aq_desc desc; 3189 int status; 3190 3191 if (buff_size == 0 || !buff) 3192 return -EINVAL; 3193 3194 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3195 3196 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3197 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3198 cmd_details); 3199 3200 return status; 3201 } 3202 3203 /** 3204 * i40e_aq_add_udp_tunnel 3205 * @hw: pointer to the hw struct 3206 * @udp_port: the UDP port to add in Host byte order 3207 * @protocol_index: protocol index type 3208 * @filter_index: pointer to filter index 3209 * @cmd_details: pointer to command details structure or NULL 3210 * 3211 * Note: Firmware expects the udp_port value to be in Little Endian format, 3212 * and this function will call cpu_to_le16 to convert from Host byte order to 3213 * Little Endian order. 3214 **/ 3215 int i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3216 u16 udp_port, u8 protocol_index, 3217 u8 *filter_index, 3218 struct i40e_asq_cmd_details *cmd_details) 3219 { 3220 struct i40e_aqc_del_udp_tunnel_completion *resp; 3221 struct i40e_aqc_add_udp_tunnel *cmd; 3222 struct libie_aq_desc desc; 3223 int status; 3224 3225 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3226 3227 resp = libie_aq_raw(&desc); 3228 cmd = libie_aq_raw(&desc); 3229 cmd->udp_port = cpu_to_le16(udp_port); 3230 cmd->protocol_type = protocol_index; 3231 3232 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3233 3234 if (!status && filter_index) 3235 *filter_index = resp->index; 3236 3237 return status; 3238 } 3239 3240 /** 3241 * i40e_aq_del_udp_tunnel 3242 * @hw: pointer to the hw struct 3243 * @index: filter index 3244 * @cmd_details: pointer to command details structure or NULL 3245 **/ 3246 int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3247 struct i40e_asq_cmd_details *cmd_details) 3248 { 3249 struct i40e_aqc_remove_udp_tunnel *cmd; 3250 struct libie_aq_desc desc; 3251 int status; 3252 3253 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3254 3255 cmd = libie_aq_raw(&desc); 3256 cmd->index = index; 3257 3258 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3259 3260 return status; 3261 } 3262 3263 /** 3264 * i40e_aq_delete_element - Delete switch element 3265 * @hw: pointer to the hw struct 3266 * @seid: the SEID to delete from the switch 3267 * @cmd_details: pointer to command details structure or NULL 3268 * 3269 * This deletes a switch element from the switch. 3270 **/ 3271 int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3272 struct i40e_asq_cmd_details *cmd_details) 3273 { 3274 struct i40e_aqc_switch_seid *cmd; 3275 struct libie_aq_desc desc; 3276 int status; 3277 3278 if (seid == 0) 3279 return -EINVAL; 3280 3281 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3282 3283 cmd = libie_aq_raw(&desc); 3284 cmd->seid = cpu_to_le16(seid); 3285 3286 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 3287 cmd_details, true); 3288 3289 return status; 3290 } 3291 3292 /** 3293 * i40e_aq_dcb_updated - DCB Updated Command 3294 * @hw: pointer to the hw struct 3295 * @cmd_details: pointer to command details structure or NULL 3296 * 3297 * EMP will return when the shared RPB settings have been 3298 * recomputed and modified. The retval field in the descriptor 3299 * will be set to 0 when RPB is modified. 3300 **/ 3301 int i40e_aq_dcb_updated(struct i40e_hw *hw, 3302 struct i40e_asq_cmd_details *cmd_details) 3303 { 3304 struct libie_aq_desc desc; 3305 int status; 3306 3307 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3308 3309 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3310 3311 return status; 3312 } 3313 3314 /** 3315 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3316 * @hw: pointer to the hw struct 3317 * @seid: seid for the physical port/switching component/vsi 3318 * @buff: Indirect buffer to hold data parameters and response 3319 * @buff_size: Indirect buffer size 3320 * @opcode: Tx scheduler AQ command opcode 3321 * @cmd_details: pointer to command details structure or NULL 3322 * 3323 * Generic command handler for Tx scheduler AQ commands 3324 **/ 3325 static int i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3326 void *buff, u16 buff_size, 3327 enum i40e_admin_queue_opc opcode, 3328 struct i40e_asq_cmd_details *cmd_details) 3329 { 3330 struct i40e_aqc_tx_sched_ind *cmd; 3331 struct libie_aq_desc desc; 3332 int status; 3333 bool cmd_param_flag = false; 3334 3335 switch (opcode) { 3336 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3337 case i40e_aqc_opc_configure_vsi_tc_bw: 3338 case i40e_aqc_opc_enable_switching_comp_ets: 3339 case i40e_aqc_opc_modify_switching_comp_ets: 3340 case i40e_aqc_opc_disable_switching_comp_ets: 3341 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3342 case i40e_aqc_opc_configure_switching_comp_bw_config: 3343 cmd_param_flag = true; 3344 break; 3345 case i40e_aqc_opc_query_vsi_bw_config: 3346 case i40e_aqc_opc_query_vsi_ets_sla_config: 3347 case i40e_aqc_opc_query_switching_comp_ets_config: 3348 case i40e_aqc_opc_query_port_ets_config: 3349 case i40e_aqc_opc_query_switching_comp_bw_config: 3350 cmd_param_flag = false; 3351 break; 3352 default: 3353 return -EINVAL; 3354 } 3355 3356 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3357 3358 cmd = libie_aq_raw(&desc); 3359 /* Indirect command */ 3360 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3361 if (cmd_param_flag) 3362 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 3363 if (buff_size > I40E_AQ_LARGE_BUF) 3364 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3365 3366 desc.datalen = cpu_to_le16(buff_size); 3367 3368 cmd->vsi_seid = cpu_to_le16(seid); 3369 3370 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3371 3372 return status; 3373 } 3374 3375 /** 3376 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3377 * @hw: pointer to the hw struct 3378 * @seid: VSI seid 3379 * @credit: BW limit credits (0 = disabled) 3380 * @max_credit: Max BW limit credits 3381 * @cmd_details: pointer to command details structure or NULL 3382 **/ 3383 int i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3384 u16 seid, u16 credit, u8 max_credit, 3385 struct i40e_asq_cmd_details *cmd_details) 3386 { 3387 struct i40e_aqc_configure_vsi_bw_limit *cmd; 3388 struct libie_aq_desc desc; 3389 int status; 3390 3391 i40e_fill_default_direct_cmd_desc(&desc, 3392 i40e_aqc_opc_configure_vsi_bw_limit); 3393 3394 cmd = libie_aq_raw(&desc); 3395 cmd->vsi_seid = cpu_to_le16(seid); 3396 cmd->credit = cpu_to_le16(credit); 3397 cmd->max_credit = max_credit; 3398 3399 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3400 3401 return status; 3402 } 3403 3404 /** 3405 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3406 * @hw: pointer to the hw struct 3407 * @seid: VSI seid 3408 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3409 * @cmd_details: pointer to command details structure or NULL 3410 **/ 3411 int i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3412 u16 seid, 3413 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3414 struct i40e_asq_cmd_details *cmd_details) 3415 { 3416 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3417 i40e_aqc_opc_configure_vsi_tc_bw, 3418 cmd_details); 3419 } 3420 3421 /** 3422 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3423 * @hw: pointer to the hw struct 3424 * @seid: seid of the switching component connected to Physical Port 3425 * @ets_data: Buffer holding ETS parameters 3426 * @opcode: Tx scheduler AQ command opcode 3427 * @cmd_details: pointer to command details structure or NULL 3428 **/ 3429 int 3430 i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3431 u16 seid, 3432 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3433 enum i40e_admin_queue_opc opcode, 3434 struct i40e_asq_cmd_details *cmd_details) 3435 { 3436 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3437 sizeof(*ets_data), opcode, cmd_details); 3438 } 3439 3440 /** 3441 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3442 * @hw: pointer to the hw struct 3443 * @seid: seid of the switching component 3444 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3445 * @cmd_details: pointer to command details structure or NULL 3446 **/ 3447 int 3448 i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3449 u16 seid, 3450 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3451 struct i40e_asq_cmd_details *cmd_details) 3452 { 3453 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3454 i40e_aqc_opc_configure_switching_comp_bw_config, 3455 cmd_details); 3456 } 3457 3458 /** 3459 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3460 * @hw: pointer to the hw struct 3461 * @seid: seid of the VSI 3462 * @bw_data: Buffer to hold VSI BW configuration 3463 * @cmd_details: pointer to command details structure or NULL 3464 **/ 3465 int 3466 i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3467 u16 seid, 3468 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3469 struct i40e_asq_cmd_details *cmd_details) 3470 { 3471 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3472 i40e_aqc_opc_query_vsi_bw_config, 3473 cmd_details); 3474 } 3475 3476 /** 3477 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3478 * @hw: pointer to the hw struct 3479 * @seid: seid of the VSI 3480 * @bw_data: Buffer to hold VSI BW configuration per TC 3481 * @cmd_details: pointer to command details structure or NULL 3482 **/ 3483 int 3484 i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3485 u16 seid, 3486 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3487 struct i40e_asq_cmd_details *cmd_details) 3488 { 3489 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3490 i40e_aqc_opc_query_vsi_ets_sla_config, 3491 cmd_details); 3492 } 3493 3494 /** 3495 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3496 * @hw: pointer to the hw struct 3497 * @seid: seid of the switching component 3498 * @bw_data: Buffer to hold switching component's per TC BW config 3499 * @cmd_details: pointer to command details structure or NULL 3500 **/ 3501 int 3502 i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3503 u16 seid, 3504 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3505 struct i40e_asq_cmd_details *cmd_details) 3506 { 3507 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3508 i40e_aqc_opc_query_switching_comp_ets_config, 3509 cmd_details); 3510 } 3511 3512 /** 3513 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3514 * @hw: pointer to the hw struct 3515 * @seid: seid of the VSI or switching component connected to Physical Port 3516 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3517 * @cmd_details: pointer to command details structure or NULL 3518 **/ 3519 int 3520 i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3521 u16 seid, 3522 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3523 struct i40e_asq_cmd_details *cmd_details) 3524 { 3525 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3526 i40e_aqc_opc_query_port_ets_config, 3527 cmd_details); 3528 } 3529 3530 /** 3531 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3532 * @hw: pointer to the hw struct 3533 * @seid: seid of the switching component 3534 * @bw_data: Buffer to hold switching component's BW configuration 3535 * @cmd_details: pointer to command details structure or NULL 3536 **/ 3537 int 3538 i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3539 u16 seid, 3540 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3541 struct i40e_asq_cmd_details *cmd_details) 3542 { 3543 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3544 i40e_aqc_opc_query_switching_comp_bw_config, 3545 cmd_details); 3546 } 3547 3548 /** 3549 * i40e_validate_filter_settings 3550 * @hw: pointer to the hardware structure 3551 * @settings: Filter control settings 3552 * 3553 * Check and validate the filter control settings passed. 3554 * The function checks for the valid filter/context sizes being 3555 * passed for FCoE and PE. 3556 * 3557 * Returns 0 if the values passed are valid and within 3558 * range else returns an error. 3559 **/ 3560 static int 3561 i40e_validate_filter_settings(struct i40e_hw *hw, 3562 struct i40e_filter_control_settings *settings) 3563 { 3564 u32 fcoe_cntx_size, fcoe_filt_size; 3565 u32 fcoe_fmax; 3566 u32 val; 3567 3568 /* Validate FCoE settings passed */ 3569 switch (settings->fcoe_filt_num) { 3570 case I40E_HASH_FILTER_SIZE_1K: 3571 case I40E_HASH_FILTER_SIZE_2K: 3572 case I40E_HASH_FILTER_SIZE_4K: 3573 case I40E_HASH_FILTER_SIZE_8K: 3574 case I40E_HASH_FILTER_SIZE_16K: 3575 case I40E_HASH_FILTER_SIZE_32K: 3576 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3577 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3578 break; 3579 default: 3580 return -EINVAL; 3581 } 3582 3583 switch (settings->fcoe_cntx_num) { 3584 case I40E_DMA_CNTX_SIZE_512: 3585 case I40E_DMA_CNTX_SIZE_1K: 3586 case I40E_DMA_CNTX_SIZE_2K: 3587 case I40E_DMA_CNTX_SIZE_4K: 3588 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3589 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3590 break; 3591 default: 3592 return -EINVAL; 3593 } 3594 3595 /* Validate PE settings passed */ 3596 switch (settings->pe_filt_num) { 3597 case I40E_HASH_FILTER_SIZE_1K: 3598 case I40E_HASH_FILTER_SIZE_2K: 3599 case I40E_HASH_FILTER_SIZE_4K: 3600 case I40E_HASH_FILTER_SIZE_8K: 3601 case I40E_HASH_FILTER_SIZE_16K: 3602 case I40E_HASH_FILTER_SIZE_32K: 3603 case I40E_HASH_FILTER_SIZE_64K: 3604 case I40E_HASH_FILTER_SIZE_128K: 3605 case I40E_HASH_FILTER_SIZE_256K: 3606 case I40E_HASH_FILTER_SIZE_512K: 3607 case I40E_HASH_FILTER_SIZE_1M: 3608 break; 3609 default: 3610 return -EINVAL; 3611 } 3612 3613 switch (settings->pe_cntx_num) { 3614 case I40E_DMA_CNTX_SIZE_512: 3615 case I40E_DMA_CNTX_SIZE_1K: 3616 case I40E_DMA_CNTX_SIZE_2K: 3617 case I40E_DMA_CNTX_SIZE_4K: 3618 case I40E_DMA_CNTX_SIZE_8K: 3619 case I40E_DMA_CNTX_SIZE_16K: 3620 case I40E_DMA_CNTX_SIZE_32K: 3621 case I40E_DMA_CNTX_SIZE_64K: 3622 case I40E_DMA_CNTX_SIZE_128K: 3623 case I40E_DMA_CNTX_SIZE_256K: 3624 break; 3625 default: 3626 return -EINVAL; 3627 } 3628 3629 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3630 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3631 fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val); 3632 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3633 return -EINVAL; 3634 3635 return 0; 3636 } 3637 3638 /** 3639 * i40e_set_filter_control 3640 * @hw: pointer to the hardware structure 3641 * @settings: Filter control settings 3642 * 3643 * Set the Queue Filters for PE/FCoE and enable filters required 3644 * for a single PF. It is expected that these settings are programmed 3645 * at the driver initialization time. 3646 **/ 3647 int i40e_set_filter_control(struct i40e_hw *hw, 3648 struct i40e_filter_control_settings *settings) 3649 { 3650 u32 hash_lut_size = 0; 3651 int ret = 0; 3652 u32 val; 3653 3654 if (!settings) 3655 return -EINVAL; 3656 3657 /* Validate the input settings */ 3658 ret = i40e_validate_filter_settings(hw, settings); 3659 if (ret) 3660 return ret; 3661 3662 /* Read the PF Queue Filter control register */ 3663 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 3664 3665 /* Program required PE hash buckets for the PF */ 3666 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 3667 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEHSIZE_MASK, settings->pe_filt_num); 3668 /* Program required PE contexts for the PF */ 3669 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 3670 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEDSIZE_MASK, settings->pe_cntx_num); 3671 3672 /* Program required FCoE hash buckets for the PF */ 3673 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3674 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCHSIZE_MASK, 3675 settings->fcoe_filt_num); 3676 /* Program required FCoE DDP contexts for the PF */ 3677 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3678 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCDSIZE_MASK, 3679 settings->fcoe_cntx_num); 3680 3681 /* Program Hash LUT size for the PF */ 3682 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3683 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 3684 hash_lut_size = 1; 3685 val |= FIELD_PREP(I40E_PFQF_CTL_0_HASHLUTSIZE_MASK, hash_lut_size); 3686 3687 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 3688 if (settings->enable_fdir) 3689 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 3690 if (settings->enable_ethtype) 3691 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 3692 if (settings->enable_macvlan) 3693 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 3694 3695 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 3696 3697 return 0; 3698 } 3699 3700 /** 3701 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 3702 * @hw: pointer to the hw struct 3703 * @mac_addr: MAC address to use in the filter 3704 * @ethtype: Ethertype to use in the filter 3705 * @flags: Flags that needs to be applied to the filter 3706 * @vsi_seid: seid of the control VSI 3707 * @queue: VSI queue number to send the packet to 3708 * @is_add: Add control packet filter if True else remove 3709 * @stats: Structure to hold information on control filter counts 3710 * @cmd_details: pointer to command details structure or NULL 3711 * 3712 * This command will Add or Remove control packet filter for a control VSI. 3713 * In return it will update the total number of perfect filter count in 3714 * the stats member. 3715 **/ 3716 int i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 3717 u8 *mac_addr, u16 ethtype, u16 flags, 3718 u16 vsi_seid, u16 queue, bool is_add, 3719 struct i40e_control_filter_stats *stats, 3720 struct i40e_asq_cmd_details *cmd_details) 3721 { 3722 struct i40e_aqc_add_remove_control_packet_filter_completion *resp; 3723 struct i40e_aqc_add_remove_control_packet_filter *cmd; 3724 struct libie_aq_desc desc; 3725 int status; 3726 3727 if (vsi_seid == 0) 3728 return -EINVAL; 3729 3730 resp = libie_aq_raw(&desc); 3731 cmd = libie_aq_raw(&desc); 3732 if (is_add) { 3733 i40e_fill_default_direct_cmd_desc(&desc, 3734 i40e_aqc_opc_add_control_packet_filter); 3735 cmd->queue = cpu_to_le16(queue); 3736 } else { 3737 i40e_fill_default_direct_cmd_desc(&desc, 3738 i40e_aqc_opc_remove_control_packet_filter); 3739 } 3740 3741 if (mac_addr) 3742 ether_addr_copy(cmd->mac, mac_addr); 3743 3744 cmd->etype = cpu_to_le16(ethtype); 3745 cmd->flags = cpu_to_le16(flags); 3746 cmd->seid = cpu_to_le16(vsi_seid); 3747 3748 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3749 3750 if (!status && stats) { 3751 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 3752 stats->etype_used = le16_to_cpu(resp->etype_used); 3753 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 3754 stats->etype_free = le16_to_cpu(resp->etype_free); 3755 } 3756 3757 return status; 3758 } 3759 3760 /** 3761 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 3762 * @hw: pointer to the hw struct 3763 * @seid: VSI seid to add ethertype filter from 3764 **/ 3765 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 3766 u16 seid) 3767 { 3768 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 3769 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 3770 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 3771 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 3772 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 3773 int status; 3774 3775 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 3776 seid, 0, true, NULL, 3777 NULL); 3778 if (status) 3779 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 3780 } 3781 3782 /** 3783 * i40e_aq_alternate_read 3784 * @hw: pointer to the hardware structure 3785 * @reg_addr0: address of first dword to be read 3786 * @reg_val0: pointer for data read from 'reg_addr0' 3787 * @reg_addr1: address of second dword to be read 3788 * @reg_val1: pointer for data read from 'reg_addr1' 3789 * 3790 * Read one or two dwords from alternate structure. Fields are indicated 3791 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 3792 * is not passed then only register at 'reg_addr0' is read. 3793 * 3794 **/ 3795 static int i40e_aq_alternate_read(struct i40e_hw *hw, 3796 u32 reg_addr0, u32 *reg_val0, 3797 u32 reg_addr1, u32 *reg_val1) 3798 { 3799 struct i40e_aqc_alternate_write *cmd_resp; 3800 struct libie_aq_desc desc; 3801 int status; 3802 3803 if (!reg_val0) 3804 return -EINVAL; 3805 3806 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 3807 cmd_resp = libie_aq_raw(&desc); 3808 cmd_resp->address0 = cpu_to_le32(reg_addr0); 3809 cmd_resp->address1 = cpu_to_le32(reg_addr1); 3810 3811 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3812 3813 if (!status) { 3814 *reg_val0 = le32_to_cpu(cmd_resp->data0); 3815 3816 if (reg_val1) 3817 *reg_val1 = le32_to_cpu(cmd_resp->data1); 3818 } 3819 3820 return status; 3821 } 3822 3823 /** 3824 * i40e_aq_suspend_port_tx 3825 * @hw: pointer to the hardware structure 3826 * @seid: port seid 3827 * @cmd_details: pointer to command details structure or NULL 3828 * 3829 * Suspend port's Tx traffic 3830 **/ 3831 int i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, 3832 struct i40e_asq_cmd_details *cmd_details) 3833 { 3834 struct i40e_aqc_tx_sched_ind *cmd; 3835 struct libie_aq_desc desc; 3836 int status; 3837 3838 cmd = libie_aq_raw(&desc); 3839 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx); 3840 cmd->vsi_seid = cpu_to_le16(seid); 3841 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3842 3843 return status; 3844 } 3845 3846 /** 3847 * i40e_aq_resume_port_tx 3848 * @hw: pointer to the hardware structure 3849 * @cmd_details: pointer to command details structure or NULL 3850 * 3851 * Resume port's Tx traffic 3852 **/ 3853 int i40e_aq_resume_port_tx(struct i40e_hw *hw, 3854 struct i40e_asq_cmd_details *cmd_details) 3855 { 3856 struct libie_aq_desc desc; 3857 int status; 3858 3859 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 3860 3861 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3862 3863 return status; 3864 } 3865 3866 /** 3867 * i40e_set_pci_config_data - store PCI bus info 3868 * @hw: pointer to hardware structure 3869 * @link_status: the link status word from PCI config space 3870 * 3871 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 3872 **/ 3873 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 3874 { 3875 hw->bus.type = i40e_bus_type_pci_express; 3876 3877 switch (link_status & PCI_EXP_LNKSTA_NLW) { 3878 case PCI_EXP_LNKSTA_NLW_X1: 3879 hw->bus.width = i40e_bus_width_pcie_x1; 3880 break; 3881 case PCI_EXP_LNKSTA_NLW_X2: 3882 hw->bus.width = i40e_bus_width_pcie_x2; 3883 break; 3884 case PCI_EXP_LNKSTA_NLW_X4: 3885 hw->bus.width = i40e_bus_width_pcie_x4; 3886 break; 3887 case PCI_EXP_LNKSTA_NLW_X8: 3888 hw->bus.width = i40e_bus_width_pcie_x8; 3889 break; 3890 default: 3891 hw->bus.width = i40e_bus_width_unknown; 3892 break; 3893 } 3894 3895 switch (link_status & PCI_EXP_LNKSTA_CLS) { 3896 case PCI_EXP_LNKSTA_CLS_2_5GB: 3897 hw->bus.speed = i40e_bus_speed_2500; 3898 break; 3899 case PCI_EXP_LNKSTA_CLS_5_0GB: 3900 hw->bus.speed = i40e_bus_speed_5000; 3901 break; 3902 case PCI_EXP_LNKSTA_CLS_8_0GB: 3903 hw->bus.speed = i40e_bus_speed_8000; 3904 break; 3905 default: 3906 hw->bus.speed = i40e_bus_speed_unknown; 3907 break; 3908 } 3909 } 3910 3911 /** 3912 * i40e_aq_debug_dump 3913 * @hw: pointer to the hardware structure 3914 * @cluster_id: specific cluster to dump 3915 * @table_id: table id within cluster 3916 * @start_index: index of line in the block to read 3917 * @buff_size: dump buffer size 3918 * @buff: dump buffer 3919 * @ret_buff_size: actual buffer size returned 3920 * @ret_next_table: next block to read 3921 * @ret_next_index: next index to read 3922 * @cmd_details: pointer to command details structure or NULL 3923 * 3924 * Dump internal FW/HW data for debug purposes. 3925 * 3926 **/ 3927 int i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 3928 u8 table_id, u32 start_index, u16 buff_size, 3929 void *buff, u16 *ret_buff_size, 3930 u8 *ret_next_table, u32 *ret_next_index, 3931 struct i40e_asq_cmd_details *cmd_details) 3932 { 3933 struct i40e_aqc_debug_dump_internals *resp; 3934 struct i40e_aqc_debug_dump_internals *cmd; 3935 struct libie_aq_desc desc; 3936 int status; 3937 3938 if (buff_size == 0 || !buff) 3939 return -EINVAL; 3940 3941 i40e_fill_default_direct_cmd_desc(&desc, 3942 i40e_aqc_opc_debug_dump_internals); 3943 resp = libie_aq_raw(&desc); 3944 cmd = libie_aq_raw(&desc); 3945 /* Indirect Command */ 3946 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3947 if (buff_size > I40E_AQ_LARGE_BUF) 3948 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3949 3950 cmd->cluster_id = cluster_id; 3951 cmd->table_id = table_id; 3952 cmd->idx = cpu_to_le32(start_index); 3953 3954 desc.datalen = cpu_to_le16(buff_size); 3955 3956 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3957 if (!status) { 3958 if (ret_buff_size) 3959 *ret_buff_size = le16_to_cpu(desc.datalen); 3960 if (ret_next_table) 3961 *ret_next_table = resp->table_id; 3962 if (ret_next_index) 3963 *ret_next_index = le32_to_cpu(resp->idx); 3964 } 3965 3966 return status; 3967 } 3968 3969 /** 3970 * i40e_read_bw_from_alt_ram 3971 * @hw: pointer to the hardware structure 3972 * @max_bw: pointer for max_bw read 3973 * @min_bw: pointer for min_bw read 3974 * @min_valid: pointer for bool that is true if min_bw is a valid value 3975 * @max_valid: pointer for bool that is true if max_bw is a valid value 3976 * 3977 * Read bw from the alternate ram for the given pf 3978 **/ 3979 int i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 3980 u32 *max_bw, u32 *min_bw, 3981 bool *min_valid, bool *max_valid) 3982 { 3983 u32 max_bw_addr, min_bw_addr; 3984 int status; 3985 3986 /* Calculate the address of the min/max bw registers */ 3987 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 3988 I40E_ALT_STRUCT_MAX_BW_OFFSET + 3989 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 3990 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 3991 I40E_ALT_STRUCT_MIN_BW_OFFSET + 3992 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 3993 3994 /* Read the bandwidths from alt ram */ 3995 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 3996 min_bw_addr, min_bw); 3997 3998 if (*min_bw & I40E_ALT_BW_VALID_MASK) 3999 *min_valid = true; 4000 else 4001 *min_valid = false; 4002 4003 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4004 *max_valid = true; 4005 else 4006 *max_valid = false; 4007 4008 return status; 4009 } 4010 4011 /** 4012 * i40e_aq_configure_partition_bw 4013 * @hw: pointer to the hardware structure 4014 * @bw_data: Buffer holding valid pfs and bw limits 4015 * @cmd_details: pointer to command details 4016 * 4017 * Configure partitions guaranteed/max bw 4018 **/ 4019 int 4020 i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4021 struct i40e_aqc_configure_partition_bw_data *bw_data, 4022 struct i40e_asq_cmd_details *cmd_details) 4023 { 4024 u16 bwd_size = sizeof(*bw_data); 4025 struct libie_aq_desc desc; 4026 int status; 4027 4028 i40e_fill_default_direct_cmd_desc(&desc, 4029 i40e_aqc_opc_configure_partition_bw); 4030 4031 /* Indirect command */ 4032 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 4033 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 4034 4035 if (bwd_size > I40E_AQ_LARGE_BUF) 4036 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4037 4038 desc.datalen = cpu_to_le16(bwd_size); 4039 4040 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4041 cmd_details); 4042 4043 return status; 4044 } 4045 4046 /** 4047 * i40e_read_phy_register_clause22 4048 * @hw: pointer to the HW structure 4049 * @reg: register address in the page 4050 * @phy_addr: PHY address on MDIO interface 4051 * @value: PHY register value 4052 * 4053 * Reads specified PHY register value 4054 **/ 4055 int i40e_read_phy_register_clause22(struct i40e_hw *hw, 4056 u16 reg, u8 phy_addr, u16 *value) 4057 { 4058 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4059 int status = -EIO; 4060 u32 command = 0; 4061 u16 retry = 1000; 4062 4063 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4064 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4065 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4066 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4067 (I40E_GLGEN_MSCA_MDICMD_MASK); 4068 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4069 do { 4070 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4071 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4072 status = 0; 4073 break; 4074 } 4075 udelay(10); 4076 retry--; 4077 } while (retry); 4078 4079 if (status) { 4080 i40e_debug(hw, I40E_DEBUG_PHY, 4081 "PHY: Can't write command to external PHY.\n"); 4082 } else { 4083 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4084 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4085 } 4086 4087 return status; 4088 } 4089 4090 /** 4091 * i40e_write_phy_register_clause22 4092 * @hw: pointer to the HW structure 4093 * @reg: register address in the page 4094 * @phy_addr: PHY address on MDIO interface 4095 * @value: PHY register value 4096 * 4097 * Writes specified PHY register value 4098 **/ 4099 int i40e_write_phy_register_clause22(struct i40e_hw *hw, 4100 u16 reg, u8 phy_addr, u16 value) 4101 { 4102 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4103 int status = -EIO; 4104 u32 command = 0; 4105 u16 retry = 1000; 4106 4107 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4108 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4109 4110 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4111 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4112 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4113 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4114 (I40E_GLGEN_MSCA_MDICMD_MASK); 4115 4116 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4117 do { 4118 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4119 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4120 status = 0; 4121 break; 4122 } 4123 udelay(10); 4124 retry--; 4125 } while (retry); 4126 4127 return status; 4128 } 4129 4130 /** 4131 * i40e_read_phy_register_clause45 4132 * @hw: pointer to the HW structure 4133 * @page: registers page number 4134 * @reg: register address in the page 4135 * @phy_addr: PHY address on MDIO interface 4136 * @value: PHY register value 4137 * 4138 * Reads specified PHY register value 4139 **/ 4140 int i40e_read_phy_register_clause45(struct i40e_hw *hw, 4141 u8 page, u16 reg, u8 phy_addr, u16 *value) 4142 { 4143 u8 port_num = hw->func_caps.mdio_port_num; 4144 int status = -EIO; 4145 u32 command = 0; 4146 u16 retry = 1000; 4147 4148 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4149 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4150 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4151 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4152 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4153 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4154 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4155 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4156 do { 4157 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4158 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4159 status = 0; 4160 break; 4161 } 4162 usleep_range(10, 20); 4163 retry--; 4164 } while (retry); 4165 4166 if (status) { 4167 i40e_debug(hw, I40E_DEBUG_PHY, 4168 "PHY: Can't write command to external PHY.\n"); 4169 goto phy_read_end; 4170 } 4171 4172 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4173 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4174 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4175 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4176 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4177 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4178 status = -EIO; 4179 retry = 1000; 4180 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4181 do { 4182 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4183 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4184 status = 0; 4185 break; 4186 } 4187 usleep_range(10, 20); 4188 retry--; 4189 } while (retry); 4190 4191 if (!status) { 4192 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4193 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4194 } else { 4195 i40e_debug(hw, I40E_DEBUG_PHY, 4196 "PHY: Can't read register value from external PHY.\n"); 4197 } 4198 4199 phy_read_end: 4200 return status; 4201 } 4202 4203 /** 4204 * i40e_write_phy_register_clause45 4205 * @hw: pointer to the HW structure 4206 * @page: registers page number 4207 * @reg: register address in the page 4208 * @phy_addr: PHY address on MDIO interface 4209 * @value: PHY register value 4210 * 4211 * Writes value to specified PHY register 4212 **/ 4213 int i40e_write_phy_register_clause45(struct i40e_hw *hw, 4214 u8 page, u16 reg, u8 phy_addr, u16 value) 4215 { 4216 u8 port_num = hw->func_caps.mdio_port_num; 4217 int status = -EIO; 4218 u16 retry = 1000; 4219 u32 command = 0; 4220 4221 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4222 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4223 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4224 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4225 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4226 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4227 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4228 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4229 do { 4230 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4231 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4232 status = 0; 4233 break; 4234 } 4235 usleep_range(10, 20); 4236 retry--; 4237 } while (retry); 4238 if (status) { 4239 i40e_debug(hw, I40E_DEBUG_PHY, 4240 "PHY: Can't write command to external PHY.\n"); 4241 goto phy_write_end; 4242 } 4243 4244 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4245 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4246 4247 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4248 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4249 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4250 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4251 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4252 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4253 status = -EIO; 4254 retry = 1000; 4255 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4256 do { 4257 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4258 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4259 status = 0; 4260 break; 4261 } 4262 usleep_range(10, 20); 4263 retry--; 4264 } while (retry); 4265 4266 phy_write_end: 4267 return status; 4268 } 4269 4270 /** 4271 * i40e_get_phy_address 4272 * @hw: pointer to the HW structure 4273 * @dev_num: PHY port num that address we want 4274 * 4275 * Gets PHY address for current port 4276 **/ 4277 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4278 { 4279 u8 port_num = hw->func_caps.mdio_port_num; 4280 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4281 4282 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4283 } 4284 4285 /** 4286 * i40e_led_get_reg - read LED register 4287 * @hw: pointer to the HW structure 4288 * @led_addr: LED register address 4289 * @reg_val: read register value 4290 **/ 4291 static int i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 4292 u32 *reg_val) 4293 { 4294 u8 phy_addr = 0; 4295 u8 port_num; 4296 int status; 4297 u32 i; 4298 4299 *reg_val = 0; 4300 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4301 status = 4302 i40e_aq_get_phy_register(hw, 4303 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4304 I40E_PHY_COM_REG_PAGE, true, 4305 I40E_PHY_LED_PROV_REG_1, 4306 reg_val, NULL); 4307 } else { 4308 i = rd32(hw, I40E_PFGEN_PORTNUM); 4309 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4310 phy_addr = i40e_get_phy_address(hw, port_num); 4311 status = i40e_read_phy_register_clause45(hw, 4312 I40E_PHY_COM_REG_PAGE, 4313 led_addr, phy_addr, 4314 (u16 *)reg_val); 4315 } 4316 return status; 4317 } 4318 4319 /** 4320 * i40e_led_set_reg - write LED register 4321 * @hw: pointer to the HW structure 4322 * @led_addr: LED register address 4323 * @reg_val: register value to write 4324 **/ 4325 static int i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 4326 u32 reg_val) 4327 { 4328 u8 phy_addr = 0; 4329 u8 port_num; 4330 int status; 4331 u32 i; 4332 4333 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4334 status = 4335 i40e_aq_set_phy_register(hw, 4336 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4337 I40E_PHY_COM_REG_PAGE, true, 4338 I40E_PHY_LED_PROV_REG_1, 4339 reg_val, NULL); 4340 } else { 4341 i = rd32(hw, I40E_PFGEN_PORTNUM); 4342 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4343 phy_addr = i40e_get_phy_address(hw, port_num); 4344 status = i40e_write_phy_register_clause45(hw, 4345 I40E_PHY_COM_REG_PAGE, 4346 led_addr, phy_addr, 4347 (u16)reg_val); 4348 } 4349 4350 return status; 4351 } 4352 4353 /** 4354 * i40e_led_get_phy - return current on/off mode 4355 * @hw: pointer to the hw struct 4356 * @led_addr: address of led register to use 4357 * @val: original value of register to use 4358 * 4359 **/ 4360 int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4361 u16 *val) 4362 { 4363 u16 gpio_led_port; 4364 u8 phy_addr = 0; 4365 u32 reg_val_aq; 4366 int status = 0; 4367 u16 temp_addr; 4368 u16 reg_val; 4369 u8 port_num; 4370 u32 i; 4371 4372 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4373 status = 4374 i40e_aq_get_phy_register(hw, 4375 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4376 I40E_PHY_COM_REG_PAGE, true, 4377 I40E_PHY_LED_PROV_REG_1, 4378 ®_val_aq, NULL); 4379 if (status == 0) 4380 *val = (u16)reg_val_aq; 4381 return status; 4382 } 4383 temp_addr = I40E_PHY_LED_PROV_REG_1; 4384 i = rd32(hw, I40E_PFGEN_PORTNUM); 4385 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4386 phy_addr = i40e_get_phy_address(hw, port_num); 4387 4388 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4389 temp_addr++) { 4390 status = i40e_read_phy_register_clause45(hw, 4391 I40E_PHY_COM_REG_PAGE, 4392 temp_addr, phy_addr, 4393 ®_val); 4394 if (status) 4395 return status; 4396 *val = reg_val; 4397 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4398 *led_addr = temp_addr; 4399 break; 4400 } 4401 } 4402 return status; 4403 } 4404 4405 /** 4406 * i40e_led_set_phy 4407 * @hw: pointer to the HW structure 4408 * @on: true or false 4409 * @led_addr: address of led register to use 4410 * @mode: original val plus bit for set or ignore 4411 * 4412 * Set led's on or off when controlled by the PHY 4413 * 4414 **/ 4415 int i40e_led_set_phy(struct i40e_hw *hw, bool on, 4416 u16 led_addr, u32 mode) 4417 { 4418 u32 led_ctl = 0; 4419 u32 led_reg = 0; 4420 int status = 0; 4421 4422 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4423 if (status) 4424 return status; 4425 led_ctl = led_reg; 4426 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4427 led_reg = 0; 4428 status = i40e_led_set_reg(hw, led_addr, led_reg); 4429 if (status) 4430 return status; 4431 } 4432 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4433 if (status) 4434 goto restore_config; 4435 if (on) 4436 led_reg = I40E_PHY_LED_MANUAL_ON; 4437 else 4438 led_reg = 0; 4439 4440 status = i40e_led_set_reg(hw, led_addr, led_reg); 4441 if (status) 4442 goto restore_config; 4443 if (mode & I40E_PHY_LED_MODE_ORIG) { 4444 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 4445 status = i40e_led_set_reg(hw, led_addr, led_ctl); 4446 } 4447 return status; 4448 4449 restore_config: 4450 status = i40e_led_set_reg(hw, led_addr, led_ctl); 4451 return status; 4452 } 4453 4454 /** 4455 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 4456 * @hw: pointer to the hw struct 4457 * @reg_addr: register address 4458 * @reg_val: ptr to register value 4459 * @cmd_details: pointer to command details structure or NULL 4460 * 4461 * Use the firmware to read the Rx control register, 4462 * especially useful if the Rx unit is under heavy pressure 4463 **/ 4464 int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 4465 u32 reg_addr, u32 *reg_val, 4466 struct i40e_asq_cmd_details *cmd_details) 4467 { 4468 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp; 4469 struct libie_aq_desc desc; 4470 int status; 4471 4472 if (!reg_val) 4473 return -EINVAL; 4474 4475 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 4476 4477 cmd_resp = libie_aq_raw(&desc); 4478 cmd_resp->address = cpu_to_le32(reg_addr); 4479 4480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4481 4482 if (status == 0) 4483 *reg_val = le32_to_cpu(cmd_resp->value); 4484 4485 return status; 4486 } 4487 4488 /** 4489 * i40e_read_rx_ctl - read from an Rx control register 4490 * @hw: pointer to the hw struct 4491 * @reg_addr: register address 4492 **/ 4493 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 4494 { 4495 bool use_register = false; 4496 int status = 0; 4497 int retry = 5; 4498 u32 val = 0; 4499 4500 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722) 4501 use_register = true; 4502 4503 if (!use_register) { 4504 do_retry: 4505 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 4506 if (hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN && retry) { 4507 usleep_range(1000, 2000); 4508 retry--; 4509 goto do_retry; 4510 } 4511 } 4512 4513 /* if the AQ access failed, try the old-fashioned way */ 4514 if (status || use_register) 4515 val = rd32(hw, reg_addr); 4516 4517 return val; 4518 } 4519 4520 /** 4521 * i40e_aq_rx_ctl_write_register 4522 * @hw: pointer to the hw struct 4523 * @reg_addr: register address 4524 * @reg_val: register value 4525 * @cmd_details: pointer to command details structure or NULL 4526 * 4527 * Use the firmware to write to an Rx control register, 4528 * especially useful if the Rx unit is under heavy pressure 4529 **/ 4530 int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 4531 u32 reg_addr, u32 reg_val, 4532 struct i40e_asq_cmd_details *cmd_details) 4533 { 4534 struct i40e_aqc_rx_ctl_reg_read_write *cmd; 4535 struct libie_aq_desc desc; 4536 int status; 4537 4538 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 4539 4540 cmd = libie_aq_raw(&desc); 4541 cmd->address = cpu_to_le32(reg_addr); 4542 cmd->value = cpu_to_le32(reg_val); 4543 4544 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4545 4546 return status; 4547 } 4548 4549 /** 4550 * i40e_write_rx_ctl - write to an Rx control register 4551 * @hw: pointer to the hw struct 4552 * @reg_addr: register address 4553 * @reg_val: register value 4554 **/ 4555 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 4556 { 4557 bool use_register = false; 4558 int status = 0; 4559 int retry = 5; 4560 4561 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722) 4562 use_register = true; 4563 4564 if (!use_register) { 4565 do_retry: 4566 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 4567 reg_val, NULL); 4568 if (hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN && retry) { 4569 usleep_range(1000, 2000); 4570 retry--; 4571 goto do_retry; 4572 } 4573 } 4574 4575 /* if the AQ access failed, try the old-fashioned way */ 4576 if (status || use_register) 4577 wr32(hw, reg_addr, reg_val); 4578 } 4579 4580 /** 4581 * i40e_mdio_if_number_selection - MDIO I/F number selection 4582 * @hw: pointer to the hw struct 4583 * @set_mdio: use MDIO I/F number specified by mdio_num 4584 * @mdio_num: MDIO I/F number 4585 * @cmd: pointer to PHY Register command structure 4586 **/ 4587 static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, 4588 u8 mdio_num, 4589 struct i40e_aqc_phy_register_access *cmd) 4590 { 4591 if (!set_mdio || 4592 cmd->phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL) 4593 return; 4594 4595 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps)) { 4596 cmd->cmd_flags |= 4597 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 4598 FIELD_PREP(I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK, 4599 mdio_num); 4600 } else { 4601 i40e_debug(hw, I40E_DEBUG_PHY, "MDIO I/F number selection not supported by current FW version.\n"); 4602 } 4603 } 4604 4605 /** 4606 * i40e_aq_set_phy_register_ext 4607 * @hw: pointer to the hw struct 4608 * @phy_select: select which phy should be accessed 4609 * @dev_addr: PHY device address 4610 * @page_change: flag to indicate if phy page should be updated 4611 * @set_mdio: use MDIO I/F number specified by mdio_num 4612 * @mdio_num: MDIO I/F number 4613 * @reg_addr: PHY register address 4614 * @reg_val: new register value 4615 * @cmd_details: pointer to command details structure or NULL 4616 * 4617 * Write the external PHY register. 4618 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 4619 * may use simple wrapper i40e_aq_set_phy_register. 4620 **/ 4621 int i40e_aq_set_phy_register_ext(struct i40e_hw *hw, 4622 u8 phy_select, u8 dev_addr, bool page_change, 4623 bool set_mdio, u8 mdio_num, 4624 u32 reg_addr, u32 reg_val, 4625 struct i40e_asq_cmd_details *cmd_details) 4626 { 4627 struct i40e_aqc_phy_register_access *cmd; 4628 struct libie_aq_desc desc; 4629 int status; 4630 4631 i40e_fill_default_direct_cmd_desc(&desc, 4632 i40e_aqc_opc_set_phy_register); 4633 4634 cmd = libie_aq_raw(&desc); 4635 cmd->phy_interface = phy_select; 4636 cmd->dev_address = dev_addr; 4637 cmd->reg_address = cpu_to_le32(reg_addr); 4638 cmd->reg_value = cpu_to_le32(reg_val); 4639 4640 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 4641 4642 if (!page_change) 4643 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 4644 4645 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4646 4647 return status; 4648 } 4649 4650 /** 4651 * i40e_aq_get_phy_register_ext 4652 * @hw: pointer to the hw struct 4653 * @phy_select: select which phy should be accessed 4654 * @dev_addr: PHY device address 4655 * @page_change: flag to indicate if phy page should be updated 4656 * @set_mdio: use MDIO I/F number specified by mdio_num 4657 * @mdio_num: MDIO I/F number 4658 * @reg_addr: PHY register address 4659 * @reg_val: read register value 4660 * @cmd_details: pointer to command details structure or NULL 4661 * 4662 * Read the external PHY register. 4663 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 4664 * may use simple wrapper i40e_aq_get_phy_register. 4665 **/ 4666 int i40e_aq_get_phy_register_ext(struct i40e_hw *hw, 4667 u8 phy_select, u8 dev_addr, bool page_change, 4668 bool set_mdio, u8 mdio_num, 4669 u32 reg_addr, u32 *reg_val, 4670 struct i40e_asq_cmd_details *cmd_details) 4671 { 4672 struct i40e_aqc_phy_register_access *cmd; 4673 struct libie_aq_desc desc; 4674 int status; 4675 4676 i40e_fill_default_direct_cmd_desc(&desc, 4677 i40e_aqc_opc_get_phy_register); 4678 4679 cmd = libie_aq_raw(&desc); 4680 cmd->phy_interface = phy_select; 4681 cmd->dev_address = dev_addr; 4682 cmd->reg_address = cpu_to_le32(reg_addr); 4683 4684 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 4685 4686 if (!page_change) 4687 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 4688 4689 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4690 if (!status) 4691 *reg_val = le32_to_cpu(cmd->reg_value); 4692 4693 return status; 4694 } 4695 4696 /** 4697 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 4698 * @hw: pointer to the hw struct 4699 * @buff: command buffer (size in bytes = buff_size) 4700 * @buff_size: buffer size in bytes 4701 * @track_id: package tracking id 4702 * @error_offset: returns error offset 4703 * @error_info: returns error information 4704 * @cmd_details: pointer to command details structure or NULL 4705 **/ 4706 int i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 4707 u16 buff_size, u32 track_id, 4708 u32 *error_offset, u32 *error_info, 4709 struct i40e_asq_cmd_details *cmd_details) 4710 { 4711 struct i40e_aqc_write_personalization_profile *cmd; 4712 struct i40e_aqc_write_ddp_resp *resp; 4713 struct libie_aq_desc desc; 4714 int status; 4715 4716 i40e_fill_default_direct_cmd_desc(&desc, 4717 i40e_aqc_opc_write_personalization_profile); 4718 4719 cmd = libie_aq_raw(&desc); 4720 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD); 4721 if (buff_size > I40E_AQ_LARGE_BUF) 4722 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4723 4724 desc.datalen = cpu_to_le16(buff_size); 4725 4726 cmd->profile_track_id = cpu_to_le32(track_id); 4727 4728 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4729 if (!status) { 4730 resp = libie_aq_raw(&desc); 4731 if (error_offset) 4732 *error_offset = le32_to_cpu(resp->error_offset); 4733 if (error_info) 4734 *error_info = le32_to_cpu(resp->error_info); 4735 } 4736 4737 return status; 4738 } 4739 4740 /** 4741 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 4742 * @hw: pointer to the hw struct 4743 * @buff: command buffer (size in bytes = buff_size) 4744 * @buff_size: buffer size in bytes 4745 * @flags: AdminQ command flags 4746 * @cmd_details: pointer to command details structure or NULL 4747 **/ 4748 int i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 4749 u16 buff_size, u8 flags, 4750 struct i40e_asq_cmd_details *cmd_details) 4751 { 4752 struct i40e_aqc_get_applied_profiles *cmd; 4753 struct libie_aq_desc desc; 4754 int status; 4755 4756 i40e_fill_default_direct_cmd_desc(&desc, 4757 i40e_aqc_opc_get_personalization_profile_list); 4758 4759 cmd = libie_aq_raw(&desc); 4760 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 4761 if (buff_size > I40E_AQ_LARGE_BUF) 4762 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4763 desc.datalen = cpu_to_le16(buff_size); 4764 4765 cmd->flags = flags; 4766 4767 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4768 4769 return status; 4770 } 4771 4772 /** 4773 * i40e_find_segment_in_package 4774 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 4775 * @pkg_hdr: pointer to the package header to be searched 4776 * 4777 * This function searches a package file for a particular segment type. On 4778 * success it returns a pointer to the segment header, otherwise it will 4779 * return NULL. 4780 **/ 4781 struct i40e_generic_seg_header * 4782 i40e_find_segment_in_package(u32 segment_type, 4783 struct i40e_package_header *pkg_hdr) 4784 { 4785 struct i40e_generic_seg_header *segment; 4786 u32 i; 4787 4788 /* Search all package segments for the requested segment type */ 4789 for (i = 0; i < pkg_hdr->segment_count; i++) { 4790 segment = 4791 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 4792 pkg_hdr->segment_offset[i]); 4793 4794 if (segment->type == segment_type) 4795 return segment; 4796 } 4797 4798 return NULL; 4799 } 4800 4801 /* Get section table in profile */ 4802 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 4803 do { \ 4804 struct i40e_profile_segment *p = (profile); \ 4805 u32 count; \ 4806 u32 *nvm; \ 4807 count = p->device_table_count; \ 4808 nvm = (u32 *)&p->device_table[count]; \ 4809 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 4810 } while (0) 4811 4812 /* Get section header in profile */ 4813 #define I40E_SECTION_HEADER(profile, offset) \ 4814 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 4815 4816 /** 4817 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 4818 * @hw: pointer to the hw struct 4819 * @aq: command buffer containing all data to execute AQ 4820 **/ 4821 static int i40e_ddp_exec_aq_section(struct i40e_hw *hw, 4822 struct i40e_profile_aq_section *aq) 4823 { 4824 struct libie_aq_desc desc; 4825 u8 *msg = NULL; 4826 u16 msglen; 4827 int status; 4828 4829 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 4830 desc.flags |= cpu_to_le16(aq->flags); 4831 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw)); 4832 4833 msglen = aq->datalen; 4834 if (msglen) { 4835 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | 4836 LIBIE_AQ_FLAG_RD)); 4837 if (msglen > I40E_AQ_LARGE_BUF) 4838 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4839 desc.datalen = cpu_to_le16(msglen); 4840 msg = &aq->data[0]; 4841 } 4842 4843 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 4844 4845 if (status) { 4846 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4847 "unable to exec DDP AQ opcode %u, error %d\n", 4848 aq->opcode, status); 4849 return status; 4850 } 4851 4852 /* copy returned desc to aq_buf */ 4853 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw)); 4854 4855 return 0; 4856 } 4857 4858 /** 4859 * i40e_validate_profile 4860 * @hw: pointer to the hardware structure 4861 * @profile: pointer to the profile segment of the package to be validated 4862 * @track_id: package tracking id 4863 * @rollback: flag if the profile is for rollback. 4864 * 4865 * Validates supported devices and profile's sections. 4866 */ 4867 static int 4868 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 4869 u32 track_id, bool rollback) 4870 { 4871 struct i40e_profile_section_header *sec = NULL; 4872 struct i40e_section_table *sec_tbl; 4873 u32 vendor_dev_id; 4874 int status = 0; 4875 u32 dev_cnt; 4876 u32 sec_off; 4877 u32 i; 4878 4879 if (track_id == I40E_DDP_TRACKID_INVALID) { 4880 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 4881 return -EOPNOTSUPP; 4882 } 4883 4884 dev_cnt = profile->device_table_count; 4885 for (i = 0; i < dev_cnt; i++) { 4886 vendor_dev_id = profile->device_table[i].vendor_dev_id; 4887 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL && 4888 hw->device_id == (vendor_dev_id & 0xFFFF)) 4889 break; 4890 } 4891 if (dev_cnt && i == dev_cnt) { 4892 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4893 "Device doesn't support DDP\n"); 4894 return -ENODEV; 4895 } 4896 4897 I40E_SECTION_TABLE(profile, sec_tbl); 4898 4899 /* Validate sections types */ 4900 for (i = 0; i < sec_tbl->section_count; i++) { 4901 sec_off = sec_tbl->section_offset[i]; 4902 sec = I40E_SECTION_HEADER(profile, sec_off); 4903 if (rollback) { 4904 if (sec->section.type == SECTION_TYPE_MMIO || 4905 sec->section.type == SECTION_TYPE_AQ || 4906 sec->section.type == SECTION_TYPE_RB_AQ) { 4907 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4908 "Not a roll-back package\n"); 4909 return -EOPNOTSUPP; 4910 } 4911 } else { 4912 if (sec->section.type == SECTION_TYPE_RB_AQ || 4913 sec->section.type == SECTION_TYPE_RB_MMIO) { 4914 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4915 "Not an original package\n"); 4916 return -EOPNOTSUPP; 4917 } 4918 } 4919 } 4920 4921 return status; 4922 } 4923 4924 /** 4925 * i40e_write_profile 4926 * @hw: pointer to the hardware structure 4927 * @profile: pointer to the profile segment of the package to be downloaded 4928 * @track_id: package tracking id 4929 * 4930 * Handles the download of a complete package. 4931 */ 4932 int 4933 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 4934 u32 track_id) 4935 { 4936 struct i40e_profile_section_header *sec = NULL; 4937 struct i40e_profile_aq_section *ddp_aq; 4938 struct i40e_section_table *sec_tbl; 4939 u32 offset = 0, info = 0; 4940 u32 section_size = 0; 4941 int status = 0; 4942 u32 sec_off; 4943 u32 i; 4944 4945 status = i40e_validate_profile(hw, profile, track_id, false); 4946 if (status) 4947 return status; 4948 4949 I40E_SECTION_TABLE(profile, sec_tbl); 4950 4951 for (i = 0; i < sec_tbl->section_count; i++) { 4952 sec_off = sec_tbl->section_offset[i]; 4953 sec = I40E_SECTION_HEADER(profile, sec_off); 4954 /* Process generic admin command */ 4955 if (sec->section.type == SECTION_TYPE_AQ) { 4956 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 4957 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 4958 if (status) { 4959 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4960 "Failed to execute aq: section %d, opcode %u\n", 4961 i, ddp_aq->opcode); 4962 break; 4963 } 4964 sec->section.type = SECTION_TYPE_RB_AQ; 4965 } 4966 4967 /* Skip any non-mmio sections */ 4968 if (sec->section.type != SECTION_TYPE_MMIO) 4969 continue; 4970 4971 section_size = sec->section.size + 4972 sizeof(struct i40e_profile_section_header); 4973 4974 /* Write MMIO section */ 4975 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 4976 track_id, &offset, &info, NULL); 4977 if (status) { 4978 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4979 "Failed to write profile: section %d, offset %d, info %d\n", 4980 i, offset, info); 4981 break; 4982 } 4983 } 4984 return status; 4985 } 4986 4987 /** 4988 * i40e_rollback_profile 4989 * @hw: pointer to the hardware structure 4990 * @profile: pointer to the profile segment of the package to be removed 4991 * @track_id: package tracking id 4992 * 4993 * Rolls back previously loaded package. 4994 */ 4995 int 4996 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 4997 u32 track_id) 4998 { 4999 struct i40e_profile_section_header *sec = NULL; 5000 struct i40e_section_table *sec_tbl; 5001 u32 offset = 0, info = 0; 5002 u32 section_size = 0; 5003 int status = 0; 5004 u32 sec_off; 5005 int i; 5006 5007 status = i40e_validate_profile(hw, profile, track_id, true); 5008 if (status) 5009 return status; 5010 5011 I40E_SECTION_TABLE(profile, sec_tbl); 5012 5013 /* For rollback write sections in reverse */ 5014 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 5015 sec_off = sec_tbl->section_offset[i]; 5016 sec = I40E_SECTION_HEADER(profile, sec_off); 5017 5018 /* Skip any non-rollback sections */ 5019 if (sec->section.type != SECTION_TYPE_RB_MMIO) 5020 continue; 5021 5022 section_size = sec->section.size + 5023 sizeof(struct i40e_profile_section_header); 5024 5025 /* Write roll-back MMIO section */ 5026 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5027 track_id, &offset, &info, NULL); 5028 if (status) { 5029 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5030 "Failed to write profile: section %d, offset %d, info %d\n", 5031 i, offset, info); 5032 break; 5033 } 5034 } 5035 return status; 5036 } 5037 5038 /** 5039 * i40e_aq_add_cloud_filters 5040 * @hw: pointer to the hardware structure 5041 * @seid: VSI seid to add cloud filters from 5042 * @filters: Buffer which contains the filters to be added 5043 * @filter_count: number of filters contained in the buffer 5044 * 5045 * Set the cloud filters for a given VSI. The contents of the 5046 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5047 * of the function. 5048 * 5049 **/ 5050 int 5051 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5052 struct i40e_aqc_cloud_filters_element_data *filters, 5053 u8 filter_count) 5054 { 5055 struct i40e_aqc_add_remove_cloud_filters *cmd; 5056 struct libie_aq_desc desc; 5057 u16 buff_len; 5058 int status; 5059 5060 i40e_fill_default_direct_cmd_desc(&desc, 5061 i40e_aqc_opc_add_cloud_filters); 5062 5063 cmd = libie_aq_raw(&desc); 5064 buff_len = filter_count * sizeof(*filters); 5065 desc.datalen = cpu_to_le16(buff_len); 5066 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5067 cmd->num_filters = filter_count; 5068 cmd->seid = cpu_to_le16(seid); 5069 5070 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5071 5072 return status; 5073 } 5074 5075 /** 5076 * i40e_aq_add_cloud_filters_bb 5077 * @hw: pointer to the hardware structure 5078 * @seid: VSI seid to add cloud filters from 5079 * @filters: Buffer which contains the filters in big buffer to be added 5080 * @filter_count: number of filters contained in the buffer 5081 * 5082 * Set the big buffer cloud filters for a given VSI. The contents of the 5083 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5084 * function. 5085 * 5086 **/ 5087 int 5088 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5089 struct i40e_aqc_cloud_filters_element_bb *filters, 5090 u8 filter_count) 5091 { 5092 struct i40e_aqc_add_remove_cloud_filters *cmd; 5093 struct libie_aq_desc desc; 5094 u16 buff_len; 5095 int status; 5096 int i; 5097 5098 i40e_fill_default_direct_cmd_desc(&desc, 5099 i40e_aqc_opc_add_cloud_filters); 5100 5101 cmd = libie_aq_raw(&desc); 5102 buff_len = filter_count * sizeof(*filters); 5103 desc.datalen = cpu_to_le16(buff_len); 5104 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5105 cmd->num_filters = filter_count; 5106 cmd->seid = cpu_to_le16(seid); 5107 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5108 5109 for (i = 0; i < filter_count; i++) { 5110 u16 tnl_type; 5111 u32 ti; 5112 5113 tnl_type = le16_get_bits(filters[i].element.flags, 5114 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5115 5116 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5117 * one more byte further than normally used for Tenant ID in 5118 * other tunnel types. 5119 */ 5120 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5121 ti = le32_to_cpu(filters[i].element.tenant_id); 5122 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5123 } 5124 } 5125 5126 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5127 5128 return status; 5129 } 5130 5131 /** 5132 * i40e_aq_rem_cloud_filters 5133 * @hw: pointer to the hardware structure 5134 * @seid: VSI seid to remove cloud filters from 5135 * @filters: Buffer which contains the filters to be removed 5136 * @filter_count: number of filters contained in the buffer 5137 * 5138 * Remove the cloud filters for a given VSI. The contents of the 5139 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5140 * of the function. 5141 * 5142 **/ 5143 int 5144 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5145 struct i40e_aqc_cloud_filters_element_data *filters, 5146 u8 filter_count) 5147 { 5148 struct i40e_aqc_add_remove_cloud_filters *cmd; 5149 struct libie_aq_desc desc; 5150 u16 buff_len; 5151 int status; 5152 5153 i40e_fill_default_direct_cmd_desc(&desc, 5154 i40e_aqc_opc_remove_cloud_filters); 5155 5156 cmd = libie_aq_raw(&desc); 5157 buff_len = filter_count * sizeof(*filters); 5158 desc.datalen = cpu_to_le16(buff_len); 5159 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5160 cmd->num_filters = filter_count; 5161 cmd->seid = cpu_to_le16(seid); 5162 5163 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5164 5165 return status; 5166 } 5167 5168 /** 5169 * i40e_aq_rem_cloud_filters_bb 5170 * @hw: pointer to the hardware structure 5171 * @seid: VSI seid to remove cloud filters from 5172 * @filters: Buffer which contains the filters in big buffer to be removed 5173 * @filter_count: number of filters contained in the buffer 5174 * 5175 * Remove the big buffer cloud filters for a given VSI. The contents of the 5176 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5177 * function. 5178 * 5179 **/ 5180 int 5181 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5182 struct i40e_aqc_cloud_filters_element_bb *filters, 5183 u8 filter_count) 5184 { 5185 struct i40e_aqc_add_remove_cloud_filters *cmd; 5186 struct libie_aq_desc desc; 5187 u16 buff_len; 5188 int status; 5189 int i; 5190 5191 i40e_fill_default_direct_cmd_desc(&desc, 5192 i40e_aqc_opc_remove_cloud_filters); 5193 5194 cmd = libie_aq_raw(&desc); 5195 buff_len = filter_count * sizeof(*filters); 5196 desc.datalen = cpu_to_le16(buff_len); 5197 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5198 cmd->num_filters = filter_count; 5199 cmd->seid = cpu_to_le16(seid); 5200 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5201 5202 for (i = 0; i < filter_count; i++) { 5203 u16 tnl_type; 5204 u32 ti; 5205 5206 tnl_type = le16_get_bits(filters[i].element.flags, 5207 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5208 5209 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5210 * one more byte further than normally used for Tenant ID in 5211 * other tunnel types. 5212 */ 5213 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5214 ti = le32_to_cpu(filters[i].element.tenant_id); 5215 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5216 } 5217 } 5218 5219 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5220 5221 return status; 5222 } 5223