1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2017 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_ADMINQ_CMD_H_ 28 #define _I40E_ADMINQ_CMD_H_ 29 30 /* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36 #define I40E_FW_API_VERSION_MAJOR 0x0001 37 #define I40E_FW_API_VERSION_MINOR_X722 0x0005 38 #define I40E_FW_API_VERSION_MINOR_X710 0x0007 39 40 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 41 I40E_FW_API_VERSION_MINOR_X710 : \ 42 I40E_FW_API_VERSION_MINOR_X722) 43 44 /* API version 1.7 implements additional link and PHY-specific APIs */ 45 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 46 47 struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69 }; 70 71 /* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76 /* command flags and offsets*/ 77 #define I40E_AQ_FLAG_DD_SHIFT 0 78 #define I40E_AQ_FLAG_CMP_SHIFT 1 79 #define I40E_AQ_FLAG_ERR_SHIFT 2 80 #define I40E_AQ_FLAG_VFE_SHIFT 3 81 #define I40E_AQ_FLAG_LB_SHIFT 9 82 #define I40E_AQ_FLAG_RD_SHIFT 10 83 #define I40E_AQ_FLAG_VFC_SHIFT 11 84 #define I40E_AQ_FLAG_BUF_SHIFT 12 85 #define I40E_AQ_FLAG_SI_SHIFT 13 86 #define I40E_AQ_FLAG_EI_SHIFT 14 87 #define I40E_AQ_FLAG_FE_SHIFT 15 88 89 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101 /* error codes */ 102 enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126 }; 127 128 /* Admin Queue command opcodes */ 129 enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* Proxy commands */ 144 i40e_aqc_opc_set_proxy_config = 0x0104, 145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 146 147 /* LAA */ 148 i40e_aqc_opc_mac_address_read = 0x0107, 149 i40e_aqc_opc_mac_address_write = 0x0108, 150 151 /* PXE */ 152 i40e_aqc_opc_clear_pxe_mode = 0x0110, 153 154 /* WoL commands */ 155 i40e_aqc_opc_set_wol_filter = 0x0120, 156 i40e_aqc_opc_get_wake_reason = 0x0121, 157 158 /* internal switch commands */ 159 i40e_aqc_opc_get_switch_config = 0x0200, 160 i40e_aqc_opc_add_statistics = 0x0201, 161 i40e_aqc_opc_remove_statistics = 0x0202, 162 i40e_aqc_opc_set_port_parameters = 0x0203, 163 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 164 i40e_aqc_opc_set_switch_config = 0x0205, 165 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 166 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 167 168 i40e_aqc_opc_add_vsi = 0x0210, 169 i40e_aqc_opc_update_vsi_parameters = 0x0211, 170 i40e_aqc_opc_get_vsi_parameters = 0x0212, 171 172 i40e_aqc_opc_add_pv = 0x0220, 173 i40e_aqc_opc_update_pv_parameters = 0x0221, 174 i40e_aqc_opc_get_pv_parameters = 0x0222, 175 176 i40e_aqc_opc_add_veb = 0x0230, 177 i40e_aqc_opc_update_veb_parameters = 0x0231, 178 i40e_aqc_opc_get_veb_parameters = 0x0232, 179 180 i40e_aqc_opc_delete_element = 0x0243, 181 182 i40e_aqc_opc_add_macvlan = 0x0250, 183 i40e_aqc_opc_remove_macvlan = 0x0251, 184 i40e_aqc_opc_add_vlan = 0x0252, 185 i40e_aqc_opc_remove_vlan = 0x0253, 186 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 187 i40e_aqc_opc_add_tag = 0x0255, 188 i40e_aqc_opc_remove_tag = 0x0256, 189 i40e_aqc_opc_add_multicast_etag = 0x0257, 190 i40e_aqc_opc_remove_multicast_etag = 0x0258, 191 i40e_aqc_opc_update_tag = 0x0259, 192 i40e_aqc_opc_add_control_packet_filter = 0x025A, 193 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 194 i40e_aqc_opc_add_cloud_filters = 0x025C, 195 i40e_aqc_opc_remove_cloud_filters = 0x025D, 196 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 197 198 i40e_aqc_opc_add_mirror_rule = 0x0260, 199 i40e_aqc_opc_delete_mirror_rule = 0x0261, 200 201 /* Pipeline Personalization Profile */ 202 i40e_aqc_opc_write_personalization_profile = 0x0270, 203 i40e_aqc_opc_get_personalization_profile_list = 0x0271, 204 205 /* DCB commands */ 206 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 207 i40e_aqc_opc_dcb_updated = 0x0302, 208 209 /* TX scheduler */ 210 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 211 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 212 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 213 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 214 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 215 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 216 217 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 218 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 219 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 220 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 221 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 222 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 223 i40e_aqc_opc_query_port_ets_config = 0x0419, 224 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 225 i40e_aqc_opc_suspend_port_tx = 0x041B, 226 i40e_aqc_opc_resume_port_tx = 0x041C, 227 i40e_aqc_opc_configure_partition_bw = 0x041D, 228 /* hmc */ 229 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 230 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 231 232 /* phy commands*/ 233 i40e_aqc_opc_get_phy_abilities = 0x0600, 234 i40e_aqc_opc_set_phy_config = 0x0601, 235 i40e_aqc_opc_set_mac_config = 0x0603, 236 i40e_aqc_opc_set_link_restart_an = 0x0605, 237 i40e_aqc_opc_get_link_status = 0x0607, 238 i40e_aqc_opc_set_phy_int_mask = 0x0613, 239 i40e_aqc_opc_get_local_advt_reg = 0x0614, 240 i40e_aqc_opc_set_local_advt_reg = 0x0615, 241 i40e_aqc_opc_get_partner_advt = 0x0616, 242 i40e_aqc_opc_set_lb_modes = 0x0618, 243 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 244 i40e_aqc_opc_set_phy_debug = 0x0622, 245 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 246 i40e_aqc_opc_run_phy_activity = 0x0626, 247 i40e_aqc_opc_set_phy_register = 0x0628, 248 i40e_aqc_opc_get_phy_register = 0x0629, 249 250 /* NVM commands */ 251 i40e_aqc_opc_nvm_read = 0x0701, 252 i40e_aqc_opc_nvm_erase = 0x0702, 253 i40e_aqc_opc_nvm_update = 0x0703, 254 i40e_aqc_opc_nvm_config_read = 0x0704, 255 i40e_aqc_opc_nvm_config_write = 0x0705, 256 i40e_aqc_opc_oem_post_update = 0x0720, 257 i40e_aqc_opc_thermal_sensor = 0x0721, 258 259 /* virtualization commands */ 260 i40e_aqc_opc_send_msg_to_pf = 0x0801, 261 i40e_aqc_opc_send_msg_to_vf = 0x0802, 262 i40e_aqc_opc_send_msg_to_peer = 0x0803, 263 264 /* alternate structure */ 265 i40e_aqc_opc_alternate_write = 0x0900, 266 i40e_aqc_opc_alternate_write_indirect = 0x0901, 267 i40e_aqc_opc_alternate_read = 0x0902, 268 i40e_aqc_opc_alternate_read_indirect = 0x0903, 269 i40e_aqc_opc_alternate_write_done = 0x0904, 270 i40e_aqc_opc_alternate_set_mode = 0x0905, 271 i40e_aqc_opc_alternate_clear_port = 0x0906, 272 273 /* LLDP commands */ 274 i40e_aqc_opc_lldp_get_mib = 0x0A00, 275 i40e_aqc_opc_lldp_update_mib = 0x0A01, 276 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 277 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 278 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 279 i40e_aqc_opc_lldp_stop = 0x0A05, 280 i40e_aqc_opc_lldp_start = 0x0A06, 281 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 282 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 283 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 284 285 /* Tunnel commands */ 286 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 287 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 288 i40e_aqc_opc_set_rss_key = 0x0B02, 289 i40e_aqc_opc_set_rss_lut = 0x0B03, 290 i40e_aqc_opc_get_rss_key = 0x0B04, 291 i40e_aqc_opc_get_rss_lut = 0x0B05, 292 293 /* Async Events */ 294 i40e_aqc_opc_event_lan_overflow = 0x1001, 295 296 /* OEM commands */ 297 i40e_aqc_opc_oem_parameter_change = 0xFE00, 298 i40e_aqc_opc_oem_device_status_change = 0xFE01, 299 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 300 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 301 302 /* debug commands */ 303 i40e_aqc_opc_debug_read_reg = 0xFF03, 304 i40e_aqc_opc_debug_write_reg = 0xFF04, 305 i40e_aqc_opc_debug_modify_reg = 0xFF07, 306 i40e_aqc_opc_debug_dump_internals = 0xFF08, 307 }; 308 309 /* command structures and indirect data structures */ 310 311 /* Structure naming conventions: 312 * - no suffix for direct command descriptor structures 313 * - _data for indirect sent data 314 * - _resp for indirect return data (data which is both will use _data) 315 * - _completion for direct return data 316 * - _element_ for repeated elements (may also be _data or _resp) 317 * 318 * Command structures are expected to overlay the params.raw member of the basic 319 * descriptor, and as such cannot exceed 16 bytes in length. 320 */ 321 322 /* This macro is used to generate a compilation error if a structure 323 * is not exactly the correct length. It gives a divide by zero error if the 324 * structure is not of the correct size, otherwise it creates an enum that is 325 * never used. 326 */ 327 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 328 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 329 330 /* This macro is used extensively to ensure that command structures are 16 331 * bytes in length as they have to map to the raw array of that size. 332 */ 333 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 334 335 /* internal (0x00XX) commands */ 336 337 /* Get version (direct 0x0001) */ 338 struct i40e_aqc_get_version { 339 __le32 rom_ver; 340 __le32 fw_build; 341 __le16 fw_major; 342 __le16 fw_minor; 343 __le16 api_major; 344 __le16 api_minor; 345 }; 346 347 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 348 349 /* Send driver version (indirect 0x0002) */ 350 struct i40e_aqc_driver_version { 351 u8 driver_major_ver; 352 u8 driver_minor_ver; 353 u8 driver_build_ver; 354 u8 driver_subbuild_ver; 355 u8 reserved[4]; 356 __le32 address_high; 357 __le32 address_low; 358 }; 359 360 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 361 362 /* Queue Shutdown (direct 0x0003) */ 363 struct i40e_aqc_queue_shutdown { 364 __le32 driver_unloading; 365 #define I40E_AQ_DRIVER_UNLOADING 0x1 366 u8 reserved[12]; 367 }; 368 369 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 370 371 /* Set PF context (0x0004, direct) */ 372 struct i40e_aqc_set_pf_context { 373 u8 pf_id; 374 u8 reserved[15]; 375 }; 376 377 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 378 379 /* Request resource ownership (direct 0x0008) 380 * Release resource ownership (direct 0x0009) 381 */ 382 #define I40E_AQ_RESOURCE_NVM 1 383 #define I40E_AQ_RESOURCE_SDP 2 384 #define I40E_AQ_RESOURCE_ACCESS_READ 1 385 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 386 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 387 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 388 389 struct i40e_aqc_request_resource { 390 __le16 resource_id; 391 __le16 access_type; 392 __le32 timeout; 393 __le32 resource_number; 394 u8 reserved[4]; 395 }; 396 397 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 398 399 /* Get function capabilities (indirect 0x000A) 400 * Get device capabilities (indirect 0x000B) 401 */ 402 struct i40e_aqc_list_capabilites { 403 u8 command_flags; 404 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 405 u8 pf_index; 406 u8 reserved[2]; 407 __le32 count; 408 __le32 addr_high; 409 __le32 addr_low; 410 }; 411 412 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 413 414 struct i40e_aqc_list_capabilities_element_resp { 415 __le16 id; 416 u8 major_rev; 417 u8 minor_rev; 418 __le32 number; 419 __le32 logical_id; 420 __le32 phys_id; 421 u8 reserved[16]; 422 }; 423 424 /* list of caps */ 425 426 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 427 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 428 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 429 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 430 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 431 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 432 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 433 #define I40E_AQ_CAP_ID_SRIOV 0x0012 434 #define I40E_AQ_CAP_ID_VF 0x0013 435 #define I40E_AQ_CAP_ID_VMDQ 0x0014 436 #define I40E_AQ_CAP_ID_8021QBG 0x0015 437 #define I40E_AQ_CAP_ID_8021QBR 0x0016 438 #define I40E_AQ_CAP_ID_VSI 0x0017 439 #define I40E_AQ_CAP_ID_DCB 0x0018 440 #define I40E_AQ_CAP_ID_FCOE 0x0021 441 #define I40E_AQ_CAP_ID_ISCSI 0x0022 442 #define I40E_AQ_CAP_ID_RSS 0x0040 443 #define I40E_AQ_CAP_ID_RXQ 0x0041 444 #define I40E_AQ_CAP_ID_TXQ 0x0042 445 #define I40E_AQ_CAP_ID_MSIX 0x0043 446 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 447 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 448 #define I40E_AQ_CAP_ID_1588 0x0046 449 #define I40E_AQ_CAP_ID_IWARP 0x0051 450 #define I40E_AQ_CAP_ID_LED 0x0061 451 #define I40E_AQ_CAP_ID_SDP 0x0062 452 #define I40E_AQ_CAP_ID_MDIO 0x0063 453 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 454 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 455 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 456 #define I40E_AQ_CAP_ID_CEM 0x00F2 457 458 /* Set CPPM Configuration (direct 0x0103) */ 459 struct i40e_aqc_cppm_configuration { 460 __le16 command_flags; 461 #define I40E_AQ_CPPM_EN_LTRC 0x0800 462 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 463 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 464 #define I40E_AQ_CPPM_EN_HPTC 0x4000 465 #define I40E_AQ_CPPM_EN_DMARC 0x8000 466 __le16 ttlx; 467 __le32 dmacr; 468 __le16 dmcth; 469 u8 hptc; 470 u8 reserved; 471 __le32 pfltrc; 472 }; 473 474 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 475 476 /* Set ARP Proxy command / response (indirect 0x0104) */ 477 struct i40e_aqc_arp_proxy_data { 478 __le16 command_flags; 479 #define I40E_AQ_ARP_INIT_IPV4 0x0800 480 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 481 #define I40E_AQ_ARP_ENA 0x2000 482 #define I40E_AQ_ARP_ADD_IPV4 0x4000 483 #define I40E_AQ_ARP_DEL_IPV4 0x8000 484 __le16 table_id; 485 __le32 enabled_offloads; 486 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 487 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 488 __le32 ip_addr; 489 u8 mac_addr[6]; 490 u8 reserved[2]; 491 }; 492 493 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 494 495 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 496 struct i40e_aqc_ns_proxy_data { 497 __le16 table_idx_mac_addr_0; 498 __le16 table_idx_mac_addr_1; 499 __le16 table_idx_ipv6_0; 500 __le16 table_idx_ipv6_1; 501 __le16 control; 502 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 503 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 504 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 505 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 506 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 507 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 508 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 509 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 510 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 511 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 512 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 513 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 514 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 515 u8 mac_addr_0[6]; 516 u8 mac_addr_1[6]; 517 u8 local_mac_addr[6]; 518 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 519 u8 ipv6_addr_1[16]; 520 }; 521 522 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 523 524 /* Manage LAA Command (0x0106) - obsolete */ 525 struct i40e_aqc_mng_laa { 526 __le16 command_flags; 527 #define I40E_AQ_LAA_FLAG_WR 0x8000 528 u8 reserved[2]; 529 __le32 sal; 530 __le16 sah; 531 u8 reserved2[6]; 532 }; 533 534 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 535 536 /* Manage MAC Address Read Command (indirect 0x0107) */ 537 struct i40e_aqc_mac_address_read { 538 __le16 command_flags; 539 #define I40E_AQC_LAN_ADDR_VALID 0x10 540 #define I40E_AQC_SAN_ADDR_VALID 0x20 541 #define I40E_AQC_PORT_ADDR_VALID 0x40 542 #define I40E_AQC_WOL_ADDR_VALID 0x80 543 #define I40E_AQC_MC_MAG_EN_VALID 0x100 544 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 545 u8 reserved[6]; 546 __le32 addr_high; 547 __le32 addr_low; 548 }; 549 550 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 551 552 struct i40e_aqc_mac_address_read_data { 553 u8 pf_lan_mac[6]; 554 u8 pf_san_mac[6]; 555 u8 port_mac[6]; 556 u8 pf_wol_mac[6]; 557 }; 558 559 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 560 561 /* Manage MAC Address Write Command (0x0108) */ 562 struct i40e_aqc_mac_address_write { 563 __le16 command_flags; 564 #define I40E_AQC_MC_MAG_EN 0x0100 565 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 566 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 567 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 568 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 569 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 570 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 571 572 __le16 mac_sah; 573 __le32 mac_sal; 574 u8 reserved[8]; 575 }; 576 577 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 578 579 /* PXE commands (0x011x) */ 580 581 /* Clear PXE Command and response (direct 0x0110) */ 582 struct i40e_aqc_clear_pxe { 583 u8 rx_cnt; 584 u8 reserved[15]; 585 }; 586 587 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 588 589 /* Set WoL Filter (0x0120) */ 590 591 struct i40e_aqc_set_wol_filter { 592 __le16 filter_index; 593 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 594 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 595 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 596 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 597 598 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 599 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 600 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 601 __le16 cmd_flags; 602 #define I40E_AQC_SET_WOL_FILTER 0x8000 603 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 604 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 605 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 606 __le16 valid_flags; 607 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 608 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 609 u8 reserved[2]; 610 __le32 address_high; 611 __le32 address_low; 612 }; 613 614 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 615 616 struct i40e_aqc_set_wol_filter_data { 617 u8 filter[128]; 618 u8 mask[16]; 619 }; 620 621 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 622 623 /* Get Wake Reason (0x0121) */ 624 625 struct i40e_aqc_get_wake_reason_completion { 626 u8 reserved_1[2]; 627 __le16 wake_reason; 628 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 629 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 630 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 631 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 632 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 633 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 634 u8 reserved_2[12]; 635 }; 636 637 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 638 639 /* Switch configuration commands (0x02xx) */ 640 641 /* Used by many indirect commands that only pass an seid and a buffer in the 642 * command 643 */ 644 struct i40e_aqc_switch_seid { 645 __le16 seid; 646 u8 reserved[6]; 647 __le32 addr_high; 648 __le32 addr_low; 649 }; 650 651 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 652 653 /* Get Switch Configuration command (indirect 0x0200) 654 * uses i40e_aqc_switch_seid for the descriptor 655 */ 656 struct i40e_aqc_get_switch_config_header_resp { 657 __le16 num_reported; 658 __le16 num_total; 659 u8 reserved[12]; 660 }; 661 662 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 663 664 struct i40e_aqc_switch_config_element_resp { 665 u8 element_type; 666 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 667 #define I40E_AQ_SW_ELEM_TYPE_PF 2 668 #define I40E_AQ_SW_ELEM_TYPE_VF 3 669 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 670 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 671 #define I40E_AQ_SW_ELEM_TYPE_PV 16 672 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 673 #define I40E_AQ_SW_ELEM_TYPE_PA 18 674 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 675 u8 revision; 676 #define I40E_AQ_SW_ELEM_REV_1 1 677 __le16 seid; 678 __le16 uplink_seid; 679 __le16 downlink_seid; 680 u8 reserved[3]; 681 u8 connection_type; 682 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 683 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 684 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 685 __le16 scheduler_id; 686 __le16 element_info; 687 }; 688 689 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 690 691 /* Get Switch Configuration (indirect 0x0200) 692 * an array of elements are returned in the response buffer 693 * the first in the array is the header, remainder are elements 694 */ 695 struct i40e_aqc_get_switch_config_resp { 696 struct i40e_aqc_get_switch_config_header_resp header; 697 struct i40e_aqc_switch_config_element_resp element[1]; 698 }; 699 700 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 701 702 /* Add Statistics (direct 0x0201) 703 * Remove Statistics (direct 0x0202) 704 */ 705 struct i40e_aqc_add_remove_statistics { 706 __le16 seid; 707 __le16 vlan; 708 __le16 stat_index; 709 u8 reserved[10]; 710 }; 711 712 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 713 714 /* Set Port Parameters command (direct 0x0203) */ 715 struct i40e_aqc_set_port_parameters { 716 __le16 command_flags; 717 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 718 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 719 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 720 __le16 bad_frame_vsi; 721 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 722 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 723 __le16 default_seid; /* reserved for command */ 724 u8 reserved[10]; 725 }; 726 727 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 728 729 /* Get Switch Resource Allocation (indirect 0x0204) */ 730 struct i40e_aqc_get_switch_resource_alloc { 731 u8 num_entries; /* reserved for command */ 732 u8 reserved[7]; 733 __le32 addr_high; 734 __le32 addr_low; 735 }; 736 737 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 738 739 /* expect an array of these structs in the response buffer */ 740 struct i40e_aqc_switch_resource_alloc_element_resp { 741 u8 resource_type; 742 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 743 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 744 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 745 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 746 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 747 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 748 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 749 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 750 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 751 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 752 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 753 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 754 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 755 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 756 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 757 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 758 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 759 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 760 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 761 u8 reserved1; 762 __le16 guaranteed; 763 __le16 total; 764 __le16 used; 765 __le16 total_unalloced; 766 u8 reserved2[6]; 767 }; 768 769 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 770 771 /* Set Switch Configuration (direct 0x0205) */ 772 struct i40e_aqc_set_switch_config { 773 __le16 flags; 774 /* flags used for both fields below */ 775 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 776 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 777 __le16 valid_flags; 778 /* The ethertype in switch_tag is dropped on ingress and used 779 * internally by the switch. Set this to zero for the default 780 * of 0x88a8 (802.1ad). Should be zero for firmware API 781 * versions lower than 1.7. 782 */ 783 __le16 switch_tag; 784 /* The ethertypes in first_tag and second_tag are used to 785 * match the outer and inner VLAN tags (respectively) when HW 786 * double VLAN tagging is enabled via the set port parameters 787 * AQ command. Otherwise these are both ignored. Set them to 788 * zero for their defaults of 0x8100 (802.1Q). Should be zero 789 * for firmware API versions lower than 1.7. 790 */ 791 __le16 first_tag; 792 __le16 second_tag; 793 u8 reserved[6]; 794 }; 795 796 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 797 798 /* Read Receive control registers (direct 0x0206) 799 * Write Receive control registers (direct 0x0207) 800 * used for accessing Rx control registers that can be 801 * slow and need special handling when under high Rx load 802 */ 803 struct i40e_aqc_rx_ctl_reg_read_write { 804 __le32 reserved1; 805 __le32 address; 806 __le32 reserved2; 807 __le32 value; 808 }; 809 810 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 811 812 /* Add VSI (indirect 0x0210) 813 * this indirect command uses struct i40e_aqc_vsi_properties_data 814 * as the indirect buffer (128 bytes) 815 * 816 * Update VSI (indirect 0x211) 817 * uses the same data structure as Add VSI 818 * 819 * Get VSI (indirect 0x0212) 820 * uses the same completion and data structure as Add VSI 821 */ 822 struct i40e_aqc_add_get_update_vsi { 823 __le16 uplink_seid; 824 u8 connection_type; 825 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 826 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 827 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 828 u8 reserved1; 829 u8 vf_id; 830 u8 reserved2; 831 __le16 vsi_flags; 832 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 833 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 834 #define I40E_AQ_VSI_TYPE_VF 0x0 835 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 836 #define I40E_AQ_VSI_TYPE_PF 0x2 837 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 838 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 839 __le32 addr_high; 840 __le32 addr_low; 841 }; 842 843 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 844 845 struct i40e_aqc_add_get_update_vsi_completion { 846 __le16 seid; 847 __le16 vsi_number; 848 __le16 vsi_used; 849 __le16 vsi_free; 850 __le32 addr_high; 851 __le32 addr_low; 852 }; 853 854 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 855 856 struct i40e_aqc_vsi_properties_data { 857 /* first 96 byte are written by SW */ 858 __le16 valid_sections; 859 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 860 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 861 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 862 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 863 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 864 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 865 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 866 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 867 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 868 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 869 /* switch section */ 870 __le16 switch_id; /* 12bit id combined with flags below */ 871 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 872 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 873 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 874 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 875 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 876 u8 sw_reserved[2]; 877 /* security section */ 878 u8 sec_flags; 879 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 880 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 881 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 882 u8 sec_reserved; 883 /* VLAN section */ 884 __le16 pvid; /* VLANS include priority bits */ 885 __le16 fcoe_pvid; 886 u8 port_vlan_flags; 887 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 888 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 889 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 890 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 891 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 892 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 893 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 894 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 895 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 896 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 897 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 898 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 899 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 900 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 901 u8 pvlan_reserved[3]; 902 /* ingress egress up sections */ 903 __le32 ingress_table; /* bitmap, 3 bits per up */ 904 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 905 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 906 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 907 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 908 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 909 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 910 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 911 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 912 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 913 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 914 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 915 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 916 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 917 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 918 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 919 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 920 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 921 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 922 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 923 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 924 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 925 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 926 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 927 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 928 __le32 egress_table; /* same defines as for ingress table */ 929 /* cascaded PV section */ 930 __le16 cas_pv_tag; 931 u8 cas_pv_flags; 932 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 933 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 934 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 935 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 936 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 937 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 938 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 939 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 940 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 941 u8 cas_pv_reserved; 942 /* queue mapping section */ 943 __le16 mapping_flags; 944 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 945 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 946 __le16 queue_mapping[16]; 947 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 948 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 949 __le16 tc_mapping[8]; 950 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 951 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 952 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 953 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 954 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 955 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 956 /* queueing option section */ 957 u8 queueing_opt_flags; 958 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 959 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 960 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 961 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 962 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 963 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 964 u8 queueing_opt_reserved[3]; 965 /* scheduler section */ 966 u8 up_enable_bits; 967 u8 sched_reserved; 968 /* outer up section */ 969 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 970 u8 cmd_reserved[8]; 971 /* last 32 bytes are written by FW */ 972 __le16 qs_handle[8]; 973 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 974 __le16 stat_counter_idx; 975 __le16 sched_id; 976 u8 resp_reserved[12]; 977 }; 978 979 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 980 981 /* Add Port Virtualizer (direct 0x0220) 982 * also used for update PV (direct 0x0221) but only flags are used 983 * (IS_CTRL_PORT only works on add PV) 984 */ 985 struct i40e_aqc_add_update_pv { 986 __le16 command_flags; 987 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 988 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 989 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 990 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 991 __le16 uplink_seid; 992 __le16 connected_seid; 993 u8 reserved[10]; 994 }; 995 996 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 997 998 struct i40e_aqc_add_update_pv_completion { 999 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1000 __le16 pv_seid; 1001 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1002 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1003 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1004 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1005 u8 reserved[14]; 1006 }; 1007 1008 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1009 1010 /* Get PV Params (direct 0x0222) 1011 * uses i40e_aqc_switch_seid for the descriptor 1012 */ 1013 1014 struct i40e_aqc_get_pv_params_completion { 1015 __le16 seid; 1016 __le16 default_stag; 1017 __le16 pv_flags; /* same flags as add_pv */ 1018 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1019 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1020 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1021 u8 reserved[8]; 1022 __le16 default_port_seid; 1023 }; 1024 1025 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1026 1027 /* Add VEB (direct 0x0230) */ 1028 struct i40e_aqc_add_veb { 1029 __le16 uplink_seid; 1030 __le16 downlink_seid; 1031 __le16 veb_flags; 1032 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1033 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1034 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1035 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1036 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1037 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1038 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1039 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1040 u8 enable_tcs; 1041 u8 reserved[9]; 1042 }; 1043 1044 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1045 1046 struct i40e_aqc_add_veb_completion { 1047 u8 reserved[6]; 1048 __le16 switch_seid; 1049 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1050 __le16 veb_seid; 1051 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1052 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1053 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1054 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1055 __le16 statistic_index; 1056 __le16 vebs_used; 1057 __le16 vebs_free; 1058 }; 1059 1060 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1061 1062 /* Get VEB Parameters (direct 0x0232) 1063 * uses i40e_aqc_switch_seid for the descriptor 1064 */ 1065 struct i40e_aqc_get_veb_parameters_completion { 1066 __le16 seid; 1067 __le16 switch_id; 1068 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1069 __le16 statistic_index; 1070 __le16 vebs_used; 1071 __le16 vebs_free; 1072 u8 reserved[4]; 1073 }; 1074 1075 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1076 1077 /* Delete Element (direct 0x0243) 1078 * uses the generic i40e_aqc_switch_seid 1079 */ 1080 1081 /* Add MAC-VLAN (indirect 0x0250) */ 1082 1083 /* used for the command for most vlan commands */ 1084 struct i40e_aqc_macvlan { 1085 __le16 num_addresses; 1086 __le16 seid[3]; 1087 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1088 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1089 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1090 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1091 __le32 addr_high; 1092 __le32 addr_low; 1093 }; 1094 1095 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1096 1097 /* indirect data for command and response */ 1098 struct i40e_aqc_add_macvlan_element_data { 1099 u8 mac_addr[6]; 1100 __le16 vlan_tag; 1101 __le16 flags; 1102 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1103 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1104 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1105 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1106 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1107 __le16 queue_number; 1108 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1109 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1110 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1111 /* response section */ 1112 u8 match_method; 1113 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1114 #define I40E_AQC_MM_HASH_MATCH 0x02 1115 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1116 u8 reserved1[3]; 1117 }; 1118 1119 struct i40e_aqc_add_remove_macvlan_completion { 1120 __le16 perfect_mac_used; 1121 __le16 perfect_mac_free; 1122 __le16 unicast_hash_free; 1123 __le16 multicast_hash_free; 1124 __le32 addr_high; 1125 __le32 addr_low; 1126 }; 1127 1128 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1129 1130 /* Remove MAC-VLAN (indirect 0x0251) 1131 * uses i40e_aqc_macvlan for the descriptor 1132 * data points to an array of num_addresses of elements 1133 */ 1134 1135 struct i40e_aqc_remove_macvlan_element_data { 1136 u8 mac_addr[6]; 1137 __le16 vlan_tag; 1138 u8 flags; 1139 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1140 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1141 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1142 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1143 u8 reserved[3]; 1144 /* reply section */ 1145 u8 error_code; 1146 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1147 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1148 u8 reply_reserved[3]; 1149 }; 1150 1151 /* Add VLAN (indirect 0x0252) 1152 * Remove VLAN (indirect 0x0253) 1153 * use the generic i40e_aqc_macvlan for the command 1154 */ 1155 struct i40e_aqc_add_remove_vlan_element_data { 1156 __le16 vlan_tag; 1157 u8 vlan_flags; 1158 /* flags for add VLAN */ 1159 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1160 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1161 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1162 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1163 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1164 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1165 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1166 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1167 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1168 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1169 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1170 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1171 /* flags for remove VLAN */ 1172 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1173 u8 reserved; 1174 u8 result; 1175 /* flags for add VLAN */ 1176 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1177 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1178 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1179 /* flags for remove VLAN */ 1180 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1181 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1182 u8 reserved1[3]; 1183 }; 1184 1185 struct i40e_aqc_add_remove_vlan_completion { 1186 u8 reserved[4]; 1187 __le16 vlans_used; 1188 __le16 vlans_free; 1189 __le32 addr_high; 1190 __le32 addr_low; 1191 }; 1192 1193 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1194 struct i40e_aqc_set_vsi_promiscuous_modes { 1195 __le16 promiscuous_flags; 1196 __le16 valid_flags; 1197 /* flags used for both fields above */ 1198 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1199 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1200 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1201 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1202 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1203 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1204 __le16 seid; 1205 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1206 __le16 vlan_tag; 1207 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1208 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1209 u8 reserved[8]; 1210 }; 1211 1212 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1213 1214 /* Add S/E-tag command (direct 0x0255) 1215 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1216 */ 1217 struct i40e_aqc_add_tag { 1218 __le16 flags; 1219 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1220 __le16 seid; 1221 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1222 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1223 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1224 __le16 tag; 1225 __le16 queue_number; 1226 u8 reserved[8]; 1227 }; 1228 1229 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1230 1231 struct i40e_aqc_add_remove_tag_completion { 1232 u8 reserved[12]; 1233 __le16 tags_used; 1234 __le16 tags_free; 1235 }; 1236 1237 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1238 1239 /* Remove S/E-tag command (direct 0x0256) 1240 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1241 */ 1242 struct i40e_aqc_remove_tag { 1243 __le16 seid; 1244 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1245 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1246 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1247 __le16 tag; 1248 u8 reserved[12]; 1249 }; 1250 1251 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1252 1253 /* Add multicast E-Tag (direct 0x0257) 1254 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1255 * and no external data 1256 */ 1257 struct i40e_aqc_add_remove_mcast_etag { 1258 __le16 pv_seid; 1259 __le16 etag; 1260 u8 num_unicast_etags; 1261 u8 reserved[3]; 1262 __le32 addr_high; /* address of array of 2-byte s-tags */ 1263 __le32 addr_low; 1264 }; 1265 1266 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1267 1268 struct i40e_aqc_add_remove_mcast_etag_completion { 1269 u8 reserved[4]; 1270 __le16 mcast_etags_used; 1271 __le16 mcast_etags_free; 1272 __le32 addr_high; 1273 __le32 addr_low; 1274 1275 }; 1276 1277 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1278 1279 /* Update S/E-Tag (direct 0x0259) */ 1280 struct i40e_aqc_update_tag { 1281 __le16 seid; 1282 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1283 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1284 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1285 __le16 old_tag; 1286 __le16 new_tag; 1287 u8 reserved[10]; 1288 }; 1289 1290 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1291 1292 struct i40e_aqc_update_tag_completion { 1293 u8 reserved[12]; 1294 __le16 tags_used; 1295 __le16 tags_free; 1296 }; 1297 1298 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1299 1300 /* Add Control Packet filter (direct 0x025A) 1301 * Remove Control Packet filter (direct 0x025B) 1302 * uses the i40e_aqc_add_oveb_cloud, 1303 * and the generic direct completion structure 1304 */ 1305 struct i40e_aqc_add_remove_control_packet_filter { 1306 u8 mac[6]; 1307 __le16 etype; 1308 __le16 flags; 1309 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1310 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1311 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1312 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1313 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1314 __le16 seid; 1315 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1316 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1317 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1318 __le16 queue; 1319 u8 reserved[2]; 1320 }; 1321 1322 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1323 1324 struct i40e_aqc_add_remove_control_packet_filter_completion { 1325 __le16 mac_etype_used; 1326 __le16 etype_used; 1327 __le16 mac_etype_free; 1328 __le16 etype_free; 1329 u8 reserved[8]; 1330 }; 1331 1332 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1333 1334 /* Add Cloud filters (indirect 0x025C) 1335 * Remove Cloud filters (indirect 0x025D) 1336 * uses the i40e_aqc_add_remove_cloud_filters, 1337 * and the generic indirect completion structure 1338 */ 1339 struct i40e_aqc_add_remove_cloud_filters { 1340 u8 num_filters; 1341 u8 reserved; 1342 __le16 seid; 1343 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1344 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1345 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1346 u8 reserved2[4]; 1347 __le32 addr_high; 1348 __le32 addr_low; 1349 }; 1350 1351 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1352 1353 struct i40e_aqc_add_remove_cloud_filters_element_data { 1354 u8 outer_mac[6]; 1355 u8 inner_mac[6]; 1356 __le16 inner_vlan; 1357 union { 1358 struct { 1359 u8 reserved[12]; 1360 u8 data[4]; 1361 } v4; 1362 struct { 1363 u8 data[16]; 1364 } v6; 1365 } ipaddr; 1366 __le16 flags; 1367 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1368 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1369 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1370 /* 0x0000 reserved */ 1371 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1372 /* 0x0002 reserved */ 1373 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1374 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1375 /* 0x0005 reserved */ 1376 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1377 /* 0x0007 reserved */ 1378 /* 0x0008 reserved */ 1379 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1380 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1381 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1382 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1383 1384 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1385 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1386 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1387 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1388 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1389 1390 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1391 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1392 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1393 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1394 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1395 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1396 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1397 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1398 1399 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1400 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1401 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1402 1403 __le32 tenant_id; 1404 u8 reserved[4]; 1405 __le16 queue_number; 1406 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1407 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1408 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1409 u8 reserved2[14]; 1410 /* response section */ 1411 u8 allocation_result; 1412 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1413 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1414 u8 response_reserved[7]; 1415 }; 1416 1417 struct i40e_aqc_remove_cloud_filters_completion { 1418 __le16 perfect_ovlan_used; 1419 __le16 perfect_ovlan_free; 1420 __le16 vlan_used; 1421 __le16 vlan_free; 1422 __le32 addr_high; 1423 __le32 addr_low; 1424 }; 1425 1426 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1427 1428 /* Add Mirror Rule (indirect or direct 0x0260) 1429 * Delete Mirror Rule (indirect or direct 0x0261) 1430 * note: some rule types (4,5) do not use an external buffer. 1431 * take care to set the flags correctly. 1432 */ 1433 struct i40e_aqc_add_delete_mirror_rule { 1434 __le16 seid; 1435 __le16 rule_type; 1436 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1437 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1438 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1439 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1440 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1441 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1442 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1443 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1444 __le16 num_entries; 1445 __le16 destination; /* VSI for add, rule id for delete */ 1446 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1447 __le32 addr_low; 1448 }; 1449 1450 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1451 1452 struct i40e_aqc_add_delete_mirror_rule_completion { 1453 u8 reserved[2]; 1454 __le16 rule_id; /* only used on add */ 1455 __le16 mirror_rules_used; 1456 __le16 mirror_rules_free; 1457 __le32 addr_high; 1458 __le32 addr_low; 1459 }; 1460 1461 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1462 1463 /* Pipeline Personalization Profile */ 1464 struct i40e_aqc_write_personalization_profile { 1465 u8 flags; 1466 u8 reserved[3]; 1467 __le32 profile_track_id; 1468 __le32 addr_high; 1469 __le32 addr_low; 1470 }; 1471 1472 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); 1473 1474 struct i40e_aqc_write_ppp_resp { 1475 __le32 error_offset; 1476 __le32 error_info; 1477 __le32 addr_high; 1478 __le32 addr_low; 1479 }; 1480 1481 struct i40e_aqc_get_applied_profiles { 1482 u8 flags; 1483 #define I40E_AQC_GET_PPP_GET_CONF 0x1 1484 #define I40E_AQC_GET_PPP_GET_RDPU_CONF 0x2 1485 u8 rsv[3]; 1486 __le32 reserved; 1487 __le32 addr_high; 1488 __le32 addr_low; 1489 }; 1490 1491 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); 1492 1493 /* DCB 0x03xx*/ 1494 1495 /* PFC Ignore (direct 0x0301) 1496 * the command and response use the same descriptor structure 1497 */ 1498 struct i40e_aqc_pfc_ignore { 1499 u8 tc_bitmap; 1500 u8 command_flags; /* unused on response */ 1501 #define I40E_AQC_PFC_IGNORE_SET 0x80 1502 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1503 u8 reserved[14]; 1504 }; 1505 1506 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1507 1508 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1509 * with no parameters 1510 */ 1511 1512 /* TX scheduler 0x04xx */ 1513 1514 /* Almost all the indirect commands use 1515 * this generic struct to pass the SEID in param0 1516 */ 1517 struct i40e_aqc_tx_sched_ind { 1518 __le16 vsi_seid; 1519 u8 reserved[6]; 1520 __le32 addr_high; 1521 __le32 addr_low; 1522 }; 1523 1524 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1525 1526 /* Several commands respond with a set of queue set handles */ 1527 struct i40e_aqc_qs_handles_resp { 1528 __le16 qs_handles[8]; 1529 }; 1530 1531 /* Configure VSI BW limits (direct 0x0400) */ 1532 struct i40e_aqc_configure_vsi_bw_limit { 1533 __le16 vsi_seid; 1534 u8 reserved[2]; 1535 __le16 credit; 1536 u8 reserved1[2]; 1537 u8 max_credit; /* 0-3, limit = 2^max */ 1538 u8 reserved2[7]; 1539 }; 1540 1541 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1542 1543 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1544 * responds with i40e_aqc_qs_handles_resp 1545 */ 1546 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1547 u8 tc_valid_bits; 1548 u8 reserved[15]; 1549 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1550 1551 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1552 __le16 tc_bw_max[2]; 1553 u8 reserved1[28]; 1554 }; 1555 1556 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1557 1558 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1559 * responds with i40e_aqc_qs_handles_resp 1560 */ 1561 struct i40e_aqc_configure_vsi_tc_bw_data { 1562 u8 tc_valid_bits; 1563 u8 reserved[3]; 1564 u8 tc_bw_credits[8]; 1565 u8 reserved1[4]; 1566 __le16 qs_handles[8]; 1567 }; 1568 1569 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1570 1571 /* Query vsi bw configuration (indirect 0x0408) */ 1572 struct i40e_aqc_query_vsi_bw_config_resp { 1573 u8 tc_valid_bits; 1574 u8 tc_suspended_bits; 1575 u8 reserved[14]; 1576 __le16 qs_handles[8]; 1577 u8 reserved1[4]; 1578 __le16 port_bw_limit; 1579 u8 reserved2[2]; 1580 u8 max_bw; /* 0-3, limit = 2^max */ 1581 u8 reserved3[23]; 1582 }; 1583 1584 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1585 1586 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1587 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1588 u8 tc_valid_bits; 1589 u8 reserved[3]; 1590 u8 share_credits[8]; 1591 __le16 credits[8]; 1592 1593 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1594 __le16 tc_bw_max[2]; 1595 }; 1596 1597 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1598 1599 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1600 struct i40e_aqc_configure_switching_comp_bw_limit { 1601 __le16 seid; 1602 u8 reserved[2]; 1603 __le16 credit; 1604 u8 reserved1[2]; 1605 u8 max_bw; /* 0-3, limit = 2^max */ 1606 u8 reserved2[7]; 1607 }; 1608 1609 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1610 1611 /* Enable Physical Port ETS (indirect 0x0413) 1612 * Modify Physical Port ETS (indirect 0x0414) 1613 * Disable Physical Port ETS (indirect 0x0415) 1614 */ 1615 struct i40e_aqc_configure_switching_comp_ets_data { 1616 u8 reserved[4]; 1617 u8 tc_valid_bits; 1618 u8 seepage; 1619 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1620 u8 tc_strict_priority_flags; 1621 u8 reserved1[17]; 1622 u8 tc_bw_share_credits[8]; 1623 u8 reserved2[96]; 1624 }; 1625 1626 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1627 1628 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1629 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1630 u8 tc_valid_bits; 1631 u8 reserved[15]; 1632 __le16 tc_bw_credit[8]; 1633 1634 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1635 __le16 tc_bw_max[2]; 1636 u8 reserved1[28]; 1637 }; 1638 1639 I40E_CHECK_STRUCT_LEN(0x40, 1640 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1641 1642 /* Configure Switching Component Bandwidth Allocation per Tc 1643 * (indirect 0x0417) 1644 */ 1645 struct i40e_aqc_configure_switching_comp_bw_config_data { 1646 u8 tc_valid_bits; 1647 u8 reserved[2]; 1648 u8 absolute_credits; /* bool */ 1649 u8 tc_bw_share_credits[8]; 1650 u8 reserved1[20]; 1651 }; 1652 1653 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1654 1655 /* Query Switching Component Configuration (indirect 0x0418) */ 1656 struct i40e_aqc_query_switching_comp_ets_config_resp { 1657 u8 tc_valid_bits; 1658 u8 reserved[35]; 1659 __le16 port_bw_limit; 1660 u8 reserved1[2]; 1661 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1662 u8 reserved2[23]; 1663 }; 1664 1665 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1666 1667 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1668 struct i40e_aqc_query_port_ets_config_resp { 1669 u8 reserved[4]; 1670 u8 tc_valid_bits; 1671 u8 reserved1; 1672 u8 tc_strict_priority_bits; 1673 u8 reserved2; 1674 u8 tc_bw_share_credits[8]; 1675 __le16 tc_bw_limits[8]; 1676 1677 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1678 __le16 tc_bw_max[2]; 1679 u8 reserved3[32]; 1680 }; 1681 1682 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1683 1684 /* Query Switching Component Bandwidth Allocation per Traffic Type 1685 * (indirect 0x041A) 1686 */ 1687 struct i40e_aqc_query_switching_comp_bw_config_resp { 1688 u8 tc_valid_bits; 1689 u8 reserved[2]; 1690 u8 absolute_credits_enable; /* bool */ 1691 u8 tc_bw_share_credits[8]; 1692 __le16 tc_bw_limits[8]; 1693 1694 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1695 __le16 tc_bw_max[2]; 1696 }; 1697 1698 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1699 1700 /* Suspend/resume port TX traffic 1701 * (direct 0x041B and 0x041C) uses the generic SEID struct 1702 */ 1703 1704 /* Configure partition BW 1705 * (indirect 0x041D) 1706 */ 1707 struct i40e_aqc_configure_partition_bw_data { 1708 __le16 pf_valid_bits; 1709 u8 min_bw[16]; /* guaranteed bandwidth */ 1710 u8 max_bw[16]; /* bandwidth limit */ 1711 }; 1712 1713 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1714 1715 /* Get and set the active HMC resource profile and status. 1716 * (direct 0x0500) and (direct 0x0501) 1717 */ 1718 struct i40e_aq_get_set_hmc_resource_profile { 1719 u8 pm_profile; 1720 u8 pe_vf_enabled; 1721 u8 reserved[14]; 1722 }; 1723 1724 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1725 1726 enum i40e_aq_hmc_profile { 1727 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1728 I40E_HMC_PROFILE_DEFAULT = 1, 1729 I40E_HMC_PROFILE_FAVOR_VF = 2, 1730 I40E_HMC_PROFILE_EQUAL = 3, 1731 }; 1732 1733 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1734 1735 /* set in param0 for get phy abilities to report qualified modules */ 1736 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1737 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1738 1739 enum i40e_aq_phy_type { 1740 I40E_PHY_TYPE_SGMII = 0x0, 1741 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1742 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1743 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1744 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1745 I40E_PHY_TYPE_XAUI = 0x5, 1746 I40E_PHY_TYPE_XFI = 0x6, 1747 I40E_PHY_TYPE_SFI = 0x7, 1748 I40E_PHY_TYPE_XLAUI = 0x8, 1749 I40E_PHY_TYPE_XLPPI = 0x9, 1750 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1751 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1752 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1753 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1754 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1755 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1756 I40E_PHY_TYPE_100BASE_TX = 0x11, 1757 I40E_PHY_TYPE_1000BASE_T = 0x12, 1758 I40E_PHY_TYPE_10GBASE_T = 0x13, 1759 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1760 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1761 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1762 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1763 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1764 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1765 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1766 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1767 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1768 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1769 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1770 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1771 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1772 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1773 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1774 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1775 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1776 I40E_PHY_TYPE_MAX, 1777 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1778 I40E_PHY_TYPE_EMPTY = 0xFE, 1779 I40E_PHY_TYPE_DEFAULT = 0xFF, 1780 }; 1781 1782 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1783 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1784 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1785 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1786 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1787 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1788 1789 enum i40e_aq_link_speed { 1790 I40E_LINK_SPEED_UNKNOWN = 0, 1791 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), 1792 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), 1793 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), 1794 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), 1795 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), 1796 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), 1797 }; 1798 1799 struct i40e_aqc_module_desc { 1800 u8 oui[3]; 1801 u8 reserved1; 1802 u8 part_number[16]; 1803 u8 revision[4]; 1804 u8 reserved2[8]; 1805 }; 1806 1807 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1808 1809 struct i40e_aq_get_phy_abilities_resp { 1810 __le32 phy_type; /* bitmap using the above enum for offsets */ 1811 u8 link_speed; /* bitmap using the above enum bit patterns */ 1812 u8 abilities; 1813 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1814 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1815 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1816 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1817 #define I40E_AQ_PHY_AN_ENABLED 0x10 1818 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1819 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1820 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1821 __le16 eee_capability; 1822 #define I40E_AQ_EEE_100BASE_TX 0x0002 1823 #define I40E_AQ_EEE_1000BASE_T 0x0004 1824 #define I40E_AQ_EEE_10GBASE_T 0x0008 1825 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1826 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1827 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1828 __le32 eeer_val; 1829 u8 d3_lpan; 1830 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1831 u8 phy_type_ext; 1832 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1833 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1834 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1835 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1836 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1837 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1838 u8 fec_cfg_curr_mod_ext_info; 1839 #define I40E_AQ_ENABLE_FEC_KR 0x01 1840 #define I40E_AQ_ENABLE_FEC_RS 0x02 1841 #define I40E_AQ_REQUEST_FEC_KR 0x04 1842 #define I40E_AQ_REQUEST_FEC_RS 0x08 1843 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 1844 #define I40E_AQ_FEC 1845 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1846 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1847 1848 u8 ext_comp_code; 1849 u8 phy_id[4]; 1850 u8 module_type[3]; 1851 u8 qualified_module_count; 1852 #define I40E_AQ_PHY_MAX_QMS 16 1853 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1854 }; 1855 1856 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1857 1858 /* Set PHY Config (direct 0x0601) */ 1859 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1860 __le32 phy_type; 1861 u8 link_speed; 1862 u8 abilities; 1863 /* bits 0-2 use the values from get_phy_abilities_resp */ 1864 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1865 #define I40E_AQ_PHY_ENABLE_AN 0x10 1866 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1867 __le16 eee_capability; 1868 __le32 eeer; 1869 u8 low_power_ctrl; 1870 u8 phy_type_ext; 1871 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1872 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1873 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1874 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1875 u8 fec_config; 1876 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 1877 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 1878 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 1879 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 1880 #define I40E_AQ_SET_FEC_AUTO BIT(4) 1881 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 1882 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 1883 u8 reserved; 1884 }; 1885 1886 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1887 1888 /* Set MAC Config command data structure (direct 0x0603) */ 1889 struct i40e_aq_set_mac_config { 1890 __le16 max_frame_size; 1891 u8 params; 1892 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1893 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1894 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1895 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1896 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1897 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1898 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1899 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1900 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1901 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1902 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1903 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1904 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1905 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1906 u8 tx_timer_priority; /* bitmap */ 1907 __le16 tx_timer_value; 1908 __le16 fc_refresh_threshold; 1909 u8 reserved[8]; 1910 }; 1911 1912 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1913 1914 /* Restart Auto-Negotiation (direct 0x605) */ 1915 struct i40e_aqc_set_link_restart_an { 1916 u8 command; 1917 #define I40E_AQ_PHY_RESTART_AN 0x02 1918 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1919 u8 reserved[15]; 1920 }; 1921 1922 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1923 1924 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1925 struct i40e_aqc_get_link_status { 1926 __le16 command_flags; /* only field set on command */ 1927 #define I40E_AQ_LSE_MASK 0x3 1928 #define I40E_AQ_LSE_NOP 0x0 1929 #define I40E_AQ_LSE_DISABLE 0x2 1930 #define I40E_AQ_LSE_ENABLE 0x3 1931 /* only response uses this flag */ 1932 #define I40E_AQ_LSE_IS_ENABLED 0x1 1933 u8 phy_type; /* i40e_aq_phy_type */ 1934 u8 link_speed; /* i40e_aq_link_speed */ 1935 u8 link_info; 1936 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1937 #define I40E_AQ_LINK_UP_FUNCTION 0x01 1938 #define I40E_AQ_LINK_FAULT 0x02 1939 #define I40E_AQ_LINK_FAULT_TX 0x04 1940 #define I40E_AQ_LINK_FAULT_RX 0x08 1941 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1942 #define I40E_AQ_LINK_UP_PORT 0x20 1943 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1944 #define I40E_AQ_SIGNAL_DETECT 0x80 1945 u8 an_info; 1946 #define I40E_AQ_AN_COMPLETED 0x01 1947 #define I40E_AQ_LP_AN_ABILITY 0x02 1948 #define I40E_AQ_PD_FAULT 0x04 1949 #define I40E_AQ_FEC_EN 0x08 1950 #define I40E_AQ_PHY_LOW_POWER 0x10 1951 #define I40E_AQ_LINK_PAUSE_TX 0x20 1952 #define I40E_AQ_LINK_PAUSE_RX 0x40 1953 #define I40E_AQ_QUALIFIED_MODULE 0x80 1954 u8 ext_info; 1955 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1956 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1957 #define I40E_AQ_LINK_TX_SHIFT 0x02 1958 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1959 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1960 #define I40E_AQ_LINK_TX_DRAINED 0x01 1961 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1962 #define I40E_AQ_LINK_FORCED_40G 0x10 1963 /* 25G Error Codes */ 1964 #define I40E_AQ_25G_NO_ERR 0X00 1965 #define I40E_AQ_25G_NOT_PRESENT 0X01 1966 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 1967 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 1968 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 1969 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 1970 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1971 /* Since firmware API 1.7 loopback field keeps power class info as well */ 1972 #define I40E_AQ_LOOPBACK_MASK 0x07 1973 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 1974 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 1975 __le16 max_frame_size; 1976 u8 config; 1977 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 1978 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 1979 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1980 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1981 union { 1982 struct { 1983 u8 power_desc; 1984 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 1985 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 1986 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 1987 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 1988 #define I40E_AQ_PWR_CLASS_MASK 0x03 1989 u8 reserved[4]; 1990 }; 1991 struct { 1992 u8 link_type[4]; 1993 u8 link_type_ext; 1994 }; 1995 }; 1996 }; 1997 1998 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1999 2000 /* Set event mask command (direct 0x613) */ 2001 struct i40e_aqc_set_phy_int_mask { 2002 u8 reserved[8]; 2003 __le16 event_mask; 2004 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2005 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2006 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2007 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2008 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2009 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2010 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2011 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2012 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2013 u8 reserved1[6]; 2014 }; 2015 2016 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2017 2018 /* Get Local AN advt register (direct 0x0614) 2019 * Set Local AN advt register (direct 0x0615) 2020 * Get Link Partner AN advt register (direct 0x0616) 2021 */ 2022 struct i40e_aqc_an_advt_reg { 2023 __le32 local_an_reg0; 2024 __le16 local_an_reg1; 2025 u8 reserved[10]; 2026 }; 2027 2028 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2029 2030 /* Set Loopback mode (0x0618) */ 2031 struct i40e_aqc_set_lb_mode { 2032 __le16 lb_mode; 2033 #define I40E_AQ_LB_PHY_LOCAL 0x01 2034 #define I40E_AQ_LB_PHY_REMOTE 0x02 2035 #define I40E_AQ_LB_MAC_LOCAL 0x04 2036 u8 reserved[14]; 2037 }; 2038 2039 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2040 2041 /* Set PHY Debug command (0x0622) */ 2042 struct i40e_aqc_set_phy_debug { 2043 u8 command_flags; 2044 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2045 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2046 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2047 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2048 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2049 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2050 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2051 /* Disable link manageability on a single port */ 2052 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2053 /* Disable link manageability on all ports */ 2054 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2055 u8 reserved[15]; 2056 }; 2057 2058 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2059 2060 enum i40e_aq_phy_reg_type { 2061 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2062 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2063 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2064 }; 2065 2066 /* Run PHY Activity (0x0626) */ 2067 struct i40e_aqc_run_phy_activity { 2068 __le16 activity_id; 2069 u8 flags; 2070 u8 reserved1; 2071 __le32 control; 2072 __le32 data; 2073 u8 reserved2[4]; 2074 }; 2075 2076 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2077 2078 /* Set PHY Register command (0x0628) */ 2079 /* Get PHY Register command (0x0629) */ 2080 struct i40e_aqc_phy_register_access { 2081 u8 phy_interface; 2082 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2083 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2084 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2085 u8 dev_address; 2086 u8 reserved1[2]; 2087 __le32 reg_address; 2088 __le32 reg_value; 2089 u8 reserved2[4]; 2090 }; 2091 2092 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2093 2094 /* NVM Read command (indirect 0x0701) 2095 * NVM Erase commands (direct 0x0702) 2096 * NVM Update commands (indirect 0x0703) 2097 */ 2098 struct i40e_aqc_nvm_update { 2099 u8 command_flags; 2100 #define I40E_AQ_NVM_LAST_CMD 0x01 2101 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2102 u8 module_pointer; 2103 __le16 length; 2104 __le32 offset; 2105 __le32 addr_high; 2106 __le32 addr_low; 2107 }; 2108 2109 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2110 2111 /* NVM Config Read (indirect 0x0704) */ 2112 struct i40e_aqc_nvm_config_read { 2113 __le16 cmd_flags; 2114 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2115 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2116 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2117 __le16 element_count; 2118 __le16 element_id; /* Feature/field ID */ 2119 __le16 element_id_msw; /* MSWord of field ID */ 2120 __le32 address_high; 2121 __le32 address_low; 2122 }; 2123 2124 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2125 2126 /* NVM Config Write (indirect 0x0705) */ 2127 struct i40e_aqc_nvm_config_write { 2128 __le16 cmd_flags; 2129 __le16 element_count; 2130 u8 reserved[4]; 2131 __le32 address_high; 2132 __le32 address_low; 2133 }; 2134 2135 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2136 2137 /* Used for 0x0704 as well as for 0x0705 commands */ 2138 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2139 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2140 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2141 #define I40E_AQ_ANVM_FEATURE 0 2142 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) 2143 struct i40e_aqc_nvm_config_data_feature { 2144 __le16 feature_id; 2145 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2146 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2147 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2148 __le16 feature_options; 2149 __le16 feature_selection; 2150 }; 2151 2152 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2153 2154 struct i40e_aqc_nvm_config_data_immediate_field { 2155 __le32 field_id; 2156 __le32 field_value; 2157 __le16 field_options; 2158 __le16 reserved; 2159 }; 2160 2161 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2162 2163 /* OEM Post Update (indirect 0x0720) 2164 * no command data struct used 2165 */ 2166 struct i40e_aqc_nvm_oem_post_update { 2167 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2168 u8 sel_data; 2169 u8 reserved[7]; 2170 }; 2171 2172 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2173 2174 struct i40e_aqc_nvm_oem_post_update_buffer { 2175 u8 str_len; 2176 u8 dev_addr; 2177 __le16 eeprom_addr; 2178 u8 data[36]; 2179 }; 2180 2181 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2182 2183 /* Thermal Sensor (indirect 0x0721) 2184 * read or set thermal sensor configs and values 2185 * takes a sensor and command specific data buffer, not detailed here 2186 */ 2187 struct i40e_aqc_thermal_sensor { 2188 u8 sensor_action; 2189 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2190 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2191 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2192 u8 reserved[7]; 2193 __le32 addr_high; 2194 __le32 addr_low; 2195 }; 2196 2197 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2198 2199 /* Send to PF command (indirect 0x0801) id is only used by PF 2200 * Send to VF command (indirect 0x0802) id is only used by PF 2201 * Send to Peer PF command (indirect 0x0803) 2202 */ 2203 struct i40e_aqc_pf_vf_message { 2204 __le32 id; 2205 u8 reserved[4]; 2206 __le32 addr_high; 2207 __le32 addr_low; 2208 }; 2209 2210 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2211 2212 /* Alternate structure */ 2213 2214 /* Direct write (direct 0x0900) 2215 * Direct read (direct 0x0902) 2216 */ 2217 struct i40e_aqc_alternate_write { 2218 __le32 address0; 2219 __le32 data0; 2220 __le32 address1; 2221 __le32 data1; 2222 }; 2223 2224 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2225 2226 /* Indirect write (indirect 0x0901) 2227 * Indirect read (indirect 0x0903) 2228 */ 2229 2230 struct i40e_aqc_alternate_ind_write { 2231 __le32 address; 2232 __le32 length; 2233 __le32 addr_high; 2234 __le32 addr_low; 2235 }; 2236 2237 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2238 2239 /* Done alternate write (direct 0x0904) 2240 * uses i40e_aq_desc 2241 */ 2242 struct i40e_aqc_alternate_write_done { 2243 __le16 cmd_flags; 2244 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2245 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2246 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2247 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2248 u8 reserved[14]; 2249 }; 2250 2251 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2252 2253 /* Set OEM mode (direct 0x0905) */ 2254 struct i40e_aqc_alternate_set_mode { 2255 __le32 mode; 2256 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2257 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2258 u8 reserved[12]; 2259 }; 2260 2261 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2262 2263 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2264 2265 /* async events 0x10xx */ 2266 2267 /* Lan Queue Overflow Event (direct, 0x1001) */ 2268 struct i40e_aqc_lan_overflow { 2269 __le32 prtdcb_rupto; 2270 __le32 otx_ctl; 2271 u8 reserved[8]; 2272 }; 2273 2274 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2275 2276 /* Get LLDP MIB (indirect 0x0A00) */ 2277 struct i40e_aqc_lldp_get_mib { 2278 u8 type; 2279 u8 reserved1; 2280 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2281 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2282 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2283 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2284 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2285 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2286 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2287 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2288 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2289 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2290 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2291 __le16 local_len; 2292 __le16 remote_len; 2293 u8 reserved2[2]; 2294 __le32 addr_high; 2295 __le32 addr_low; 2296 }; 2297 2298 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2299 2300 /* Configure LLDP MIB Change Event (direct 0x0A01) 2301 * also used for the event (with type in the command field) 2302 */ 2303 struct i40e_aqc_lldp_update_mib { 2304 u8 command; 2305 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2306 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2307 u8 reserved[7]; 2308 __le32 addr_high; 2309 __le32 addr_low; 2310 }; 2311 2312 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2313 2314 /* Add LLDP TLV (indirect 0x0A02) 2315 * Delete LLDP TLV (indirect 0x0A04) 2316 */ 2317 struct i40e_aqc_lldp_add_tlv { 2318 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2319 u8 reserved1[1]; 2320 __le16 len; 2321 u8 reserved2[4]; 2322 __le32 addr_high; 2323 __le32 addr_low; 2324 }; 2325 2326 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2327 2328 /* Update LLDP TLV (indirect 0x0A03) */ 2329 struct i40e_aqc_lldp_update_tlv { 2330 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2331 u8 reserved; 2332 __le16 old_len; 2333 __le16 new_offset; 2334 __le16 new_len; 2335 __le32 addr_high; 2336 __le32 addr_low; 2337 }; 2338 2339 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2340 2341 /* Stop LLDP (direct 0x0A05) */ 2342 struct i40e_aqc_lldp_stop { 2343 u8 command; 2344 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2345 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2346 u8 reserved[15]; 2347 }; 2348 2349 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2350 2351 /* Start LLDP (direct 0x0A06) */ 2352 2353 struct i40e_aqc_lldp_start { 2354 u8 command; 2355 #define I40E_AQ_LLDP_AGENT_START 0x1 2356 u8 reserved[15]; 2357 }; 2358 2359 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2360 2361 /* Get CEE DCBX Oper Config (0x0A07) 2362 * uses the generic descriptor struct 2363 * returns below as indirect response 2364 */ 2365 2366 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2367 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2368 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2369 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2370 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2371 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2372 2373 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2374 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2375 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2376 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2377 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2378 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2379 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2380 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2381 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2382 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2383 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2384 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2385 2386 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2387 * word boundary layout issues, which the Linux compilers silently deal 2388 * with by adding padding, making the actual struct larger than designed. 2389 * However, the FW compiler for the NIC is less lenient and complains 2390 * about the struct. Hence, the struct defined here has an extra byte in 2391 * fields reserved3 and reserved4 to directly acknowledge that padding, 2392 * and the new length is used in the length check macro. 2393 */ 2394 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2395 u8 reserved1; 2396 u8 oper_num_tc; 2397 u8 oper_prio_tc[4]; 2398 u8 reserved2; 2399 u8 oper_tc_bw[8]; 2400 u8 oper_pfc_en; 2401 u8 reserved3[2]; 2402 __le16 oper_app_prio; 2403 u8 reserved4[2]; 2404 __le16 tlv_status; 2405 }; 2406 2407 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2408 2409 struct i40e_aqc_get_cee_dcb_cfg_resp { 2410 u8 oper_num_tc; 2411 u8 oper_prio_tc[4]; 2412 u8 oper_tc_bw[8]; 2413 u8 oper_pfc_en; 2414 __le16 oper_app_prio; 2415 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2416 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2417 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2418 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2419 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2420 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2421 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2422 __le32 tlv_status; 2423 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2424 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2425 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2426 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2427 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2428 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2429 u8 reserved[12]; 2430 }; 2431 2432 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2433 2434 /* Set Local LLDP MIB (indirect 0x0A08) 2435 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2436 */ 2437 struct i40e_aqc_lldp_set_local_mib { 2438 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2439 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2440 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2441 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2442 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \ 2443 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2444 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2445 u8 type; 2446 u8 reserved0; 2447 __le16 length; 2448 u8 reserved1[4]; 2449 __le32 address_high; 2450 __le32 address_low; 2451 }; 2452 2453 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2454 2455 /* Stop/Start LLDP Agent (direct 0x0A09) 2456 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2457 */ 2458 struct i40e_aqc_lldp_stop_start_specific_agent { 2459 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2460 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2461 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2462 u8 command; 2463 u8 reserved[15]; 2464 }; 2465 2466 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2467 2468 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2469 struct i40e_aqc_add_udp_tunnel { 2470 __le16 udp_port; 2471 u8 reserved0[3]; 2472 u8 protocol_type; 2473 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2474 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2475 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2476 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2477 u8 reserved1[10]; 2478 }; 2479 2480 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2481 2482 struct i40e_aqc_add_udp_tunnel_completion { 2483 __le16 udp_port; 2484 u8 filter_entry_index; 2485 u8 multiple_pfs; 2486 #define I40E_AQC_SINGLE_PF 0x0 2487 #define I40E_AQC_MULTIPLE_PFS 0x1 2488 u8 total_filters; 2489 u8 reserved[11]; 2490 }; 2491 2492 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2493 2494 /* remove UDP Tunnel command (0x0B01) */ 2495 struct i40e_aqc_remove_udp_tunnel { 2496 u8 reserved[2]; 2497 u8 index; /* 0 to 15 */ 2498 u8 reserved2[13]; 2499 }; 2500 2501 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2502 2503 struct i40e_aqc_del_udp_tunnel_completion { 2504 __le16 udp_port; 2505 u8 index; /* 0 to 15 */ 2506 u8 multiple_pfs; 2507 u8 total_filters_used; 2508 u8 reserved1[11]; 2509 }; 2510 2511 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2512 2513 struct i40e_aqc_get_set_rss_key { 2514 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) 2515 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2516 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2517 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2518 __le16 vsi_id; 2519 u8 reserved[6]; 2520 __le32 addr_high; 2521 __le32 addr_low; 2522 }; 2523 2524 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2525 2526 struct i40e_aqc_get_set_rss_key_data { 2527 u8 standard_rss_key[0x28]; 2528 u8 extended_hash_key[0xc]; 2529 }; 2530 2531 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2532 2533 struct i40e_aqc_get_set_rss_lut { 2534 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) 2535 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2536 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2537 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2538 __le16 vsi_id; 2539 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2540 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2541 2542 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2543 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2544 __le16 flags; 2545 u8 reserved[4]; 2546 __le32 addr_high; 2547 __le32 addr_low; 2548 }; 2549 2550 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2551 2552 /* tunnel key structure 0x0B10 */ 2553 2554 struct i40e_aqc_tunnel_key_structure { 2555 u8 key1_off; 2556 u8 key2_off; 2557 u8 key1_len; /* 0 to 15 */ 2558 u8 key2_len; /* 0 to 15 */ 2559 u8 flags; 2560 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2561 /* response flags */ 2562 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2563 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2564 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2565 u8 network_key_index; 2566 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2567 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2568 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2569 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2570 u8 reserved[10]; 2571 }; 2572 2573 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2574 2575 /* OEM mode commands (direct 0xFE0x) */ 2576 struct i40e_aqc_oem_param_change { 2577 __le32 param_type; 2578 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2579 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2580 #define I40E_AQ_OEM_PARAM_MAC 2 2581 __le32 param_value1; 2582 __le16 param_value2; 2583 u8 reserved[6]; 2584 }; 2585 2586 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2587 2588 struct i40e_aqc_oem_state_change { 2589 __le32 state; 2590 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2591 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2592 u8 reserved[12]; 2593 }; 2594 2595 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2596 2597 /* Initialize OCSD (0xFE02, direct) */ 2598 struct i40e_aqc_opc_oem_ocsd_initialize { 2599 u8 type_status; 2600 u8 reserved1[3]; 2601 __le32 ocsd_memory_block_addr_high; 2602 __le32 ocsd_memory_block_addr_low; 2603 __le32 requested_update_interval; 2604 }; 2605 2606 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2607 2608 /* Initialize OCBB (0xFE03, direct) */ 2609 struct i40e_aqc_opc_oem_ocbb_initialize { 2610 u8 type_status; 2611 u8 reserved1[3]; 2612 __le32 ocbb_memory_block_addr_high; 2613 __le32 ocbb_memory_block_addr_low; 2614 u8 reserved2[4]; 2615 }; 2616 2617 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2618 2619 /* debug commands */ 2620 2621 /* get device id (0xFF00) uses the generic structure */ 2622 2623 /* set test more (0xFF01, internal) */ 2624 2625 struct i40e_acq_set_test_mode { 2626 u8 mode; 2627 #define I40E_AQ_TEST_PARTIAL 0 2628 #define I40E_AQ_TEST_FULL 1 2629 #define I40E_AQ_TEST_NVM 2 2630 u8 reserved[3]; 2631 u8 command; 2632 #define I40E_AQ_TEST_OPEN 0 2633 #define I40E_AQ_TEST_CLOSE 1 2634 #define I40E_AQ_TEST_INC 2 2635 u8 reserved2[3]; 2636 __le32 address_high; 2637 __le32 address_low; 2638 }; 2639 2640 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2641 2642 /* Debug Read Register command (0xFF03) 2643 * Debug Write Register command (0xFF04) 2644 */ 2645 struct i40e_aqc_debug_reg_read_write { 2646 __le32 reserved; 2647 __le32 address; 2648 __le32 value_high; 2649 __le32 value_low; 2650 }; 2651 2652 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2653 2654 /* Scatter/gather Reg Read (indirect 0xFF05) 2655 * Scatter/gather Reg Write (indirect 0xFF06) 2656 */ 2657 2658 /* i40e_aq_desc is used for the command */ 2659 struct i40e_aqc_debug_reg_sg_element_data { 2660 __le32 address; 2661 __le32 value; 2662 }; 2663 2664 /* Debug Modify register (direct 0xFF07) */ 2665 struct i40e_aqc_debug_modify_reg { 2666 __le32 address; 2667 __le32 value; 2668 __le32 clear_mask; 2669 __le32 set_mask; 2670 }; 2671 2672 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2673 2674 /* dump internal data (0xFF08, indirect) */ 2675 2676 #define I40E_AQ_CLUSTER_ID_AUX 0 2677 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2678 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2679 #define I40E_AQ_CLUSTER_ID_HMC 3 2680 #define I40E_AQ_CLUSTER_ID_MAC0 4 2681 #define I40E_AQ_CLUSTER_ID_MAC1 5 2682 #define I40E_AQ_CLUSTER_ID_MAC2 6 2683 #define I40E_AQ_CLUSTER_ID_MAC3 7 2684 #define I40E_AQ_CLUSTER_ID_DCB 8 2685 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2686 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2687 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2688 2689 struct i40e_aqc_debug_dump_internals { 2690 u8 cluster_id; 2691 u8 table_id; 2692 __le16 data_size; 2693 __le32 idx; 2694 __le32 address_high; 2695 __le32 address_low; 2696 }; 2697 2698 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2699 2700 struct i40e_aqc_debug_modify_internals { 2701 u8 cluster_id; 2702 u8 cluster_specific_params[7]; 2703 __le32 address_high; 2704 __le32 address_low; 2705 }; 2706 2707 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2708 2709 #endif /* _I40E_ADMINQ_CMD_H_ */ 2710