1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_ADMINQ_CMD_H_ 28 #define _I40E_ADMINQ_CMD_H_ 29 30 /* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36 #define I40E_FW_API_VERSION_MAJOR 0x0001 37 #define I40E_FW_API_VERSION_MINOR 0x0005 38 39 struct i40e_aq_desc { 40 __le16 flags; 41 __le16 opcode; 42 __le16 datalen; 43 __le16 retval; 44 __le32 cookie_high; 45 __le32 cookie_low; 46 union { 47 struct { 48 __le32 param0; 49 __le32 param1; 50 __le32 param2; 51 __le32 param3; 52 } internal; 53 struct { 54 __le32 param0; 55 __le32 param1; 56 __le32 addr_high; 57 __le32 addr_low; 58 } external; 59 u8 raw[16]; 60 } params; 61 }; 62 63 /* Flags sub-structure 64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 66 */ 67 68 /* command flags and offsets*/ 69 #define I40E_AQ_FLAG_DD_SHIFT 0 70 #define I40E_AQ_FLAG_CMP_SHIFT 1 71 #define I40E_AQ_FLAG_ERR_SHIFT 2 72 #define I40E_AQ_FLAG_VFE_SHIFT 3 73 #define I40E_AQ_FLAG_LB_SHIFT 9 74 #define I40E_AQ_FLAG_RD_SHIFT 10 75 #define I40E_AQ_FLAG_VFC_SHIFT 11 76 #define I40E_AQ_FLAG_BUF_SHIFT 12 77 #define I40E_AQ_FLAG_SI_SHIFT 13 78 #define I40E_AQ_FLAG_EI_SHIFT 14 79 #define I40E_AQ_FLAG_FE_SHIFT 15 80 81 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 82 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 83 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 84 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 85 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 86 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 87 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 88 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 89 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 90 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 91 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 92 93 /* error codes */ 94 enum i40e_admin_queue_err { 95 I40E_AQ_RC_OK = 0, /* success */ 96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 97 I40E_AQ_RC_ENOENT = 2, /* No such element */ 98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 100 I40E_AQ_RC_EIO = 5, /* I/O error */ 101 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 103 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 105 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 106 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 108 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 117 I40E_AQ_RC_EFBIG = 22, /* File too large */ 118 }; 119 120 /* Admin Queue command opcodes */ 121 enum i40e_admin_queue_opc { 122 /* aq commands */ 123 i40e_aqc_opc_get_version = 0x0001, 124 i40e_aqc_opc_driver_version = 0x0002, 125 i40e_aqc_opc_queue_shutdown = 0x0003, 126 i40e_aqc_opc_set_pf_context = 0x0004, 127 128 /* resource ownership */ 129 i40e_aqc_opc_request_resource = 0x0008, 130 i40e_aqc_opc_release_resource = 0x0009, 131 132 i40e_aqc_opc_list_func_capabilities = 0x000A, 133 i40e_aqc_opc_list_dev_capabilities = 0x000B, 134 135 /* LAA */ 136 i40e_aqc_opc_mac_address_read = 0x0107, 137 i40e_aqc_opc_mac_address_write = 0x0108, 138 139 /* PXE */ 140 i40e_aqc_opc_clear_pxe_mode = 0x0110, 141 142 /* internal switch commands */ 143 i40e_aqc_opc_get_switch_config = 0x0200, 144 i40e_aqc_opc_add_statistics = 0x0201, 145 i40e_aqc_opc_remove_statistics = 0x0202, 146 i40e_aqc_opc_set_port_parameters = 0x0203, 147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 148 i40e_aqc_opc_set_switch_config = 0x0205, 149 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 150 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 151 152 i40e_aqc_opc_add_vsi = 0x0210, 153 i40e_aqc_opc_update_vsi_parameters = 0x0211, 154 i40e_aqc_opc_get_vsi_parameters = 0x0212, 155 156 i40e_aqc_opc_add_pv = 0x0220, 157 i40e_aqc_opc_update_pv_parameters = 0x0221, 158 i40e_aqc_opc_get_pv_parameters = 0x0222, 159 160 i40e_aqc_opc_add_veb = 0x0230, 161 i40e_aqc_opc_update_veb_parameters = 0x0231, 162 i40e_aqc_opc_get_veb_parameters = 0x0232, 163 164 i40e_aqc_opc_delete_element = 0x0243, 165 166 i40e_aqc_opc_add_macvlan = 0x0250, 167 i40e_aqc_opc_remove_macvlan = 0x0251, 168 i40e_aqc_opc_add_vlan = 0x0252, 169 i40e_aqc_opc_remove_vlan = 0x0253, 170 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 171 i40e_aqc_opc_add_tag = 0x0255, 172 i40e_aqc_opc_remove_tag = 0x0256, 173 i40e_aqc_opc_add_multicast_etag = 0x0257, 174 i40e_aqc_opc_remove_multicast_etag = 0x0258, 175 i40e_aqc_opc_update_tag = 0x0259, 176 i40e_aqc_opc_add_control_packet_filter = 0x025A, 177 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 178 i40e_aqc_opc_add_cloud_filters = 0x025C, 179 i40e_aqc_opc_remove_cloud_filters = 0x025D, 180 181 i40e_aqc_opc_add_mirror_rule = 0x0260, 182 i40e_aqc_opc_delete_mirror_rule = 0x0261, 183 184 /* DCB commands */ 185 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 186 i40e_aqc_opc_dcb_updated = 0x0302, 187 188 /* TX scheduler */ 189 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 190 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 191 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 192 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 193 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 194 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 195 196 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 197 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 198 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 199 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 200 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 201 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 202 i40e_aqc_opc_query_port_ets_config = 0x0419, 203 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 204 i40e_aqc_opc_suspend_port_tx = 0x041B, 205 i40e_aqc_opc_resume_port_tx = 0x041C, 206 i40e_aqc_opc_configure_partition_bw = 0x041D, 207 208 /* phy commands*/ 209 i40e_aqc_opc_get_phy_abilities = 0x0600, 210 i40e_aqc_opc_set_phy_config = 0x0601, 211 i40e_aqc_opc_set_mac_config = 0x0603, 212 i40e_aqc_opc_set_link_restart_an = 0x0605, 213 i40e_aqc_opc_get_link_status = 0x0607, 214 i40e_aqc_opc_set_phy_int_mask = 0x0613, 215 i40e_aqc_opc_get_local_advt_reg = 0x0614, 216 i40e_aqc_opc_set_local_advt_reg = 0x0615, 217 i40e_aqc_opc_get_partner_advt = 0x0616, 218 i40e_aqc_opc_set_lb_modes = 0x0618, 219 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 220 i40e_aqc_opc_set_phy_debug = 0x0622, 221 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 222 i40e_aqc_opc_run_phy_activity = 0x0626, 223 224 /* NVM commands */ 225 i40e_aqc_opc_nvm_read = 0x0701, 226 i40e_aqc_opc_nvm_erase = 0x0702, 227 i40e_aqc_opc_nvm_update = 0x0703, 228 i40e_aqc_opc_nvm_config_read = 0x0704, 229 i40e_aqc_opc_nvm_config_write = 0x0705, 230 i40e_aqc_opc_oem_post_update = 0x0720, 231 i40e_aqc_opc_thermal_sensor = 0x0721, 232 233 /* virtualization commands */ 234 i40e_aqc_opc_send_msg_to_pf = 0x0801, 235 i40e_aqc_opc_send_msg_to_vf = 0x0802, 236 i40e_aqc_opc_send_msg_to_peer = 0x0803, 237 238 /* alternate structure */ 239 i40e_aqc_opc_alternate_write = 0x0900, 240 i40e_aqc_opc_alternate_write_indirect = 0x0901, 241 i40e_aqc_opc_alternate_read = 0x0902, 242 i40e_aqc_opc_alternate_read_indirect = 0x0903, 243 i40e_aqc_opc_alternate_write_done = 0x0904, 244 i40e_aqc_opc_alternate_set_mode = 0x0905, 245 i40e_aqc_opc_alternate_clear_port = 0x0906, 246 247 /* LLDP commands */ 248 i40e_aqc_opc_lldp_get_mib = 0x0A00, 249 i40e_aqc_opc_lldp_update_mib = 0x0A01, 250 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 251 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 252 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 253 i40e_aqc_opc_lldp_stop = 0x0A05, 254 i40e_aqc_opc_lldp_start = 0x0A06, 255 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 256 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 257 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 258 259 /* Tunnel commands */ 260 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 261 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 262 i40e_aqc_opc_set_rss_key = 0x0B02, 263 i40e_aqc_opc_set_rss_lut = 0x0B03, 264 i40e_aqc_opc_get_rss_key = 0x0B04, 265 i40e_aqc_opc_get_rss_lut = 0x0B05, 266 267 /* Async Events */ 268 i40e_aqc_opc_event_lan_overflow = 0x1001, 269 270 /* OEM commands */ 271 i40e_aqc_opc_oem_parameter_change = 0xFE00, 272 i40e_aqc_opc_oem_device_status_change = 0xFE01, 273 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 274 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 275 276 /* debug commands */ 277 i40e_aqc_opc_debug_read_reg = 0xFF03, 278 i40e_aqc_opc_debug_write_reg = 0xFF04, 279 i40e_aqc_opc_debug_modify_reg = 0xFF07, 280 i40e_aqc_opc_debug_dump_internals = 0xFF08, 281 }; 282 283 /* command structures and indirect data structures */ 284 285 /* Structure naming conventions: 286 * - no suffix for direct command descriptor structures 287 * - _data for indirect sent data 288 * - _resp for indirect return data (data which is both will use _data) 289 * - _completion for direct return data 290 * - _element_ for repeated elements (may also be _data or _resp) 291 * 292 * Command structures are expected to overlay the params.raw member of the basic 293 * descriptor, and as such cannot exceed 16 bytes in length. 294 */ 295 296 /* This macro is used to generate a compilation error if a structure 297 * is not exactly the correct length. It gives a divide by zero error if the 298 * structure is not of the correct size, otherwise it creates an enum that is 299 * never used. 300 */ 301 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 302 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 303 304 /* This macro is used extensively to ensure that command structures are 16 305 * bytes in length as they have to map to the raw array of that size. 306 */ 307 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 308 309 /* internal (0x00XX) commands */ 310 311 /* Get version (direct 0x0001) */ 312 struct i40e_aqc_get_version { 313 __le32 rom_ver; 314 __le32 fw_build; 315 __le16 fw_major; 316 __le16 fw_minor; 317 __le16 api_major; 318 __le16 api_minor; 319 }; 320 321 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 322 323 /* Send driver version (indirect 0x0002) */ 324 struct i40e_aqc_driver_version { 325 u8 driver_major_ver; 326 u8 driver_minor_ver; 327 u8 driver_build_ver; 328 u8 driver_subbuild_ver; 329 u8 reserved[4]; 330 __le32 address_high; 331 __le32 address_low; 332 }; 333 334 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 335 336 /* Queue Shutdown (direct 0x0003) */ 337 struct i40e_aqc_queue_shutdown { 338 __le32 driver_unloading; 339 #define I40E_AQ_DRIVER_UNLOADING 0x1 340 u8 reserved[12]; 341 }; 342 343 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 344 345 /* Set PF context (0x0004, direct) */ 346 struct i40e_aqc_set_pf_context { 347 u8 pf_id; 348 u8 reserved[15]; 349 }; 350 351 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 352 353 /* Request resource ownership (direct 0x0008) 354 * Release resource ownership (direct 0x0009) 355 */ 356 #define I40E_AQ_RESOURCE_NVM 1 357 #define I40E_AQ_RESOURCE_SDP 2 358 #define I40E_AQ_RESOURCE_ACCESS_READ 1 359 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 360 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 361 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 362 363 struct i40e_aqc_request_resource { 364 __le16 resource_id; 365 __le16 access_type; 366 __le32 timeout; 367 __le32 resource_number; 368 u8 reserved[4]; 369 }; 370 371 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 372 373 /* Get function capabilities (indirect 0x000A) 374 * Get device capabilities (indirect 0x000B) 375 */ 376 struct i40e_aqc_list_capabilites { 377 u8 command_flags; 378 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 379 u8 pf_index; 380 u8 reserved[2]; 381 __le32 count; 382 __le32 addr_high; 383 __le32 addr_low; 384 }; 385 386 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 387 388 struct i40e_aqc_list_capabilities_element_resp { 389 __le16 id; 390 u8 major_rev; 391 u8 minor_rev; 392 __le32 number; 393 __le32 logical_id; 394 __le32 phys_id; 395 u8 reserved[16]; 396 }; 397 398 /* list of caps */ 399 400 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 401 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 402 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 403 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 404 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 405 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 406 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 407 #define I40E_AQ_CAP_ID_SRIOV 0x0012 408 #define I40E_AQ_CAP_ID_VF 0x0013 409 #define I40E_AQ_CAP_ID_VMDQ 0x0014 410 #define I40E_AQ_CAP_ID_8021QBG 0x0015 411 #define I40E_AQ_CAP_ID_8021QBR 0x0016 412 #define I40E_AQ_CAP_ID_VSI 0x0017 413 #define I40E_AQ_CAP_ID_DCB 0x0018 414 #define I40E_AQ_CAP_ID_FCOE 0x0021 415 #define I40E_AQ_CAP_ID_ISCSI 0x0022 416 #define I40E_AQ_CAP_ID_RSS 0x0040 417 #define I40E_AQ_CAP_ID_RXQ 0x0041 418 #define I40E_AQ_CAP_ID_TXQ 0x0042 419 #define I40E_AQ_CAP_ID_MSIX 0x0043 420 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 421 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 422 #define I40E_AQ_CAP_ID_1588 0x0046 423 #define I40E_AQ_CAP_ID_IWARP 0x0051 424 #define I40E_AQ_CAP_ID_LED 0x0061 425 #define I40E_AQ_CAP_ID_SDP 0x0062 426 #define I40E_AQ_CAP_ID_MDIO 0x0063 427 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 428 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 429 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 430 #define I40E_AQ_CAP_ID_CEM 0x00F2 431 432 /* Set CPPM Configuration (direct 0x0103) */ 433 struct i40e_aqc_cppm_configuration { 434 __le16 command_flags; 435 #define I40E_AQ_CPPM_EN_LTRC 0x0800 436 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 437 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 438 #define I40E_AQ_CPPM_EN_HPTC 0x4000 439 #define I40E_AQ_CPPM_EN_DMARC 0x8000 440 __le16 ttlx; 441 __le32 dmacr; 442 __le16 dmcth; 443 u8 hptc; 444 u8 reserved; 445 __le32 pfltrc; 446 }; 447 448 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 449 450 /* Set ARP Proxy command / response (indirect 0x0104) */ 451 struct i40e_aqc_arp_proxy_data { 452 __le16 command_flags; 453 #define I40E_AQ_ARP_INIT_IPV4 0x0008 454 #define I40E_AQ_ARP_UNSUP_CTL 0x0010 455 #define I40E_AQ_ARP_ENA 0x0020 456 #define I40E_AQ_ARP_ADD_IPV4 0x0040 457 #define I40E_AQ_ARP_DEL_IPV4 0x0080 458 __le16 table_id; 459 __le32 pfpm_proxyfc; 460 __le32 ip_addr; 461 u8 mac_addr[6]; 462 u8 reserved[2]; 463 }; 464 465 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 466 467 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 468 struct i40e_aqc_ns_proxy_data { 469 __le16 table_idx_mac_addr_0; 470 __le16 table_idx_mac_addr_1; 471 __le16 table_idx_ipv6_0; 472 __le16 table_idx_ipv6_1; 473 __le16 control; 474 #define I40E_AQ_NS_PROXY_ADD_0 0x0100 475 #define I40E_AQ_NS_PROXY_DEL_0 0x0200 476 #define I40E_AQ_NS_PROXY_ADD_1 0x0400 477 #define I40E_AQ_NS_PROXY_DEL_1 0x0800 478 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 479 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 480 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 481 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 482 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 483 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 484 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 485 u8 mac_addr_0[6]; 486 u8 mac_addr_1[6]; 487 u8 local_mac_addr[6]; 488 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 489 u8 ipv6_addr_1[16]; 490 }; 491 492 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 493 494 /* Manage LAA Command (0x0106) - obsolete */ 495 struct i40e_aqc_mng_laa { 496 __le16 command_flags; 497 #define I40E_AQ_LAA_FLAG_WR 0x8000 498 u8 reserved[2]; 499 __le32 sal; 500 __le16 sah; 501 u8 reserved2[6]; 502 }; 503 504 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 505 506 /* Manage MAC Address Read Command (indirect 0x0107) */ 507 struct i40e_aqc_mac_address_read { 508 __le16 command_flags; 509 #define I40E_AQC_LAN_ADDR_VALID 0x10 510 #define I40E_AQC_SAN_ADDR_VALID 0x20 511 #define I40E_AQC_PORT_ADDR_VALID 0x40 512 #define I40E_AQC_WOL_ADDR_VALID 0x80 513 #define I40E_AQC_MC_MAG_EN_VALID 0x100 514 #define I40E_AQC_ADDR_VALID_MASK 0x1F0 515 u8 reserved[6]; 516 __le32 addr_high; 517 __le32 addr_low; 518 }; 519 520 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 521 522 struct i40e_aqc_mac_address_read_data { 523 u8 pf_lan_mac[6]; 524 u8 pf_san_mac[6]; 525 u8 port_mac[6]; 526 u8 pf_wol_mac[6]; 527 }; 528 529 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 530 531 /* Manage MAC Address Write Command (0x0108) */ 532 struct i40e_aqc_mac_address_write { 533 __le16 command_flags; 534 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 535 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 536 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 537 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 538 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 539 540 __le16 mac_sah; 541 __le32 mac_sal; 542 u8 reserved[8]; 543 }; 544 545 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 546 547 /* PXE commands (0x011x) */ 548 549 /* Clear PXE Command and response (direct 0x0110) */ 550 struct i40e_aqc_clear_pxe { 551 u8 rx_cnt; 552 u8 reserved[15]; 553 }; 554 555 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 556 557 /* Switch configuration commands (0x02xx) */ 558 559 /* Used by many indirect commands that only pass an seid and a buffer in the 560 * command 561 */ 562 struct i40e_aqc_switch_seid { 563 __le16 seid; 564 u8 reserved[6]; 565 __le32 addr_high; 566 __le32 addr_low; 567 }; 568 569 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 570 571 /* Get Switch Configuration command (indirect 0x0200) 572 * uses i40e_aqc_switch_seid for the descriptor 573 */ 574 struct i40e_aqc_get_switch_config_header_resp { 575 __le16 num_reported; 576 __le16 num_total; 577 u8 reserved[12]; 578 }; 579 580 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 581 582 struct i40e_aqc_switch_config_element_resp { 583 u8 element_type; 584 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 585 #define I40E_AQ_SW_ELEM_TYPE_PF 2 586 #define I40E_AQ_SW_ELEM_TYPE_VF 3 587 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 588 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 589 #define I40E_AQ_SW_ELEM_TYPE_PV 16 590 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 591 #define I40E_AQ_SW_ELEM_TYPE_PA 18 592 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 593 u8 revision; 594 #define I40E_AQ_SW_ELEM_REV_1 1 595 __le16 seid; 596 __le16 uplink_seid; 597 __le16 downlink_seid; 598 u8 reserved[3]; 599 u8 connection_type; 600 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 601 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 602 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 603 __le16 scheduler_id; 604 __le16 element_info; 605 }; 606 607 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 608 609 /* Get Switch Configuration (indirect 0x0200) 610 * an array of elements are returned in the response buffer 611 * the first in the array is the header, remainder are elements 612 */ 613 struct i40e_aqc_get_switch_config_resp { 614 struct i40e_aqc_get_switch_config_header_resp header; 615 struct i40e_aqc_switch_config_element_resp element[1]; 616 }; 617 618 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 619 620 /* Add Statistics (direct 0x0201) 621 * Remove Statistics (direct 0x0202) 622 */ 623 struct i40e_aqc_add_remove_statistics { 624 __le16 seid; 625 __le16 vlan; 626 __le16 stat_index; 627 u8 reserved[10]; 628 }; 629 630 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 631 632 /* Set Port Parameters command (direct 0x0203) */ 633 struct i40e_aqc_set_port_parameters { 634 __le16 command_flags; 635 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 636 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 637 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 638 __le16 bad_frame_vsi; 639 __le16 default_seid; /* reserved for command */ 640 u8 reserved[10]; 641 }; 642 643 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 644 645 /* Get Switch Resource Allocation (indirect 0x0204) */ 646 struct i40e_aqc_get_switch_resource_alloc { 647 u8 num_entries; /* reserved for command */ 648 u8 reserved[7]; 649 __le32 addr_high; 650 __le32 addr_low; 651 }; 652 653 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 654 655 /* expect an array of these structs in the response buffer */ 656 struct i40e_aqc_switch_resource_alloc_element_resp { 657 u8 resource_type; 658 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 659 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 660 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 661 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 662 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 663 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 664 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 665 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 666 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 667 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 668 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 669 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 670 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 671 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 672 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 673 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 674 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 675 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 676 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 677 u8 reserved1; 678 __le16 guaranteed; 679 __le16 total; 680 __le16 used; 681 __le16 total_unalloced; 682 u8 reserved2[6]; 683 }; 684 685 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 686 687 /* Set Switch Configuration (direct 0x0205) */ 688 struct i40e_aqc_set_switch_config { 689 __le16 flags; 690 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 691 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 692 __le16 valid_flags; 693 u8 reserved[12]; 694 }; 695 696 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 697 698 /* Read Receive control registers (direct 0x0206) 699 * Write Receive control registers (direct 0x0207) 700 * used for accessing Rx control registers that can be 701 * slow and need special handling when under high Rx load 702 */ 703 struct i40e_aqc_rx_ctl_reg_read_write { 704 __le32 reserved1; 705 __le32 address; 706 __le32 reserved2; 707 __le32 value; 708 }; 709 710 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 711 712 /* Add VSI (indirect 0x0210) 713 * this indirect command uses struct i40e_aqc_vsi_properties_data 714 * as the indirect buffer (128 bytes) 715 * 716 * Update VSI (indirect 0x211) 717 * uses the same data structure as Add VSI 718 * 719 * Get VSI (indirect 0x0212) 720 * uses the same completion and data structure as Add VSI 721 */ 722 struct i40e_aqc_add_get_update_vsi { 723 __le16 uplink_seid; 724 u8 connection_type; 725 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 726 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 727 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 728 u8 reserved1; 729 u8 vf_id; 730 u8 reserved2; 731 __le16 vsi_flags; 732 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 733 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 734 #define I40E_AQ_VSI_TYPE_VF 0x0 735 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 736 #define I40E_AQ_VSI_TYPE_PF 0x2 737 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 738 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 739 __le32 addr_high; 740 __le32 addr_low; 741 }; 742 743 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 744 745 struct i40e_aqc_add_get_update_vsi_completion { 746 __le16 seid; 747 __le16 vsi_number; 748 __le16 vsi_used; 749 __le16 vsi_free; 750 __le32 addr_high; 751 __le32 addr_low; 752 }; 753 754 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 755 756 struct i40e_aqc_vsi_properties_data { 757 /* first 96 byte are written by SW */ 758 __le16 valid_sections; 759 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 760 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 761 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 762 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 763 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 764 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 765 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 766 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 767 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 768 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 769 /* switch section */ 770 __le16 switch_id; /* 12bit id combined with flags below */ 771 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 772 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 773 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 774 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 775 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 776 u8 sw_reserved[2]; 777 /* security section */ 778 u8 sec_flags; 779 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 780 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 781 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 782 u8 sec_reserved; 783 /* VLAN section */ 784 __le16 pvid; /* VLANS include priority bits */ 785 __le16 fcoe_pvid; 786 u8 port_vlan_flags; 787 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 788 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 789 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 790 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 791 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 792 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 793 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 794 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 795 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 796 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 797 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 798 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 799 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 800 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 801 u8 pvlan_reserved[3]; 802 /* ingress egress up sections */ 803 __le32 ingress_table; /* bitmap, 3 bits per up */ 804 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 805 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 806 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 807 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 808 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 809 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 810 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 811 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 812 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 813 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 814 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 815 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 816 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 817 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 818 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 819 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 820 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 821 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 822 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 823 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 824 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 825 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 826 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 827 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 828 __le32 egress_table; /* same defines as for ingress table */ 829 /* cascaded PV section */ 830 __le16 cas_pv_tag; 831 u8 cas_pv_flags; 832 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 833 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 834 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 835 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 836 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 837 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 838 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 839 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 840 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 841 u8 cas_pv_reserved; 842 /* queue mapping section */ 843 __le16 mapping_flags; 844 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 845 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 846 __le16 queue_mapping[16]; 847 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 848 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 849 __le16 tc_mapping[8]; 850 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 851 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 852 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 853 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 854 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 855 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 856 /* queueing option section */ 857 u8 queueing_opt_flags; 858 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 859 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 860 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 861 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 862 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 863 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 864 u8 queueing_opt_reserved[3]; 865 /* scheduler section */ 866 u8 up_enable_bits; 867 u8 sched_reserved; 868 /* outer up section */ 869 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 870 u8 cmd_reserved[8]; 871 /* last 32 bytes are written by FW */ 872 __le16 qs_handle[8]; 873 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 874 __le16 stat_counter_idx; 875 __le16 sched_id; 876 u8 resp_reserved[12]; 877 }; 878 879 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 880 881 /* Add Port Virtualizer (direct 0x0220) 882 * also used for update PV (direct 0x0221) but only flags are used 883 * (IS_CTRL_PORT only works on add PV) 884 */ 885 struct i40e_aqc_add_update_pv { 886 __le16 command_flags; 887 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 888 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 889 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 890 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 891 __le16 uplink_seid; 892 __le16 connected_seid; 893 u8 reserved[10]; 894 }; 895 896 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 897 898 struct i40e_aqc_add_update_pv_completion { 899 /* reserved for update; for add also encodes error if rc == ENOSPC */ 900 __le16 pv_seid; 901 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 902 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 903 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 904 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 905 u8 reserved[14]; 906 }; 907 908 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 909 910 /* Get PV Params (direct 0x0222) 911 * uses i40e_aqc_switch_seid for the descriptor 912 */ 913 914 struct i40e_aqc_get_pv_params_completion { 915 __le16 seid; 916 __le16 default_stag; 917 __le16 pv_flags; /* same flags as add_pv */ 918 #define I40E_AQC_GET_PV_PV_TYPE 0x1 919 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 920 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 921 u8 reserved[8]; 922 __le16 default_port_seid; 923 }; 924 925 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 926 927 /* Add VEB (direct 0x0230) */ 928 struct i40e_aqc_add_veb { 929 __le16 uplink_seid; 930 __le16 downlink_seid; 931 __le16 veb_flags; 932 #define I40E_AQC_ADD_VEB_FLOATING 0x1 933 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 934 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 935 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 936 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 937 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 938 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 939 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 940 u8 enable_tcs; 941 u8 reserved[9]; 942 }; 943 944 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 945 946 struct i40e_aqc_add_veb_completion { 947 u8 reserved[6]; 948 __le16 switch_seid; 949 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 950 __le16 veb_seid; 951 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 952 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 953 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 954 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 955 __le16 statistic_index; 956 __le16 vebs_used; 957 __le16 vebs_free; 958 }; 959 960 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 961 962 /* Get VEB Parameters (direct 0x0232) 963 * uses i40e_aqc_switch_seid for the descriptor 964 */ 965 struct i40e_aqc_get_veb_parameters_completion { 966 __le16 seid; 967 __le16 switch_id; 968 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 969 __le16 statistic_index; 970 __le16 vebs_used; 971 __le16 vebs_free; 972 u8 reserved[4]; 973 }; 974 975 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 976 977 /* Delete Element (direct 0x0243) 978 * uses the generic i40e_aqc_switch_seid 979 */ 980 981 /* Add MAC-VLAN (indirect 0x0250) */ 982 983 /* used for the command for most vlan commands */ 984 struct i40e_aqc_macvlan { 985 __le16 num_addresses; 986 __le16 seid[3]; 987 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 988 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 989 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 990 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 991 __le32 addr_high; 992 __le32 addr_low; 993 }; 994 995 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 996 997 /* indirect data for command and response */ 998 struct i40e_aqc_add_macvlan_element_data { 999 u8 mac_addr[6]; 1000 __le16 vlan_tag; 1001 __le16 flags; 1002 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1003 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1004 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1005 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1006 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1007 __le16 queue_number; 1008 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1009 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1010 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1011 /* response section */ 1012 u8 match_method; 1013 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1014 #define I40E_AQC_MM_HASH_MATCH 0x02 1015 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1016 u8 reserved1[3]; 1017 }; 1018 1019 struct i40e_aqc_add_remove_macvlan_completion { 1020 __le16 perfect_mac_used; 1021 __le16 perfect_mac_free; 1022 __le16 unicast_hash_free; 1023 __le16 multicast_hash_free; 1024 __le32 addr_high; 1025 __le32 addr_low; 1026 }; 1027 1028 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1029 1030 /* Remove MAC-VLAN (indirect 0x0251) 1031 * uses i40e_aqc_macvlan for the descriptor 1032 * data points to an array of num_addresses of elements 1033 */ 1034 1035 struct i40e_aqc_remove_macvlan_element_data { 1036 u8 mac_addr[6]; 1037 __le16 vlan_tag; 1038 u8 flags; 1039 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1040 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1041 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1042 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1043 u8 reserved[3]; 1044 /* reply section */ 1045 u8 error_code; 1046 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1047 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1048 u8 reply_reserved[3]; 1049 }; 1050 1051 /* Add VLAN (indirect 0x0252) 1052 * Remove VLAN (indirect 0x0253) 1053 * use the generic i40e_aqc_macvlan for the command 1054 */ 1055 struct i40e_aqc_add_remove_vlan_element_data { 1056 __le16 vlan_tag; 1057 u8 vlan_flags; 1058 /* flags for add VLAN */ 1059 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1060 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1061 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1062 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1063 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1064 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1065 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1066 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1067 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1068 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1069 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1070 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1071 /* flags for remove VLAN */ 1072 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1073 u8 reserved; 1074 u8 result; 1075 /* flags for add VLAN */ 1076 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1077 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1078 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1079 /* flags for remove VLAN */ 1080 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1081 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1082 u8 reserved1[3]; 1083 }; 1084 1085 struct i40e_aqc_add_remove_vlan_completion { 1086 u8 reserved[4]; 1087 __le16 vlans_used; 1088 __le16 vlans_free; 1089 __le32 addr_high; 1090 __le32 addr_low; 1091 }; 1092 1093 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1094 struct i40e_aqc_set_vsi_promiscuous_modes { 1095 __le16 promiscuous_flags; 1096 __le16 valid_flags; 1097 /* flags used for both fields above */ 1098 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1099 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1100 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1101 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1102 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1103 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1104 __le16 seid; 1105 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1106 __le16 vlan_tag; 1107 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1108 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1109 u8 reserved[8]; 1110 }; 1111 1112 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1113 1114 /* Add S/E-tag command (direct 0x0255) 1115 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1116 */ 1117 struct i40e_aqc_add_tag { 1118 __le16 flags; 1119 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1120 __le16 seid; 1121 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1122 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1123 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1124 __le16 tag; 1125 __le16 queue_number; 1126 u8 reserved[8]; 1127 }; 1128 1129 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1130 1131 struct i40e_aqc_add_remove_tag_completion { 1132 u8 reserved[12]; 1133 __le16 tags_used; 1134 __le16 tags_free; 1135 }; 1136 1137 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1138 1139 /* Remove S/E-tag command (direct 0x0256) 1140 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1141 */ 1142 struct i40e_aqc_remove_tag { 1143 __le16 seid; 1144 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1145 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1146 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1147 __le16 tag; 1148 u8 reserved[12]; 1149 }; 1150 1151 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1152 1153 /* Add multicast E-Tag (direct 0x0257) 1154 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1155 * and no external data 1156 */ 1157 struct i40e_aqc_add_remove_mcast_etag { 1158 __le16 pv_seid; 1159 __le16 etag; 1160 u8 num_unicast_etags; 1161 u8 reserved[3]; 1162 __le32 addr_high; /* address of array of 2-byte s-tags */ 1163 __le32 addr_low; 1164 }; 1165 1166 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1167 1168 struct i40e_aqc_add_remove_mcast_etag_completion { 1169 u8 reserved[4]; 1170 __le16 mcast_etags_used; 1171 __le16 mcast_etags_free; 1172 __le32 addr_high; 1173 __le32 addr_low; 1174 1175 }; 1176 1177 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1178 1179 /* Update S/E-Tag (direct 0x0259) */ 1180 struct i40e_aqc_update_tag { 1181 __le16 seid; 1182 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1183 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1184 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1185 __le16 old_tag; 1186 __le16 new_tag; 1187 u8 reserved[10]; 1188 }; 1189 1190 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1191 1192 struct i40e_aqc_update_tag_completion { 1193 u8 reserved[12]; 1194 __le16 tags_used; 1195 __le16 tags_free; 1196 }; 1197 1198 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1199 1200 /* Add Control Packet filter (direct 0x025A) 1201 * Remove Control Packet filter (direct 0x025B) 1202 * uses the i40e_aqc_add_oveb_cloud, 1203 * and the generic direct completion structure 1204 */ 1205 struct i40e_aqc_add_remove_control_packet_filter { 1206 u8 mac[6]; 1207 __le16 etype; 1208 __le16 flags; 1209 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1210 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1211 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1212 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1213 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1214 __le16 seid; 1215 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1216 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1217 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1218 __le16 queue; 1219 u8 reserved[2]; 1220 }; 1221 1222 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1223 1224 struct i40e_aqc_add_remove_control_packet_filter_completion { 1225 __le16 mac_etype_used; 1226 __le16 etype_used; 1227 __le16 mac_etype_free; 1228 __le16 etype_free; 1229 u8 reserved[8]; 1230 }; 1231 1232 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1233 1234 /* Add Cloud filters (indirect 0x025C) 1235 * Remove Cloud filters (indirect 0x025D) 1236 * uses the i40e_aqc_add_remove_cloud_filters, 1237 * and the generic indirect completion structure 1238 */ 1239 struct i40e_aqc_add_remove_cloud_filters { 1240 u8 num_filters; 1241 u8 reserved; 1242 __le16 seid; 1243 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1244 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1245 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1246 u8 reserved2[4]; 1247 __le32 addr_high; 1248 __le32 addr_low; 1249 }; 1250 1251 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1252 1253 struct i40e_aqc_add_remove_cloud_filters_element_data { 1254 u8 outer_mac[6]; 1255 u8 inner_mac[6]; 1256 __le16 inner_vlan; 1257 union { 1258 struct { 1259 u8 reserved[12]; 1260 u8 data[4]; 1261 } v4; 1262 struct { 1263 u8 data[16]; 1264 } v6; 1265 } ipaddr; 1266 __le16 flags; 1267 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1268 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1269 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1270 /* 0x0000 reserved */ 1271 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1272 /* 0x0002 reserved */ 1273 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1274 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1275 /* 0x0005 reserved */ 1276 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1277 /* 0x0007 reserved */ 1278 /* 0x0008 reserved */ 1279 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1280 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1281 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1282 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1283 1284 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1285 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1286 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1287 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1288 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1289 1290 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1291 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1292 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1293 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1294 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1295 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1296 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1297 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1298 1299 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1300 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1301 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1302 1303 __le32 tenant_id; 1304 u8 reserved[4]; 1305 __le16 queue_number; 1306 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1307 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1308 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1309 u8 reserved2[14]; 1310 /* response section */ 1311 u8 allocation_result; 1312 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1313 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1314 u8 response_reserved[7]; 1315 }; 1316 1317 struct i40e_aqc_remove_cloud_filters_completion { 1318 __le16 perfect_ovlan_used; 1319 __le16 perfect_ovlan_free; 1320 __le16 vlan_used; 1321 __le16 vlan_free; 1322 __le32 addr_high; 1323 __le32 addr_low; 1324 }; 1325 1326 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1327 1328 /* Add Mirror Rule (indirect or direct 0x0260) 1329 * Delete Mirror Rule (indirect or direct 0x0261) 1330 * note: some rule types (4,5) do not use an external buffer. 1331 * take care to set the flags correctly. 1332 */ 1333 struct i40e_aqc_add_delete_mirror_rule { 1334 __le16 seid; 1335 __le16 rule_type; 1336 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1337 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1338 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1339 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1340 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1341 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1342 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1343 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1344 __le16 num_entries; 1345 __le16 destination; /* VSI for add, rule id for delete */ 1346 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1347 __le32 addr_low; 1348 }; 1349 1350 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1351 1352 struct i40e_aqc_add_delete_mirror_rule_completion { 1353 u8 reserved[2]; 1354 __le16 rule_id; /* only used on add */ 1355 __le16 mirror_rules_used; 1356 __le16 mirror_rules_free; 1357 __le32 addr_high; 1358 __le32 addr_low; 1359 }; 1360 1361 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1362 1363 /* DCB 0x03xx*/ 1364 1365 /* PFC Ignore (direct 0x0301) 1366 * the command and response use the same descriptor structure 1367 */ 1368 struct i40e_aqc_pfc_ignore { 1369 u8 tc_bitmap; 1370 u8 command_flags; /* unused on response */ 1371 #define I40E_AQC_PFC_IGNORE_SET 0x80 1372 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1373 u8 reserved[14]; 1374 }; 1375 1376 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1377 1378 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1379 * with no parameters 1380 */ 1381 1382 /* TX scheduler 0x04xx */ 1383 1384 /* Almost all the indirect commands use 1385 * this generic struct to pass the SEID in param0 1386 */ 1387 struct i40e_aqc_tx_sched_ind { 1388 __le16 vsi_seid; 1389 u8 reserved[6]; 1390 __le32 addr_high; 1391 __le32 addr_low; 1392 }; 1393 1394 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1395 1396 /* Several commands respond with a set of queue set handles */ 1397 struct i40e_aqc_qs_handles_resp { 1398 __le16 qs_handles[8]; 1399 }; 1400 1401 /* Configure VSI BW limits (direct 0x0400) */ 1402 struct i40e_aqc_configure_vsi_bw_limit { 1403 __le16 vsi_seid; 1404 u8 reserved[2]; 1405 __le16 credit; 1406 u8 reserved1[2]; 1407 u8 max_credit; /* 0-3, limit = 2^max */ 1408 u8 reserved2[7]; 1409 }; 1410 1411 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1412 1413 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1414 * responds with i40e_aqc_qs_handles_resp 1415 */ 1416 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1417 u8 tc_valid_bits; 1418 u8 reserved[15]; 1419 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1420 1421 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1422 __le16 tc_bw_max[2]; 1423 u8 reserved1[28]; 1424 }; 1425 1426 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1427 1428 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1429 * responds with i40e_aqc_qs_handles_resp 1430 */ 1431 struct i40e_aqc_configure_vsi_tc_bw_data { 1432 u8 tc_valid_bits; 1433 u8 reserved[3]; 1434 u8 tc_bw_credits[8]; 1435 u8 reserved1[4]; 1436 __le16 qs_handles[8]; 1437 }; 1438 1439 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1440 1441 /* Query vsi bw configuration (indirect 0x0408) */ 1442 struct i40e_aqc_query_vsi_bw_config_resp { 1443 u8 tc_valid_bits; 1444 u8 tc_suspended_bits; 1445 u8 reserved[14]; 1446 __le16 qs_handles[8]; 1447 u8 reserved1[4]; 1448 __le16 port_bw_limit; 1449 u8 reserved2[2]; 1450 u8 max_bw; /* 0-3, limit = 2^max */ 1451 u8 reserved3[23]; 1452 }; 1453 1454 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1455 1456 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1457 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1458 u8 tc_valid_bits; 1459 u8 reserved[3]; 1460 u8 share_credits[8]; 1461 __le16 credits[8]; 1462 1463 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1464 __le16 tc_bw_max[2]; 1465 }; 1466 1467 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1468 1469 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1470 struct i40e_aqc_configure_switching_comp_bw_limit { 1471 __le16 seid; 1472 u8 reserved[2]; 1473 __le16 credit; 1474 u8 reserved1[2]; 1475 u8 max_bw; /* 0-3, limit = 2^max */ 1476 u8 reserved2[7]; 1477 }; 1478 1479 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1480 1481 /* Enable Physical Port ETS (indirect 0x0413) 1482 * Modify Physical Port ETS (indirect 0x0414) 1483 * Disable Physical Port ETS (indirect 0x0415) 1484 */ 1485 struct i40e_aqc_configure_switching_comp_ets_data { 1486 u8 reserved[4]; 1487 u8 tc_valid_bits; 1488 u8 seepage; 1489 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1490 u8 tc_strict_priority_flags; 1491 u8 reserved1[17]; 1492 u8 tc_bw_share_credits[8]; 1493 u8 reserved2[96]; 1494 }; 1495 1496 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1497 1498 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1499 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1500 u8 tc_valid_bits; 1501 u8 reserved[15]; 1502 __le16 tc_bw_credit[8]; 1503 1504 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1505 __le16 tc_bw_max[2]; 1506 u8 reserved1[28]; 1507 }; 1508 1509 I40E_CHECK_STRUCT_LEN(0x40, 1510 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1511 1512 /* Configure Switching Component Bandwidth Allocation per Tc 1513 * (indirect 0x0417) 1514 */ 1515 struct i40e_aqc_configure_switching_comp_bw_config_data { 1516 u8 tc_valid_bits; 1517 u8 reserved[2]; 1518 u8 absolute_credits; /* bool */ 1519 u8 tc_bw_share_credits[8]; 1520 u8 reserved1[20]; 1521 }; 1522 1523 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1524 1525 /* Query Switching Component Configuration (indirect 0x0418) */ 1526 struct i40e_aqc_query_switching_comp_ets_config_resp { 1527 u8 tc_valid_bits; 1528 u8 reserved[35]; 1529 __le16 port_bw_limit; 1530 u8 reserved1[2]; 1531 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1532 u8 reserved2[23]; 1533 }; 1534 1535 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1536 1537 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1538 struct i40e_aqc_query_port_ets_config_resp { 1539 u8 reserved[4]; 1540 u8 tc_valid_bits; 1541 u8 reserved1; 1542 u8 tc_strict_priority_bits; 1543 u8 reserved2; 1544 u8 tc_bw_share_credits[8]; 1545 __le16 tc_bw_limits[8]; 1546 1547 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1548 __le16 tc_bw_max[2]; 1549 u8 reserved3[32]; 1550 }; 1551 1552 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1553 1554 /* Query Switching Component Bandwidth Allocation per Traffic Type 1555 * (indirect 0x041A) 1556 */ 1557 struct i40e_aqc_query_switching_comp_bw_config_resp { 1558 u8 tc_valid_bits; 1559 u8 reserved[2]; 1560 u8 absolute_credits_enable; /* bool */ 1561 u8 tc_bw_share_credits[8]; 1562 __le16 tc_bw_limits[8]; 1563 1564 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1565 __le16 tc_bw_max[2]; 1566 }; 1567 1568 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1569 1570 /* Suspend/resume port TX traffic 1571 * (direct 0x041B and 0x041C) uses the generic SEID struct 1572 */ 1573 1574 /* Configure partition BW 1575 * (indirect 0x041D) 1576 */ 1577 struct i40e_aqc_configure_partition_bw_data { 1578 __le16 pf_valid_bits; 1579 u8 min_bw[16]; /* guaranteed bandwidth */ 1580 u8 max_bw[16]; /* bandwidth limit */ 1581 }; 1582 1583 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1584 1585 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1586 1587 /* set in param0 for get phy abilities to report qualified modules */ 1588 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1589 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1590 1591 enum i40e_aq_phy_type { 1592 I40E_PHY_TYPE_SGMII = 0x0, 1593 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1594 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1595 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1596 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1597 I40E_PHY_TYPE_XAUI = 0x5, 1598 I40E_PHY_TYPE_XFI = 0x6, 1599 I40E_PHY_TYPE_SFI = 0x7, 1600 I40E_PHY_TYPE_XLAUI = 0x8, 1601 I40E_PHY_TYPE_XLPPI = 0x9, 1602 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1603 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1604 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1605 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1606 I40E_PHY_TYPE_100BASE_TX = 0x11, 1607 I40E_PHY_TYPE_1000BASE_T = 0x12, 1608 I40E_PHY_TYPE_10GBASE_T = 0x13, 1609 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1610 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1611 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1612 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1613 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1614 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1615 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1616 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1617 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1618 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1619 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1620 I40E_PHY_TYPE_MAX 1621 }; 1622 1623 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1624 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1625 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1626 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1627 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1628 1629 enum i40e_aq_link_speed { 1630 I40E_LINK_SPEED_UNKNOWN = 0, 1631 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), 1632 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), 1633 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), 1634 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), 1635 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT) 1636 }; 1637 1638 struct i40e_aqc_module_desc { 1639 u8 oui[3]; 1640 u8 reserved1; 1641 u8 part_number[16]; 1642 u8 revision[4]; 1643 u8 reserved2[8]; 1644 }; 1645 1646 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1647 1648 struct i40e_aq_get_phy_abilities_resp { 1649 __le32 phy_type; /* bitmap using the above enum for offsets */ 1650 u8 link_speed; /* bitmap using the above enum bit patterns */ 1651 u8 abilities; 1652 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1653 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1654 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1655 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1656 #define I40E_AQ_PHY_AN_ENABLED 0x10 1657 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1658 __le16 eee_capability; 1659 #define I40E_AQ_EEE_100BASE_TX 0x0002 1660 #define I40E_AQ_EEE_1000BASE_T 0x0004 1661 #define I40E_AQ_EEE_10GBASE_T 0x0008 1662 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1663 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1664 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1665 __le32 eeer_val; 1666 u8 d3_lpan; 1667 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1668 u8 reserved[3]; 1669 u8 phy_id[4]; 1670 u8 module_type[3]; 1671 u8 qualified_module_count; 1672 #define I40E_AQ_PHY_MAX_QMS 16 1673 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1674 }; 1675 1676 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1677 1678 /* Set PHY Config (direct 0x0601) */ 1679 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1680 __le32 phy_type; 1681 u8 link_speed; 1682 u8 abilities; 1683 /* bits 0-2 use the values from get_phy_abilities_resp */ 1684 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1685 #define I40E_AQ_PHY_ENABLE_AN 0x10 1686 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1687 __le16 eee_capability; 1688 __le32 eeer; 1689 u8 low_power_ctrl; 1690 u8 reserved[3]; 1691 }; 1692 1693 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1694 1695 /* Set MAC Config command data structure (direct 0x0603) */ 1696 struct i40e_aq_set_mac_config { 1697 __le16 max_frame_size; 1698 u8 params; 1699 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1700 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1701 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1702 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1703 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1704 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1705 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1706 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1707 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1708 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1709 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1710 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1711 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1712 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1713 u8 tx_timer_priority; /* bitmap */ 1714 __le16 tx_timer_value; 1715 __le16 fc_refresh_threshold; 1716 u8 reserved[8]; 1717 }; 1718 1719 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1720 1721 /* Restart Auto-Negotiation (direct 0x605) */ 1722 struct i40e_aqc_set_link_restart_an { 1723 u8 command; 1724 #define I40E_AQ_PHY_RESTART_AN 0x02 1725 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1726 u8 reserved[15]; 1727 }; 1728 1729 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1730 1731 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1732 struct i40e_aqc_get_link_status { 1733 __le16 command_flags; /* only field set on command */ 1734 #define I40E_AQ_LSE_MASK 0x3 1735 #define I40E_AQ_LSE_NOP 0x0 1736 #define I40E_AQ_LSE_DISABLE 0x2 1737 #define I40E_AQ_LSE_ENABLE 0x3 1738 /* only response uses this flag */ 1739 #define I40E_AQ_LSE_IS_ENABLED 0x1 1740 u8 phy_type; /* i40e_aq_phy_type */ 1741 u8 link_speed; /* i40e_aq_link_speed */ 1742 u8 link_info; 1743 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1744 #define I40E_AQ_LINK_UP_FUNCTION 0x01 1745 #define I40E_AQ_LINK_FAULT 0x02 1746 #define I40E_AQ_LINK_FAULT_TX 0x04 1747 #define I40E_AQ_LINK_FAULT_RX 0x08 1748 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1749 #define I40E_AQ_LINK_UP_PORT 0x20 1750 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1751 #define I40E_AQ_SIGNAL_DETECT 0x80 1752 u8 an_info; 1753 #define I40E_AQ_AN_COMPLETED 0x01 1754 #define I40E_AQ_LP_AN_ABILITY 0x02 1755 #define I40E_AQ_PD_FAULT 0x04 1756 #define I40E_AQ_FEC_EN 0x08 1757 #define I40E_AQ_PHY_LOW_POWER 0x10 1758 #define I40E_AQ_LINK_PAUSE_TX 0x20 1759 #define I40E_AQ_LINK_PAUSE_RX 0x40 1760 #define I40E_AQ_QUALIFIED_MODULE 0x80 1761 u8 ext_info; 1762 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1763 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1764 #define I40E_AQ_LINK_TX_SHIFT 0x02 1765 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1766 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1767 #define I40E_AQ_LINK_TX_DRAINED 0x01 1768 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1769 #define I40E_AQ_LINK_FORCED_40G 0x10 1770 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1771 __le16 max_frame_size; 1772 u8 config; 1773 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1774 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1775 u8 external_power_ability; 1776 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 1777 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 1778 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 1779 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 1780 u8 reserved[4]; 1781 }; 1782 1783 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1784 1785 /* Set event mask command (direct 0x613) */ 1786 struct i40e_aqc_set_phy_int_mask { 1787 u8 reserved[8]; 1788 __le16 event_mask; 1789 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1790 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1791 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1792 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1793 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1794 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1795 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1796 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1797 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1798 u8 reserved1[6]; 1799 }; 1800 1801 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1802 1803 /* Get Local AN advt register (direct 0x0614) 1804 * Set Local AN advt register (direct 0x0615) 1805 * Get Link Partner AN advt register (direct 0x0616) 1806 */ 1807 struct i40e_aqc_an_advt_reg { 1808 __le32 local_an_reg0; 1809 __le16 local_an_reg1; 1810 u8 reserved[10]; 1811 }; 1812 1813 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1814 1815 /* Set Loopback mode (0x0618) */ 1816 struct i40e_aqc_set_lb_mode { 1817 __le16 lb_mode; 1818 #define I40E_AQ_LB_PHY_LOCAL 0x01 1819 #define I40E_AQ_LB_PHY_REMOTE 0x02 1820 #define I40E_AQ_LB_MAC_LOCAL 0x04 1821 u8 reserved[14]; 1822 }; 1823 1824 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1825 1826 /* Set PHY Debug command (0x0622) */ 1827 struct i40e_aqc_set_phy_debug { 1828 u8 command_flags; 1829 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1830 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1831 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1832 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1833 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1834 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1835 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1836 /* Disable link manageability on a single port */ 1837 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1838 /* Disable link manageability on all ports */ 1839 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 1840 u8 reserved[15]; 1841 }; 1842 1843 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1844 1845 enum i40e_aq_phy_reg_type { 1846 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1847 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1848 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1849 }; 1850 1851 /* Run PHY Activity (0x0626) */ 1852 struct i40e_aqc_run_phy_activity { 1853 __le16 activity_id; 1854 u8 flags; 1855 u8 reserved1; 1856 __le32 control; 1857 __le32 data; 1858 u8 reserved2[4]; 1859 }; 1860 1861 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 1862 1863 /* NVM Read command (indirect 0x0701) 1864 * NVM Erase commands (direct 0x0702) 1865 * NVM Update commands (indirect 0x0703) 1866 */ 1867 struct i40e_aqc_nvm_update { 1868 u8 command_flags; 1869 #define I40E_AQ_NVM_LAST_CMD 0x01 1870 #define I40E_AQ_NVM_FLASH_ONLY 0x80 1871 u8 module_pointer; 1872 __le16 length; 1873 __le32 offset; 1874 __le32 addr_high; 1875 __le32 addr_low; 1876 }; 1877 1878 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1879 1880 /* NVM Config Read (indirect 0x0704) */ 1881 struct i40e_aqc_nvm_config_read { 1882 __le16 cmd_flags; 1883 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1884 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1885 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1886 __le16 element_count; 1887 __le16 element_id; /* Feature/field ID */ 1888 __le16 element_id_msw; /* MSWord of field ID */ 1889 __le32 address_high; 1890 __le32 address_low; 1891 }; 1892 1893 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1894 1895 /* NVM Config Write (indirect 0x0705) */ 1896 struct i40e_aqc_nvm_config_write { 1897 __le16 cmd_flags; 1898 __le16 element_count; 1899 u8 reserved[4]; 1900 __le32 address_high; 1901 __le32 address_low; 1902 }; 1903 1904 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1905 1906 /* Used for 0x0704 as well as for 0x0705 commands */ 1907 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1908 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 1909 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1910 #define I40E_AQ_ANVM_FEATURE 0 1911 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) 1912 struct i40e_aqc_nvm_config_data_feature { 1913 __le16 feature_id; 1914 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1915 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1916 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1917 __le16 feature_options; 1918 __le16 feature_selection; 1919 }; 1920 1921 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1922 1923 struct i40e_aqc_nvm_config_data_immediate_field { 1924 __le32 field_id; 1925 __le32 field_value; 1926 __le16 field_options; 1927 __le16 reserved; 1928 }; 1929 1930 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1931 1932 /* OEM Post Update (indirect 0x0720) 1933 * no command data struct used 1934 */ 1935 struct i40e_aqc_nvm_oem_post_update { 1936 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1937 u8 sel_data; 1938 u8 reserved[7]; 1939 }; 1940 1941 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1942 1943 struct i40e_aqc_nvm_oem_post_update_buffer { 1944 u8 str_len; 1945 u8 dev_addr; 1946 __le16 eeprom_addr; 1947 u8 data[36]; 1948 }; 1949 1950 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1951 1952 /* Thermal Sensor (indirect 0x0721) 1953 * read or set thermal sensor configs and values 1954 * takes a sensor and command specific data buffer, not detailed here 1955 */ 1956 struct i40e_aqc_thermal_sensor { 1957 u8 sensor_action; 1958 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 1959 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 1960 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 1961 u8 reserved[7]; 1962 __le32 addr_high; 1963 __le32 addr_low; 1964 }; 1965 1966 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 1967 1968 /* Send to PF command (indirect 0x0801) id is only used by PF 1969 * Send to VF command (indirect 0x0802) id is only used by PF 1970 * Send to Peer PF command (indirect 0x0803) 1971 */ 1972 struct i40e_aqc_pf_vf_message { 1973 __le32 id; 1974 u8 reserved[4]; 1975 __le32 addr_high; 1976 __le32 addr_low; 1977 }; 1978 1979 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1980 1981 /* Alternate structure */ 1982 1983 /* Direct write (direct 0x0900) 1984 * Direct read (direct 0x0902) 1985 */ 1986 struct i40e_aqc_alternate_write { 1987 __le32 address0; 1988 __le32 data0; 1989 __le32 address1; 1990 __le32 data1; 1991 }; 1992 1993 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1994 1995 /* Indirect write (indirect 0x0901) 1996 * Indirect read (indirect 0x0903) 1997 */ 1998 1999 struct i40e_aqc_alternate_ind_write { 2000 __le32 address; 2001 __le32 length; 2002 __le32 addr_high; 2003 __le32 addr_low; 2004 }; 2005 2006 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2007 2008 /* Done alternate write (direct 0x0904) 2009 * uses i40e_aq_desc 2010 */ 2011 struct i40e_aqc_alternate_write_done { 2012 __le16 cmd_flags; 2013 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2014 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2015 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2016 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2017 u8 reserved[14]; 2018 }; 2019 2020 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2021 2022 /* Set OEM mode (direct 0x0905) */ 2023 struct i40e_aqc_alternate_set_mode { 2024 __le32 mode; 2025 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2026 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2027 u8 reserved[12]; 2028 }; 2029 2030 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2031 2032 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2033 2034 /* async events 0x10xx */ 2035 2036 /* Lan Queue Overflow Event (direct, 0x1001) */ 2037 struct i40e_aqc_lan_overflow { 2038 __le32 prtdcb_rupto; 2039 __le32 otx_ctl; 2040 u8 reserved[8]; 2041 }; 2042 2043 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2044 2045 /* Get LLDP MIB (indirect 0x0A00) */ 2046 struct i40e_aqc_lldp_get_mib { 2047 u8 type; 2048 u8 reserved1; 2049 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2050 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2051 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2052 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2053 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2054 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2055 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2056 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2057 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2058 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2059 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2060 __le16 local_len; 2061 __le16 remote_len; 2062 u8 reserved2[2]; 2063 __le32 addr_high; 2064 __le32 addr_low; 2065 }; 2066 2067 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2068 2069 /* Configure LLDP MIB Change Event (direct 0x0A01) 2070 * also used for the event (with type in the command field) 2071 */ 2072 struct i40e_aqc_lldp_update_mib { 2073 u8 command; 2074 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2075 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2076 u8 reserved[7]; 2077 __le32 addr_high; 2078 __le32 addr_low; 2079 }; 2080 2081 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2082 2083 /* Add LLDP TLV (indirect 0x0A02) 2084 * Delete LLDP TLV (indirect 0x0A04) 2085 */ 2086 struct i40e_aqc_lldp_add_tlv { 2087 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2088 u8 reserved1[1]; 2089 __le16 len; 2090 u8 reserved2[4]; 2091 __le32 addr_high; 2092 __le32 addr_low; 2093 }; 2094 2095 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2096 2097 /* Update LLDP TLV (indirect 0x0A03) */ 2098 struct i40e_aqc_lldp_update_tlv { 2099 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2100 u8 reserved; 2101 __le16 old_len; 2102 __le16 new_offset; 2103 __le16 new_len; 2104 __le32 addr_high; 2105 __le32 addr_low; 2106 }; 2107 2108 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2109 2110 /* Stop LLDP (direct 0x0A05) */ 2111 struct i40e_aqc_lldp_stop { 2112 u8 command; 2113 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2114 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2115 u8 reserved[15]; 2116 }; 2117 2118 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2119 2120 /* Start LLDP (direct 0x0A06) */ 2121 2122 struct i40e_aqc_lldp_start { 2123 u8 command; 2124 #define I40E_AQ_LLDP_AGENT_START 0x1 2125 u8 reserved[15]; 2126 }; 2127 2128 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2129 2130 /* Get CEE DCBX Oper Config (0x0A07) 2131 * uses the generic descriptor struct 2132 * returns below as indirect response 2133 */ 2134 2135 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2136 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2137 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2138 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2139 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2140 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2141 2142 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2143 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2144 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2145 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2146 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2147 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2148 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2149 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2150 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2151 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2152 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2153 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2154 2155 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2156 * word boundary layout issues, which the Linux compilers silently deal 2157 * with by adding padding, making the actual struct larger than designed. 2158 * However, the FW compiler for the NIC is less lenient and complains 2159 * about the struct. Hence, the struct defined here has an extra byte in 2160 * fields reserved3 and reserved4 to directly acknowledge that padding, 2161 * and the new length is used in the length check macro. 2162 */ 2163 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2164 u8 reserved1; 2165 u8 oper_num_tc; 2166 u8 oper_prio_tc[4]; 2167 u8 reserved2; 2168 u8 oper_tc_bw[8]; 2169 u8 oper_pfc_en; 2170 u8 reserved3[2]; 2171 __le16 oper_app_prio; 2172 u8 reserved4[2]; 2173 __le16 tlv_status; 2174 }; 2175 2176 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2177 2178 struct i40e_aqc_get_cee_dcb_cfg_resp { 2179 u8 oper_num_tc; 2180 u8 oper_prio_tc[4]; 2181 u8 oper_tc_bw[8]; 2182 u8 oper_pfc_en; 2183 __le16 oper_app_prio; 2184 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2185 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2186 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2187 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2188 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2189 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2190 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2191 __le32 tlv_status; 2192 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2193 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2194 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2195 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2196 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2197 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2198 u8 reserved[12]; 2199 }; 2200 2201 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2202 2203 /* Set Local LLDP MIB (indirect 0x0A08) 2204 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2205 */ 2206 struct i40e_aqc_lldp_set_local_mib { 2207 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2208 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2209 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2210 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2211 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \ 2212 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2213 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2214 u8 type; 2215 u8 reserved0; 2216 __le16 length; 2217 u8 reserved1[4]; 2218 __le32 address_high; 2219 __le32 address_low; 2220 }; 2221 2222 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2223 2224 /* Stop/Start LLDP Agent (direct 0x0A09) 2225 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2226 */ 2227 struct i40e_aqc_lldp_stop_start_specific_agent { 2228 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2229 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2230 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2231 u8 command; 2232 u8 reserved[15]; 2233 }; 2234 2235 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2236 2237 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2238 struct i40e_aqc_add_udp_tunnel { 2239 __le16 udp_port; 2240 u8 reserved0[3]; 2241 u8 protocol_type; 2242 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2243 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2244 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2245 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2246 u8 reserved1[10]; 2247 }; 2248 2249 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2250 2251 struct i40e_aqc_add_udp_tunnel_completion { 2252 __le16 udp_port; 2253 u8 filter_entry_index; 2254 u8 multiple_pfs; 2255 #define I40E_AQC_SINGLE_PF 0x0 2256 #define I40E_AQC_MULTIPLE_PFS 0x1 2257 u8 total_filters; 2258 u8 reserved[11]; 2259 }; 2260 2261 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2262 2263 /* remove UDP Tunnel command (0x0B01) */ 2264 struct i40e_aqc_remove_udp_tunnel { 2265 u8 reserved[2]; 2266 u8 index; /* 0 to 15 */ 2267 u8 reserved2[13]; 2268 }; 2269 2270 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2271 2272 struct i40e_aqc_del_udp_tunnel_completion { 2273 __le16 udp_port; 2274 u8 index; /* 0 to 15 */ 2275 u8 multiple_pfs; 2276 u8 total_filters_used; 2277 u8 reserved1[11]; 2278 }; 2279 2280 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2281 2282 struct i40e_aqc_get_set_rss_key { 2283 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) 2284 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2285 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2286 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2287 __le16 vsi_id; 2288 u8 reserved[6]; 2289 __le32 addr_high; 2290 __le32 addr_low; 2291 }; 2292 2293 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2294 2295 struct i40e_aqc_get_set_rss_key_data { 2296 u8 standard_rss_key[0x28]; 2297 u8 extended_hash_key[0xc]; 2298 }; 2299 2300 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2301 2302 struct i40e_aqc_get_set_rss_lut { 2303 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) 2304 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2305 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2306 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2307 __le16 vsi_id; 2308 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2309 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2310 2311 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2312 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2313 __le16 flags; 2314 u8 reserved[4]; 2315 __le32 addr_high; 2316 __le32 addr_low; 2317 }; 2318 2319 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2320 2321 /* tunnel key structure 0x0B10 */ 2322 2323 struct i40e_aqc_tunnel_key_structure { 2324 u8 key1_off; 2325 u8 key2_off; 2326 u8 key1_len; /* 0 to 15 */ 2327 u8 key2_len; /* 0 to 15 */ 2328 u8 flags; 2329 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2330 /* response flags */ 2331 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2332 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2333 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2334 u8 network_key_index; 2335 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2336 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2337 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2338 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2339 u8 reserved[10]; 2340 }; 2341 2342 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2343 2344 /* OEM mode commands (direct 0xFE0x) */ 2345 struct i40e_aqc_oem_param_change { 2346 __le32 param_type; 2347 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2348 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2349 #define I40E_AQ_OEM_PARAM_MAC 2 2350 __le32 param_value1; 2351 __le16 param_value2; 2352 u8 reserved[6]; 2353 }; 2354 2355 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2356 2357 struct i40e_aqc_oem_state_change { 2358 __le32 state; 2359 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2360 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2361 u8 reserved[12]; 2362 }; 2363 2364 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2365 2366 /* Initialize OCSD (0xFE02, direct) */ 2367 struct i40e_aqc_opc_oem_ocsd_initialize { 2368 u8 type_status; 2369 u8 reserved1[3]; 2370 __le32 ocsd_memory_block_addr_high; 2371 __le32 ocsd_memory_block_addr_low; 2372 __le32 requested_update_interval; 2373 }; 2374 2375 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2376 2377 /* Initialize OCBB (0xFE03, direct) */ 2378 struct i40e_aqc_opc_oem_ocbb_initialize { 2379 u8 type_status; 2380 u8 reserved1[3]; 2381 __le32 ocbb_memory_block_addr_high; 2382 __le32 ocbb_memory_block_addr_low; 2383 u8 reserved2[4]; 2384 }; 2385 2386 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2387 2388 /* debug commands */ 2389 2390 /* get device id (0xFF00) uses the generic structure */ 2391 2392 /* set test more (0xFF01, internal) */ 2393 2394 struct i40e_acq_set_test_mode { 2395 u8 mode; 2396 #define I40E_AQ_TEST_PARTIAL 0 2397 #define I40E_AQ_TEST_FULL 1 2398 #define I40E_AQ_TEST_NVM 2 2399 u8 reserved[3]; 2400 u8 command; 2401 #define I40E_AQ_TEST_OPEN 0 2402 #define I40E_AQ_TEST_CLOSE 1 2403 #define I40E_AQ_TEST_INC 2 2404 u8 reserved2[3]; 2405 __le32 address_high; 2406 __le32 address_low; 2407 }; 2408 2409 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2410 2411 /* Debug Read Register command (0xFF03) 2412 * Debug Write Register command (0xFF04) 2413 */ 2414 struct i40e_aqc_debug_reg_read_write { 2415 __le32 reserved; 2416 __le32 address; 2417 __le32 value_high; 2418 __le32 value_low; 2419 }; 2420 2421 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2422 2423 /* Scatter/gather Reg Read (indirect 0xFF05) 2424 * Scatter/gather Reg Write (indirect 0xFF06) 2425 */ 2426 2427 /* i40e_aq_desc is used for the command */ 2428 struct i40e_aqc_debug_reg_sg_element_data { 2429 __le32 address; 2430 __le32 value; 2431 }; 2432 2433 /* Debug Modify register (direct 0xFF07) */ 2434 struct i40e_aqc_debug_modify_reg { 2435 __le32 address; 2436 __le32 value; 2437 __le32 clear_mask; 2438 __le32 set_mask; 2439 }; 2440 2441 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2442 2443 /* dump internal data (0xFF08, indirect) */ 2444 2445 #define I40E_AQ_CLUSTER_ID_AUX 0 2446 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2447 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2448 #define I40E_AQ_CLUSTER_ID_HMC 3 2449 #define I40E_AQ_CLUSTER_ID_MAC0 4 2450 #define I40E_AQ_CLUSTER_ID_MAC1 5 2451 #define I40E_AQ_CLUSTER_ID_MAC2 6 2452 #define I40E_AQ_CLUSTER_ID_MAC3 7 2453 #define I40E_AQ_CLUSTER_ID_DCB 8 2454 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2455 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2456 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2457 2458 struct i40e_aqc_debug_dump_internals { 2459 u8 cluster_id; 2460 u8 table_id; 2461 __le16 data_size; 2462 __le32 idx; 2463 __le32 address_high; 2464 __le32 address_low; 2465 }; 2466 2467 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2468 2469 struct i40e_aqc_debug_modify_internals { 2470 u8 cluster_id; 2471 u8 cluster_specific_params[7]; 2472 __le32 address_high; 2473 __le32 address_low; 2474 }; 2475 2476 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2477 2478 #endif /* _I40E_ADMINQ_CMD_H_ */ 2479