1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_ADMINQ_CMD_H_ 28 #define _I40E_ADMINQ_CMD_H_ 29 30 /* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36 #define I40E_FW_API_VERSION_MAJOR 0x0001 37 #define I40E_FW_API_VERSION_MINOR 0x0002 38 39 struct i40e_aq_desc { 40 __le16 flags; 41 __le16 opcode; 42 __le16 datalen; 43 __le16 retval; 44 __le32 cookie_high; 45 __le32 cookie_low; 46 union { 47 struct { 48 __le32 param0; 49 __le32 param1; 50 __le32 param2; 51 __le32 param3; 52 } internal; 53 struct { 54 __le32 param0; 55 __le32 param1; 56 __le32 addr_high; 57 __le32 addr_low; 58 } external; 59 u8 raw[16]; 60 } params; 61 }; 62 63 /* Flags sub-structure 64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 66 */ 67 68 /* command flags and offsets*/ 69 #define I40E_AQ_FLAG_DD_SHIFT 0 70 #define I40E_AQ_FLAG_CMP_SHIFT 1 71 #define I40E_AQ_FLAG_ERR_SHIFT 2 72 #define I40E_AQ_FLAG_VFE_SHIFT 3 73 #define I40E_AQ_FLAG_LB_SHIFT 9 74 #define I40E_AQ_FLAG_RD_SHIFT 10 75 #define I40E_AQ_FLAG_VFC_SHIFT 11 76 #define I40E_AQ_FLAG_BUF_SHIFT 12 77 #define I40E_AQ_FLAG_SI_SHIFT 13 78 #define I40E_AQ_FLAG_EI_SHIFT 14 79 #define I40E_AQ_FLAG_FE_SHIFT 15 80 81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 92 93 /* error codes */ 94 enum i40e_admin_queue_err { 95 I40E_AQ_RC_OK = 0, /* success */ 96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 97 I40E_AQ_RC_ENOENT = 2, /* No such element */ 98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 100 I40E_AQ_RC_EIO = 5, /* I/O error */ 101 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 103 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 105 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 106 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 108 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 117 I40E_AQ_RC_EFBIG = 22, /* File too large */ 118 }; 119 120 /* Admin Queue command opcodes */ 121 enum i40e_admin_queue_opc { 122 /* aq commands */ 123 i40e_aqc_opc_get_version = 0x0001, 124 i40e_aqc_opc_driver_version = 0x0002, 125 i40e_aqc_opc_queue_shutdown = 0x0003, 126 i40e_aqc_opc_set_pf_context = 0x0004, 127 128 /* resource ownership */ 129 i40e_aqc_opc_request_resource = 0x0008, 130 i40e_aqc_opc_release_resource = 0x0009, 131 132 i40e_aqc_opc_list_func_capabilities = 0x000A, 133 i40e_aqc_opc_list_dev_capabilities = 0x000B, 134 135 i40e_aqc_opc_set_cppm_configuration = 0x0103, 136 i40e_aqc_opc_set_arp_proxy_entry = 0x0104, 137 i40e_aqc_opc_set_ns_proxy_entry = 0x0105, 138 139 /* LAA */ 140 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */ 141 i40e_aqc_opc_mac_address_read = 0x0107, 142 i40e_aqc_opc_mac_address_write = 0x0108, 143 144 /* PXE */ 145 i40e_aqc_opc_clear_pxe_mode = 0x0110, 146 147 /* internal switch commands */ 148 i40e_aqc_opc_get_switch_config = 0x0200, 149 i40e_aqc_opc_add_statistics = 0x0201, 150 i40e_aqc_opc_remove_statistics = 0x0202, 151 i40e_aqc_opc_set_port_parameters = 0x0203, 152 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 153 154 i40e_aqc_opc_add_vsi = 0x0210, 155 i40e_aqc_opc_update_vsi_parameters = 0x0211, 156 i40e_aqc_opc_get_vsi_parameters = 0x0212, 157 158 i40e_aqc_opc_add_pv = 0x0220, 159 i40e_aqc_opc_update_pv_parameters = 0x0221, 160 i40e_aqc_opc_get_pv_parameters = 0x0222, 161 162 i40e_aqc_opc_add_veb = 0x0230, 163 i40e_aqc_opc_update_veb_parameters = 0x0231, 164 i40e_aqc_opc_get_veb_parameters = 0x0232, 165 166 i40e_aqc_opc_delete_element = 0x0243, 167 168 i40e_aqc_opc_add_macvlan = 0x0250, 169 i40e_aqc_opc_remove_macvlan = 0x0251, 170 i40e_aqc_opc_add_vlan = 0x0252, 171 i40e_aqc_opc_remove_vlan = 0x0253, 172 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 173 i40e_aqc_opc_add_tag = 0x0255, 174 i40e_aqc_opc_remove_tag = 0x0256, 175 i40e_aqc_opc_add_multicast_etag = 0x0257, 176 i40e_aqc_opc_remove_multicast_etag = 0x0258, 177 i40e_aqc_opc_update_tag = 0x0259, 178 i40e_aqc_opc_add_control_packet_filter = 0x025A, 179 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 180 i40e_aqc_opc_add_cloud_filters = 0x025C, 181 i40e_aqc_opc_remove_cloud_filters = 0x025D, 182 183 i40e_aqc_opc_add_mirror_rule = 0x0260, 184 i40e_aqc_opc_delete_mirror_rule = 0x0261, 185 186 /* DCB commands */ 187 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 188 i40e_aqc_opc_dcb_updated = 0x0302, 189 190 /* TX scheduler */ 191 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 192 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 193 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 194 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 195 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 196 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 197 198 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 199 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 200 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 201 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 202 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 203 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 204 i40e_aqc_opc_query_port_ets_config = 0x0419, 205 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 206 i40e_aqc_opc_suspend_port_tx = 0x041B, 207 i40e_aqc_opc_resume_port_tx = 0x041C, 208 i40e_aqc_opc_configure_partition_bw = 0x041D, 209 210 /* hmc */ 211 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 212 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 213 214 /* phy commands*/ 215 i40e_aqc_opc_get_phy_abilities = 0x0600, 216 i40e_aqc_opc_set_phy_config = 0x0601, 217 i40e_aqc_opc_set_mac_config = 0x0603, 218 i40e_aqc_opc_set_link_restart_an = 0x0605, 219 i40e_aqc_opc_get_link_status = 0x0607, 220 i40e_aqc_opc_set_phy_int_mask = 0x0613, 221 i40e_aqc_opc_get_local_advt_reg = 0x0614, 222 i40e_aqc_opc_set_local_advt_reg = 0x0615, 223 i40e_aqc_opc_get_partner_advt = 0x0616, 224 i40e_aqc_opc_set_lb_modes = 0x0618, 225 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 226 i40e_aqc_opc_set_phy_debug = 0x0622, 227 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 228 229 /* NVM commands */ 230 i40e_aqc_opc_nvm_read = 0x0701, 231 i40e_aqc_opc_nvm_erase = 0x0702, 232 i40e_aqc_opc_nvm_update = 0x0703, 233 i40e_aqc_opc_nvm_config_read = 0x0704, 234 i40e_aqc_opc_nvm_config_write = 0x0705, 235 236 /* virtualization commands */ 237 i40e_aqc_opc_send_msg_to_pf = 0x0801, 238 i40e_aqc_opc_send_msg_to_vf = 0x0802, 239 i40e_aqc_opc_send_msg_to_peer = 0x0803, 240 241 /* alternate structure */ 242 i40e_aqc_opc_alternate_write = 0x0900, 243 i40e_aqc_opc_alternate_write_indirect = 0x0901, 244 i40e_aqc_opc_alternate_read = 0x0902, 245 i40e_aqc_opc_alternate_read_indirect = 0x0903, 246 i40e_aqc_opc_alternate_write_done = 0x0904, 247 i40e_aqc_opc_alternate_set_mode = 0x0905, 248 i40e_aqc_opc_alternate_clear_port = 0x0906, 249 250 /* LLDP commands */ 251 i40e_aqc_opc_lldp_get_mib = 0x0A00, 252 i40e_aqc_opc_lldp_update_mib = 0x0A01, 253 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 254 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 255 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 256 i40e_aqc_opc_lldp_stop = 0x0A05, 257 i40e_aqc_opc_lldp_start = 0x0A06, 258 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 259 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 260 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 261 262 /* Tunnel commands */ 263 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 264 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 265 i40e_aqc_opc_tunnel_key_structure = 0x0B10, 266 267 /* Async Events */ 268 i40e_aqc_opc_event_lan_overflow = 0x1001, 269 270 /* OEM commands */ 271 i40e_aqc_opc_oem_parameter_change = 0xFE00, 272 i40e_aqc_opc_oem_device_status_change = 0xFE01, 273 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 274 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 275 276 /* debug commands */ 277 i40e_aqc_opc_debug_get_deviceid = 0xFF00, 278 i40e_aqc_opc_debug_set_mode = 0xFF01, 279 i40e_aqc_opc_debug_read_reg = 0xFF03, 280 i40e_aqc_opc_debug_write_reg = 0xFF04, 281 i40e_aqc_opc_debug_modify_reg = 0xFF07, 282 i40e_aqc_opc_debug_dump_internals = 0xFF08, 283 }; 284 285 /* command structures and indirect data structures */ 286 287 /* Structure naming conventions: 288 * - no suffix for direct command descriptor structures 289 * - _data for indirect sent data 290 * - _resp for indirect return data (data which is both will use _data) 291 * - _completion for direct return data 292 * - _element_ for repeated elements (may also be _data or _resp) 293 * 294 * Command structures are expected to overlay the params.raw member of the basic 295 * descriptor, and as such cannot exceed 16 bytes in length. 296 */ 297 298 /* This macro is used to generate a compilation error if a structure 299 * is not exactly the correct length. It gives a divide by zero error if the 300 * structure is not of the correct size, otherwise it creates an enum that is 301 * never used. 302 */ 303 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 304 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 305 306 /* This macro is used extensively to ensure that command structures are 16 307 * bytes in length as they have to map to the raw array of that size. 308 */ 309 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 310 311 /* internal (0x00XX) commands */ 312 313 /* Get version (direct 0x0001) */ 314 struct i40e_aqc_get_version { 315 __le32 rom_ver; 316 __le32 fw_build; 317 __le16 fw_major; 318 __le16 fw_minor; 319 __le16 api_major; 320 __le16 api_minor; 321 }; 322 323 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 324 325 /* Send driver version (indirect 0x0002) */ 326 struct i40e_aqc_driver_version { 327 u8 driver_major_ver; 328 u8 driver_minor_ver; 329 u8 driver_build_ver; 330 u8 driver_subbuild_ver; 331 u8 reserved[4]; 332 __le32 address_high; 333 __le32 address_low; 334 }; 335 336 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 337 338 /* Queue Shutdown (direct 0x0003) */ 339 struct i40e_aqc_queue_shutdown { 340 __le32 driver_unloading; 341 #define I40E_AQ_DRIVER_UNLOADING 0x1 342 u8 reserved[12]; 343 }; 344 345 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 346 347 /* Set PF context (0x0004, direct) */ 348 struct i40e_aqc_set_pf_context { 349 u8 pf_id; 350 u8 reserved[15]; 351 }; 352 353 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 354 355 /* Request resource ownership (direct 0x0008) 356 * Release resource ownership (direct 0x0009) 357 */ 358 #define I40E_AQ_RESOURCE_NVM 1 359 #define I40E_AQ_RESOURCE_SDP 2 360 #define I40E_AQ_RESOURCE_ACCESS_READ 1 361 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 362 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 363 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 364 365 struct i40e_aqc_request_resource { 366 __le16 resource_id; 367 __le16 access_type; 368 __le32 timeout; 369 __le32 resource_number; 370 u8 reserved[4]; 371 }; 372 373 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 374 375 /* Get function capabilities (indirect 0x000A) 376 * Get device capabilities (indirect 0x000B) 377 */ 378 struct i40e_aqc_list_capabilites { 379 u8 command_flags; 380 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 381 u8 pf_index; 382 u8 reserved[2]; 383 __le32 count; 384 __le32 addr_high; 385 __le32 addr_low; 386 }; 387 388 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 389 390 struct i40e_aqc_list_capabilities_element_resp { 391 __le16 id; 392 u8 major_rev; 393 u8 minor_rev; 394 __le32 number; 395 __le32 logical_id; 396 __le32 phys_id; 397 u8 reserved[16]; 398 }; 399 400 /* list of caps */ 401 402 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 403 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 404 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 405 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 406 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 407 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 408 #define I40E_AQ_CAP_ID_SRIOV 0x0012 409 #define I40E_AQ_CAP_ID_VF 0x0013 410 #define I40E_AQ_CAP_ID_VMDQ 0x0014 411 #define I40E_AQ_CAP_ID_8021QBG 0x0015 412 #define I40E_AQ_CAP_ID_8021QBR 0x0016 413 #define I40E_AQ_CAP_ID_VSI 0x0017 414 #define I40E_AQ_CAP_ID_DCB 0x0018 415 #define I40E_AQ_CAP_ID_FCOE 0x0021 416 #define I40E_AQ_CAP_ID_ISCSI 0x0022 417 #define I40E_AQ_CAP_ID_RSS 0x0040 418 #define I40E_AQ_CAP_ID_RXQ 0x0041 419 #define I40E_AQ_CAP_ID_TXQ 0x0042 420 #define I40E_AQ_CAP_ID_MSIX 0x0043 421 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 422 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 423 #define I40E_AQ_CAP_ID_1588 0x0046 424 #define I40E_AQ_CAP_ID_IWARP 0x0051 425 #define I40E_AQ_CAP_ID_LED 0x0061 426 #define I40E_AQ_CAP_ID_SDP 0x0062 427 #define I40E_AQ_CAP_ID_MDIO 0x0063 428 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 429 #define I40E_AQ_CAP_ID_CEM 0x00F2 430 431 /* Set CPPM Configuration (direct 0x0103) */ 432 struct i40e_aqc_cppm_configuration { 433 __le16 command_flags; 434 #define I40E_AQ_CPPM_EN_LTRC 0x0800 435 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 436 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 437 #define I40E_AQ_CPPM_EN_HPTC 0x4000 438 #define I40E_AQ_CPPM_EN_DMARC 0x8000 439 __le16 ttlx; 440 __le32 dmacr; 441 __le16 dmcth; 442 u8 hptc; 443 u8 reserved; 444 __le32 pfltrc; 445 }; 446 447 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 448 449 /* Set ARP Proxy command / response (indirect 0x0104) */ 450 struct i40e_aqc_arp_proxy_data { 451 __le16 command_flags; 452 #define I40E_AQ_ARP_INIT_IPV4 0x0008 453 #define I40E_AQ_ARP_UNSUP_CTL 0x0010 454 #define I40E_AQ_ARP_ENA 0x0020 455 #define I40E_AQ_ARP_ADD_IPV4 0x0040 456 #define I40E_AQ_ARP_DEL_IPV4 0x0080 457 __le16 table_id; 458 __le32 pfpm_proxyfc; 459 __le32 ip_addr; 460 u8 mac_addr[6]; 461 u8 reserved[2]; 462 }; 463 464 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 465 466 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 467 struct i40e_aqc_ns_proxy_data { 468 __le16 table_idx_mac_addr_0; 469 __le16 table_idx_mac_addr_1; 470 __le16 table_idx_ipv6_0; 471 __le16 table_idx_ipv6_1; 472 __le16 control; 473 #define I40E_AQ_NS_PROXY_ADD_0 0x0100 474 #define I40E_AQ_NS_PROXY_DEL_0 0x0200 475 #define I40E_AQ_NS_PROXY_ADD_1 0x0400 476 #define I40E_AQ_NS_PROXY_DEL_1 0x0800 477 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 478 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 479 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 480 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 481 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 482 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 483 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 484 u8 mac_addr_0[6]; 485 u8 mac_addr_1[6]; 486 u8 local_mac_addr[6]; 487 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 488 u8 ipv6_addr_1[16]; 489 }; 490 491 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 492 493 /* Manage LAA Command (0x0106) - obsolete */ 494 struct i40e_aqc_mng_laa { 495 __le16 command_flags; 496 #define I40E_AQ_LAA_FLAG_WR 0x8000 497 u8 reserved[2]; 498 __le32 sal; 499 __le16 sah; 500 u8 reserved2[6]; 501 }; 502 503 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 504 505 /* Manage MAC Address Read Command (indirect 0x0107) */ 506 struct i40e_aqc_mac_address_read { 507 __le16 command_flags; 508 #define I40E_AQC_LAN_ADDR_VALID 0x10 509 #define I40E_AQC_SAN_ADDR_VALID 0x20 510 #define I40E_AQC_PORT_ADDR_VALID 0x40 511 #define I40E_AQC_WOL_ADDR_VALID 0x80 512 #define I40E_AQC_ADDR_VALID_MASK 0xf0 513 u8 reserved[6]; 514 __le32 addr_high; 515 __le32 addr_low; 516 }; 517 518 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 519 520 struct i40e_aqc_mac_address_read_data { 521 u8 pf_lan_mac[6]; 522 u8 pf_san_mac[6]; 523 u8 port_mac[6]; 524 u8 pf_wol_mac[6]; 525 }; 526 527 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 528 529 /* Manage MAC Address Write Command (0x0108) */ 530 struct i40e_aqc_mac_address_write { 531 __le16 command_flags; 532 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 533 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 534 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 535 #define I40E_AQC_WRITE_TYPE_MASK 0xc000 536 __le16 mac_sah; 537 __le32 mac_sal; 538 u8 reserved[8]; 539 }; 540 541 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 542 543 /* PXE commands (0x011x) */ 544 545 /* Clear PXE Command and response (direct 0x0110) */ 546 struct i40e_aqc_clear_pxe { 547 u8 rx_cnt; 548 u8 reserved[15]; 549 }; 550 551 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 552 553 /* Switch configuration commands (0x02xx) */ 554 555 /* Used by many indirect commands that only pass an seid and a buffer in the 556 * command 557 */ 558 struct i40e_aqc_switch_seid { 559 __le16 seid; 560 u8 reserved[6]; 561 __le32 addr_high; 562 __le32 addr_low; 563 }; 564 565 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 566 567 /* Get Switch Configuration command (indirect 0x0200) 568 * uses i40e_aqc_switch_seid for the descriptor 569 */ 570 struct i40e_aqc_get_switch_config_header_resp { 571 __le16 num_reported; 572 __le16 num_total; 573 u8 reserved[12]; 574 }; 575 576 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 577 578 struct i40e_aqc_switch_config_element_resp { 579 u8 element_type; 580 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 581 #define I40E_AQ_SW_ELEM_TYPE_PF 2 582 #define I40E_AQ_SW_ELEM_TYPE_VF 3 583 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 584 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 585 #define I40E_AQ_SW_ELEM_TYPE_PV 16 586 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 587 #define I40E_AQ_SW_ELEM_TYPE_PA 18 588 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 589 u8 revision; 590 #define I40E_AQ_SW_ELEM_REV_1 1 591 __le16 seid; 592 __le16 uplink_seid; 593 __le16 downlink_seid; 594 u8 reserved[3]; 595 u8 connection_type; 596 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 597 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 598 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 599 __le16 scheduler_id; 600 __le16 element_info; 601 }; 602 603 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 604 605 /* Get Switch Configuration (indirect 0x0200) 606 * an array of elements are returned in the response buffer 607 * the first in the array is the header, remainder are elements 608 */ 609 struct i40e_aqc_get_switch_config_resp { 610 struct i40e_aqc_get_switch_config_header_resp header; 611 struct i40e_aqc_switch_config_element_resp element[1]; 612 }; 613 614 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 615 616 /* Add Statistics (direct 0x0201) 617 * Remove Statistics (direct 0x0202) 618 */ 619 struct i40e_aqc_add_remove_statistics { 620 __le16 seid; 621 __le16 vlan; 622 __le16 stat_index; 623 u8 reserved[10]; 624 }; 625 626 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 627 628 /* Set Port Parameters command (direct 0x0203) */ 629 struct i40e_aqc_set_port_parameters { 630 __le16 command_flags; 631 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 632 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 633 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 634 __le16 bad_frame_vsi; 635 __le16 default_seid; /* reserved for command */ 636 u8 reserved[10]; 637 }; 638 639 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 640 641 /* Get Switch Resource Allocation (indirect 0x0204) */ 642 struct i40e_aqc_get_switch_resource_alloc { 643 u8 num_entries; /* reserved for command */ 644 u8 reserved[7]; 645 __le32 addr_high; 646 __le32 addr_low; 647 }; 648 649 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 650 651 /* expect an array of these structs in the response buffer */ 652 struct i40e_aqc_switch_resource_alloc_element_resp { 653 u8 resource_type; 654 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 655 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 656 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 657 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 658 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 659 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 660 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 661 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 662 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 663 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 664 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 665 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 666 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 667 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 668 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 669 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 670 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 671 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 672 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 673 u8 reserved1; 674 __le16 guaranteed; 675 __le16 total; 676 __le16 used; 677 __le16 total_unalloced; 678 u8 reserved2[6]; 679 }; 680 681 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 682 683 /* Add VSI (indirect 0x0210) 684 * this indirect command uses struct i40e_aqc_vsi_properties_data 685 * as the indirect buffer (128 bytes) 686 * 687 * Update VSI (indirect 0x211) 688 * uses the same data structure as Add VSI 689 * 690 * Get VSI (indirect 0x0212) 691 * uses the same completion and data structure as Add VSI 692 */ 693 struct i40e_aqc_add_get_update_vsi { 694 __le16 uplink_seid; 695 u8 connection_type; 696 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 697 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 698 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 699 u8 reserved1; 700 u8 vf_id; 701 u8 reserved2; 702 __le16 vsi_flags; 703 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 704 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 705 #define I40E_AQ_VSI_TYPE_VF 0x0 706 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 707 #define I40E_AQ_VSI_TYPE_PF 0x2 708 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 709 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 710 __le32 addr_high; 711 __le32 addr_low; 712 }; 713 714 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 715 716 struct i40e_aqc_add_get_update_vsi_completion { 717 __le16 seid; 718 __le16 vsi_number; 719 __le16 vsi_used; 720 __le16 vsi_free; 721 __le32 addr_high; 722 __le32 addr_low; 723 }; 724 725 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 726 727 struct i40e_aqc_vsi_properties_data { 728 /* first 96 byte are written by SW */ 729 __le16 valid_sections; 730 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 731 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 732 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 733 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 734 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 735 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 736 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 737 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 738 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 739 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 740 /* switch section */ 741 __le16 switch_id; /* 12bit id combined with flags below */ 742 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 743 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 744 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 745 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 746 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 747 u8 sw_reserved[2]; 748 /* security section */ 749 u8 sec_flags; 750 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 751 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 752 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 753 u8 sec_reserved; 754 /* VLAN section */ 755 __le16 pvid; /* VLANS include priority bits */ 756 __le16 fcoe_pvid; 757 u8 port_vlan_flags; 758 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 759 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 760 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 761 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 762 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 763 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 764 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 765 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 766 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 767 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 768 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 769 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 770 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 771 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 772 u8 pvlan_reserved[3]; 773 /* ingress egress up sections */ 774 __le32 ingress_table; /* bitmap, 3 bits per up */ 775 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 776 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 777 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 778 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 779 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 780 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 781 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 782 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 783 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 784 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 785 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 786 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 787 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 788 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 789 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 790 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 791 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 792 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 793 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 794 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 795 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 796 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 797 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 798 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 799 __le32 egress_table; /* same defines as for ingress table */ 800 /* cascaded PV section */ 801 __le16 cas_pv_tag; 802 u8 cas_pv_flags; 803 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 804 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 805 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 806 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 807 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 808 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 809 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 810 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 811 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 812 u8 cas_pv_reserved; 813 /* queue mapping section */ 814 __le16 mapping_flags; 815 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 816 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 817 __le16 queue_mapping[16]; 818 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 819 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 820 __le16 tc_mapping[8]; 821 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 822 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 823 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 824 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 825 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 826 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 827 /* queueing option section */ 828 u8 queueing_opt_flags; 829 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 830 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 831 u8 queueing_opt_reserved[3]; 832 /* scheduler section */ 833 u8 up_enable_bits; 834 u8 sched_reserved; 835 /* outer up section */ 836 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 837 u8 cmd_reserved[8]; 838 /* last 32 bytes are written by FW */ 839 __le16 qs_handle[8]; 840 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 841 __le16 stat_counter_idx; 842 __le16 sched_id; 843 u8 resp_reserved[12]; 844 }; 845 846 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 847 848 /* Add Port Virtualizer (direct 0x0220) 849 * also used for update PV (direct 0x0221) but only flags are used 850 * (IS_CTRL_PORT only works on add PV) 851 */ 852 struct i40e_aqc_add_update_pv { 853 __le16 command_flags; 854 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 855 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 856 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 857 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 858 __le16 uplink_seid; 859 __le16 connected_seid; 860 u8 reserved[10]; 861 }; 862 863 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 864 865 struct i40e_aqc_add_update_pv_completion { 866 /* reserved for update; for add also encodes error if rc == ENOSPC */ 867 __le16 pv_seid; 868 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 869 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 870 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 871 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 872 u8 reserved[14]; 873 }; 874 875 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 876 877 /* Get PV Params (direct 0x0222) 878 * uses i40e_aqc_switch_seid for the descriptor 879 */ 880 881 struct i40e_aqc_get_pv_params_completion { 882 __le16 seid; 883 __le16 default_stag; 884 __le16 pv_flags; /* same flags as add_pv */ 885 #define I40E_AQC_GET_PV_PV_TYPE 0x1 886 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 887 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 888 u8 reserved[8]; 889 __le16 default_port_seid; 890 }; 891 892 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 893 894 /* Add VEB (direct 0x0230) */ 895 struct i40e_aqc_add_veb { 896 __le16 uplink_seid; 897 __le16 downlink_seid; 898 __le16 veb_flags; 899 #define I40E_AQC_ADD_VEB_FLOATING 0x1 900 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 901 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 902 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 903 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 904 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 905 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 906 u8 enable_tcs; 907 u8 reserved[9]; 908 }; 909 910 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 911 912 struct i40e_aqc_add_veb_completion { 913 u8 reserved[6]; 914 __le16 switch_seid; 915 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 916 __le16 veb_seid; 917 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 918 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 919 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 920 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 921 __le16 statistic_index; 922 __le16 vebs_used; 923 __le16 vebs_free; 924 }; 925 926 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 927 928 /* Get VEB Parameters (direct 0x0232) 929 * uses i40e_aqc_switch_seid for the descriptor 930 */ 931 struct i40e_aqc_get_veb_parameters_completion { 932 __le16 seid; 933 __le16 switch_id; 934 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 935 __le16 statistic_index; 936 __le16 vebs_used; 937 __le16 vebs_free; 938 u8 reserved[4]; 939 }; 940 941 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 942 943 /* Delete Element (direct 0x0243) 944 * uses the generic i40e_aqc_switch_seid 945 */ 946 947 /* Add MAC-VLAN (indirect 0x0250) */ 948 949 /* used for the command for most vlan commands */ 950 struct i40e_aqc_macvlan { 951 __le16 num_addresses; 952 __le16 seid[3]; 953 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 954 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 955 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 956 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 957 __le32 addr_high; 958 __le32 addr_low; 959 }; 960 961 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 962 963 /* indirect data for command and response */ 964 struct i40e_aqc_add_macvlan_element_data { 965 u8 mac_addr[6]; 966 __le16 vlan_tag; 967 __le16 flags; 968 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 969 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 970 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 971 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 972 __le16 queue_number; 973 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 974 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 975 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 976 /* response section */ 977 u8 match_method; 978 #define I40E_AQC_MM_PERFECT_MATCH 0x01 979 #define I40E_AQC_MM_HASH_MATCH 0x02 980 #define I40E_AQC_MM_ERR_NO_RES 0xFF 981 u8 reserved1[3]; 982 }; 983 984 struct i40e_aqc_add_remove_macvlan_completion { 985 __le16 perfect_mac_used; 986 __le16 perfect_mac_free; 987 __le16 unicast_hash_free; 988 __le16 multicast_hash_free; 989 __le32 addr_high; 990 __le32 addr_low; 991 }; 992 993 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 994 995 /* Remove MAC-VLAN (indirect 0x0251) 996 * uses i40e_aqc_macvlan for the descriptor 997 * data points to an array of num_addresses of elements 998 */ 999 1000 struct i40e_aqc_remove_macvlan_element_data { 1001 u8 mac_addr[6]; 1002 __le16 vlan_tag; 1003 u8 flags; 1004 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1005 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1006 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1007 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1008 u8 reserved[3]; 1009 /* reply section */ 1010 u8 error_code; 1011 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1012 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1013 u8 reply_reserved[3]; 1014 }; 1015 1016 /* Add VLAN (indirect 0x0252) 1017 * Remove VLAN (indirect 0x0253) 1018 * use the generic i40e_aqc_macvlan for the command 1019 */ 1020 struct i40e_aqc_add_remove_vlan_element_data { 1021 __le16 vlan_tag; 1022 u8 vlan_flags; 1023 /* flags for add VLAN */ 1024 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1025 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1026 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1027 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1028 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1029 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1030 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1031 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1032 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1033 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1034 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1035 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1036 /* flags for remove VLAN */ 1037 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1038 u8 reserved; 1039 u8 result; 1040 /* flags for add VLAN */ 1041 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1042 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1043 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1044 /* flags for remove VLAN */ 1045 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1046 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1047 u8 reserved1[3]; 1048 }; 1049 1050 struct i40e_aqc_add_remove_vlan_completion { 1051 u8 reserved[4]; 1052 __le16 vlans_used; 1053 __le16 vlans_free; 1054 __le32 addr_high; 1055 __le32 addr_low; 1056 }; 1057 1058 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1059 struct i40e_aqc_set_vsi_promiscuous_modes { 1060 __le16 promiscuous_flags; 1061 __le16 valid_flags; 1062 /* flags used for both fields above */ 1063 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1064 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1065 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1066 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1067 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1068 __le16 seid; 1069 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1070 __le16 vlan_tag; 1071 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1072 u8 reserved[8]; 1073 }; 1074 1075 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1076 1077 /* Add S/E-tag command (direct 0x0255) 1078 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1079 */ 1080 struct i40e_aqc_add_tag { 1081 __le16 flags; 1082 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1083 __le16 seid; 1084 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1085 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1086 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1087 __le16 tag; 1088 __le16 queue_number; 1089 u8 reserved[8]; 1090 }; 1091 1092 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1093 1094 struct i40e_aqc_add_remove_tag_completion { 1095 u8 reserved[12]; 1096 __le16 tags_used; 1097 __le16 tags_free; 1098 }; 1099 1100 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1101 1102 /* Remove S/E-tag command (direct 0x0256) 1103 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1104 */ 1105 struct i40e_aqc_remove_tag { 1106 __le16 seid; 1107 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1108 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1109 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1110 __le16 tag; 1111 u8 reserved[12]; 1112 }; 1113 1114 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1115 1116 /* Add multicast E-Tag (direct 0x0257) 1117 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1118 * and no external data 1119 */ 1120 struct i40e_aqc_add_remove_mcast_etag { 1121 __le16 pv_seid; 1122 __le16 etag; 1123 u8 num_unicast_etags; 1124 u8 reserved[3]; 1125 __le32 addr_high; /* address of array of 2-byte s-tags */ 1126 __le32 addr_low; 1127 }; 1128 1129 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1130 1131 struct i40e_aqc_add_remove_mcast_etag_completion { 1132 u8 reserved[4]; 1133 __le16 mcast_etags_used; 1134 __le16 mcast_etags_free; 1135 __le32 addr_high; 1136 __le32 addr_low; 1137 1138 }; 1139 1140 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1141 1142 /* Update S/E-Tag (direct 0x0259) */ 1143 struct i40e_aqc_update_tag { 1144 __le16 seid; 1145 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1146 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1147 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1148 __le16 old_tag; 1149 __le16 new_tag; 1150 u8 reserved[10]; 1151 }; 1152 1153 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1154 1155 struct i40e_aqc_update_tag_completion { 1156 u8 reserved[12]; 1157 __le16 tags_used; 1158 __le16 tags_free; 1159 }; 1160 1161 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1162 1163 /* Add Control Packet filter (direct 0x025A) 1164 * Remove Control Packet filter (direct 0x025B) 1165 * uses the i40e_aqc_add_oveb_cloud, 1166 * and the generic direct completion structure 1167 */ 1168 struct i40e_aqc_add_remove_control_packet_filter { 1169 u8 mac[6]; 1170 __le16 etype; 1171 __le16 flags; 1172 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1173 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1174 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1175 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1176 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1177 __le16 seid; 1178 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1179 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1180 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1181 __le16 queue; 1182 u8 reserved[2]; 1183 }; 1184 1185 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1186 1187 struct i40e_aqc_add_remove_control_packet_filter_completion { 1188 __le16 mac_etype_used; 1189 __le16 etype_used; 1190 __le16 mac_etype_free; 1191 __le16 etype_free; 1192 u8 reserved[8]; 1193 }; 1194 1195 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1196 1197 /* Add Cloud filters (indirect 0x025C) 1198 * Remove Cloud filters (indirect 0x025D) 1199 * uses the i40e_aqc_add_remove_cloud_filters, 1200 * and the generic indirect completion structure 1201 */ 1202 struct i40e_aqc_add_remove_cloud_filters { 1203 u8 num_filters; 1204 u8 reserved; 1205 __le16 seid; 1206 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1207 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1208 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1209 u8 reserved2[4]; 1210 __le32 addr_high; 1211 __le32 addr_low; 1212 }; 1213 1214 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1215 1216 struct i40e_aqc_add_remove_cloud_filters_element_data { 1217 u8 outer_mac[6]; 1218 u8 inner_mac[6]; 1219 __le16 inner_vlan; 1220 union { 1221 struct { 1222 u8 reserved[12]; 1223 u8 data[4]; 1224 } v4; 1225 struct { 1226 u8 data[16]; 1227 } v6; 1228 } ipaddr; 1229 __le16 flags; 1230 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1231 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1232 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1233 /* 0x0000 reserved */ 1234 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1235 /* 0x0002 reserved */ 1236 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1237 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1238 /* 0x0005 reserved */ 1239 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1240 /* 0x0007 reserved */ 1241 /* 0x0008 reserved */ 1242 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1243 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1244 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1245 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1246 1247 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1248 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1249 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1250 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1251 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1252 1253 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1254 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1255 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1256 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1257 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1258 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1259 1260 __le32 tenant_id; 1261 u8 reserved[4]; 1262 __le16 queue_number; 1263 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1264 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1265 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1266 u8 reserved2[14]; 1267 /* response section */ 1268 u8 allocation_result; 1269 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1270 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1271 u8 response_reserved[7]; 1272 }; 1273 1274 struct i40e_aqc_remove_cloud_filters_completion { 1275 __le16 perfect_ovlan_used; 1276 __le16 perfect_ovlan_free; 1277 __le16 vlan_used; 1278 __le16 vlan_free; 1279 __le32 addr_high; 1280 __le32 addr_low; 1281 }; 1282 1283 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1284 1285 /* Add Mirror Rule (indirect or direct 0x0260) 1286 * Delete Mirror Rule (indirect or direct 0x0261) 1287 * note: some rule types (4,5) do not use an external buffer. 1288 * take care to set the flags correctly. 1289 */ 1290 struct i40e_aqc_add_delete_mirror_rule { 1291 __le16 seid; 1292 __le16 rule_type; 1293 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1294 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1295 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1296 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1297 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1298 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1299 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1300 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1301 __le16 num_entries; 1302 __le16 destination; /* VSI for add, rule id for delete */ 1303 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1304 __le32 addr_low; 1305 }; 1306 1307 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1308 1309 struct i40e_aqc_add_delete_mirror_rule_completion { 1310 u8 reserved[2]; 1311 __le16 rule_id; /* only used on add */ 1312 __le16 mirror_rules_used; 1313 __le16 mirror_rules_free; 1314 __le32 addr_high; 1315 __le32 addr_low; 1316 }; 1317 1318 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1319 1320 /* DCB 0x03xx*/ 1321 1322 /* PFC Ignore (direct 0x0301) 1323 * the command and response use the same descriptor structure 1324 */ 1325 struct i40e_aqc_pfc_ignore { 1326 u8 tc_bitmap; 1327 u8 command_flags; /* unused on response */ 1328 #define I40E_AQC_PFC_IGNORE_SET 0x80 1329 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1330 u8 reserved[14]; 1331 }; 1332 1333 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1334 1335 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1336 * with no parameters 1337 */ 1338 1339 /* TX scheduler 0x04xx */ 1340 1341 /* Almost all the indirect commands use 1342 * this generic struct to pass the SEID in param0 1343 */ 1344 struct i40e_aqc_tx_sched_ind { 1345 __le16 vsi_seid; 1346 u8 reserved[6]; 1347 __le32 addr_high; 1348 __le32 addr_low; 1349 }; 1350 1351 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1352 1353 /* Several commands respond with a set of queue set handles */ 1354 struct i40e_aqc_qs_handles_resp { 1355 __le16 qs_handles[8]; 1356 }; 1357 1358 /* Configure VSI BW limits (direct 0x0400) */ 1359 struct i40e_aqc_configure_vsi_bw_limit { 1360 __le16 vsi_seid; 1361 u8 reserved[2]; 1362 __le16 credit; 1363 u8 reserved1[2]; 1364 u8 max_credit; /* 0-3, limit = 2^max */ 1365 u8 reserved2[7]; 1366 }; 1367 1368 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1369 1370 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1371 * responds with i40e_aqc_qs_handles_resp 1372 */ 1373 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1374 u8 tc_valid_bits; 1375 u8 reserved[15]; 1376 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1377 1378 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1379 __le16 tc_bw_max[2]; 1380 u8 reserved1[28]; 1381 }; 1382 1383 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1384 1385 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1386 * responds with i40e_aqc_qs_handles_resp 1387 */ 1388 struct i40e_aqc_configure_vsi_tc_bw_data { 1389 u8 tc_valid_bits; 1390 u8 reserved[3]; 1391 u8 tc_bw_credits[8]; 1392 u8 reserved1[4]; 1393 __le16 qs_handles[8]; 1394 }; 1395 1396 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1397 1398 /* Query vsi bw configuration (indirect 0x0408) */ 1399 struct i40e_aqc_query_vsi_bw_config_resp { 1400 u8 tc_valid_bits; 1401 u8 tc_suspended_bits; 1402 u8 reserved[14]; 1403 __le16 qs_handles[8]; 1404 u8 reserved1[4]; 1405 __le16 port_bw_limit; 1406 u8 reserved2[2]; 1407 u8 max_bw; /* 0-3, limit = 2^max */ 1408 u8 reserved3[23]; 1409 }; 1410 1411 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1412 1413 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1414 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1415 u8 tc_valid_bits; 1416 u8 reserved[3]; 1417 u8 share_credits[8]; 1418 __le16 credits[8]; 1419 1420 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1421 __le16 tc_bw_max[2]; 1422 }; 1423 1424 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1425 1426 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1427 struct i40e_aqc_configure_switching_comp_bw_limit { 1428 __le16 seid; 1429 u8 reserved[2]; 1430 __le16 credit; 1431 u8 reserved1[2]; 1432 u8 max_bw; /* 0-3, limit = 2^max */ 1433 u8 reserved2[7]; 1434 }; 1435 1436 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1437 1438 /* Enable Physical Port ETS (indirect 0x0413) 1439 * Modify Physical Port ETS (indirect 0x0414) 1440 * Disable Physical Port ETS (indirect 0x0415) 1441 */ 1442 struct i40e_aqc_configure_switching_comp_ets_data { 1443 u8 reserved[4]; 1444 u8 tc_valid_bits; 1445 u8 seepage; 1446 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1447 u8 tc_strict_priority_flags; 1448 u8 reserved1[17]; 1449 u8 tc_bw_share_credits[8]; 1450 u8 reserved2[96]; 1451 }; 1452 1453 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1454 1455 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1456 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1457 u8 tc_valid_bits; 1458 u8 reserved[15]; 1459 __le16 tc_bw_credit[8]; 1460 1461 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1462 __le16 tc_bw_max[2]; 1463 u8 reserved1[28]; 1464 }; 1465 1466 I40E_CHECK_STRUCT_LEN(0x40, 1467 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1468 1469 /* Configure Switching Component Bandwidth Allocation per Tc 1470 * (indirect 0x0417) 1471 */ 1472 struct i40e_aqc_configure_switching_comp_bw_config_data { 1473 u8 tc_valid_bits; 1474 u8 reserved[2]; 1475 u8 absolute_credits; /* bool */ 1476 u8 tc_bw_share_credits[8]; 1477 u8 reserved1[20]; 1478 }; 1479 1480 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1481 1482 /* Query Switching Component Configuration (indirect 0x0418) */ 1483 struct i40e_aqc_query_switching_comp_ets_config_resp { 1484 u8 tc_valid_bits; 1485 u8 reserved[35]; 1486 __le16 port_bw_limit; 1487 u8 reserved1[2]; 1488 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1489 u8 reserved2[23]; 1490 }; 1491 1492 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1493 1494 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1495 struct i40e_aqc_query_port_ets_config_resp { 1496 u8 reserved[4]; 1497 u8 tc_valid_bits; 1498 u8 reserved1; 1499 u8 tc_strict_priority_bits; 1500 u8 reserved2; 1501 u8 tc_bw_share_credits[8]; 1502 __le16 tc_bw_limits[8]; 1503 1504 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1505 __le16 tc_bw_max[2]; 1506 u8 reserved3[32]; 1507 }; 1508 1509 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1510 1511 /* Query Switching Component Bandwidth Allocation per Traffic Type 1512 * (indirect 0x041A) 1513 */ 1514 struct i40e_aqc_query_switching_comp_bw_config_resp { 1515 u8 tc_valid_bits; 1516 u8 reserved[2]; 1517 u8 absolute_credits_enable; /* bool */ 1518 u8 tc_bw_share_credits[8]; 1519 __le16 tc_bw_limits[8]; 1520 1521 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1522 __le16 tc_bw_max[2]; 1523 }; 1524 1525 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1526 1527 /* Suspend/resume port TX traffic 1528 * (direct 0x041B and 0x041C) uses the generic SEID struct 1529 */ 1530 1531 /* Configure partition BW 1532 * (indirect 0x041D) 1533 */ 1534 struct i40e_aqc_configure_partition_bw_data { 1535 __le16 pf_valid_bits; 1536 u8 min_bw[16]; /* guaranteed bandwidth */ 1537 u8 max_bw[16]; /* bandwidth limit */ 1538 }; 1539 1540 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1541 1542 /* Get and set the active HMC resource profile and status. 1543 * (direct 0x0500) and (direct 0x0501) 1544 */ 1545 struct i40e_aq_get_set_hmc_resource_profile { 1546 u8 pm_profile; 1547 u8 pe_vf_enabled; 1548 u8 reserved[14]; 1549 }; 1550 1551 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1552 1553 enum i40e_aq_hmc_profile { 1554 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1555 I40E_HMC_PROFILE_DEFAULT = 1, 1556 I40E_HMC_PROFILE_FAVOR_VF = 2, 1557 I40E_HMC_PROFILE_EQUAL = 3, 1558 }; 1559 1560 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1561 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1562 1563 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1564 1565 /* set in param0 for get phy abilities to report qualified modules */ 1566 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1567 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1568 1569 enum i40e_aq_phy_type { 1570 I40E_PHY_TYPE_SGMII = 0x0, 1571 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1572 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1573 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1574 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1575 I40E_PHY_TYPE_XAUI = 0x5, 1576 I40E_PHY_TYPE_XFI = 0x6, 1577 I40E_PHY_TYPE_SFI = 0x7, 1578 I40E_PHY_TYPE_XLAUI = 0x8, 1579 I40E_PHY_TYPE_XLPPI = 0x9, 1580 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1581 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1582 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1583 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1584 I40E_PHY_TYPE_100BASE_TX = 0x11, 1585 I40E_PHY_TYPE_1000BASE_T = 0x12, 1586 I40E_PHY_TYPE_10GBASE_T = 0x13, 1587 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1588 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1589 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1590 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1591 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1592 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1593 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1594 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1595 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1596 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1597 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1598 I40E_PHY_TYPE_MAX 1599 }; 1600 1601 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1602 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1603 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1604 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1605 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1606 1607 enum i40e_aq_link_speed { 1608 I40E_LINK_SPEED_UNKNOWN = 0, 1609 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1610 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1611 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1612 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1613 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1614 }; 1615 1616 struct i40e_aqc_module_desc { 1617 u8 oui[3]; 1618 u8 reserved1; 1619 u8 part_number[16]; 1620 u8 revision[4]; 1621 u8 reserved2[8]; 1622 }; 1623 1624 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1625 1626 struct i40e_aq_get_phy_abilities_resp { 1627 __le32 phy_type; /* bitmap using the above enum for offsets */ 1628 u8 link_speed; /* bitmap using the above enum bit patterns */ 1629 u8 abilities; 1630 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1631 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1632 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1633 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1634 #define I40E_AQ_PHY_AN_ENABLED 0x10 1635 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1636 __le16 eee_capability; 1637 #define I40E_AQ_EEE_100BASE_TX 0x0002 1638 #define I40E_AQ_EEE_1000BASE_T 0x0004 1639 #define I40E_AQ_EEE_10GBASE_T 0x0008 1640 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1641 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1642 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1643 __le32 eeer_val; 1644 u8 d3_lpan; 1645 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1646 u8 reserved[3]; 1647 u8 phy_id[4]; 1648 u8 module_type[3]; 1649 u8 qualified_module_count; 1650 #define I40E_AQ_PHY_MAX_QMS 16 1651 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1652 }; 1653 1654 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1655 1656 /* Set PHY Config (direct 0x0601) */ 1657 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1658 __le32 phy_type; 1659 u8 link_speed; 1660 u8 abilities; 1661 /* bits 0-2 use the values from get_phy_abilities_resp */ 1662 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1663 #define I40E_AQ_PHY_ENABLE_AN 0x10 1664 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1665 __le16 eee_capability; 1666 __le32 eeer; 1667 u8 low_power_ctrl; 1668 u8 reserved[3]; 1669 }; 1670 1671 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1672 1673 /* Set MAC Config command data structure (direct 0x0603) */ 1674 struct i40e_aq_set_mac_config { 1675 __le16 max_frame_size; 1676 u8 params; 1677 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1678 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1679 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1680 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1681 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1682 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1683 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1691 u8 tx_timer_priority; /* bitmap */ 1692 __le16 tx_timer_value; 1693 __le16 fc_refresh_threshold; 1694 u8 reserved[8]; 1695 }; 1696 1697 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1698 1699 /* Restart Auto-Negotiation (direct 0x605) */ 1700 struct i40e_aqc_set_link_restart_an { 1701 u8 command; 1702 #define I40E_AQ_PHY_RESTART_AN 0x02 1703 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1704 u8 reserved[15]; 1705 }; 1706 1707 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1708 1709 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1710 struct i40e_aqc_get_link_status { 1711 __le16 command_flags; /* only field set on command */ 1712 #define I40E_AQ_LSE_MASK 0x3 1713 #define I40E_AQ_LSE_NOP 0x0 1714 #define I40E_AQ_LSE_DISABLE 0x2 1715 #define I40E_AQ_LSE_ENABLE 0x3 1716 /* only response uses this flag */ 1717 #define I40E_AQ_LSE_IS_ENABLED 0x1 1718 u8 phy_type; /* i40e_aq_phy_type */ 1719 u8 link_speed; /* i40e_aq_link_speed */ 1720 u8 link_info; 1721 #define I40E_AQ_LINK_UP 0x01 1722 #define I40E_AQ_LINK_FAULT 0x02 1723 #define I40E_AQ_LINK_FAULT_TX 0x04 1724 #define I40E_AQ_LINK_FAULT_RX 0x08 1725 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1726 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1727 #define I40E_AQ_SIGNAL_DETECT 0x80 1728 u8 an_info; 1729 #define I40E_AQ_AN_COMPLETED 0x01 1730 #define I40E_AQ_LP_AN_ABILITY 0x02 1731 #define I40E_AQ_PD_FAULT 0x04 1732 #define I40E_AQ_FEC_EN 0x08 1733 #define I40E_AQ_PHY_LOW_POWER 0x10 1734 #define I40E_AQ_LINK_PAUSE_TX 0x20 1735 #define I40E_AQ_LINK_PAUSE_RX 0x40 1736 #define I40E_AQ_QUALIFIED_MODULE 0x80 1737 u8 ext_info; 1738 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1739 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1740 #define I40E_AQ_LINK_TX_SHIFT 0x02 1741 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1742 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1743 #define I40E_AQ_LINK_TX_DRAINED 0x01 1744 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1745 #define I40E_AQ_LINK_FORCED_40G 0x10 1746 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1747 __le16 max_frame_size; 1748 u8 config; 1749 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1750 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1751 u8 reserved[5]; 1752 }; 1753 1754 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1755 1756 /* Set event mask command (direct 0x613) */ 1757 struct i40e_aqc_set_phy_int_mask { 1758 u8 reserved[8]; 1759 __le16 event_mask; 1760 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1761 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1762 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1763 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1764 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1765 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1766 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1767 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1768 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1769 u8 reserved1[6]; 1770 }; 1771 1772 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1773 1774 /* Get Local AN advt register (direct 0x0614) 1775 * Set Local AN advt register (direct 0x0615) 1776 * Get Link Partner AN advt register (direct 0x0616) 1777 */ 1778 struct i40e_aqc_an_advt_reg { 1779 __le32 local_an_reg0; 1780 __le16 local_an_reg1; 1781 u8 reserved[10]; 1782 }; 1783 1784 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1785 1786 /* Set Loopback mode (0x0618) */ 1787 struct i40e_aqc_set_lb_mode { 1788 __le16 lb_mode; 1789 #define I40E_AQ_LB_PHY_LOCAL 0x01 1790 #define I40E_AQ_LB_PHY_REMOTE 0x02 1791 #define I40E_AQ_LB_MAC_LOCAL 0x04 1792 u8 reserved[14]; 1793 }; 1794 1795 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1796 1797 /* Set PHY Debug command (0x0622) */ 1798 struct i40e_aqc_set_phy_debug { 1799 u8 command_flags; 1800 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1801 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1802 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1803 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1804 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1805 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1806 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1807 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1808 u8 reserved[15]; 1809 }; 1810 1811 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1812 1813 enum i40e_aq_phy_reg_type { 1814 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1815 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1816 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1817 }; 1818 1819 /* NVM Read command (indirect 0x0701) 1820 * NVM Erase commands (direct 0x0702) 1821 * NVM Update commands (indirect 0x0703) 1822 */ 1823 struct i40e_aqc_nvm_update { 1824 u8 command_flags; 1825 #define I40E_AQ_NVM_LAST_CMD 0x01 1826 #define I40E_AQ_NVM_FLASH_ONLY 0x80 1827 u8 module_pointer; 1828 __le16 length; 1829 __le32 offset; 1830 __le32 addr_high; 1831 __le32 addr_low; 1832 }; 1833 1834 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1835 1836 /* NVM Config Read (indirect 0x0704) */ 1837 struct i40e_aqc_nvm_config_read { 1838 __le16 cmd_flags; 1839 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1840 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1841 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1842 __le16 element_count; 1843 __le16 element_id; /* Feature/field ID */ 1844 __le16 element_id_msw; /* MSWord of field ID */ 1845 __le32 address_high; 1846 __le32 address_low; 1847 }; 1848 1849 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1850 1851 /* NVM Config Write (indirect 0x0705) */ 1852 struct i40e_aqc_nvm_config_write { 1853 __le16 cmd_flags; 1854 __le16 element_count; 1855 u8 reserved[4]; 1856 __le32 address_high; 1857 __le32 address_low; 1858 }; 1859 1860 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1861 1862 /* Used for 0x0704 as well as for 0x0705 commands */ 1863 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1864 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 1865 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1866 #define I40E_AQ_ANVM_FEATURE 0 1867 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1868 struct i40e_aqc_nvm_config_data_feature { 1869 __le16 feature_id; 1870 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1871 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1872 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1873 __le16 feature_options; 1874 __le16 feature_selection; 1875 }; 1876 1877 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1878 1879 struct i40e_aqc_nvm_config_data_immediate_field { 1880 __le32 field_id; 1881 __le32 field_value; 1882 __le16 field_options; 1883 __le16 reserved; 1884 }; 1885 1886 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1887 1888 /* Send to PF command (indirect 0x0801) id is only used by PF 1889 * Send to VF command (indirect 0x0802) id is only used by PF 1890 * Send to Peer PF command (indirect 0x0803) 1891 */ 1892 struct i40e_aqc_pf_vf_message { 1893 __le32 id; 1894 u8 reserved[4]; 1895 __le32 addr_high; 1896 __le32 addr_low; 1897 }; 1898 1899 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1900 1901 /* Alternate structure */ 1902 1903 /* Direct write (direct 0x0900) 1904 * Direct read (direct 0x0902) 1905 */ 1906 struct i40e_aqc_alternate_write { 1907 __le32 address0; 1908 __le32 data0; 1909 __le32 address1; 1910 __le32 data1; 1911 }; 1912 1913 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1914 1915 /* Indirect write (indirect 0x0901) 1916 * Indirect read (indirect 0x0903) 1917 */ 1918 1919 struct i40e_aqc_alternate_ind_write { 1920 __le32 address; 1921 __le32 length; 1922 __le32 addr_high; 1923 __le32 addr_low; 1924 }; 1925 1926 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1927 1928 /* Done alternate write (direct 0x0904) 1929 * uses i40e_aq_desc 1930 */ 1931 struct i40e_aqc_alternate_write_done { 1932 __le16 cmd_flags; 1933 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1934 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1935 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1936 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1937 u8 reserved[14]; 1938 }; 1939 1940 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1941 1942 /* Set OEM mode (direct 0x0905) */ 1943 struct i40e_aqc_alternate_set_mode { 1944 __le32 mode; 1945 #define I40E_AQ_ALTERNATE_MODE_NONE 0 1946 #define I40E_AQ_ALTERNATE_MODE_OEM 1 1947 u8 reserved[12]; 1948 }; 1949 1950 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1951 1952 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1953 1954 /* async events 0x10xx */ 1955 1956 /* Lan Queue Overflow Event (direct, 0x1001) */ 1957 struct i40e_aqc_lan_overflow { 1958 __le32 prtdcb_rupto; 1959 __le32 otx_ctl; 1960 u8 reserved[8]; 1961 }; 1962 1963 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1964 1965 /* Get LLDP MIB (indirect 0x0A00) */ 1966 struct i40e_aqc_lldp_get_mib { 1967 u8 type; 1968 u8 reserved1; 1969 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1970 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 1971 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 1972 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1973 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1974 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1975 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1976 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1977 #define I40E_AQ_LLDP_TX_SHIFT 0x4 1978 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1979 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 1980 __le16 local_len; 1981 __le16 remote_len; 1982 u8 reserved2[2]; 1983 __le32 addr_high; 1984 __le32 addr_low; 1985 }; 1986 1987 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1988 1989 /* Configure LLDP MIB Change Event (direct 0x0A01) 1990 * also used for the event (with type in the command field) 1991 */ 1992 struct i40e_aqc_lldp_update_mib { 1993 u8 command; 1994 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1995 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1996 u8 reserved[7]; 1997 __le32 addr_high; 1998 __le32 addr_low; 1999 }; 2000 2001 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2002 2003 /* Add LLDP TLV (indirect 0x0A02) 2004 * Delete LLDP TLV (indirect 0x0A04) 2005 */ 2006 struct i40e_aqc_lldp_add_tlv { 2007 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2008 u8 reserved1[1]; 2009 __le16 len; 2010 u8 reserved2[4]; 2011 __le32 addr_high; 2012 __le32 addr_low; 2013 }; 2014 2015 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2016 2017 /* Update LLDP TLV (indirect 0x0A03) */ 2018 struct i40e_aqc_lldp_update_tlv { 2019 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2020 u8 reserved; 2021 __le16 old_len; 2022 __le16 new_offset; 2023 __le16 new_len; 2024 __le32 addr_high; 2025 __le32 addr_low; 2026 }; 2027 2028 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2029 2030 /* Stop LLDP (direct 0x0A05) */ 2031 struct i40e_aqc_lldp_stop { 2032 u8 command; 2033 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2034 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2035 u8 reserved[15]; 2036 }; 2037 2038 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2039 2040 /* Start LLDP (direct 0x0A06) */ 2041 2042 struct i40e_aqc_lldp_start { 2043 u8 command; 2044 #define I40E_AQ_LLDP_AGENT_START 0x1 2045 u8 reserved[15]; 2046 }; 2047 2048 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2049 2050 /* Get CEE DCBX Oper Config (0x0A07) 2051 * uses the generic descriptor struct 2052 * returns below as indirect response 2053 */ 2054 2055 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2056 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2057 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2058 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2059 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2060 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2061 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2062 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2063 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2064 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2065 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2066 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2067 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2068 u8 reserved1; 2069 u8 oper_num_tc; 2070 u8 oper_prio_tc[4]; 2071 u8 reserved2; 2072 u8 oper_tc_bw[8]; 2073 u8 oper_pfc_en; 2074 u8 reserved3; 2075 __le16 oper_app_prio; 2076 u8 reserved4; 2077 __le16 tlv_status; 2078 }; 2079 2080 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2081 2082 struct i40e_aqc_get_cee_dcb_cfg_resp { 2083 u8 oper_num_tc; 2084 u8 oper_prio_tc[4]; 2085 u8 oper_tc_bw[8]; 2086 u8 oper_pfc_en; 2087 __le16 oper_app_prio; 2088 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2089 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2090 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2091 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2092 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2093 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2094 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2095 __le32 tlv_status; 2096 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2097 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2098 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2099 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2100 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2101 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2102 u8 reserved[12]; 2103 }; 2104 2105 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2106 2107 /* Set Local LLDP MIB (indirect 0x0A08) 2108 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2109 */ 2110 struct i40e_aqc_lldp_set_local_mib { 2111 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2112 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2113 u8 type; 2114 u8 reserved0; 2115 __le16 length; 2116 u8 reserved1[4]; 2117 __le32 address_high; 2118 __le32 address_low; 2119 }; 2120 2121 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2122 2123 /* Stop/Start LLDP Agent (direct 0x0A09) 2124 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2125 */ 2126 struct i40e_aqc_lldp_stop_start_specific_agent { 2127 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2128 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2129 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2130 u8 command; 2131 u8 reserved[15]; 2132 }; 2133 2134 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2135 2136 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2137 struct i40e_aqc_add_udp_tunnel { 2138 __le16 udp_port; 2139 u8 reserved0[3]; 2140 u8 protocol_type; 2141 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2142 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2143 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2144 u8 reserved1[10]; 2145 }; 2146 2147 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2148 2149 struct i40e_aqc_add_udp_tunnel_completion { 2150 __le16 udp_port; 2151 u8 filter_entry_index; 2152 u8 multiple_pfs; 2153 #define I40E_AQC_SINGLE_PF 0x0 2154 #define I40E_AQC_MULTIPLE_PFS 0x1 2155 u8 total_filters; 2156 u8 reserved[11]; 2157 }; 2158 2159 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2160 2161 /* remove UDP Tunnel command (0x0B01) */ 2162 struct i40e_aqc_remove_udp_tunnel { 2163 u8 reserved[2]; 2164 u8 index; /* 0 to 15 */ 2165 u8 reserved2[13]; 2166 }; 2167 2168 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2169 2170 struct i40e_aqc_del_udp_tunnel_completion { 2171 __le16 udp_port; 2172 u8 index; /* 0 to 15 */ 2173 u8 multiple_pfs; 2174 u8 total_filters_used; 2175 u8 reserved1[11]; 2176 }; 2177 2178 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2179 2180 /* tunnel key structure 0x0B10 */ 2181 2182 struct i40e_aqc_tunnel_key_structure { 2183 u8 key1_off; 2184 u8 key2_off; 2185 u8 key1_len; /* 0 to 15 */ 2186 u8 key2_len; /* 0 to 15 */ 2187 u8 flags; 2188 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2189 /* response flags */ 2190 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2191 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2192 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2193 u8 network_key_index; 2194 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2195 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2196 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2197 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2198 u8 reserved[10]; 2199 }; 2200 2201 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2202 2203 /* OEM mode commands (direct 0xFE0x) */ 2204 struct i40e_aqc_oem_param_change { 2205 __le32 param_type; 2206 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2207 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2208 #define I40E_AQ_OEM_PARAM_MAC 2 2209 __le32 param_value1; 2210 __le16 param_value2; 2211 u8 reserved[6]; 2212 }; 2213 2214 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2215 2216 struct i40e_aqc_oem_state_change { 2217 __le32 state; 2218 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2219 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2220 u8 reserved[12]; 2221 }; 2222 2223 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2224 2225 /* Initialize OCSD (0xFE02, direct) */ 2226 struct i40e_aqc_opc_oem_ocsd_initialize { 2227 u8 type_status; 2228 u8 reserved1[3]; 2229 __le32 ocsd_memory_block_addr_high; 2230 __le32 ocsd_memory_block_addr_low; 2231 __le32 requested_update_interval; 2232 }; 2233 2234 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2235 2236 /* Initialize OCBB (0xFE03, direct) */ 2237 struct i40e_aqc_opc_oem_ocbb_initialize { 2238 u8 type_status; 2239 u8 reserved1[3]; 2240 __le32 ocbb_memory_block_addr_high; 2241 __le32 ocbb_memory_block_addr_low; 2242 u8 reserved2[4]; 2243 }; 2244 2245 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2246 2247 /* debug commands */ 2248 2249 /* get device id (0xFF00) uses the generic structure */ 2250 2251 /* set test more (0xFF01, internal) */ 2252 2253 struct i40e_acq_set_test_mode { 2254 u8 mode; 2255 #define I40E_AQ_TEST_PARTIAL 0 2256 #define I40E_AQ_TEST_FULL 1 2257 #define I40E_AQ_TEST_NVM 2 2258 u8 reserved[3]; 2259 u8 command; 2260 #define I40E_AQ_TEST_OPEN 0 2261 #define I40E_AQ_TEST_CLOSE 1 2262 #define I40E_AQ_TEST_INC 2 2263 u8 reserved2[3]; 2264 __le32 address_high; 2265 __le32 address_low; 2266 }; 2267 2268 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2269 2270 /* Debug Read Register command (0xFF03) 2271 * Debug Write Register command (0xFF04) 2272 */ 2273 struct i40e_aqc_debug_reg_read_write { 2274 __le32 reserved; 2275 __le32 address; 2276 __le32 value_high; 2277 __le32 value_low; 2278 }; 2279 2280 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2281 2282 /* Scatter/gather Reg Read (indirect 0xFF05) 2283 * Scatter/gather Reg Write (indirect 0xFF06) 2284 */ 2285 2286 /* i40e_aq_desc is used for the command */ 2287 struct i40e_aqc_debug_reg_sg_element_data { 2288 __le32 address; 2289 __le32 value; 2290 }; 2291 2292 /* Debug Modify register (direct 0xFF07) */ 2293 struct i40e_aqc_debug_modify_reg { 2294 __le32 address; 2295 __le32 value; 2296 __le32 clear_mask; 2297 __le32 set_mask; 2298 }; 2299 2300 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2301 2302 /* dump internal data (0xFF08, indirect) */ 2303 2304 #define I40E_AQ_CLUSTER_ID_AUX 0 2305 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2306 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2307 #define I40E_AQ_CLUSTER_ID_HMC 3 2308 #define I40E_AQ_CLUSTER_ID_MAC0 4 2309 #define I40E_AQ_CLUSTER_ID_MAC1 5 2310 #define I40E_AQ_CLUSTER_ID_MAC2 6 2311 #define I40E_AQ_CLUSTER_ID_MAC3 7 2312 #define I40E_AQ_CLUSTER_ID_DCB 8 2313 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2314 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2315 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2316 2317 struct i40e_aqc_debug_dump_internals { 2318 u8 cluster_id; 2319 u8 table_id; 2320 __le16 data_size; 2321 __le32 idx; 2322 __le32 address_high; 2323 __le32 address_low; 2324 }; 2325 2326 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2327 2328 struct i40e_aqc_debug_modify_internals { 2329 u8 cluster_id; 2330 u8 cluster_specific_params[7]; 2331 __le32 address_high; 2332 __le32 address_low; 2333 }; 2334 2335 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2336 2337 #endif 2338