1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_ADMINQ_H_ 5 #define _I40E_ADMINQ_H_ 6 7 #include <linux/mutex.h> 8 #include "i40e_alloc.h" 9 #include "i40e_adminq_cmd.h" 10 11 #define I40E_ADMINQ_DESC(R, i) \ 12 (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i])) 13 14 #define I40E_ADMINQ_DESC_ALIGNMENT 4096 15 16 struct i40e_adminq_ring { 17 struct i40e_virt_mem dma_head; /* space for dma structures */ 18 struct i40e_dma_mem desc_buf; /* descriptor ring memory */ 19 struct i40e_virt_mem cmd_buf; /* command buffer memory */ 20 21 union { 22 struct i40e_dma_mem *asq_bi; 23 struct i40e_dma_mem *arq_bi; 24 } r; 25 26 u16 count; /* Number of descriptors */ 27 u16 rx_buf_len; /* Admin Receive Queue buffer length */ 28 29 /* used for interrupt processing */ 30 u16 next_to_use; 31 u16 next_to_clean; 32 }; 33 34 /* ASQ transaction details */ 35 struct i40e_asq_cmd_details { 36 void *callback; /* cast from type I40E_ADMINQ_CALLBACK */ 37 u64 cookie; 38 u16 flags_ena; 39 u16 flags_dis; 40 bool async; 41 bool postpone; 42 struct i40e_aq_desc *wb_desc; 43 }; 44 45 #define I40E_ADMINQ_DETAILS(R, i) \ 46 (&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i])) 47 48 /* ARQ event information */ 49 struct i40e_arq_event_info { 50 struct i40e_aq_desc desc; 51 u16 msg_len; 52 u16 buf_len; 53 u8 *msg_buf; 54 }; 55 56 /* Admin Queue information */ 57 struct i40e_adminq_info { 58 struct i40e_adminq_ring arq; /* receive queue */ 59 struct i40e_adminq_ring asq; /* send queue */ 60 u32 asq_cmd_timeout; /* send queue cmd write back timeout*/ 61 u16 num_arq_entries; /* receive queue depth */ 62 u16 num_asq_entries; /* send queue depth */ 63 u16 arq_buf_size; /* receive queue buffer size */ 64 u16 asq_buf_size; /* send queue buffer size */ 65 u16 fw_maj_ver; /* firmware major version */ 66 u16 fw_min_ver; /* firmware minor version */ 67 u32 fw_build; /* firmware build number */ 68 u16 api_maj_ver; /* api major version */ 69 u16 api_min_ver; /* api minor version */ 70 71 struct mutex asq_mutex; /* Send queue lock */ 72 struct mutex arq_mutex; /* Receive queue lock */ 73 74 /* last status values on send and receive queues */ 75 enum i40e_admin_queue_err asq_last_status; 76 enum i40e_admin_queue_err arq_last_status; 77 }; 78 79 /** 80 * i40e_aq_rc_to_posix - convert errors to user-land codes 81 * @aq_ret: AdminQ handler error code can override aq_rc 82 * @aq_rc: AdminQ firmware error code to convert 83 **/ 84 static inline int i40e_aq_rc_to_posix(int aq_ret, int aq_rc) 85 { 86 int aq_to_posix[] = { 87 0, /* I40E_AQ_RC_OK */ 88 -EPERM, /* I40E_AQ_RC_EPERM */ 89 -ENOENT, /* I40E_AQ_RC_ENOENT */ 90 -ESRCH, /* I40E_AQ_RC_ESRCH */ 91 -EINTR, /* I40E_AQ_RC_EINTR */ 92 -EIO, /* I40E_AQ_RC_EIO */ 93 -ENXIO, /* I40E_AQ_RC_ENXIO */ 94 -E2BIG, /* I40E_AQ_RC_E2BIG */ 95 -EAGAIN, /* I40E_AQ_RC_EAGAIN */ 96 -ENOMEM, /* I40E_AQ_RC_ENOMEM */ 97 -EACCES, /* I40E_AQ_RC_EACCES */ 98 -EFAULT, /* I40E_AQ_RC_EFAULT */ 99 -EBUSY, /* I40E_AQ_RC_EBUSY */ 100 -EEXIST, /* I40E_AQ_RC_EEXIST */ 101 -EINVAL, /* I40E_AQ_RC_EINVAL */ 102 -ENOTTY, /* I40E_AQ_RC_ENOTTY */ 103 -ENOSPC, /* I40E_AQ_RC_ENOSPC */ 104 -ENOSYS, /* I40E_AQ_RC_ENOSYS */ 105 -ERANGE, /* I40E_AQ_RC_ERANGE */ 106 -EPIPE, /* I40E_AQ_RC_EFLUSHED */ 107 -ESPIPE, /* I40E_AQ_RC_BAD_ADDR */ 108 -EROFS, /* I40E_AQ_RC_EMODE */ 109 -EFBIG, /* I40E_AQ_RC_EFBIG */ 110 }; 111 112 if (!((u32)aq_rc < (sizeof(aq_to_posix) / sizeof((aq_to_posix)[0])))) 113 return -ERANGE; 114 115 return aq_to_posix[aq_rc]; 116 } 117 118 /* general information */ 119 #define I40E_AQ_LARGE_BUF 512 120 #define I40E_ASQ_CMD_TIMEOUT 250000 /* usecs */ 121 122 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, 123 u16 opcode); 124 125 #endif /* _I40E_ADMINQ_H_ */ 126