xref: /linux/drivers/net/ethernet/intel/i40e/i40e_adminq.c (revision b2d0f5d5dc53532e6f07bc546a476a55ebdfe0f3)
1 /*******************************************************************************
2  *
3  * Intel Ethernet Controller XL710 Family Linux Driver
4  * Copyright(c) 2013 - 2016 Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * The full GNU General Public License is included in this distribution in
19  * the file called "COPYING".
20  *
21  * Contact Information:
22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  ******************************************************************************/
26 
27 #include "i40e_status.h"
28 #include "i40e_type.h"
29 #include "i40e_register.h"
30 #include "i40e_adminq.h"
31 #include "i40e_prototype.h"
32 
33 static void i40e_resume_aq(struct i40e_hw *hw);
34 
35 /**
36  *  i40e_adminq_init_regs - Initialize AdminQ registers
37  *  @hw: pointer to the hardware structure
38  *
39  *  This assumes the alloc_asq and alloc_arq functions have already been called
40  **/
41 static void i40e_adminq_init_regs(struct i40e_hw *hw)
42 {
43 	/* set head and tail registers in our local struct */
44 	if (i40e_is_vf(hw)) {
45 		hw->aq.asq.tail = I40E_VF_ATQT1;
46 		hw->aq.asq.head = I40E_VF_ATQH1;
47 		hw->aq.asq.len  = I40E_VF_ATQLEN1;
48 		hw->aq.asq.bal  = I40E_VF_ATQBAL1;
49 		hw->aq.asq.bah  = I40E_VF_ATQBAH1;
50 		hw->aq.arq.tail = I40E_VF_ARQT1;
51 		hw->aq.arq.head = I40E_VF_ARQH1;
52 		hw->aq.arq.len  = I40E_VF_ARQLEN1;
53 		hw->aq.arq.bal  = I40E_VF_ARQBAL1;
54 		hw->aq.arq.bah  = I40E_VF_ARQBAH1;
55 	} else {
56 		hw->aq.asq.tail = I40E_PF_ATQT;
57 		hw->aq.asq.head = I40E_PF_ATQH;
58 		hw->aq.asq.len  = I40E_PF_ATQLEN;
59 		hw->aq.asq.bal  = I40E_PF_ATQBAL;
60 		hw->aq.asq.bah  = I40E_PF_ATQBAH;
61 		hw->aq.arq.tail = I40E_PF_ARQT;
62 		hw->aq.arq.head = I40E_PF_ARQH;
63 		hw->aq.arq.len  = I40E_PF_ARQLEN;
64 		hw->aq.arq.bal  = I40E_PF_ARQBAL;
65 		hw->aq.arq.bah  = I40E_PF_ARQBAH;
66 	}
67 }
68 
69 /**
70  *  i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
71  *  @hw: pointer to the hardware structure
72  **/
73 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
74 {
75 	i40e_status ret_code;
76 
77 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
78 					 i40e_mem_atq_ring,
79 					 (hw->aq.num_asq_entries *
80 					 sizeof(struct i40e_aq_desc)),
81 					 I40E_ADMINQ_DESC_ALIGNMENT);
82 	if (ret_code)
83 		return ret_code;
84 
85 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
86 					  (hw->aq.num_asq_entries *
87 					  sizeof(struct i40e_asq_cmd_details)));
88 	if (ret_code) {
89 		i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
90 		return ret_code;
91 	}
92 
93 	return ret_code;
94 }
95 
96 /**
97  *  i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
98  *  @hw: pointer to the hardware structure
99  **/
100 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
101 {
102 	i40e_status ret_code;
103 
104 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
105 					 i40e_mem_arq_ring,
106 					 (hw->aq.num_arq_entries *
107 					 sizeof(struct i40e_aq_desc)),
108 					 I40E_ADMINQ_DESC_ALIGNMENT);
109 
110 	return ret_code;
111 }
112 
113 /**
114  *  i40e_free_adminq_asq - Free Admin Queue send rings
115  *  @hw: pointer to the hardware structure
116  *
117  *  This assumes the posted send buffers have already been cleaned
118  *  and de-allocated
119  **/
120 static void i40e_free_adminq_asq(struct i40e_hw *hw)
121 {
122 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
123 }
124 
125 /**
126  *  i40e_free_adminq_arq - Free Admin Queue receive rings
127  *  @hw: pointer to the hardware structure
128  *
129  *  This assumes the posted receive buffers have already been cleaned
130  *  and de-allocated
131  **/
132 static void i40e_free_adminq_arq(struct i40e_hw *hw)
133 {
134 	i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
135 }
136 
137 /**
138  *  i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
139  *  @hw: pointer to the hardware structure
140  **/
141 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
142 {
143 	i40e_status ret_code;
144 	struct i40e_aq_desc *desc;
145 	struct i40e_dma_mem *bi;
146 	int i;
147 
148 	/* We'll be allocating the buffer info memory first, then we can
149 	 * allocate the mapped buffers for the event processing
150 	 */
151 
152 	/* buffer_info structures do not need alignment */
153 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
154 		(hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
155 	if (ret_code)
156 		goto alloc_arq_bufs;
157 	hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
158 
159 	/* allocate the mapped buffers */
160 	for (i = 0; i < hw->aq.num_arq_entries; i++) {
161 		bi = &hw->aq.arq.r.arq_bi[i];
162 		ret_code = i40e_allocate_dma_mem(hw, bi,
163 						 i40e_mem_arq_buf,
164 						 hw->aq.arq_buf_size,
165 						 I40E_ADMINQ_DESC_ALIGNMENT);
166 		if (ret_code)
167 			goto unwind_alloc_arq_bufs;
168 
169 		/* now configure the descriptors for use */
170 		desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
171 
172 		desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
173 		if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
174 			desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
175 		desc->opcode = 0;
176 		/* This is in accordance with Admin queue design, there is no
177 		 * register for buffer size configuration
178 		 */
179 		desc->datalen = cpu_to_le16((u16)bi->size);
180 		desc->retval = 0;
181 		desc->cookie_high = 0;
182 		desc->cookie_low = 0;
183 		desc->params.external.addr_high =
184 			cpu_to_le32(upper_32_bits(bi->pa));
185 		desc->params.external.addr_low =
186 			cpu_to_le32(lower_32_bits(bi->pa));
187 		desc->params.external.param0 = 0;
188 		desc->params.external.param1 = 0;
189 	}
190 
191 alloc_arq_bufs:
192 	return ret_code;
193 
194 unwind_alloc_arq_bufs:
195 	/* don't try to free the one that failed... */
196 	i--;
197 	for (; i >= 0; i--)
198 		i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
199 	i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
200 
201 	return ret_code;
202 }
203 
204 /**
205  *  i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
206  *  @hw: pointer to the hardware structure
207  **/
208 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
209 {
210 	i40e_status ret_code;
211 	struct i40e_dma_mem *bi;
212 	int i;
213 
214 	/* No mapped memory needed yet, just the buffer info structures */
215 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
216 		(hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
217 	if (ret_code)
218 		goto alloc_asq_bufs;
219 	hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
220 
221 	/* allocate the mapped buffers */
222 	for (i = 0; i < hw->aq.num_asq_entries; i++) {
223 		bi = &hw->aq.asq.r.asq_bi[i];
224 		ret_code = i40e_allocate_dma_mem(hw, bi,
225 						 i40e_mem_asq_buf,
226 						 hw->aq.asq_buf_size,
227 						 I40E_ADMINQ_DESC_ALIGNMENT);
228 		if (ret_code)
229 			goto unwind_alloc_asq_bufs;
230 	}
231 alloc_asq_bufs:
232 	return ret_code;
233 
234 unwind_alloc_asq_bufs:
235 	/* don't try to free the one that failed... */
236 	i--;
237 	for (; i >= 0; i--)
238 		i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
239 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
240 
241 	return ret_code;
242 }
243 
244 /**
245  *  i40e_free_arq_bufs - Free receive queue buffer info elements
246  *  @hw: pointer to the hardware structure
247  **/
248 static void i40e_free_arq_bufs(struct i40e_hw *hw)
249 {
250 	int i;
251 
252 	/* free descriptors */
253 	for (i = 0; i < hw->aq.num_arq_entries; i++)
254 		i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
255 
256 	/* free the descriptor memory */
257 	i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
258 
259 	/* free the dma header */
260 	i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
261 }
262 
263 /**
264  *  i40e_free_asq_bufs - Free send queue buffer info elements
265  *  @hw: pointer to the hardware structure
266  **/
267 static void i40e_free_asq_bufs(struct i40e_hw *hw)
268 {
269 	int i;
270 
271 	/* only unmap if the address is non-NULL */
272 	for (i = 0; i < hw->aq.num_asq_entries; i++)
273 		if (hw->aq.asq.r.asq_bi[i].pa)
274 			i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
275 
276 	/* free the buffer info list */
277 	i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
278 
279 	/* free the descriptor memory */
280 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
281 
282 	/* free the dma header */
283 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
284 }
285 
286 /**
287  *  i40e_config_asq_regs - configure ASQ registers
288  *  @hw: pointer to the hardware structure
289  *
290  *  Configure base address and length registers for the transmit queue
291  **/
292 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
293 {
294 	i40e_status ret_code = 0;
295 	u32 reg = 0;
296 
297 	/* Clear Head and Tail */
298 	wr32(hw, hw->aq.asq.head, 0);
299 	wr32(hw, hw->aq.asq.tail, 0);
300 
301 	/* set starting point */
302 	wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
303 				  I40E_PF_ATQLEN_ATQENABLE_MASK));
304 	wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
305 	wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
306 
307 	/* Check one register to verify that config was applied */
308 	reg = rd32(hw, hw->aq.asq.bal);
309 	if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
310 		ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
311 
312 	return ret_code;
313 }
314 
315 /**
316  *  i40e_config_arq_regs - ARQ register configuration
317  *  @hw: pointer to the hardware structure
318  *
319  * Configure base address and length registers for the receive (event queue)
320  **/
321 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
322 {
323 	i40e_status ret_code = 0;
324 	u32 reg = 0;
325 
326 	/* Clear Head and Tail */
327 	wr32(hw, hw->aq.arq.head, 0);
328 	wr32(hw, hw->aq.arq.tail, 0);
329 
330 	/* set starting point */
331 	wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
332 				  I40E_PF_ARQLEN_ARQENABLE_MASK));
333 	wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
334 	wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
335 
336 	/* Update tail in the HW to post pre-allocated buffers */
337 	wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
338 
339 	/* Check one register to verify that config was applied */
340 	reg = rd32(hw, hw->aq.arq.bal);
341 	if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
342 		ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
343 
344 	return ret_code;
345 }
346 
347 /**
348  *  i40e_init_asq - main initialization routine for ASQ
349  *  @hw: pointer to the hardware structure
350  *
351  *  This is the main initialization routine for the Admin Send Queue
352  *  Prior to calling this function, drivers *MUST* set the following fields
353  *  in the hw->aq structure:
354  *     - hw->aq.num_asq_entries
355  *     - hw->aq.arq_buf_size
356  *
357  *  Do *NOT* hold the lock when calling this as the memory allocation routines
358  *  called are not going to be atomic context safe
359  **/
360 static i40e_status i40e_init_asq(struct i40e_hw *hw)
361 {
362 	i40e_status ret_code = 0;
363 
364 	if (hw->aq.asq.count > 0) {
365 		/* queue already initialized */
366 		ret_code = I40E_ERR_NOT_READY;
367 		goto init_adminq_exit;
368 	}
369 
370 	/* verify input for valid configuration */
371 	if ((hw->aq.num_asq_entries == 0) ||
372 	    (hw->aq.asq_buf_size == 0)) {
373 		ret_code = I40E_ERR_CONFIG;
374 		goto init_adminq_exit;
375 	}
376 
377 	hw->aq.asq.next_to_use = 0;
378 	hw->aq.asq.next_to_clean = 0;
379 
380 	/* allocate the ring memory */
381 	ret_code = i40e_alloc_adminq_asq_ring(hw);
382 	if (ret_code)
383 		goto init_adminq_exit;
384 
385 	/* allocate buffers in the rings */
386 	ret_code = i40e_alloc_asq_bufs(hw);
387 	if (ret_code)
388 		goto init_adminq_free_rings;
389 
390 	/* initialize base registers */
391 	ret_code = i40e_config_asq_regs(hw);
392 	if (ret_code)
393 		goto init_adminq_free_rings;
394 
395 	/* success! */
396 	hw->aq.asq.count = hw->aq.num_asq_entries;
397 	goto init_adminq_exit;
398 
399 init_adminq_free_rings:
400 	i40e_free_adminq_asq(hw);
401 
402 init_adminq_exit:
403 	return ret_code;
404 }
405 
406 /**
407  *  i40e_init_arq - initialize ARQ
408  *  @hw: pointer to the hardware structure
409  *
410  *  The main initialization routine for the Admin Receive (Event) Queue.
411  *  Prior to calling this function, drivers *MUST* set the following fields
412  *  in the hw->aq structure:
413  *     - hw->aq.num_asq_entries
414  *     - hw->aq.arq_buf_size
415  *
416  *  Do *NOT* hold the lock when calling this as the memory allocation routines
417  *  called are not going to be atomic context safe
418  **/
419 static i40e_status i40e_init_arq(struct i40e_hw *hw)
420 {
421 	i40e_status ret_code = 0;
422 
423 	if (hw->aq.arq.count > 0) {
424 		/* queue already initialized */
425 		ret_code = I40E_ERR_NOT_READY;
426 		goto init_adminq_exit;
427 	}
428 
429 	/* verify input for valid configuration */
430 	if ((hw->aq.num_arq_entries == 0) ||
431 	    (hw->aq.arq_buf_size == 0)) {
432 		ret_code = I40E_ERR_CONFIG;
433 		goto init_adminq_exit;
434 	}
435 
436 	hw->aq.arq.next_to_use = 0;
437 	hw->aq.arq.next_to_clean = 0;
438 
439 	/* allocate the ring memory */
440 	ret_code = i40e_alloc_adminq_arq_ring(hw);
441 	if (ret_code)
442 		goto init_adminq_exit;
443 
444 	/* allocate buffers in the rings */
445 	ret_code = i40e_alloc_arq_bufs(hw);
446 	if (ret_code)
447 		goto init_adminq_free_rings;
448 
449 	/* initialize base registers */
450 	ret_code = i40e_config_arq_regs(hw);
451 	if (ret_code)
452 		goto init_adminq_free_rings;
453 
454 	/* success! */
455 	hw->aq.arq.count = hw->aq.num_arq_entries;
456 	goto init_adminq_exit;
457 
458 init_adminq_free_rings:
459 	i40e_free_adminq_arq(hw);
460 
461 init_adminq_exit:
462 	return ret_code;
463 }
464 
465 /**
466  *  i40e_shutdown_asq - shutdown the ASQ
467  *  @hw: pointer to the hardware structure
468  *
469  *  The main shutdown routine for the Admin Send Queue
470  **/
471 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
472 {
473 	i40e_status ret_code = 0;
474 
475 	mutex_lock(&hw->aq.asq_mutex);
476 
477 	if (hw->aq.asq.count == 0) {
478 		ret_code = I40E_ERR_NOT_READY;
479 		goto shutdown_asq_out;
480 	}
481 
482 	/* Stop firmware AdminQ processing */
483 	wr32(hw, hw->aq.asq.head, 0);
484 	wr32(hw, hw->aq.asq.tail, 0);
485 	wr32(hw, hw->aq.asq.len, 0);
486 	wr32(hw, hw->aq.asq.bal, 0);
487 	wr32(hw, hw->aq.asq.bah, 0);
488 
489 	hw->aq.asq.count = 0; /* to indicate uninitialized queue */
490 
491 	/* free ring buffers */
492 	i40e_free_asq_bufs(hw);
493 
494 shutdown_asq_out:
495 	mutex_unlock(&hw->aq.asq_mutex);
496 	return ret_code;
497 }
498 
499 /**
500  *  i40e_shutdown_arq - shutdown ARQ
501  *  @hw: pointer to the hardware structure
502  *
503  *  The main shutdown routine for the Admin Receive Queue
504  **/
505 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
506 {
507 	i40e_status ret_code = 0;
508 
509 	mutex_lock(&hw->aq.arq_mutex);
510 
511 	if (hw->aq.arq.count == 0) {
512 		ret_code = I40E_ERR_NOT_READY;
513 		goto shutdown_arq_out;
514 	}
515 
516 	/* Stop firmware AdminQ processing */
517 	wr32(hw, hw->aq.arq.head, 0);
518 	wr32(hw, hw->aq.arq.tail, 0);
519 	wr32(hw, hw->aq.arq.len, 0);
520 	wr32(hw, hw->aq.arq.bal, 0);
521 	wr32(hw, hw->aq.arq.bah, 0);
522 
523 	hw->aq.arq.count = 0; /* to indicate uninitialized queue */
524 
525 	/* free ring buffers */
526 	i40e_free_arq_bufs(hw);
527 
528 shutdown_arq_out:
529 	mutex_unlock(&hw->aq.arq_mutex);
530 	return ret_code;
531 }
532 
533 /**
534  *  i40e_init_adminq - main initialization routine for Admin Queue
535  *  @hw: pointer to the hardware structure
536  *
537  *  Prior to calling this function, drivers *MUST* set the following fields
538  *  in the hw->aq structure:
539  *     - hw->aq.num_asq_entries
540  *     - hw->aq.num_arq_entries
541  *     - hw->aq.arq_buf_size
542  *     - hw->aq.asq_buf_size
543  **/
544 i40e_status i40e_init_adminq(struct i40e_hw *hw)
545 {
546 	u16 cfg_ptr, oem_hi, oem_lo;
547 	u16 eetrack_lo, eetrack_hi;
548 	i40e_status ret_code;
549 	int retry = 0;
550 
551 	/* verify input for valid configuration */
552 	if ((hw->aq.num_arq_entries == 0) ||
553 	    (hw->aq.num_asq_entries == 0) ||
554 	    (hw->aq.arq_buf_size == 0) ||
555 	    (hw->aq.asq_buf_size == 0)) {
556 		ret_code = I40E_ERR_CONFIG;
557 		goto init_adminq_exit;
558 	}
559 
560 	/* Set up register offsets */
561 	i40e_adminq_init_regs(hw);
562 
563 	/* setup ASQ command write back timeout */
564 	hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
565 
566 	/* allocate the ASQ */
567 	ret_code = i40e_init_asq(hw);
568 	if (ret_code)
569 		goto init_adminq_destroy_locks;
570 
571 	/* allocate the ARQ */
572 	ret_code = i40e_init_arq(hw);
573 	if (ret_code)
574 		goto init_adminq_free_asq;
575 
576 	/* There are some cases where the firmware may not be quite ready
577 	 * for AdminQ operations, so we retry the AdminQ setup a few times
578 	 * if we see timeouts in this first AQ call.
579 	 */
580 	do {
581 		ret_code = i40e_aq_get_firmware_version(hw,
582 							&hw->aq.fw_maj_ver,
583 							&hw->aq.fw_min_ver,
584 							&hw->aq.fw_build,
585 							&hw->aq.api_maj_ver,
586 							&hw->aq.api_min_ver,
587 							NULL);
588 		if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)
589 			break;
590 		retry++;
591 		msleep(100);
592 		i40e_resume_aq(hw);
593 	} while (retry < 10);
594 	if (ret_code != I40E_SUCCESS)
595 		goto init_adminq_free_arq;
596 
597 	/* get the NVM version info */
598 	i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION,
599 			   &hw->nvm.version);
600 	i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
601 	i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
602 	hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
603 	i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr);
604 	i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF),
605 			   &oem_hi);
606 	i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)),
607 			   &oem_lo);
608 	hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
609 
610 	if (hw->mac.type == I40E_MAC_XL710 &&
611 	    hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
612 	    hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
613 		hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE;
614 	}
615 
616 	/* The ability to RX (not drop) 802.1ad frames was added in API 1.7 */
617 	if (hw->aq.api_maj_ver > 1 ||
618 	    (hw->aq.api_maj_ver == 1 &&
619 	     hw->aq.api_min_ver >= 7))
620 		hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE;
621 
622 	if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
623 		ret_code = I40E_ERR_FIRMWARE_API_VERSION;
624 		goto init_adminq_free_arq;
625 	}
626 
627 	/* pre-emptive resource lock release */
628 	i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
629 	hw->nvm_release_on_done = false;
630 	hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
631 
632 	ret_code = 0;
633 
634 	/* success! */
635 	goto init_adminq_exit;
636 
637 init_adminq_free_arq:
638 	i40e_shutdown_arq(hw);
639 init_adminq_free_asq:
640 	i40e_shutdown_asq(hw);
641 init_adminq_destroy_locks:
642 
643 init_adminq_exit:
644 	return ret_code;
645 }
646 
647 /**
648  *  i40e_shutdown_adminq - shutdown routine for the Admin Queue
649  *  @hw: pointer to the hardware structure
650  **/
651 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw)
652 {
653 	i40e_status ret_code = 0;
654 
655 	if (i40e_check_asq_alive(hw))
656 		i40e_aq_queue_shutdown(hw, true);
657 
658 	i40e_shutdown_asq(hw);
659 	i40e_shutdown_arq(hw);
660 
661 	if (hw->nvm_buff.va)
662 		i40e_free_virt_mem(hw, &hw->nvm_buff);
663 
664 	return ret_code;
665 }
666 
667 /**
668  *  i40e_clean_asq - cleans Admin send queue
669  *  @hw: pointer to the hardware structure
670  *
671  *  returns the number of free desc
672  **/
673 static u16 i40e_clean_asq(struct i40e_hw *hw)
674 {
675 	struct i40e_adminq_ring *asq = &(hw->aq.asq);
676 	struct i40e_asq_cmd_details *details;
677 	u16 ntc = asq->next_to_clean;
678 	struct i40e_aq_desc desc_cb;
679 	struct i40e_aq_desc *desc;
680 
681 	desc = I40E_ADMINQ_DESC(*asq, ntc);
682 	details = I40E_ADMINQ_DETAILS(*asq, ntc);
683 	while (rd32(hw, hw->aq.asq.head) != ntc) {
684 		i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
685 			   "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
686 
687 		if (details->callback) {
688 			I40E_ADMINQ_CALLBACK cb_func =
689 					(I40E_ADMINQ_CALLBACK)details->callback;
690 			desc_cb = *desc;
691 			cb_func(hw, &desc_cb);
692 		}
693 		memset(desc, 0, sizeof(*desc));
694 		memset(details, 0, sizeof(*details));
695 		ntc++;
696 		if (ntc == asq->count)
697 			ntc = 0;
698 		desc = I40E_ADMINQ_DESC(*asq, ntc);
699 		details = I40E_ADMINQ_DETAILS(*asq, ntc);
700 	}
701 
702 	asq->next_to_clean = ntc;
703 
704 	return I40E_DESC_UNUSED(asq);
705 }
706 
707 /**
708  *  i40e_asq_done - check if FW has processed the Admin Send Queue
709  *  @hw: pointer to the hw struct
710  *
711  *  Returns true if the firmware has processed all descriptors on the
712  *  admin send queue. Returns false if there are still requests pending.
713  **/
714 static bool i40e_asq_done(struct i40e_hw *hw)
715 {
716 	/* AQ designers suggest use of head for better
717 	 * timing reliability than DD bit
718 	 */
719 	return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
720 
721 }
722 
723 /**
724  *  i40e_asq_send_command - send command to Admin Queue
725  *  @hw: pointer to the hw struct
726  *  @desc: prefilled descriptor describing the command (non DMA mem)
727  *  @buff: buffer to use for indirect commands
728  *  @buff_size: size of buffer for indirect commands
729  *  @cmd_details: pointer to command details structure
730  *
731  *  This is the main send command driver routine for the Admin Queue send
732  *  queue.  It runs the queue, cleans the queue, etc
733  **/
734 i40e_status i40e_asq_send_command(struct i40e_hw *hw,
735 				struct i40e_aq_desc *desc,
736 				void *buff, /* can be NULL */
737 				u16  buff_size,
738 				struct i40e_asq_cmd_details *cmd_details)
739 {
740 	i40e_status status = 0;
741 	struct i40e_dma_mem *dma_buff = NULL;
742 	struct i40e_asq_cmd_details *details;
743 	struct i40e_aq_desc *desc_on_ring;
744 	bool cmd_completed = false;
745 	u16  retval = 0;
746 	u32  val = 0;
747 
748 	mutex_lock(&hw->aq.asq_mutex);
749 
750 	if (hw->aq.asq.count == 0) {
751 		i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
752 			   "AQTX: Admin queue not initialized.\n");
753 		status = I40E_ERR_QUEUE_EMPTY;
754 		goto asq_send_command_error;
755 	}
756 
757 	hw->aq.asq_last_status = I40E_AQ_RC_OK;
758 
759 	val = rd32(hw, hw->aq.asq.head);
760 	if (val >= hw->aq.num_asq_entries) {
761 		i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
762 			   "AQTX: head overrun at %d\n", val);
763 		status = I40E_ERR_QUEUE_EMPTY;
764 		goto asq_send_command_error;
765 	}
766 
767 	details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
768 	if (cmd_details) {
769 		*details = *cmd_details;
770 
771 		/* If the cmd_details are defined copy the cookie.  The
772 		 * cpu_to_le32 is not needed here because the data is ignored
773 		 * by the FW, only used by the driver
774 		 */
775 		if (details->cookie) {
776 			desc->cookie_high =
777 				cpu_to_le32(upper_32_bits(details->cookie));
778 			desc->cookie_low =
779 				cpu_to_le32(lower_32_bits(details->cookie));
780 		}
781 	} else {
782 		memset(details, 0, sizeof(struct i40e_asq_cmd_details));
783 	}
784 
785 	/* clear requested flags and then set additional flags if defined */
786 	desc->flags &= ~cpu_to_le16(details->flags_dis);
787 	desc->flags |= cpu_to_le16(details->flags_ena);
788 
789 	if (buff_size > hw->aq.asq_buf_size) {
790 		i40e_debug(hw,
791 			   I40E_DEBUG_AQ_MESSAGE,
792 			   "AQTX: Invalid buffer size: %d.\n",
793 			   buff_size);
794 		status = I40E_ERR_INVALID_SIZE;
795 		goto asq_send_command_error;
796 	}
797 
798 	if (details->postpone && !details->async) {
799 		i40e_debug(hw,
800 			   I40E_DEBUG_AQ_MESSAGE,
801 			   "AQTX: Async flag not set along with postpone flag");
802 		status = I40E_ERR_PARAM;
803 		goto asq_send_command_error;
804 	}
805 
806 	/* call clean and check queue available function to reclaim the
807 	 * descriptors that were processed by FW, the function returns the
808 	 * number of desc available
809 	 */
810 	/* the clean function called here could be called in a separate thread
811 	 * in case of asynchronous completions
812 	 */
813 	if (i40e_clean_asq(hw) == 0) {
814 		i40e_debug(hw,
815 			   I40E_DEBUG_AQ_MESSAGE,
816 			   "AQTX: Error queue is full.\n");
817 		status = I40E_ERR_ADMIN_QUEUE_FULL;
818 		goto asq_send_command_error;
819 	}
820 
821 	/* initialize the temp desc pointer with the right desc */
822 	desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
823 
824 	/* if the desc is available copy the temp desc to the right place */
825 	*desc_on_ring = *desc;
826 
827 	/* if buff is not NULL assume indirect command */
828 	if (buff != NULL) {
829 		dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
830 		/* copy the user buff into the respective DMA buff */
831 		memcpy(dma_buff->va, buff, buff_size);
832 		desc_on_ring->datalen = cpu_to_le16(buff_size);
833 
834 		/* Update the address values in the desc with the pa value
835 		 * for respective buffer
836 		 */
837 		desc_on_ring->params.external.addr_high =
838 				cpu_to_le32(upper_32_bits(dma_buff->pa));
839 		desc_on_ring->params.external.addr_low =
840 				cpu_to_le32(lower_32_bits(dma_buff->pa));
841 	}
842 
843 	/* bump the tail */
844 	i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
845 	i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
846 		      buff, buff_size);
847 	(hw->aq.asq.next_to_use)++;
848 	if (hw->aq.asq.next_to_use == hw->aq.asq.count)
849 		hw->aq.asq.next_to_use = 0;
850 	if (!details->postpone)
851 		wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
852 
853 	/* if cmd_details are not defined or async flag is not set,
854 	 * we need to wait for desc write back
855 	 */
856 	if (!details->async && !details->postpone) {
857 		u32 total_delay = 0;
858 
859 		do {
860 			/* AQ designers suggest use of head for better
861 			 * timing reliability than DD bit
862 			 */
863 			if (i40e_asq_done(hw))
864 				break;
865 			udelay(50);
866 			total_delay += 50;
867 		} while (total_delay < hw->aq.asq_cmd_timeout);
868 	}
869 
870 	/* if ready, copy the desc back to temp */
871 	if (i40e_asq_done(hw)) {
872 		*desc = *desc_on_ring;
873 		if (buff != NULL)
874 			memcpy(buff, dma_buff->va, buff_size);
875 		retval = le16_to_cpu(desc->retval);
876 		if (retval != 0) {
877 			i40e_debug(hw,
878 				   I40E_DEBUG_AQ_MESSAGE,
879 				   "AQTX: Command completed with error 0x%X.\n",
880 				   retval);
881 
882 			/* strip off FW internal code */
883 			retval &= 0xff;
884 		}
885 		cmd_completed = true;
886 		if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
887 			status = 0;
888 		else
889 			status = I40E_ERR_ADMIN_QUEUE_ERROR;
890 		hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
891 	}
892 
893 	i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
894 		   "AQTX: desc and buffer writeback:\n");
895 	i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
896 
897 	/* save writeback aq if requested */
898 	if (details->wb_desc)
899 		*details->wb_desc = *desc_on_ring;
900 
901 	/* update the error if time out occurred */
902 	if ((!cmd_completed) &&
903 	    (!details->async && !details->postpone)) {
904 		i40e_debug(hw,
905 			   I40E_DEBUG_AQ_MESSAGE,
906 			   "AQTX: Writeback timeout.\n");
907 		status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
908 	}
909 
910 asq_send_command_error:
911 	mutex_unlock(&hw->aq.asq_mutex);
912 	return status;
913 }
914 
915 /**
916  *  i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
917  *  @desc:     pointer to the temp descriptor (non DMA mem)
918  *  @opcode:   the opcode can be used to decide which flags to turn off or on
919  *
920  *  Fill the desc with default values
921  **/
922 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
923 				       u16 opcode)
924 {
925 	/* zero out the desc */
926 	memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
927 	desc->opcode = cpu_to_le16(opcode);
928 	desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);
929 }
930 
931 /**
932  *  i40e_clean_arq_element
933  *  @hw: pointer to the hw struct
934  *  @e: event info from the receive descriptor, includes any buffers
935  *  @pending: number of events that could be left to process
936  *
937  *  This function cleans one Admin Receive Queue element and returns
938  *  the contents through e.  It can also return how many events are
939  *  left to process through 'pending'
940  **/
941 i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
942 					     struct i40e_arq_event_info *e,
943 					     u16 *pending)
944 {
945 	i40e_status ret_code = 0;
946 	u16 ntc = hw->aq.arq.next_to_clean;
947 	struct i40e_aq_desc *desc;
948 	struct i40e_dma_mem *bi;
949 	u16 desc_idx;
950 	u16 datalen;
951 	u16 flags;
952 	u16 ntu;
953 
954 	/* pre-clean the event info */
955 	memset(&e->desc, 0, sizeof(e->desc));
956 
957 	/* take the lock before we start messing with the ring */
958 	mutex_lock(&hw->aq.arq_mutex);
959 
960 	if (hw->aq.arq.count == 0) {
961 		i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
962 			   "AQRX: Admin queue not initialized.\n");
963 		ret_code = I40E_ERR_QUEUE_EMPTY;
964 		goto clean_arq_element_err;
965 	}
966 
967 	/* set next_to_use to head */
968 	ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
969 	if (ntu == ntc) {
970 		/* nothing to do - shouldn't need to update ring's values */
971 		ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
972 		goto clean_arq_element_out;
973 	}
974 
975 	/* now clean the next descriptor */
976 	desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
977 	desc_idx = ntc;
978 
979 	hw->aq.arq_last_status =
980 		(enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
981 	flags = le16_to_cpu(desc->flags);
982 	if (flags & I40E_AQ_FLAG_ERR) {
983 		ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
984 		i40e_debug(hw,
985 			   I40E_DEBUG_AQ_MESSAGE,
986 			   "AQRX: Event received with error 0x%X.\n",
987 			   hw->aq.arq_last_status);
988 	}
989 
990 	e->desc = *desc;
991 	datalen = le16_to_cpu(desc->datalen);
992 	e->msg_len = min(datalen, e->buf_len);
993 	if (e->msg_buf != NULL && (e->msg_len != 0))
994 		memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
995 		       e->msg_len);
996 
997 	i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
998 	i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
999 		      hw->aq.arq_buf_size);
1000 
1001 	/* Restore the original datalen and buffer address in the desc,
1002 	 * FW updates datalen to indicate the event message
1003 	 * size
1004 	 */
1005 	bi = &hw->aq.arq.r.arq_bi[ntc];
1006 	memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
1007 
1008 	desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
1009 	if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
1010 		desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
1011 	desc->datalen = cpu_to_le16((u16)bi->size);
1012 	desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
1013 	desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
1014 
1015 	/* set tail = the last cleaned desc index. */
1016 	wr32(hw, hw->aq.arq.tail, ntc);
1017 	/* ntc is updated to tail + 1 */
1018 	ntc++;
1019 	if (ntc == hw->aq.num_arq_entries)
1020 		ntc = 0;
1021 	hw->aq.arq.next_to_clean = ntc;
1022 	hw->aq.arq.next_to_use = ntu;
1023 
1024 	i40e_nvmupd_check_wait_event(hw, le16_to_cpu(e->desc.opcode));
1025 clean_arq_element_out:
1026 	/* Set pending if needed, unlock and return */
1027 	if (pending)
1028 		*pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
1029 clean_arq_element_err:
1030 	mutex_unlock(&hw->aq.arq_mutex);
1031 
1032 	return ret_code;
1033 }
1034 
1035 static void i40e_resume_aq(struct i40e_hw *hw)
1036 {
1037 	/* Registers are reset after PF reset */
1038 	hw->aq.asq.next_to_use = 0;
1039 	hw->aq.asq.next_to_clean = 0;
1040 
1041 	i40e_config_asq_regs(hw);
1042 
1043 	hw->aq.arq.next_to_use = 0;
1044 	hw->aq.arq.next_to_clean = 0;
1045 
1046 	i40e_config_arq_regs(hw);
1047 }
1048