1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <linux/linkmode.h> 8 #include <linux/pci.h> 9 #include <linux/ptp_clock_kernel.h> 10 #include <linux/types.h> 11 #include <linux/avf/virtchnl.h> 12 #include <linux/net/intel/i40e_client.h> 13 #include <net/devlink.h> 14 #include <net/pkt_cls.h> 15 #include <net/udp_tunnel.h> 16 #include "i40e_dcb.h" 17 #include "i40e_debug.h" 18 #include "i40e_devlink.h" 19 #include "i40e_io.h" 20 #include "i40e_prototype.h" 21 #include "i40e_register.h" 22 #include "i40e_txrx.h" 23 24 /* Useful i40e defaults */ 25 #define I40E_MAX_VEB 16 26 27 #define I40E_MAX_NUM_DESCRIPTORS 4096 28 #define I40E_MAX_NUM_DESCRIPTORS_XL710 8160 29 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 30 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 31 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 32 #define I40E_MIN_NUM_DESCRIPTORS 64 33 #define I40E_MIN_MSIX 2 34 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 35 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 36 /* max 16 qps */ 37 #define i40e_default_queues_per_vmdq(pf) \ 38 (test_bit(I40E_HW_CAP_RSS_AQ, (pf)->hw.caps) ? 4 : 1) 39 #define I40E_DEFAULT_QUEUES_PER_VF 4 40 #define I40E_MAX_VF_QUEUES 16 41 #define i40e_pf_get_max_q_per_tc(pf) \ 42 (test_bit(I40E_HW_CAP_128_QP_RSS, (pf)->hw.caps) ? 128 : 64) 43 #define I40E_FDIR_RING_COUNT 32 44 #define I40E_MAX_AQ_BUF_SIZE 4096 45 #define I40E_AQ_LEN 256 46 #define I40E_MIN_ARQ_LEN 1 47 #define I40E_MIN_ASQ_LEN 2 48 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 49 #define I40E_MAX_USER_PRIORITY 8 50 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 51 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 52 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 53 54 #define I40E_PHY_DEBUG_ALL \ 55 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 56 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 57 58 #define I40E_OEM_EETRACK_ID 0xffffffff 59 #define I40E_NVM_VERSION_LO_MASK GENMASK(7, 0) 60 #define I40E_NVM_VERSION_HI_MASK GENMASK(15, 12) 61 #define I40E_OEM_VER_BUILD_MASK GENMASK(23, 8) 62 #define I40E_OEM_VER_PATCH_MASK GENMASK(7, 0) 63 #define I40E_OEM_VER_MASK GENMASK(31, 24) 64 #define I40E_OEM_GEN_MASK GENMASK(31, 24) 65 #define I40E_OEM_SNAP_MASK GENMASK(23, 16) 66 #define I40E_OEM_RELEASE_MASK GENMASK(15, 0) 67 68 #define I40E_RX_DESC(R, i) \ 69 (&(((union i40e_rx_desc *)((R)->desc))[i])) 70 #define I40E_TX_DESC(R, i) \ 71 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 72 #define I40E_TX_CTXTDESC(R, i) \ 73 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 74 #define I40E_TX_FDIRDESC(R, i) \ 75 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 76 77 /* BW rate limiting */ 78 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 79 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 80 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 81 82 /* driver state flags */ 83 enum i40e_state { 84 __I40E_TESTING, 85 __I40E_CONFIG_BUSY, 86 __I40E_CONFIG_DONE, 87 __I40E_DOWN, 88 __I40E_SERVICE_SCHED, 89 __I40E_ADMINQ_EVENT_PENDING, 90 __I40E_MDD_EVENT_PENDING, 91 __I40E_VFLR_EVENT_PENDING, 92 __I40E_RESET_RECOVERY_PENDING, 93 __I40E_TIMEOUT_RECOVERY_PENDING, 94 __I40E_MISC_IRQ_REQUESTED, 95 __I40E_RESET_INTR_RECEIVED, 96 __I40E_REINIT_REQUESTED, 97 __I40E_PF_RESET_REQUESTED, 98 __I40E_PF_RESET_AND_REBUILD_REQUESTED, 99 __I40E_CORE_RESET_REQUESTED, 100 __I40E_GLOBAL_RESET_REQUESTED, 101 __I40E_EMP_RESET_INTR_RECEIVED, 102 __I40E_SUSPENDED, 103 __I40E_PTP_TX_IN_PROGRESS, 104 __I40E_BAD_EEPROM, 105 __I40E_DOWN_REQUESTED, 106 __I40E_FD_FLUSH_REQUESTED, 107 __I40E_FD_ATR_AUTO_DISABLED, 108 __I40E_FD_SB_AUTO_DISABLED, 109 __I40E_RESET_FAILED, 110 __I40E_PORT_SUSPENDED, 111 __I40E_VF_DISABLE, 112 __I40E_MACVLAN_SYNC_PENDING, 113 __I40E_TEMP_LINK_POLLING, 114 __I40E_CLIENT_SERVICE_REQUESTED, 115 __I40E_CLIENT_L2_CHANGE, 116 __I40E_CLIENT_RESET, 117 __I40E_VIRTCHNL_OP_PENDING, 118 __I40E_RECOVERY_MODE, 119 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */ 120 __I40E_IN_REMOVE, 121 __I40E_VFS_RELEASING, 122 /* This must be last as it determines the size of the BITMAP */ 123 __I40E_STATE_SIZE__, 124 }; 125 126 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 127 #define I40E_PF_RESET_AND_REBUILD_FLAG \ 128 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED) 129 130 /* VSI state flags */ 131 enum i40e_vsi_state { 132 __I40E_VSI_DOWN, 133 __I40E_VSI_NEEDS_RESTART, 134 __I40E_VSI_SYNCING_FILTERS, 135 __I40E_VSI_OVERFLOW_PROMISC, 136 __I40E_VSI_REINIT_REQUESTED, 137 __I40E_VSI_DOWN_REQUESTED, 138 __I40E_VSI_RELEASING, 139 /* This must be last as it determines the size of the BITMAP */ 140 __I40E_VSI_STATE_SIZE__, 141 }; 142 143 enum i40e_pf_flags { 144 I40E_FLAG_MSI_ENA, 145 I40E_FLAG_MSIX_ENA, 146 I40E_FLAG_RSS_ENA, 147 I40E_FLAG_VMDQ_ENA, 148 I40E_FLAG_SRIOV_ENA, 149 I40E_FLAG_DCB_CAPABLE, 150 I40E_FLAG_DCB_ENA, 151 I40E_FLAG_FD_SB_ENA, 152 I40E_FLAG_FD_ATR_ENA, 153 I40E_FLAG_MFP_ENA, 154 I40E_FLAG_HW_ATR_EVICT_ENA, 155 I40E_FLAG_VEB_MODE_ENA, 156 I40E_FLAG_VEB_STATS_ENA, 157 I40E_FLAG_LINK_POLLING_ENA, 158 I40E_FLAG_TRUE_PROMISC_ENA, 159 I40E_FLAG_LEGACY_RX_ENA, 160 I40E_FLAG_PTP_ENA, 161 I40E_FLAG_IWARP_ENA, 162 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, 163 I40E_FLAG_SOURCE_PRUNING_DIS, 164 I40E_FLAG_TC_MQPRIO_ENA, 165 I40E_FLAG_FD_SB_INACTIVE, 166 I40E_FLAG_FD_SB_TO_CLOUD_FILTER, 167 I40E_FLAG_FW_LLDP_DIS, 168 I40E_FLAG_RS_FEC, 169 I40E_FLAG_BASE_R_FEC, 170 /* TOTAL_PORT_SHUTDOWN_ENA 171 * Allows to physically disable the link on the NIC's port. 172 * If enabled, (after link down request from the OS) 173 * no link, traffic or led activity is possible on that port. 174 * 175 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA is set, the 176 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA must be explicitly forced 177 * to true and cannot be disabled by system admin at that time. 178 * The functionalities are exclusive in terms of configuration, but 179 * they also have similar behavior (allowing to disable physical 180 * link of the port), with following differences: 181 * - LINK_DOWN_ON_CLOSE_ENA is configurable at host OS run-time and 182 * is supported by whole family of 7xx Intel Ethernet Controllers 183 * - TOTAL_PORT_SHUTDOWN_ENA may be enabled only before OS loads 184 * (in BIOS) only if motherboard's BIOS and NIC's FW has support of it 185 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought 186 * down by sending phy_type=0 to NIC's FW 187 * - when TOTAL_PORT_SHUTDOWN_ENA is used, phy_type is not altered, 188 * instead the link is being brought down by clearing 189 * bit (I40E_AQ_PHY_ENABLE_LINK) in abilities field of 190 * i40e_aq_set_phy_config structure 191 */ 192 I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, 193 I40E_FLAG_VF_VLAN_PRUNING_ENA, 194 I40E_PF_FLAGS_NBITS, /* must be last */ 195 }; 196 197 enum i40e_interrupt_policy { 198 I40E_INTERRUPT_BEST_CASE, 199 I40E_INTERRUPT_MEDIUM, 200 I40E_INTERRUPT_LOWEST 201 }; 202 203 struct i40e_lump_tracking { 204 u16 num_entries; 205 u16 list[]; 206 #define I40E_PILE_VALID_BIT 0x8000 207 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 208 }; 209 210 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 211 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 212 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 213 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 214 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 215 216 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 217 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 218 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 219 220 enum i40e_fd_stat_idx { 221 I40E_FD_STAT_ATR, 222 I40E_FD_STAT_SB, 223 I40E_FD_STAT_ATR_TUNNEL, 224 I40E_FD_STAT_PF_COUNT 225 }; 226 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 227 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 228 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 229 #define I40E_FD_SB_STAT_IDX(pf_id) \ 230 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 231 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 232 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 233 234 /* The following structure contains the data parsed from the user-defined 235 * field of the ethtool_rx_flow_spec structure. 236 */ 237 struct i40e_rx_flow_userdef { 238 bool flex_filter; 239 u16 flex_word; 240 u16 flex_offset; 241 }; 242 243 struct i40e_fdir_filter { 244 struct hlist_node fdir_node; 245 /* filter ipnut set */ 246 u8 flow_type; 247 u8 ipl4_proto; 248 /* TX packet view of src and dst */ 249 __be32 dst_ip; 250 __be32 src_ip; 251 __be32 dst_ip6[4]; 252 __be32 src_ip6[4]; 253 __be16 src_port; 254 __be16 dst_port; 255 __be32 sctp_v_tag; 256 257 __be16 vlan_etype; 258 __be16 vlan_tag; 259 /* Flexible data to match within the packet payload */ 260 __be16 flex_word; 261 u16 flex_offset; 262 bool flex_filter; 263 264 /* filter control */ 265 u16 q_index; 266 u8 flex_off; 267 u8 pctype; 268 u16 dest_vsi; 269 u8 dest_ctl; 270 u8 fd_status; 271 u16 cnt_index; 272 u32 fd_id; 273 }; 274 275 #define I40E_CLOUD_FIELD_OMAC BIT(0) 276 #define I40E_CLOUD_FIELD_IMAC BIT(1) 277 #define I40E_CLOUD_FIELD_IVLAN BIT(2) 278 #define I40E_CLOUD_FIELD_TEN_ID BIT(3) 279 #define I40E_CLOUD_FIELD_IIP BIT(4) 280 281 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 282 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 283 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 284 I40E_CLOUD_FIELD_IVLAN) 285 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 286 I40E_CLOUD_FIELD_TEN_ID) 287 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 288 I40E_CLOUD_FIELD_IMAC | \ 289 I40E_CLOUD_FIELD_TEN_ID) 290 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 291 I40E_CLOUD_FIELD_IVLAN | \ 292 I40E_CLOUD_FIELD_TEN_ID) 293 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 294 295 struct i40e_cloud_filter { 296 struct hlist_node cloud_node; 297 unsigned long cookie; 298 /* cloud filter input set follows */ 299 u8 dst_mac[ETH_ALEN]; 300 u8 src_mac[ETH_ALEN]; 301 __be16 vlan_id; 302 u16 seid; /* filter control */ 303 __be16 dst_port; 304 __be16 src_port; 305 u32 tenant_id; 306 union { 307 struct { 308 struct in_addr dst_ip; 309 struct in_addr src_ip; 310 } v4; 311 struct { 312 struct in6_addr dst_ip6; 313 struct in6_addr src_ip6; 314 } v6; 315 } ip; 316 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 317 #define src_ipv6 ip.v6.src_ip6.s6_addr32 318 #define dst_ipv4 ip.v4.dst_ip.s_addr 319 #define src_ipv4 ip.v4.src_ip.s_addr 320 u16 n_proto; /* Ethernet Protocol */ 321 u8 ip_proto; /* IPPROTO value */ 322 u8 flags; 323 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 324 u8 tunnel_type; 325 }; 326 327 #define I40E_DCB_PRIO_TYPE_STRICT 0 328 #define I40E_DCB_PRIO_TYPE_ETS 1 329 #define I40E_DCB_STRICT_PRIO_CREDITS 127 330 /* DCB per TC information data structure */ 331 struct i40e_tc_info { 332 u16 qoffset; /* Queue offset from base queue */ 333 u16 qcount; /* Total Queues */ 334 u8 netdev_tc; /* Netdev TC index if netdev associated */ 335 }; 336 337 /* TC configuration data structure */ 338 struct i40e_tc_configuration { 339 u8 numtc; /* Total number of enabled TCs */ 340 u8 enabled_tc; /* TC map */ 341 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 342 }; 343 344 #define I40E_UDP_PORT_INDEX_UNUSED 255 345 struct i40e_udp_port_config { 346 /* AdminQ command interface expects port number in Host byte order */ 347 u16 port; 348 u8 type; 349 u8 filter_index; 350 }; 351 352 /* macros related to FLX_PIT */ 353 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 354 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 355 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 356 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 357 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 358 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 359 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 360 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 361 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 362 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 363 I40E_FLEX_SET_FSIZE(fsize) | \ 364 I40E_FLEX_SET_SRC_WORD(src)) 365 366 367 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 368 369 /* macros related to GLQF_ORT */ 370 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 371 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 372 I40E_GLQF_ORT_PIT_INDX_MASK) 373 374 #define I40E_ORT_SET_COUNT(count) (((count) << \ 375 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 376 I40E_GLQF_ORT_FIELD_CNT_MASK) 377 378 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 379 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 380 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 381 382 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 383 I40E_ORT_SET_COUNT(count) | \ 384 I40E_ORT_SET_PAYLOAD(payload)) 385 386 #define I40E_L3_GLQF_ORT_IDX 34 387 #define I40E_L4_GLQF_ORT_IDX 35 388 389 /* Flex PIT register index */ 390 #define I40E_FLEX_PIT_IDX_START_L3 3 391 #define I40E_FLEX_PIT_IDX_START_L4 6 392 393 #define I40E_FLEX_PIT_TABLE_SIZE 3 394 395 #define I40E_FLEX_DEST_UNUSED 63 396 397 #define I40E_FLEX_INDEX_ENTRIES 8 398 399 /* Flex MASK to disable all flexible entries */ 400 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 401 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 402 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 403 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 404 405 #define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \ 406 (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \ 407 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \ 408 ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \ 409 ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \ 410 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)) 411 412 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \ 413 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \ 414 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \ 415 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \ 416 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \ 417 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)) 418 419 struct i40e_flex_pit { 420 struct list_head list; 421 u16 src_offset; 422 u8 pit_index; 423 }; 424 425 struct i40e_fwd_adapter { 426 struct net_device *netdev; 427 int bit_no; 428 }; 429 430 struct i40e_channel { 431 struct list_head list; 432 bool initialized; 433 u8 type; 434 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 435 u16 stat_counter_idx; 436 u16 base_queue; 437 u16 num_queue_pairs; /* Requested by user */ 438 u16 seid; 439 440 u8 enabled_tc; 441 struct i40e_aqc_vsi_properties_data info; 442 443 u64 max_tx_rate; 444 struct i40e_fwd_adapter *fwd; 445 446 /* track this channel belongs to which VSI */ 447 struct i40e_vsi *parent_vsi; 448 }; 449 450 struct i40e_ptp_pins_settings; 451 452 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch) 453 { 454 return !!ch->fwd; 455 } 456 457 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch) 458 { 459 if (i40e_is_channel_macvlan(ch)) 460 return ch->fwd->netdev->dev_addr; 461 else 462 return NULL; 463 } 464 465 /* struct that defines the Ethernet device */ 466 struct i40e_pf { 467 struct pci_dev *pdev; 468 struct devlink_port devlink_port; 469 struct i40e_hw hw; 470 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 471 struct msix_entry *msix_entries; 472 473 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 474 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 475 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 476 u16 num_req_vfs; /* num VFs requested for this PF */ 477 u16 num_vf_qps; /* num queue pairs per VF */ 478 u16 num_lan_qps; /* num lan queues this PF has set up */ 479 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 480 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 481 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 482 int iwarp_base_vector; 483 int queues_left; /* queues left unclaimed */ 484 u16 alloc_rss_size; /* allocated RSS queues */ 485 u16 rss_size_max; /* HW defined max RSS queues */ 486 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 487 u16 num_alloc_vsi; /* num VSIs this driver supports */ 488 bool wol_en; 489 490 struct hlist_head fdir_filter_list; 491 u16 fdir_pf_active_filters; 492 unsigned long fd_flush_timestamp; 493 u32 fd_flush_cnt; 494 u32 fd_add_err; 495 u32 fd_atr_cnt; 496 497 /* Book-keeping of side-band filter count per flow-type. 498 * This is used to detect and handle input set changes for 499 * respective flow-type. 500 */ 501 u16 fd_tcp4_filter_cnt; 502 u16 fd_udp4_filter_cnt; 503 u16 fd_sctp4_filter_cnt; 504 u16 fd_ip4_filter_cnt; 505 506 u16 fd_tcp6_filter_cnt; 507 u16 fd_udp6_filter_cnt; 508 u16 fd_sctp6_filter_cnt; 509 u16 fd_ip6_filter_cnt; 510 511 /* Flexible filter table values that need to be programmed into 512 * hardware, which expects L3 and L4 to be programmed separately. We 513 * need to ensure that the values are in ascended order and don't have 514 * duplicates, so we track each L3 and L4 values in separate lists. 515 */ 516 struct list_head l3_flex_pit_list; 517 struct list_head l4_flex_pit_list; 518 519 struct udp_tunnel_nic_shared udp_tunnel_shared; 520 struct udp_tunnel_nic_info udp_tunnel_nic; 521 522 struct hlist_head cloud_filter_list; 523 u16 num_cloud_filters; 524 525 u16 rx_itr_default; 526 u16 tx_itr_default; 527 u32 msg_enable; 528 char int_name[I40E_INT_NAME_STR_LEN]; 529 unsigned long service_timer_period; 530 unsigned long service_timer_previous; 531 struct timer_list service_timer; 532 struct work_struct service_task; 533 534 DECLARE_BITMAP(flags, I40E_PF_FLAGS_NBITS); 535 struct i40e_client_instance *cinst; 536 bool stat_offsets_loaded; 537 struct i40e_hw_port_stats stats; 538 struct i40e_hw_port_stats stats_offsets; 539 u32 tx_timeout_count; 540 u32 tx_timeout_recovery_level; 541 unsigned long tx_timeout_last_recovery; 542 u32 hw_csum_rx_error; 543 u32 led_status; 544 u16 corer_count; /* Core reset count */ 545 u16 globr_count; /* Global reset count */ 546 u16 empr_count; /* EMP reset count */ 547 u16 pfr_count; /* PF reset count */ 548 u16 sw_int_count; /* SW interrupt count */ 549 550 struct mutex switch_mutex; 551 u16 lan_vsi; /* our default LAN VSI */ 552 u16 lan_veb; /* initial relay, if exists */ 553 #define I40E_NO_VEB 0xffff 554 #define I40E_NO_VSI 0xffff 555 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 556 struct i40e_vsi **vsi; 557 struct i40e_veb *veb[I40E_MAX_VEB]; 558 559 struct i40e_lump_tracking *qp_pile; 560 struct i40e_lump_tracking *irq_pile; 561 562 /* switch config info */ 563 u16 main_vsi_seid; 564 u16 mac_seid; 565 #ifdef CONFIG_DEBUG_FS 566 struct dentry *i40e_dbg_pf; 567 #endif /* CONFIG_DEBUG_FS */ 568 bool cur_promisc; 569 570 /* sr-iov config info */ 571 struct i40e_vf *vf; 572 int num_alloc_vfs; /* actual number of VFs allocated */ 573 u32 vf_aq_requests; 574 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 575 576 /* DCBx/DCBNL capability for PF that indicates 577 * whether DCBx is managed by firmware or host 578 * based agent (LLDPAD). Also, indicates what 579 * flavor of DCBx protocol (IEEE/CEE) is supported 580 * by the device. For now we're supporting IEEE 581 * mode only. 582 */ 583 u16 dcbx_cap; 584 585 struct i40e_filter_control_settings filter_settings; 586 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */ 587 struct i40e_dcbx_config tmp_cfg; 588 589 /* GPIO defines used by PTP */ 590 #define I40E_SDP3_2 18 591 #define I40E_SDP3_3 19 592 #define I40E_GPIO_4 20 593 #define I40E_LED2_0 26 594 #define I40E_LED2_1 27 595 #define I40E_LED3_0 28 596 #define I40E_LED3_1 29 597 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \ 598 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 599 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \ 600 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 601 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \ 602 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 603 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \ 604 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 605 #define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2) 606 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \ 607 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 608 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \ 609 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) 610 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \ 611 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) 612 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \ 613 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) 614 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \ 615 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 616 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \ 617 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 618 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \ 619 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) 620 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \ 621 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 622 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \ 623 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 624 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 625 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 626 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \ 627 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 628 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 629 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 630 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \ 631 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 632 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 633 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 634 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 635 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \ 636 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 637 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 638 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 639 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 640 #define I40E_GLGEN_GPIO_CTL_LED_INIT \ 641 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \ 642 I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 643 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \ 644 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 645 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \ 646 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN) 647 #define I40E_PRTTSYN_AUX_1_INSTNT \ 648 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) 649 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \ 650 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) 651 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) 652 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \ 653 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD) 654 #define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */ 655 #define I40E_PTP_2_SEC_DELAY 2 656 657 struct ptp_clock *ptp_clock; 658 struct ptp_clock_info ptp_caps; 659 struct sk_buff *ptp_tx_skb; 660 unsigned long ptp_tx_start; 661 struct hwtstamp_config tstamp_config; 662 struct timespec64 ptp_prev_hw_time; 663 struct work_struct ptp_extts0_work; 664 ktime_t ptp_reset_start; 665 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 666 u32 ptp_adj_mult; 667 u32 tx_hwtstamp_timeouts; 668 u32 tx_hwtstamp_skipped; 669 u32 rx_hwtstamp_cleared; 670 u32 latch_event_flags; 671 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 672 unsigned long latch_events[4]; 673 bool ptp_tx; 674 bool ptp_rx; 675 struct i40e_ptp_pins_settings *ptp_pins; 676 u16 rss_table_size; /* HW RSS table size */ 677 u32 max_bw; 678 u32 min_bw; 679 680 u32 ioremap_len; 681 u32 fd_inv; 682 u16 phy_led_val; 683 684 u16 last_sw_conf_flags; 685 u16 last_sw_conf_valid_flags; 686 /* List to keep previous DDP profiles to be rolled back in the future */ 687 struct list_head ddp_old_prof; 688 }; 689 690 /** 691 * __i40e_pf_next_vsi - get next valid VSI 692 * @pf: pointer to the PF struct 693 * @idx: pointer to start position number 694 * 695 * Find and return next non-NULL VSI pointer in pf->vsi array and 696 * updates idx position. Returns NULL if no VSI is found. 697 **/ 698 static __always_inline struct i40e_vsi * 699 __i40e_pf_next_vsi(struct i40e_pf *pf, int *idx) 700 { 701 while (*idx < pf->num_alloc_vsi) { 702 if (pf->vsi[*idx]) 703 return pf->vsi[*idx]; 704 (*idx)++; 705 } 706 return NULL; 707 } 708 709 #define i40e_pf_for_each_vsi(_pf, _i, _vsi) \ 710 for (_i = 0, _vsi = __i40e_pf_next_vsi(_pf, &_i); \ 711 _vsi; \ 712 _i++, _vsi = __i40e_pf_next_vsi(_pf, &_i)) 713 714 /** 715 * __i40e_pf_next_veb - get next valid VEB 716 * @pf: pointer to the PF struct 717 * @idx: pointer to start position number 718 * 719 * Find and return next non-NULL VEB pointer in pf->veb array and 720 * updates idx position. Returns NULL if no VEB is found. 721 **/ 722 static __always_inline struct i40e_veb * 723 __i40e_pf_next_veb(struct i40e_pf *pf, int *idx) 724 { 725 while (*idx < I40E_MAX_VEB) { 726 if (pf->veb[*idx]) 727 return pf->veb[*idx]; 728 (*idx)++; 729 } 730 return NULL; 731 } 732 733 #define i40e_pf_for_each_veb(_pf, _i, _veb) \ 734 for (_i = 0, _veb = __i40e_pf_next_veb(_pf, &_i); \ 735 _veb; \ 736 _i++, _veb = __i40e_pf_next_veb(_pf, &_i)) 737 738 /** 739 * i40e_addr_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 740 * @macaddr: the MAC Address as the base key 741 * 742 * Simply copies the address and returns it as a u64 for hashing 743 **/ 744 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 745 { 746 u64 key = 0; 747 748 ether_addr_copy((u8 *)&key, macaddr); 749 return key; 750 } 751 752 enum i40e_filter_state { 753 I40E_FILTER_INVALID = 0, /* Invalid state */ 754 I40E_FILTER_NEW, /* New, not sent to FW yet */ 755 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 756 I40E_FILTER_FAILED, /* Rejected by FW */ 757 I40E_FILTER_REMOVE, /* To be removed */ 758 I40E_FILTER_NEW_SYNC, /* New, not sent yet, is in i40e_sync_vsi_filters() */ 759 /* There is no 'removed' state; the filter struct is freed */ 760 }; 761 struct i40e_mac_filter { 762 struct hlist_node hlist; 763 u8 macaddr[ETH_ALEN]; 764 #define I40E_VLAN_ANY -1 765 s16 vlan; 766 enum i40e_filter_state state; 767 }; 768 769 /* Wrapper structure to keep track of filters while we are preparing to send 770 * firmware commands. We cannot send firmware commands while holding a 771 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 772 * a separate structure, which will track the state change and update the real 773 * filter while under lock. We can't simply hold the filters in a separate 774 * list, as this opens a window for a race condition when adding new MAC 775 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 776 */ 777 struct i40e_new_mac_filter { 778 struct hlist_node hlist; 779 struct i40e_mac_filter *f; 780 781 /* Track future changes to state separately */ 782 enum i40e_filter_state state; 783 }; 784 785 struct i40e_veb { 786 struct i40e_pf *pf; 787 u16 idx; 788 u16 seid; 789 u16 uplink_seid; 790 u16 stats_idx; /* index of VEB parent */ 791 u8 enabled_tc; 792 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 793 u16 bw_limit; 794 u8 bw_max_quanta; 795 bool is_abs_credits; 796 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 797 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 798 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 799 struct kobject *kobj; 800 bool stat_offsets_loaded; 801 struct i40e_eth_stats stats; 802 struct i40e_eth_stats stats_offsets; 803 struct i40e_veb_tc_stats tc_stats; 804 struct i40e_veb_tc_stats tc_stats_offsets; 805 }; 806 807 /* struct that defines a VSI, associated with a dev */ 808 struct i40e_vsi { 809 struct net_device *netdev; 810 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 811 bool netdev_registered; 812 bool stat_offsets_loaded; 813 814 u32 current_netdev_flags; 815 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 816 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 817 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 818 unsigned long flags; 819 820 /* Per VSI lock to protect elements/hash (MAC filter) */ 821 spinlock_t mac_filter_hash_lock; 822 /* Fixed size hash table with 2^8 buckets for MAC filters */ 823 DECLARE_HASHTABLE(mac_filter_hash, 8); 824 bool has_vlan_filter; 825 826 /* VSI stats */ 827 struct rtnl_link_stats64 net_stats; 828 struct rtnl_link_stats64 net_stats_offsets; 829 struct i40e_eth_stats eth_stats; 830 struct i40e_eth_stats eth_stats_offsets; 831 u64 tx_restart; 832 u64 tx_busy; 833 u64 tx_linearize; 834 u64 tx_force_wb; 835 u64 tx_stopped; 836 u64 rx_buf_failed; 837 u64 rx_page_failed; 838 u64 rx_page_reuse; 839 u64 rx_page_alloc; 840 u64 rx_page_waive; 841 u64 rx_page_busy; 842 843 /* These are containers of ring pointers, allocated at run-time */ 844 struct i40e_ring **rx_rings; 845 struct i40e_ring **tx_rings; 846 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 847 848 u32 active_filters; 849 u32 promisc_threshold; 850 851 u16 work_limit; 852 u16 int_rate_limit; /* value in usecs */ 853 854 u16 rss_table_size; /* HW RSS table size */ 855 u16 rss_size; /* Allocated RSS queues */ 856 u8 *rss_hkey_user; /* User configured hash keys */ 857 u8 *rss_lut_user; /* User configured lookup table entries */ 858 859 860 u16 max_frame; 861 u16 rx_buf_len; 862 863 struct bpf_prog *xdp_prog; 864 865 /* List of q_vectors allocated to this VSI */ 866 struct i40e_q_vector **q_vectors; 867 int num_q_vectors; 868 int base_vector; 869 bool irqs_ready; 870 871 u16 seid; /* HW index of this VSI (absolute index) */ 872 u16 id; /* VSI number */ 873 u16 uplink_seid; 874 875 u16 base_queue; /* vsi's first queue in hw array */ 876 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 877 u16 req_queue_pairs; /* User requested queue pairs */ 878 u16 num_queue_pairs; /* Used tx and rx pairs */ 879 u16 num_tx_desc; 880 u16 num_rx_desc; 881 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 882 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 883 884 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 885 struct i40e_tc_configuration tc_config; 886 struct i40e_aqc_vsi_properties_data info; 887 888 /* VSI BW limit (absolute across all TCs) */ 889 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 890 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 891 892 /* Relative TC credits across VSIs */ 893 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 894 /* TC BW limit credits within VSI */ 895 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 896 /* TC BW limit max quanta within VSI */ 897 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 898 899 struct i40e_pf *back; /* Backreference to associated PF */ 900 u16 idx; /* index in pf->vsi[] */ 901 u16 veb_idx; /* index of VEB parent */ 902 struct kobject *kobj; /* sysfs object */ 903 bool current_isup; /* Sync 'link up' logging */ 904 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 905 906 /* channel specific fields */ 907 u16 cnt_q_avail; /* num of queues available for channel usage */ 908 u16 orig_rss_size; 909 u16 current_rss_size; 910 bool reconfig_rss; 911 912 u16 next_base_queue; /* next queue to be used for channel setup */ 913 914 struct list_head ch_list; 915 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 916 917 /* macvlan fields */ 918 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */ 919 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */ 920 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS); 921 struct list_head macvlan_list; 922 int macvlan_cnt; 923 924 void *priv; /* client driver data reference. */ 925 926 /* VSI specific handlers */ 927 irqreturn_t (*irq_handler)(int irq, void *data); 928 929 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 930 } ____cacheline_internodealigned_in_smp; 931 932 struct i40e_netdev_priv { 933 struct i40e_vsi *vsi; 934 }; 935 936 extern struct ida i40e_client_ida; 937 938 /* struct that defines an interrupt vector */ 939 struct i40e_q_vector { 940 struct i40e_vsi *vsi; 941 942 u16 v_idx; /* index in the vsi->q_vector array. */ 943 u16 reg_idx; /* register index of the interrupt */ 944 945 struct napi_struct napi; 946 947 struct i40e_ring_container rx; 948 struct i40e_ring_container tx; 949 950 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 951 u8 num_ringpairs; /* total number of ring pairs in vector */ 952 953 cpumask_t affinity_mask; 954 struct irq_affinity_notify affinity_notify; 955 956 struct rcu_head rcu; /* to avoid race with update stats on free */ 957 char name[I40E_INT_NAME_STR_LEN]; 958 bool arm_wb_state; 959 bool in_busy_poll; 960 int irq_num; /* IRQ assigned to this q_vector */ 961 } ____cacheline_internodealigned_in_smp; 962 963 /* lan device */ 964 struct i40e_device { 965 struct list_head list; 966 struct i40e_pf *pf; 967 }; 968 969 /** 970 * i40e_info_nvm_ver - format the NVM version string 971 * @hw: ptr to the hardware info 972 * @buf: string buffer to store 973 * @len: buffer size 974 * 975 * Formats NVM version string as: 976 * <gen>.<snap>.<release> when eetrackid == I40E_OEM_EETRACK_ID 977 * <nvm_major>.<nvm_minor> otherwise 978 **/ 979 static inline void i40e_info_nvm_ver(struct i40e_hw *hw, char *buf, size_t len) 980 { 981 struct i40e_nvm_info *nvm = &hw->nvm; 982 983 if (nvm->eetrack == I40E_OEM_EETRACK_ID) { 984 u32 full_ver = nvm->oem_ver; 985 u8 gen, snap; 986 u16 release; 987 988 gen = FIELD_GET(I40E_OEM_GEN_MASK, full_ver); 989 snap = FIELD_GET(I40E_OEM_SNAP_MASK, full_ver); 990 release = FIELD_GET(I40E_OEM_RELEASE_MASK, full_ver); 991 snprintf(buf, len, "%x.%x.%x", gen, snap, release); 992 } else { 993 u8 major, minor; 994 995 major = FIELD_GET(I40E_NVM_VERSION_HI_MASK, nvm->version); 996 minor = FIELD_GET(I40E_NVM_VERSION_LO_MASK, nvm->version); 997 snprintf(buf, len, "%x.%02x", major, minor); 998 } 999 } 1000 1001 /** 1002 * i40e_info_eetrack - format the EETrackID string 1003 * @hw: ptr to the hardware info 1004 * @buf: string buffer to store 1005 * @len: buffer size 1006 * 1007 * Returns hexadecimally formated EETrackID if it is 1008 * different from I40E_OEM_EETRACK_ID or empty string. 1009 **/ 1010 static inline void i40e_info_eetrack(struct i40e_hw *hw, char *buf, size_t len) 1011 { 1012 struct i40e_nvm_info *nvm = &hw->nvm; 1013 1014 buf[0] = '\0'; 1015 if (nvm->eetrack != I40E_OEM_EETRACK_ID) 1016 snprintf(buf, len, "0x%08x", nvm->eetrack); 1017 } 1018 1019 /** 1020 * i40e_info_civd_ver - format the NVM version strings 1021 * @hw: ptr to the hardware info 1022 * @buf: string buffer to store 1023 * @len: buffer size 1024 * 1025 * Returns formated combo image version if adapter's EETrackID is 1026 * different from I40E_OEM_EETRACK_ID or empty string. 1027 **/ 1028 static inline void i40e_info_civd_ver(struct i40e_hw *hw, char *buf, size_t len) 1029 { 1030 struct i40e_nvm_info *nvm = &hw->nvm; 1031 1032 buf[0] = '\0'; 1033 if (nvm->eetrack != I40E_OEM_EETRACK_ID) { 1034 u32 full_ver = nvm->oem_ver; 1035 u8 major, minor; 1036 u16 build; 1037 1038 major = FIELD_GET(I40E_OEM_VER_MASK, full_ver); 1039 build = FIELD_GET(I40E_OEM_VER_BUILD_MASK, full_ver); 1040 minor = FIELD_GET(I40E_OEM_VER_PATCH_MASK, full_ver); 1041 snprintf(buf, len, "%d.%d.%d", major, build, minor); 1042 } 1043 } 1044 1045 /** 1046 * i40e_nvm_version_str - format the NVM version strings 1047 * @hw: ptr to the hardware info 1048 * @buf: string buffer to store 1049 * @len: buffer size 1050 **/ 1051 static inline char *i40e_nvm_version_str(struct i40e_hw *hw, char *buf, 1052 size_t len) 1053 { 1054 char ver[16] = " "; 1055 1056 /* Get NVM version */ 1057 i40e_info_nvm_ver(hw, buf, len); 1058 1059 /* Append EETrackID if provided */ 1060 i40e_info_eetrack(hw, &ver[1], sizeof(ver) - 1); 1061 if (strlen(ver) > 1) 1062 strlcat(buf, ver, len); 1063 1064 /* Append combo image version if provided */ 1065 i40e_info_civd_ver(hw, &ver[1], sizeof(ver) - 1); 1066 if (strlen(ver) > 1) 1067 strlcat(buf, ver, len); 1068 1069 return buf; 1070 } 1071 1072 /** 1073 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 1074 * @netdev: the corresponding netdev 1075 * 1076 * Return the PF struct for the given netdev 1077 **/ 1078 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 1079 { 1080 struct i40e_netdev_priv *np = netdev_priv(netdev); 1081 struct i40e_vsi *vsi = np->vsi; 1082 1083 return vsi->back; 1084 } 1085 1086 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 1087 irqreturn_t (*irq_handler)(int, void *)) 1088 { 1089 vsi->irq_handler = irq_handler; 1090 } 1091 1092 /** 1093 * i40e_get_fd_cnt_all - get the total FD filter space available 1094 * @pf: pointer to the PF struct 1095 **/ 1096 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 1097 { 1098 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 1099 } 1100 1101 /** 1102 * i40e_read_fd_input_set - reads value of flow director input set register 1103 * @pf: pointer to the PF struct 1104 * @addr: register addr 1105 * 1106 * This function reads value of flow director input set register 1107 * specified by 'addr' (which is specific to flow-type) 1108 **/ 1109 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 1110 { 1111 u64 val; 1112 1113 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 1114 val <<= 32; 1115 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 1116 1117 return val; 1118 } 1119 1120 /** 1121 * i40e_write_fd_input_set - writes value into flow director input set register 1122 * @pf: pointer to the PF struct 1123 * @addr: register addr 1124 * @val: value to be written 1125 * 1126 * This function writes specified value to the register specified by 'addr'. 1127 * This register is input set register based on flow-type. 1128 **/ 1129 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 1130 u16 addr, u64 val) 1131 { 1132 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 1133 (u32)(val >> 32)); 1134 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 1135 (u32)(val & 0xFFFFFFFFULL)); 1136 } 1137 1138 /** 1139 * i40e_get_pf_count - get PCI PF count. 1140 * @hw: pointer to a hw. 1141 * 1142 * Reports the function number of the highest PCI physical 1143 * function plus 1 as it is loaded from the NVM. 1144 * 1145 * Return: PCI PF count. 1146 **/ 1147 static inline u32 i40e_get_pf_count(struct i40e_hw *hw) 1148 { 1149 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK, 1150 rd32(hw, I40E_GLGEN_PCIFCNCNT)); 1151 } 1152 1153 /* needed by i40e_ethtool.c */ 1154 int i40e_up(struct i40e_vsi *vsi); 1155 void i40e_down(struct i40e_vsi *vsi); 1156 extern const char i40e_driver_name[]; 1157 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 1158 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 1159 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1160 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1161 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 1162 u16 rss_table_size, u16 rss_size); 1163 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 1164 /** 1165 * i40e_find_vsi_by_type - Find and return Flow Director VSI 1166 * @pf: PF to search for VSI 1167 * @type: Value indicating type of VSI we are looking for 1168 **/ 1169 static inline struct i40e_vsi * 1170 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 1171 { 1172 struct i40e_vsi *vsi; 1173 int i; 1174 1175 i40e_pf_for_each_vsi(pf, i, vsi) 1176 if (vsi->type == type) 1177 return vsi; 1178 1179 return NULL; 1180 } 1181 void i40e_update_stats(struct i40e_vsi *vsi); 1182 void i40e_update_veb_stats(struct i40e_veb *veb); 1183 void i40e_update_eth_stats(struct i40e_vsi *vsi); 1184 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 1185 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1186 bool printconfig); 1187 1188 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1189 struct i40e_fdir_filter *input, bool add); 1190 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1191 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1192 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1193 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1194 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1195 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1196 void i40e_set_ethtool_ops(struct net_device *netdev); 1197 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1198 const u8 *macaddr, s16 vlan); 1199 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1200 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1201 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1202 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1203 u16 uplink, u32 param1); 1204 int i40e_vsi_release(struct i40e_vsi *vsi); 1205 void i40e_service_event_schedule(struct i40e_pf *pf); 1206 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1207 u8 *msg, u16 len); 1208 1209 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1210 bool enable); 1211 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1212 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1213 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1214 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1215 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1216 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1217 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 uplink_seid, 1218 u16 downlink_seid, u8 enabled_tc); 1219 void i40e_veb_release(struct i40e_veb *veb); 1220 1221 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1222 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1223 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1224 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1225 void i40e_pf_reset_stats(struct i40e_pf *pf); 1226 #ifdef CONFIG_DEBUG_FS 1227 void i40e_dbg_pf_init(struct i40e_pf *pf); 1228 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1229 void i40e_dbg_init(void); 1230 void i40e_dbg_exit(void); 1231 #else 1232 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1233 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1234 static inline void i40e_dbg_init(void) {} 1235 static inline void i40e_dbg_exit(void) {} 1236 #endif /* CONFIG_DEBUG_FS*/ 1237 /* needed by client drivers */ 1238 int i40e_lan_add_device(struct i40e_pf *pf); 1239 int i40e_lan_del_device(struct i40e_pf *pf); 1240 void i40e_client_subtask(struct i40e_pf *pf); 1241 void i40e_notify_client_of_l2_param_changes(struct i40e_pf *pf); 1242 void i40e_notify_client_of_netdev_close(struct i40e_pf *pf, bool reset); 1243 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1244 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1245 void i40e_client_update_msix_info(struct i40e_pf *pf); 1246 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1247 /** 1248 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1249 * @vsi: pointer to a vsi 1250 * @vector: enable a particular Hw Interrupt vector, without base_vector 1251 **/ 1252 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1253 { 1254 struct i40e_pf *pf = vsi->back; 1255 struct i40e_hw *hw = &pf->hw; 1256 u32 val; 1257 1258 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1259 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1260 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1261 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1262 /* skip the flush */ 1263 } 1264 1265 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1266 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1267 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1268 int i40e_open(struct net_device *netdev); 1269 int i40e_close(struct net_device *netdev); 1270 int i40e_vsi_open(struct i40e_vsi *vsi); 1271 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1272 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1273 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1274 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1275 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1276 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1277 const u8 *macaddr); 1278 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1279 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1280 int i40e_count_filters(struct i40e_vsi *vsi); 1281 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1282 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1283 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf) 1284 { 1285 return test_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags); 1286 } 1287 1288 #ifdef CONFIG_I40E_DCB 1289 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1290 struct i40e_dcbx_config *old_cfg, 1291 struct i40e_dcbx_config *new_cfg); 1292 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1293 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1294 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1295 struct i40e_dcbx_config *old_cfg, 1296 struct i40e_dcbx_config *new_cfg); 1297 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg); 1298 int i40e_dcb_sw_default_config(struct i40e_pf *pf); 1299 #endif /* CONFIG_I40E_DCB */ 1300 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1301 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1302 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1303 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1304 void i40e_ptp_set_increment(struct i40e_pf *pf); 1305 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1306 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1307 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1308 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1309 void i40e_ptp_init(struct i40e_pf *pf); 1310 void i40e_ptp_stop(struct i40e_pf *pf); 1311 int i40e_ptp_alloc_pins(struct i40e_pf *pf); 1312 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset); 1313 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1314 int i40e_get_partition_bw_setting(struct i40e_pf *pf); 1315 int i40e_set_partition_bw_setting(struct i40e_pf *pf); 1316 int i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1317 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1318 1319 void i40e_set_fec_in_flags(u8 fec_cfg, unsigned long *flags); 1320 1321 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1322 { 1323 return !!READ_ONCE(vsi->xdp_prog); 1324 } 1325 1326 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1327 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1328 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1329 struct i40e_cloud_filter *filter, 1330 bool add); 1331 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1332 struct i40e_cloud_filter *filter, 1333 bool add); 1334 1335 /** 1336 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF 1337 * @pf: pointer to a pf. 1338 * 1339 * Check and return state of flag I40E_FLAG_TC_MQPRIO. 1340 * 1341 * Return: true/false if I40E_FLAG_TC_MQPRIO is set or not 1342 **/ 1343 static inline bool i40e_is_tc_mqprio_enabled(struct i40e_pf *pf) 1344 { 1345 return test_bit(I40E_FLAG_TC_MQPRIO_ENA, pf->flags); 1346 } 1347 1348 /** 1349 * i40e_hw_to_pf - get pf pointer from the hardware structure 1350 * @hw: pointer to the device HW structure 1351 **/ 1352 static inline struct i40e_pf *i40e_hw_to_pf(struct i40e_hw *hw) 1353 { 1354 return container_of(hw, struct i40e_pf, hw); 1355 } 1356 1357 struct device *i40e_hw_to_dev(struct i40e_hw *hw); 1358 1359 /** 1360 * i40e_pf_get_vsi_by_seid - find VSI by SEID 1361 * @pf: pointer to a PF 1362 * @seid: SEID of the VSI 1363 **/ 1364 static inline struct i40e_vsi * 1365 i40e_pf_get_vsi_by_seid(struct i40e_pf *pf, u16 seid) 1366 { 1367 struct i40e_vsi *vsi; 1368 int i; 1369 1370 i40e_pf_for_each_vsi(pf, i, vsi) 1371 if (vsi->seid == seid) 1372 return vsi; 1373 1374 return NULL; 1375 } 1376 1377 /** 1378 * i40e_pf_get_main_vsi - get pointer to main VSI 1379 * @pf: pointer to a PF 1380 * 1381 * Return: pointer to main VSI or NULL if it does not exist 1382 **/ 1383 static inline struct i40e_vsi *i40e_pf_get_main_vsi(struct i40e_pf *pf) 1384 { 1385 return (pf->lan_vsi != I40E_NO_VSI) ? pf->vsi[pf->lan_vsi] : NULL; 1386 } 1387 1388 /** 1389 * i40e_pf_get_veb_by_seid - find VEB by SEID 1390 * @pf: pointer to a PF 1391 * @seid: SEID of the VSI 1392 **/ 1393 static inline struct i40e_veb * 1394 i40e_pf_get_veb_by_seid(struct i40e_pf *pf, u16 seid) 1395 { 1396 struct i40e_veb *veb; 1397 int i; 1398 1399 i40e_pf_for_each_veb(pf, i, veb) 1400 if (veb->seid == seid) 1401 return veb; 1402 1403 return NULL; 1404 } 1405 1406 /** 1407 * i40e_pf_get_main_veb - get pointer to main VEB 1408 * @pf: pointer to a PF 1409 * 1410 * Return: pointer to main VEB or NULL if it does not exist 1411 **/ 1412 static inline struct i40e_veb *i40e_pf_get_main_veb(struct i40e_pf *pf) 1413 { 1414 return (pf->lan_veb != I40E_NO_VEB) ? pf->veb[pf->lan_veb] : NULL; 1415 } 1416 1417 #endif /* _I40E_H_ */ 1418