1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <linux/pci.h> 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/types.h> 10 #include <linux/avf/virtchnl.h> 11 #include <linux/net/intel/i40e_client.h> 12 #include <net/pkt_cls.h> 13 #include <net/udp_tunnel.h> 14 #include "i40e_dcb.h" 15 #include "i40e_debug.h" 16 #include "i40e_io.h" 17 #include "i40e_prototype.h" 18 #include "i40e_register.h" 19 #include "i40e_txrx.h" 20 21 /* Useful i40e defaults */ 22 #define I40E_MAX_VEB 16 23 24 #define I40E_MAX_NUM_DESCRIPTORS 4096 25 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 26 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 27 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 28 #define I40E_MIN_NUM_DESCRIPTORS 64 29 #define I40E_MIN_MSIX 2 30 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 31 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 32 /* max 16 qps */ 33 #define i40e_default_queues_per_vmdq(pf) \ 34 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 35 #define I40E_DEFAULT_QUEUES_PER_VF 4 36 #define I40E_MAX_VF_QUEUES 16 37 #define i40e_pf_get_max_q_per_tc(pf) \ 38 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 39 #define I40E_FDIR_RING_COUNT 32 40 #define I40E_MAX_AQ_BUF_SIZE 4096 41 #define I40E_AQ_LEN 256 42 #define I40E_MIN_ARQ_LEN 1 43 #define I40E_MIN_ASQ_LEN 2 44 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 45 #define I40E_MAX_USER_PRIORITY 8 46 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 47 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 48 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 49 50 #define I40E_NVM_VERSION_LO_SHIFT 0 51 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 52 #define I40E_NVM_VERSION_HI_SHIFT 12 53 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 54 #define I40E_OEM_VER_BUILD_MASK 0xffff 55 #define I40E_OEM_VER_PATCH_MASK 0xff 56 #define I40E_OEM_VER_BUILD_SHIFT 8 57 #define I40E_OEM_VER_SHIFT 24 58 #define I40E_PHY_DEBUG_ALL \ 59 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 60 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 61 62 #define I40E_OEM_EETRACK_ID 0xffffffff 63 #define I40E_OEM_GEN_SHIFT 24 64 #define I40E_OEM_SNAP_MASK 0x00ff0000 65 #define I40E_OEM_SNAP_SHIFT 16 66 #define I40E_OEM_RELEASE_MASK 0x0000ffff 67 68 #define I40E_RX_DESC(R, i) \ 69 (&(((union i40e_rx_desc *)((R)->desc))[i])) 70 #define I40E_TX_DESC(R, i) \ 71 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 72 #define I40E_TX_CTXTDESC(R, i) \ 73 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 74 #define I40E_TX_FDIRDESC(R, i) \ 75 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 76 77 /* BW rate limiting */ 78 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 79 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 80 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 81 82 /* driver state flags */ 83 enum i40e_state_t { 84 __I40E_TESTING, 85 __I40E_CONFIG_BUSY, 86 __I40E_CONFIG_DONE, 87 __I40E_DOWN, 88 __I40E_SERVICE_SCHED, 89 __I40E_ADMINQ_EVENT_PENDING, 90 __I40E_MDD_EVENT_PENDING, 91 __I40E_VFLR_EVENT_PENDING, 92 __I40E_RESET_RECOVERY_PENDING, 93 __I40E_TIMEOUT_RECOVERY_PENDING, 94 __I40E_MISC_IRQ_REQUESTED, 95 __I40E_RESET_INTR_RECEIVED, 96 __I40E_REINIT_REQUESTED, 97 __I40E_PF_RESET_REQUESTED, 98 __I40E_PF_RESET_AND_REBUILD_REQUESTED, 99 __I40E_CORE_RESET_REQUESTED, 100 __I40E_GLOBAL_RESET_REQUESTED, 101 __I40E_EMP_RESET_INTR_RECEIVED, 102 __I40E_SUSPENDED, 103 __I40E_PTP_TX_IN_PROGRESS, 104 __I40E_BAD_EEPROM, 105 __I40E_DOWN_REQUESTED, 106 __I40E_FD_FLUSH_REQUESTED, 107 __I40E_FD_ATR_AUTO_DISABLED, 108 __I40E_FD_SB_AUTO_DISABLED, 109 __I40E_RESET_FAILED, 110 __I40E_PORT_SUSPENDED, 111 __I40E_VF_DISABLE, 112 __I40E_MACVLAN_SYNC_PENDING, 113 __I40E_TEMP_LINK_POLLING, 114 __I40E_CLIENT_SERVICE_REQUESTED, 115 __I40E_CLIENT_L2_CHANGE, 116 __I40E_CLIENT_RESET, 117 __I40E_VIRTCHNL_OP_PENDING, 118 __I40E_RECOVERY_MODE, 119 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */ 120 __I40E_IN_REMOVE, 121 __I40E_VFS_RELEASING, 122 /* This must be last as it determines the size of the BITMAP */ 123 __I40E_STATE_SIZE__, 124 }; 125 126 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 127 #define I40E_PF_RESET_AND_REBUILD_FLAG \ 128 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED) 129 130 /* VSI state flags */ 131 enum i40e_vsi_state_t { 132 __I40E_VSI_DOWN, 133 __I40E_VSI_NEEDS_RESTART, 134 __I40E_VSI_SYNCING_FILTERS, 135 __I40E_VSI_OVERFLOW_PROMISC, 136 __I40E_VSI_REINIT_REQUESTED, 137 __I40E_VSI_DOWN_REQUESTED, 138 __I40E_VSI_RELEASING, 139 /* This must be last as it determines the size of the BITMAP */ 140 __I40E_VSI_STATE_SIZE__, 141 }; 142 143 enum i40e_interrupt_policy { 144 I40E_INTERRUPT_BEST_CASE, 145 I40E_INTERRUPT_MEDIUM, 146 I40E_INTERRUPT_LOWEST 147 }; 148 149 struct i40e_lump_tracking { 150 u16 num_entries; 151 u16 list[]; 152 #define I40E_PILE_VALID_BIT 0x8000 153 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 154 }; 155 156 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 157 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 158 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 159 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 160 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 161 162 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 163 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 164 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 165 166 enum i40e_fd_stat_idx { 167 I40E_FD_STAT_ATR, 168 I40E_FD_STAT_SB, 169 I40E_FD_STAT_ATR_TUNNEL, 170 I40E_FD_STAT_PF_COUNT 171 }; 172 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 173 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 174 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 175 #define I40E_FD_SB_STAT_IDX(pf_id) \ 176 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 177 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 178 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 179 180 /* The following structure contains the data parsed from the user-defined 181 * field of the ethtool_rx_flow_spec structure. 182 */ 183 struct i40e_rx_flow_userdef { 184 bool flex_filter; 185 u16 flex_word; 186 u16 flex_offset; 187 }; 188 189 struct i40e_fdir_filter { 190 struct hlist_node fdir_node; 191 /* filter ipnut set */ 192 u8 flow_type; 193 u8 ipl4_proto; 194 /* TX packet view of src and dst */ 195 __be32 dst_ip; 196 __be32 src_ip; 197 __be32 dst_ip6[4]; 198 __be32 src_ip6[4]; 199 __be16 src_port; 200 __be16 dst_port; 201 __be32 sctp_v_tag; 202 203 __be16 vlan_etype; 204 __be16 vlan_tag; 205 /* Flexible data to match within the packet payload */ 206 __be16 flex_word; 207 u16 flex_offset; 208 bool flex_filter; 209 210 /* filter control */ 211 u16 q_index; 212 u8 flex_off; 213 u8 pctype; 214 u16 dest_vsi; 215 u8 dest_ctl; 216 u8 fd_status; 217 u16 cnt_index; 218 u32 fd_id; 219 }; 220 221 #define I40E_CLOUD_FIELD_OMAC BIT(0) 222 #define I40E_CLOUD_FIELD_IMAC BIT(1) 223 #define I40E_CLOUD_FIELD_IVLAN BIT(2) 224 #define I40E_CLOUD_FIELD_TEN_ID BIT(3) 225 #define I40E_CLOUD_FIELD_IIP BIT(4) 226 227 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 228 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 229 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 230 I40E_CLOUD_FIELD_IVLAN) 231 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 232 I40E_CLOUD_FIELD_TEN_ID) 233 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 234 I40E_CLOUD_FIELD_IMAC | \ 235 I40E_CLOUD_FIELD_TEN_ID) 236 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 237 I40E_CLOUD_FIELD_IVLAN | \ 238 I40E_CLOUD_FIELD_TEN_ID) 239 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 240 241 struct i40e_cloud_filter { 242 struct hlist_node cloud_node; 243 unsigned long cookie; 244 /* cloud filter input set follows */ 245 u8 dst_mac[ETH_ALEN]; 246 u8 src_mac[ETH_ALEN]; 247 __be16 vlan_id; 248 u16 seid; /* filter control */ 249 __be16 dst_port; 250 __be16 src_port; 251 u32 tenant_id; 252 union { 253 struct { 254 struct in_addr dst_ip; 255 struct in_addr src_ip; 256 } v4; 257 struct { 258 struct in6_addr dst_ip6; 259 struct in6_addr src_ip6; 260 } v6; 261 } ip; 262 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 263 #define src_ipv6 ip.v6.src_ip6.s6_addr32 264 #define dst_ipv4 ip.v4.dst_ip.s_addr 265 #define src_ipv4 ip.v4.src_ip.s_addr 266 u16 n_proto; /* Ethernet Protocol */ 267 u8 ip_proto; /* IPPROTO value */ 268 u8 flags; 269 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 270 u8 tunnel_type; 271 }; 272 273 #define I40E_DCB_PRIO_TYPE_STRICT 0 274 #define I40E_DCB_PRIO_TYPE_ETS 1 275 #define I40E_DCB_STRICT_PRIO_CREDITS 127 276 /* DCB per TC information data structure */ 277 struct i40e_tc_info { 278 u16 qoffset; /* Queue offset from base queue */ 279 u16 qcount; /* Total Queues */ 280 u8 netdev_tc; /* Netdev TC index if netdev associated */ 281 }; 282 283 /* TC configuration data structure */ 284 struct i40e_tc_configuration { 285 u8 numtc; /* Total number of enabled TCs */ 286 u8 enabled_tc; /* TC map */ 287 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 288 }; 289 290 #define I40E_UDP_PORT_INDEX_UNUSED 255 291 struct i40e_udp_port_config { 292 /* AdminQ command interface expects port number in Host byte order */ 293 u16 port; 294 u8 type; 295 u8 filter_index; 296 }; 297 298 /* macros related to FLX_PIT */ 299 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 300 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 301 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 302 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 303 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 304 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 305 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 306 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 307 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 308 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 309 I40E_FLEX_SET_FSIZE(fsize) | \ 310 I40E_FLEX_SET_SRC_WORD(src)) 311 312 313 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 314 315 /* macros related to GLQF_ORT */ 316 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 317 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 318 I40E_GLQF_ORT_PIT_INDX_MASK) 319 320 #define I40E_ORT_SET_COUNT(count) (((count) << \ 321 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 322 I40E_GLQF_ORT_FIELD_CNT_MASK) 323 324 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 325 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 326 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 327 328 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 329 I40E_ORT_SET_COUNT(count) | \ 330 I40E_ORT_SET_PAYLOAD(payload)) 331 332 #define I40E_L3_GLQF_ORT_IDX 34 333 #define I40E_L4_GLQF_ORT_IDX 35 334 335 /* Flex PIT register index */ 336 #define I40E_FLEX_PIT_IDX_START_L3 3 337 #define I40E_FLEX_PIT_IDX_START_L4 6 338 339 #define I40E_FLEX_PIT_TABLE_SIZE 3 340 341 #define I40E_FLEX_DEST_UNUSED 63 342 343 #define I40E_FLEX_INDEX_ENTRIES 8 344 345 /* Flex MASK to disable all flexible entries */ 346 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 347 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 348 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 349 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 350 351 #define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \ 352 (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \ 353 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \ 354 ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \ 355 ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \ 356 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)) 357 358 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \ 359 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \ 360 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \ 361 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \ 362 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \ 363 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)) 364 365 struct i40e_flex_pit { 366 struct list_head list; 367 u16 src_offset; 368 u8 pit_index; 369 }; 370 371 struct i40e_fwd_adapter { 372 struct net_device *netdev; 373 int bit_no; 374 }; 375 376 struct i40e_channel { 377 struct list_head list; 378 bool initialized; 379 u8 type; 380 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 381 u16 stat_counter_idx; 382 u16 base_queue; 383 u16 num_queue_pairs; /* Requested by user */ 384 u16 seid; 385 386 u8 enabled_tc; 387 struct i40e_aqc_vsi_properties_data info; 388 389 u64 max_tx_rate; 390 struct i40e_fwd_adapter *fwd; 391 392 /* track this channel belongs to which VSI */ 393 struct i40e_vsi *parent_vsi; 394 }; 395 396 struct i40e_ptp_pins_settings; 397 398 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch) 399 { 400 return !!ch->fwd; 401 } 402 403 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch) 404 { 405 if (i40e_is_channel_macvlan(ch)) 406 return ch->fwd->netdev->dev_addr; 407 else 408 return NULL; 409 } 410 411 /* struct that defines the Ethernet device */ 412 struct i40e_pf { 413 struct pci_dev *pdev; 414 struct i40e_hw hw; 415 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 416 struct msix_entry *msix_entries; 417 bool fc_autoneg_status; 418 419 u16 eeprom_version; 420 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 421 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 422 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 423 u16 num_req_vfs; /* num VFs requested for this PF */ 424 u16 num_vf_qps; /* num queue pairs per VF */ 425 u16 num_lan_qps; /* num lan queues this PF has set up */ 426 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 427 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 428 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 429 int iwarp_base_vector; 430 int queues_left; /* queues left unclaimed */ 431 u16 alloc_rss_size; /* allocated RSS queues */ 432 u16 rss_size_max; /* HW defined max RSS queues */ 433 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 434 u16 num_alloc_vsi; /* num VSIs this driver supports */ 435 u8 atr_sample_rate; 436 bool wol_en; 437 438 struct hlist_head fdir_filter_list; 439 u16 fdir_pf_active_filters; 440 unsigned long fd_flush_timestamp; 441 u32 fd_flush_cnt; 442 u32 fd_add_err; 443 u32 fd_atr_cnt; 444 445 /* Book-keeping of side-band filter count per flow-type. 446 * This is used to detect and handle input set changes for 447 * respective flow-type. 448 */ 449 u16 fd_tcp4_filter_cnt; 450 u16 fd_udp4_filter_cnt; 451 u16 fd_sctp4_filter_cnt; 452 u16 fd_ip4_filter_cnt; 453 454 u16 fd_tcp6_filter_cnt; 455 u16 fd_udp6_filter_cnt; 456 u16 fd_sctp6_filter_cnt; 457 u16 fd_ip6_filter_cnt; 458 459 /* Flexible filter table values that need to be programmed into 460 * hardware, which expects L3 and L4 to be programmed separately. We 461 * need to ensure that the values are in ascended order and don't have 462 * duplicates, so we track each L3 and L4 values in separate lists. 463 */ 464 struct list_head l3_flex_pit_list; 465 struct list_head l4_flex_pit_list; 466 467 struct udp_tunnel_nic_shared udp_tunnel_shared; 468 struct udp_tunnel_nic_info udp_tunnel_nic; 469 470 struct hlist_head cloud_filter_list; 471 u16 num_cloud_filters; 472 473 enum i40e_interrupt_policy int_policy; 474 u16 rx_itr_default; 475 u16 tx_itr_default; 476 u32 msg_enable; 477 char int_name[I40E_INT_NAME_STR_LEN]; 478 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 479 unsigned long service_timer_period; 480 unsigned long service_timer_previous; 481 struct timer_list service_timer; 482 struct work_struct service_task; 483 484 u32 hw_features; 485 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 486 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 487 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 488 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 489 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 490 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 491 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 492 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 493 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 494 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 495 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 496 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 497 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 498 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 499 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 500 #define I40E_HW_STOP_FW_LLDP BIT(16) 501 #define I40E_HW_PORT_ID_VALID BIT(17) 502 #define I40E_HW_RESTART_AUTONEG BIT(18) 503 504 u32 flags; 505 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 506 #define I40E_FLAG_MSI_ENABLED BIT(1) 507 #define I40E_FLAG_MSIX_ENABLED BIT(2) 508 #define I40E_FLAG_RSS_ENABLED BIT(3) 509 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 510 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 511 #define I40E_FLAG_DCB_CAPABLE BIT(6) 512 #define I40E_FLAG_DCB_ENABLED BIT(7) 513 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 514 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 515 #define I40E_FLAG_MFP_ENABLED BIT(10) 516 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 517 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 518 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 519 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 520 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 521 #define I40E_FLAG_LEGACY_RX BIT(16) 522 #define I40E_FLAG_PTP BIT(17) 523 #define I40E_FLAG_IWARP_ENABLED BIT(18) 524 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 525 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 526 #define I40E_FLAG_TC_MQPRIO BIT(21) 527 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 528 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 529 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 530 #define I40E_FLAG_RS_FEC BIT(25) 531 #define I40E_FLAG_BASE_R_FEC BIT(26) 532 #define I40E_FLAG_VF_VLAN_PRUNING BIT(27) 533 /* TOTAL_PORT_SHUTDOWN 534 * Allows to physically disable the link on the NIC's port. 535 * If enabled, (after link down request from the OS) 536 * no link, traffic or led activity is possible on that port. 537 * 538 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the 539 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true 540 * and cannot be disabled by system admin at that time. 541 * The functionalities are exclusive in terms of configuration, but they also 542 * have similar behavior (allowing to disable physical link of the port), 543 * with following differences: 544 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is 545 * supported by whole family of 7xx Intel Ethernet Controllers 546 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS) 547 * only if motherboard's BIOS and NIC's FW has support of it 548 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down 549 * by sending phy_type=0 to NIC's FW 550 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead 551 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK) 552 * in abilities field of i40e_aq_set_phy_config structure 553 */ 554 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27) 555 556 struct i40e_client_instance *cinst; 557 bool stat_offsets_loaded; 558 struct i40e_hw_port_stats stats; 559 struct i40e_hw_port_stats stats_offsets; 560 u32 tx_timeout_count; 561 u32 tx_timeout_recovery_level; 562 unsigned long tx_timeout_last_recovery; 563 u32 tx_sluggish_count; 564 u32 hw_csum_rx_error; 565 u32 led_status; 566 u16 corer_count; /* Core reset count */ 567 u16 globr_count; /* Global reset count */ 568 u16 empr_count; /* EMP reset count */ 569 u16 pfr_count; /* PF reset count */ 570 u16 sw_int_count; /* SW interrupt count */ 571 572 struct mutex switch_mutex; 573 u16 lan_vsi; /* our default LAN VSI */ 574 u16 lan_veb; /* initial relay, if exists */ 575 #define I40E_NO_VEB 0xffff 576 #define I40E_NO_VSI 0xffff 577 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 578 struct i40e_vsi **vsi; 579 struct i40e_veb *veb[I40E_MAX_VEB]; 580 581 struct i40e_lump_tracking *qp_pile; 582 struct i40e_lump_tracking *irq_pile; 583 584 /* switch config info */ 585 u16 pf_seid; 586 u16 main_vsi_seid; 587 u16 mac_seid; 588 struct kobject *switch_kobj; 589 #ifdef CONFIG_DEBUG_FS 590 struct dentry *i40e_dbg_pf; 591 #endif /* CONFIG_DEBUG_FS */ 592 bool cur_promisc; 593 594 u16 instance; /* A unique number per i40e_pf instance in the system */ 595 596 /* sr-iov config info */ 597 struct i40e_vf *vf; 598 int num_alloc_vfs; /* actual number of VFs allocated */ 599 u32 vf_aq_requests; 600 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 601 602 /* DCBx/DCBNL capability for PF that indicates 603 * whether DCBx is managed by firmware or host 604 * based agent (LLDPAD). Also, indicates what 605 * flavor of DCBx protocol (IEEE/CEE) is supported 606 * by the device. For now we're supporting IEEE 607 * mode only. 608 */ 609 u16 dcbx_cap; 610 611 struct i40e_filter_control_settings filter_settings; 612 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */ 613 struct i40e_dcbx_config tmp_cfg; 614 615 /* GPIO defines used by PTP */ 616 #define I40E_SDP3_2 18 617 #define I40E_SDP3_3 19 618 #define I40E_GPIO_4 20 619 #define I40E_LED2_0 26 620 #define I40E_LED2_1 27 621 #define I40E_LED3_0 28 622 #define I40E_LED3_1 29 623 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \ 624 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 625 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \ 626 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 627 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \ 628 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 629 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \ 630 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 631 #define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2) 632 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \ 633 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 634 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \ 635 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) 636 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \ 637 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) 638 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \ 639 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) 640 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \ 641 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 642 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \ 643 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 644 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \ 645 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) 646 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \ 647 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 648 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \ 649 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 650 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 651 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 652 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \ 653 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 654 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 655 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 656 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \ 657 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 658 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 659 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 660 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 661 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \ 662 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 663 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 664 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 665 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 666 #define I40E_GLGEN_GPIO_CTL_LED_INIT \ 667 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \ 668 I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 669 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \ 670 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 671 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \ 672 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN) 673 #define I40E_PRTTSYN_AUX_1_INSTNT \ 674 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) 675 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \ 676 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) 677 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) 678 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \ 679 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD) 680 #define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */ 681 #define I40E_PTP_2_SEC_DELAY 2 682 683 struct ptp_clock *ptp_clock; 684 struct ptp_clock_info ptp_caps; 685 struct sk_buff *ptp_tx_skb; 686 unsigned long ptp_tx_start; 687 struct hwtstamp_config tstamp_config; 688 struct timespec64 ptp_prev_hw_time; 689 struct work_struct ptp_pps_work; 690 struct work_struct ptp_extts0_work; 691 struct work_struct ptp_extts1_work; 692 ktime_t ptp_reset_start; 693 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 694 u32 ptp_adj_mult; 695 u32 tx_hwtstamp_timeouts; 696 u32 tx_hwtstamp_skipped; 697 u32 rx_hwtstamp_cleared; 698 u32 latch_event_flags; 699 u64 ptp_pps_start; 700 u32 pps_delay; 701 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 702 struct ptp_pin_desc ptp_pin[3]; 703 unsigned long latch_events[4]; 704 bool ptp_tx; 705 bool ptp_rx; 706 struct i40e_ptp_pins_settings *ptp_pins; 707 u16 rss_table_size; /* HW RSS table size */ 708 u32 max_bw; 709 u32 min_bw; 710 711 u32 ioremap_len; 712 u32 fd_inv; 713 u16 phy_led_val; 714 715 u16 override_q_count; 716 u16 last_sw_conf_flags; 717 u16 last_sw_conf_valid_flags; 718 /* List to keep previous DDP profiles to be rolled back in the future */ 719 struct list_head ddp_old_prof; 720 }; 721 722 /** 723 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 724 * @macaddr: the MAC Address as the base key 725 * 726 * Simply copies the address and returns it as a u64 for hashing 727 **/ 728 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 729 { 730 u64 key = 0; 731 732 ether_addr_copy((u8 *)&key, macaddr); 733 return key; 734 } 735 736 enum i40e_filter_state { 737 I40E_FILTER_INVALID = 0, /* Invalid state */ 738 I40E_FILTER_NEW, /* New, not sent to FW yet */ 739 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 740 I40E_FILTER_FAILED, /* Rejected by FW */ 741 I40E_FILTER_REMOVE, /* To be removed */ 742 /* There is no 'removed' state; the filter struct is freed */ 743 }; 744 struct i40e_mac_filter { 745 struct hlist_node hlist; 746 u8 macaddr[ETH_ALEN]; 747 #define I40E_VLAN_ANY -1 748 s16 vlan; 749 enum i40e_filter_state state; 750 }; 751 752 /* Wrapper structure to keep track of filters while we are preparing to send 753 * firmware commands. We cannot send firmware commands while holding a 754 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 755 * a separate structure, which will track the state change and update the real 756 * filter while under lock. We can't simply hold the filters in a separate 757 * list, as this opens a window for a race condition when adding new MAC 758 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 759 */ 760 struct i40e_new_mac_filter { 761 struct hlist_node hlist; 762 struct i40e_mac_filter *f; 763 764 /* Track future changes to state separately */ 765 enum i40e_filter_state state; 766 }; 767 768 struct i40e_veb { 769 struct i40e_pf *pf; 770 u16 idx; 771 u16 veb_idx; /* index of VEB parent */ 772 u16 seid; 773 u16 uplink_seid; 774 u16 stats_idx; /* index of VEB parent */ 775 u8 enabled_tc; 776 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 777 u16 flags; 778 u16 bw_limit; 779 u8 bw_max_quanta; 780 bool is_abs_credits; 781 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 782 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 783 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 784 struct kobject *kobj; 785 bool stat_offsets_loaded; 786 struct i40e_eth_stats stats; 787 struct i40e_eth_stats stats_offsets; 788 struct i40e_veb_tc_stats tc_stats; 789 struct i40e_veb_tc_stats tc_stats_offsets; 790 }; 791 792 /* struct that defines a VSI, associated with a dev */ 793 struct i40e_vsi { 794 struct net_device *netdev; 795 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 796 bool netdev_registered; 797 bool stat_offsets_loaded; 798 799 u32 current_netdev_flags; 800 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 801 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 802 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 803 unsigned long flags; 804 805 /* Per VSI lock to protect elements/hash (MAC filter) */ 806 spinlock_t mac_filter_hash_lock; 807 /* Fixed size hash table with 2^8 buckets for MAC filters */ 808 DECLARE_HASHTABLE(mac_filter_hash, 8); 809 bool has_vlan_filter; 810 811 /* VSI stats */ 812 struct rtnl_link_stats64 net_stats; 813 struct rtnl_link_stats64 net_stats_offsets; 814 struct i40e_eth_stats eth_stats; 815 struct i40e_eth_stats eth_stats_offsets; 816 u64 tx_restart; 817 u64 tx_busy; 818 u64 tx_linearize; 819 u64 tx_force_wb; 820 u64 tx_stopped; 821 u64 rx_buf_failed; 822 u64 rx_page_failed; 823 u64 rx_page_reuse; 824 u64 rx_page_alloc; 825 u64 rx_page_waive; 826 u64 rx_page_busy; 827 828 /* These are containers of ring pointers, allocated at run-time */ 829 struct i40e_ring **rx_rings; 830 struct i40e_ring **tx_rings; 831 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 832 833 u32 active_filters; 834 u32 promisc_threshold; 835 836 u16 work_limit; 837 u16 int_rate_limit; /* value in usecs */ 838 839 u16 rss_table_size; /* HW RSS table size */ 840 u16 rss_size; /* Allocated RSS queues */ 841 u8 *rss_hkey_user; /* User configured hash keys */ 842 u8 *rss_lut_user; /* User configured lookup table entries */ 843 844 845 u16 max_frame; 846 u16 rx_buf_len; 847 848 struct bpf_prog *xdp_prog; 849 850 /* List of q_vectors allocated to this VSI */ 851 struct i40e_q_vector **q_vectors; 852 int num_q_vectors; 853 int base_vector; 854 bool irqs_ready; 855 856 u16 seid; /* HW index of this VSI (absolute index) */ 857 u16 id; /* VSI number */ 858 u16 uplink_seid; 859 860 u16 base_queue; /* vsi's first queue in hw array */ 861 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 862 u16 req_queue_pairs; /* User requested queue pairs */ 863 u16 num_queue_pairs; /* Used tx and rx pairs */ 864 u16 num_tx_desc; 865 u16 num_rx_desc; 866 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 867 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 868 869 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 870 struct i40e_tc_configuration tc_config; 871 struct i40e_aqc_vsi_properties_data info; 872 873 /* VSI BW limit (absolute across all TCs) */ 874 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 875 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 876 877 /* Relative TC credits across VSIs */ 878 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 879 /* TC BW limit credits within VSI */ 880 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 881 /* TC BW limit max quanta within VSI */ 882 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 883 884 struct i40e_pf *back; /* Backreference to associated PF */ 885 u16 idx; /* index in pf->vsi[] */ 886 u16 veb_idx; /* index of VEB parent */ 887 struct kobject *kobj; /* sysfs object */ 888 bool current_isup; /* Sync 'link up' logging */ 889 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 890 891 /* channel specific fields */ 892 u16 cnt_q_avail; /* num of queues available for channel usage */ 893 u16 orig_rss_size; 894 u16 current_rss_size; 895 bool reconfig_rss; 896 897 u16 next_base_queue; /* next queue to be used for channel setup */ 898 899 struct list_head ch_list; 900 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 901 902 /* macvlan fields */ 903 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */ 904 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */ 905 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS); 906 struct list_head macvlan_list; 907 int macvlan_cnt; 908 909 void *priv; /* client driver data reference. */ 910 911 /* VSI specific handlers */ 912 irqreturn_t (*irq_handler)(int irq, void *data); 913 914 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 915 } ____cacheline_internodealigned_in_smp; 916 917 struct i40e_netdev_priv { 918 struct i40e_vsi *vsi; 919 }; 920 921 extern struct ida i40e_client_ida; 922 923 /* struct that defines an interrupt vector */ 924 struct i40e_q_vector { 925 struct i40e_vsi *vsi; 926 927 u16 v_idx; /* index in the vsi->q_vector array. */ 928 u16 reg_idx; /* register index of the interrupt */ 929 930 struct napi_struct napi; 931 932 struct i40e_ring_container rx; 933 struct i40e_ring_container tx; 934 935 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 936 u8 num_ringpairs; /* total number of ring pairs in vector */ 937 938 cpumask_t affinity_mask; 939 struct irq_affinity_notify affinity_notify; 940 941 struct rcu_head rcu; /* to avoid race with update stats on free */ 942 char name[I40E_INT_NAME_STR_LEN]; 943 bool arm_wb_state; 944 int irq_num; /* IRQ assigned to this q_vector */ 945 } ____cacheline_internodealigned_in_smp; 946 947 /* lan device */ 948 struct i40e_device { 949 struct list_head list; 950 struct i40e_pf *pf; 951 }; 952 953 /** 954 * i40e_nvm_version_str - format the NVM version strings 955 * @hw: ptr to the hardware info 956 **/ 957 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 958 { 959 static char buf[32]; 960 u32 full_ver; 961 962 full_ver = hw->nvm.oem_ver; 963 964 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 965 u8 gen, snap; 966 u16 release; 967 968 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 969 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 970 I40E_OEM_SNAP_SHIFT); 971 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 972 973 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 974 } else { 975 u8 ver, patch; 976 u16 build; 977 978 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 979 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 980 I40E_OEM_VER_BUILD_MASK); 981 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 982 983 snprintf(buf, sizeof(buf), 984 "%x.%02x 0x%x %d.%d.%d", 985 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 986 I40E_NVM_VERSION_HI_SHIFT, 987 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 988 I40E_NVM_VERSION_LO_SHIFT, 989 hw->nvm.eetrack, ver, build, patch); 990 } 991 992 return buf; 993 } 994 995 /** 996 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 997 * @netdev: the corresponding netdev 998 * 999 * Return the PF struct for the given netdev 1000 **/ 1001 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 1002 { 1003 struct i40e_netdev_priv *np = netdev_priv(netdev); 1004 struct i40e_vsi *vsi = np->vsi; 1005 1006 return vsi->back; 1007 } 1008 1009 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 1010 irqreturn_t (*irq_handler)(int, void *)) 1011 { 1012 vsi->irq_handler = irq_handler; 1013 } 1014 1015 /** 1016 * i40e_get_fd_cnt_all - get the total FD filter space available 1017 * @pf: pointer to the PF struct 1018 **/ 1019 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 1020 { 1021 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 1022 } 1023 1024 /** 1025 * i40e_read_fd_input_set - reads value of flow director input set register 1026 * @pf: pointer to the PF struct 1027 * @addr: register addr 1028 * 1029 * This function reads value of flow director input set register 1030 * specified by 'addr' (which is specific to flow-type) 1031 **/ 1032 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 1033 { 1034 u64 val; 1035 1036 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 1037 val <<= 32; 1038 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 1039 1040 return val; 1041 } 1042 1043 /** 1044 * i40e_write_fd_input_set - writes value into flow director input set register 1045 * @pf: pointer to the PF struct 1046 * @addr: register addr 1047 * @val: value to be written 1048 * 1049 * This function writes specified value to the register specified by 'addr'. 1050 * This register is input set register based on flow-type. 1051 **/ 1052 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 1053 u16 addr, u64 val) 1054 { 1055 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 1056 (u32)(val >> 32)); 1057 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 1058 (u32)(val & 0xFFFFFFFFULL)); 1059 } 1060 1061 /** 1062 * i40e_get_pf_count - get PCI PF count. 1063 * @hw: pointer to a hw. 1064 * 1065 * Reports the function number of the highest PCI physical 1066 * function plus 1 as it is loaded from the NVM. 1067 * 1068 * Return: PCI PF count. 1069 **/ 1070 static inline u32 i40e_get_pf_count(struct i40e_hw *hw) 1071 { 1072 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK, 1073 rd32(hw, I40E_GLGEN_PCIFCNCNT)); 1074 } 1075 1076 /* needed by i40e_ethtool.c */ 1077 int i40e_up(struct i40e_vsi *vsi); 1078 void i40e_down(struct i40e_vsi *vsi); 1079 extern const char i40e_driver_name[]; 1080 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 1081 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 1082 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1083 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1084 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 1085 u16 rss_table_size, u16 rss_size); 1086 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 1087 /** 1088 * i40e_find_vsi_by_type - Find and return Flow Director VSI 1089 * @pf: PF to search for VSI 1090 * @type: Value indicating type of VSI we are looking for 1091 **/ 1092 static inline struct i40e_vsi * 1093 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 1094 { 1095 int i; 1096 1097 for (i = 0; i < pf->num_alloc_vsi; i++) { 1098 struct i40e_vsi *vsi = pf->vsi[i]; 1099 1100 if (vsi && vsi->type == type) 1101 return vsi; 1102 } 1103 1104 return NULL; 1105 } 1106 void i40e_update_stats(struct i40e_vsi *vsi); 1107 void i40e_update_veb_stats(struct i40e_veb *veb); 1108 void i40e_update_eth_stats(struct i40e_vsi *vsi); 1109 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 1110 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1111 bool printconfig); 1112 1113 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1114 struct i40e_fdir_filter *input, bool add); 1115 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1116 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1117 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1118 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1119 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1120 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1121 void i40e_set_ethtool_ops(struct net_device *netdev); 1122 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1123 const u8 *macaddr, s16 vlan); 1124 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1125 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1126 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1127 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1128 u16 uplink, u32 param1); 1129 int i40e_vsi_release(struct i40e_vsi *vsi); 1130 void i40e_service_event_schedule(struct i40e_pf *pf); 1131 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1132 u8 *msg, u16 len); 1133 1134 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1135 bool enable); 1136 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1137 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1138 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1139 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1140 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1141 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1142 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1143 u16 downlink_seid, u8 enabled_tc); 1144 void i40e_veb_release(struct i40e_veb *veb); 1145 1146 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1147 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1148 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1149 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1150 void i40e_pf_reset_stats(struct i40e_pf *pf); 1151 #ifdef CONFIG_DEBUG_FS 1152 void i40e_dbg_pf_init(struct i40e_pf *pf); 1153 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1154 void i40e_dbg_init(void); 1155 void i40e_dbg_exit(void); 1156 #else 1157 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1158 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1159 static inline void i40e_dbg_init(void) {} 1160 static inline void i40e_dbg_exit(void) {} 1161 #endif /* CONFIG_DEBUG_FS*/ 1162 /* needed by client drivers */ 1163 int i40e_lan_add_device(struct i40e_pf *pf); 1164 int i40e_lan_del_device(struct i40e_pf *pf); 1165 void i40e_client_subtask(struct i40e_pf *pf); 1166 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1167 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1168 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1169 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1170 void i40e_client_update_msix_info(struct i40e_pf *pf); 1171 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1172 /** 1173 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1174 * @vsi: pointer to a vsi 1175 * @vector: enable a particular Hw Interrupt vector, without base_vector 1176 **/ 1177 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1178 { 1179 struct i40e_pf *pf = vsi->back; 1180 struct i40e_hw *hw = &pf->hw; 1181 u32 val; 1182 1183 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1184 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1185 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1186 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1187 /* skip the flush */ 1188 } 1189 1190 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1191 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1192 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1193 int i40e_open(struct net_device *netdev); 1194 int i40e_close(struct net_device *netdev); 1195 int i40e_vsi_open(struct i40e_vsi *vsi); 1196 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1197 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1198 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1199 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1200 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1201 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1202 const u8 *macaddr); 1203 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1204 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1205 int i40e_count_filters(struct i40e_vsi *vsi); 1206 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1207 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1208 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf) 1209 { 1210 return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP); 1211 } 1212 1213 #ifdef CONFIG_I40E_DCB 1214 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1215 struct i40e_dcbx_config *old_cfg, 1216 struct i40e_dcbx_config *new_cfg); 1217 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1218 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1219 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1220 struct i40e_dcbx_config *old_cfg, 1221 struct i40e_dcbx_config *new_cfg); 1222 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg); 1223 int i40e_dcb_sw_default_config(struct i40e_pf *pf); 1224 #endif /* CONFIG_I40E_DCB */ 1225 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1226 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1227 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1228 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1229 void i40e_ptp_set_increment(struct i40e_pf *pf); 1230 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1231 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1232 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1233 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1234 void i40e_ptp_init(struct i40e_pf *pf); 1235 void i40e_ptp_stop(struct i40e_pf *pf); 1236 int i40e_ptp_alloc_pins(struct i40e_pf *pf); 1237 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset); 1238 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1239 int i40e_get_partition_bw_setting(struct i40e_pf *pf); 1240 int i40e_set_partition_bw_setting(struct i40e_pf *pf); 1241 int i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1242 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1243 1244 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1245 1246 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1247 { 1248 return !!READ_ONCE(vsi->xdp_prog); 1249 } 1250 1251 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1252 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1253 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1254 struct i40e_cloud_filter *filter, 1255 bool add); 1256 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1257 struct i40e_cloud_filter *filter, 1258 bool add); 1259 1260 /** 1261 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF 1262 * @pf: pointer to a pf. 1263 * 1264 * Check and return value of flag I40E_FLAG_TC_MQPRIO. 1265 * 1266 * Return: I40E_FLAG_TC_MQPRIO set state. 1267 **/ 1268 static inline u32 i40e_is_tc_mqprio_enabled(struct i40e_pf *pf) 1269 { 1270 return pf->flags & I40E_FLAG_TC_MQPRIO; 1271 } 1272 1273 /** 1274 * i40e_hw_to_pf - get pf pointer from the hardware structure 1275 * @hw: pointer to the device HW structure 1276 **/ 1277 static inline struct i40e_pf *i40e_hw_to_pf(struct i40e_hw *hw) 1278 { 1279 return container_of(hw, struct i40e_pf, hw); 1280 } 1281 1282 struct device *i40e_hw_to_dev(struct i40e_hw *hw); 1283 1284 #endif /* _I40E_H_ */ 1285