1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <linux/pci.h> 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/types.h> 10 #include <linux/avf/virtchnl.h> 11 #include <linux/net/intel/i40e_client.h> 12 #include <net/devlink.h> 13 #include <net/pkt_cls.h> 14 #include <net/udp_tunnel.h> 15 #include "i40e_dcb.h" 16 #include "i40e_debug.h" 17 #include "i40e_devlink.h" 18 #include "i40e_io.h" 19 #include "i40e_prototype.h" 20 #include "i40e_register.h" 21 #include "i40e_txrx.h" 22 23 /* Useful i40e defaults */ 24 #define I40E_MAX_VEB 16 25 26 #define I40E_MAX_NUM_DESCRIPTORS 4096 27 #define I40E_MAX_NUM_DESCRIPTORS_XL710 8160 28 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 29 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 30 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 31 #define I40E_MIN_NUM_DESCRIPTORS 64 32 #define I40E_MIN_MSIX 2 33 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 34 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 35 /* max 16 qps */ 36 #define i40e_default_queues_per_vmdq(pf) \ 37 (test_bit(I40E_HW_CAP_RSS_AQ, (pf)->hw.caps) ? 4 : 1) 38 #define I40E_DEFAULT_QUEUES_PER_VF 4 39 #define I40E_MAX_VF_QUEUES 16 40 #define i40e_pf_get_max_q_per_tc(pf) \ 41 (test_bit(I40E_HW_CAP_128_QP_RSS, (pf)->hw.caps) ? 128 : 64) 42 #define I40E_FDIR_RING_COUNT 32 43 #define I40E_MAX_AQ_BUF_SIZE 4096 44 #define I40E_AQ_LEN 256 45 #define I40E_MIN_ARQ_LEN 1 46 #define I40E_MIN_ASQ_LEN 2 47 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 48 #define I40E_MAX_USER_PRIORITY 8 49 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 50 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 51 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 52 53 #define I40E_PHY_DEBUG_ALL \ 54 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 55 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 56 57 #define I40E_OEM_EETRACK_ID 0xffffffff 58 #define I40E_NVM_VERSION_LO_MASK GENMASK(7, 0) 59 #define I40E_NVM_VERSION_HI_MASK GENMASK(15, 12) 60 #define I40E_OEM_VER_BUILD_MASK GENMASK(23, 8) 61 #define I40E_OEM_VER_PATCH_MASK GENMASK(7, 0) 62 #define I40E_OEM_VER_MASK GENMASK(31, 24) 63 #define I40E_OEM_GEN_MASK GENMASK(31, 24) 64 #define I40E_OEM_SNAP_MASK GENMASK(23, 16) 65 #define I40E_OEM_RELEASE_MASK GENMASK(15, 0) 66 67 #define I40E_RX_DESC(R, i) \ 68 (&(((union i40e_rx_desc *)((R)->desc))[i])) 69 #define I40E_TX_DESC(R, i) \ 70 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 71 #define I40E_TX_CTXTDESC(R, i) \ 72 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 73 #define I40E_TX_FDIRDESC(R, i) \ 74 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 75 76 /* BW rate limiting */ 77 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 78 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 79 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 80 81 /* driver state flags */ 82 enum i40e_state { 83 __I40E_TESTING, 84 __I40E_CONFIG_BUSY, 85 __I40E_CONFIG_DONE, 86 __I40E_DOWN, 87 __I40E_SERVICE_SCHED, 88 __I40E_ADMINQ_EVENT_PENDING, 89 __I40E_MDD_EVENT_PENDING, 90 __I40E_VFLR_EVENT_PENDING, 91 __I40E_RESET_RECOVERY_PENDING, 92 __I40E_TIMEOUT_RECOVERY_PENDING, 93 __I40E_MISC_IRQ_REQUESTED, 94 __I40E_RESET_INTR_RECEIVED, 95 __I40E_REINIT_REQUESTED, 96 __I40E_PF_RESET_REQUESTED, 97 __I40E_PF_RESET_AND_REBUILD_REQUESTED, 98 __I40E_CORE_RESET_REQUESTED, 99 __I40E_GLOBAL_RESET_REQUESTED, 100 __I40E_EMP_RESET_INTR_RECEIVED, 101 __I40E_SUSPENDED, 102 __I40E_PTP_TX_IN_PROGRESS, 103 __I40E_BAD_EEPROM, 104 __I40E_DOWN_REQUESTED, 105 __I40E_FD_FLUSH_REQUESTED, 106 __I40E_FD_ATR_AUTO_DISABLED, 107 __I40E_FD_SB_AUTO_DISABLED, 108 __I40E_RESET_FAILED, 109 __I40E_PORT_SUSPENDED, 110 __I40E_VF_DISABLE, 111 __I40E_MACVLAN_SYNC_PENDING, 112 __I40E_TEMP_LINK_POLLING, 113 __I40E_CLIENT_SERVICE_REQUESTED, 114 __I40E_CLIENT_L2_CHANGE, 115 __I40E_CLIENT_RESET, 116 __I40E_VIRTCHNL_OP_PENDING, 117 __I40E_RECOVERY_MODE, 118 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */ 119 __I40E_IN_REMOVE, 120 __I40E_VFS_RELEASING, 121 /* This must be last as it determines the size of the BITMAP */ 122 __I40E_STATE_SIZE__, 123 }; 124 125 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 126 #define I40E_PF_RESET_AND_REBUILD_FLAG \ 127 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED) 128 129 /* VSI state flags */ 130 enum i40e_vsi_state { 131 __I40E_VSI_DOWN, 132 __I40E_VSI_NEEDS_RESTART, 133 __I40E_VSI_SYNCING_FILTERS, 134 __I40E_VSI_OVERFLOW_PROMISC, 135 __I40E_VSI_REINIT_REQUESTED, 136 __I40E_VSI_DOWN_REQUESTED, 137 __I40E_VSI_RELEASING, 138 /* This must be last as it determines the size of the BITMAP */ 139 __I40E_VSI_STATE_SIZE__, 140 }; 141 142 enum i40e_pf_flags { 143 I40E_FLAG_MSI_ENA, 144 I40E_FLAG_MSIX_ENA, 145 I40E_FLAG_RSS_ENA, 146 I40E_FLAG_VMDQ_ENA, 147 I40E_FLAG_SRIOV_ENA, 148 I40E_FLAG_DCB_CAPABLE, 149 I40E_FLAG_DCB_ENA, 150 I40E_FLAG_FD_SB_ENA, 151 I40E_FLAG_FD_ATR_ENA, 152 I40E_FLAG_MFP_ENA, 153 I40E_FLAG_HW_ATR_EVICT_ENA, 154 I40E_FLAG_VEB_MODE_ENA, 155 I40E_FLAG_VEB_STATS_ENA, 156 I40E_FLAG_LINK_POLLING_ENA, 157 I40E_FLAG_TRUE_PROMISC_ENA, 158 I40E_FLAG_LEGACY_RX_ENA, 159 I40E_FLAG_PTP_ENA, 160 I40E_FLAG_IWARP_ENA, 161 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, 162 I40E_FLAG_SOURCE_PRUNING_DIS, 163 I40E_FLAG_TC_MQPRIO_ENA, 164 I40E_FLAG_FD_SB_INACTIVE, 165 I40E_FLAG_FD_SB_TO_CLOUD_FILTER, 166 I40E_FLAG_FW_LLDP_DIS, 167 I40E_FLAG_RS_FEC, 168 I40E_FLAG_BASE_R_FEC, 169 /* TOTAL_PORT_SHUTDOWN_ENA 170 * Allows to physically disable the link on the NIC's port. 171 * If enabled, (after link down request from the OS) 172 * no link, traffic or led activity is possible on that port. 173 * 174 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA is set, the 175 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA must be explicitly forced 176 * to true and cannot be disabled by system admin at that time. 177 * The functionalities are exclusive in terms of configuration, but 178 * they also have similar behavior (allowing to disable physical 179 * link of the port), with following differences: 180 * - LINK_DOWN_ON_CLOSE_ENA is configurable at host OS run-time and 181 * is supported by whole family of 7xx Intel Ethernet Controllers 182 * - TOTAL_PORT_SHUTDOWN_ENA may be enabled only before OS loads 183 * (in BIOS) only if motherboard's BIOS and NIC's FW has support of it 184 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought 185 * down by sending phy_type=0 to NIC's FW 186 * - when TOTAL_PORT_SHUTDOWN_ENA is used, phy_type is not altered, 187 * instead the link is being brought down by clearing 188 * bit (I40E_AQ_PHY_ENABLE_LINK) in abilities field of 189 * i40e_aq_set_phy_config structure 190 */ 191 I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, 192 I40E_FLAG_VF_VLAN_PRUNING_ENA, 193 I40E_PF_FLAGS_NBITS, /* must be last */ 194 }; 195 196 enum i40e_interrupt_policy { 197 I40E_INTERRUPT_BEST_CASE, 198 I40E_INTERRUPT_MEDIUM, 199 I40E_INTERRUPT_LOWEST 200 }; 201 202 struct i40e_lump_tracking { 203 u16 num_entries; 204 u16 list[]; 205 #define I40E_PILE_VALID_BIT 0x8000 206 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 207 }; 208 209 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 210 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 211 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 212 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 213 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 214 215 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 216 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 217 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 218 219 enum i40e_fd_stat_idx { 220 I40E_FD_STAT_ATR, 221 I40E_FD_STAT_SB, 222 I40E_FD_STAT_ATR_TUNNEL, 223 I40E_FD_STAT_PF_COUNT 224 }; 225 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 226 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 227 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 228 #define I40E_FD_SB_STAT_IDX(pf_id) \ 229 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 230 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 231 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 232 233 /* The following structure contains the data parsed from the user-defined 234 * field of the ethtool_rx_flow_spec structure. 235 */ 236 struct i40e_rx_flow_userdef { 237 bool flex_filter; 238 u16 flex_word; 239 u16 flex_offset; 240 }; 241 242 struct i40e_fdir_filter { 243 struct hlist_node fdir_node; 244 /* filter ipnut set */ 245 u8 flow_type; 246 u8 ipl4_proto; 247 /* TX packet view of src and dst */ 248 __be32 dst_ip; 249 __be32 src_ip; 250 __be32 dst_ip6[4]; 251 __be32 src_ip6[4]; 252 __be16 src_port; 253 __be16 dst_port; 254 __be32 sctp_v_tag; 255 256 __be16 vlan_etype; 257 __be16 vlan_tag; 258 /* Flexible data to match within the packet payload */ 259 __be16 flex_word; 260 u16 flex_offset; 261 bool flex_filter; 262 263 /* filter control */ 264 u16 q_index; 265 u8 flex_off; 266 u8 pctype; 267 u16 dest_vsi; 268 u8 dest_ctl; 269 u8 fd_status; 270 u16 cnt_index; 271 u32 fd_id; 272 }; 273 274 #define I40E_CLOUD_FIELD_OMAC BIT(0) 275 #define I40E_CLOUD_FIELD_IMAC BIT(1) 276 #define I40E_CLOUD_FIELD_IVLAN BIT(2) 277 #define I40E_CLOUD_FIELD_TEN_ID BIT(3) 278 #define I40E_CLOUD_FIELD_IIP BIT(4) 279 280 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 281 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 282 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 283 I40E_CLOUD_FIELD_IVLAN) 284 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 285 I40E_CLOUD_FIELD_TEN_ID) 286 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 287 I40E_CLOUD_FIELD_IMAC | \ 288 I40E_CLOUD_FIELD_TEN_ID) 289 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 290 I40E_CLOUD_FIELD_IVLAN | \ 291 I40E_CLOUD_FIELD_TEN_ID) 292 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 293 294 struct i40e_cloud_filter { 295 struct hlist_node cloud_node; 296 unsigned long cookie; 297 /* cloud filter input set follows */ 298 u8 dst_mac[ETH_ALEN]; 299 u8 src_mac[ETH_ALEN]; 300 __be16 vlan_id; 301 u16 seid; /* filter control */ 302 __be16 dst_port; 303 __be16 src_port; 304 u32 tenant_id; 305 union { 306 struct { 307 struct in_addr dst_ip; 308 struct in_addr src_ip; 309 } v4; 310 struct { 311 struct in6_addr dst_ip6; 312 struct in6_addr src_ip6; 313 } v6; 314 } ip; 315 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 316 #define src_ipv6 ip.v6.src_ip6.s6_addr32 317 #define dst_ipv4 ip.v4.dst_ip.s_addr 318 #define src_ipv4 ip.v4.src_ip.s_addr 319 u16 n_proto; /* Ethernet Protocol */ 320 u8 ip_proto; /* IPPROTO value */ 321 u8 flags; 322 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 323 u8 tunnel_type; 324 }; 325 326 #define I40E_DCB_PRIO_TYPE_STRICT 0 327 #define I40E_DCB_PRIO_TYPE_ETS 1 328 #define I40E_DCB_STRICT_PRIO_CREDITS 127 329 /* DCB per TC information data structure */ 330 struct i40e_tc_info { 331 u16 qoffset; /* Queue offset from base queue */ 332 u16 qcount; /* Total Queues */ 333 u8 netdev_tc; /* Netdev TC index if netdev associated */ 334 }; 335 336 /* TC configuration data structure */ 337 struct i40e_tc_configuration { 338 u8 numtc; /* Total number of enabled TCs */ 339 u8 enabled_tc; /* TC map */ 340 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 341 }; 342 343 #define I40E_UDP_PORT_INDEX_UNUSED 255 344 struct i40e_udp_port_config { 345 /* AdminQ command interface expects port number in Host byte order */ 346 u16 port; 347 u8 type; 348 u8 filter_index; 349 }; 350 351 /* macros related to FLX_PIT */ 352 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 353 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 354 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 355 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 356 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 357 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 358 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 359 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 360 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 361 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 362 I40E_FLEX_SET_FSIZE(fsize) | \ 363 I40E_FLEX_SET_SRC_WORD(src)) 364 365 366 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 367 368 /* macros related to GLQF_ORT */ 369 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 370 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 371 I40E_GLQF_ORT_PIT_INDX_MASK) 372 373 #define I40E_ORT_SET_COUNT(count) (((count) << \ 374 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 375 I40E_GLQF_ORT_FIELD_CNT_MASK) 376 377 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 378 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 379 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 380 381 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 382 I40E_ORT_SET_COUNT(count) | \ 383 I40E_ORT_SET_PAYLOAD(payload)) 384 385 #define I40E_L3_GLQF_ORT_IDX 34 386 #define I40E_L4_GLQF_ORT_IDX 35 387 388 /* Flex PIT register index */ 389 #define I40E_FLEX_PIT_IDX_START_L3 3 390 #define I40E_FLEX_PIT_IDX_START_L4 6 391 392 #define I40E_FLEX_PIT_TABLE_SIZE 3 393 394 #define I40E_FLEX_DEST_UNUSED 63 395 396 #define I40E_FLEX_INDEX_ENTRIES 8 397 398 /* Flex MASK to disable all flexible entries */ 399 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 400 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 401 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 402 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 403 404 #define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \ 405 (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \ 406 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \ 407 ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \ 408 ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \ 409 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)) 410 411 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \ 412 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \ 413 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \ 414 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \ 415 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \ 416 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)) 417 418 struct i40e_flex_pit { 419 struct list_head list; 420 u16 src_offset; 421 u8 pit_index; 422 }; 423 424 struct i40e_fwd_adapter { 425 struct net_device *netdev; 426 int bit_no; 427 }; 428 429 struct i40e_channel { 430 struct list_head list; 431 bool initialized; 432 u8 type; 433 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 434 u16 stat_counter_idx; 435 u16 base_queue; 436 u16 num_queue_pairs; /* Requested by user */ 437 u16 seid; 438 439 u8 enabled_tc; 440 struct i40e_aqc_vsi_properties_data info; 441 442 u64 max_tx_rate; 443 struct i40e_fwd_adapter *fwd; 444 445 /* track this channel belongs to which VSI */ 446 struct i40e_vsi *parent_vsi; 447 }; 448 449 struct i40e_ptp_pins_settings; 450 451 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch) 452 { 453 return !!ch->fwd; 454 } 455 456 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch) 457 { 458 if (i40e_is_channel_macvlan(ch)) 459 return ch->fwd->netdev->dev_addr; 460 else 461 return NULL; 462 } 463 464 /* struct that defines the Ethernet device */ 465 struct i40e_pf { 466 struct pci_dev *pdev; 467 struct devlink_port devlink_port; 468 struct i40e_hw hw; 469 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 470 struct msix_entry *msix_entries; 471 bool fc_autoneg_status; 472 473 u16 eeprom_version; 474 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 475 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 476 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 477 u16 num_req_vfs; /* num VFs requested for this PF */ 478 u16 num_vf_qps; /* num queue pairs per VF */ 479 u16 num_lan_qps; /* num lan queues this PF has set up */ 480 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 481 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 482 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 483 int iwarp_base_vector; 484 int queues_left; /* queues left unclaimed */ 485 u16 alloc_rss_size; /* allocated RSS queues */ 486 u16 rss_size_max; /* HW defined max RSS queues */ 487 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 488 u16 num_alloc_vsi; /* num VSIs this driver supports */ 489 u8 atr_sample_rate; 490 bool wol_en; 491 492 struct hlist_head fdir_filter_list; 493 u16 fdir_pf_active_filters; 494 unsigned long fd_flush_timestamp; 495 u32 fd_flush_cnt; 496 u32 fd_add_err; 497 u32 fd_atr_cnt; 498 499 /* Book-keeping of side-band filter count per flow-type. 500 * This is used to detect and handle input set changes for 501 * respective flow-type. 502 */ 503 u16 fd_tcp4_filter_cnt; 504 u16 fd_udp4_filter_cnt; 505 u16 fd_sctp4_filter_cnt; 506 u16 fd_ip4_filter_cnt; 507 508 u16 fd_tcp6_filter_cnt; 509 u16 fd_udp6_filter_cnt; 510 u16 fd_sctp6_filter_cnt; 511 u16 fd_ip6_filter_cnt; 512 513 /* Flexible filter table values that need to be programmed into 514 * hardware, which expects L3 and L4 to be programmed separately. We 515 * need to ensure that the values are in ascended order and don't have 516 * duplicates, so we track each L3 and L4 values in separate lists. 517 */ 518 struct list_head l3_flex_pit_list; 519 struct list_head l4_flex_pit_list; 520 521 struct udp_tunnel_nic_shared udp_tunnel_shared; 522 struct udp_tunnel_nic_info udp_tunnel_nic; 523 524 struct hlist_head cloud_filter_list; 525 u16 num_cloud_filters; 526 527 enum i40e_interrupt_policy int_policy; 528 u16 rx_itr_default; 529 u16 tx_itr_default; 530 u32 msg_enable; 531 char int_name[I40E_INT_NAME_STR_LEN]; 532 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 533 unsigned long service_timer_period; 534 unsigned long service_timer_previous; 535 struct timer_list service_timer; 536 struct work_struct service_task; 537 538 DECLARE_BITMAP(flags, I40E_PF_FLAGS_NBITS); 539 struct i40e_client_instance *cinst; 540 bool stat_offsets_loaded; 541 struct i40e_hw_port_stats stats; 542 struct i40e_hw_port_stats stats_offsets; 543 u32 tx_timeout_count; 544 u32 tx_timeout_recovery_level; 545 unsigned long tx_timeout_last_recovery; 546 u32 tx_sluggish_count; 547 u32 hw_csum_rx_error; 548 u32 led_status; 549 u16 corer_count; /* Core reset count */ 550 u16 globr_count; /* Global reset count */ 551 u16 empr_count; /* EMP reset count */ 552 u16 pfr_count; /* PF reset count */ 553 u16 sw_int_count; /* SW interrupt count */ 554 555 struct mutex switch_mutex; 556 u16 lan_vsi; /* our default LAN VSI */ 557 u16 lan_veb; /* initial relay, if exists */ 558 #define I40E_NO_VEB 0xffff 559 #define I40E_NO_VSI 0xffff 560 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 561 struct i40e_vsi **vsi; 562 struct i40e_veb *veb[I40E_MAX_VEB]; 563 564 struct i40e_lump_tracking *qp_pile; 565 struct i40e_lump_tracking *irq_pile; 566 567 /* switch config info */ 568 u16 pf_seid; 569 u16 main_vsi_seid; 570 u16 mac_seid; 571 struct kobject *switch_kobj; 572 #ifdef CONFIG_DEBUG_FS 573 struct dentry *i40e_dbg_pf; 574 #endif /* CONFIG_DEBUG_FS */ 575 bool cur_promisc; 576 577 u16 instance; /* A unique number per i40e_pf instance in the system */ 578 579 /* sr-iov config info */ 580 struct i40e_vf *vf; 581 int num_alloc_vfs; /* actual number of VFs allocated */ 582 u32 vf_aq_requests; 583 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 584 585 /* DCBx/DCBNL capability for PF that indicates 586 * whether DCBx is managed by firmware or host 587 * based agent (LLDPAD). Also, indicates what 588 * flavor of DCBx protocol (IEEE/CEE) is supported 589 * by the device. For now we're supporting IEEE 590 * mode only. 591 */ 592 u16 dcbx_cap; 593 594 struct i40e_filter_control_settings filter_settings; 595 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */ 596 struct i40e_dcbx_config tmp_cfg; 597 598 /* GPIO defines used by PTP */ 599 #define I40E_SDP3_2 18 600 #define I40E_SDP3_3 19 601 #define I40E_GPIO_4 20 602 #define I40E_LED2_0 26 603 #define I40E_LED2_1 27 604 #define I40E_LED3_0 28 605 #define I40E_LED3_1 29 606 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \ 607 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 608 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \ 609 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 610 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \ 611 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 612 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \ 613 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 614 #define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2) 615 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \ 616 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 617 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \ 618 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) 619 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \ 620 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) 621 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \ 622 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) 623 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \ 624 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 625 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \ 626 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 627 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \ 628 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) 629 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \ 630 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 631 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \ 632 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 633 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 634 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 635 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \ 636 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 637 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 638 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 639 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \ 640 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 641 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 642 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 643 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 644 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \ 645 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 646 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 647 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 648 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 649 #define I40E_GLGEN_GPIO_CTL_LED_INIT \ 650 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \ 651 I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 652 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \ 653 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 654 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \ 655 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN) 656 #define I40E_PRTTSYN_AUX_1_INSTNT \ 657 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) 658 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \ 659 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) 660 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) 661 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \ 662 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD) 663 #define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */ 664 #define I40E_PTP_2_SEC_DELAY 2 665 666 struct ptp_clock *ptp_clock; 667 struct ptp_clock_info ptp_caps; 668 struct sk_buff *ptp_tx_skb; 669 unsigned long ptp_tx_start; 670 struct hwtstamp_config tstamp_config; 671 struct timespec64 ptp_prev_hw_time; 672 struct work_struct ptp_pps_work; 673 struct work_struct ptp_extts0_work; 674 struct work_struct ptp_extts1_work; 675 ktime_t ptp_reset_start; 676 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 677 u32 ptp_adj_mult; 678 u32 tx_hwtstamp_timeouts; 679 u32 tx_hwtstamp_skipped; 680 u32 rx_hwtstamp_cleared; 681 u32 latch_event_flags; 682 u64 ptp_pps_start; 683 u32 pps_delay; 684 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 685 struct ptp_pin_desc ptp_pin[3]; 686 unsigned long latch_events[4]; 687 bool ptp_tx; 688 bool ptp_rx; 689 struct i40e_ptp_pins_settings *ptp_pins; 690 u16 rss_table_size; /* HW RSS table size */ 691 u32 max_bw; 692 u32 min_bw; 693 694 u32 ioremap_len; 695 u32 fd_inv; 696 u16 phy_led_val; 697 698 u16 override_q_count; 699 u16 last_sw_conf_flags; 700 u16 last_sw_conf_valid_flags; 701 /* List to keep previous DDP profiles to be rolled back in the future */ 702 struct list_head ddp_old_prof; 703 }; 704 705 /** 706 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 707 * @macaddr: the MAC Address as the base key 708 * 709 * Simply copies the address and returns it as a u64 for hashing 710 **/ 711 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 712 { 713 u64 key = 0; 714 715 ether_addr_copy((u8 *)&key, macaddr); 716 return key; 717 } 718 719 enum i40e_filter_state { 720 I40E_FILTER_INVALID = 0, /* Invalid state */ 721 I40E_FILTER_NEW, /* New, not sent to FW yet */ 722 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 723 I40E_FILTER_FAILED, /* Rejected by FW */ 724 I40E_FILTER_REMOVE, /* To be removed */ 725 /* There is no 'removed' state; the filter struct is freed */ 726 }; 727 struct i40e_mac_filter { 728 struct hlist_node hlist; 729 u8 macaddr[ETH_ALEN]; 730 #define I40E_VLAN_ANY -1 731 s16 vlan; 732 enum i40e_filter_state state; 733 }; 734 735 /* Wrapper structure to keep track of filters while we are preparing to send 736 * firmware commands. We cannot send firmware commands while holding a 737 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 738 * a separate structure, which will track the state change and update the real 739 * filter while under lock. We can't simply hold the filters in a separate 740 * list, as this opens a window for a race condition when adding new MAC 741 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 742 */ 743 struct i40e_new_mac_filter { 744 struct hlist_node hlist; 745 struct i40e_mac_filter *f; 746 747 /* Track future changes to state separately */ 748 enum i40e_filter_state state; 749 }; 750 751 struct i40e_veb { 752 struct i40e_pf *pf; 753 u16 idx; 754 u16 veb_idx; /* index of VEB parent */ 755 u16 seid; 756 u16 uplink_seid; 757 u16 stats_idx; /* index of VEB parent */ 758 u8 enabled_tc; 759 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 760 u16 flags; 761 u16 bw_limit; 762 u8 bw_max_quanta; 763 bool is_abs_credits; 764 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 765 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 766 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 767 struct kobject *kobj; 768 bool stat_offsets_loaded; 769 struct i40e_eth_stats stats; 770 struct i40e_eth_stats stats_offsets; 771 struct i40e_veb_tc_stats tc_stats; 772 struct i40e_veb_tc_stats tc_stats_offsets; 773 }; 774 775 /* struct that defines a VSI, associated with a dev */ 776 struct i40e_vsi { 777 struct net_device *netdev; 778 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 779 bool netdev_registered; 780 bool stat_offsets_loaded; 781 782 u32 current_netdev_flags; 783 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 784 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 785 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 786 unsigned long flags; 787 788 /* Per VSI lock to protect elements/hash (MAC filter) */ 789 spinlock_t mac_filter_hash_lock; 790 /* Fixed size hash table with 2^8 buckets for MAC filters */ 791 DECLARE_HASHTABLE(mac_filter_hash, 8); 792 bool has_vlan_filter; 793 794 /* VSI stats */ 795 struct rtnl_link_stats64 net_stats; 796 struct rtnl_link_stats64 net_stats_offsets; 797 struct i40e_eth_stats eth_stats; 798 struct i40e_eth_stats eth_stats_offsets; 799 u64 tx_restart; 800 u64 tx_busy; 801 u64 tx_linearize; 802 u64 tx_force_wb; 803 u64 tx_stopped; 804 u64 rx_buf_failed; 805 u64 rx_page_failed; 806 u64 rx_page_reuse; 807 u64 rx_page_alloc; 808 u64 rx_page_waive; 809 u64 rx_page_busy; 810 811 /* These are containers of ring pointers, allocated at run-time */ 812 struct i40e_ring **rx_rings; 813 struct i40e_ring **tx_rings; 814 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 815 816 u32 active_filters; 817 u32 promisc_threshold; 818 819 u16 work_limit; 820 u16 int_rate_limit; /* value in usecs */ 821 822 u16 rss_table_size; /* HW RSS table size */ 823 u16 rss_size; /* Allocated RSS queues */ 824 u8 *rss_hkey_user; /* User configured hash keys */ 825 u8 *rss_lut_user; /* User configured lookup table entries */ 826 827 828 u16 max_frame; 829 u16 rx_buf_len; 830 831 struct bpf_prog *xdp_prog; 832 833 /* List of q_vectors allocated to this VSI */ 834 struct i40e_q_vector **q_vectors; 835 int num_q_vectors; 836 int base_vector; 837 bool irqs_ready; 838 839 u16 seid; /* HW index of this VSI (absolute index) */ 840 u16 id; /* VSI number */ 841 u16 uplink_seid; 842 843 u16 base_queue; /* vsi's first queue in hw array */ 844 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 845 u16 req_queue_pairs; /* User requested queue pairs */ 846 u16 num_queue_pairs; /* Used tx and rx pairs */ 847 u16 num_tx_desc; 848 u16 num_rx_desc; 849 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 850 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 851 852 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 853 struct i40e_tc_configuration tc_config; 854 struct i40e_aqc_vsi_properties_data info; 855 856 /* VSI BW limit (absolute across all TCs) */ 857 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 858 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 859 860 /* Relative TC credits across VSIs */ 861 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 862 /* TC BW limit credits within VSI */ 863 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 864 /* TC BW limit max quanta within VSI */ 865 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 866 867 struct i40e_pf *back; /* Backreference to associated PF */ 868 u16 idx; /* index in pf->vsi[] */ 869 u16 veb_idx; /* index of VEB parent */ 870 struct kobject *kobj; /* sysfs object */ 871 bool current_isup; /* Sync 'link up' logging */ 872 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 873 874 /* channel specific fields */ 875 u16 cnt_q_avail; /* num of queues available for channel usage */ 876 u16 orig_rss_size; 877 u16 current_rss_size; 878 bool reconfig_rss; 879 880 u16 next_base_queue; /* next queue to be used for channel setup */ 881 882 struct list_head ch_list; 883 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 884 885 /* macvlan fields */ 886 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */ 887 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */ 888 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS); 889 struct list_head macvlan_list; 890 int macvlan_cnt; 891 892 void *priv; /* client driver data reference. */ 893 894 /* VSI specific handlers */ 895 irqreturn_t (*irq_handler)(int irq, void *data); 896 897 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 898 } ____cacheline_internodealigned_in_smp; 899 900 struct i40e_netdev_priv { 901 struct i40e_vsi *vsi; 902 }; 903 904 extern struct ida i40e_client_ida; 905 906 /* struct that defines an interrupt vector */ 907 struct i40e_q_vector { 908 struct i40e_vsi *vsi; 909 910 u16 v_idx; /* index in the vsi->q_vector array. */ 911 u16 reg_idx; /* register index of the interrupt */ 912 913 struct napi_struct napi; 914 915 struct i40e_ring_container rx; 916 struct i40e_ring_container tx; 917 918 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 919 u8 num_ringpairs; /* total number of ring pairs in vector */ 920 921 cpumask_t affinity_mask; 922 struct irq_affinity_notify affinity_notify; 923 924 struct rcu_head rcu; /* to avoid race with update stats on free */ 925 char name[I40E_INT_NAME_STR_LEN]; 926 bool arm_wb_state; 927 int irq_num; /* IRQ assigned to this q_vector */ 928 } ____cacheline_internodealigned_in_smp; 929 930 /* lan device */ 931 struct i40e_device { 932 struct list_head list; 933 struct i40e_pf *pf; 934 }; 935 936 /** 937 * i40e_info_nvm_ver - format the NVM version string 938 * @hw: ptr to the hardware info 939 * @buf: string buffer to store 940 * @len: buffer size 941 * 942 * Formats NVM version string as: 943 * <gen>.<snap>.<release> when eetrackid == I40E_OEM_EETRACK_ID 944 * <nvm_major>.<nvm_minor> otherwise 945 **/ 946 static inline void i40e_info_nvm_ver(struct i40e_hw *hw, char *buf, size_t len) 947 { 948 struct i40e_nvm_info *nvm = &hw->nvm; 949 950 if (nvm->eetrack == I40E_OEM_EETRACK_ID) { 951 u32 full_ver = nvm->oem_ver; 952 u8 gen, snap; 953 u16 release; 954 955 gen = FIELD_GET(I40E_OEM_GEN_MASK, full_ver); 956 snap = FIELD_GET(I40E_OEM_SNAP_MASK, full_ver); 957 release = FIELD_GET(I40E_OEM_RELEASE_MASK, full_ver); 958 snprintf(buf, len, "%x.%x.%x", gen, snap, release); 959 } else { 960 u8 major, minor; 961 962 major = FIELD_GET(I40E_NVM_VERSION_HI_MASK, nvm->version); 963 minor = FIELD_GET(I40E_NVM_VERSION_LO_MASK, nvm->version); 964 snprintf(buf, len, "%x.%02x", major, minor); 965 } 966 } 967 968 /** 969 * i40e_info_eetrack - format the EETrackID string 970 * @hw: ptr to the hardware info 971 * @buf: string buffer to store 972 * @len: buffer size 973 * 974 * Returns hexadecimally formated EETrackID if it is 975 * different from I40E_OEM_EETRACK_ID or empty string. 976 **/ 977 static inline void i40e_info_eetrack(struct i40e_hw *hw, char *buf, size_t len) 978 { 979 struct i40e_nvm_info *nvm = &hw->nvm; 980 981 buf[0] = '\0'; 982 if (nvm->eetrack != I40E_OEM_EETRACK_ID) 983 snprintf(buf, len, "0x%08x", nvm->eetrack); 984 } 985 986 /** 987 * i40e_info_civd_ver - format the NVM version strings 988 * @hw: ptr to the hardware info 989 * @buf: string buffer to store 990 * @len: buffer size 991 * 992 * Returns formated combo image version if adapter's EETrackID is 993 * different from I40E_OEM_EETRACK_ID or empty string. 994 **/ 995 static inline void i40e_info_civd_ver(struct i40e_hw *hw, char *buf, size_t len) 996 { 997 struct i40e_nvm_info *nvm = &hw->nvm; 998 999 buf[0] = '\0'; 1000 if (nvm->eetrack != I40E_OEM_EETRACK_ID) { 1001 u32 full_ver = nvm->oem_ver; 1002 u8 major, minor; 1003 u16 build; 1004 1005 major = FIELD_GET(I40E_OEM_VER_MASK, full_ver); 1006 build = FIELD_GET(I40E_OEM_VER_BUILD_MASK, full_ver); 1007 minor = FIELD_GET(I40E_OEM_VER_PATCH_MASK, full_ver); 1008 snprintf(buf, len, "%d.%d.%d", major, build, minor); 1009 } 1010 } 1011 1012 /** 1013 * i40e_nvm_version_str - format the NVM version strings 1014 * @hw: ptr to the hardware info 1015 * @buf: string buffer to store 1016 * @len: buffer size 1017 **/ 1018 static inline char *i40e_nvm_version_str(struct i40e_hw *hw, char *buf, 1019 size_t len) 1020 { 1021 char ver[16] = " "; 1022 1023 /* Get NVM version */ 1024 i40e_info_nvm_ver(hw, buf, len); 1025 1026 /* Append EETrackID if provided */ 1027 i40e_info_eetrack(hw, &ver[1], sizeof(ver) - 1); 1028 if (strlen(ver) > 1) 1029 strlcat(buf, ver, len); 1030 1031 /* Append combo image version if provided */ 1032 i40e_info_civd_ver(hw, &ver[1], sizeof(ver) - 1); 1033 if (strlen(ver) > 1) 1034 strlcat(buf, ver, len); 1035 1036 return buf; 1037 } 1038 1039 /** 1040 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 1041 * @netdev: the corresponding netdev 1042 * 1043 * Return the PF struct for the given netdev 1044 **/ 1045 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 1046 { 1047 struct i40e_netdev_priv *np = netdev_priv(netdev); 1048 struct i40e_vsi *vsi = np->vsi; 1049 1050 return vsi->back; 1051 } 1052 1053 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 1054 irqreturn_t (*irq_handler)(int, void *)) 1055 { 1056 vsi->irq_handler = irq_handler; 1057 } 1058 1059 /** 1060 * i40e_get_fd_cnt_all - get the total FD filter space available 1061 * @pf: pointer to the PF struct 1062 **/ 1063 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 1064 { 1065 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 1066 } 1067 1068 /** 1069 * i40e_read_fd_input_set - reads value of flow director input set register 1070 * @pf: pointer to the PF struct 1071 * @addr: register addr 1072 * 1073 * This function reads value of flow director input set register 1074 * specified by 'addr' (which is specific to flow-type) 1075 **/ 1076 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 1077 { 1078 u64 val; 1079 1080 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 1081 val <<= 32; 1082 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 1083 1084 return val; 1085 } 1086 1087 /** 1088 * i40e_write_fd_input_set - writes value into flow director input set register 1089 * @pf: pointer to the PF struct 1090 * @addr: register addr 1091 * @val: value to be written 1092 * 1093 * This function writes specified value to the register specified by 'addr'. 1094 * This register is input set register based on flow-type. 1095 **/ 1096 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 1097 u16 addr, u64 val) 1098 { 1099 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 1100 (u32)(val >> 32)); 1101 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 1102 (u32)(val & 0xFFFFFFFFULL)); 1103 } 1104 1105 /** 1106 * i40e_get_pf_count - get PCI PF count. 1107 * @hw: pointer to a hw. 1108 * 1109 * Reports the function number of the highest PCI physical 1110 * function plus 1 as it is loaded from the NVM. 1111 * 1112 * Return: PCI PF count. 1113 **/ 1114 static inline u32 i40e_get_pf_count(struct i40e_hw *hw) 1115 { 1116 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK, 1117 rd32(hw, I40E_GLGEN_PCIFCNCNT)); 1118 } 1119 1120 /* needed by i40e_ethtool.c */ 1121 int i40e_up(struct i40e_vsi *vsi); 1122 void i40e_down(struct i40e_vsi *vsi); 1123 extern const char i40e_driver_name[]; 1124 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 1125 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 1126 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1127 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1128 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 1129 u16 rss_table_size, u16 rss_size); 1130 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 1131 /** 1132 * i40e_find_vsi_by_type - Find and return Flow Director VSI 1133 * @pf: PF to search for VSI 1134 * @type: Value indicating type of VSI we are looking for 1135 **/ 1136 static inline struct i40e_vsi * 1137 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 1138 { 1139 int i; 1140 1141 for (i = 0; i < pf->num_alloc_vsi; i++) { 1142 struct i40e_vsi *vsi = pf->vsi[i]; 1143 1144 if (vsi && vsi->type == type) 1145 return vsi; 1146 } 1147 1148 return NULL; 1149 } 1150 void i40e_update_stats(struct i40e_vsi *vsi); 1151 void i40e_update_veb_stats(struct i40e_veb *veb); 1152 void i40e_update_eth_stats(struct i40e_vsi *vsi); 1153 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 1154 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1155 bool printconfig); 1156 1157 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1158 struct i40e_fdir_filter *input, bool add); 1159 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1160 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1161 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1162 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1163 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1164 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1165 void i40e_set_ethtool_ops(struct net_device *netdev); 1166 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1167 const u8 *macaddr, s16 vlan); 1168 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1169 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1170 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1171 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1172 u16 uplink, u32 param1); 1173 int i40e_vsi_release(struct i40e_vsi *vsi); 1174 void i40e_service_event_schedule(struct i40e_pf *pf); 1175 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1176 u8 *msg, u16 len); 1177 1178 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1179 bool enable); 1180 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1181 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1182 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1183 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1184 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1185 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1186 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1187 u16 downlink_seid, u8 enabled_tc); 1188 void i40e_veb_release(struct i40e_veb *veb); 1189 1190 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1191 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1192 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1193 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1194 void i40e_pf_reset_stats(struct i40e_pf *pf); 1195 #ifdef CONFIG_DEBUG_FS 1196 void i40e_dbg_pf_init(struct i40e_pf *pf); 1197 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1198 void i40e_dbg_init(void); 1199 void i40e_dbg_exit(void); 1200 #else 1201 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1202 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1203 static inline void i40e_dbg_init(void) {} 1204 static inline void i40e_dbg_exit(void) {} 1205 #endif /* CONFIG_DEBUG_FS*/ 1206 /* needed by client drivers */ 1207 int i40e_lan_add_device(struct i40e_pf *pf); 1208 int i40e_lan_del_device(struct i40e_pf *pf); 1209 void i40e_client_subtask(struct i40e_pf *pf); 1210 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1211 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1212 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1213 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1214 void i40e_client_update_msix_info(struct i40e_pf *pf); 1215 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1216 /** 1217 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1218 * @vsi: pointer to a vsi 1219 * @vector: enable a particular Hw Interrupt vector, without base_vector 1220 **/ 1221 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1222 { 1223 struct i40e_pf *pf = vsi->back; 1224 struct i40e_hw *hw = &pf->hw; 1225 u32 val; 1226 1227 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1228 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1229 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1230 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1231 /* skip the flush */ 1232 } 1233 1234 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1235 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1236 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1237 int i40e_open(struct net_device *netdev); 1238 int i40e_close(struct net_device *netdev); 1239 int i40e_vsi_open(struct i40e_vsi *vsi); 1240 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1241 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1242 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1243 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1244 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1245 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1246 const u8 *macaddr); 1247 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1248 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1249 int i40e_count_filters(struct i40e_vsi *vsi); 1250 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1251 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1252 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf) 1253 { 1254 return test_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags); 1255 } 1256 1257 #ifdef CONFIG_I40E_DCB 1258 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1259 struct i40e_dcbx_config *old_cfg, 1260 struct i40e_dcbx_config *new_cfg); 1261 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1262 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1263 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1264 struct i40e_dcbx_config *old_cfg, 1265 struct i40e_dcbx_config *new_cfg); 1266 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg); 1267 int i40e_dcb_sw_default_config(struct i40e_pf *pf); 1268 #endif /* CONFIG_I40E_DCB */ 1269 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1270 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1271 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1272 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1273 void i40e_ptp_set_increment(struct i40e_pf *pf); 1274 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1275 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1276 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1277 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1278 void i40e_ptp_init(struct i40e_pf *pf); 1279 void i40e_ptp_stop(struct i40e_pf *pf); 1280 int i40e_ptp_alloc_pins(struct i40e_pf *pf); 1281 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset); 1282 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1283 int i40e_get_partition_bw_setting(struct i40e_pf *pf); 1284 int i40e_set_partition_bw_setting(struct i40e_pf *pf); 1285 int i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1286 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1287 1288 void i40e_set_fec_in_flags(u8 fec_cfg, unsigned long *flags); 1289 1290 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1291 { 1292 return !!READ_ONCE(vsi->xdp_prog); 1293 } 1294 1295 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1296 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1297 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1298 struct i40e_cloud_filter *filter, 1299 bool add); 1300 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1301 struct i40e_cloud_filter *filter, 1302 bool add); 1303 1304 /** 1305 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF 1306 * @pf: pointer to a pf. 1307 * 1308 * Check and return state of flag I40E_FLAG_TC_MQPRIO. 1309 * 1310 * Return: true/false if I40E_FLAG_TC_MQPRIO is set or not 1311 **/ 1312 static inline bool i40e_is_tc_mqprio_enabled(struct i40e_pf *pf) 1313 { 1314 return test_bit(I40E_FLAG_TC_MQPRIO_ENA, pf->flags); 1315 } 1316 1317 /** 1318 * i40e_hw_to_pf - get pf pointer from the hardware structure 1319 * @hw: pointer to the device HW structure 1320 **/ 1321 static inline struct i40e_pf *i40e_hw_to_pf(struct i40e_hw *hw) 1322 { 1323 return container_of(hw, struct i40e_pf, hw); 1324 } 1325 1326 struct device *i40e_hw_to_dev(struct i40e_hw *hw); 1327 1328 #endif /* _I40E_H_ */ 1329