1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <linux/pci.h> 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/types.h> 10 #include <linux/avf/virtchnl.h> 11 #include <linux/net/intel/i40e_client.h> 12 #include <net/devlink.h> 13 #include <net/pkt_cls.h> 14 #include <net/udp_tunnel.h> 15 #include "i40e_dcb.h" 16 #include "i40e_debug.h" 17 #include "i40e_devlink.h" 18 #include "i40e_io.h" 19 #include "i40e_prototype.h" 20 #include "i40e_register.h" 21 #include "i40e_txrx.h" 22 23 /* Useful i40e defaults */ 24 #define I40E_MAX_VEB 16 25 26 #define I40E_MAX_NUM_DESCRIPTORS 4096 27 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 28 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 29 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 30 #define I40E_MIN_NUM_DESCRIPTORS 64 31 #define I40E_MIN_MSIX 2 32 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 33 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 34 /* max 16 qps */ 35 #define i40e_default_queues_per_vmdq(pf) \ 36 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 37 #define I40E_DEFAULT_QUEUES_PER_VF 4 38 #define I40E_MAX_VF_QUEUES 16 39 #define i40e_pf_get_max_q_per_tc(pf) \ 40 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 41 #define I40E_FDIR_RING_COUNT 32 42 #define I40E_MAX_AQ_BUF_SIZE 4096 43 #define I40E_AQ_LEN 256 44 #define I40E_MIN_ARQ_LEN 1 45 #define I40E_MIN_ASQ_LEN 2 46 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 47 #define I40E_MAX_USER_PRIORITY 8 48 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 49 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 50 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 51 52 #define I40E_NVM_VERSION_LO_SHIFT 0 53 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 54 #define I40E_NVM_VERSION_HI_SHIFT 12 55 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 56 #define I40E_OEM_VER_BUILD_MASK 0xffff 57 #define I40E_OEM_VER_PATCH_MASK 0xff 58 #define I40E_OEM_VER_BUILD_SHIFT 8 59 #define I40E_OEM_VER_SHIFT 24 60 #define I40E_PHY_DEBUG_ALL \ 61 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 62 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 63 64 #define I40E_OEM_EETRACK_ID 0xffffffff 65 #define I40E_OEM_GEN_SHIFT 24 66 #define I40E_OEM_SNAP_MASK 0x00ff0000 67 #define I40E_OEM_SNAP_SHIFT 16 68 #define I40E_OEM_RELEASE_MASK 0x0000ffff 69 70 #define I40E_RX_DESC(R, i) \ 71 (&(((union i40e_rx_desc *)((R)->desc))[i])) 72 #define I40E_TX_DESC(R, i) \ 73 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 74 #define I40E_TX_CTXTDESC(R, i) \ 75 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 76 #define I40E_TX_FDIRDESC(R, i) \ 77 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 78 79 /* BW rate limiting */ 80 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 81 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 82 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 83 84 /* driver state flags */ 85 enum i40e_state_t { 86 __I40E_TESTING, 87 __I40E_CONFIG_BUSY, 88 __I40E_CONFIG_DONE, 89 __I40E_DOWN, 90 __I40E_SERVICE_SCHED, 91 __I40E_ADMINQ_EVENT_PENDING, 92 __I40E_MDD_EVENT_PENDING, 93 __I40E_VFLR_EVENT_PENDING, 94 __I40E_RESET_RECOVERY_PENDING, 95 __I40E_TIMEOUT_RECOVERY_PENDING, 96 __I40E_MISC_IRQ_REQUESTED, 97 __I40E_RESET_INTR_RECEIVED, 98 __I40E_REINIT_REQUESTED, 99 __I40E_PF_RESET_REQUESTED, 100 __I40E_PF_RESET_AND_REBUILD_REQUESTED, 101 __I40E_CORE_RESET_REQUESTED, 102 __I40E_GLOBAL_RESET_REQUESTED, 103 __I40E_EMP_RESET_INTR_RECEIVED, 104 __I40E_SUSPENDED, 105 __I40E_PTP_TX_IN_PROGRESS, 106 __I40E_BAD_EEPROM, 107 __I40E_DOWN_REQUESTED, 108 __I40E_FD_FLUSH_REQUESTED, 109 __I40E_FD_ATR_AUTO_DISABLED, 110 __I40E_FD_SB_AUTO_DISABLED, 111 __I40E_RESET_FAILED, 112 __I40E_PORT_SUSPENDED, 113 __I40E_VF_DISABLE, 114 __I40E_MACVLAN_SYNC_PENDING, 115 __I40E_TEMP_LINK_POLLING, 116 __I40E_CLIENT_SERVICE_REQUESTED, 117 __I40E_CLIENT_L2_CHANGE, 118 __I40E_CLIENT_RESET, 119 __I40E_VIRTCHNL_OP_PENDING, 120 __I40E_RECOVERY_MODE, 121 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */ 122 __I40E_IN_REMOVE, 123 __I40E_VFS_RELEASING, 124 /* This must be last as it determines the size of the BITMAP */ 125 __I40E_STATE_SIZE__, 126 }; 127 128 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 129 #define I40E_PF_RESET_AND_REBUILD_FLAG \ 130 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED) 131 132 /* VSI state flags */ 133 enum i40e_vsi_state_t { 134 __I40E_VSI_DOWN, 135 __I40E_VSI_NEEDS_RESTART, 136 __I40E_VSI_SYNCING_FILTERS, 137 __I40E_VSI_OVERFLOW_PROMISC, 138 __I40E_VSI_REINIT_REQUESTED, 139 __I40E_VSI_DOWN_REQUESTED, 140 __I40E_VSI_RELEASING, 141 /* This must be last as it determines the size of the BITMAP */ 142 __I40E_VSI_STATE_SIZE__, 143 }; 144 145 enum i40e_interrupt_policy { 146 I40E_INTERRUPT_BEST_CASE, 147 I40E_INTERRUPT_MEDIUM, 148 I40E_INTERRUPT_LOWEST 149 }; 150 151 struct i40e_lump_tracking { 152 u16 num_entries; 153 u16 list[]; 154 #define I40E_PILE_VALID_BIT 0x8000 155 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 156 }; 157 158 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 159 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 160 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 161 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 162 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 163 164 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 165 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 166 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 167 168 enum i40e_fd_stat_idx { 169 I40E_FD_STAT_ATR, 170 I40E_FD_STAT_SB, 171 I40E_FD_STAT_ATR_TUNNEL, 172 I40E_FD_STAT_PF_COUNT 173 }; 174 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 175 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 176 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 177 #define I40E_FD_SB_STAT_IDX(pf_id) \ 178 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 179 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 180 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 181 182 /* The following structure contains the data parsed from the user-defined 183 * field of the ethtool_rx_flow_spec structure. 184 */ 185 struct i40e_rx_flow_userdef { 186 bool flex_filter; 187 u16 flex_word; 188 u16 flex_offset; 189 }; 190 191 struct i40e_fdir_filter { 192 struct hlist_node fdir_node; 193 /* filter ipnut set */ 194 u8 flow_type; 195 u8 ipl4_proto; 196 /* TX packet view of src and dst */ 197 __be32 dst_ip; 198 __be32 src_ip; 199 __be32 dst_ip6[4]; 200 __be32 src_ip6[4]; 201 __be16 src_port; 202 __be16 dst_port; 203 __be32 sctp_v_tag; 204 205 __be16 vlan_etype; 206 __be16 vlan_tag; 207 /* Flexible data to match within the packet payload */ 208 __be16 flex_word; 209 u16 flex_offset; 210 bool flex_filter; 211 212 /* filter control */ 213 u16 q_index; 214 u8 flex_off; 215 u8 pctype; 216 u16 dest_vsi; 217 u8 dest_ctl; 218 u8 fd_status; 219 u16 cnt_index; 220 u32 fd_id; 221 }; 222 223 #define I40E_CLOUD_FIELD_OMAC BIT(0) 224 #define I40E_CLOUD_FIELD_IMAC BIT(1) 225 #define I40E_CLOUD_FIELD_IVLAN BIT(2) 226 #define I40E_CLOUD_FIELD_TEN_ID BIT(3) 227 #define I40E_CLOUD_FIELD_IIP BIT(4) 228 229 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 230 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 231 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 232 I40E_CLOUD_FIELD_IVLAN) 233 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 234 I40E_CLOUD_FIELD_TEN_ID) 235 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 236 I40E_CLOUD_FIELD_IMAC | \ 237 I40E_CLOUD_FIELD_TEN_ID) 238 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 239 I40E_CLOUD_FIELD_IVLAN | \ 240 I40E_CLOUD_FIELD_TEN_ID) 241 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 242 243 struct i40e_cloud_filter { 244 struct hlist_node cloud_node; 245 unsigned long cookie; 246 /* cloud filter input set follows */ 247 u8 dst_mac[ETH_ALEN]; 248 u8 src_mac[ETH_ALEN]; 249 __be16 vlan_id; 250 u16 seid; /* filter control */ 251 __be16 dst_port; 252 __be16 src_port; 253 u32 tenant_id; 254 union { 255 struct { 256 struct in_addr dst_ip; 257 struct in_addr src_ip; 258 } v4; 259 struct { 260 struct in6_addr dst_ip6; 261 struct in6_addr src_ip6; 262 } v6; 263 } ip; 264 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 265 #define src_ipv6 ip.v6.src_ip6.s6_addr32 266 #define dst_ipv4 ip.v4.dst_ip.s_addr 267 #define src_ipv4 ip.v4.src_ip.s_addr 268 u16 n_proto; /* Ethernet Protocol */ 269 u8 ip_proto; /* IPPROTO value */ 270 u8 flags; 271 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 272 u8 tunnel_type; 273 }; 274 275 #define I40E_DCB_PRIO_TYPE_STRICT 0 276 #define I40E_DCB_PRIO_TYPE_ETS 1 277 #define I40E_DCB_STRICT_PRIO_CREDITS 127 278 /* DCB per TC information data structure */ 279 struct i40e_tc_info { 280 u16 qoffset; /* Queue offset from base queue */ 281 u16 qcount; /* Total Queues */ 282 u8 netdev_tc; /* Netdev TC index if netdev associated */ 283 }; 284 285 /* TC configuration data structure */ 286 struct i40e_tc_configuration { 287 u8 numtc; /* Total number of enabled TCs */ 288 u8 enabled_tc; /* TC map */ 289 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 290 }; 291 292 #define I40E_UDP_PORT_INDEX_UNUSED 255 293 struct i40e_udp_port_config { 294 /* AdminQ command interface expects port number in Host byte order */ 295 u16 port; 296 u8 type; 297 u8 filter_index; 298 }; 299 300 /* macros related to FLX_PIT */ 301 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 302 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 303 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 304 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 305 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 306 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 307 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 308 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 309 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 310 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 311 I40E_FLEX_SET_FSIZE(fsize) | \ 312 I40E_FLEX_SET_SRC_WORD(src)) 313 314 315 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 316 317 /* macros related to GLQF_ORT */ 318 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 319 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 320 I40E_GLQF_ORT_PIT_INDX_MASK) 321 322 #define I40E_ORT_SET_COUNT(count) (((count) << \ 323 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 324 I40E_GLQF_ORT_FIELD_CNT_MASK) 325 326 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 327 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 328 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 329 330 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 331 I40E_ORT_SET_COUNT(count) | \ 332 I40E_ORT_SET_PAYLOAD(payload)) 333 334 #define I40E_L3_GLQF_ORT_IDX 34 335 #define I40E_L4_GLQF_ORT_IDX 35 336 337 /* Flex PIT register index */ 338 #define I40E_FLEX_PIT_IDX_START_L3 3 339 #define I40E_FLEX_PIT_IDX_START_L4 6 340 341 #define I40E_FLEX_PIT_TABLE_SIZE 3 342 343 #define I40E_FLEX_DEST_UNUSED 63 344 345 #define I40E_FLEX_INDEX_ENTRIES 8 346 347 /* Flex MASK to disable all flexible entries */ 348 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 349 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 350 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 351 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 352 353 #define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \ 354 (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \ 355 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \ 356 ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \ 357 ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \ 358 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)) 359 360 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \ 361 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \ 362 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \ 363 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \ 364 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \ 365 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)) 366 367 struct i40e_flex_pit { 368 struct list_head list; 369 u16 src_offset; 370 u8 pit_index; 371 }; 372 373 struct i40e_fwd_adapter { 374 struct net_device *netdev; 375 int bit_no; 376 }; 377 378 struct i40e_channel { 379 struct list_head list; 380 bool initialized; 381 u8 type; 382 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 383 u16 stat_counter_idx; 384 u16 base_queue; 385 u16 num_queue_pairs; /* Requested by user */ 386 u16 seid; 387 388 u8 enabled_tc; 389 struct i40e_aqc_vsi_properties_data info; 390 391 u64 max_tx_rate; 392 struct i40e_fwd_adapter *fwd; 393 394 /* track this channel belongs to which VSI */ 395 struct i40e_vsi *parent_vsi; 396 }; 397 398 struct i40e_ptp_pins_settings; 399 400 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch) 401 { 402 return !!ch->fwd; 403 } 404 405 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch) 406 { 407 if (i40e_is_channel_macvlan(ch)) 408 return ch->fwd->netdev->dev_addr; 409 else 410 return NULL; 411 } 412 413 /* struct that defines the Ethernet device */ 414 struct i40e_pf { 415 struct pci_dev *pdev; 416 struct devlink_port devlink_port; 417 struct i40e_hw hw; 418 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 419 struct msix_entry *msix_entries; 420 bool fc_autoneg_status; 421 422 u16 eeprom_version; 423 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 424 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 425 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 426 u16 num_req_vfs; /* num VFs requested for this PF */ 427 u16 num_vf_qps; /* num queue pairs per VF */ 428 u16 num_lan_qps; /* num lan queues this PF has set up */ 429 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 430 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 431 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 432 int iwarp_base_vector; 433 int queues_left; /* queues left unclaimed */ 434 u16 alloc_rss_size; /* allocated RSS queues */ 435 u16 rss_size_max; /* HW defined max RSS queues */ 436 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 437 u16 num_alloc_vsi; /* num VSIs this driver supports */ 438 u8 atr_sample_rate; 439 bool wol_en; 440 441 struct hlist_head fdir_filter_list; 442 u16 fdir_pf_active_filters; 443 unsigned long fd_flush_timestamp; 444 u32 fd_flush_cnt; 445 u32 fd_add_err; 446 u32 fd_atr_cnt; 447 448 /* Book-keeping of side-band filter count per flow-type. 449 * This is used to detect and handle input set changes for 450 * respective flow-type. 451 */ 452 u16 fd_tcp4_filter_cnt; 453 u16 fd_udp4_filter_cnt; 454 u16 fd_sctp4_filter_cnt; 455 u16 fd_ip4_filter_cnt; 456 457 u16 fd_tcp6_filter_cnt; 458 u16 fd_udp6_filter_cnt; 459 u16 fd_sctp6_filter_cnt; 460 u16 fd_ip6_filter_cnt; 461 462 /* Flexible filter table values that need to be programmed into 463 * hardware, which expects L3 and L4 to be programmed separately. We 464 * need to ensure that the values are in ascended order and don't have 465 * duplicates, so we track each L3 and L4 values in separate lists. 466 */ 467 struct list_head l3_flex_pit_list; 468 struct list_head l4_flex_pit_list; 469 470 struct udp_tunnel_nic_shared udp_tunnel_shared; 471 struct udp_tunnel_nic_info udp_tunnel_nic; 472 473 struct hlist_head cloud_filter_list; 474 u16 num_cloud_filters; 475 476 enum i40e_interrupt_policy int_policy; 477 u16 rx_itr_default; 478 u16 tx_itr_default; 479 u32 msg_enable; 480 char int_name[I40E_INT_NAME_STR_LEN]; 481 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 482 unsigned long service_timer_period; 483 unsigned long service_timer_previous; 484 struct timer_list service_timer; 485 struct work_struct service_task; 486 487 u32 hw_features; 488 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 489 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 490 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 491 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 492 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 493 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 494 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 495 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 496 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 497 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 498 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 499 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 500 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 501 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 502 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 503 #define I40E_HW_STOP_FW_LLDP BIT(16) 504 #define I40E_HW_PORT_ID_VALID BIT(17) 505 #define I40E_HW_RESTART_AUTONEG BIT(18) 506 507 u32 flags; 508 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 509 #define I40E_FLAG_MSI_ENABLED BIT(1) 510 #define I40E_FLAG_MSIX_ENABLED BIT(2) 511 #define I40E_FLAG_RSS_ENABLED BIT(3) 512 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 513 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 514 #define I40E_FLAG_DCB_CAPABLE BIT(6) 515 #define I40E_FLAG_DCB_ENABLED BIT(7) 516 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 517 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 518 #define I40E_FLAG_MFP_ENABLED BIT(10) 519 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 520 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 521 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 522 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 523 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 524 #define I40E_FLAG_LEGACY_RX BIT(16) 525 #define I40E_FLAG_PTP BIT(17) 526 #define I40E_FLAG_IWARP_ENABLED BIT(18) 527 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 528 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 529 #define I40E_FLAG_TC_MQPRIO BIT(21) 530 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 531 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 532 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 533 #define I40E_FLAG_RS_FEC BIT(25) 534 #define I40E_FLAG_BASE_R_FEC BIT(26) 535 #define I40E_FLAG_VF_VLAN_PRUNING BIT(27) 536 /* TOTAL_PORT_SHUTDOWN 537 * Allows to physically disable the link on the NIC's port. 538 * If enabled, (after link down request from the OS) 539 * no link, traffic or led activity is possible on that port. 540 * 541 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the 542 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true 543 * and cannot be disabled by system admin at that time. 544 * The functionalities are exclusive in terms of configuration, but they also 545 * have similar behavior (allowing to disable physical link of the port), 546 * with following differences: 547 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is 548 * supported by whole family of 7xx Intel Ethernet Controllers 549 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS) 550 * only if motherboard's BIOS and NIC's FW has support of it 551 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down 552 * by sending phy_type=0 to NIC's FW 553 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead 554 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK) 555 * in abilities field of i40e_aq_set_phy_config structure 556 */ 557 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27) 558 559 struct i40e_client_instance *cinst; 560 bool stat_offsets_loaded; 561 struct i40e_hw_port_stats stats; 562 struct i40e_hw_port_stats stats_offsets; 563 u32 tx_timeout_count; 564 u32 tx_timeout_recovery_level; 565 unsigned long tx_timeout_last_recovery; 566 u32 tx_sluggish_count; 567 u32 hw_csum_rx_error; 568 u32 led_status; 569 u16 corer_count; /* Core reset count */ 570 u16 globr_count; /* Global reset count */ 571 u16 empr_count; /* EMP reset count */ 572 u16 pfr_count; /* PF reset count */ 573 u16 sw_int_count; /* SW interrupt count */ 574 575 struct mutex switch_mutex; 576 u16 lan_vsi; /* our default LAN VSI */ 577 u16 lan_veb; /* initial relay, if exists */ 578 #define I40E_NO_VEB 0xffff 579 #define I40E_NO_VSI 0xffff 580 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 581 struct i40e_vsi **vsi; 582 struct i40e_veb *veb[I40E_MAX_VEB]; 583 584 struct i40e_lump_tracking *qp_pile; 585 struct i40e_lump_tracking *irq_pile; 586 587 /* switch config info */ 588 u16 pf_seid; 589 u16 main_vsi_seid; 590 u16 mac_seid; 591 struct kobject *switch_kobj; 592 #ifdef CONFIG_DEBUG_FS 593 struct dentry *i40e_dbg_pf; 594 #endif /* CONFIG_DEBUG_FS */ 595 bool cur_promisc; 596 597 u16 instance; /* A unique number per i40e_pf instance in the system */ 598 599 /* sr-iov config info */ 600 struct i40e_vf *vf; 601 int num_alloc_vfs; /* actual number of VFs allocated */ 602 u32 vf_aq_requests; 603 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 604 605 /* DCBx/DCBNL capability for PF that indicates 606 * whether DCBx is managed by firmware or host 607 * based agent (LLDPAD). Also, indicates what 608 * flavor of DCBx protocol (IEEE/CEE) is supported 609 * by the device. For now we're supporting IEEE 610 * mode only. 611 */ 612 u16 dcbx_cap; 613 614 struct i40e_filter_control_settings filter_settings; 615 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */ 616 struct i40e_dcbx_config tmp_cfg; 617 618 /* GPIO defines used by PTP */ 619 #define I40E_SDP3_2 18 620 #define I40E_SDP3_3 19 621 #define I40E_GPIO_4 20 622 #define I40E_LED2_0 26 623 #define I40E_LED2_1 27 624 #define I40E_LED3_0 28 625 #define I40E_LED3_1 29 626 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \ 627 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 628 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \ 629 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 630 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \ 631 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 632 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \ 633 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 634 #define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2) 635 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \ 636 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 637 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \ 638 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) 639 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \ 640 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) 641 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \ 642 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) 643 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \ 644 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 645 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \ 646 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 647 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \ 648 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) 649 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \ 650 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 651 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \ 652 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 653 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 654 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 655 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \ 656 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 657 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 658 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 659 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \ 660 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 661 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 662 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 663 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 664 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \ 665 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 666 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 667 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 668 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 669 #define I40E_GLGEN_GPIO_CTL_LED_INIT \ 670 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \ 671 I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 672 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \ 673 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 674 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \ 675 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN) 676 #define I40E_PRTTSYN_AUX_1_INSTNT \ 677 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) 678 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \ 679 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) 680 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) 681 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \ 682 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD) 683 #define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */ 684 #define I40E_PTP_2_SEC_DELAY 2 685 686 struct ptp_clock *ptp_clock; 687 struct ptp_clock_info ptp_caps; 688 struct sk_buff *ptp_tx_skb; 689 unsigned long ptp_tx_start; 690 struct hwtstamp_config tstamp_config; 691 struct timespec64 ptp_prev_hw_time; 692 struct work_struct ptp_pps_work; 693 struct work_struct ptp_extts0_work; 694 struct work_struct ptp_extts1_work; 695 ktime_t ptp_reset_start; 696 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 697 u32 ptp_adj_mult; 698 u32 tx_hwtstamp_timeouts; 699 u32 tx_hwtstamp_skipped; 700 u32 rx_hwtstamp_cleared; 701 u32 latch_event_flags; 702 u64 ptp_pps_start; 703 u32 pps_delay; 704 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 705 struct ptp_pin_desc ptp_pin[3]; 706 unsigned long latch_events[4]; 707 bool ptp_tx; 708 bool ptp_rx; 709 struct i40e_ptp_pins_settings *ptp_pins; 710 u16 rss_table_size; /* HW RSS table size */ 711 u32 max_bw; 712 u32 min_bw; 713 714 u32 ioremap_len; 715 u32 fd_inv; 716 u16 phy_led_val; 717 718 u16 override_q_count; 719 u16 last_sw_conf_flags; 720 u16 last_sw_conf_valid_flags; 721 /* List to keep previous DDP profiles to be rolled back in the future */ 722 struct list_head ddp_old_prof; 723 }; 724 725 /** 726 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 727 * @macaddr: the MAC Address as the base key 728 * 729 * Simply copies the address and returns it as a u64 for hashing 730 **/ 731 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 732 { 733 u64 key = 0; 734 735 ether_addr_copy((u8 *)&key, macaddr); 736 return key; 737 } 738 739 enum i40e_filter_state { 740 I40E_FILTER_INVALID = 0, /* Invalid state */ 741 I40E_FILTER_NEW, /* New, not sent to FW yet */ 742 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 743 I40E_FILTER_FAILED, /* Rejected by FW */ 744 I40E_FILTER_REMOVE, /* To be removed */ 745 /* There is no 'removed' state; the filter struct is freed */ 746 }; 747 struct i40e_mac_filter { 748 struct hlist_node hlist; 749 u8 macaddr[ETH_ALEN]; 750 #define I40E_VLAN_ANY -1 751 s16 vlan; 752 enum i40e_filter_state state; 753 }; 754 755 /* Wrapper structure to keep track of filters while we are preparing to send 756 * firmware commands. We cannot send firmware commands while holding a 757 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 758 * a separate structure, which will track the state change and update the real 759 * filter while under lock. We can't simply hold the filters in a separate 760 * list, as this opens a window for a race condition when adding new MAC 761 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 762 */ 763 struct i40e_new_mac_filter { 764 struct hlist_node hlist; 765 struct i40e_mac_filter *f; 766 767 /* Track future changes to state separately */ 768 enum i40e_filter_state state; 769 }; 770 771 struct i40e_veb { 772 struct i40e_pf *pf; 773 u16 idx; 774 u16 veb_idx; /* index of VEB parent */ 775 u16 seid; 776 u16 uplink_seid; 777 u16 stats_idx; /* index of VEB parent */ 778 u8 enabled_tc; 779 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 780 u16 flags; 781 u16 bw_limit; 782 u8 bw_max_quanta; 783 bool is_abs_credits; 784 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 785 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 786 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 787 struct kobject *kobj; 788 bool stat_offsets_loaded; 789 struct i40e_eth_stats stats; 790 struct i40e_eth_stats stats_offsets; 791 struct i40e_veb_tc_stats tc_stats; 792 struct i40e_veb_tc_stats tc_stats_offsets; 793 }; 794 795 /* struct that defines a VSI, associated with a dev */ 796 struct i40e_vsi { 797 struct net_device *netdev; 798 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 799 bool netdev_registered; 800 bool stat_offsets_loaded; 801 802 u32 current_netdev_flags; 803 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 804 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 805 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 806 unsigned long flags; 807 808 /* Per VSI lock to protect elements/hash (MAC filter) */ 809 spinlock_t mac_filter_hash_lock; 810 /* Fixed size hash table with 2^8 buckets for MAC filters */ 811 DECLARE_HASHTABLE(mac_filter_hash, 8); 812 bool has_vlan_filter; 813 814 /* VSI stats */ 815 struct rtnl_link_stats64 net_stats; 816 struct rtnl_link_stats64 net_stats_offsets; 817 struct i40e_eth_stats eth_stats; 818 struct i40e_eth_stats eth_stats_offsets; 819 u64 tx_restart; 820 u64 tx_busy; 821 u64 tx_linearize; 822 u64 tx_force_wb; 823 u64 tx_stopped; 824 u64 rx_buf_failed; 825 u64 rx_page_failed; 826 u64 rx_page_reuse; 827 u64 rx_page_alloc; 828 u64 rx_page_waive; 829 u64 rx_page_busy; 830 831 /* These are containers of ring pointers, allocated at run-time */ 832 struct i40e_ring **rx_rings; 833 struct i40e_ring **tx_rings; 834 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 835 836 u32 active_filters; 837 u32 promisc_threshold; 838 839 u16 work_limit; 840 u16 int_rate_limit; /* value in usecs */ 841 842 u16 rss_table_size; /* HW RSS table size */ 843 u16 rss_size; /* Allocated RSS queues */ 844 u8 *rss_hkey_user; /* User configured hash keys */ 845 u8 *rss_lut_user; /* User configured lookup table entries */ 846 847 848 u16 max_frame; 849 u16 rx_buf_len; 850 851 struct bpf_prog *xdp_prog; 852 853 /* List of q_vectors allocated to this VSI */ 854 struct i40e_q_vector **q_vectors; 855 int num_q_vectors; 856 int base_vector; 857 bool irqs_ready; 858 859 u16 seid; /* HW index of this VSI (absolute index) */ 860 u16 id; /* VSI number */ 861 u16 uplink_seid; 862 863 u16 base_queue; /* vsi's first queue in hw array */ 864 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 865 u16 req_queue_pairs; /* User requested queue pairs */ 866 u16 num_queue_pairs; /* Used tx and rx pairs */ 867 u16 num_tx_desc; 868 u16 num_rx_desc; 869 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 870 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 871 872 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 873 struct i40e_tc_configuration tc_config; 874 struct i40e_aqc_vsi_properties_data info; 875 876 /* VSI BW limit (absolute across all TCs) */ 877 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 878 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 879 880 /* Relative TC credits across VSIs */ 881 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 882 /* TC BW limit credits within VSI */ 883 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 884 /* TC BW limit max quanta within VSI */ 885 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 886 887 struct i40e_pf *back; /* Backreference to associated PF */ 888 u16 idx; /* index in pf->vsi[] */ 889 u16 veb_idx; /* index of VEB parent */ 890 struct kobject *kobj; /* sysfs object */ 891 bool current_isup; /* Sync 'link up' logging */ 892 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 893 894 /* channel specific fields */ 895 u16 cnt_q_avail; /* num of queues available for channel usage */ 896 u16 orig_rss_size; 897 u16 current_rss_size; 898 bool reconfig_rss; 899 900 u16 next_base_queue; /* next queue to be used for channel setup */ 901 902 struct list_head ch_list; 903 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 904 905 /* macvlan fields */ 906 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */ 907 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */ 908 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS); 909 struct list_head macvlan_list; 910 int macvlan_cnt; 911 912 void *priv; /* client driver data reference. */ 913 914 /* VSI specific handlers */ 915 irqreturn_t (*irq_handler)(int irq, void *data); 916 917 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 918 } ____cacheline_internodealigned_in_smp; 919 920 struct i40e_netdev_priv { 921 struct i40e_vsi *vsi; 922 }; 923 924 extern struct ida i40e_client_ida; 925 926 /* struct that defines an interrupt vector */ 927 struct i40e_q_vector { 928 struct i40e_vsi *vsi; 929 930 u16 v_idx; /* index in the vsi->q_vector array. */ 931 u16 reg_idx; /* register index of the interrupt */ 932 933 struct napi_struct napi; 934 935 struct i40e_ring_container rx; 936 struct i40e_ring_container tx; 937 938 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 939 u8 num_ringpairs; /* total number of ring pairs in vector */ 940 941 cpumask_t affinity_mask; 942 struct irq_affinity_notify affinity_notify; 943 944 struct rcu_head rcu; /* to avoid race with update stats on free */ 945 char name[I40E_INT_NAME_STR_LEN]; 946 bool arm_wb_state; 947 int irq_num; /* IRQ assigned to this q_vector */ 948 } ____cacheline_internodealigned_in_smp; 949 950 /* lan device */ 951 struct i40e_device { 952 struct list_head list; 953 struct i40e_pf *pf; 954 }; 955 956 /** 957 * i40e_nvm_version_str - format the NVM version strings 958 * @hw: ptr to the hardware info 959 **/ 960 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 961 { 962 static char buf[32]; 963 u32 full_ver; 964 965 full_ver = hw->nvm.oem_ver; 966 967 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 968 u8 gen, snap; 969 u16 release; 970 971 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 972 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 973 I40E_OEM_SNAP_SHIFT); 974 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 975 976 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 977 } else { 978 u8 ver, patch; 979 u16 build; 980 981 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 982 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 983 I40E_OEM_VER_BUILD_MASK); 984 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 985 986 snprintf(buf, sizeof(buf), 987 "%x.%02x 0x%x %d.%d.%d", 988 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 989 I40E_NVM_VERSION_HI_SHIFT, 990 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 991 I40E_NVM_VERSION_LO_SHIFT, 992 hw->nvm.eetrack, ver, build, patch); 993 } 994 995 return buf; 996 } 997 998 /** 999 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 1000 * @netdev: the corresponding netdev 1001 * 1002 * Return the PF struct for the given netdev 1003 **/ 1004 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 1005 { 1006 struct i40e_netdev_priv *np = netdev_priv(netdev); 1007 struct i40e_vsi *vsi = np->vsi; 1008 1009 return vsi->back; 1010 } 1011 1012 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 1013 irqreturn_t (*irq_handler)(int, void *)) 1014 { 1015 vsi->irq_handler = irq_handler; 1016 } 1017 1018 /** 1019 * i40e_get_fd_cnt_all - get the total FD filter space available 1020 * @pf: pointer to the PF struct 1021 **/ 1022 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 1023 { 1024 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 1025 } 1026 1027 /** 1028 * i40e_read_fd_input_set - reads value of flow director input set register 1029 * @pf: pointer to the PF struct 1030 * @addr: register addr 1031 * 1032 * This function reads value of flow director input set register 1033 * specified by 'addr' (which is specific to flow-type) 1034 **/ 1035 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 1036 { 1037 u64 val; 1038 1039 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 1040 val <<= 32; 1041 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 1042 1043 return val; 1044 } 1045 1046 /** 1047 * i40e_write_fd_input_set - writes value into flow director input set register 1048 * @pf: pointer to the PF struct 1049 * @addr: register addr 1050 * @val: value to be written 1051 * 1052 * This function writes specified value to the register specified by 'addr'. 1053 * This register is input set register based on flow-type. 1054 **/ 1055 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 1056 u16 addr, u64 val) 1057 { 1058 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 1059 (u32)(val >> 32)); 1060 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 1061 (u32)(val & 0xFFFFFFFFULL)); 1062 } 1063 1064 /** 1065 * i40e_get_pf_count - get PCI PF count. 1066 * @hw: pointer to a hw. 1067 * 1068 * Reports the function number of the highest PCI physical 1069 * function plus 1 as it is loaded from the NVM. 1070 * 1071 * Return: PCI PF count. 1072 **/ 1073 static inline u32 i40e_get_pf_count(struct i40e_hw *hw) 1074 { 1075 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK, 1076 rd32(hw, I40E_GLGEN_PCIFCNCNT)); 1077 } 1078 1079 /* needed by i40e_ethtool.c */ 1080 int i40e_up(struct i40e_vsi *vsi); 1081 void i40e_down(struct i40e_vsi *vsi); 1082 extern const char i40e_driver_name[]; 1083 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 1084 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 1085 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1086 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1087 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 1088 u16 rss_table_size, u16 rss_size); 1089 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 1090 /** 1091 * i40e_find_vsi_by_type - Find and return Flow Director VSI 1092 * @pf: PF to search for VSI 1093 * @type: Value indicating type of VSI we are looking for 1094 **/ 1095 static inline struct i40e_vsi * 1096 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 1097 { 1098 int i; 1099 1100 for (i = 0; i < pf->num_alloc_vsi; i++) { 1101 struct i40e_vsi *vsi = pf->vsi[i]; 1102 1103 if (vsi && vsi->type == type) 1104 return vsi; 1105 } 1106 1107 return NULL; 1108 } 1109 void i40e_update_stats(struct i40e_vsi *vsi); 1110 void i40e_update_veb_stats(struct i40e_veb *veb); 1111 void i40e_update_eth_stats(struct i40e_vsi *vsi); 1112 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 1113 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1114 bool printconfig); 1115 1116 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1117 struct i40e_fdir_filter *input, bool add); 1118 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1119 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1120 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1121 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1122 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1123 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1124 void i40e_set_ethtool_ops(struct net_device *netdev); 1125 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1126 const u8 *macaddr, s16 vlan); 1127 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1128 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1129 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1130 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1131 u16 uplink, u32 param1); 1132 int i40e_vsi_release(struct i40e_vsi *vsi); 1133 void i40e_service_event_schedule(struct i40e_pf *pf); 1134 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1135 u8 *msg, u16 len); 1136 1137 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1138 bool enable); 1139 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1140 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1141 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1142 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1143 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1144 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1145 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1146 u16 downlink_seid, u8 enabled_tc); 1147 void i40e_veb_release(struct i40e_veb *veb); 1148 1149 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1150 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1151 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1152 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1153 void i40e_pf_reset_stats(struct i40e_pf *pf); 1154 #ifdef CONFIG_DEBUG_FS 1155 void i40e_dbg_pf_init(struct i40e_pf *pf); 1156 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1157 void i40e_dbg_init(void); 1158 void i40e_dbg_exit(void); 1159 #else 1160 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1161 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1162 static inline void i40e_dbg_init(void) {} 1163 static inline void i40e_dbg_exit(void) {} 1164 #endif /* CONFIG_DEBUG_FS*/ 1165 /* needed by client drivers */ 1166 int i40e_lan_add_device(struct i40e_pf *pf); 1167 int i40e_lan_del_device(struct i40e_pf *pf); 1168 void i40e_client_subtask(struct i40e_pf *pf); 1169 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1170 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1171 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1172 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1173 void i40e_client_update_msix_info(struct i40e_pf *pf); 1174 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1175 /** 1176 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1177 * @vsi: pointer to a vsi 1178 * @vector: enable a particular Hw Interrupt vector, without base_vector 1179 **/ 1180 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1181 { 1182 struct i40e_pf *pf = vsi->back; 1183 struct i40e_hw *hw = &pf->hw; 1184 u32 val; 1185 1186 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1187 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1188 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1189 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1190 /* skip the flush */ 1191 } 1192 1193 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1194 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1195 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1196 int i40e_open(struct net_device *netdev); 1197 int i40e_close(struct net_device *netdev); 1198 int i40e_vsi_open(struct i40e_vsi *vsi); 1199 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1200 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1201 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1202 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1203 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1204 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1205 const u8 *macaddr); 1206 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1207 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1208 int i40e_count_filters(struct i40e_vsi *vsi); 1209 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1210 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1211 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf) 1212 { 1213 return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP); 1214 } 1215 1216 #ifdef CONFIG_I40E_DCB 1217 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1218 struct i40e_dcbx_config *old_cfg, 1219 struct i40e_dcbx_config *new_cfg); 1220 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1221 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1222 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1223 struct i40e_dcbx_config *old_cfg, 1224 struct i40e_dcbx_config *new_cfg); 1225 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg); 1226 int i40e_dcb_sw_default_config(struct i40e_pf *pf); 1227 #endif /* CONFIG_I40E_DCB */ 1228 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1229 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1230 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1231 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1232 void i40e_ptp_set_increment(struct i40e_pf *pf); 1233 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1234 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1235 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1236 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1237 void i40e_ptp_init(struct i40e_pf *pf); 1238 void i40e_ptp_stop(struct i40e_pf *pf); 1239 int i40e_ptp_alloc_pins(struct i40e_pf *pf); 1240 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset); 1241 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1242 int i40e_get_partition_bw_setting(struct i40e_pf *pf); 1243 int i40e_set_partition_bw_setting(struct i40e_pf *pf); 1244 int i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1245 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1246 1247 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1248 1249 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1250 { 1251 return !!READ_ONCE(vsi->xdp_prog); 1252 } 1253 1254 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1255 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1256 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1257 struct i40e_cloud_filter *filter, 1258 bool add); 1259 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1260 struct i40e_cloud_filter *filter, 1261 bool add); 1262 1263 /** 1264 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF 1265 * @pf: pointer to a pf. 1266 * 1267 * Check and return value of flag I40E_FLAG_TC_MQPRIO. 1268 * 1269 * Return: I40E_FLAG_TC_MQPRIO set state. 1270 **/ 1271 static inline u32 i40e_is_tc_mqprio_enabled(struct i40e_pf *pf) 1272 { 1273 return pf->flags & I40E_FLAG_TC_MQPRIO; 1274 } 1275 1276 /** 1277 * i40e_hw_to_pf - get pf pointer from the hardware structure 1278 * @hw: pointer to the device HW structure 1279 **/ 1280 static inline struct i40e_pf *i40e_hw_to_pf(struct i40e_hw *hw) 1281 { 1282 return container_of(hw, struct i40e_pf, hw); 1283 } 1284 1285 struct device *i40e_hw_to_dev(struct i40e_hw *hw); 1286 1287 #endif /* _I40E_H_ */ 1288