1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2017 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_H_ 28 #define _I40E_H_ 29 30 #include <net/tcp.h> 31 #include <net/udp.h> 32 #include <linux/types.h> 33 #include <linux/errno.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/aer.h> 37 #include <linux/netdevice.h> 38 #include <linux/ioport.h> 39 #include <linux/iommu.h> 40 #include <linux/slab.h> 41 #include <linux/list.h> 42 #include <linux/hashtable.h> 43 #include <linux/string.h> 44 #include <linux/in.h> 45 #include <linux/ip.h> 46 #include <linux/sctp.h> 47 #include <linux/pkt_sched.h> 48 #include <linux/ipv6.h> 49 #include <net/checksum.h> 50 #include <net/ip6_checksum.h> 51 #include <linux/ethtool.h> 52 #include <linux/if_vlan.h> 53 #include <linux/if_bridge.h> 54 #include <linux/clocksource.h> 55 #include <linux/net_tstamp.h> 56 #include <linux/ptp_clock_kernel.h> 57 #include <net/pkt_cls.h> 58 #include "i40e_type.h" 59 #include "i40e_prototype.h" 60 #include "i40e_client.h" 61 #include <linux/avf/virtchnl.h> 62 #include "i40e_virtchnl_pf.h" 63 #include "i40e_txrx.h" 64 #include "i40e_dcb.h" 65 66 /* Useful i40e defaults */ 67 #define I40E_MAX_VEB 16 68 69 #define I40E_MAX_NUM_DESCRIPTORS 4096 70 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 71 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 72 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 73 #define I40E_MIN_NUM_DESCRIPTORS 64 74 #define I40E_MIN_MSIX 2 75 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 76 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 77 /* max 16 qps */ 78 #define i40e_default_queues_per_vmdq(pf) \ 79 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 80 #define I40E_DEFAULT_QUEUES_PER_VF 4 81 #define I40E_MAX_VF_QUEUES 16 82 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */ 83 #define i40e_pf_get_max_q_per_tc(pf) \ 84 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 85 #define I40E_FDIR_RING 0 86 #define I40E_FDIR_RING_COUNT 32 87 #define I40E_MAX_AQ_BUF_SIZE 4096 88 #define I40E_AQ_LEN 256 89 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 90 #define I40E_MAX_USER_PRIORITY 8 91 #define I40E_MAX_QUEUES_PER_CH 64 92 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 93 #define I40E_DEFAULT_MSG_ENABLE 4 94 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 95 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 96 97 #define I40E_NVM_VERSION_LO_SHIFT 0 98 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 99 #define I40E_NVM_VERSION_HI_SHIFT 12 100 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 101 #define I40E_OEM_VER_BUILD_MASK 0xffff 102 #define I40E_OEM_VER_PATCH_MASK 0xff 103 #define I40E_OEM_VER_BUILD_SHIFT 8 104 #define I40E_OEM_VER_SHIFT 24 105 #define I40E_PHY_DEBUG_ALL \ 106 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 107 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 108 109 #define I40E_OEM_EETRACK_ID 0xffffffff 110 #define I40E_OEM_GEN_SHIFT 24 111 #define I40E_OEM_SNAP_MASK 0x00ff0000 112 #define I40E_OEM_SNAP_SHIFT 16 113 #define I40E_OEM_RELEASE_MASK 0x0000ffff 114 115 /* The values in here are decimal coded as hex as is the case in the NVM map*/ 116 #define I40E_CURRENT_NVM_VERSION_HI 0x2 117 #define I40E_CURRENT_NVM_VERSION_LO 0x40 118 119 #define I40E_RX_DESC(R, i) \ 120 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) 121 #define I40E_TX_DESC(R, i) \ 122 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 123 #define I40E_TX_CTXTDESC(R, i) \ 124 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 125 #define I40E_TX_FDIRDESC(R, i) \ 126 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 127 128 /* default to trying for four seconds */ 129 #define I40E_TRY_LINK_TIMEOUT (4 * HZ) 130 131 /* BW rate limiting */ 132 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 133 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 134 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 135 136 /* driver state flags */ 137 enum i40e_state_t { 138 __I40E_TESTING, 139 __I40E_CONFIG_BUSY, 140 __I40E_CONFIG_DONE, 141 __I40E_DOWN, 142 __I40E_SERVICE_SCHED, 143 __I40E_ADMINQ_EVENT_PENDING, 144 __I40E_MDD_EVENT_PENDING, 145 __I40E_VFLR_EVENT_PENDING, 146 __I40E_RESET_RECOVERY_PENDING, 147 __I40E_MISC_IRQ_REQUESTED, 148 __I40E_RESET_INTR_RECEIVED, 149 __I40E_REINIT_REQUESTED, 150 __I40E_PF_RESET_REQUESTED, 151 __I40E_CORE_RESET_REQUESTED, 152 __I40E_GLOBAL_RESET_REQUESTED, 153 __I40E_EMP_RESET_REQUESTED, 154 __I40E_EMP_RESET_INTR_RECEIVED, 155 __I40E_SUSPENDED, 156 __I40E_PTP_TX_IN_PROGRESS, 157 __I40E_BAD_EEPROM, 158 __I40E_DOWN_REQUESTED, 159 __I40E_FD_FLUSH_REQUESTED, 160 __I40E_RESET_FAILED, 161 __I40E_PORT_SUSPENDED, 162 __I40E_VF_DISABLE, 163 /* This must be last as it determines the size of the BITMAP */ 164 __I40E_STATE_SIZE__, 165 }; 166 167 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 168 169 /* VSI state flags */ 170 enum i40e_vsi_state_t { 171 __I40E_VSI_DOWN, 172 __I40E_VSI_NEEDS_RESTART, 173 __I40E_VSI_SYNCING_FILTERS, 174 __I40E_VSI_OVERFLOW_PROMISC, 175 __I40E_VSI_REINIT_REQUESTED, 176 __I40E_VSI_DOWN_REQUESTED, 177 /* This must be last as it determines the size of the BITMAP */ 178 __I40E_VSI_STATE_SIZE__, 179 }; 180 181 enum i40e_interrupt_policy { 182 I40E_INTERRUPT_BEST_CASE, 183 I40E_INTERRUPT_MEDIUM, 184 I40E_INTERRUPT_LOWEST 185 }; 186 187 struct i40e_lump_tracking { 188 u16 num_entries; 189 u16 search_hint; 190 u16 list[0]; 191 #define I40E_PILE_VALID_BIT 0x8000 192 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 193 }; 194 195 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 196 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 197 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 198 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 199 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 200 201 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 202 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 203 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 204 205 enum i40e_fd_stat_idx { 206 I40E_FD_STAT_ATR, 207 I40E_FD_STAT_SB, 208 I40E_FD_STAT_ATR_TUNNEL, 209 I40E_FD_STAT_PF_COUNT 210 }; 211 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 212 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 213 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 214 #define I40E_FD_SB_STAT_IDX(pf_id) \ 215 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 216 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 217 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 218 219 /* The following structure contains the data parsed from the user-defined 220 * field of the ethtool_rx_flow_spec structure. 221 */ 222 struct i40e_rx_flow_userdef { 223 bool flex_filter; 224 u16 flex_word; 225 u16 flex_offset; 226 }; 227 228 struct i40e_fdir_filter { 229 struct hlist_node fdir_node; 230 /* filter ipnut set */ 231 u8 flow_type; 232 u8 ip4_proto; 233 /* TX packet view of src and dst */ 234 __be32 dst_ip; 235 __be32 src_ip; 236 __be16 src_port; 237 __be16 dst_port; 238 __be32 sctp_v_tag; 239 240 /* Flexible data to match within the packet payload */ 241 __be16 flex_word; 242 u16 flex_offset; 243 bool flex_filter; 244 245 /* filter control */ 246 u16 q_index; 247 u8 flex_off; 248 u8 pctype; 249 u16 dest_vsi; 250 u8 dest_ctl; 251 u8 fd_status; 252 u16 cnt_index; 253 u32 fd_id; 254 }; 255 256 #define I40E_ETH_P_LLDP 0x88cc 257 258 #define I40E_DCB_PRIO_TYPE_STRICT 0 259 #define I40E_DCB_PRIO_TYPE_ETS 1 260 #define I40E_DCB_STRICT_PRIO_CREDITS 127 261 /* DCB per TC information data structure */ 262 struct i40e_tc_info { 263 u16 qoffset; /* Queue offset from base queue */ 264 u16 qcount; /* Total Queues */ 265 u8 netdev_tc; /* Netdev TC index if netdev associated */ 266 }; 267 268 /* TC configuration data structure */ 269 struct i40e_tc_configuration { 270 u8 numtc; /* Total number of enabled TCs */ 271 u8 enabled_tc; /* TC map */ 272 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 273 }; 274 275 struct i40e_udp_port_config { 276 /* AdminQ command interface expects port number in Host byte order */ 277 u16 port; 278 u8 type; 279 }; 280 281 /* macros related to FLX_PIT */ 282 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 283 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 284 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 285 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 286 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 287 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 288 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 289 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 290 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 291 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 292 I40E_FLEX_SET_FSIZE(fsize) | \ 293 I40E_FLEX_SET_SRC_WORD(src)) 294 295 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \ 296 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \ 297 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 298 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \ 299 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \ 300 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 301 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \ 302 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \ 303 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 304 305 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 306 307 /* macros related to GLQF_ORT */ 308 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 309 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 310 I40E_GLQF_ORT_PIT_INDX_MASK) 311 312 #define I40E_ORT_SET_COUNT(count) (((count) << \ 313 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 314 I40E_GLQF_ORT_FIELD_CNT_MASK) 315 316 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 317 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 318 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 319 320 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 321 I40E_ORT_SET_COUNT(count) | \ 322 I40E_ORT_SET_PAYLOAD(payload)) 323 324 #define I40E_L3_GLQF_ORT_IDX 34 325 #define I40E_L4_GLQF_ORT_IDX 35 326 327 /* Flex PIT register index */ 328 #define I40E_FLEX_PIT_IDX_START_L2 0 329 #define I40E_FLEX_PIT_IDX_START_L3 3 330 #define I40E_FLEX_PIT_IDX_START_L4 6 331 332 #define I40E_FLEX_PIT_TABLE_SIZE 3 333 334 #define I40E_FLEX_DEST_UNUSED 63 335 336 #define I40E_FLEX_INDEX_ENTRIES 8 337 338 /* Flex MASK to disable all flexible entries */ 339 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 340 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 341 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 342 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 343 344 struct i40e_flex_pit { 345 struct list_head list; 346 u16 src_offset; 347 u8 pit_index; 348 }; 349 350 struct i40e_channel { 351 struct list_head list; 352 bool initialized; 353 u8 type; 354 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 355 u16 stat_counter_idx; 356 u16 base_queue; 357 u16 num_queue_pairs; /* Requested by user */ 358 u16 seid; 359 360 u8 enabled_tc; 361 struct i40e_aqc_vsi_properties_data info; 362 363 u64 max_tx_rate; 364 365 /* track this channel belongs to which VSI */ 366 struct i40e_vsi *parent_vsi; 367 }; 368 369 /* struct that defines the Ethernet device */ 370 struct i40e_pf { 371 struct pci_dev *pdev; 372 struct i40e_hw hw; 373 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 374 struct msix_entry *msix_entries; 375 bool fc_autoneg_status; 376 377 u16 eeprom_version; 378 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 379 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 380 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 381 u16 num_req_vfs; /* num VFs requested for this PF */ 382 u16 num_vf_qps; /* num queue pairs per VF */ 383 u16 num_lan_qps; /* num lan queues this PF has set up */ 384 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 385 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 386 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 387 int iwarp_base_vector; 388 int queues_left; /* queues left unclaimed */ 389 u16 alloc_rss_size; /* allocated RSS queues */ 390 u16 rss_size_max; /* HW defined max RSS queues */ 391 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 392 u16 num_alloc_vsi; /* num VSIs this driver supports */ 393 u8 atr_sample_rate; 394 bool wol_en; 395 396 struct hlist_head fdir_filter_list; 397 u16 fdir_pf_active_filters; 398 unsigned long fd_flush_timestamp; 399 u32 fd_flush_cnt; 400 u32 fd_add_err; 401 u32 fd_atr_cnt; 402 403 /* Book-keeping of side-band filter count per flow-type. 404 * This is used to detect and handle input set changes for 405 * respective flow-type. 406 */ 407 u16 fd_tcp4_filter_cnt; 408 u16 fd_udp4_filter_cnt; 409 u16 fd_sctp4_filter_cnt; 410 u16 fd_ip4_filter_cnt; 411 412 /* Flexible filter table values that need to be programmed into 413 * hardware, which expects L3 and L4 to be programmed separately. We 414 * need to ensure that the values are in ascended order and don't have 415 * duplicates, so we track each L3 and L4 values in separate lists. 416 */ 417 struct list_head l3_flex_pit_list; 418 struct list_head l4_flex_pit_list; 419 420 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 421 u16 pending_udp_bitmap; 422 423 enum i40e_interrupt_policy int_policy; 424 u16 rx_itr_default; 425 u16 tx_itr_default; 426 u32 msg_enable; 427 char int_name[I40E_INT_NAME_STR_LEN]; 428 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 429 unsigned long service_timer_period; 430 unsigned long service_timer_previous; 431 struct timer_list service_timer; 432 struct work_struct service_task; 433 434 u32 hw_features; 435 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 436 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 437 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 438 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 439 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 440 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 441 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 442 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 443 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 444 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 445 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 446 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 447 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12) 448 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 449 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 450 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 451 #define I40E_HW_STOP_FW_LLDP BIT(16) 452 #define I40E_HW_PORT_ID_VALID BIT(17) 453 #define I40E_HW_RESTART_AUTONEG BIT(18) 454 455 u32 flags; 456 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 457 #define I40E_FLAG_MSI_ENABLED BIT(1) 458 #define I40E_FLAG_MSIX_ENABLED BIT(2) 459 #define I40E_FLAG_RSS_ENABLED BIT(3) 460 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 461 #define I40E_FLAG_FILTER_SYNC BIT(5) 462 #define I40E_FLAG_SRIOV_ENABLED BIT(6) 463 #define I40E_FLAG_DCB_CAPABLE BIT(7) 464 #define I40E_FLAG_DCB_ENABLED BIT(8) 465 #define I40E_FLAG_FD_SB_ENABLED BIT(9) 466 #define I40E_FLAG_FD_ATR_ENABLED BIT(10) 467 #define I40E_FLAG_FD_SB_AUTO_DISABLED BIT(11) 468 #define I40E_FLAG_FD_ATR_AUTO_DISABLED BIT(12) 469 #define I40E_FLAG_MFP_ENABLED BIT(13) 470 #define I40E_FLAG_UDP_FILTER_SYNC BIT(14) 471 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(15) 472 #define I40E_FLAG_VEB_MODE_ENABLED BIT(16) 473 #define I40E_FLAG_VEB_STATS_ENABLED BIT(17) 474 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(18) 475 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(19) 476 #define I40E_FLAG_TEMP_LINK_POLLING BIT(20) 477 #define I40E_FLAG_LEGACY_RX BIT(21) 478 #define I40E_FLAG_PTP BIT(22) 479 #define I40E_FLAG_IWARP_ENABLED BIT(23) 480 #define I40E_FLAG_SERVICE_CLIENT_REQUESTED BIT(24) 481 #define I40E_FLAG_CLIENT_L2_CHANGE BIT(25) 482 #define I40E_FLAG_CLIENT_RESET BIT(26) 483 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(27) 484 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(28) 485 #define I40E_FLAG_TC_MQPRIO BIT(29) 486 487 struct i40e_client_instance *cinst; 488 bool stat_offsets_loaded; 489 struct i40e_hw_port_stats stats; 490 struct i40e_hw_port_stats stats_offsets; 491 u32 tx_timeout_count; 492 u32 tx_timeout_recovery_level; 493 unsigned long tx_timeout_last_recovery; 494 u32 tx_sluggish_count; 495 u32 hw_csum_rx_error; 496 u32 led_status; 497 u16 corer_count; /* Core reset count */ 498 u16 globr_count; /* Global reset count */ 499 u16 empr_count; /* EMP reset count */ 500 u16 pfr_count; /* PF reset count */ 501 u16 sw_int_count; /* SW interrupt count */ 502 503 struct mutex switch_mutex; 504 u16 lan_vsi; /* our default LAN VSI */ 505 u16 lan_veb; /* initial relay, if exists */ 506 #define I40E_NO_VEB 0xffff 507 #define I40E_NO_VSI 0xffff 508 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 509 struct i40e_vsi **vsi; 510 struct i40e_veb *veb[I40E_MAX_VEB]; 511 512 struct i40e_lump_tracking *qp_pile; 513 struct i40e_lump_tracking *irq_pile; 514 515 /* switch config info */ 516 u16 pf_seid; 517 u16 main_vsi_seid; 518 u16 mac_seid; 519 struct kobject *switch_kobj; 520 #ifdef CONFIG_DEBUG_FS 521 struct dentry *i40e_dbg_pf; 522 #endif /* CONFIG_DEBUG_FS */ 523 bool cur_promisc; 524 525 u16 instance; /* A unique number per i40e_pf instance in the system */ 526 527 /* sr-iov config info */ 528 struct i40e_vf *vf; 529 int num_alloc_vfs; /* actual number of VFs allocated */ 530 u32 vf_aq_requests; 531 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 532 533 /* DCBx/DCBNL capability for PF that indicates 534 * whether DCBx is managed by firmware or host 535 * based agent (LLDPAD). Also, indicates what 536 * flavor of DCBx protocol (IEEE/CEE) is supported 537 * by the device. For now we're supporting IEEE 538 * mode only. 539 */ 540 u16 dcbx_cap; 541 542 struct i40e_filter_control_settings filter_settings; 543 544 struct ptp_clock *ptp_clock; 545 struct ptp_clock_info ptp_caps; 546 struct sk_buff *ptp_tx_skb; 547 unsigned long ptp_tx_start; 548 struct hwtstamp_config tstamp_config; 549 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 550 u64 ptp_base_adj; 551 u32 tx_hwtstamp_timeouts; 552 u32 tx_hwtstamp_skipped; 553 u32 rx_hwtstamp_cleared; 554 u32 latch_event_flags; 555 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 556 unsigned long latch_events[4]; 557 bool ptp_tx; 558 bool ptp_rx; 559 u16 rss_table_size; /* HW RSS table size */ 560 u32 max_bw; 561 u32 min_bw; 562 563 u32 ioremap_len; 564 u32 fd_inv; 565 u16 phy_led_val; 566 567 u16 override_q_count; 568 }; 569 570 /** 571 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 572 * @macaddr: the MAC Address as the base key 573 * 574 * Simply copies the address and returns it as a u64 for hashing 575 **/ 576 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 577 { 578 u64 key = 0; 579 580 ether_addr_copy((u8 *)&key, macaddr); 581 return key; 582 } 583 584 enum i40e_filter_state { 585 I40E_FILTER_INVALID = 0, /* Invalid state */ 586 I40E_FILTER_NEW, /* New, not sent to FW yet */ 587 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 588 I40E_FILTER_FAILED, /* Rejected by FW */ 589 I40E_FILTER_REMOVE, /* To be removed */ 590 /* There is no 'removed' state; the filter struct is freed */ 591 }; 592 struct i40e_mac_filter { 593 struct hlist_node hlist; 594 u8 macaddr[ETH_ALEN]; 595 #define I40E_VLAN_ANY -1 596 s16 vlan; 597 enum i40e_filter_state state; 598 }; 599 600 /* Wrapper structure to keep track of filters while we are preparing to send 601 * firmware commands. We cannot send firmware commands while holding a 602 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 603 * a separate structure, which will track the state change and update the real 604 * filter while under lock. We can't simply hold the filters in a separate 605 * list, as this opens a window for a race condition when adding new MAC 606 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 607 */ 608 struct i40e_new_mac_filter { 609 struct hlist_node hlist; 610 struct i40e_mac_filter *f; 611 612 /* Track future changes to state separately */ 613 enum i40e_filter_state state; 614 }; 615 616 struct i40e_veb { 617 struct i40e_pf *pf; 618 u16 idx; 619 u16 veb_idx; /* index of VEB parent */ 620 u16 seid; 621 u16 uplink_seid; 622 u16 stats_idx; /* index of VEB parent */ 623 u8 enabled_tc; 624 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 625 u16 flags; 626 u16 bw_limit; 627 u8 bw_max_quanta; 628 bool is_abs_credits; 629 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 630 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 631 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 632 struct kobject *kobj; 633 bool stat_offsets_loaded; 634 struct i40e_eth_stats stats; 635 struct i40e_eth_stats stats_offsets; 636 struct i40e_veb_tc_stats tc_stats; 637 struct i40e_veb_tc_stats tc_stats_offsets; 638 }; 639 640 /* struct that defines a VSI, associated with a dev */ 641 struct i40e_vsi { 642 struct net_device *netdev; 643 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 644 bool netdev_registered; 645 bool stat_offsets_loaded; 646 647 u32 current_netdev_flags; 648 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 649 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 650 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 651 unsigned long flags; 652 653 /* Per VSI lock to protect elements/hash (MAC filter) */ 654 spinlock_t mac_filter_hash_lock; 655 /* Fixed size hash table with 2^8 buckets for MAC filters */ 656 DECLARE_HASHTABLE(mac_filter_hash, 8); 657 bool has_vlan_filter; 658 659 /* VSI stats */ 660 struct rtnl_link_stats64 net_stats; 661 struct rtnl_link_stats64 net_stats_offsets; 662 struct i40e_eth_stats eth_stats; 663 struct i40e_eth_stats eth_stats_offsets; 664 u32 tx_restart; 665 u32 tx_busy; 666 u64 tx_linearize; 667 u64 tx_force_wb; 668 u32 rx_buf_failed; 669 u32 rx_page_failed; 670 671 /* These are containers of ring pointers, allocated at run-time */ 672 struct i40e_ring **rx_rings; 673 struct i40e_ring **tx_rings; 674 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 675 676 u32 active_filters; 677 u32 promisc_threshold; 678 679 u16 work_limit; 680 u16 int_rate_limit; /* value in usecs */ 681 682 u16 rss_table_size; /* HW RSS table size */ 683 u16 rss_size; /* Allocated RSS queues */ 684 u8 *rss_hkey_user; /* User configured hash keys */ 685 u8 *rss_lut_user; /* User configured lookup table entries */ 686 687 688 u16 max_frame; 689 u16 rx_buf_len; 690 691 struct bpf_prog *xdp_prog; 692 693 /* List of q_vectors allocated to this VSI */ 694 struct i40e_q_vector **q_vectors; 695 int num_q_vectors; 696 int base_vector; 697 bool irqs_ready; 698 699 u16 seid; /* HW index of this VSI (absolute index) */ 700 u16 id; /* VSI number */ 701 u16 uplink_seid; 702 703 u16 base_queue; /* vsi's first queue in hw array */ 704 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 705 u16 req_queue_pairs; /* User requested queue pairs */ 706 u16 num_queue_pairs; /* Used tx and rx pairs */ 707 u16 num_desc; 708 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 709 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 710 711 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 712 struct i40e_tc_configuration tc_config; 713 struct i40e_aqc_vsi_properties_data info; 714 715 /* VSI BW limit (absolute across all TCs) */ 716 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 717 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 718 719 /* Relative TC credits across VSIs */ 720 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 721 /* TC BW limit credits within VSI */ 722 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 723 /* TC BW limit max quanta within VSI */ 724 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 725 726 struct i40e_pf *back; /* Backreference to associated PF */ 727 u16 idx; /* index in pf->vsi[] */ 728 u16 veb_idx; /* index of VEB parent */ 729 struct kobject *kobj; /* sysfs object */ 730 bool current_isup; /* Sync 'link up' logging */ 731 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 732 733 /* channel specific fields */ 734 u16 cnt_q_avail; /* num of queues available for channel usage */ 735 u16 orig_rss_size; 736 u16 current_rss_size; 737 bool reconfig_rss; 738 739 u16 next_base_queue; /* next queue to be used for channel setup */ 740 741 struct list_head ch_list; 742 743 void *priv; /* client driver data reference. */ 744 745 /* VSI specific handlers */ 746 irqreturn_t (*irq_handler)(int irq, void *data); 747 } ____cacheline_internodealigned_in_smp; 748 749 struct i40e_netdev_priv { 750 struct i40e_vsi *vsi; 751 }; 752 753 /* struct that defines an interrupt vector */ 754 struct i40e_q_vector { 755 struct i40e_vsi *vsi; 756 757 u16 v_idx; /* index in the vsi->q_vector array. */ 758 u16 reg_idx; /* register index of the interrupt */ 759 760 struct napi_struct napi; 761 762 struct i40e_ring_container rx; 763 struct i40e_ring_container tx; 764 765 u8 num_ringpairs; /* total number of ring pairs in vector */ 766 767 cpumask_t affinity_mask; 768 struct irq_affinity_notify affinity_notify; 769 770 struct rcu_head rcu; /* to avoid race with update stats on free */ 771 char name[I40E_INT_NAME_STR_LEN]; 772 bool arm_wb_state; 773 #define ITR_COUNTDOWN_START 100 774 u8 itr_countdown; /* when 0 should adjust ITR */ 775 } ____cacheline_internodealigned_in_smp; 776 777 /* lan device */ 778 struct i40e_device { 779 struct list_head list; 780 struct i40e_pf *pf; 781 }; 782 783 /** 784 * i40e_nvm_version_str - format the NVM version strings 785 * @hw: ptr to the hardware info 786 **/ 787 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 788 { 789 static char buf[32]; 790 u32 full_ver; 791 792 full_ver = hw->nvm.oem_ver; 793 794 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 795 u8 gen, snap; 796 u16 release; 797 798 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 799 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 800 I40E_OEM_SNAP_SHIFT); 801 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 802 803 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 804 } else { 805 u8 ver, patch; 806 u16 build; 807 808 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 809 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 810 I40E_OEM_VER_BUILD_MASK); 811 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 812 813 snprintf(buf, sizeof(buf), 814 "%x.%02x 0x%x %d.%d.%d", 815 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 816 I40E_NVM_VERSION_HI_SHIFT, 817 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 818 I40E_NVM_VERSION_LO_SHIFT, 819 hw->nvm.eetrack, ver, build, patch); 820 } 821 822 return buf; 823 } 824 825 /** 826 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 827 * @netdev: the corresponding netdev 828 * 829 * Return the PF struct for the given netdev 830 **/ 831 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 832 { 833 struct i40e_netdev_priv *np = netdev_priv(netdev); 834 struct i40e_vsi *vsi = np->vsi; 835 836 return vsi->back; 837 } 838 839 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 840 irqreturn_t (*irq_handler)(int, void *)) 841 { 842 vsi->irq_handler = irq_handler; 843 } 844 845 /** 846 * i40e_get_fd_cnt_all - get the total FD filter space available 847 * @pf: pointer to the PF struct 848 **/ 849 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 850 { 851 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 852 } 853 854 /** 855 * i40e_read_fd_input_set - reads value of flow director input set register 856 * @pf: pointer to the PF struct 857 * @addr: register addr 858 * 859 * This function reads value of flow director input set register 860 * specified by 'addr' (which is specific to flow-type) 861 **/ 862 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 863 { 864 u64 val; 865 866 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 867 val <<= 32; 868 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 869 870 return val; 871 } 872 873 /** 874 * i40e_write_fd_input_set - writes value into flow director input set register 875 * @pf: pointer to the PF struct 876 * @addr: register addr 877 * @val: value to be written 878 * 879 * This function writes specified value to the register specified by 'addr'. 880 * This register is input set register based on flow-type. 881 **/ 882 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 883 u16 addr, u64 val) 884 { 885 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 886 (u32)(val >> 32)); 887 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 888 (u32)(val & 0xFFFFFFFFULL)); 889 } 890 891 /* needed by i40e_ethtool.c */ 892 int i40e_up(struct i40e_vsi *vsi); 893 void i40e_down(struct i40e_vsi *vsi); 894 extern const char i40e_driver_name[]; 895 extern const char i40e_driver_version_str[]; 896 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 897 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 898 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 899 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 900 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 901 u16 rss_table_size, u16 rss_size); 902 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 903 /** 904 * i40e_find_vsi_by_type - Find and return Flow Director VSI 905 * @pf: PF to search for VSI 906 * @type: Value indicating type of VSI we are looking for 907 **/ 908 static inline struct i40e_vsi * 909 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 910 { 911 int i; 912 913 for (i = 0; i < pf->num_alloc_vsi; i++) { 914 struct i40e_vsi *vsi = pf->vsi[i]; 915 916 if (vsi && vsi->type == type) 917 return vsi; 918 } 919 920 return NULL; 921 } 922 void i40e_update_stats(struct i40e_vsi *vsi); 923 void i40e_update_eth_stats(struct i40e_vsi *vsi); 924 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 925 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 926 bool printconfig); 927 928 int i40e_add_del_fdir(struct i40e_vsi *vsi, 929 struct i40e_fdir_filter *input, bool add); 930 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 931 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 932 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 933 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 934 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 935 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 936 void i40e_set_ethtool_ops(struct net_device *netdev); 937 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 938 const u8 *macaddr, s16 vlan); 939 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 940 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 941 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 942 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 943 u16 uplink, u32 param1); 944 int i40e_vsi_release(struct i40e_vsi *vsi); 945 void i40e_service_event_schedule(struct i40e_pf *pf); 946 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 947 u8 *msg, u16 len); 948 949 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 950 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 951 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 952 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 953 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 954 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 955 u16 downlink_seid, u8 enabled_tc); 956 void i40e_veb_release(struct i40e_veb *veb); 957 958 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 959 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 960 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 961 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 962 void i40e_pf_reset_stats(struct i40e_pf *pf); 963 #ifdef CONFIG_DEBUG_FS 964 void i40e_dbg_pf_init(struct i40e_pf *pf); 965 void i40e_dbg_pf_exit(struct i40e_pf *pf); 966 void i40e_dbg_init(void); 967 void i40e_dbg_exit(void); 968 #else 969 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 970 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 971 static inline void i40e_dbg_init(void) {} 972 static inline void i40e_dbg_exit(void) {} 973 #endif /* CONFIG_DEBUG_FS*/ 974 /* needed by client drivers */ 975 int i40e_lan_add_device(struct i40e_pf *pf); 976 int i40e_lan_del_device(struct i40e_pf *pf); 977 void i40e_client_subtask(struct i40e_pf *pf); 978 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 979 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 980 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 981 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 982 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 983 /** 984 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 985 * @vsi: pointer to a vsi 986 * @vector: enable a particular Hw Interrupt vector, without base_vector 987 **/ 988 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 989 { 990 struct i40e_pf *pf = vsi->back; 991 struct i40e_hw *hw = &pf->hw; 992 u32 val; 993 994 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 995 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 996 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 997 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 998 /* skip the flush */ 999 } 1000 1001 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1002 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1003 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1004 int i40e_open(struct net_device *netdev); 1005 int i40e_close(struct net_device *netdev); 1006 int i40e_vsi_open(struct i40e_vsi *vsi); 1007 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1008 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1009 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1010 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1011 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1012 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1013 const u8 *macaddr); 1014 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1015 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1016 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1017 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1018 #ifdef CONFIG_I40E_DCB 1019 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1020 struct i40e_dcbx_config *old_cfg, 1021 struct i40e_dcbx_config *new_cfg); 1022 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1023 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1024 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1025 struct i40e_dcbx_config *old_cfg, 1026 struct i40e_dcbx_config *new_cfg); 1027 #endif /* CONFIG_I40E_DCB */ 1028 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1029 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1030 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1031 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1032 void i40e_ptp_set_increment(struct i40e_pf *pf); 1033 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1034 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1035 void i40e_ptp_init(struct i40e_pf *pf); 1036 void i40e_ptp_stop(struct i40e_pf *pf); 1037 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1038 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); 1039 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); 1040 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1041 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1042 1043 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1044 { 1045 return !!vsi->xdp_prog; 1046 } 1047 1048 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1049 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1050 #endif /* _I40E_H_ */ 1051