1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <net/tcp.h> 8 #include <net/udp.h> 9 #include <linux/types.h> 10 #include <linux/errno.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/aer.h> 14 #include <linux/netdevice.h> 15 #include <linux/ioport.h> 16 #include <linux/iommu.h> 17 #include <linux/slab.h> 18 #include <linux/list.h> 19 #include <linux/hashtable.h> 20 #include <linux/string.h> 21 #include <linux/in.h> 22 #include <linux/ip.h> 23 #include <linux/sctp.h> 24 #include <linux/pkt_sched.h> 25 #include <linux/ipv6.h> 26 #include <net/checksum.h> 27 #include <net/ip6_checksum.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/if_macvlan.h> 31 #include <linux/if_bridge.h> 32 #include <linux/clocksource.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/ptp_clock_kernel.h> 35 #include <net/pkt_cls.h> 36 #include <net/tc_act/tc_gact.h> 37 #include <net/tc_act/tc_mirred.h> 38 #include <net/xdp_sock.h> 39 #include "i40e_type.h" 40 #include "i40e_prototype.h" 41 #include <linux/net/intel/i40e_client.h> 42 #include <linux/avf/virtchnl.h> 43 #include "i40e_virtchnl_pf.h" 44 #include "i40e_txrx.h" 45 #include "i40e_dcb.h" 46 47 /* Useful i40e defaults */ 48 #define I40E_MAX_VEB 16 49 50 #define I40E_MAX_NUM_DESCRIPTORS 4096 51 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 52 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 53 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 54 #define I40E_MIN_NUM_DESCRIPTORS 64 55 #define I40E_MIN_MSIX 2 56 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 57 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 58 /* max 16 qps */ 59 #define i40e_default_queues_per_vmdq(pf) \ 60 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 61 #define I40E_DEFAULT_QUEUES_PER_VF 4 62 #define I40E_MAX_VF_QUEUES 16 63 #define i40e_pf_get_max_q_per_tc(pf) \ 64 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 65 #define I40E_FDIR_RING_COUNT 32 66 #define I40E_MAX_AQ_BUF_SIZE 4096 67 #define I40E_AQ_LEN 256 68 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 69 #define I40E_MAX_USER_PRIORITY 8 70 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 71 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 72 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 73 74 #define I40E_NVM_VERSION_LO_SHIFT 0 75 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 76 #define I40E_NVM_VERSION_HI_SHIFT 12 77 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 78 #define I40E_OEM_VER_BUILD_MASK 0xffff 79 #define I40E_OEM_VER_PATCH_MASK 0xff 80 #define I40E_OEM_VER_BUILD_SHIFT 8 81 #define I40E_OEM_VER_SHIFT 24 82 #define I40E_PHY_DEBUG_ALL \ 83 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 84 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 85 86 #define I40E_OEM_EETRACK_ID 0xffffffff 87 #define I40E_OEM_GEN_SHIFT 24 88 #define I40E_OEM_SNAP_MASK 0x00ff0000 89 #define I40E_OEM_SNAP_SHIFT 16 90 #define I40E_OEM_RELEASE_MASK 0x0000ffff 91 92 #define I40E_RX_DESC(R, i) \ 93 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) 94 #define I40E_TX_DESC(R, i) \ 95 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 96 #define I40E_TX_CTXTDESC(R, i) \ 97 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 98 #define I40E_TX_FDIRDESC(R, i) \ 99 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 100 101 /* BW rate limiting */ 102 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 103 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 104 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 105 106 /* driver state flags */ 107 enum i40e_state_t { 108 __I40E_TESTING, 109 __I40E_CONFIG_BUSY, 110 __I40E_CONFIG_DONE, 111 __I40E_DOWN, 112 __I40E_SERVICE_SCHED, 113 __I40E_ADMINQ_EVENT_PENDING, 114 __I40E_MDD_EVENT_PENDING, 115 __I40E_VFLR_EVENT_PENDING, 116 __I40E_RESET_RECOVERY_PENDING, 117 __I40E_TIMEOUT_RECOVERY_PENDING, 118 __I40E_MISC_IRQ_REQUESTED, 119 __I40E_RESET_INTR_RECEIVED, 120 __I40E_REINIT_REQUESTED, 121 __I40E_PF_RESET_REQUESTED, 122 __I40E_CORE_RESET_REQUESTED, 123 __I40E_GLOBAL_RESET_REQUESTED, 124 __I40E_EMP_RESET_INTR_RECEIVED, 125 __I40E_SUSPENDED, 126 __I40E_PTP_TX_IN_PROGRESS, 127 __I40E_BAD_EEPROM, 128 __I40E_DOWN_REQUESTED, 129 __I40E_FD_FLUSH_REQUESTED, 130 __I40E_FD_ATR_AUTO_DISABLED, 131 __I40E_FD_SB_AUTO_DISABLED, 132 __I40E_RESET_FAILED, 133 __I40E_PORT_SUSPENDED, 134 __I40E_VF_DISABLE, 135 __I40E_MACVLAN_SYNC_PENDING, 136 __I40E_UDP_FILTER_SYNC_PENDING, 137 __I40E_TEMP_LINK_POLLING, 138 __I40E_CLIENT_SERVICE_REQUESTED, 139 __I40E_CLIENT_L2_CHANGE, 140 __I40E_CLIENT_RESET, 141 __I40E_VIRTCHNL_OP_PENDING, 142 __I40E_RECOVERY_MODE, 143 /* This must be last as it determines the size of the BITMAP */ 144 __I40E_STATE_SIZE__, 145 }; 146 147 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 148 149 /* VSI state flags */ 150 enum i40e_vsi_state_t { 151 __I40E_VSI_DOWN, 152 __I40E_VSI_NEEDS_RESTART, 153 __I40E_VSI_SYNCING_FILTERS, 154 __I40E_VSI_OVERFLOW_PROMISC, 155 __I40E_VSI_REINIT_REQUESTED, 156 __I40E_VSI_DOWN_REQUESTED, 157 /* This must be last as it determines the size of the BITMAP */ 158 __I40E_VSI_STATE_SIZE__, 159 }; 160 161 enum i40e_interrupt_policy { 162 I40E_INTERRUPT_BEST_CASE, 163 I40E_INTERRUPT_MEDIUM, 164 I40E_INTERRUPT_LOWEST 165 }; 166 167 struct i40e_lump_tracking { 168 u16 num_entries; 169 u16 search_hint; 170 u16 list[0]; 171 #define I40E_PILE_VALID_BIT 0x8000 172 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 173 }; 174 175 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 176 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 177 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 178 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 179 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 180 181 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 182 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 183 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 184 185 enum i40e_fd_stat_idx { 186 I40E_FD_STAT_ATR, 187 I40E_FD_STAT_SB, 188 I40E_FD_STAT_ATR_TUNNEL, 189 I40E_FD_STAT_PF_COUNT 190 }; 191 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 192 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 193 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 194 #define I40E_FD_SB_STAT_IDX(pf_id) \ 195 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 196 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 197 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 198 199 /* The following structure contains the data parsed from the user-defined 200 * field of the ethtool_rx_flow_spec structure. 201 */ 202 struct i40e_rx_flow_userdef { 203 bool flex_filter; 204 u16 flex_word; 205 u16 flex_offset; 206 }; 207 208 struct i40e_fdir_filter { 209 struct hlist_node fdir_node; 210 /* filter ipnut set */ 211 u8 flow_type; 212 u8 ip4_proto; 213 /* TX packet view of src and dst */ 214 __be32 dst_ip; 215 __be32 src_ip; 216 __be16 src_port; 217 __be16 dst_port; 218 __be32 sctp_v_tag; 219 220 /* Flexible data to match within the packet payload */ 221 __be16 flex_word; 222 u16 flex_offset; 223 bool flex_filter; 224 225 /* filter control */ 226 u16 q_index; 227 u8 flex_off; 228 u8 pctype; 229 u16 dest_vsi; 230 u8 dest_ctl; 231 u8 fd_status; 232 u16 cnt_index; 233 u32 fd_id; 234 }; 235 236 #define I40E_CLOUD_FIELD_OMAC BIT(0) 237 #define I40E_CLOUD_FIELD_IMAC BIT(1) 238 #define I40E_CLOUD_FIELD_IVLAN BIT(2) 239 #define I40E_CLOUD_FIELD_TEN_ID BIT(3) 240 #define I40E_CLOUD_FIELD_IIP BIT(4) 241 242 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 243 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 244 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 245 I40E_CLOUD_FIELD_IVLAN) 246 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 247 I40E_CLOUD_FIELD_TEN_ID) 248 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 249 I40E_CLOUD_FIELD_IMAC | \ 250 I40E_CLOUD_FIELD_TEN_ID) 251 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 252 I40E_CLOUD_FIELD_IVLAN | \ 253 I40E_CLOUD_FIELD_TEN_ID) 254 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 255 256 struct i40e_cloud_filter { 257 struct hlist_node cloud_node; 258 unsigned long cookie; 259 /* cloud filter input set follows */ 260 u8 dst_mac[ETH_ALEN]; 261 u8 src_mac[ETH_ALEN]; 262 __be16 vlan_id; 263 u16 seid; /* filter control */ 264 __be16 dst_port; 265 __be16 src_port; 266 u32 tenant_id; 267 union { 268 struct { 269 struct in_addr dst_ip; 270 struct in_addr src_ip; 271 } v4; 272 struct { 273 struct in6_addr dst_ip6; 274 struct in6_addr src_ip6; 275 } v6; 276 } ip; 277 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 278 #define src_ipv6 ip.v6.src_ip6.s6_addr32 279 #define dst_ipv4 ip.v4.dst_ip.s_addr 280 #define src_ipv4 ip.v4.src_ip.s_addr 281 u16 n_proto; /* Ethernet Protocol */ 282 u8 ip_proto; /* IPPROTO value */ 283 u8 flags; 284 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 285 u8 tunnel_type; 286 }; 287 288 /* DCB per TC information data structure */ 289 struct i40e_tc_info { 290 u16 qoffset; /* Queue offset from base queue */ 291 u16 qcount; /* Total Queues */ 292 u8 netdev_tc; /* Netdev TC index if netdev associated */ 293 }; 294 295 /* TC configuration data structure */ 296 struct i40e_tc_configuration { 297 u8 numtc; /* Total number of enabled TCs */ 298 u8 enabled_tc; /* TC map */ 299 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 300 }; 301 302 #define I40E_UDP_PORT_INDEX_UNUSED 255 303 struct i40e_udp_port_config { 304 /* AdminQ command interface expects port number in Host byte order */ 305 u16 port; 306 u8 type; 307 u8 filter_index; 308 }; 309 310 #define I40_DDP_FLASH_REGION 100 311 #define I40E_PROFILE_INFO_SIZE 48 312 #define I40E_MAX_PROFILE_NUM 16 313 #define I40E_PROFILE_LIST_SIZE \ 314 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4) 315 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/" 316 #define I40E_DDP_PROFILE_NAME_MAX 64 317 318 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size, 319 bool is_add); 320 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash); 321 322 struct i40e_ddp_profile_list { 323 u32 p_count; 324 struct i40e_profile_info p_info[]; 325 }; 326 327 struct i40e_ddp_old_profile_list { 328 struct list_head list; 329 size_t old_ddp_size; 330 u8 old_ddp_buf[]; 331 }; 332 333 /* macros related to FLX_PIT */ 334 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 335 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 336 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 337 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 338 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 339 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 340 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 341 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 342 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 343 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 344 I40E_FLEX_SET_FSIZE(fsize) | \ 345 I40E_FLEX_SET_SRC_WORD(src)) 346 347 348 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 349 350 /* macros related to GLQF_ORT */ 351 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 352 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 353 I40E_GLQF_ORT_PIT_INDX_MASK) 354 355 #define I40E_ORT_SET_COUNT(count) (((count) << \ 356 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 357 I40E_GLQF_ORT_FIELD_CNT_MASK) 358 359 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 360 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 361 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 362 363 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 364 I40E_ORT_SET_COUNT(count) | \ 365 I40E_ORT_SET_PAYLOAD(payload)) 366 367 #define I40E_L3_GLQF_ORT_IDX 34 368 #define I40E_L4_GLQF_ORT_IDX 35 369 370 /* Flex PIT register index */ 371 #define I40E_FLEX_PIT_IDX_START_L3 3 372 #define I40E_FLEX_PIT_IDX_START_L4 6 373 374 #define I40E_FLEX_PIT_TABLE_SIZE 3 375 376 #define I40E_FLEX_DEST_UNUSED 63 377 378 #define I40E_FLEX_INDEX_ENTRIES 8 379 380 /* Flex MASK to disable all flexible entries */ 381 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 382 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 383 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 384 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 385 386 struct i40e_flex_pit { 387 struct list_head list; 388 u16 src_offset; 389 u8 pit_index; 390 }; 391 392 struct i40e_fwd_adapter { 393 struct net_device *netdev; 394 int bit_no; 395 }; 396 397 struct i40e_channel { 398 struct list_head list; 399 bool initialized; 400 u8 type; 401 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 402 u16 stat_counter_idx; 403 u16 base_queue; 404 u16 num_queue_pairs; /* Requested by user */ 405 u16 seid; 406 407 u8 enabled_tc; 408 struct i40e_aqc_vsi_properties_data info; 409 410 u64 max_tx_rate; 411 struct i40e_fwd_adapter *fwd; 412 413 /* track this channel belongs to which VSI */ 414 struct i40e_vsi *parent_vsi; 415 }; 416 417 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch) 418 { 419 return !!ch->fwd; 420 } 421 422 static inline u8 *i40e_channel_mac(struct i40e_channel *ch) 423 { 424 if (i40e_is_channel_macvlan(ch)) 425 return ch->fwd->netdev->dev_addr; 426 else 427 return NULL; 428 } 429 430 /* struct that defines the Ethernet device */ 431 struct i40e_pf { 432 struct pci_dev *pdev; 433 struct i40e_hw hw; 434 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 435 struct msix_entry *msix_entries; 436 bool fc_autoneg_status; 437 438 u16 eeprom_version; 439 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 440 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 441 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 442 u16 num_req_vfs; /* num VFs requested for this PF */ 443 u16 num_vf_qps; /* num queue pairs per VF */ 444 u16 num_lan_qps; /* num lan queues this PF has set up */ 445 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 446 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 447 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 448 int iwarp_base_vector; 449 int queues_left; /* queues left unclaimed */ 450 u16 alloc_rss_size; /* allocated RSS queues */ 451 u16 rss_size_max; /* HW defined max RSS queues */ 452 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 453 u16 num_alloc_vsi; /* num VSIs this driver supports */ 454 u8 atr_sample_rate; 455 bool wol_en; 456 457 struct hlist_head fdir_filter_list; 458 u16 fdir_pf_active_filters; 459 unsigned long fd_flush_timestamp; 460 u32 fd_flush_cnt; 461 u32 fd_add_err; 462 u32 fd_atr_cnt; 463 464 /* Book-keeping of side-band filter count per flow-type. 465 * This is used to detect and handle input set changes for 466 * respective flow-type. 467 */ 468 u16 fd_tcp4_filter_cnt; 469 u16 fd_udp4_filter_cnt; 470 u16 fd_sctp4_filter_cnt; 471 u16 fd_ip4_filter_cnt; 472 473 /* Flexible filter table values that need to be programmed into 474 * hardware, which expects L3 and L4 to be programmed separately. We 475 * need to ensure that the values are in ascended order and don't have 476 * duplicates, so we track each L3 and L4 values in separate lists. 477 */ 478 struct list_head l3_flex_pit_list; 479 struct list_head l4_flex_pit_list; 480 481 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 482 u16 pending_udp_bitmap; 483 484 struct hlist_head cloud_filter_list; 485 u16 num_cloud_filters; 486 487 enum i40e_interrupt_policy int_policy; 488 u16 rx_itr_default; 489 u16 tx_itr_default; 490 u32 msg_enable; 491 char int_name[I40E_INT_NAME_STR_LEN]; 492 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 493 unsigned long service_timer_period; 494 unsigned long service_timer_previous; 495 struct timer_list service_timer; 496 struct work_struct service_task; 497 498 u32 hw_features; 499 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 500 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 501 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 502 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 503 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 504 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 505 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 506 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 507 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 508 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 509 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 510 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 511 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 512 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 513 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 514 #define I40E_HW_STOP_FW_LLDP BIT(16) 515 #define I40E_HW_PORT_ID_VALID BIT(17) 516 #define I40E_HW_RESTART_AUTONEG BIT(18) 517 518 u32 flags; 519 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 520 #define I40E_FLAG_MSI_ENABLED BIT(1) 521 #define I40E_FLAG_MSIX_ENABLED BIT(2) 522 #define I40E_FLAG_RSS_ENABLED BIT(3) 523 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 524 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 525 #define I40E_FLAG_DCB_CAPABLE BIT(6) 526 #define I40E_FLAG_DCB_ENABLED BIT(7) 527 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 528 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 529 #define I40E_FLAG_MFP_ENABLED BIT(10) 530 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 531 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 532 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 533 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 534 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 535 #define I40E_FLAG_LEGACY_RX BIT(16) 536 #define I40E_FLAG_PTP BIT(17) 537 #define I40E_FLAG_IWARP_ENABLED BIT(18) 538 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 539 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 540 #define I40E_FLAG_TC_MQPRIO BIT(21) 541 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 542 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 543 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 544 #define I40E_FLAG_RS_FEC BIT(25) 545 #define I40E_FLAG_BASE_R_FEC BIT(26) 546 /* TOTAL_PORT_SHUTDOWN 547 * Allows to physically disable the link on the NIC's port. 548 * If enabled, (after link down request from the OS) 549 * no link, traffic or led activity is possible on that port. 550 * 551 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the 552 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true 553 * and cannot be disabled by system admin at that time. 554 * The functionalities are exclusive in terms of configuration, but they also 555 * have similar behavior (allowing to disable physical link of the port), 556 * with following differences: 557 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is 558 * supported by whole family of 7xx Intel Ethernet Controllers 559 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS) 560 * only if motherboard's BIOS and NIC's FW has support of it 561 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down 562 * by sending phy_type=0 to NIC's FW 563 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead 564 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK) 565 * in abilities field of i40e_aq_set_phy_config structure 566 */ 567 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27) 568 569 struct i40e_client_instance *cinst; 570 bool stat_offsets_loaded; 571 struct i40e_hw_port_stats stats; 572 struct i40e_hw_port_stats stats_offsets; 573 u32 tx_timeout_count; 574 u32 tx_timeout_recovery_level; 575 unsigned long tx_timeout_last_recovery; 576 u32 tx_sluggish_count; 577 u32 hw_csum_rx_error; 578 u32 led_status; 579 u16 corer_count; /* Core reset count */ 580 u16 globr_count; /* Global reset count */ 581 u16 empr_count; /* EMP reset count */ 582 u16 pfr_count; /* PF reset count */ 583 u16 sw_int_count; /* SW interrupt count */ 584 585 struct mutex switch_mutex; 586 u16 lan_vsi; /* our default LAN VSI */ 587 u16 lan_veb; /* initial relay, if exists */ 588 #define I40E_NO_VEB 0xffff 589 #define I40E_NO_VSI 0xffff 590 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 591 struct i40e_vsi **vsi; 592 struct i40e_veb *veb[I40E_MAX_VEB]; 593 594 struct i40e_lump_tracking *qp_pile; 595 struct i40e_lump_tracking *irq_pile; 596 597 /* switch config info */ 598 u16 pf_seid; 599 u16 main_vsi_seid; 600 u16 mac_seid; 601 struct kobject *switch_kobj; 602 #ifdef CONFIG_DEBUG_FS 603 struct dentry *i40e_dbg_pf; 604 #endif /* CONFIG_DEBUG_FS */ 605 bool cur_promisc; 606 607 u16 instance; /* A unique number per i40e_pf instance in the system */ 608 609 /* sr-iov config info */ 610 struct i40e_vf *vf; 611 int num_alloc_vfs; /* actual number of VFs allocated */ 612 u32 vf_aq_requests; 613 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 614 615 /* DCBx/DCBNL capability for PF that indicates 616 * whether DCBx is managed by firmware or host 617 * based agent (LLDPAD). Also, indicates what 618 * flavor of DCBx protocol (IEEE/CEE) is supported 619 * by the device. For now we're supporting IEEE 620 * mode only. 621 */ 622 u16 dcbx_cap; 623 624 struct i40e_filter_control_settings filter_settings; 625 626 struct ptp_clock *ptp_clock; 627 struct ptp_clock_info ptp_caps; 628 struct sk_buff *ptp_tx_skb; 629 unsigned long ptp_tx_start; 630 struct hwtstamp_config tstamp_config; 631 struct timespec64 ptp_prev_hw_time; 632 ktime_t ptp_reset_start; 633 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 634 u32 ptp_adj_mult; 635 u32 tx_hwtstamp_timeouts; 636 u32 tx_hwtstamp_skipped; 637 u32 rx_hwtstamp_cleared; 638 u32 latch_event_flags; 639 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 640 unsigned long latch_events[4]; 641 bool ptp_tx; 642 bool ptp_rx; 643 u16 rss_table_size; /* HW RSS table size */ 644 u32 max_bw; 645 u32 min_bw; 646 647 u32 ioremap_len; 648 u32 fd_inv; 649 u16 phy_led_val; 650 651 u16 override_q_count; 652 u16 last_sw_conf_flags; 653 u16 last_sw_conf_valid_flags; 654 /* List to keep previous DDP profiles to be rolled back in the future */ 655 struct list_head ddp_old_prof; 656 }; 657 658 /** 659 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 660 * @macaddr: the MAC Address as the base key 661 * 662 * Simply copies the address and returns it as a u64 for hashing 663 **/ 664 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 665 { 666 u64 key = 0; 667 668 ether_addr_copy((u8 *)&key, macaddr); 669 return key; 670 } 671 672 enum i40e_filter_state { 673 I40E_FILTER_INVALID = 0, /* Invalid state */ 674 I40E_FILTER_NEW, /* New, not sent to FW yet */ 675 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 676 I40E_FILTER_FAILED, /* Rejected by FW */ 677 I40E_FILTER_REMOVE, /* To be removed */ 678 /* There is no 'removed' state; the filter struct is freed */ 679 }; 680 struct i40e_mac_filter { 681 struct hlist_node hlist; 682 u8 macaddr[ETH_ALEN]; 683 #define I40E_VLAN_ANY -1 684 s16 vlan; 685 enum i40e_filter_state state; 686 }; 687 688 /* Wrapper structure to keep track of filters while we are preparing to send 689 * firmware commands. We cannot send firmware commands while holding a 690 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 691 * a separate structure, which will track the state change and update the real 692 * filter while under lock. We can't simply hold the filters in a separate 693 * list, as this opens a window for a race condition when adding new MAC 694 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 695 */ 696 struct i40e_new_mac_filter { 697 struct hlist_node hlist; 698 struct i40e_mac_filter *f; 699 700 /* Track future changes to state separately */ 701 enum i40e_filter_state state; 702 }; 703 704 struct i40e_veb { 705 struct i40e_pf *pf; 706 u16 idx; 707 u16 veb_idx; /* index of VEB parent */ 708 u16 seid; 709 u16 uplink_seid; 710 u16 stats_idx; /* index of VEB parent */ 711 u8 enabled_tc; 712 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 713 u16 flags; 714 u16 bw_limit; 715 u8 bw_max_quanta; 716 bool is_abs_credits; 717 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 718 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 719 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 720 struct kobject *kobj; 721 bool stat_offsets_loaded; 722 struct i40e_eth_stats stats; 723 struct i40e_eth_stats stats_offsets; 724 struct i40e_veb_tc_stats tc_stats; 725 struct i40e_veb_tc_stats tc_stats_offsets; 726 }; 727 728 /* struct that defines a VSI, associated with a dev */ 729 struct i40e_vsi { 730 struct net_device *netdev; 731 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 732 bool netdev_registered; 733 bool stat_offsets_loaded; 734 735 u32 current_netdev_flags; 736 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 737 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 738 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 739 unsigned long flags; 740 741 /* Per VSI lock to protect elements/hash (MAC filter) */ 742 spinlock_t mac_filter_hash_lock; 743 /* Fixed size hash table with 2^8 buckets for MAC filters */ 744 DECLARE_HASHTABLE(mac_filter_hash, 8); 745 bool has_vlan_filter; 746 747 /* VSI stats */ 748 struct rtnl_link_stats64 net_stats; 749 struct rtnl_link_stats64 net_stats_offsets; 750 struct i40e_eth_stats eth_stats; 751 struct i40e_eth_stats eth_stats_offsets; 752 u32 tx_restart; 753 u32 tx_busy; 754 u64 tx_linearize; 755 u64 tx_force_wb; 756 u32 rx_buf_failed; 757 u32 rx_page_failed; 758 759 /* These are containers of ring pointers, allocated at run-time */ 760 struct i40e_ring **rx_rings; 761 struct i40e_ring **tx_rings; 762 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 763 764 u32 active_filters; 765 u32 promisc_threshold; 766 767 u16 work_limit; 768 u16 int_rate_limit; /* value in usecs */ 769 770 u16 rss_table_size; /* HW RSS table size */ 771 u16 rss_size; /* Allocated RSS queues */ 772 u8 *rss_hkey_user; /* User configured hash keys */ 773 u8 *rss_lut_user; /* User configured lookup table entries */ 774 775 776 u16 max_frame; 777 u16 rx_buf_len; 778 779 struct bpf_prog *xdp_prog; 780 781 /* List of q_vectors allocated to this VSI */ 782 struct i40e_q_vector **q_vectors; 783 int num_q_vectors; 784 int base_vector; 785 bool irqs_ready; 786 787 u16 seid; /* HW index of this VSI (absolute index) */ 788 u16 id; /* VSI number */ 789 u16 uplink_seid; 790 791 u16 base_queue; /* vsi's first queue in hw array */ 792 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 793 u16 req_queue_pairs; /* User requested queue pairs */ 794 u16 num_queue_pairs; /* Used tx and rx pairs */ 795 u16 num_tx_desc; 796 u16 num_rx_desc; 797 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 798 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 799 800 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 801 struct i40e_tc_configuration tc_config; 802 struct i40e_aqc_vsi_properties_data info; 803 804 /* VSI BW limit (absolute across all TCs) */ 805 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 806 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 807 808 /* Relative TC credits across VSIs */ 809 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 810 /* TC BW limit credits within VSI */ 811 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 812 /* TC BW limit max quanta within VSI */ 813 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 814 815 struct i40e_pf *back; /* Backreference to associated PF */ 816 u16 idx; /* index in pf->vsi[] */ 817 u16 veb_idx; /* index of VEB parent */ 818 struct kobject *kobj; /* sysfs object */ 819 bool current_isup; /* Sync 'link up' logging */ 820 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 821 822 /* channel specific fields */ 823 u16 cnt_q_avail; /* num of queues available for channel usage */ 824 u16 orig_rss_size; 825 u16 current_rss_size; 826 bool reconfig_rss; 827 828 u16 next_base_queue; /* next queue to be used for channel setup */ 829 830 struct list_head ch_list; 831 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 832 833 /* macvlan fields */ 834 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */ 835 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */ 836 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS); 837 struct list_head macvlan_list; 838 int macvlan_cnt; 839 840 void *priv; /* client driver data reference. */ 841 842 /* VSI specific handlers */ 843 irqreturn_t (*irq_handler)(int irq, void *data); 844 845 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 846 } ____cacheline_internodealigned_in_smp; 847 848 struct i40e_netdev_priv { 849 struct i40e_vsi *vsi; 850 }; 851 852 /* struct that defines an interrupt vector */ 853 struct i40e_q_vector { 854 struct i40e_vsi *vsi; 855 856 u16 v_idx; /* index in the vsi->q_vector array. */ 857 u16 reg_idx; /* register index of the interrupt */ 858 859 struct napi_struct napi; 860 861 struct i40e_ring_container rx; 862 struct i40e_ring_container tx; 863 864 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 865 u8 num_ringpairs; /* total number of ring pairs in vector */ 866 867 cpumask_t affinity_mask; 868 struct irq_affinity_notify affinity_notify; 869 870 struct rcu_head rcu; /* to avoid race with update stats on free */ 871 char name[I40E_INT_NAME_STR_LEN]; 872 bool arm_wb_state; 873 } ____cacheline_internodealigned_in_smp; 874 875 /* lan device */ 876 struct i40e_device { 877 struct list_head list; 878 struct i40e_pf *pf; 879 }; 880 881 /** 882 * i40e_nvm_version_str - format the NVM version strings 883 * @hw: ptr to the hardware info 884 **/ 885 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 886 { 887 static char buf[32]; 888 u32 full_ver; 889 890 full_ver = hw->nvm.oem_ver; 891 892 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 893 u8 gen, snap; 894 u16 release; 895 896 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 897 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 898 I40E_OEM_SNAP_SHIFT); 899 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 900 901 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 902 } else { 903 u8 ver, patch; 904 u16 build; 905 906 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 907 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 908 I40E_OEM_VER_BUILD_MASK); 909 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 910 911 snprintf(buf, sizeof(buf), 912 "%x.%02x 0x%x %d.%d.%d", 913 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 914 I40E_NVM_VERSION_HI_SHIFT, 915 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 916 I40E_NVM_VERSION_LO_SHIFT, 917 hw->nvm.eetrack, ver, build, patch); 918 } 919 920 return buf; 921 } 922 923 /** 924 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 925 * @netdev: the corresponding netdev 926 * 927 * Return the PF struct for the given netdev 928 **/ 929 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 930 { 931 struct i40e_netdev_priv *np = netdev_priv(netdev); 932 struct i40e_vsi *vsi = np->vsi; 933 934 return vsi->back; 935 } 936 937 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 938 irqreturn_t (*irq_handler)(int, void *)) 939 { 940 vsi->irq_handler = irq_handler; 941 } 942 943 /** 944 * i40e_get_fd_cnt_all - get the total FD filter space available 945 * @pf: pointer to the PF struct 946 **/ 947 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 948 { 949 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 950 } 951 952 /** 953 * i40e_read_fd_input_set - reads value of flow director input set register 954 * @pf: pointer to the PF struct 955 * @addr: register addr 956 * 957 * This function reads value of flow director input set register 958 * specified by 'addr' (which is specific to flow-type) 959 **/ 960 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 961 { 962 u64 val; 963 964 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 965 val <<= 32; 966 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 967 968 return val; 969 } 970 971 /** 972 * i40e_write_fd_input_set - writes value into flow director input set register 973 * @pf: pointer to the PF struct 974 * @addr: register addr 975 * @val: value to be written 976 * 977 * This function writes specified value to the register specified by 'addr'. 978 * This register is input set register based on flow-type. 979 **/ 980 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 981 u16 addr, u64 val) 982 { 983 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 984 (u32)(val >> 32)); 985 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 986 (u32)(val & 0xFFFFFFFFULL)); 987 } 988 989 /* needed by i40e_ethtool.c */ 990 int i40e_up(struct i40e_vsi *vsi); 991 void i40e_down(struct i40e_vsi *vsi); 992 extern const char i40e_driver_name[]; 993 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 994 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 995 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 996 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 997 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 998 u16 rss_table_size, u16 rss_size); 999 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 1000 /** 1001 * i40e_find_vsi_by_type - Find and return Flow Director VSI 1002 * @pf: PF to search for VSI 1003 * @type: Value indicating type of VSI we are looking for 1004 **/ 1005 static inline struct i40e_vsi * 1006 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 1007 { 1008 int i; 1009 1010 for (i = 0; i < pf->num_alloc_vsi; i++) { 1011 struct i40e_vsi *vsi = pf->vsi[i]; 1012 1013 if (vsi && vsi->type == type) 1014 return vsi; 1015 } 1016 1017 return NULL; 1018 } 1019 void i40e_update_stats(struct i40e_vsi *vsi); 1020 void i40e_update_veb_stats(struct i40e_veb *veb); 1021 void i40e_update_eth_stats(struct i40e_vsi *vsi); 1022 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 1023 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1024 bool printconfig); 1025 1026 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1027 struct i40e_fdir_filter *input, bool add); 1028 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1029 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1030 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1031 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1032 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1033 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1034 void i40e_set_ethtool_ops(struct net_device *netdev); 1035 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1036 const u8 *macaddr, s16 vlan); 1037 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1038 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1039 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1040 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1041 u16 uplink, u32 param1); 1042 int i40e_vsi_release(struct i40e_vsi *vsi); 1043 void i40e_service_event_schedule(struct i40e_pf *pf); 1044 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1045 u8 *msg, u16 len); 1046 1047 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1048 bool enable); 1049 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1050 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1051 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1052 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1053 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1054 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1055 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1056 u16 downlink_seid, u8 enabled_tc); 1057 void i40e_veb_release(struct i40e_veb *veb); 1058 1059 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1060 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1061 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1062 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1063 void i40e_pf_reset_stats(struct i40e_pf *pf); 1064 #ifdef CONFIG_DEBUG_FS 1065 void i40e_dbg_pf_init(struct i40e_pf *pf); 1066 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1067 void i40e_dbg_init(void); 1068 void i40e_dbg_exit(void); 1069 #else 1070 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1071 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1072 static inline void i40e_dbg_init(void) {} 1073 static inline void i40e_dbg_exit(void) {} 1074 #endif /* CONFIG_DEBUG_FS*/ 1075 /* needed by client drivers */ 1076 int i40e_lan_add_device(struct i40e_pf *pf); 1077 int i40e_lan_del_device(struct i40e_pf *pf); 1078 void i40e_client_subtask(struct i40e_pf *pf); 1079 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1080 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1081 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1082 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1083 void i40e_client_update_msix_info(struct i40e_pf *pf); 1084 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1085 /** 1086 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1087 * @vsi: pointer to a vsi 1088 * @vector: enable a particular Hw Interrupt vector, without base_vector 1089 **/ 1090 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1091 { 1092 struct i40e_pf *pf = vsi->back; 1093 struct i40e_hw *hw = &pf->hw; 1094 u32 val; 1095 1096 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1097 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1098 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1099 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1100 /* skip the flush */ 1101 } 1102 1103 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1104 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1105 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1106 int i40e_open(struct net_device *netdev); 1107 int i40e_close(struct net_device *netdev); 1108 int i40e_vsi_open(struct i40e_vsi *vsi); 1109 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1110 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1111 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1112 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1113 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1114 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1115 const u8 *macaddr); 1116 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1117 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1118 int i40e_count_filters(struct i40e_vsi *vsi); 1119 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1120 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1121 #ifdef CONFIG_I40E_DCB 1122 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1123 struct i40e_dcbx_config *old_cfg, 1124 struct i40e_dcbx_config *new_cfg); 1125 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1126 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1127 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1128 struct i40e_dcbx_config *old_cfg, 1129 struct i40e_dcbx_config *new_cfg); 1130 #endif /* CONFIG_I40E_DCB */ 1131 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1132 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1133 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1134 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1135 void i40e_ptp_set_increment(struct i40e_pf *pf); 1136 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1137 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1138 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1139 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1140 void i40e_ptp_init(struct i40e_pf *pf); 1141 void i40e_ptp_stop(struct i40e_pf *pf); 1142 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1143 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); 1144 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); 1145 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1146 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1147 1148 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1149 1150 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1151 { 1152 return !!READ_ONCE(vsi->xdp_prog); 1153 } 1154 1155 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1156 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1157 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1158 struct i40e_cloud_filter *filter, 1159 bool add); 1160 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1161 struct i40e_cloud_filter *filter, 1162 bool add); 1163 #endif /* _I40E_H_ */ 1164