1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <net/tcp.h> 8 #include <net/udp.h> 9 #include <linux/types.h> 10 #include <linux/errno.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/aer.h> 14 #include <linux/netdevice.h> 15 #include <linux/ioport.h> 16 #include <linux/iommu.h> 17 #include <linux/slab.h> 18 #include <linux/list.h> 19 #include <linux/hashtable.h> 20 #include <linux/string.h> 21 #include <linux/in.h> 22 #include <linux/ip.h> 23 #include <linux/sctp.h> 24 #include <linux/pkt_sched.h> 25 #include <linux/ipv6.h> 26 #include <net/checksum.h> 27 #include <net/ip6_checksum.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/if_bridge.h> 31 #include <linux/clocksource.h> 32 #include <linux/net_tstamp.h> 33 #include <linux/ptp_clock_kernel.h> 34 #include <net/pkt_cls.h> 35 #include <net/tc_act/tc_gact.h> 36 #include <net/tc_act/tc_mirred.h> 37 #include <net/xdp_sock.h> 38 #include "i40e_type.h" 39 #include "i40e_prototype.h" 40 #include "i40e_client.h" 41 #include <linux/avf/virtchnl.h> 42 #include "i40e_virtchnl_pf.h" 43 #include "i40e_txrx.h" 44 #include "i40e_dcb.h" 45 46 /* Useful i40e defaults */ 47 #define I40E_MAX_VEB 16 48 49 #define I40E_MAX_NUM_DESCRIPTORS 4096 50 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 51 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 52 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 53 #define I40E_MIN_NUM_DESCRIPTORS 64 54 #define I40E_MIN_MSIX 2 55 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 56 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 57 /* max 16 qps */ 58 #define i40e_default_queues_per_vmdq(pf) \ 59 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 60 #define I40E_DEFAULT_QUEUES_PER_VF 4 61 #define I40E_MAX_VF_QUEUES 16 62 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */ 63 #define i40e_pf_get_max_q_per_tc(pf) \ 64 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 65 #define I40E_FDIR_RING 0 66 #define I40E_FDIR_RING_COUNT 32 67 #define I40E_MAX_AQ_BUF_SIZE 4096 68 #define I40E_AQ_LEN 256 69 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 70 #define I40E_MAX_USER_PRIORITY 8 71 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 72 #define I40E_DEFAULT_MSG_ENABLE 4 73 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 74 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 75 76 #define I40E_NVM_VERSION_LO_SHIFT 0 77 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 78 #define I40E_NVM_VERSION_HI_SHIFT 12 79 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 80 #define I40E_OEM_VER_BUILD_MASK 0xffff 81 #define I40E_OEM_VER_PATCH_MASK 0xff 82 #define I40E_OEM_VER_BUILD_SHIFT 8 83 #define I40E_OEM_VER_SHIFT 24 84 #define I40E_PHY_DEBUG_ALL \ 85 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 86 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 87 88 #define I40E_OEM_EETRACK_ID 0xffffffff 89 #define I40E_OEM_GEN_SHIFT 24 90 #define I40E_OEM_SNAP_MASK 0x00ff0000 91 #define I40E_OEM_SNAP_SHIFT 16 92 #define I40E_OEM_RELEASE_MASK 0x0000ffff 93 94 /* The values in here are decimal coded as hex as is the case in the NVM map*/ 95 #define I40E_CURRENT_NVM_VERSION_HI 0x2 96 #define I40E_CURRENT_NVM_VERSION_LO 0x40 97 98 #define I40E_RX_DESC(R, i) \ 99 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) 100 #define I40E_TX_DESC(R, i) \ 101 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 102 #define I40E_TX_CTXTDESC(R, i) \ 103 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 104 #define I40E_TX_FDIRDESC(R, i) \ 105 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 106 107 /* default to trying for four seconds */ 108 #define I40E_TRY_LINK_TIMEOUT (4 * HZ) 109 110 /* BW rate limiting */ 111 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 112 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 113 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 114 115 /* driver state flags */ 116 enum i40e_state_t { 117 __I40E_TESTING, 118 __I40E_CONFIG_BUSY, 119 __I40E_CONFIG_DONE, 120 __I40E_DOWN, 121 __I40E_SERVICE_SCHED, 122 __I40E_ADMINQ_EVENT_PENDING, 123 __I40E_MDD_EVENT_PENDING, 124 __I40E_VFLR_EVENT_PENDING, 125 __I40E_RESET_RECOVERY_PENDING, 126 __I40E_TIMEOUT_RECOVERY_PENDING, 127 __I40E_MISC_IRQ_REQUESTED, 128 __I40E_RESET_INTR_RECEIVED, 129 __I40E_REINIT_REQUESTED, 130 __I40E_PF_RESET_REQUESTED, 131 __I40E_CORE_RESET_REQUESTED, 132 __I40E_GLOBAL_RESET_REQUESTED, 133 __I40E_EMP_RESET_REQUESTED, 134 __I40E_EMP_RESET_INTR_RECEIVED, 135 __I40E_SUSPENDED, 136 __I40E_PTP_TX_IN_PROGRESS, 137 __I40E_BAD_EEPROM, 138 __I40E_DOWN_REQUESTED, 139 __I40E_FD_FLUSH_REQUESTED, 140 __I40E_FD_ATR_AUTO_DISABLED, 141 __I40E_FD_SB_AUTO_DISABLED, 142 __I40E_RESET_FAILED, 143 __I40E_PORT_SUSPENDED, 144 __I40E_VF_DISABLE, 145 __I40E_MACVLAN_SYNC_PENDING, 146 __I40E_UDP_FILTER_SYNC_PENDING, 147 __I40E_TEMP_LINK_POLLING, 148 __I40E_CLIENT_SERVICE_REQUESTED, 149 __I40E_CLIENT_L2_CHANGE, 150 __I40E_CLIENT_RESET, 151 __I40E_VIRTCHNL_OP_PENDING, 152 __I40E_RECOVERY_MODE, 153 /* This must be last as it determines the size of the BITMAP */ 154 __I40E_STATE_SIZE__, 155 }; 156 157 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 158 159 /* VSI state flags */ 160 enum i40e_vsi_state_t { 161 __I40E_VSI_DOWN, 162 __I40E_VSI_NEEDS_RESTART, 163 __I40E_VSI_SYNCING_FILTERS, 164 __I40E_VSI_OVERFLOW_PROMISC, 165 __I40E_VSI_REINIT_REQUESTED, 166 __I40E_VSI_DOWN_REQUESTED, 167 /* This must be last as it determines the size of the BITMAP */ 168 __I40E_VSI_STATE_SIZE__, 169 }; 170 171 enum i40e_interrupt_policy { 172 I40E_INTERRUPT_BEST_CASE, 173 I40E_INTERRUPT_MEDIUM, 174 I40E_INTERRUPT_LOWEST 175 }; 176 177 struct i40e_lump_tracking { 178 u16 num_entries; 179 u16 search_hint; 180 u16 list[0]; 181 #define I40E_PILE_VALID_BIT 0x8000 182 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 183 }; 184 185 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 186 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 187 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 188 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 189 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 190 191 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 192 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 193 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 194 195 enum i40e_fd_stat_idx { 196 I40E_FD_STAT_ATR, 197 I40E_FD_STAT_SB, 198 I40E_FD_STAT_ATR_TUNNEL, 199 I40E_FD_STAT_PF_COUNT 200 }; 201 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 202 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 203 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 204 #define I40E_FD_SB_STAT_IDX(pf_id) \ 205 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 206 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 207 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 208 209 /* The following structure contains the data parsed from the user-defined 210 * field of the ethtool_rx_flow_spec structure. 211 */ 212 struct i40e_rx_flow_userdef { 213 bool flex_filter; 214 u16 flex_word; 215 u16 flex_offset; 216 }; 217 218 struct i40e_fdir_filter { 219 struct hlist_node fdir_node; 220 /* filter ipnut set */ 221 u8 flow_type; 222 u8 ip4_proto; 223 /* TX packet view of src and dst */ 224 __be32 dst_ip; 225 __be32 src_ip; 226 __be16 src_port; 227 __be16 dst_port; 228 __be32 sctp_v_tag; 229 230 /* Flexible data to match within the packet payload */ 231 __be16 flex_word; 232 u16 flex_offset; 233 bool flex_filter; 234 235 /* filter control */ 236 u16 q_index; 237 u8 flex_off; 238 u8 pctype; 239 u16 dest_vsi; 240 u8 dest_ctl; 241 u8 fd_status; 242 u16 cnt_index; 243 u32 fd_id; 244 }; 245 246 #define I40E_CLOUD_FIELD_OMAC 0x01 247 #define I40E_CLOUD_FIELD_IMAC 0x02 248 #define I40E_CLOUD_FIELD_IVLAN 0x04 249 #define I40E_CLOUD_FIELD_TEN_ID 0x08 250 #define I40E_CLOUD_FIELD_IIP 0x10 251 252 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 253 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 254 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 255 I40E_CLOUD_FIELD_IVLAN) 256 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 257 I40E_CLOUD_FIELD_TEN_ID) 258 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 259 I40E_CLOUD_FIELD_IMAC | \ 260 I40E_CLOUD_FIELD_TEN_ID) 261 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 262 I40E_CLOUD_FIELD_IVLAN | \ 263 I40E_CLOUD_FIELD_TEN_ID) 264 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 265 266 struct i40e_cloud_filter { 267 struct hlist_node cloud_node; 268 unsigned long cookie; 269 /* cloud filter input set follows */ 270 u8 dst_mac[ETH_ALEN]; 271 u8 src_mac[ETH_ALEN]; 272 __be16 vlan_id; 273 u16 seid; /* filter control */ 274 __be16 dst_port; 275 __be16 src_port; 276 u32 tenant_id; 277 union { 278 struct { 279 struct in_addr dst_ip; 280 struct in_addr src_ip; 281 } v4; 282 struct { 283 struct in6_addr dst_ip6; 284 struct in6_addr src_ip6; 285 } v6; 286 } ip; 287 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 288 #define src_ipv6 ip.v6.src_ip6.s6_addr32 289 #define dst_ipv4 ip.v4.dst_ip.s_addr 290 #define src_ipv4 ip.v4.src_ip.s_addr 291 u16 n_proto; /* Ethernet Protocol */ 292 u8 ip_proto; /* IPPROTO value */ 293 u8 flags; 294 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 295 u8 tunnel_type; 296 }; 297 298 #define I40E_DCB_PRIO_TYPE_STRICT 0 299 #define I40E_DCB_PRIO_TYPE_ETS 1 300 #define I40E_DCB_STRICT_PRIO_CREDITS 127 301 /* DCB per TC information data structure */ 302 struct i40e_tc_info { 303 u16 qoffset; /* Queue offset from base queue */ 304 u16 qcount; /* Total Queues */ 305 u8 netdev_tc; /* Netdev TC index if netdev associated */ 306 }; 307 308 /* TC configuration data structure */ 309 struct i40e_tc_configuration { 310 u8 numtc; /* Total number of enabled TCs */ 311 u8 enabled_tc; /* TC map */ 312 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 313 }; 314 315 #define I40E_UDP_PORT_INDEX_UNUSED 255 316 struct i40e_udp_port_config { 317 /* AdminQ command interface expects port number in Host byte order */ 318 u16 port; 319 u8 type; 320 u8 filter_index; 321 }; 322 323 #define I40_DDP_FLASH_REGION 100 324 #define I40E_PROFILE_INFO_SIZE 48 325 #define I40E_MAX_PROFILE_NUM 16 326 #define I40E_PROFILE_LIST_SIZE \ 327 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4) 328 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/" 329 #define I40E_DDP_PROFILE_NAME_MAX 64 330 331 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size, 332 bool is_add); 333 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash); 334 335 struct i40e_ddp_profile_list { 336 u32 p_count; 337 struct i40e_profile_info p_info[0]; 338 }; 339 340 struct i40e_ddp_old_profile_list { 341 struct list_head list; 342 size_t old_ddp_size; 343 u8 old_ddp_buf[0]; 344 }; 345 346 /* macros related to FLX_PIT */ 347 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 348 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 349 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 350 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 351 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 352 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 353 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 354 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 355 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 356 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 357 I40E_FLEX_SET_FSIZE(fsize) | \ 358 I40E_FLEX_SET_SRC_WORD(src)) 359 360 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \ 361 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \ 362 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 363 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \ 364 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \ 365 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 366 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \ 367 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \ 368 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 369 370 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 371 372 /* macros related to GLQF_ORT */ 373 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 374 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 375 I40E_GLQF_ORT_PIT_INDX_MASK) 376 377 #define I40E_ORT_SET_COUNT(count) (((count) << \ 378 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 379 I40E_GLQF_ORT_FIELD_CNT_MASK) 380 381 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 382 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 383 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 384 385 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 386 I40E_ORT_SET_COUNT(count) | \ 387 I40E_ORT_SET_PAYLOAD(payload)) 388 389 #define I40E_L3_GLQF_ORT_IDX 34 390 #define I40E_L4_GLQF_ORT_IDX 35 391 392 /* Flex PIT register index */ 393 #define I40E_FLEX_PIT_IDX_START_L2 0 394 #define I40E_FLEX_PIT_IDX_START_L3 3 395 #define I40E_FLEX_PIT_IDX_START_L4 6 396 397 #define I40E_FLEX_PIT_TABLE_SIZE 3 398 399 #define I40E_FLEX_DEST_UNUSED 63 400 401 #define I40E_FLEX_INDEX_ENTRIES 8 402 403 /* Flex MASK to disable all flexible entries */ 404 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 405 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 406 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 407 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 408 409 struct i40e_flex_pit { 410 struct list_head list; 411 u16 src_offset; 412 u8 pit_index; 413 }; 414 415 struct i40e_channel { 416 struct list_head list; 417 bool initialized; 418 u8 type; 419 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 420 u16 stat_counter_idx; 421 u16 base_queue; 422 u16 num_queue_pairs; /* Requested by user */ 423 u16 seid; 424 425 u8 enabled_tc; 426 struct i40e_aqc_vsi_properties_data info; 427 428 u64 max_tx_rate; 429 430 /* track this channel belongs to which VSI */ 431 struct i40e_vsi *parent_vsi; 432 }; 433 434 /* struct that defines the Ethernet device */ 435 struct i40e_pf { 436 struct pci_dev *pdev; 437 struct i40e_hw hw; 438 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 439 struct msix_entry *msix_entries; 440 bool fc_autoneg_status; 441 442 u16 eeprom_version; 443 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 444 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 445 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 446 u16 num_req_vfs; /* num VFs requested for this PF */ 447 u16 num_vf_qps; /* num queue pairs per VF */ 448 u16 num_lan_qps; /* num lan queues this PF has set up */ 449 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 450 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 451 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 452 int iwarp_base_vector; 453 int queues_left; /* queues left unclaimed */ 454 u16 alloc_rss_size; /* allocated RSS queues */ 455 u16 rss_size_max; /* HW defined max RSS queues */ 456 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 457 u16 num_alloc_vsi; /* num VSIs this driver supports */ 458 u8 atr_sample_rate; 459 bool wol_en; 460 461 struct hlist_head fdir_filter_list; 462 u16 fdir_pf_active_filters; 463 unsigned long fd_flush_timestamp; 464 u32 fd_flush_cnt; 465 u32 fd_add_err; 466 u32 fd_atr_cnt; 467 468 /* Book-keeping of side-band filter count per flow-type. 469 * This is used to detect and handle input set changes for 470 * respective flow-type. 471 */ 472 u16 fd_tcp4_filter_cnt; 473 u16 fd_udp4_filter_cnt; 474 u16 fd_sctp4_filter_cnt; 475 u16 fd_ip4_filter_cnt; 476 477 /* Flexible filter table values that need to be programmed into 478 * hardware, which expects L3 and L4 to be programmed separately. We 479 * need to ensure that the values are in ascended order and don't have 480 * duplicates, so we track each L3 and L4 values in separate lists. 481 */ 482 struct list_head l3_flex_pit_list; 483 struct list_head l4_flex_pit_list; 484 485 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 486 u16 pending_udp_bitmap; 487 488 struct hlist_head cloud_filter_list; 489 u16 num_cloud_filters; 490 491 enum i40e_interrupt_policy int_policy; 492 u16 rx_itr_default; 493 u16 tx_itr_default; 494 u32 msg_enable; 495 char int_name[I40E_INT_NAME_STR_LEN]; 496 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 497 unsigned long service_timer_period; 498 unsigned long service_timer_previous; 499 struct timer_list service_timer; 500 struct work_struct service_task; 501 502 u32 hw_features; 503 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 504 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 505 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 506 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 507 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 508 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 509 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 510 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 511 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 512 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 513 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 514 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 515 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12) 516 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 517 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 518 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 519 #define I40E_HW_STOP_FW_LLDP BIT(16) 520 #define I40E_HW_PORT_ID_VALID BIT(17) 521 #define I40E_HW_RESTART_AUTONEG BIT(18) 522 523 u32 flags; 524 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 525 #define I40E_FLAG_MSI_ENABLED BIT(1) 526 #define I40E_FLAG_MSIX_ENABLED BIT(2) 527 #define I40E_FLAG_RSS_ENABLED BIT(3) 528 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 529 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 530 #define I40E_FLAG_DCB_CAPABLE BIT(6) 531 #define I40E_FLAG_DCB_ENABLED BIT(7) 532 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 533 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 534 #define I40E_FLAG_MFP_ENABLED BIT(10) 535 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 536 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 537 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 538 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 539 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 540 #define I40E_FLAG_LEGACY_RX BIT(16) 541 #define I40E_FLAG_PTP BIT(17) 542 #define I40E_FLAG_IWARP_ENABLED BIT(18) 543 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 544 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 545 #define I40E_FLAG_TC_MQPRIO BIT(21) 546 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 547 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 548 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 549 #define I40E_FLAG_RS_FEC BIT(25) 550 #define I40E_FLAG_BASE_R_FEC BIT(26) 551 552 struct i40e_client_instance *cinst; 553 bool stat_offsets_loaded; 554 struct i40e_hw_port_stats stats; 555 struct i40e_hw_port_stats stats_offsets; 556 u32 tx_timeout_count; 557 u32 tx_timeout_recovery_level; 558 unsigned long tx_timeout_last_recovery; 559 u32 tx_sluggish_count; 560 u32 hw_csum_rx_error; 561 u32 led_status; 562 u16 corer_count; /* Core reset count */ 563 u16 globr_count; /* Global reset count */ 564 u16 empr_count; /* EMP reset count */ 565 u16 pfr_count; /* PF reset count */ 566 u16 sw_int_count; /* SW interrupt count */ 567 568 struct mutex switch_mutex; 569 u16 lan_vsi; /* our default LAN VSI */ 570 u16 lan_veb; /* initial relay, if exists */ 571 #define I40E_NO_VEB 0xffff 572 #define I40E_NO_VSI 0xffff 573 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 574 struct i40e_vsi **vsi; 575 struct i40e_veb *veb[I40E_MAX_VEB]; 576 577 struct i40e_lump_tracking *qp_pile; 578 struct i40e_lump_tracking *irq_pile; 579 580 /* switch config info */ 581 u16 pf_seid; 582 u16 main_vsi_seid; 583 u16 mac_seid; 584 struct kobject *switch_kobj; 585 #ifdef CONFIG_DEBUG_FS 586 struct dentry *i40e_dbg_pf; 587 #endif /* CONFIG_DEBUG_FS */ 588 bool cur_promisc; 589 590 u16 instance; /* A unique number per i40e_pf instance in the system */ 591 592 /* sr-iov config info */ 593 struct i40e_vf *vf; 594 int num_alloc_vfs; /* actual number of VFs allocated */ 595 u32 vf_aq_requests; 596 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 597 598 /* DCBx/DCBNL capability for PF that indicates 599 * whether DCBx is managed by firmware or host 600 * based agent (LLDPAD). Also, indicates what 601 * flavor of DCBx protocol (IEEE/CEE) is supported 602 * by the device. For now we're supporting IEEE 603 * mode only. 604 */ 605 u16 dcbx_cap; 606 607 struct i40e_filter_control_settings filter_settings; 608 609 struct ptp_clock *ptp_clock; 610 struct ptp_clock_info ptp_caps; 611 struct sk_buff *ptp_tx_skb; 612 unsigned long ptp_tx_start; 613 struct hwtstamp_config tstamp_config; 614 struct timespec64 ptp_prev_hw_time; 615 ktime_t ptp_reset_start; 616 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 617 u32 ptp_adj_mult; 618 u32 tx_hwtstamp_timeouts; 619 u32 tx_hwtstamp_skipped; 620 u32 rx_hwtstamp_cleared; 621 u32 latch_event_flags; 622 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 623 unsigned long latch_events[4]; 624 bool ptp_tx; 625 bool ptp_rx; 626 u16 rss_table_size; /* HW RSS table size */ 627 u32 max_bw; 628 u32 min_bw; 629 630 u32 ioremap_len; 631 u32 fd_inv; 632 u16 phy_led_val; 633 634 u16 override_q_count; 635 u16 last_sw_conf_flags; 636 u16 last_sw_conf_valid_flags; 637 /* List to keep previous DDP profiles to be rolled back in the future */ 638 struct list_head ddp_old_prof; 639 }; 640 641 /** 642 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 643 * @macaddr: the MAC Address as the base key 644 * 645 * Simply copies the address and returns it as a u64 for hashing 646 **/ 647 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 648 { 649 u64 key = 0; 650 651 ether_addr_copy((u8 *)&key, macaddr); 652 return key; 653 } 654 655 enum i40e_filter_state { 656 I40E_FILTER_INVALID = 0, /* Invalid state */ 657 I40E_FILTER_NEW, /* New, not sent to FW yet */ 658 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 659 I40E_FILTER_FAILED, /* Rejected by FW */ 660 I40E_FILTER_REMOVE, /* To be removed */ 661 /* There is no 'removed' state; the filter struct is freed */ 662 }; 663 struct i40e_mac_filter { 664 struct hlist_node hlist; 665 u8 macaddr[ETH_ALEN]; 666 #define I40E_VLAN_ANY -1 667 s16 vlan; 668 enum i40e_filter_state state; 669 }; 670 671 /* Wrapper structure to keep track of filters while we are preparing to send 672 * firmware commands. We cannot send firmware commands while holding a 673 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 674 * a separate structure, which will track the state change and update the real 675 * filter while under lock. We can't simply hold the filters in a separate 676 * list, as this opens a window for a race condition when adding new MAC 677 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 678 */ 679 struct i40e_new_mac_filter { 680 struct hlist_node hlist; 681 struct i40e_mac_filter *f; 682 683 /* Track future changes to state separately */ 684 enum i40e_filter_state state; 685 }; 686 687 struct i40e_veb { 688 struct i40e_pf *pf; 689 u16 idx; 690 u16 veb_idx; /* index of VEB parent */ 691 u16 seid; 692 u16 uplink_seid; 693 u16 stats_idx; /* index of VEB parent */ 694 u8 enabled_tc; 695 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 696 u16 flags; 697 u16 bw_limit; 698 u8 bw_max_quanta; 699 bool is_abs_credits; 700 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 701 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 702 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 703 struct kobject *kobj; 704 bool stat_offsets_loaded; 705 struct i40e_eth_stats stats; 706 struct i40e_eth_stats stats_offsets; 707 struct i40e_veb_tc_stats tc_stats; 708 struct i40e_veb_tc_stats tc_stats_offsets; 709 }; 710 711 /* struct that defines a VSI, associated with a dev */ 712 struct i40e_vsi { 713 struct net_device *netdev; 714 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 715 bool netdev_registered; 716 bool stat_offsets_loaded; 717 718 u32 current_netdev_flags; 719 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 720 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 721 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 722 unsigned long flags; 723 724 /* Per VSI lock to protect elements/hash (MAC filter) */ 725 spinlock_t mac_filter_hash_lock; 726 /* Fixed size hash table with 2^8 buckets for MAC filters */ 727 DECLARE_HASHTABLE(mac_filter_hash, 8); 728 bool has_vlan_filter; 729 730 /* VSI stats */ 731 struct rtnl_link_stats64 net_stats; 732 struct rtnl_link_stats64 net_stats_offsets; 733 struct i40e_eth_stats eth_stats; 734 struct i40e_eth_stats eth_stats_offsets; 735 u32 tx_restart; 736 u32 tx_busy; 737 u64 tx_linearize; 738 u64 tx_force_wb; 739 u32 rx_buf_failed; 740 u32 rx_page_failed; 741 742 /* These are containers of ring pointers, allocated at run-time */ 743 struct i40e_ring **rx_rings; 744 struct i40e_ring **tx_rings; 745 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 746 747 u32 active_filters; 748 u32 promisc_threshold; 749 750 u16 work_limit; 751 u16 int_rate_limit; /* value in usecs */ 752 753 u16 rss_table_size; /* HW RSS table size */ 754 u16 rss_size; /* Allocated RSS queues */ 755 u8 *rss_hkey_user; /* User configured hash keys */ 756 u8 *rss_lut_user; /* User configured lookup table entries */ 757 758 759 u16 max_frame; 760 u16 rx_buf_len; 761 762 struct bpf_prog *xdp_prog; 763 764 /* List of q_vectors allocated to this VSI */ 765 struct i40e_q_vector **q_vectors; 766 int num_q_vectors; 767 int base_vector; 768 bool irqs_ready; 769 770 u16 seid; /* HW index of this VSI (absolute index) */ 771 u16 id; /* VSI number */ 772 u16 uplink_seid; 773 774 u16 base_queue; /* vsi's first queue in hw array */ 775 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 776 u16 req_queue_pairs; /* User requested queue pairs */ 777 u16 num_queue_pairs; /* Used tx and rx pairs */ 778 u16 num_desc; 779 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 780 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 781 782 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 783 struct i40e_tc_configuration tc_config; 784 struct i40e_aqc_vsi_properties_data info; 785 786 /* VSI BW limit (absolute across all TCs) */ 787 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 788 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 789 790 /* Relative TC credits across VSIs */ 791 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 792 /* TC BW limit credits within VSI */ 793 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 794 /* TC BW limit max quanta within VSI */ 795 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 796 797 struct i40e_pf *back; /* Backreference to associated PF */ 798 u16 idx; /* index in pf->vsi[] */ 799 u16 veb_idx; /* index of VEB parent */ 800 struct kobject *kobj; /* sysfs object */ 801 bool current_isup; /* Sync 'link up' logging */ 802 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 803 804 /* channel specific fields */ 805 u16 cnt_q_avail; /* num of queues available for channel usage */ 806 u16 orig_rss_size; 807 u16 current_rss_size; 808 bool reconfig_rss; 809 810 u16 next_base_queue; /* next queue to be used for channel setup */ 811 812 struct list_head ch_list; 813 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 814 815 void *priv; /* client driver data reference. */ 816 817 /* VSI specific handlers */ 818 irqreturn_t (*irq_handler)(int irq, void *data); 819 820 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 821 } ____cacheline_internodealigned_in_smp; 822 823 struct i40e_netdev_priv { 824 struct i40e_vsi *vsi; 825 }; 826 827 /* struct that defines an interrupt vector */ 828 struct i40e_q_vector { 829 struct i40e_vsi *vsi; 830 831 u16 v_idx; /* index in the vsi->q_vector array. */ 832 u16 reg_idx; /* register index of the interrupt */ 833 834 struct napi_struct napi; 835 836 struct i40e_ring_container rx; 837 struct i40e_ring_container tx; 838 839 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 840 u8 num_ringpairs; /* total number of ring pairs in vector */ 841 842 cpumask_t affinity_mask; 843 struct irq_affinity_notify affinity_notify; 844 845 struct rcu_head rcu; /* to avoid race with update stats on free */ 846 char name[I40E_INT_NAME_STR_LEN]; 847 bool arm_wb_state; 848 } ____cacheline_internodealigned_in_smp; 849 850 /* lan device */ 851 struct i40e_device { 852 struct list_head list; 853 struct i40e_pf *pf; 854 }; 855 856 /** 857 * i40e_nvm_version_str - format the NVM version strings 858 * @hw: ptr to the hardware info 859 **/ 860 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 861 { 862 static char buf[32]; 863 u32 full_ver; 864 865 full_ver = hw->nvm.oem_ver; 866 867 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 868 u8 gen, snap; 869 u16 release; 870 871 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 872 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 873 I40E_OEM_SNAP_SHIFT); 874 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 875 876 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 877 } else { 878 u8 ver, patch; 879 u16 build; 880 881 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 882 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 883 I40E_OEM_VER_BUILD_MASK); 884 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 885 886 snprintf(buf, sizeof(buf), 887 "%x.%02x 0x%x %d.%d.%d", 888 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 889 I40E_NVM_VERSION_HI_SHIFT, 890 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 891 I40E_NVM_VERSION_LO_SHIFT, 892 hw->nvm.eetrack, ver, build, patch); 893 } 894 895 return buf; 896 } 897 898 /** 899 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 900 * @netdev: the corresponding netdev 901 * 902 * Return the PF struct for the given netdev 903 **/ 904 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 905 { 906 struct i40e_netdev_priv *np = netdev_priv(netdev); 907 struct i40e_vsi *vsi = np->vsi; 908 909 return vsi->back; 910 } 911 912 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 913 irqreturn_t (*irq_handler)(int, void *)) 914 { 915 vsi->irq_handler = irq_handler; 916 } 917 918 /** 919 * i40e_get_fd_cnt_all - get the total FD filter space available 920 * @pf: pointer to the PF struct 921 **/ 922 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 923 { 924 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 925 } 926 927 /** 928 * i40e_read_fd_input_set - reads value of flow director input set register 929 * @pf: pointer to the PF struct 930 * @addr: register addr 931 * 932 * This function reads value of flow director input set register 933 * specified by 'addr' (which is specific to flow-type) 934 **/ 935 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 936 { 937 u64 val; 938 939 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 940 val <<= 32; 941 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 942 943 return val; 944 } 945 946 /** 947 * i40e_write_fd_input_set - writes value into flow director input set register 948 * @pf: pointer to the PF struct 949 * @addr: register addr 950 * @val: value to be written 951 * 952 * This function writes specified value to the register specified by 'addr'. 953 * This register is input set register based on flow-type. 954 **/ 955 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 956 u16 addr, u64 val) 957 { 958 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 959 (u32)(val >> 32)); 960 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 961 (u32)(val & 0xFFFFFFFFULL)); 962 } 963 964 /* needed by i40e_ethtool.c */ 965 int i40e_up(struct i40e_vsi *vsi); 966 void i40e_down(struct i40e_vsi *vsi); 967 extern const char i40e_driver_name[]; 968 extern const char i40e_driver_version_str[]; 969 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 970 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 971 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 972 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 973 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 974 u16 rss_table_size, u16 rss_size); 975 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 976 /** 977 * i40e_find_vsi_by_type - Find and return Flow Director VSI 978 * @pf: PF to search for VSI 979 * @type: Value indicating type of VSI we are looking for 980 **/ 981 static inline struct i40e_vsi * 982 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 983 { 984 int i; 985 986 for (i = 0; i < pf->num_alloc_vsi; i++) { 987 struct i40e_vsi *vsi = pf->vsi[i]; 988 989 if (vsi && vsi->type == type) 990 return vsi; 991 } 992 993 return NULL; 994 } 995 void i40e_update_stats(struct i40e_vsi *vsi); 996 void i40e_update_eth_stats(struct i40e_vsi *vsi); 997 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 998 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 999 bool printconfig); 1000 1001 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1002 struct i40e_fdir_filter *input, bool add); 1003 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1004 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1005 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1006 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1007 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1008 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1009 void i40e_set_ethtool_ops(struct net_device *netdev); 1010 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1011 const u8 *macaddr, s16 vlan); 1012 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1013 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1014 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1015 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1016 u16 uplink, u32 param1); 1017 int i40e_vsi_release(struct i40e_vsi *vsi); 1018 void i40e_service_event_schedule(struct i40e_pf *pf); 1019 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1020 u8 *msg, u16 len); 1021 1022 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1023 bool enable); 1024 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1025 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1026 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1027 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1028 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1029 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1030 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1031 u16 downlink_seid, u8 enabled_tc); 1032 void i40e_veb_release(struct i40e_veb *veb); 1033 1034 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1035 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1036 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1037 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1038 void i40e_pf_reset_stats(struct i40e_pf *pf); 1039 #ifdef CONFIG_DEBUG_FS 1040 void i40e_dbg_pf_init(struct i40e_pf *pf); 1041 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1042 void i40e_dbg_init(void); 1043 void i40e_dbg_exit(void); 1044 #else 1045 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1046 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1047 static inline void i40e_dbg_init(void) {} 1048 static inline void i40e_dbg_exit(void) {} 1049 #endif /* CONFIG_DEBUG_FS*/ 1050 /* needed by client drivers */ 1051 int i40e_lan_add_device(struct i40e_pf *pf); 1052 int i40e_lan_del_device(struct i40e_pf *pf); 1053 void i40e_client_subtask(struct i40e_pf *pf); 1054 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1055 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1056 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1057 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1058 void i40e_client_update_msix_info(struct i40e_pf *pf); 1059 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1060 /** 1061 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1062 * @vsi: pointer to a vsi 1063 * @vector: enable a particular Hw Interrupt vector, without base_vector 1064 **/ 1065 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1066 { 1067 struct i40e_pf *pf = vsi->back; 1068 struct i40e_hw *hw = &pf->hw; 1069 u32 val; 1070 1071 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1072 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1073 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1074 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1075 /* skip the flush */ 1076 } 1077 1078 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1079 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1080 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1081 int i40e_open(struct net_device *netdev); 1082 int i40e_close(struct net_device *netdev); 1083 int i40e_vsi_open(struct i40e_vsi *vsi); 1084 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1085 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1086 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1087 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1088 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1089 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1090 const u8 *macaddr); 1091 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1092 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1093 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1094 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1095 #ifdef CONFIG_I40E_DCB 1096 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1097 struct i40e_dcbx_config *old_cfg, 1098 struct i40e_dcbx_config *new_cfg); 1099 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1100 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1101 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1102 struct i40e_dcbx_config *old_cfg, 1103 struct i40e_dcbx_config *new_cfg); 1104 #endif /* CONFIG_I40E_DCB */ 1105 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1106 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1107 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1108 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1109 void i40e_ptp_set_increment(struct i40e_pf *pf); 1110 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1111 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1112 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1113 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1114 void i40e_ptp_init(struct i40e_pf *pf); 1115 void i40e_ptp_stop(struct i40e_pf *pf); 1116 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1117 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); 1118 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); 1119 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1120 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1121 1122 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1123 1124 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1125 { 1126 return !!vsi->xdp_prog; 1127 } 1128 1129 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1130 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1131 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1132 struct i40e_cloud_filter *filter, 1133 bool add); 1134 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1135 struct i40e_cloud_filter *filter, 1136 bool add); 1137 #endif /* _I40E_H_ */ 1138