1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include "e1000.h" 30 31 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 32 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 33 u16 *data, bool read, bool page_set); 34 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 35 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 36 u16 *data, bool read); 37 38 /* Cable length tables */ 39 static const u16 e1000_m88_cable_length_table[] = { 40 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED 41 }; 42 43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 44 ARRAY_SIZE(e1000_m88_cable_length_table) 45 46 static const u16 e1000_igp_2_cable_length_table[] = { 47 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 48 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 49 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 50 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 51 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 52 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 53 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 54 124 55 }; 56 57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 58 ARRAY_SIZE(e1000_igp_2_cable_length_table) 59 60 /** 61 * e1000e_check_reset_block_generic - Check if PHY reset is blocked 62 * @hw: pointer to the HW structure 63 * 64 * Read the PHY management control register and check whether a PHY reset 65 * is blocked. If a reset is not blocked return 0, otherwise 66 * return E1000_BLK_PHY_RESET (12). 67 **/ 68 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) 69 { 70 u32 manc; 71 72 manc = er32(MANC); 73 74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; 75 } 76 77 /** 78 * e1000e_get_phy_id - Retrieve the PHY ID and revision 79 * @hw: pointer to the HW structure 80 * 81 * Reads the PHY registers and stores the PHY ID and possibly the PHY 82 * revision in the hardware structure. 83 **/ 84 s32 e1000e_get_phy_id(struct e1000_hw *hw) 85 { 86 struct e1000_phy_info *phy = &hw->phy; 87 s32 ret_val = 0; 88 u16 phy_id; 89 u16 retry_count = 0; 90 91 if (!phy->ops.read_reg) 92 return 0; 93 94 while (retry_count < 2) { 95 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); 96 if (ret_val) 97 return ret_val; 98 99 phy->id = (u32)(phy_id << 16); 100 usleep_range(20, 40); 101 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id); 102 if (ret_val) 103 return ret_val; 104 105 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 106 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 107 108 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 109 return 0; 110 111 retry_count++; 112 } 113 114 return 0; 115 } 116 117 /** 118 * e1000e_phy_reset_dsp - Reset PHY DSP 119 * @hw: pointer to the HW structure 120 * 121 * Reset the digital signal processor. 122 **/ 123 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) 124 { 125 s32 ret_val; 126 127 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 128 if (ret_val) 129 return ret_val; 130 131 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); 132 } 133 134 /** 135 * e1000e_read_phy_reg_mdic - Read MDI control register 136 * @hw: pointer to the HW structure 137 * @offset: register offset to be read 138 * @data: pointer to the read data 139 * 140 * Reads the MDI control register in the PHY at offset and stores the 141 * information read to data. 142 **/ 143 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 144 { 145 struct e1000_phy_info *phy = &hw->phy; 146 u32 i, mdic = 0; 147 148 if (offset > MAX_PHY_REG_ADDRESS) { 149 e_dbg("PHY Address %d is out of range\n", offset); 150 return -E1000_ERR_PARAM; 151 } 152 153 /* Set up Op-code, Phy Address, and register offset in the MDI 154 * Control register. The MAC will take care of interfacing with the 155 * PHY to retrieve the desired data. 156 */ 157 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 158 (phy->addr << E1000_MDIC_PHY_SHIFT) | 159 (E1000_MDIC_OP_READ)); 160 161 ew32(MDIC, mdic); 162 163 /* Poll the ready bit to see if the MDI read completed 164 * Increasing the time out as testing showed failures with 165 * the lower time out 166 */ 167 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 168 usleep_range(50, 100); 169 mdic = er32(MDIC); 170 if (mdic & E1000_MDIC_READY) 171 break; 172 } 173 if (!(mdic & E1000_MDIC_READY)) { 174 e_dbg("MDI Read did not complete\n"); 175 return -E1000_ERR_PHY; 176 } 177 if (mdic & E1000_MDIC_ERROR) { 178 e_dbg("MDI Error\n"); 179 return -E1000_ERR_PHY; 180 } 181 *data = (u16)mdic; 182 183 /* Allow some time after each MDIC transaction to avoid 184 * reading duplicate data in the next MDIC transaction. 185 */ 186 if (hw->mac.type == e1000_pch2lan) 187 usleep_range(100, 200); 188 189 return 0; 190 } 191 192 /** 193 * e1000e_write_phy_reg_mdic - Write MDI control register 194 * @hw: pointer to the HW structure 195 * @offset: register offset to write to 196 * @data: data to write to register at offset 197 * 198 * Writes data to MDI control register in the PHY at offset. 199 **/ 200 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 201 { 202 struct e1000_phy_info *phy = &hw->phy; 203 u32 i, mdic = 0; 204 205 if (offset > MAX_PHY_REG_ADDRESS) { 206 e_dbg("PHY Address %d is out of range\n", offset); 207 return -E1000_ERR_PARAM; 208 } 209 210 /* Set up Op-code, Phy Address, and register offset in the MDI 211 * Control register. The MAC will take care of interfacing with the 212 * PHY to retrieve the desired data. 213 */ 214 mdic = (((u32)data) | 215 (offset << E1000_MDIC_REG_SHIFT) | 216 (phy->addr << E1000_MDIC_PHY_SHIFT) | 217 (E1000_MDIC_OP_WRITE)); 218 219 ew32(MDIC, mdic); 220 221 /* Poll the ready bit to see if the MDI read completed 222 * Increasing the time out as testing showed failures with 223 * the lower time out 224 */ 225 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 226 usleep_range(50, 100); 227 mdic = er32(MDIC); 228 if (mdic & E1000_MDIC_READY) 229 break; 230 } 231 if (!(mdic & E1000_MDIC_READY)) { 232 e_dbg("MDI Write did not complete\n"); 233 return -E1000_ERR_PHY; 234 } 235 if (mdic & E1000_MDIC_ERROR) { 236 e_dbg("MDI Error\n"); 237 return -E1000_ERR_PHY; 238 } 239 240 /* Allow some time after each MDIC transaction to avoid 241 * reading duplicate data in the next MDIC transaction. 242 */ 243 if (hw->mac.type == e1000_pch2lan) 244 usleep_range(100, 200); 245 246 return 0; 247 } 248 249 /** 250 * e1000e_read_phy_reg_m88 - Read m88 PHY register 251 * @hw: pointer to the HW structure 252 * @offset: register offset to be read 253 * @data: pointer to the read data 254 * 255 * Acquires semaphore, if necessary, then reads the PHY register at offset 256 * and storing the retrieved information in data. Release any acquired 257 * semaphores before exiting. 258 **/ 259 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 260 { 261 s32 ret_val; 262 263 ret_val = hw->phy.ops.acquire(hw); 264 if (ret_val) 265 return ret_val; 266 267 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 268 data); 269 270 hw->phy.ops.release(hw); 271 272 return ret_val; 273 } 274 275 /** 276 * e1000e_write_phy_reg_m88 - Write m88 PHY register 277 * @hw: pointer to the HW structure 278 * @offset: register offset to write to 279 * @data: data to write at register offset 280 * 281 * Acquires semaphore, if necessary, then writes the data to PHY register 282 * at the offset. Release any acquired semaphores before exiting. 283 **/ 284 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 285 { 286 s32 ret_val; 287 288 ret_val = hw->phy.ops.acquire(hw); 289 if (ret_val) 290 return ret_val; 291 292 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 293 data); 294 295 hw->phy.ops.release(hw); 296 297 return ret_val; 298 } 299 300 /** 301 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 302 * @hw: pointer to the HW structure 303 * @page: page to set (shifted left when necessary) 304 * 305 * Sets PHY page required for PHY register access. Assumes semaphore is 306 * already acquired. Note, this function sets phy.addr to 1 so the caller 307 * must set it appropriately (if necessary) after this function returns. 308 **/ 309 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 310 { 311 e_dbg("Setting page 0x%x\n", page); 312 313 hw->phy.addr = 1; 314 315 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 316 } 317 318 /** 319 * __e1000e_read_phy_reg_igp - Read igp PHY register 320 * @hw: pointer to the HW structure 321 * @offset: register offset to be read 322 * @data: pointer to the read data 323 * @locked: semaphore has already been acquired or not 324 * 325 * Acquires semaphore, if necessary, then reads the PHY register at offset 326 * and stores the retrieved information in data. Release any acquired 327 * semaphores before exiting. 328 **/ 329 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 330 bool locked) 331 { 332 s32 ret_val = 0; 333 334 if (!locked) { 335 if (!hw->phy.ops.acquire) 336 return 0; 337 338 ret_val = hw->phy.ops.acquire(hw); 339 if (ret_val) 340 return ret_val; 341 } 342 343 if (offset > MAX_PHY_MULTI_PAGE_REG) 344 ret_val = e1000e_write_phy_reg_mdic(hw, 345 IGP01E1000_PHY_PAGE_SELECT, 346 (u16)offset); 347 if (!ret_val) 348 ret_val = e1000e_read_phy_reg_mdic(hw, 349 MAX_PHY_REG_ADDRESS & offset, 350 data); 351 if (!locked) 352 hw->phy.ops.release(hw); 353 354 return ret_val; 355 } 356 357 /** 358 * e1000e_read_phy_reg_igp - Read igp PHY register 359 * @hw: pointer to the HW structure 360 * @offset: register offset to be read 361 * @data: pointer to the read data 362 * 363 * Acquires semaphore then reads the PHY register at offset and stores the 364 * retrieved information in data. 365 * Release the acquired semaphore before exiting. 366 **/ 367 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 368 { 369 return __e1000e_read_phy_reg_igp(hw, offset, data, false); 370 } 371 372 /** 373 * e1000e_read_phy_reg_igp_locked - Read igp PHY register 374 * @hw: pointer to the HW structure 375 * @offset: register offset to be read 376 * @data: pointer to the read data 377 * 378 * Reads the PHY register at offset and stores the retrieved information 379 * in data. Assumes semaphore already acquired. 380 **/ 381 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 382 { 383 return __e1000e_read_phy_reg_igp(hw, offset, data, true); 384 } 385 386 /** 387 * e1000e_write_phy_reg_igp - Write igp PHY register 388 * @hw: pointer to the HW structure 389 * @offset: register offset to write to 390 * @data: data to write at register offset 391 * @locked: semaphore has already been acquired or not 392 * 393 * Acquires semaphore, if necessary, then writes the data to PHY register 394 * at the offset. Release any acquired semaphores before exiting. 395 **/ 396 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 397 bool locked) 398 { 399 s32 ret_val = 0; 400 401 if (!locked) { 402 if (!hw->phy.ops.acquire) 403 return 0; 404 405 ret_val = hw->phy.ops.acquire(hw); 406 if (ret_val) 407 return ret_val; 408 } 409 410 if (offset > MAX_PHY_MULTI_PAGE_REG) 411 ret_val = e1000e_write_phy_reg_mdic(hw, 412 IGP01E1000_PHY_PAGE_SELECT, 413 (u16)offset); 414 if (!ret_val) 415 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 416 offset, data); 417 if (!locked) 418 hw->phy.ops.release(hw); 419 420 return ret_val; 421 } 422 423 /** 424 * e1000e_write_phy_reg_igp - Write igp PHY register 425 * @hw: pointer to the HW structure 426 * @offset: register offset to write to 427 * @data: data to write at register offset 428 * 429 * Acquires semaphore then writes the data to PHY register 430 * at the offset. Release any acquired semaphores before exiting. 431 **/ 432 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 433 { 434 return __e1000e_write_phy_reg_igp(hw, offset, data, false); 435 } 436 437 /** 438 * e1000e_write_phy_reg_igp_locked - Write igp PHY register 439 * @hw: pointer to the HW structure 440 * @offset: register offset to write to 441 * @data: data to write at register offset 442 * 443 * Writes the data to PHY register at the offset. 444 * Assumes semaphore already acquired. 445 **/ 446 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 447 { 448 return __e1000e_write_phy_reg_igp(hw, offset, data, true); 449 } 450 451 /** 452 * __e1000_read_kmrn_reg - Read kumeran register 453 * @hw: pointer to the HW structure 454 * @offset: register offset to be read 455 * @data: pointer to the read data 456 * @locked: semaphore has already been acquired or not 457 * 458 * Acquires semaphore, if necessary. Then reads the PHY register at offset 459 * using the kumeran interface. The information retrieved is stored in data. 460 * Release any acquired semaphores before exiting. 461 **/ 462 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 463 bool locked) 464 { 465 u32 kmrnctrlsta; 466 467 if (!locked) { 468 s32 ret_val = 0; 469 470 if (!hw->phy.ops.acquire) 471 return 0; 472 473 ret_val = hw->phy.ops.acquire(hw); 474 if (ret_val) 475 return ret_val; 476 } 477 478 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 479 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 480 ew32(KMRNCTRLSTA, kmrnctrlsta); 481 e1e_flush(); 482 483 udelay(2); 484 485 kmrnctrlsta = er32(KMRNCTRLSTA); 486 *data = (u16)kmrnctrlsta; 487 488 if (!locked) 489 hw->phy.ops.release(hw); 490 491 return 0; 492 } 493 494 /** 495 * e1000e_read_kmrn_reg - Read kumeran register 496 * @hw: pointer to the HW structure 497 * @offset: register offset to be read 498 * @data: pointer to the read data 499 * 500 * Acquires semaphore then reads the PHY register at offset using the 501 * kumeran interface. The information retrieved is stored in data. 502 * Release the acquired semaphore before exiting. 503 **/ 504 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) 505 { 506 return __e1000_read_kmrn_reg(hw, offset, data, false); 507 } 508 509 /** 510 * e1000e_read_kmrn_reg_locked - Read kumeran register 511 * @hw: pointer to the HW structure 512 * @offset: register offset to be read 513 * @data: pointer to the read data 514 * 515 * Reads the PHY register at offset using the kumeran interface. The 516 * information retrieved is stored in data. 517 * Assumes semaphore already acquired. 518 **/ 519 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 520 { 521 return __e1000_read_kmrn_reg(hw, offset, data, true); 522 } 523 524 /** 525 * __e1000_write_kmrn_reg - Write kumeran register 526 * @hw: pointer to the HW structure 527 * @offset: register offset to write to 528 * @data: data to write at register offset 529 * @locked: semaphore has already been acquired or not 530 * 531 * Acquires semaphore, if necessary. Then write the data to PHY register 532 * at the offset using the kumeran interface. Release any acquired semaphores 533 * before exiting. 534 **/ 535 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 536 bool locked) 537 { 538 u32 kmrnctrlsta; 539 540 if (!locked) { 541 s32 ret_val = 0; 542 543 if (!hw->phy.ops.acquire) 544 return 0; 545 546 ret_val = hw->phy.ops.acquire(hw); 547 if (ret_val) 548 return ret_val; 549 } 550 551 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 552 E1000_KMRNCTRLSTA_OFFSET) | data; 553 ew32(KMRNCTRLSTA, kmrnctrlsta); 554 e1e_flush(); 555 556 udelay(2); 557 558 if (!locked) 559 hw->phy.ops.release(hw); 560 561 return 0; 562 } 563 564 /** 565 * e1000e_write_kmrn_reg - Write kumeran register 566 * @hw: pointer to the HW structure 567 * @offset: register offset to write to 568 * @data: data to write at register offset 569 * 570 * Acquires semaphore then writes the data to the PHY register at the offset 571 * using the kumeran interface. Release the acquired semaphore before exiting. 572 **/ 573 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) 574 { 575 return __e1000_write_kmrn_reg(hw, offset, data, false); 576 } 577 578 /** 579 * e1000e_write_kmrn_reg_locked - Write kumeran register 580 * @hw: pointer to the HW structure 581 * @offset: register offset to write to 582 * @data: data to write at register offset 583 * 584 * Write the data to PHY register at the offset using the kumeran interface. 585 * Assumes semaphore already acquired. 586 **/ 587 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 588 { 589 return __e1000_write_kmrn_reg(hw, offset, data, true); 590 } 591 592 /** 593 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 594 * @hw: pointer to the HW structure 595 * 596 * Sets up Master/slave mode 597 **/ 598 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 599 { 600 s32 ret_val; 601 u16 phy_data; 602 603 /* Resolve Master/Slave mode */ 604 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data); 605 if (ret_val) 606 return ret_val; 607 608 /* load defaults for future use */ 609 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ? 610 ((phy_data & CTL1000_AS_MASTER) ? 611 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto; 612 613 switch (hw->phy.ms_type) { 614 case e1000_ms_force_master: 615 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 616 break; 617 case e1000_ms_force_slave: 618 phy_data |= CTL1000_ENABLE_MASTER; 619 phy_data &= ~(CTL1000_AS_MASTER); 620 break; 621 case e1000_ms_auto: 622 phy_data &= ~CTL1000_ENABLE_MASTER; 623 /* fall-through */ 624 default: 625 break; 626 } 627 628 return e1e_wphy(hw, MII_CTRL1000, phy_data); 629 } 630 631 /** 632 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 633 * @hw: pointer to the HW structure 634 * 635 * Sets up Carrier-sense on Transmit and downshift values. 636 **/ 637 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 638 { 639 s32 ret_val; 640 u16 phy_data; 641 642 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 643 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); 644 if (ret_val) 645 return ret_val; 646 647 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 648 649 /* Enable downshift */ 650 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 651 652 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); 653 if (ret_val) 654 return ret_val; 655 656 /* Set MDI/MDIX mode */ 657 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data); 658 if (ret_val) 659 return ret_val; 660 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 661 /* Options: 662 * 0 - Auto (default) 663 * 1 - MDI mode 664 * 2 - MDI-X mode 665 */ 666 switch (hw->phy.mdix) { 667 case 1: 668 break; 669 case 2: 670 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; 671 break; 672 case 0: 673 default: 674 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; 675 break; 676 } 677 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data); 678 if (ret_val) 679 return ret_val; 680 681 return e1000_set_master_slave_mode(hw); 682 } 683 684 /** 685 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link 686 * @hw: pointer to the HW structure 687 * 688 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 689 * and downshift values are set also. 690 **/ 691 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) 692 { 693 struct e1000_phy_info *phy = &hw->phy; 694 s32 ret_val; 695 u16 phy_data; 696 697 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 698 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 699 if (ret_val) 700 return ret_val; 701 702 /* For BM PHY this bit is downshift enable */ 703 if (phy->type != e1000_phy_bm) 704 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 705 706 /* Options: 707 * MDI/MDI-X = 0 (default) 708 * 0 - Auto for all speeds 709 * 1 - MDI mode 710 * 2 - MDI-X mode 711 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 712 */ 713 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 714 715 switch (phy->mdix) { 716 case 1: 717 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 718 break; 719 case 2: 720 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 721 break; 722 case 3: 723 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 724 break; 725 case 0: 726 default: 727 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 728 break; 729 } 730 731 /* Options: 732 * disable_polarity_correction = 0 (default) 733 * Automatic Correction for Reversed Cable Polarity 734 * 0 - Disabled 735 * 1 - Enabled 736 */ 737 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 738 if (phy->disable_polarity_correction) 739 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 740 741 /* Enable downshift on BM (disabled by default) */ 742 if (phy->type == e1000_phy_bm) { 743 /* For 82574/82583, first disable then enable downshift */ 744 if (phy->id == BME1000_E_PHY_ID_R2) { 745 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 746 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 747 phy_data); 748 if (ret_val) 749 return ret_val; 750 /* Commit the changes. */ 751 ret_val = phy->ops.commit(hw); 752 if (ret_val) { 753 e_dbg("Error committing the PHY changes\n"); 754 return ret_val; 755 } 756 } 757 758 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 759 } 760 761 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 762 if (ret_val) 763 return ret_val; 764 765 if ((phy->type == e1000_phy_m88) && 766 (phy->revision < E1000_REVISION_4) && 767 (phy->id != BME1000_E_PHY_ID_R2)) { 768 /* Force TX_CLK in the Extended PHY Specific Control Register 769 * to 25MHz clock. 770 */ 771 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 772 if (ret_val) 773 return ret_val; 774 775 phy_data |= M88E1000_EPSCR_TX_CLK_25; 776 777 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) { 778 /* 82573L PHY - set the downshift counter to 5x. */ 779 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 780 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 781 } else { 782 /* Configure Master and Slave downshift values */ 783 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 784 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 785 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 786 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 787 } 788 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 789 if (ret_val) 790 return ret_val; 791 } 792 793 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 794 /* Set PHY page 0, register 29 to 0x0003 */ 795 ret_val = e1e_wphy(hw, 29, 0x0003); 796 if (ret_val) 797 return ret_val; 798 799 /* Set PHY page 0, register 30 to 0x0000 */ 800 ret_val = e1e_wphy(hw, 30, 0x0000); 801 if (ret_val) 802 return ret_val; 803 } 804 805 /* Commit the changes. */ 806 if (phy->ops.commit) { 807 ret_val = phy->ops.commit(hw); 808 if (ret_val) { 809 e_dbg("Error committing the PHY changes\n"); 810 return ret_val; 811 } 812 } 813 814 if (phy->type == e1000_phy_82578) { 815 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 816 if (ret_val) 817 return ret_val; 818 819 /* 82578 PHY - set the downshift count to 1x. */ 820 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 821 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 822 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 823 if (ret_val) 824 return ret_val; 825 } 826 827 return 0; 828 } 829 830 /** 831 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link 832 * @hw: pointer to the HW structure 833 * 834 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 835 * igp PHY's. 836 **/ 837 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) 838 { 839 struct e1000_phy_info *phy = &hw->phy; 840 s32 ret_val; 841 u16 data; 842 843 ret_val = e1000_phy_hw_reset(hw); 844 if (ret_val) { 845 e_dbg("Error resetting the PHY.\n"); 846 return ret_val; 847 } 848 849 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 850 * timeout issues when LFS is enabled. 851 */ 852 msleep(100); 853 854 /* disable lplu d0 during driver init */ 855 if (hw->phy.ops.set_d0_lplu_state) { 856 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 857 if (ret_val) { 858 e_dbg("Error Disabling LPLU D0\n"); 859 return ret_val; 860 } 861 } 862 /* Configure mdi-mdix settings */ 863 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); 864 if (ret_val) 865 return ret_val; 866 867 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 868 869 switch (phy->mdix) { 870 case 1: 871 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 872 break; 873 case 2: 874 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 875 break; 876 case 0: 877 default: 878 data |= IGP01E1000_PSCR_AUTO_MDIX; 879 break; 880 } 881 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); 882 if (ret_val) 883 return ret_val; 884 885 /* set auto-master slave resolution settings */ 886 if (hw->mac.autoneg) { 887 /* when autonegotiation advertisement is only 1000Mbps then we 888 * should disable SmartSpeed and enable Auto MasterSlave 889 * resolution as hardware default. 890 */ 891 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 892 /* Disable SmartSpeed */ 893 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 894 &data); 895 if (ret_val) 896 return ret_val; 897 898 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 899 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 900 data); 901 if (ret_val) 902 return ret_val; 903 904 /* Set auto Master/Slave resolution process */ 905 ret_val = e1e_rphy(hw, MII_CTRL1000, &data); 906 if (ret_val) 907 return ret_val; 908 909 data &= ~CTL1000_ENABLE_MASTER; 910 ret_val = e1e_wphy(hw, MII_CTRL1000, data); 911 if (ret_val) 912 return ret_val; 913 } 914 915 ret_val = e1000_set_master_slave_mode(hw); 916 } 917 918 return ret_val; 919 } 920 921 /** 922 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 923 * @hw: pointer to the HW structure 924 * 925 * Reads the MII auto-neg advertisement register and/or the 1000T control 926 * register and if the PHY is already setup for auto-negotiation, then 927 * return successful. Otherwise, setup advertisement and flow control to 928 * the appropriate values for the wanted auto-negotiation. 929 **/ 930 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 931 { 932 struct e1000_phy_info *phy = &hw->phy; 933 s32 ret_val; 934 u16 mii_autoneg_adv_reg; 935 u16 mii_1000t_ctrl_reg = 0; 936 937 phy->autoneg_advertised &= phy->autoneg_mask; 938 939 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 940 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg); 941 if (ret_val) 942 return ret_val; 943 944 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 945 /* Read the MII 1000Base-T Control Register (Address 9). */ 946 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg); 947 if (ret_val) 948 return ret_val; 949 } 950 951 /* Need to parse both autoneg_advertised and fc and set up 952 * the appropriate PHY registers. First we will parse for 953 * autoneg_advertised software override. Since we can advertise 954 * a plethora of combinations, we need to check each bit 955 * individually. 956 */ 957 958 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 959 * Advertisement Register (Address 4) and the 1000 mb speed bits in 960 * the 1000Base-T Control Register (Address 9). 961 */ 962 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL | 963 ADVERTISE_100HALF | 964 ADVERTISE_10FULL | ADVERTISE_10HALF); 965 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); 966 967 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 968 969 /* Do we want to advertise 10 Mb Half Duplex? */ 970 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 971 e_dbg("Advertise 10mb Half duplex\n"); 972 mii_autoneg_adv_reg |= ADVERTISE_10HALF; 973 } 974 975 /* Do we want to advertise 10 Mb Full Duplex? */ 976 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 977 e_dbg("Advertise 10mb Full duplex\n"); 978 mii_autoneg_adv_reg |= ADVERTISE_10FULL; 979 } 980 981 /* Do we want to advertise 100 Mb Half Duplex? */ 982 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 983 e_dbg("Advertise 100mb Half duplex\n"); 984 mii_autoneg_adv_reg |= ADVERTISE_100HALF; 985 } 986 987 /* Do we want to advertise 100 Mb Full Duplex? */ 988 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 989 e_dbg("Advertise 100mb Full duplex\n"); 990 mii_autoneg_adv_reg |= ADVERTISE_100FULL; 991 } 992 993 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 994 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 995 e_dbg("Advertise 1000mb Half duplex request denied!\n"); 996 997 /* Do we want to advertise 1000 Mb Full Duplex? */ 998 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 999 e_dbg("Advertise 1000mb Full duplex\n"); 1000 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL; 1001 } 1002 1003 /* Check for a software override of the flow control settings, and 1004 * setup the PHY advertisement registers accordingly. If 1005 * auto-negotiation is enabled, then software will have to set the 1006 * "PAUSE" bits to the correct value in the Auto-Negotiation 1007 * Advertisement Register (MII_ADVERTISE) and re-start auto- 1008 * negotiation. 1009 * 1010 * The possible values of the "fc" parameter are: 1011 * 0: Flow control is completely disabled 1012 * 1: Rx flow control is enabled (we can receive pause frames 1013 * but not send pause frames). 1014 * 2: Tx flow control is enabled (we can send pause frames 1015 * but we do not support receiving pause frames). 1016 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1017 * other: No software override. The flow control configuration 1018 * in the EEPROM is used. 1019 */ 1020 switch (hw->fc.current_mode) { 1021 case e1000_fc_none: 1022 /* Flow control (Rx & Tx) is completely disabled by a 1023 * software over-ride. 1024 */ 1025 mii_autoneg_adv_reg &= 1026 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); 1027 break; 1028 case e1000_fc_rx_pause: 1029 /* Rx Flow control is enabled, and Tx Flow control is 1030 * disabled, by a software over-ride. 1031 * 1032 * Since there really isn't a way to advertise that we are 1033 * capable of Rx Pause ONLY, we will advertise that we 1034 * support both symmetric and asymmetric Rx PAUSE. Later 1035 * (in e1000e_config_fc_after_link_up) we will disable the 1036 * hw's ability to send PAUSE frames. 1037 */ 1038 mii_autoneg_adv_reg |= 1039 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); 1040 break; 1041 case e1000_fc_tx_pause: 1042 /* Tx Flow control is enabled, and Rx Flow control is 1043 * disabled, by a software over-ride. 1044 */ 1045 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM; 1046 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP; 1047 break; 1048 case e1000_fc_full: 1049 /* Flow control (both Rx and Tx) is enabled by a software 1050 * over-ride. 1051 */ 1052 mii_autoneg_adv_reg |= 1053 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); 1054 break; 1055 default: 1056 e_dbg("Flow control param set incorrectly\n"); 1057 return -E1000_ERR_CONFIG; 1058 } 1059 1060 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 1061 if (ret_val) 1062 return ret_val; 1063 1064 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1065 1066 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1067 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg); 1068 1069 return ret_val; 1070 } 1071 1072 /** 1073 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1074 * @hw: pointer to the HW structure 1075 * 1076 * Performs initial bounds checking on autoneg advertisement parameter, then 1077 * configure to advertise the full capability. Setup the PHY to autoneg 1078 * and restart the negotiation process between the link partner. If 1079 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1080 **/ 1081 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1082 { 1083 struct e1000_phy_info *phy = &hw->phy; 1084 s32 ret_val; 1085 u16 phy_ctrl; 1086 1087 /* Perform some bounds checking on the autoneg advertisement 1088 * parameter. 1089 */ 1090 phy->autoneg_advertised &= phy->autoneg_mask; 1091 1092 /* If autoneg_advertised is zero, we assume it was not defaulted 1093 * by the calling code so we set to advertise full capability. 1094 */ 1095 if (!phy->autoneg_advertised) 1096 phy->autoneg_advertised = phy->autoneg_mask; 1097 1098 e_dbg("Reconfiguring auto-neg advertisement params\n"); 1099 ret_val = e1000_phy_setup_autoneg(hw); 1100 if (ret_val) { 1101 e_dbg("Error Setting up Auto-Negotiation\n"); 1102 return ret_val; 1103 } 1104 e_dbg("Restarting Auto-Neg\n"); 1105 1106 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1107 * the Auto Neg Restart bit in the PHY control register. 1108 */ 1109 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); 1110 if (ret_val) 1111 return ret_val; 1112 1113 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART); 1114 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); 1115 if (ret_val) 1116 return ret_val; 1117 1118 /* Does the user want to wait for Auto-Neg to complete here, or 1119 * check at a later time (for example, callback routine). 1120 */ 1121 if (phy->autoneg_wait_to_complete) { 1122 ret_val = e1000_wait_autoneg(hw); 1123 if (ret_val) { 1124 e_dbg("Error while waiting for autoneg to complete\n"); 1125 return ret_val; 1126 } 1127 } 1128 1129 hw->mac.get_link_status = true; 1130 1131 return ret_val; 1132 } 1133 1134 /** 1135 * e1000e_setup_copper_link - Configure copper link settings 1136 * @hw: pointer to the HW structure 1137 * 1138 * Calls the appropriate function to configure the link for auto-neg or forced 1139 * speed and duplex. Then we check for link, once link is established calls 1140 * to configure collision distance and flow control are called. If link is 1141 * not established, we return -E1000_ERR_PHY (-2). 1142 **/ 1143 s32 e1000e_setup_copper_link(struct e1000_hw *hw) 1144 { 1145 s32 ret_val; 1146 bool link; 1147 1148 if (hw->mac.autoneg) { 1149 /* Setup autoneg and flow control advertisement and perform 1150 * autonegotiation. 1151 */ 1152 ret_val = e1000_copper_link_autoneg(hw); 1153 if (ret_val) 1154 return ret_val; 1155 } else { 1156 /* PHY will be set to 10H, 10F, 100H or 100F 1157 * depending on user settings. 1158 */ 1159 e_dbg("Forcing Speed and Duplex\n"); 1160 ret_val = hw->phy.ops.force_speed_duplex(hw); 1161 if (ret_val) { 1162 e_dbg("Error Forcing Speed and Duplex\n"); 1163 return ret_val; 1164 } 1165 } 1166 1167 /* Check link status. Wait up to 100 microseconds for link to become 1168 * valid. 1169 */ 1170 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1171 &link); 1172 if (ret_val) 1173 return ret_val; 1174 1175 if (link) { 1176 e_dbg("Valid link established!!!\n"); 1177 hw->mac.ops.config_collision_dist(hw); 1178 ret_val = e1000e_config_fc_after_link_up(hw); 1179 } else { 1180 e_dbg("Unable to establish link!!!\n"); 1181 } 1182 1183 return ret_val; 1184 } 1185 1186 /** 1187 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1188 * @hw: pointer to the HW structure 1189 * 1190 * Calls the PHY setup function to force speed and duplex. Clears the 1191 * auto-crossover to force MDI manually. Waits for link and returns 1192 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1193 **/ 1194 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1195 { 1196 struct e1000_phy_info *phy = &hw->phy; 1197 s32 ret_val; 1198 u16 phy_data; 1199 bool link; 1200 1201 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); 1202 if (ret_val) 1203 return ret_val; 1204 1205 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 1206 1207 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); 1208 if (ret_val) 1209 return ret_val; 1210 1211 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1212 * forced whenever speed and duplex are forced. 1213 */ 1214 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1215 if (ret_val) 1216 return ret_val; 1217 1218 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1219 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1220 1221 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1222 if (ret_val) 1223 return ret_val; 1224 1225 e_dbg("IGP PSCR: %X\n", phy_data); 1226 1227 udelay(1); 1228 1229 if (phy->autoneg_wait_to_complete) { 1230 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1231 1232 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1233 100000, &link); 1234 if (ret_val) 1235 return ret_val; 1236 1237 if (!link) 1238 e_dbg("Link taking longer than expected.\n"); 1239 1240 /* Try once more */ 1241 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1242 100000, &link); 1243 } 1244 1245 return ret_val; 1246 } 1247 1248 /** 1249 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1250 * @hw: pointer to the HW structure 1251 * 1252 * Calls the PHY setup function to force speed and duplex. Clears the 1253 * auto-crossover to force MDI manually. Resets the PHY to commit the 1254 * changes. If time expires while waiting for link up, we reset the DSP. 1255 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1256 * successful completion, else return corresponding error code. 1257 **/ 1258 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1259 { 1260 struct e1000_phy_info *phy = &hw->phy; 1261 s32 ret_val; 1262 u16 phy_data; 1263 bool link; 1264 1265 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1266 * forced whenever speed and duplex are forced. 1267 */ 1268 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1269 if (ret_val) 1270 return ret_val; 1271 1272 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1273 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1274 if (ret_val) 1275 return ret_val; 1276 1277 e_dbg("M88E1000 PSCR: %X\n", phy_data); 1278 1279 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); 1280 if (ret_val) 1281 return ret_val; 1282 1283 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 1284 1285 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); 1286 if (ret_val) 1287 return ret_val; 1288 1289 /* Reset the phy to commit changes. */ 1290 if (hw->phy.ops.commit) { 1291 ret_val = hw->phy.ops.commit(hw); 1292 if (ret_val) 1293 return ret_val; 1294 } 1295 1296 if (phy->autoneg_wait_to_complete) { 1297 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1298 1299 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1300 100000, &link); 1301 if (ret_val) 1302 return ret_val; 1303 1304 if (!link) { 1305 if (hw->phy.type != e1000_phy_m88) { 1306 e_dbg("Link taking longer than expected.\n"); 1307 } else { 1308 /* We didn't get link. 1309 * Reset the DSP and cross our fingers. 1310 */ 1311 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 1312 0x001d); 1313 if (ret_val) 1314 return ret_val; 1315 ret_val = e1000e_phy_reset_dsp(hw); 1316 if (ret_val) 1317 return ret_val; 1318 } 1319 } 1320 1321 /* Try once more */ 1322 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1323 100000, &link); 1324 if (ret_val) 1325 return ret_val; 1326 } 1327 1328 if (hw->phy.type != e1000_phy_m88) 1329 return 0; 1330 1331 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1332 if (ret_val) 1333 return ret_val; 1334 1335 /* Resetting the phy means we need to re-force TX_CLK in the 1336 * Extended PHY Specific Control Register to 25MHz clock from 1337 * the reset value of 2.5MHz. 1338 */ 1339 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1340 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1341 if (ret_val) 1342 return ret_val; 1343 1344 /* In addition, we must re-enable CRS on Tx for both half and full 1345 * duplex. 1346 */ 1347 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1348 if (ret_val) 1349 return ret_val; 1350 1351 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1352 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1353 1354 return ret_val; 1355 } 1356 1357 /** 1358 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1359 * @hw: pointer to the HW structure 1360 * 1361 * Forces the speed and duplex settings of the PHY. 1362 * This is a function pointer entry point only called by 1363 * PHY setup routines. 1364 **/ 1365 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1366 { 1367 struct e1000_phy_info *phy = &hw->phy; 1368 s32 ret_val; 1369 u16 data; 1370 bool link; 1371 1372 ret_val = e1e_rphy(hw, MII_BMCR, &data); 1373 if (ret_val) 1374 return ret_val; 1375 1376 e1000e_phy_force_speed_duplex_setup(hw, &data); 1377 1378 ret_val = e1e_wphy(hw, MII_BMCR, data); 1379 if (ret_val) 1380 return ret_val; 1381 1382 /* Disable MDI-X support for 10/100 */ 1383 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 1384 if (ret_val) 1385 return ret_val; 1386 1387 data &= ~IFE_PMC_AUTO_MDIX; 1388 data &= ~IFE_PMC_FORCE_MDIX; 1389 1390 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); 1391 if (ret_val) 1392 return ret_val; 1393 1394 e_dbg("IFE PMC: %X\n", data); 1395 1396 udelay(1); 1397 1398 if (phy->autoneg_wait_to_complete) { 1399 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); 1400 1401 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1402 100000, &link); 1403 if (ret_val) 1404 return ret_val; 1405 1406 if (!link) 1407 e_dbg("Link taking longer than expected.\n"); 1408 1409 /* Try once more */ 1410 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1411 100000, &link); 1412 if (ret_val) 1413 return ret_val; 1414 } 1415 1416 return 0; 1417 } 1418 1419 /** 1420 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1421 * @hw: pointer to the HW structure 1422 * @phy_ctrl: pointer to current value of MII_BMCR 1423 * 1424 * Forces speed and duplex on the PHY by doing the following: disable flow 1425 * control, force speed/duplex on the MAC, disable auto speed detection, 1426 * disable auto-negotiation, configure duplex, configure speed, configure 1427 * the collision distance, write configuration to CTRL register. The 1428 * caller must write to the MII_BMCR register for these settings to 1429 * take affect. 1430 **/ 1431 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1432 { 1433 struct e1000_mac_info *mac = &hw->mac; 1434 u32 ctrl; 1435 1436 /* Turn off flow control when forcing speed/duplex */ 1437 hw->fc.current_mode = e1000_fc_none; 1438 1439 /* Force speed/duplex on the mac */ 1440 ctrl = er32(CTRL); 1441 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1442 ctrl &= ~E1000_CTRL_SPD_SEL; 1443 1444 /* Disable Auto Speed Detection */ 1445 ctrl &= ~E1000_CTRL_ASDE; 1446 1447 /* Disable autoneg on the phy */ 1448 *phy_ctrl &= ~BMCR_ANENABLE; 1449 1450 /* Forcing Full or Half Duplex? */ 1451 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1452 ctrl &= ~E1000_CTRL_FD; 1453 *phy_ctrl &= ~BMCR_FULLDPLX; 1454 e_dbg("Half Duplex\n"); 1455 } else { 1456 ctrl |= E1000_CTRL_FD; 1457 *phy_ctrl |= BMCR_FULLDPLX; 1458 e_dbg("Full Duplex\n"); 1459 } 1460 1461 /* Forcing 10mb or 100mb? */ 1462 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1463 ctrl |= E1000_CTRL_SPD_100; 1464 *phy_ctrl |= BMCR_SPEED100; 1465 *phy_ctrl &= ~BMCR_SPEED1000; 1466 e_dbg("Forcing 100mb\n"); 1467 } else { 1468 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1469 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100); 1470 e_dbg("Forcing 10mb\n"); 1471 } 1472 1473 hw->mac.ops.config_collision_dist(hw); 1474 1475 ew32(CTRL, ctrl); 1476 } 1477 1478 /** 1479 * e1000e_set_d3_lplu_state - Sets low power link up state for D3 1480 * @hw: pointer to the HW structure 1481 * @active: boolean used to enable/disable lplu 1482 * 1483 * Success returns 0, Failure returns 1 1484 * 1485 * The low power link up (lplu) state is set to the power management level D3 1486 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1487 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1488 * is used during Dx states where the power conservation is most important. 1489 * During driver activity, SmartSpeed should be enabled so performance is 1490 * maintained. 1491 **/ 1492 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1493 { 1494 struct e1000_phy_info *phy = &hw->phy; 1495 s32 ret_val; 1496 u16 data; 1497 1498 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1499 if (ret_val) 1500 return ret_val; 1501 1502 if (!active) { 1503 data &= ~IGP02E1000_PM_D3_LPLU; 1504 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1505 if (ret_val) 1506 return ret_val; 1507 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1508 * during Dx states where the power conservation is most 1509 * important. During driver activity we should enable 1510 * SmartSpeed, so performance is maintained. 1511 */ 1512 if (phy->smart_speed == e1000_smart_speed_on) { 1513 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1514 &data); 1515 if (ret_val) 1516 return ret_val; 1517 1518 data |= IGP01E1000_PSCFR_SMART_SPEED; 1519 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1520 data); 1521 if (ret_val) 1522 return ret_val; 1523 } else if (phy->smart_speed == e1000_smart_speed_off) { 1524 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1525 &data); 1526 if (ret_val) 1527 return ret_val; 1528 1529 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1530 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1531 data); 1532 if (ret_val) 1533 return ret_val; 1534 } 1535 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1536 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1537 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1538 data |= IGP02E1000_PM_D3_LPLU; 1539 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1540 if (ret_val) 1541 return ret_val; 1542 1543 /* When LPLU is enabled, we should disable SmartSpeed */ 1544 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 1545 if (ret_val) 1546 return ret_val; 1547 1548 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1549 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 1550 } 1551 1552 return ret_val; 1553 } 1554 1555 /** 1556 * e1000e_check_downshift - Checks whether a downshift in speed occurred 1557 * @hw: pointer to the HW structure 1558 * 1559 * Success returns 0, Failure returns 1 1560 * 1561 * A downshift is detected by querying the PHY link health. 1562 **/ 1563 s32 e1000e_check_downshift(struct e1000_hw *hw) 1564 { 1565 struct e1000_phy_info *phy = &hw->phy; 1566 s32 ret_val; 1567 u16 phy_data, offset, mask; 1568 1569 switch (phy->type) { 1570 case e1000_phy_m88: 1571 case e1000_phy_gg82563: 1572 case e1000_phy_bm: 1573 case e1000_phy_82578: 1574 offset = M88E1000_PHY_SPEC_STATUS; 1575 mask = M88E1000_PSSR_DOWNSHIFT; 1576 break; 1577 case e1000_phy_igp_2: 1578 case e1000_phy_igp_3: 1579 offset = IGP01E1000_PHY_LINK_HEALTH; 1580 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1581 break; 1582 default: 1583 /* speed downshift not supported */ 1584 phy->speed_downgraded = false; 1585 return 0; 1586 } 1587 1588 ret_val = e1e_rphy(hw, offset, &phy_data); 1589 1590 if (!ret_val) 1591 phy->speed_downgraded = !!(phy_data & mask); 1592 1593 return ret_val; 1594 } 1595 1596 /** 1597 * e1000_check_polarity_m88 - Checks the polarity. 1598 * @hw: pointer to the HW structure 1599 * 1600 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1601 * 1602 * Polarity is determined based on the PHY specific status register. 1603 **/ 1604 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1605 { 1606 struct e1000_phy_info *phy = &hw->phy; 1607 s32 ret_val; 1608 u16 data; 1609 1610 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); 1611 1612 if (!ret_val) 1613 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) 1614 ? e1000_rev_polarity_reversed 1615 : e1000_rev_polarity_normal); 1616 1617 return ret_val; 1618 } 1619 1620 /** 1621 * e1000_check_polarity_igp - Checks the polarity. 1622 * @hw: pointer to the HW structure 1623 * 1624 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1625 * 1626 * Polarity is determined based on the PHY port status register, and the 1627 * current speed (since there is no polarity at 100Mbps). 1628 **/ 1629 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1630 { 1631 struct e1000_phy_info *phy = &hw->phy; 1632 s32 ret_val; 1633 u16 data, offset, mask; 1634 1635 /* Polarity is determined based on the speed of 1636 * our connection. 1637 */ 1638 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1639 if (ret_val) 1640 return ret_val; 1641 1642 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1643 IGP01E1000_PSSR_SPEED_1000MBPS) { 1644 offset = IGP01E1000_PHY_PCS_INIT_REG; 1645 mask = IGP01E1000_PHY_POLARITY_MASK; 1646 } else { 1647 /* This really only applies to 10Mbps since 1648 * there is no polarity for 100Mbps (always 0). 1649 */ 1650 offset = IGP01E1000_PHY_PORT_STATUS; 1651 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1652 } 1653 1654 ret_val = e1e_rphy(hw, offset, &data); 1655 1656 if (!ret_val) 1657 phy->cable_polarity = ((data & mask) 1658 ? e1000_rev_polarity_reversed 1659 : e1000_rev_polarity_normal); 1660 1661 return ret_val; 1662 } 1663 1664 /** 1665 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1666 * @hw: pointer to the HW structure 1667 * 1668 * Polarity is determined on the polarity reversal feature being enabled. 1669 **/ 1670 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 1671 { 1672 struct e1000_phy_info *phy = &hw->phy; 1673 s32 ret_val; 1674 u16 phy_data, offset, mask; 1675 1676 /* Polarity is determined based on the reversal feature being enabled. 1677 */ 1678 if (phy->polarity_correction) { 1679 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1680 mask = IFE_PESC_POLARITY_REVERSED; 1681 } else { 1682 offset = IFE_PHY_SPECIAL_CONTROL; 1683 mask = IFE_PSC_FORCE_POLARITY; 1684 } 1685 1686 ret_val = e1e_rphy(hw, offset, &phy_data); 1687 1688 if (!ret_val) 1689 phy->cable_polarity = ((phy_data & mask) 1690 ? e1000_rev_polarity_reversed 1691 : e1000_rev_polarity_normal); 1692 1693 return ret_val; 1694 } 1695 1696 /** 1697 * e1000_wait_autoneg - Wait for auto-neg completion 1698 * @hw: pointer to the HW structure 1699 * 1700 * Waits for auto-negotiation to complete or for the auto-negotiation time 1701 * limit to expire, which ever happens first. 1702 **/ 1703 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 1704 { 1705 s32 ret_val = 0; 1706 u16 i, phy_status; 1707 1708 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1709 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1710 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); 1711 if (ret_val) 1712 break; 1713 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); 1714 if (ret_val) 1715 break; 1716 if (phy_status & BMSR_ANEGCOMPLETE) 1717 break; 1718 msleep(100); 1719 } 1720 1721 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1722 * has completed. 1723 */ 1724 return ret_val; 1725 } 1726 1727 /** 1728 * e1000e_phy_has_link_generic - Polls PHY for link 1729 * @hw: pointer to the HW structure 1730 * @iterations: number of times to poll for link 1731 * @usec_interval: delay between polling attempts 1732 * @success: pointer to whether polling was successful or not 1733 * 1734 * Polls the PHY status register for link, 'iterations' number of times. 1735 **/ 1736 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1737 u32 usec_interval, bool *success) 1738 { 1739 s32 ret_val = 0; 1740 u16 i, phy_status; 1741 1742 for (i = 0; i < iterations; i++) { 1743 /* Some PHYs require the MII_BMSR register to be read 1744 * twice due to the link bit being sticky. No harm doing 1745 * it across the board. 1746 */ 1747 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); 1748 if (ret_val) 1749 /* If the first read fails, another entity may have 1750 * ownership of the resources, wait and try again to 1751 * see if they have relinquished the resources yet. 1752 */ 1753 udelay(usec_interval); 1754 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); 1755 if (ret_val) 1756 break; 1757 if (phy_status & BMSR_LSTATUS) 1758 break; 1759 if (usec_interval >= 1000) 1760 mdelay(usec_interval / 1000); 1761 else 1762 udelay(usec_interval); 1763 } 1764 1765 *success = (i < iterations); 1766 1767 return ret_val; 1768 } 1769 1770 /** 1771 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY 1772 * @hw: pointer to the HW structure 1773 * 1774 * Reads the PHY specific status register to retrieve the cable length 1775 * information. The cable length is determined by averaging the minimum and 1776 * maximum values to get the "average" cable length. The m88 PHY has four 1777 * possible cable length values, which are: 1778 * Register Value Cable Length 1779 * 0 < 50 meters 1780 * 1 50 - 80 meters 1781 * 2 80 - 110 meters 1782 * 3 110 - 140 meters 1783 * 4 > 140 meters 1784 **/ 1785 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) 1786 { 1787 struct e1000_phy_info *phy = &hw->phy; 1788 s32 ret_val; 1789 u16 phy_data, index; 1790 1791 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1792 if (ret_val) 1793 return ret_val; 1794 1795 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1796 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 1797 1798 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 1799 return -E1000_ERR_PHY; 1800 1801 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1802 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1803 1804 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1805 1806 return 0; 1807 } 1808 1809 /** 1810 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1811 * @hw: pointer to the HW structure 1812 * 1813 * The automatic gain control (agc) normalizes the amplitude of the 1814 * received signal, adjusting for the attenuation produced by the 1815 * cable. By reading the AGC registers, which represent the 1816 * combination of coarse and fine gain value, the value can be put 1817 * into a lookup table to obtain the approximate cable length 1818 * for each channel. 1819 **/ 1820 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) 1821 { 1822 struct e1000_phy_info *phy = &hw->phy; 1823 s32 ret_val; 1824 u16 phy_data, i, agc_value = 0; 1825 u16 cur_agc_index, max_agc_index = 0; 1826 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1827 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1828 IGP02E1000_PHY_AGC_A, 1829 IGP02E1000_PHY_AGC_B, 1830 IGP02E1000_PHY_AGC_C, 1831 IGP02E1000_PHY_AGC_D 1832 }; 1833 1834 /* Read the AGC registers for all channels */ 1835 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1836 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); 1837 if (ret_val) 1838 return ret_val; 1839 1840 /* Getting bits 15:9, which represent the combination of 1841 * coarse and fine gain values. The result is a number 1842 * that can be put into the lookup table to obtain the 1843 * approximate cable length. 1844 */ 1845 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1846 IGP02E1000_AGC_LENGTH_MASK); 1847 1848 /* Array index bound check. */ 1849 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1850 (cur_agc_index == 0)) 1851 return -E1000_ERR_PHY; 1852 1853 /* Remove min & max AGC values from calculation. */ 1854 if (e1000_igp_2_cable_length_table[min_agc_index] > 1855 e1000_igp_2_cable_length_table[cur_agc_index]) 1856 min_agc_index = cur_agc_index; 1857 if (e1000_igp_2_cable_length_table[max_agc_index] < 1858 e1000_igp_2_cable_length_table[cur_agc_index]) 1859 max_agc_index = cur_agc_index; 1860 1861 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1862 } 1863 1864 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1865 e1000_igp_2_cable_length_table[max_agc_index]); 1866 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1867 1868 /* Calculate cable length with the error range of +/- 10 meters. */ 1869 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1870 (agc_value - IGP02E1000_AGC_RANGE) : 0); 1871 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1872 1873 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1874 1875 return 0; 1876 } 1877 1878 /** 1879 * e1000e_get_phy_info_m88 - Retrieve PHY information 1880 * @hw: pointer to the HW structure 1881 * 1882 * Valid for only copper links. Read the PHY status register (sticky read) 1883 * to verify that link is up. Read the PHY special control register to 1884 * determine the polarity and 10base-T extended distance. Read the PHY 1885 * special status register to determine MDI/MDIx and current speed. If 1886 * speed is 1000, then determine cable length, local and remote receiver. 1887 **/ 1888 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) 1889 { 1890 struct e1000_phy_info *phy = &hw->phy; 1891 s32 ret_val; 1892 u16 phy_data; 1893 bool link; 1894 1895 if (phy->media_type != e1000_media_type_copper) { 1896 e_dbg("Phy info is only valid for copper media\n"); 1897 return -E1000_ERR_CONFIG; 1898 } 1899 1900 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1901 if (ret_val) 1902 return ret_val; 1903 1904 if (!link) { 1905 e_dbg("Phy info is only valid if link is up\n"); 1906 return -E1000_ERR_CONFIG; 1907 } 1908 1909 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1910 if (ret_val) 1911 return ret_val; 1912 1913 phy->polarity_correction = !!(phy_data & 1914 M88E1000_PSCR_POLARITY_REVERSAL); 1915 1916 ret_val = e1000_check_polarity_m88(hw); 1917 if (ret_val) 1918 return ret_val; 1919 1920 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1921 if (ret_val) 1922 return ret_val; 1923 1924 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 1925 1926 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1927 ret_val = hw->phy.ops.get_cable_length(hw); 1928 if (ret_val) 1929 return ret_val; 1930 1931 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data); 1932 if (ret_val) 1933 return ret_val; 1934 1935 phy->local_rx = (phy_data & LPA_1000LOCALRXOK) 1936 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 1937 1938 phy->remote_rx = (phy_data & LPA_1000REMRXOK) 1939 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 1940 } else { 1941 /* Set values to "undefined" */ 1942 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1943 phy->local_rx = e1000_1000t_rx_status_undefined; 1944 phy->remote_rx = e1000_1000t_rx_status_undefined; 1945 } 1946 1947 return ret_val; 1948 } 1949 1950 /** 1951 * e1000e_get_phy_info_igp - Retrieve igp PHY information 1952 * @hw: pointer to the HW structure 1953 * 1954 * Read PHY status to determine if link is up. If link is up, then 1955 * set/determine 10base-T extended distance and polarity correction. Read 1956 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1957 * determine on the cable length, local and remote receiver. 1958 **/ 1959 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) 1960 { 1961 struct e1000_phy_info *phy = &hw->phy; 1962 s32 ret_val; 1963 u16 data; 1964 bool link; 1965 1966 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1967 if (ret_val) 1968 return ret_val; 1969 1970 if (!link) { 1971 e_dbg("Phy info is only valid if link is up\n"); 1972 return -E1000_ERR_CONFIG; 1973 } 1974 1975 phy->polarity_correction = true; 1976 1977 ret_val = e1000_check_polarity_igp(hw); 1978 if (ret_val) 1979 return ret_val; 1980 1981 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1982 if (ret_val) 1983 return ret_val; 1984 1985 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 1986 1987 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1988 IGP01E1000_PSSR_SPEED_1000MBPS) { 1989 ret_val = phy->ops.get_cable_length(hw); 1990 if (ret_val) 1991 return ret_val; 1992 1993 ret_val = e1e_rphy(hw, MII_STAT1000, &data); 1994 if (ret_val) 1995 return ret_val; 1996 1997 phy->local_rx = (data & LPA_1000LOCALRXOK) 1998 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 1999 2000 phy->remote_rx = (data & LPA_1000REMRXOK) 2001 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 2002 } else { 2003 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2004 phy->local_rx = e1000_1000t_rx_status_undefined; 2005 phy->remote_rx = e1000_1000t_rx_status_undefined; 2006 } 2007 2008 return ret_val; 2009 } 2010 2011 /** 2012 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2013 * @hw: pointer to the HW structure 2014 * 2015 * Populates "phy" structure with various feature states. 2016 **/ 2017 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2018 { 2019 struct e1000_phy_info *phy = &hw->phy; 2020 s32 ret_val; 2021 u16 data; 2022 bool link; 2023 2024 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 2025 if (ret_val) 2026 return ret_val; 2027 2028 if (!link) { 2029 e_dbg("Phy info is only valid if link is up\n"); 2030 return -E1000_ERR_CONFIG; 2031 } 2032 2033 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2034 if (ret_val) 2035 return ret_val; 2036 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2037 2038 if (phy->polarity_correction) { 2039 ret_val = e1000_check_polarity_ife(hw); 2040 if (ret_val) 2041 return ret_val; 2042 } else { 2043 /* Polarity is forced */ 2044 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) 2045 ? e1000_rev_polarity_reversed 2046 : e1000_rev_polarity_normal); 2047 } 2048 2049 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 2050 if (ret_val) 2051 return ret_val; 2052 2053 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2054 2055 /* The following parameters are undefined for 10/100 operation. */ 2056 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2057 phy->local_rx = e1000_1000t_rx_status_undefined; 2058 phy->remote_rx = e1000_1000t_rx_status_undefined; 2059 2060 return 0; 2061 } 2062 2063 /** 2064 * e1000e_phy_sw_reset - PHY software reset 2065 * @hw: pointer to the HW structure 2066 * 2067 * Does a software reset of the PHY by reading the PHY control register and 2068 * setting/write the control register reset bit to the PHY. 2069 **/ 2070 s32 e1000e_phy_sw_reset(struct e1000_hw *hw) 2071 { 2072 s32 ret_val; 2073 u16 phy_ctrl; 2074 2075 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); 2076 if (ret_val) 2077 return ret_val; 2078 2079 phy_ctrl |= BMCR_RESET; 2080 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); 2081 if (ret_val) 2082 return ret_val; 2083 2084 udelay(1); 2085 2086 return ret_val; 2087 } 2088 2089 /** 2090 * e1000e_phy_hw_reset_generic - PHY hardware reset 2091 * @hw: pointer to the HW structure 2092 * 2093 * Verify the reset block is not blocking us from resetting. Acquire 2094 * semaphore (if necessary) and read/set/write the device control reset 2095 * bit in the PHY. Wait the appropriate delay time for the device to 2096 * reset and release the semaphore (if necessary). 2097 **/ 2098 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) 2099 { 2100 struct e1000_phy_info *phy = &hw->phy; 2101 s32 ret_val; 2102 u32 ctrl; 2103 2104 if (phy->ops.check_reset_block) { 2105 ret_val = phy->ops.check_reset_block(hw); 2106 if (ret_val) 2107 return 0; 2108 } 2109 2110 ret_val = phy->ops.acquire(hw); 2111 if (ret_val) 2112 return ret_val; 2113 2114 ctrl = er32(CTRL); 2115 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 2116 e1e_flush(); 2117 2118 udelay(phy->reset_delay_us); 2119 2120 ew32(CTRL, ctrl); 2121 e1e_flush(); 2122 2123 usleep_range(150, 300); 2124 2125 phy->ops.release(hw); 2126 2127 return phy->ops.get_cfg_done(hw); 2128 } 2129 2130 /** 2131 * e1000e_get_cfg_done_generic - Generic configuration done 2132 * @hw: pointer to the HW structure 2133 * 2134 * Generic function to wait 10 milli-seconds for configuration to complete 2135 * and return success. 2136 **/ 2137 s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw) 2138 { 2139 mdelay(10); 2140 2141 return 0; 2142 } 2143 2144 /** 2145 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY 2146 * @hw: pointer to the HW structure 2147 * 2148 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2149 **/ 2150 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) 2151 { 2152 e_dbg("Running IGP 3 PHY init script\n"); 2153 2154 /* PHY init IGP 3 */ 2155 /* Enable rise/fall, 10-mode work in class-A */ 2156 e1e_wphy(hw, 0x2F5B, 0x9018); 2157 /* Remove all caps from Replica path filter */ 2158 e1e_wphy(hw, 0x2F52, 0x0000); 2159 /* Bias trimming for ADC, AFE and Driver (Default) */ 2160 e1e_wphy(hw, 0x2FB1, 0x8B24); 2161 /* Increase Hybrid poly bias */ 2162 e1e_wphy(hw, 0x2FB2, 0xF8F0); 2163 /* Add 4% to Tx amplitude in Gig mode */ 2164 e1e_wphy(hw, 0x2010, 0x10B0); 2165 /* Disable trimming (TTT) */ 2166 e1e_wphy(hw, 0x2011, 0x0000); 2167 /* Poly DC correction to 94.6% + 2% for all channels */ 2168 e1e_wphy(hw, 0x20DD, 0x249A); 2169 /* ABS DC correction to 95.9% */ 2170 e1e_wphy(hw, 0x20DE, 0x00D3); 2171 /* BG temp curve trim */ 2172 e1e_wphy(hw, 0x28B4, 0x04CE); 2173 /* Increasing ADC OPAMP stage 1 currents to max */ 2174 e1e_wphy(hw, 0x2F70, 0x29E4); 2175 /* Force 1000 ( required for enabling PHY regs configuration) */ 2176 e1e_wphy(hw, 0x0000, 0x0140); 2177 /* Set upd_freq to 6 */ 2178 e1e_wphy(hw, 0x1F30, 0x1606); 2179 /* Disable NPDFE */ 2180 e1e_wphy(hw, 0x1F31, 0xB814); 2181 /* Disable adaptive fixed FFE (Default) */ 2182 e1e_wphy(hw, 0x1F35, 0x002A); 2183 /* Enable FFE hysteresis */ 2184 e1e_wphy(hw, 0x1F3E, 0x0067); 2185 /* Fixed FFE for short cable lengths */ 2186 e1e_wphy(hw, 0x1F54, 0x0065); 2187 /* Fixed FFE for medium cable lengths */ 2188 e1e_wphy(hw, 0x1F55, 0x002A); 2189 /* Fixed FFE for long cable lengths */ 2190 e1e_wphy(hw, 0x1F56, 0x002A); 2191 /* Enable Adaptive Clip Threshold */ 2192 e1e_wphy(hw, 0x1F72, 0x3FB0); 2193 /* AHT reset limit to 1 */ 2194 e1e_wphy(hw, 0x1F76, 0xC0FF); 2195 /* Set AHT master delay to 127 msec */ 2196 e1e_wphy(hw, 0x1F77, 0x1DEC); 2197 /* Set scan bits for AHT */ 2198 e1e_wphy(hw, 0x1F78, 0xF9EF); 2199 /* Set AHT Preset bits */ 2200 e1e_wphy(hw, 0x1F79, 0x0210); 2201 /* Change integ_factor of channel A to 3 */ 2202 e1e_wphy(hw, 0x1895, 0x0003); 2203 /* Change prop_factor of channels BCD to 8 */ 2204 e1e_wphy(hw, 0x1796, 0x0008); 2205 /* Change cg_icount + enable integbp for channels BCD */ 2206 e1e_wphy(hw, 0x1798, 0xD008); 2207 /* Change cg_icount + enable integbp + change prop_factor_master 2208 * to 8 for channel A 2209 */ 2210 e1e_wphy(hw, 0x1898, 0xD918); 2211 /* Disable AHT in Slave mode on channel A */ 2212 e1e_wphy(hw, 0x187A, 0x0800); 2213 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2214 * Enable SPD+B2B 2215 */ 2216 e1e_wphy(hw, 0x0019, 0x008D); 2217 /* Enable restart AN on an1000_dis change */ 2218 e1e_wphy(hw, 0x001B, 0x2080); 2219 /* Enable wh_fifo read clock in 10/100 modes */ 2220 e1e_wphy(hw, 0x0014, 0x0045); 2221 /* Restart AN, Speed selection is 1000 */ 2222 e1e_wphy(hw, 0x0000, 0x1340); 2223 2224 return 0; 2225 } 2226 2227 /** 2228 * e1000e_get_phy_type_from_id - Get PHY type from id 2229 * @phy_id: phy_id read from the phy 2230 * 2231 * Returns the phy type from the id. 2232 **/ 2233 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) 2234 { 2235 enum e1000_phy_type phy_type = e1000_phy_unknown; 2236 2237 switch (phy_id) { 2238 case M88E1000_I_PHY_ID: 2239 case M88E1000_E_PHY_ID: 2240 case M88E1111_I_PHY_ID: 2241 case M88E1011_I_PHY_ID: 2242 phy_type = e1000_phy_m88; 2243 break; 2244 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2245 phy_type = e1000_phy_igp_2; 2246 break; 2247 case GG82563_E_PHY_ID: 2248 phy_type = e1000_phy_gg82563; 2249 break; 2250 case IGP03E1000_E_PHY_ID: 2251 phy_type = e1000_phy_igp_3; 2252 break; 2253 case IFE_E_PHY_ID: 2254 case IFE_PLUS_E_PHY_ID: 2255 case IFE_C_E_PHY_ID: 2256 phy_type = e1000_phy_ife; 2257 break; 2258 case BME1000_E_PHY_ID: 2259 case BME1000_E_PHY_ID_R2: 2260 phy_type = e1000_phy_bm; 2261 break; 2262 case I82578_E_PHY_ID: 2263 phy_type = e1000_phy_82578; 2264 break; 2265 case I82577_E_PHY_ID: 2266 phy_type = e1000_phy_82577; 2267 break; 2268 case I82579_E_PHY_ID: 2269 phy_type = e1000_phy_82579; 2270 break; 2271 case I217_E_PHY_ID: 2272 phy_type = e1000_phy_i217; 2273 break; 2274 default: 2275 phy_type = e1000_phy_unknown; 2276 break; 2277 } 2278 return phy_type; 2279 } 2280 2281 /** 2282 * e1000e_determine_phy_address - Determines PHY address. 2283 * @hw: pointer to the HW structure 2284 * 2285 * This uses a trial and error method to loop through possible PHY 2286 * addresses. It tests each by reading the PHY ID registers and 2287 * checking for a match. 2288 **/ 2289 s32 e1000e_determine_phy_address(struct e1000_hw *hw) 2290 { 2291 u32 phy_addr = 0; 2292 u32 i; 2293 enum e1000_phy_type phy_type = e1000_phy_unknown; 2294 2295 hw->phy.id = phy_type; 2296 2297 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2298 hw->phy.addr = phy_addr; 2299 i = 0; 2300 2301 do { 2302 e1000e_get_phy_id(hw); 2303 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 2304 2305 /* If phy_type is valid, break - we found our 2306 * PHY address 2307 */ 2308 if (phy_type != e1000_phy_unknown) 2309 return 0; 2310 2311 usleep_range(1000, 2000); 2312 i++; 2313 } while (i < 10); 2314 } 2315 2316 return -E1000_ERR_PHY_TYPE; 2317 } 2318 2319 /** 2320 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2321 * @page: page to access 2322 * 2323 * Returns the phy address for the page requested. 2324 **/ 2325 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2326 { 2327 u32 phy_addr = 2; 2328 2329 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2330 phy_addr = 1; 2331 2332 return phy_addr; 2333 } 2334 2335 /** 2336 * e1000e_write_phy_reg_bm - Write BM PHY register 2337 * @hw: pointer to the HW structure 2338 * @offset: register offset to write to 2339 * @data: data to write at register offset 2340 * 2341 * Acquires semaphore, if necessary, then writes the data to PHY register 2342 * at the offset. Release any acquired semaphores before exiting. 2343 **/ 2344 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2345 { 2346 s32 ret_val; 2347 u32 page = offset >> IGP_PAGE_SHIFT; 2348 2349 ret_val = hw->phy.ops.acquire(hw); 2350 if (ret_val) 2351 return ret_val; 2352 2353 /* Page 800 works differently than the rest so it has its own func */ 2354 if (page == BM_WUC_PAGE) { 2355 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2356 false, false); 2357 goto release; 2358 } 2359 2360 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2361 2362 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2363 u32 page_shift, page_select; 2364 2365 /* Page select is register 31 for phy address 1 and 22 for 2366 * phy address 2 and 3. Page select is shifted only for 2367 * phy address 1. 2368 */ 2369 if (hw->phy.addr == 1) { 2370 page_shift = IGP_PAGE_SHIFT; 2371 page_select = IGP01E1000_PHY_PAGE_SELECT; 2372 } else { 2373 page_shift = 0; 2374 page_select = BM_PHY_PAGE_SELECT; 2375 } 2376 2377 /* Page is shifted left, PHY expects (page x 32) */ 2378 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 2379 (page << page_shift)); 2380 if (ret_val) 2381 goto release; 2382 } 2383 2384 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2385 data); 2386 2387 release: 2388 hw->phy.ops.release(hw); 2389 return ret_val; 2390 } 2391 2392 /** 2393 * e1000e_read_phy_reg_bm - Read BM PHY register 2394 * @hw: pointer to the HW structure 2395 * @offset: register offset to be read 2396 * @data: pointer to the read data 2397 * 2398 * Acquires semaphore, if necessary, then reads the PHY register at offset 2399 * and storing the retrieved information in data. Release any acquired 2400 * semaphores before exiting. 2401 **/ 2402 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2403 { 2404 s32 ret_val; 2405 u32 page = offset >> IGP_PAGE_SHIFT; 2406 2407 ret_val = hw->phy.ops.acquire(hw); 2408 if (ret_val) 2409 return ret_val; 2410 2411 /* Page 800 works differently than the rest so it has its own func */ 2412 if (page == BM_WUC_PAGE) { 2413 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2414 true, false); 2415 goto release; 2416 } 2417 2418 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2419 2420 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2421 u32 page_shift, page_select; 2422 2423 /* Page select is register 31 for phy address 1 and 22 for 2424 * phy address 2 and 3. Page select is shifted only for 2425 * phy address 1. 2426 */ 2427 if (hw->phy.addr == 1) { 2428 page_shift = IGP_PAGE_SHIFT; 2429 page_select = IGP01E1000_PHY_PAGE_SELECT; 2430 } else { 2431 page_shift = 0; 2432 page_select = BM_PHY_PAGE_SELECT; 2433 } 2434 2435 /* Page is shifted left, PHY expects (page x 32) */ 2436 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 2437 (page << page_shift)); 2438 if (ret_val) 2439 goto release; 2440 } 2441 2442 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2443 data); 2444 release: 2445 hw->phy.ops.release(hw); 2446 return ret_val; 2447 } 2448 2449 /** 2450 * e1000e_read_phy_reg_bm2 - Read BM PHY register 2451 * @hw: pointer to the HW structure 2452 * @offset: register offset to be read 2453 * @data: pointer to the read data 2454 * 2455 * Acquires semaphore, if necessary, then reads the PHY register at offset 2456 * and storing the retrieved information in data. Release any acquired 2457 * semaphores before exiting. 2458 **/ 2459 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2460 { 2461 s32 ret_val; 2462 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2463 2464 ret_val = hw->phy.ops.acquire(hw); 2465 if (ret_val) 2466 return ret_val; 2467 2468 /* Page 800 works differently than the rest so it has its own func */ 2469 if (page == BM_WUC_PAGE) { 2470 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2471 true, false); 2472 goto release; 2473 } 2474 2475 hw->phy.addr = 1; 2476 2477 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2478 /* Page is shifted left, PHY expects (page x 32) */ 2479 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2480 page); 2481 2482 if (ret_val) 2483 goto release; 2484 } 2485 2486 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2487 data); 2488 release: 2489 hw->phy.ops.release(hw); 2490 return ret_val; 2491 } 2492 2493 /** 2494 * e1000e_write_phy_reg_bm2 - Write BM PHY register 2495 * @hw: pointer to the HW structure 2496 * @offset: register offset to write to 2497 * @data: data to write at register offset 2498 * 2499 * Acquires semaphore, if necessary, then writes the data to PHY register 2500 * at the offset. Release any acquired semaphores before exiting. 2501 **/ 2502 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2503 { 2504 s32 ret_val; 2505 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2506 2507 ret_val = hw->phy.ops.acquire(hw); 2508 if (ret_val) 2509 return ret_val; 2510 2511 /* Page 800 works differently than the rest so it has its own func */ 2512 if (page == BM_WUC_PAGE) { 2513 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2514 false, false); 2515 goto release; 2516 } 2517 2518 hw->phy.addr = 1; 2519 2520 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2521 /* Page is shifted left, PHY expects (page x 32) */ 2522 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2523 page); 2524 2525 if (ret_val) 2526 goto release; 2527 } 2528 2529 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2530 data); 2531 2532 release: 2533 hw->phy.ops.release(hw); 2534 return ret_val; 2535 } 2536 2537 /** 2538 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 2539 * @hw: pointer to the HW structure 2540 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 2541 * 2542 * Assumes semaphore already acquired and phy_reg points to a valid memory 2543 * address to store contents of the BM_WUC_ENABLE_REG register. 2544 **/ 2545 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 2546 { 2547 s32 ret_val; 2548 u16 temp; 2549 2550 /* All page select, port ctrl and wakeup registers use phy address 1 */ 2551 hw->phy.addr = 1; 2552 2553 /* Select Port Control Registers page */ 2554 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2555 if (ret_val) { 2556 e_dbg("Could not set Port Control page\n"); 2557 return ret_val; 2558 } 2559 2560 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2561 if (ret_val) { 2562 e_dbg("Could not read PHY register %d.%d\n", 2563 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2564 return ret_val; 2565 } 2566 2567 /* Enable both PHY wakeup mode and Wakeup register page writes. 2568 * Prevent a power state change by disabling ME and Host PHY wakeup. 2569 */ 2570 temp = *phy_reg; 2571 temp |= BM_WUC_ENABLE_BIT; 2572 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 2573 2574 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 2575 if (ret_val) { 2576 e_dbg("Could not write PHY register %d.%d\n", 2577 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2578 return ret_val; 2579 } 2580 2581 /* Select Host Wakeup Registers page - caller now able to write 2582 * registers on the Wakeup registers page 2583 */ 2584 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2585 } 2586 2587 /** 2588 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 2589 * @hw: pointer to the HW structure 2590 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 2591 * 2592 * Restore BM_WUC_ENABLE_REG to its original value. 2593 * 2594 * Assumes semaphore already acquired and *phy_reg is the contents of the 2595 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 2596 * caller. 2597 **/ 2598 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 2599 { 2600 s32 ret_val; 2601 2602 /* Select Port Control Registers page */ 2603 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2604 if (ret_val) { 2605 e_dbg("Could not set Port Control page\n"); 2606 return ret_val; 2607 } 2608 2609 /* Restore 769.17 to its original value */ 2610 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 2611 if (ret_val) 2612 e_dbg("Could not restore PHY register %d.%d\n", 2613 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2614 2615 return ret_val; 2616 } 2617 2618 /** 2619 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 2620 * @hw: pointer to the HW structure 2621 * @offset: register offset to be read or written 2622 * @data: pointer to the data to read or write 2623 * @read: determines if operation is read or write 2624 * @page_set: BM_WUC_PAGE already set and access enabled 2625 * 2626 * Read the PHY register at offset and store the retrieved information in 2627 * data, or write data to PHY register at offset. Note the procedure to 2628 * access the PHY wakeup registers is different than reading the other PHY 2629 * registers. It works as such: 2630 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 2631 * 2) Set page to 800 for host (801 if we were manageability) 2632 * 3) Write the address using the address opcode (0x11) 2633 * 4) Read or write the data using the data opcode (0x12) 2634 * 5) Restore 769.17.2 to its original value 2635 * 2636 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 2637 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 2638 * 2639 * Assumes semaphore is already acquired. When page_set==true, assumes 2640 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 2641 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 2642 **/ 2643 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 2644 u16 *data, bool read, bool page_set) 2645 { 2646 s32 ret_val; 2647 u16 reg = BM_PHY_REG_NUM(offset); 2648 u16 page = BM_PHY_REG_PAGE(offset); 2649 u16 phy_reg = 0; 2650 2651 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 2652 if ((hw->mac.type == e1000_pchlan) && 2653 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2654 e_dbg("Attempting to access page %d while gig enabled.\n", 2655 page); 2656 2657 if (!page_set) { 2658 /* Enable access to PHY wakeup registers */ 2659 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2660 if (ret_val) { 2661 e_dbg("Could not enable PHY wakeup reg access\n"); 2662 return ret_val; 2663 } 2664 } 2665 2666 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); 2667 2668 /* Write the Wakeup register page offset value using opcode 0x11 */ 2669 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2670 if (ret_val) { 2671 e_dbg("Could not write address opcode to page %d\n", page); 2672 return ret_val; 2673 } 2674 2675 if (read) { 2676 /* Read the Wakeup register page value using opcode 0x12 */ 2677 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2678 data); 2679 } else { 2680 /* Write the Wakeup register page value using opcode 0x12 */ 2681 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2682 *data); 2683 } 2684 2685 if (ret_val) { 2686 e_dbg("Could not access PHY reg %d.%d\n", page, reg); 2687 return ret_val; 2688 } 2689 2690 if (!page_set) 2691 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2692 2693 return ret_val; 2694 } 2695 2696 /** 2697 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2698 * @hw: pointer to the HW structure 2699 * 2700 * In the case of a PHY power down to save power, or to turn off link during a 2701 * driver unload, or wake on lan is not enabled, restore the link to previous 2702 * settings. 2703 **/ 2704 void e1000_power_up_phy_copper(struct e1000_hw *hw) 2705 { 2706 u16 mii_reg = 0; 2707 2708 /* The PHY will retain its settings across a power down/up cycle */ 2709 e1e_rphy(hw, MII_BMCR, &mii_reg); 2710 mii_reg &= ~BMCR_PDOWN; 2711 e1e_wphy(hw, MII_BMCR, mii_reg); 2712 } 2713 2714 /** 2715 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2716 * @hw: pointer to the HW structure 2717 * 2718 * In the case of a PHY power down to save power, or to turn off link during a 2719 * driver unload, or wake on lan is not enabled, restore the link to previous 2720 * settings. 2721 **/ 2722 void e1000_power_down_phy_copper(struct e1000_hw *hw) 2723 { 2724 u16 mii_reg = 0; 2725 2726 /* The PHY will retain its settings across a power down/up cycle */ 2727 e1e_rphy(hw, MII_BMCR, &mii_reg); 2728 mii_reg |= BMCR_PDOWN; 2729 e1e_wphy(hw, MII_BMCR, mii_reg); 2730 usleep_range(1000, 2000); 2731 } 2732 2733 /** 2734 * __e1000_read_phy_reg_hv - Read HV PHY register 2735 * @hw: pointer to the HW structure 2736 * @offset: register offset to be read 2737 * @data: pointer to the read data 2738 * @locked: semaphore has already been acquired or not 2739 * 2740 * Acquires semaphore, if necessary, then reads the PHY register at offset 2741 * and stores the retrieved information in data. Release any acquired 2742 * semaphore before exiting. 2743 **/ 2744 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 2745 bool locked, bool page_set) 2746 { 2747 s32 ret_val; 2748 u16 page = BM_PHY_REG_PAGE(offset); 2749 u16 reg = BM_PHY_REG_NUM(offset); 2750 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2751 2752 if (!locked) { 2753 ret_val = hw->phy.ops.acquire(hw); 2754 if (ret_val) 2755 return ret_val; 2756 } 2757 2758 /* Page 800 works differently than the rest so it has its own func */ 2759 if (page == BM_WUC_PAGE) { 2760 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2761 true, page_set); 2762 goto out; 2763 } 2764 2765 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 2766 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 2767 data, true); 2768 goto out; 2769 } 2770 2771 if (!page_set) { 2772 if (page == HV_INTC_FC_PAGE_START) 2773 page = 0; 2774 2775 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2776 /* Page is shifted left, PHY expects (page x 32) */ 2777 ret_val = e1000_set_page_igp(hw, 2778 (page << IGP_PAGE_SHIFT)); 2779 2780 hw->phy.addr = phy_addr; 2781 2782 if (ret_val) 2783 goto out; 2784 } 2785 } 2786 2787 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 2788 page << IGP_PAGE_SHIFT, reg); 2789 2790 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data); 2791 out: 2792 if (!locked) 2793 hw->phy.ops.release(hw); 2794 2795 return ret_val; 2796 } 2797 2798 /** 2799 * e1000_read_phy_reg_hv - Read HV PHY register 2800 * @hw: pointer to the HW structure 2801 * @offset: register offset to be read 2802 * @data: pointer to the read data 2803 * 2804 * Acquires semaphore then reads the PHY register at offset and stores 2805 * the retrieved information in data. Release the acquired semaphore 2806 * before exiting. 2807 **/ 2808 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2809 { 2810 return __e1000_read_phy_reg_hv(hw, offset, data, false, false); 2811 } 2812 2813 /** 2814 * e1000_read_phy_reg_hv_locked - Read HV PHY register 2815 * @hw: pointer to the HW structure 2816 * @offset: register offset to be read 2817 * @data: pointer to the read data 2818 * 2819 * Reads the PHY register at offset and stores the retrieved information 2820 * in data. Assumes semaphore already acquired. 2821 **/ 2822 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 2823 { 2824 return __e1000_read_phy_reg_hv(hw, offset, data, true, false); 2825 } 2826 2827 /** 2828 * e1000_read_phy_reg_page_hv - Read HV PHY register 2829 * @hw: pointer to the HW structure 2830 * @offset: register offset to write to 2831 * @data: data to write at register offset 2832 * 2833 * Reads the PHY register at offset and stores the retrieved information 2834 * in data. Assumes semaphore already acquired and page already set. 2835 **/ 2836 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2837 { 2838 return __e1000_read_phy_reg_hv(hw, offset, data, true, true); 2839 } 2840 2841 /** 2842 * __e1000_write_phy_reg_hv - Write HV PHY register 2843 * @hw: pointer to the HW structure 2844 * @offset: register offset to write to 2845 * @data: data to write at register offset 2846 * @locked: semaphore has already been acquired or not 2847 * 2848 * Acquires semaphore, if necessary, then writes the data to PHY register 2849 * at the offset. Release any acquired semaphores before exiting. 2850 **/ 2851 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 2852 bool locked, bool page_set) 2853 { 2854 s32 ret_val; 2855 u16 page = BM_PHY_REG_PAGE(offset); 2856 u16 reg = BM_PHY_REG_NUM(offset); 2857 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2858 2859 if (!locked) { 2860 ret_val = hw->phy.ops.acquire(hw); 2861 if (ret_val) 2862 return ret_val; 2863 } 2864 2865 /* Page 800 works differently than the rest so it has its own func */ 2866 if (page == BM_WUC_PAGE) { 2867 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2868 false, page_set); 2869 goto out; 2870 } 2871 2872 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 2873 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 2874 &data, false); 2875 goto out; 2876 } 2877 2878 if (!page_set) { 2879 if (page == HV_INTC_FC_PAGE_START) 2880 page = 0; 2881 2882 /* Workaround MDIO accesses being disabled after entering IEEE 2883 * Power Down (when bit 11 of the PHY Control register is set) 2884 */ 2885 if ((hw->phy.type == e1000_phy_82578) && 2886 (hw->phy.revision >= 1) && 2887 (hw->phy.addr == 2) && 2888 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) { 2889 u16 data2 = 0x7EFF; 2890 ret_val = e1000_access_phy_debug_regs_hv(hw, 2891 (1 << 6) | 0x3, 2892 &data2, false); 2893 if (ret_val) 2894 goto out; 2895 } 2896 2897 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2898 /* Page is shifted left, PHY expects (page x 32) */ 2899 ret_val = e1000_set_page_igp(hw, 2900 (page << IGP_PAGE_SHIFT)); 2901 2902 hw->phy.addr = phy_addr; 2903 2904 if (ret_val) 2905 goto out; 2906 } 2907 } 2908 2909 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 2910 page << IGP_PAGE_SHIFT, reg); 2911 2912 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2913 data); 2914 2915 out: 2916 if (!locked) 2917 hw->phy.ops.release(hw); 2918 2919 return ret_val; 2920 } 2921 2922 /** 2923 * e1000_write_phy_reg_hv - Write HV PHY register 2924 * @hw: pointer to the HW structure 2925 * @offset: register offset to write to 2926 * @data: data to write at register offset 2927 * 2928 * Acquires semaphore then writes the data to PHY register at the offset. 2929 * Release the acquired semaphores before exiting. 2930 **/ 2931 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 2932 { 2933 return __e1000_write_phy_reg_hv(hw, offset, data, false, false); 2934 } 2935 2936 /** 2937 * e1000_write_phy_reg_hv_locked - Write HV PHY register 2938 * @hw: pointer to the HW structure 2939 * @offset: register offset to write to 2940 * @data: data to write at register offset 2941 * 2942 * Writes the data to PHY register at the offset. Assumes semaphore 2943 * already acquired. 2944 **/ 2945 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 2946 { 2947 return __e1000_write_phy_reg_hv(hw, offset, data, true, false); 2948 } 2949 2950 /** 2951 * e1000_write_phy_reg_page_hv - Write HV PHY register 2952 * @hw: pointer to the HW structure 2953 * @offset: register offset to write to 2954 * @data: data to write at register offset 2955 * 2956 * Writes the data to PHY register at the offset. Assumes semaphore 2957 * already acquired and page already set. 2958 **/ 2959 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 2960 { 2961 return __e1000_write_phy_reg_hv(hw, offset, data, true, true); 2962 } 2963 2964 /** 2965 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page 2966 * @page: page to be accessed 2967 **/ 2968 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 2969 { 2970 u32 phy_addr = 2; 2971 2972 if (page >= HV_INTC_FC_PAGE_START) 2973 phy_addr = 1; 2974 2975 return phy_addr; 2976 } 2977 2978 /** 2979 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 2980 * @hw: pointer to the HW structure 2981 * @offset: register offset to be read or written 2982 * @data: pointer to the data to be read or written 2983 * @read: determines if operation is read or write 2984 * 2985 * Reads the PHY register at offset and stores the retreived information 2986 * in data. Assumes semaphore already acquired. Note that the procedure 2987 * to access these regs uses the address port and data port to read/write. 2988 * These accesses done with PHY address 2 and without using pages. 2989 **/ 2990 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 2991 u16 *data, bool read) 2992 { 2993 s32 ret_val; 2994 u32 addr_reg; 2995 u32 data_reg; 2996 2997 /* This takes care of the difference with desktop vs mobile phy */ 2998 addr_reg = ((hw->phy.type == e1000_phy_82578) ? 2999 I82578_ADDR_REG : I82577_ADDR_REG); 3000 data_reg = addr_reg + 1; 3001 3002 /* All operations in this function are phy address 2 */ 3003 hw->phy.addr = 2; 3004 3005 /* masking with 0x3F to remove the page from offset */ 3006 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3007 if (ret_val) { 3008 e_dbg("Could not write the Address Offset port register\n"); 3009 return ret_val; 3010 } 3011 3012 /* Read or write the data value next */ 3013 if (read) 3014 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); 3015 else 3016 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); 3017 3018 if (ret_val) 3019 e_dbg("Could not access the Data port register\n"); 3020 3021 return ret_val; 3022 } 3023 3024 /** 3025 * e1000_link_stall_workaround_hv - Si workaround 3026 * @hw: pointer to the HW structure 3027 * 3028 * This function works around a Si bug where the link partner can get 3029 * a link up indication before the PHY does. If small packets are sent 3030 * by the link partner they can be placed in the packet buffer without 3031 * being properly accounted for by the PHY and will stall preventing 3032 * further packets from being received. The workaround is to clear the 3033 * packet buffer after the PHY detects link up. 3034 **/ 3035 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3036 { 3037 s32 ret_val = 0; 3038 u16 data; 3039 3040 if (hw->phy.type != e1000_phy_82578) 3041 return 0; 3042 3043 /* Do not apply workaround if in PHY loopback bit 14 set */ 3044 e1e_rphy(hw, MII_BMCR, &data); 3045 if (data & BMCR_LOOPBACK) 3046 return 0; 3047 3048 /* check if link is up and at 1Gbps */ 3049 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); 3050 if (ret_val) 3051 return ret_val; 3052 3053 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3054 BM_CS_STATUS_SPEED_MASK); 3055 3056 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3057 BM_CS_STATUS_SPEED_1000)) 3058 return 0; 3059 3060 msleep(200); 3061 3062 /* flush the packets in the fifo buffer */ 3063 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, 3064 (HV_MUX_DATA_CTRL_GEN_TO_MAC | 3065 HV_MUX_DATA_CTRL_FORCE_SPEED)); 3066 if (ret_val) 3067 return ret_val; 3068 3069 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); 3070 } 3071 3072 /** 3073 * e1000_check_polarity_82577 - Checks the polarity. 3074 * @hw: pointer to the HW structure 3075 * 3076 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3077 * 3078 * Polarity is determined based on the PHY specific status register. 3079 **/ 3080 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3081 { 3082 struct e1000_phy_info *phy = &hw->phy; 3083 s32 ret_val; 3084 u16 data; 3085 3086 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 3087 3088 if (!ret_val) 3089 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) 3090 ? e1000_rev_polarity_reversed 3091 : e1000_rev_polarity_normal); 3092 3093 return ret_val; 3094 } 3095 3096 /** 3097 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3098 * @hw: pointer to the HW structure 3099 * 3100 * Calls the PHY setup function to force speed and duplex. 3101 **/ 3102 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3103 { 3104 struct e1000_phy_info *phy = &hw->phy; 3105 s32 ret_val; 3106 u16 phy_data; 3107 bool link; 3108 3109 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); 3110 if (ret_val) 3111 return ret_val; 3112 3113 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 3114 3115 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); 3116 if (ret_val) 3117 return ret_val; 3118 3119 udelay(1); 3120 3121 if (phy->autoneg_wait_to_complete) { 3122 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); 3123 3124 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3125 100000, &link); 3126 if (ret_val) 3127 return ret_val; 3128 3129 if (!link) 3130 e_dbg("Link taking longer than expected.\n"); 3131 3132 /* Try once more */ 3133 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3134 100000, &link); 3135 } 3136 3137 return ret_val; 3138 } 3139 3140 /** 3141 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3142 * @hw: pointer to the HW structure 3143 * 3144 * Read PHY status to determine if link is up. If link is up, then 3145 * set/determine 10base-T extended distance and polarity correction. Read 3146 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3147 * determine on the cable length, local and remote receiver. 3148 **/ 3149 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3150 { 3151 struct e1000_phy_info *phy = &hw->phy; 3152 s32 ret_val; 3153 u16 data; 3154 bool link; 3155 3156 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 3157 if (ret_val) 3158 return ret_val; 3159 3160 if (!link) { 3161 e_dbg("Phy info is only valid if link is up\n"); 3162 return -E1000_ERR_CONFIG; 3163 } 3164 3165 phy->polarity_correction = true; 3166 3167 ret_val = e1000_check_polarity_82577(hw); 3168 if (ret_val) 3169 return ret_val; 3170 3171 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 3172 if (ret_val) 3173 return ret_val; 3174 3175 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 3176 3177 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3178 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3179 ret_val = hw->phy.ops.get_cable_length(hw); 3180 if (ret_val) 3181 return ret_val; 3182 3183 ret_val = e1e_rphy(hw, MII_STAT1000, &data); 3184 if (ret_val) 3185 return ret_val; 3186 3187 phy->local_rx = (data & LPA_1000LOCALRXOK) 3188 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3189 3190 phy->remote_rx = (data & LPA_1000REMRXOK) 3191 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3192 } else { 3193 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3194 phy->local_rx = e1000_1000t_rx_status_undefined; 3195 phy->remote_rx = e1000_1000t_rx_status_undefined; 3196 } 3197 3198 return 0; 3199 } 3200 3201 /** 3202 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3203 * @hw: pointer to the HW structure 3204 * 3205 * Reads the diagnostic status register and verifies result is valid before 3206 * placing it in the phy_cable_length field. 3207 **/ 3208 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3209 { 3210 struct e1000_phy_info *phy = &hw->phy; 3211 s32 ret_val; 3212 u16 phy_data, length; 3213 3214 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3215 if (ret_val) 3216 return ret_val; 3217 3218 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3219 I82577_DSTATUS_CABLE_LENGTH_SHIFT); 3220 3221 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3222 return -E1000_ERR_PHY; 3223 3224 phy->cable_length = length; 3225 3226 return 0; 3227 } 3228