1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include "e1000.h" 30 31 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 32 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); 33 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); 34 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 35 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 36 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 37 u16 *data, bool read, bool page_set); 38 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 39 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 40 u16 *data, bool read); 41 42 /* Cable length tables */ 43 static const u16 e1000_m88_cable_length_table[] = { 44 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 45 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 46 ARRAY_SIZE(e1000_m88_cable_length_table) 47 48 static const u16 e1000_igp_2_cable_length_table[] = { 49 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 50 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 51 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 52 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 53 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 54 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 55 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 56 124}; 57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 58 ARRAY_SIZE(e1000_igp_2_cable_length_table) 59 60 #define BM_PHY_REG_PAGE(offset) \ 61 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 62 #define BM_PHY_REG_NUM(offset) \ 63 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ 64 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 65 ~MAX_PHY_REG_ADDRESS))) 66 67 #define HV_INTC_FC_PAGE_START 768 68 #define I82578_ADDR_REG 29 69 #define I82577_ADDR_REG 16 70 #define I82577_CFG_REG 22 71 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 72 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ 73 #define I82577_CTRL_REG 23 74 75 /* 82577 specific PHY registers */ 76 #define I82577_PHY_CTRL_2 18 77 #define I82577_PHY_STATUS_2 26 78 #define I82577_PHY_DIAG_STATUS 31 79 80 /* I82577 PHY Status 2 */ 81 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 82 #define I82577_PHY_STATUS2_MDIX 0x0800 83 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 84 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 85 86 /* I82577 PHY Control 2 */ 87 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 88 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 89 90 /* I82577 PHY Diagnostics Status */ 91 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC 92 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 93 94 /* BM PHY Copper Specific Control 1 */ 95 #define BM_CS_CTRL1 16 96 97 #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 98 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 99 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 100 101 /** 102 * e1000e_check_reset_block_generic - Check if PHY reset is blocked 103 * @hw: pointer to the HW structure 104 * 105 * Read the PHY management control register and check whether a PHY reset 106 * is blocked. If a reset is not blocked return 0, otherwise 107 * return E1000_BLK_PHY_RESET (12). 108 **/ 109 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) 110 { 111 u32 manc; 112 113 manc = er32(MANC); 114 115 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 116 E1000_BLK_PHY_RESET : 0; 117 } 118 119 /** 120 * e1000e_get_phy_id - Retrieve the PHY ID and revision 121 * @hw: pointer to the HW structure 122 * 123 * Reads the PHY registers and stores the PHY ID and possibly the PHY 124 * revision in the hardware structure. 125 **/ 126 s32 e1000e_get_phy_id(struct e1000_hw *hw) 127 { 128 struct e1000_phy_info *phy = &hw->phy; 129 s32 ret_val = 0; 130 u16 phy_id; 131 u16 retry_count = 0; 132 133 if (!phy->ops.read_reg) 134 return 0; 135 136 while (retry_count < 2) { 137 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); 138 if (ret_val) 139 return ret_val; 140 141 phy->id = (u32)(phy_id << 16); 142 udelay(20); 143 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); 144 if (ret_val) 145 return ret_val; 146 147 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 148 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 149 150 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 151 return 0; 152 153 retry_count++; 154 } 155 156 return 0; 157 } 158 159 /** 160 * e1000e_phy_reset_dsp - Reset PHY DSP 161 * @hw: pointer to the HW structure 162 * 163 * Reset the digital signal processor. 164 **/ 165 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) 166 { 167 s32 ret_val; 168 169 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 170 if (ret_val) 171 return ret_val; 172 173 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); 174 } 175 176 /** 177 * e1000e_read_phy_reg_mdic - Read MDI control register 178 * @hw: pointer to the HW structure 179 * @offset: register offset to be read 180 * @data: pointer to the read data 181 * 182 * Reads the MDI control register in the PHY at offset and stores the 183 * information read to data. 184 **/ 185 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 186 { 187 struct e1000_phy_info *phy = &hw->phy; 188 u32 i, mdic = 0; 189 190 if (offset > MAX_PHY_REG_ADDRESS) { 191 e_dbg("PHY Address %d is out of range\n", offset); 192 return -E1000_ERR_PARAM; 193 } 194 195 /* 196 * Set up Op-code, Phy Address, and register offset in the MDI 197 * Control register. The MAC will take care of interfacing with the 198 * PHY to retrieve the desired data. 199 */ 200 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 201 (phy->addr << E1000_MDIC_PHY_SHIFT) | 202 (E1000_MDIC_OP_READ)); 203 204 ew32(MDIC, mdic); 205 206 /* 207 * Poll the ready bit to see if the MDI read completed 208 * Increasing the time out as testing showed failures with 209 * the lower time out 210 */ 211 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 212 udelay(50); 213 mdic = er32(MDIC); 214 if (mdic & E1000_MDIC_READY) 215 break; 216 } 217 if (!(mdic & E1000_MDIC_READY)) { 218 e_dbg("MDI Read did not complete\n"); 219 return -E1000_ERR_PHY; 220 } 221 if (mdic & E1000_MDIC_ERROR) { 222 e_dbg("MDI Error\n"); 223 return -E1000_ERR_PHY; 224 } 225 *data = (u16) mdic; 226 227 /* 228 * Allow some time after each MDIC transaction to avoid 229 * reading duplicate data in the next MDIC transaction. 230 */ 231 if (hw->mac.type == e1000_pch2lan) 232 udelay(100); 233 234 return 0; 235 } 236 237 /** 238 * e1000e_write_phy_reg_mdic - Write MDI control register 239 * @hw: pointer to the HW structure 240 * @offset: register offset to write to 241 * @data: data to write to register at offset 242 * 243 * Writes data to MDI control register in the PHY at offset. 244 **/ 245 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 246 { 247 struct e1000_phy_info *phy = &hw->phy; 248 u32 i, mdic = 0; 249 250 if (offset > MAX_PHY_REG_ADDRESS) { 251 e_dbg("PHY Address %d is out of range\n", offset); 252 return -E1000_ERR_PARAM; 253 } 254 255 /* 256 * Set up Op-code, Phy Address, and register offset in the MDI 257 * Control register. The MAC will take care of interfacing with the 258 * PHY to retrieve the desired data. 259 */ 260 mdic = (((u32)data) | 261 (offset << E1000_MDIC_REG_SHIFT) | 262 (phy->addr << E1000_MDIC_PHY_SHIFT) | 263 (E1000_MDIC_OP_WRITE)); 264 265 ew32(MDIC, mdic); 266 267 /* 268 * Poll the ready bit to see if the MDI read completed 269 * Increasing the time out as testing showed failures with 270 * the lower time out 271 */ 272 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 273 udelay(50); 274 mdic = er32(MDIC); 275 if (mdic & E1000_MDIC_READY) 276 break; 277 } 278 if (!(mdic & E1000_MDIC_READY)) { 279 e_dbg("MDI Write did not complete\n"); 280 return -E1000_ERR_PHY; 281 } 282 if (mdic & E1000_MDIC_ERROR) { 283 e_dbg("MDI Error\n"); 284 return -E1000_ERR_PHY; 285 } 286 287 /* 288 * Allow some time after each MDIC transaction to avoid 289 * reading duplicate data in the next MDIC transaction. 290 */ 291 if (hw->mac.type == e1000_pch2lan) 292 udelay(100); 293 294 return 0; 295 } 296 297 /** 298 * e1000e_read_phy_reg_m88 - Read m88 PHY register 299 * @hw: pointer to the HW structure 300 * @offset: register offset to be read 301 * @data: pointer to the read data 302 * 303 * Acquires semaphore, if necessary, then reads the PHY register at offset 304 * and storing the retrieved information in data. Release any acquired 305 * semaphores before exiting. 306 **/ 307 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 308 { 309 s32 ret_val; 310 311 ret_val = hw->phy.ops.acquire(hw); 312 if (ret_val) 313 return ret_val; 314 315 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 316 data); 317 318 hw->phy.ops.release(hw); 319 320 return ret_val; 321 } 322 323 /** 324 * e1000e_write_phy_reg_m88 - Write m88 PHY register 325 * @hw: pointer to the HW structure 326 * @offset: register offset to write to 327 * @data: data to write at register offset 328 * 329 * Acquires semaphore, if necessary, then writes the data to PHY register 330 * at the offset. Release any acquired semaphores before exiting. 331 **/ 332 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 333 { 334 s32 ret_val; 335 336 ret_val = hw->phy.ops.acquire(hw); 337 if (ret_val) 338 return ret_val; 339 340 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 341 data); 342 343 hw->phy.ops.release(hw); 344 345 return ret_val; 346 } 347 348 /** 349 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 350 * @hw: pointer to the HW structure 351 * @page: page to set (shifted left when necessary) 352 * 353 * Sets PHY page required for PHY register access. Assumes semaphore is 354 * already acquired. Note, this function sets phy.addr to 1 so the caller 355 * must set it appropriately (if necessary) after this function returns. 356 **/ 357 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 358 { 359 e_dbg("Setting page 0x%x\n", page); 360 361 hw->phy.addr = 1; 362 363 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 364 } 365 366 /** 367 * __e1000e_read_phy_reg_igp - Read igp PHY register 368 * @hw: pointer to the HW structure 369 * @offset: register offset to be read 370 * @data: pointer to the read data 371 * @locked: semaphore has already been acquired or not 372 * 373 * Acquires semaphore, if necessary, then reads the PHY register at offset 374 * and stores the retrieved information in data. Release any acquired 375 * semaphores before exiting. 376 **/ 377 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 378 bool locked) 379 { 380 s32 ret_val = 0; 381 382 if (!locked) { 383 if (!hw->phy.ops.acquire) 384 return 0; 385 386 ret_val = hw->phy.ops.acquire(hw); 387 if (ret_val) 388 return ret_val; 389 } 390 391 if (offset > MAX_PHY_MULTI_PAGE_REG) 392 ret_val = e1000e_write_phy_reg_mdic(hw, 393 IGP01E1000_PHY_PAGE_SELECT, 394 (u16)offset); 395 if (!ret_val) 396 ret_val = e1000e_read_phy_reg_mdic(hw, 397 MAX_PHY_REG_ADDRESS & offset, 398 data); 399 if (!locked) 400 hw->phy.ops.release(hw); 401 402 return ret_val; 403 } 404 405 /** 406 * e1000e_read_phy_reg_igp - Read igp PHY register 407 * @hw: pointer to the HW structure 408 * @offset: register offset to be read 409 * @data: pointer to the read data 410 * 411 * Acquires semaphore then reads the PHY register at offset and stores the 412 * retrieved information in data. 413 * Release the acquired semaphore before exiting. 414 **/ 415 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 416 { 417 return __e1000e_read_phy_reg_igp(hw, offset, data, false); 418 } 419 420 /** 421 * e1000e_read_phy_reg_igp_locked - Read igp PHY register 422 * @hw: pointer to the HW structure 423 * @offset: register offset to be read 424 * @data: pointer to the read data 425 * 426 * Reads the PHY register at offset and stores the retrieved information 427 * in data. Assumes semaphore already acquired. 428 **/ 429 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 430 { 431 return __e1000e_read_phy_reg_igp(hw, offset, data, true); 432 } 433 434 /** 435 * e1000e_write_phy_reg_igp - Write igp PHY register 436 * @hw: pointer to the HW structure 437 * @offset: register offset to write to 438 * @data: data to write at register offset 439 * @locked: semaphore has already been acquired or not 440 * 441 * Acquires semaphore, if necessary, then writes the data to PHY register 442 * at the offset. Release any acquired semaphores before exiting. 443 **/ 444 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 445 bool locked) 446 { 447 s32 ret_val = 0; 448 449 if (!locked) { 450 if (!hw->phy.ops.acquire) 451 return 0; 452 453 ret_val = hw->phy.ops.acquire(hw); 454 if (ret_val) 455 return ret_val; 456 } 457 458 if (offset > MAX_PHY_MULTI_PAGE_REG) 459 ret_val = e1000e_write_phy_reg_mdic(hw, 460 IGP01E1000_PHY_PAGE_SELECT, 461 (u16)offset); 462 if (!ret_val) 463 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 464 offset, 465 data); 466 if (!locked) 467 hw->phy.ops.release(hw); 468 469 return ret_val; 470 } 471 472 /** 473 * e1000e_write_phy_reg_igp - Write igp PHY register 474 * @hw: pointer to the HW structure 475 * @offset: register offset to write to 476 * @data: data to write at register offset 477 * 478 * Acquires semaphore then writes the data to PHY register 479 * at the offset. Release any acquired semaphores before exiting. 480 **/ 481 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 482 { 483 return __e1000e_write_phy_reg_igp(hw, offset, data, false); 484 } 485 486 /** 487 * e1000e_write_phy_reg_igp_locked - Write igp PHY register 488 * @hw: pointer to the HW structure 489 * @offset: register offset to write to 490 * @data: data to write at register offset 491 * 492 * Writes the data to PHY register at the offset. 493 * Assumes semaphore already acquired. 494 **/ 495 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 496 { 497 return __e1000e_write_phy_reg_igp(hw, offset, data, true); 498 } 499 500 /** 501 * __e1000_read_kmrn_reg - Read kumeran register 502 * @hw: pointer to the HW structure 503 * @offset: register offset to be read 504 * @data: pointer to the read data 505 * @locked: semaphore has already been acquired or not 506 * 507 * Acquires semaphore, if necessary. Then reads the PHY register at offset 508 * using the kumeran interface. The information retrieved is stored in data. 509 * Release any acquired semaphores before exiting. 510 **/ 511 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 512 bool locked) 513 { 514 u32 kmrnctrlsta; 515 516 if (!locked) { 517 s32 ret_val = 0; 518 519 if (!hw->phy.ops.acquire) 520 return 0; 521 522 ret_val = hw->phy.ops.acquire(hw); 523 if (ret_val) 524 return ret_val; 525 } 526 527 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 528 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 529 ew32(KMRNCTRLSTA, kmrnctrlsta); 530 e1e_flush(); 531 532 udelay(2); 533 534 kmrnctrlsta = er32(KMRNCTRLSTA); 535 *data = (u16)kmrnctrlsta; 536 537 if (!locked) 538 hw->phy.ops.release(hw); 539 540 return 0; 541 } 542 543 /** 544 * e1000e_read_kmrn_reg - Read kumeran register 545 * @hw: pointer to the HW structure 546 * @offset: register offset to be read 547 * @data: pointer to the read data 548 * 549 * Acquires semaphore then reads the PHY register at offset using the 550 * kumeran interface. The information retrieved is stored in data. 551 * Release the acquired semaphore before exiting. 552 **/ 553 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) 554 { 555 return __e1000_read_kmrn_reg(hw, offset, data, false); 556 } 557 558 /** 559 * e1000e_read_kmrn_reg_locked - Read kumeran register 560 * @hw: pointer to the HW structure 561 * @offset: register offset to be read 562 * @data: pointer to the read data 563 * 564 * Reads the PHY register at offset using the kumeran interface. The 565 * information retrieved is stored in data. 566 * Assumes semaphore already acquired. 567 **/ 568 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 569 { 570 return __e1000_read_kmrn_reg(hw, offset, data, true); 571 } 572 573 /** 574 * __e1000_write_kmrn_reg - Write kumeran register 575 * @hw: pointer to the HW structure 576 * @offset: register offset to write to 577 * @data: data to write at register offset 578 * @locked: semaphore has already been acquired or not 579 * 580 * Acquires semaphore, if necessary. Then write the data to PHY register 581 * at the offset using the kumeran interface. Release any acquired semaphores 582 * before exiting. 583 **/ 584 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 585 bool locked) 586 { 587 u32 kmrnctrlsta; 588 589 if (!locked) { 590 s32 ret_val = 0; 591 592 if (!hw->phy.ops.acquire) 593 return 0; 594 595 ret_val = hw->phy.ops.acquire(hw); 596 if (ret_val) 597 return ret_val; 598 } 599 600 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 601 E1000_KMRNCTRLSTA_OFFSET) | data; 602 ew32(KMRNCTRLSTA, kmrnctrlsta); 603 e1e_flush(); 604 605 udelay(2); 606 607 if (!locked) 608 hw->phy.ops.release(hw); 609 610 return 0; 611 } 612 613 /** 614 * e1000e_write_kmrn_reg - Write kumeran register 615 * @hw: pointer to the HW structure 616 * @offset: register offset to write to 617 * @data: data to write at register offset 618 * 619 * Acquires semaphore then writes the data to the PHY register at the offset 620 * using the kumeran interface. Release the acquired semaphore before exiting. 621 **/ 622 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) 623 { 624 return __e1000_write_kmrn_reg(hw, offset, data, false); 625 } 626 627 /** 628 * e1000e_write_kmrn_reg_locked - Write kumeran register 629 * @hw: pointer to the HW structure 630 * @offset: register offset to write to 631 * @data: data to write at register offset 632 * 633 * Write the data to PHY register at the offset using the kumeran interface. 634 * Assumes semaphore already acquired. 635 **/ 636 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 637 { 638 return __e1000_write_kmrn_reg(hw, offset, data, true); 639 } 640 641 /** 642 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 643 * @hw: pointer to the HW structure 644 * 645 * Sets up Master/slave mode 646 **/ 647 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 648 { 649 s32 ret_val; 650 u16 phy_data; 651 652 /* Resolve Master/Slave mode */ 653 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &phy_data); 654 if (ret_val) 655 return ret_val; 656 657 /* load defaults for future use */ 658 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 659 ((phy_data & CR_1000T_MS_VALUE) ? 660 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto; 661 662 switch (hw->phy.ms_type) { 663 case e1000_ms_force_master: 664 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 665 break; 666 case e1000_ms_force_slave: 667 phy_data |= CR_1000T_MS_ENABLE; 668 phy_data &= ~(CR_1000T_MS_VALUE); 669 break; 670 case e1000_ms_auto: 671 phy_data &= ~CR_1000T_MS_ENABLE; 672 /* fall-through */ 673 default: 674 break; 675 } 676 677 return e1e_wphy(hw, PHY_1000T_CTRL, phy_data); 678 } 679 680 /** 681 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 682 * @hw: pointer to the HW structure 683 * 684 * Sets up Carrier-sense on Transmit and downshift values. 685 **/ 686 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 687 { 688 s32 ret_val; 689 u16 phy_data; 690 691 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 692 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); 693 if (ret_val) 694 return ret_val; 695 696 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 697 698 /* Enable downshift */ 699 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 700 701 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); 702 if (ret_val) 703 return ret_val; 704 705 return e1000_set_master_slave_mode(hw); 706 } 707 708 /** 709 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link 710 * @hw: pointer to the HW structure 711 * 712 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 713 * and downshift values are set also. 714 **/ 715 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) 716 { 717 struct e1000_phy_info *phy = &hw->phy; 718 s32 ret_val; 719 u16 phy_data; 720 721 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 722 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 723 if (ret_val) 724 return ret_val; 725 726 /* For BM PHY this bit is downshift enable */ 727 if (phy->type != e1000_phy_bm) 728 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 729 730 /* 731 * Options: 732 * MDI/MDI-X = 0 (default) 733 * 0 - Auto for all speeds 734 * 1 - MDI mode 735 * 2 - MDI-X mode 736 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 737 */ 738 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 739 740 switch (phy->mdix) { 741 case 1: 742 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 743 break; 744 case 2: 745 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 746 break; 747 case 3: 748 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 749 break; 750 case 0: 751 default: 752 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 753 break; 754 } 755 756 /* 757 * Options: 758 * disable_polarity_correction = 0 (default) 759 * Automatic Correction for Reversed Cable Polarity 760 * 0 - Disabled 761 * 1 - Enabled 762 */ 763 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 764 if (phy->disable_polarity_correction) 765 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 766 767 /* Enable downshift on BM (disabled by default) */ 768 if (phy->type == e1000_phy_bm) { 769 /* For 82574/82583, first disable then enable downshift */ 770 if (phy->id == BME1000_E_PHY_ID_R2) { 771 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 772 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 773 phy_data); 774 if (ret_val) 775 return ret_val; 776 /* Commit the changes. */ 777 ret_val = e1000e_commit_phy(hw); 778 if (ret_val) { 779 e_dbg("Error committing the PHY changes\n"); 780 return ret_val; 781 } 782 } 783 784 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 785 } 786 787 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 788 if (ret_val) 789 return ret_val; 790 791 if ((phy->type == e1000_phy_m88) && 792 (phy->revision < E1000_REVISION_4) && 793 (phy->id != BME1000_E_PHY_ID_R2)) { 794 /* 795 * Force TX_CLK in the Extended PHY Specific Control Register 796 * to 25MHz clock. 797 */ 798 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 799 if (ret_val) 800 return ret_val; 801 802 phy_data |= M88E1000_EPSCR_TX_CLK_25; 803 804 if ((phy->revision == 2) && 805 (phy->id == M88E1111_I_PHY_ID)) { 806 /* 82573L PHY - set the downshift counter to 5x. */ 807 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 808 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 809 } else { 810 /* Configure Master and Slave downshift values */ 811 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 812 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 813 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 814 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 815 } 816 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 817 if (ret_val) 818 return ret_val; 819 } 820 821 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 822 /* Set PHY page 0, register 29 to 0x0003 */ 823 ret_val = e1e_wphy(hw, 29, 0x0003); 824 if (ret_val) 825 return ret_val; 826 827 /* Set PHY page 0, register 30 to 0x0000 */ 828 ret_val = e1e_wphy(hw, 30, 0x0000); 829 if (ret_val) 830 return ret_val; 831 } 832 833 /* Commit the changes. */ 834 ret_val = e1000e_commit_phy(hw); 835 if (ret_val) { 836 e_dbg("Error committing the PHY changes\n"); 837 return ret_val; 838 } 839 840 if (phy->type == e1000_phy_82578) { 841 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 842 if (ret_val) 843 return ret_val; 844 845 /* 82578 PHY - set the downshift count to 1x. */ 846 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 847 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 848 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 849 if (ret_val) 850 return ret_val; 851 } 852 853 return 0; 854 } 855 856 /** 857 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link 858 * @hw: pointer to the HW structure 859 * 860 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 861 * igp PHY's. 862 **/ 863 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) 864 { 865 struct e1000_phy_info *phy = &hw->phy; 866 s32 ret_val; 867 u16 data; 868 869 ret_val = e1000_phy_hw_reset(hw); 870 if (ret_val) { 871 e_dbg("Error resetting the PHY.\n"); 872 return ret_val; 873 } 874 875 /* 876 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 877 * timeout issues when LFS is enabled. 878 */ 879 msleep(100); 880 881 /* disable lplu d0 during driver init */ 882 ret_val = e1000_set_d0_lplu_state(hw, false); 883 if (ret_val) { 884 e_dbg("Error Disabling LPLU D0\n"); 885 return ret_val; 886 } 887 /* Configure mdi-mdix settings */ 888 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); 889 if (ret_val) 890 return ret_val; 891 892 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 893 894 switch (phy->mdix) { 895 case 1: 896 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 897 break; 898 case 2: 899 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 900 break; 901 case 0: 902 default: 903 data |= IGP01E1000_PSCR_AUTO_MDIX; 904 break; 905 } 906 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); 907 if (ret_val) 908 return ret_val; 909 910 /* set auto-master slave resolution settings */ 911 if (hw->mac.autoneg) { 912 /* 913 * when autonegotiation advertisement is only 1000Mbps then we 914 * should disable SmartSpeed and enable Auto MasterSlave 915 * resolution as hardware default. 916 */ 917 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 918 /* Disable SmartSpeed */ 919 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 920 &data); 921 if (ret_val) 922 return ret_val; 923 924 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 925 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 926 data); 927 if (ret_val) 928 return ret_val; 929 930 /* Set auto Master/Slave resolution process */ 931 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); 932 if (ret_val) 933 return ret_val; 934 935 data &= ~CR_1000T_MS_ENABLE; 936 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); 937 if (ret_val) 938 return ret_val; 939 } 940 941 ret_val = e1000_set_master_slave_mode(hw); 942 } 943 944 return ret_val; 945 } 946 947 /** 948 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 949 * @hw: pointer to the HW structure 950 * 951 * Reads the MII auto-neg advertisement register and/or the 1000T control 952 * register and if the PHY is already setup for auto-negotiation, then 953 * return successful. Otherwise, setup advertisement and flow control to 954 * the appropriate values for the wanted auto-negotiation. 955 **/ 956 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 957 { 958 struct e1000_phy_info *phy = &hw->phy; 959 s32 ret_val; 960 u16 mii_autoneg_adv_reg; 961 u16 mii_1000t_ctrl_reg = 0; 962 963 phy->autoneg_advertised &= phy->autoneg_mask; 964 965 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 966 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 967 if (ret_val) 968 return ret_val; 969 970 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 971 /* Read the MII 1000Base-T Control Register (Address 9). */ 972 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 973 if (ret_val) 974 return ret_val; 975 } 976 977 /* 978 * Need to parse both autoneg_advertised and fc and set up 979 * the appropriate PHY registers. First we will parse for 980 * autoneg_advertised software override. Since we can advertise 981 * a plethora of combinations, we need to check each bit 982 * individually. 983 */ 984 985 /* 986 * First we clear all the 10/100 mb speed bits in the Auto-Neg 987 * Advertisement Register (Address 4) and the 1000 mb speed bits in 988 * the 1000Base-T Control Register (Address 9). 989 */ 990 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 991 NWAY_AR_100TX_HD_CAPS | 992 NWAY_AR_10T_FD_CAPS | 993 NWAY_AR_10T_HD_CAPS); 994 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 995 996 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 997 998 /* Do we want to advertise 10 Mb Half Duplex? */ 999 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1000 e_dbg("Advertise 10mb Half duplex\n"); 1001 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1002 } 1003 1004 /* Do we want to advertise 10 Mb Full Duplex? */ 1005 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1006 e_dbg("Advertise 10mb Full duplex\n"); 1007 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1008 } 1009 1010 /* Do we want to advertise 100 Mb Half Duplex? */ 1011 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1012 e_dbg("Advertise 100mb Half duplex\n"); 1013 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1014 } 1015 1016 /* Do we want to advertise 100 Mb Full Duplex? */ 1017 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1018 e_dbg("Advertise 100mb Full duplex\n"); 1019 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1020 } 1021 1022 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1023 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1024 e_dbg("Advertise 1000mb Half duplex request denied!\n"); 1025 1026 /* Do we want to advertise 1000 Mb Full Duplex? */ 1027 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1028 e_dbg("Advertise 1000mb Full duplex\n"); 1029 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1030 } 1031 1032 /* 1033 * Check for a software override of the flow control settings, and 1034 * setup the PHY advertisement registers accordingly. If 1035 * auto-negotiation is enabled, then software will have to set the 1036 * "PAUSE" bits to the correct value in the Auto-Negotiation 1037 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1038 * negotiation. 1039 * 1040 * The possible values of the "fc" parameter are: 1041 * 0: Flow control is completely disabled 1042 * 1: Rx flow control is enabled (we can receive pause frames 1043 * but not send pause frames). 1044 * 2: Tx flow control is enabled (we can send pause frames 1045 * but we do not support receiving pause frames). 1046 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1047 * other: No software override. The flow control configuration 1048 * in the EEPROM is used. 1049 */ 1050 switch (hw->fc.current_mode) { 1051 case e1000_fc_none: 1052 /* 1053 * Flow control (Rx & Tx) is completely disabled by a 1054 * software over-ride. 1055 */ 1056 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1057 break; 1058 case e1000_fc_rx_pause: 1059 /* 1060 * Rx Flow control is enabled, and Tx Flow control is 1061 * disabled, by a software over-ride. 1062 * 1063 * Since there really isn't a way to advertise that we are 1064 * capable of Rx Pause ONLY, we will advertise that we 1065 * support both symmetric and asymmetric Rx PAUSE. Later 1066 * (in e1000e_config_fc_after_link_up) we will disable the 1067 * hw's ability to send PAUSE frames. 1068 */ 1069 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1070 break; 1071 case e1000_fc_tx_pause: 1072 /* 1073 * Tx Flow control is enabled, and Rx Flow control is 1074 * disabled, by a software over-ride. 1075 */ 1076 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1077 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1078 break; 1079 case e1000_fc_full: 1080 /* 1081 * Flow control (both Rx and Tx) is enabled by a software 1082 * over-ride. 1083 */ 1084 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1085 break; 1086 default: 1087 e_dbg("Flow control param set incorrectly\n"); 1088 return -E1000_ERR_CONFIG; 1089 } 1090 1091 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1092 if (ret_val) 1093 return ret_val; 1094 1095 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1096 1097 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1098 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1099 1100 return ret_val; 1101 } 1102 1103 /** 1104 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1105 * @hw: pointer to the HW structure 1106 * 1107 * Performs initial bounds checking on autoneg advertisement parameter, then 1108 * configure to advertise the full capability. Setup the PHY to autoneg 1109 * and restart the negotiation process between the link partner. If 1110 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1111 **/ 1112 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1113 { 1114 struct e1000_phy_info *phy = &hw->phy; 1115 s32 ret_val; 1116 u16 phy_ctrl; 1117 1118 /* 1119 * Perform some bounds checking on the autoneg advertisement 1120 * parameter. 1121 */ 1122 phy->autoneg_advertised &= phy->autoneg_mask; 1123 1124 /* 1125 * If autoneg_advertised is zero, we assume it was not defaulted 1126 * by the calling code so we set to advertise full capability. 1127 */ 1128 if (!phy->autoneg_advertised) 1129 phy->autoneg_advertised = phy->autoneg_mask; 1130 1131 e_dbg("Reconfiguring auto-neg advertisement params\n"); 1132 ret_val = e1000_phy_setup_autoneg(hw); 1133 if (ret_val) { 1134 e_dbg("Error Setting up Auto-Negotiation\n"); 1135 return ret_val; 1136 } 1137 e_dbg("Restarting Auto-Neg\n"); 1138 1139 /* 1140 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1141 * the Auto Neg Restart bit in the PHY control register. 1142 */ 1143 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); 1144 if (ret_val) 1145 return ret_val; 1146 1147 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1148 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); 1149 if (ret_val) 1150 return ret_val; 1151 1152 /* 1153 * Does the user want to wait for Auto-Neg to complete here, or 1154 * check at a later time (for example, callback routine). 1155 */ 1156 if (phy->autoneg_wait_to_complete) { 1157 ret_val = e1000_wait_autoneg(hw); 1158 if (ret_val) { 1159 e_dbg("Error while waiting for autoneg to complete\n"); 1160 return ret_val; 1161 } 1162 } 1163 1164 hw->mac.get_link_status = true; 1165 1166 return ret_val; 1167 } 1168 1169 /** 1170 * e1000e_setup_copper_link - Configure copper link settings 1171 * @hw: pointer to the HW structure 1172 * 1173 * Calls the appropriate function to configure the link for auto-neg or forced 1174 * speed and duplex. Then we check for link, once link is established calls 1175 * to configure collision distance and flow control are called. If link is 1176 * not established, we return -E1000_ERR_PHY (-2). 1177 **/ 1178 s32 e1000e_setup_copper_link(struct e1000_hw *hw) 1179 { 1180 s32 ret_val; 1181 bool link; 1182 1183 if (hw->mac.autoneg) { 1184 /* 1185 * Setup autoneg and flow control advertisement and perform 1186 * autonegotiation. 1187 */ 1188 ret_val = e1000_copper_link_autoneg(hw); 1189 if (ret_val) 1190 return ret_val; 1191 } else { 1192 /* 1193 * PHY will be set to 10H, 10F, 100H or 100F 1194 * depending on user settings. 1195 */ 1196 e_dbg("Forcing Speed and Duplex\n"); 1197 ret_val = e1000_phy_force_speed_duplex(hw); 1198 if (ret_val) { 1199 e_dbg("Error Forcing Speed and Duplex\n"); 1200 return ret_val; 1201 } 1202 } 1203 1204 /* 1205 * Check link status. Wait up to 100 microseconds for link to become 1206 * valid. 1207 */ 1208 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1209 &link); 1210 if (ret_val) 1211 return ret_val; 1212 1213 if (link) { 1214 e_dbg("Valid link established!!!\n"); 1215 hw->mac.ops.config_collision_dist(hw); 1216 ret_val = e1000e_config_fc_after_link_up(hw); 1217 } else { 1218 e_dbg("Unable to establish link!!!\n"); 1219 } 1220 1221 return ret_val; 1222 } 1223 1224 /** 1225 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1226 * @hw: pointer to the HW structure 1227 * 1228 * Calls the PHY setup function to force speed and duplex. Clears the 1229 * auto-crossover to force MDI manually. Waits for link and returns 1230 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1231 **/ 1232 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1233 { 1234 struct e1000_phy_info *phy = &hw->phy; 1235 s32 ret_val; 1236 u16 phy_data; 1237 bool link; 1238 1239 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 1240 if (ret_val) 1241 return ret_val; 1242 1243 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 1244 1245 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); 1246 if (ret_val) 1247 return ret_val; 1248 1249 /* 1250 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1251 * forced whenever speed and duplex are forced. 1252 */ 1253 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1254 if (ret_val) 1255 return ret_val; 1256 1257 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1258 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1259 1260 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1261 if (ret_val) 1262 return ret_val; 1263 1264 e_dbg("IGP PSCR: %X\n", phy_data); 1265 1266 udelay(1); 1267 1268 if (phy->autoneg_wait_to_complete) { 1269 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1270 1271 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1272 100000, &link); 1273 if (ret_val) 1274 return ret_val; 1275 1276 if (!link) 1277 e_dbg("Link taking longer than expected.\n"); 1278 1279 /* Try once more */ 1280 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1281 100000, &link); 1282 } 1283 1284 return ret_val; 1285 } 1286 1287 /** 1288 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1289 * @hw: pointer to the HW structure 1290 * 1291 * Calls the PHY setup function to force speed and duplex. Clears the 1292 * auto-crossover to force MDI manually. Resets the PHY to commit the 1293 * changes. If time expires while waiting for link up, we reset the DSP. 1294 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1295 * successful completion, else return corresponding error code. 1296 **/ 1297 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1298 { 1299 struct e1000_phy_info *phy = &hw->phy; 1300 s32 ret_val; 1301 u16 phy_data; 1302 bool link; 1303 1304 /* 1305 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1306 * forced whenever speed and duplex are forced. 1307 */ 1308 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1309 if (ret_val) 1310 return ret_val; 1311 1312 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1313 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1314 if (ret_val) 1315 return ret_val; 1316 1317 e_dbg("M88E1000 PSCR: %X\n", phy_data); 1318 1319 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 1320 if (ret_val) 1321 return ret_val; 1322 1323 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 1324 1325 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); 1326 if (ret_val) 1327 return ret_val; 1328 1329 /* Reset the phy to commit changes. */ 1330 ret_val = e1000e_commit_phy(hw); 1331 if (ret_val) 1332 return ret_val; 1333 1334 if (phy->autoneg_wait_to_complete) { 1335 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1336 1337 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1338 100000, &link); 1339 if (ret_val) 1340 return ret_val; 1341 1342 if (!link) { 1343 if (hw->phy.type != e1000_phy_m88) { 1344 e_dbg("Link taking longer than expected.\n"); 1345 } else { 1346 /* 1347 * We didn't get link. 1348 * Reset the DSP and cross our fingers. 1349 */ 1350 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 1351 0x001d); 1352 if (ret_val) 1353 return ret_val; 1354 ret_val = e1000e_phy_reset_dsp(hw); 1355 if (ret_val) 1356 return ret_val; 1357 } 1358 } 1359 1360 /* Try once more */ 1361 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1362 100000, &link); 1363 if (ret_val) 1364 return ret_val; 1365 } 1366 1367 if (hw->phy.type != e1000_phy_m88) 1368 return 0; 1369 1370 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1371 if (ret_val) 1372 return ret_val; 1373 1374 /* 1375 * Resetting the phy means we need to re-force TX_CLK in the 1376 * Extended PHY Specific Control Register to 25MHz clock from 1377 * the reset value of 2.5MHz. 1378 */ 1379 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1380 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1381 if (ret_val) 1382 return ret_val; 1383 1384 /* 1385 * In addition, we must re-enable CRS on Tx for both half and full 1386 * duplex. 1387 */ 1388 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1389 if (ret_val) 1390 return ret_val; 1391 1392 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1393 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1394 1395 return ret_val; 1396 } 1397 1398 /** 1399 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1400 * @hw: pointer to the HW structure 1401 * 1402 * Forces the speed and duplex settings of the PHY. 1403 * This is a function pointer entry point only called by 1404 * PHY setup routines. 1405 **/ 1406 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1407 { 1408 struct e1000_phy_info *phy = &hw->phy; 1409 s32 ret_val; 1410 u16 data; 1411 bool link; 1412 1413 ret_val = e1e_rphy(hw, PHY_CONTROL, &data); 1414 if (ret_val) 1415 return ret_val; 1416 1417 e1000e_phy_force_speed_duplex_setup(hw, &data); 1418 1419 ret_val = e1e_wphy(hw, PHY_CONTROL, data); 1420 if (ret_val) 1421 return ret_val; 1422 1423 /* Disable MDI-X support for 10/100 */ 1424 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 1425 if (ret_val) 1426 return ret_val; 1427 1428 data &= ~IFE_PMC_AUTO_MDIX; 1429 data &= ~IFE_PMC_FORCE_MDIX; 1430 1431 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); 1432 if (ret_val) 1433 return ret_val; 1434 1435 e_dbg("IFE PMC: %X\n", data); 1436 1437 udelay(1); 1438 1439 if (phy->autoneg_wait_to_complete) { 1440 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); 1441 1442 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1443 100000, &link); 1444 if (ret_val) 1445 return ret_val; 1446 1447 if (!link) 1448 e_dbg("Link taking longer than expected.\n"); 1449 1450 /* Try once more */ 1451 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1452 100000, &link); 1453 if (ret_val) 1454 return ret_val; 1455 } 1456 1457 return 0; 1458 } 1459 1460 /** 1461 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1462 * @hw: pointer to the HW structure 1463 * @phy_ctrl: pointer to current value of PHY_CONTROL 1464 * 1465 * Forces speed and duplex on the PHY by doing the following: disable flow 1466 * control, force speed/duplex on the MAC, disable auto speed detection, 1467 * disable auto-negotiation, configure duplex, configure speed, configure 1468 * the collision distance, write configuration to CTRL register. The 1469 * caller must write to the PHY_CONTROL register for these settings to 1470 * take affect. 1471 **/ 1472 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1473 { 1474 struct e1000_mac_info *mac = &hw->mac; 1475 u32 ctrl; 1476 1477 /* Turn off flow control when forcing speed/duplex */ 1478 hw->fc.current_mode = e1000_fc_none; 1479 1480 /* Force speed/duplex on the mac */ 1481 ctrl = er32(CTRL); 1482 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1483 ctrl &= ~E1000_CTRL_SPD_SEL; 1484 1485 /* Disable Auto Speed Detection */ 1486 ctrl &= ~E1000_CTRL_ASDE; 1487 1488 /* Disable autoneg on the phy */ 1489 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1490 1491 /* Forcing Full or Half Duplex? */ 1492 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1493 ctrl &= ~E1000_CTRL_FD; 1494 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1495 e_dbg("Half Duplex\n"); 1496 } else { 1497 ctrl |= E1000_CTRL_FD; 1498 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1499 e_dbg("Full Duplex\n"); 1500 } 1501 1502 /* Forcing 10mb or 100mb? */ 1503 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1504 ctrl |= E1000_CTRL_SPD_100; 1505 *phy_ctrl |= MII_CR_SPEED_100; 1506 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1507 e_dbg("Forcing 100mb\n"); 1508 } else { 1509 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1510 *phy_ctrl |= MII_CR_SPEED_10; 1511 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1512 e_dbg("Forcing 10mb\n"); 1513 } 1514 1515 hw->mac.ops.config_collision_dist(hw); 1516 1517 ew32(CTRL, ctrl); 1518 } 1519 1520 /** 1521 * e1000e_set_d3_lplu_state - Sets low power link up state for D3 1522 * @hw: pointer to the HW structure 1523 * @active: boolean used to enable/disable lplu 1524 * 1525 * Success returns 0, Failure returns 1 1526 * 1527 * The low power link up (lplu) state is set to the power management level D3 1528 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1529 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1530 * is used during Dx states where the power conservation is most important. 1531 * During driver activity, SmartSpeed should be enabled so performance is 1532 * maintained. 1533 **/ 1534 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1535 { 1536 struct e1000_phy_info *phy = &hw->phy; 1537 s32 ret_val; 1538 u16 data; 1539 1540 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1541 if (ret_val) 1542 return ret_val; 1543 1544 if (!active) { 1545 data &= ~IGP02E1000_PM_D3_LPLU; 1546 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1547 if (ret_val) 1548 return ret_val; 1549 /* 1550 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1551 * during Dx states where the power conservation is most 1552 * important. During driver activity we should enable 1553 * SmartSpeed, so performance is maintained. 1554 */ 1555 if (phy->smart_speed == e1000_smart_speed_on) { 1556 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1557 &data); 1558 if (ret_val) 1559 return ret_val; 1560 1561 data |= IGP01E1000_PSCFR_SMART_SPEED; 1562 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1563 data); 1564 if (ret_val) 1565 return ret_val; 1566 } else if (phy->smart_speed == e1000_smart_speed_off) { 1567 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1568 &data); 1569 if (ret_val) 1570 return ret_val; 1571 1572 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1573 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1574 data); 1575 if (ret_val) 1576 return ret_val; 1577 } 1578 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1579 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1580 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1581 data |= IGP02E1000_PM_D3_LPLU; 1582 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1583 if (ret_val) 1584 return ret_val; 1585 1586 /* When LPLU is enabled, we should disable SmartSpeed */ 1587 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 1588 if (ret_val) 1589 return ret_val; 1590 1591 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1592 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 1593 } 1594 1595 return ret_val; 1596 } 1597 1598 /** 1599 * e1000e_check_downshift - Checks whether a downshift in speed occurred 1600 * @hw: pointer to the HW structure 1601 * 1602 * Success returns 0, Failure returns 1 1603 * 1604 * A downshift is detected by querying the PHY link health. 1605 **/ 1606 s32 e1000e_check_downshift(struct e1000_hw *hw) 1607 { 1608 struct e1000_phy_info *phy = &hw->phy; 1609 s32 ret_val; 1610 u16 phy_data, offset, mask; 1611 1612 switch (phy->type) { 1613 case e1000_phy_m88: 1614 case e1000_phy_gg82563: 1615 case e1000_phy_bm: 1616 case e1000_phy_82578: 1617 offset = M88E1000_PHY_SPEC_STATUS; 1618 mask = M88E1000_PSSR_DOWNSHIFT; 1619 break; 1620 case e1000_phy_igp_2: 1621 case e1000_phy_igp_3: 1622 offset = IGP01E1000_PHY_LINK_HEALTH; 1623 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1624 break; 1625 default: 1626 /* speed downshift not supported */ 1627 phy->speed_downgraded = false; 1628 return 0; 1629 } 1630 1631 ret_val = e1e_rphy(hw, offset, &phy_data); 1632 1633 if (!ret_val) 1634 phy->speed_downgraded = !!(phy_data & mask); 1635 1636 return ret_val; 1637 } 1638 1639 /** 1640 * e1000_check_polarity_m88 - Checks the polarity. 1641 * @hw: pointer to the HW structure 1642 * 1643 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1644 * 1645 * Polarity is determined based on the PHY specific status register. 1646 **/ 1647 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1648 { 1649 struct e1000_phy_info *phy = &hw->phy; 1650 s32 ret_val; 1651 u16 data; 1652 1653 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); 1654 1655 if (!ret_val) 1656 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1657 ? e1000_rev_polarity_reversed 1658 : e1000_rev_polarity_normal; 1659 1660 return ret_val; 1661 } 1662 1663 /** 1664 * e1000_check_polarity_igp - Checks the polarity. 1665 * @hw: pointer to the HW structure 1666 * 1667 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1668 * 1669 * Polarity is determined based on the PHY port status register, and the 1670 * current speed (since there is no polarity at 100Mbps). 1671 **/ 1672 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1673 { 1674 struct e1000_phy_info *phy = &hw->phy; 1675 s32 ret_val; 1676 u16 data, offset, mask; 1677 1678 /* 1679 * Polarity is determined based on the speed of 1680 * our connection. 1681 */ 1682 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1683 if (ret_val) 1684 return ret_val; 1685 1686 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1687 IGP01E1000_PSSR_SPEED_1000MBPS) { 1688 offset = IGP01E1000_PHY_PCS_INIT_REG; 1689 mask = IGP01E1000_PHY_POLARITY_MASK; 1690 } else { 1691 /* 1692 * This really only applies to 10Mbps since 1693 * there is no polarity for 100Mbps (always 0). 1694 */ 1695 offset = IGP01E1000_PHY_PORT_STATUS; 1696 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1697 } 1698 1699 ret_val = e1e_rphy(hw, offset, &data); 1700 1701 if (!ret_val) 1702 phy->cable_polarity = (data & mask) 1703 ? e1000_rev_polarity_reversed 1704 : e1000_rev_polarity_normal; 1705 1706 return ret_val; 1707 } 1708 1709 /** 1710 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1711 * @hw: pointer to the HW structure 1712 * 1713 * Polarity is determined on the polarity reversal feature being enabled. 1714 **/ 1715 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 1716 { 1717 struct e1000_phy_info *phy = &hw->phy; 1718 s32 ret_val; 1719 u16 phy_data, offset, mask; 1720 1721 /* 1722 * Polarity is determined based on the reversal feature being enabled. 1723 */ 1724 if (phy->polarity_correction) { 1725 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1726 mask = IFE_PESC_POLARITY_REVERSED; 1727 } else { 1728 offset = IFE_PHY_SPECIAL_CONTROL; 1729 mask = IFE_PSC_FORCE_POLARITY; 1730 } 1731 1732 ret_val = e1e_rphy(hw, offset, &phy_data); 1733 1734 if (!ret_val) 1735 phy->cable_polarity = (phy_data & mask) 1736 ? e1000_rev_polarity_reversed 1737 : e1000_rev_polarity_normal; 1738 1739 return ret_val; 1740 } 1741 1742 /** 1743 * e1000_wait_autoneg - Wait for auto-neg completion 1744 * @hw: pointer to the HW structure 1745 * 1746 * Waits for auto-negotiation to complete or for the auto-negotiation time 1747 * limit to expire, which ever happens first. 1748 **/ 1749 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 1750 { 1751 s32 ret_val = 0; 1752 u16 i, phy_status; 1753 1754 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1755 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1756 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1757 if (ret_val) 1758 break; 1759 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1760 if (ret_val) 1761 break; 1762 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1763 break; 1764 msleep(100); 1765 } 1766 1767 /* 1768 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1769 * has completed. 1770 */ 1771 return ret_val; 1772 } 1773 1774 /** 1775 * e1000e_phy_has_link_generic - Polls PHY for link 1776 * @hw: pointer to the HW structure 1777 * @iterations: number of times to poll for link 1778 * @usec_interval: delay between polling attempts 1779 * @success: pointer to whether polling was successful or not 1780 * 1781 * Polls the PHY status register for link, 'iterations' number of times. 1782 **/ 1783 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1784 u32 usec_interval, bool *success) 1785 { 1786 s32 ret_val = 0; 1787 u16 i, phy_status; 1788 1789 for (i = 0; i < iterations; i++) { 1790 /* 1791 * Some PHYs require the PHY_STATUS register to be read 1792 * twice due to the link bit being sticky. No harm doing 1793 * it across the board. 1794 */ 1795 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1796 if (ret_val) 1797 /* 1798 * If the first read fails, another entity may have 1799 * ownership of the resources, wait and try again to 1800 * see if they have relinquished the resources yet. 1801 */ 1802 udelay(usec_interval); 1803 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1804 if (ret_val) 1805 break; 1806 if (phy_status & MII_SR_LINK_STATUS) 1807 break; 1808 if (usec_interval >= 1000) 1809 mdelay(usec_interval/1000); 1810 else 1811 udelay(usec_interval); 1812 } 1813 1814 *success = (i < iterations); 1815 1816 return ret_val; 1817 } 1818 1819 /** 1820 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY 1821 * @hw: pointer to the HW structure 1822 * 1823 * Reads the PHY specific status register to retrieve the cable length 1824 * information. The cable length is determined by averaging the minimum and 1825 * maximum values to get the "average" cable length. The m88 PHY has four 1826 * possible cable length values, which are: 1827 * Register Value Cable Length 1828 * 0 < 50 meters 1829 * 1 50 - 80 meters 1830 * 2 80 - 110 meters 1831 * 3 110 - 140 meters 1832 * 4 > 140 meters 1833 **/ 1834 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) 1835 { 1836 struct e1000_phy_info *phy = &hw->phy; 1837 s32 ret_val; 1838 u16 phy_data, index; 1839 1840 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1841 if (ret_val) 1842 return ret_val; 1843 1844 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1845 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1846 1847 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 1848 return -E1000_ERR_PHY; 1849 1850 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1851 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1852 1853 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1854 1855 return 0; 1856 } 1857 1858 /** 1859 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1860 * @hw: pointer to the HW structure 1861 * 1862 * The automatic gain control (agc) normalizes the amplitude of the 1863 * received signal, adjusting for the attenuation produced by the 1864 * cable. By reading the AGC registers, which represent the 1865 * combination of coarse and fine gain value, the value can be put 1866 * into a lookup table to obtain the approximate cable length 1867 * for each channel. 1868 **/ 1869 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) 1870 { 1871 struct e1000_phy_info *phy = &hw->phy; 1872 s32 ret_val; 1873 u16 phy_data, i, agc_value = 0; 1874 u16 cur_agc_index, max_agc_index = 0; 1875 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1876 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1877 IGP02E1000_PHY_AGC_A, 1878 IGP02E1000_PHY_AGC_B, 1879 IGP02E1000_PHY_AGC_C, 1880 IGP02E1000_PHY_AGC_D 1881 }; 1882 1883 /* Read the AGC registers for all channels */ 1884 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1885 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); 1886 if (ret_val) 1887 return ret_val; 1888 1889 /* 1890 * Getting bits 15:9, which represent the combination of 1891 * coarse and fine gain values. The result is a number 1892 * that can be put into the lookup table to obtain the 1893 * approximate cable length. 1894 */ 1895 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1896 IGP02E1000_AGC_LENGTH_MASK; 1897 1898 /* Array index bound check. */ 1899 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1900 (cur_agc_index == 0)) 1901 return -E1000_ERR_PHY; 1902 1903 /* Remove min & max AGC values from calculation. */ 1904 if (e1000_igp_2_cable_length_table[min_agc_index] > 1905 e1000_igp_2_cable_length_table[cur_agc_index]) 1906 min_agc_index = cur_agc_index; 1907 if (e1000_igp_2_cable_length_table[max_agc_index] < 1908 e1000_igp_2_cable_length_table[cur_agc_index]) 1909 max_agc_index = cur_agc_index; 1910 1911 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1912 } 1913 1914 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1915 e1000_igp_2_cable_length_table[max_agc_index]); 1916 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1917 1918 /* Calculate cable length with the error range of +/- 10 meters. */ 1919 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1920 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1921 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1922 1923 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1924 1925 return 0; 1926 } 1927 1928 /** 1929 * e1000e_get_phy_info_m88 - Retrieve PHY information 1930 * @hw: pointer to the HW structure 1931 * 1932 * Valid for only copper links. Read the PHY status register (sticky read) 1933 * to verify that link is up. Read the PHY special control register to 1934 * determine the polarity and 10base-T extended distance. Read the PHY 1935 * special status register to determine MDI/MDIx and current speed. If 1936 * speed is 1000, then determine cable length, local and remote receiver. 1937 **/ 1938 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) 1939 { 1940 struct e1000_phy_info *phy = &hw->phy; 1941 s32 ret_val; 1942 u16 phy_data; 1943 bool link; 1944 1945 if (phy->media_type != e1000_media_type_copper) { 1946 e_dbg("Phy info is only valid for copper media\n"); 1947 return -E1000_ERR_CONFIG; 1948 } 1949 1950 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1951 if (ret_val) 1952 return ret_val; 1953 1954 if (!link) { 1955 e_dbg("Phy info is only valid if link is up\n"); 1956 return -E1000_ERR_CONFIG; 1957 } 1958 1959 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1960 if (ret_val) 1961 return ret_val; 1962 1963 phy->polarity_correction = !!(phy_data & 1964 M88E1000_PSCR_POLARITY_REVERSAL); 1965 1966 ret_val = e1000_check_polarity_m88(hw); 1967 if (ret_val) 1968 return ret_val; 1969 1970 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1971 if (ret_val) 1972 return ret_val; 1973 1974 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 1975 1976 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1977 ret_val = e1000_get_cable_length(hw); 1978 if (ret_val) 1979 return ret_val; 1980 1981 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); 1982 if (ret_val) 1983 return ret_val; 1984 1985 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1986 ? e1000_1000t_rx_status_ok 1987 : e1000_1000t_rx_status_not_ok; 1988 1989 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1990 ? e1000_1000t_rx_status_ok 1991 : e1000_1000t_rx_status_not_ok; 1992 } else { 1993 /* Set values to "undefined" */ 1994 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1995 phy->local_rx = e1000_1000t_rx_status_undefined; 1996 phy->remote_rx = e1000_1000t_rx_status_undefined; 1997 } 1998 1999 return ret_val; 2000 } 2001 2002 /** 2003 * e1000e_get_phy_info_igp - Retrieve igp PHY information 2004 * @hw: pointer to the HW structure 2005 * 2006 * Read PHY status to determine if link is up. If link is up, then 2007 * set/determine 10base-T extended distance and polarity correction. Read 2008 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2009 * determine on the cable length, local and remote receiver. 2010 **/ 2011 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) 2012 { 2013 struct e1000_phy_info *phy = &hw->phy; 2014 s32 ret_val; 2015 u16 data; 2016 bool link; 2017 2018 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 2019 if (ret_val) 2020 return ret_val; 2021 2022 if (!link) { 2023 e_dbg("Phy info is only valid if link is up\n"); 2024 return -E1000_ERR_CONFIG; 2025 } 2026 2027 phy->polarity_correction = true; 2028 2029 ret_val = e1000_check_polarity_igp(hw); 2030 if (ret_val) 2031 return ret_val; 2032 2033 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2034 if (ret_val) 2035 return ret_val; 2036 2037 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 2038 2039 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2040 IGP01E1000_PSSR_SPEED_1000MBPS) { 2041 ret_val = e1000_get_cable_length(hw); 2042 if (ret_val) 2043 return ret_val; 2044 2045 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); 2046 if (ret_val) 2047 return ret_val; 2048 2049 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2050 ? e1000_1000t_rx_status_ok 2051 : e1000_1000t_rx_status_not_ok; 2052 2053 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2054 ? e1000_1000t_rx_status_ok 2055 : e1000_1000t_rx_status_not_ok; 2056 } else { 2057 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2058 phy->local_rx = e1000_1000t_rx_status_undefined; 2059 phy->remote_rx = e1000_1000t_rx_status_undefined; 2060 } 2061 2062 return ret_val; 2063 } 2064 2065 /** 2066 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2067 * @hw: pointer to the HW structure 2068 * 2069 * Populates "phy" structure with various feature states. 2070 **/ 2071 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2072 { 2073 struct e1000_phy_info *phy = &hw->phy; 2074 s32 ret_val; 2075 u16 data; 2076 bool link; 2077 2078 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 2079 if (ret_val) 2080 return ret_val; 2081 2082 if (!link) { 2083 e_dbg("Phy info is only valid if link is up\n"); 2084 return -E1000_ERR_CONFIG; 2085 } 2086 2087 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2088 if (ret_val) 2089 return ret_val; 2090 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2091 2092 if (phy->polarity_correction) { 2093 ret_val = e1000_check_polarity_ife(hw); 2094 if (ret_val) 2095 return ret_val; 2096 } else { 2097 /* Polarity is forced */ 2098 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 2099 ? e1000_rev_polarity_reversed 2100 : e1000_rev_polarity_normal; 2101 } 2102 2103 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 2104 if (ret_val) 2105 return ret_val; 2106 2107 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2108 2109 /* The following parameters are undefined for 10/100 operation. */ 2110 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2111 phy->local_rx = e1000_1000t_rx_status_undefined; 2112 phy->remote_rx = e1000_1000t_rx_status_undefined; 2113 2114 return 0; 2115 } 2116 2117 /** 2118 * e1000e_phy_sw_reset - PHY software reset 2119 * @hw: pointer to the HW structure 2120 * 2121 * Does a software reset of the PHY by reading the PHY control register and 2122 * setting/write the control register reset bit to the PHY. 2123 **/ 2124 s32 e1000e_phy_sw_reset(struct e1000_hw *hw) 2125 { 2126 s32 ret_val; 2127 u16 phy_ctrl; 2128 2129 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); 2130 if (ret_val) 2131 return ret_val; 2132 2133 phy_ctrl |= MII_CR_RESET; 2134 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); 2135 if (ret_val) 2136 return ret_val; 2137 2138 udelay(1); 2139 2140 return ret_val; 2141 } 2142 2143 /** 2144 * e1000e_phy_hw_reset_generic - PHY hardware reset 2145 * @hw: pointer to the HW structure 2146 * 2147 * Verify the reset block is not blocking us from resetting. Acquire 2148 * semaphore (if necessary) and read/set/write the device control reset 2149 * bit in the PHY. Wait the appropriate delay time for the device to 2150 * reset and release the semaphore (if necessary). 2151 **/ 2152 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) 2153 { 2154 struct e1000_phy_info *phy = &hw->phy; 2155 s32 ret_val; 2156 u32 ctrl; 2157 2158 if (phy->ops.check_reset_block) { 2159 ret_val = phy->ops.check_reset_block(hw); 2160 if (ret_val) 2161 return 0; 2162 } 2163 2164 ret_val = phy->ops.acquire(hw); 2165 if (ret_val) 2166 return ret_val; 2167 2168 ctrl = er32(CTRL); 2169 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 2170 e1e_flush(); 2171 2172 udelay(phy->reset_delay_us); 2173 2174 ew32(CTRL, ctrl); 2175 e1e_flush(); 2176 2177 udelay(150); 2178 2179 phy->ops.release(hw); 2180 2181 return e1000_get_phy_cfg_done(hw); 2182 } 2183 2184 /** 2185 * e1000e_get_cfg_done - Generic configuration done 2186 * @hw: pointer to the HW structure 2187 * 2188 * Generic function to wait 10 milli-seconds for configuration to complete 2189 * and return success. 2190 **/ 2191 s32 e1000e_get_cfg_done(struct e1000_hw *hw) 2192 { 2193 mdelay(10); 2194 2195 return 0; 2196 } 2197 2198 /** 2199 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY 2200 * @hw: pointer to the HW structure 2201 * 2202 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2203 **/ 2204 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) 2205 { 2206 e_dbg("Running IGP 3 PHY init script\n"); 2207 2208 /* PHY init IGP 3 */ 2209 /* Enable rise/fall, 10-mode work in class-A */ 2210 e1e_wphy(hw, 0x2F5B, 0x9018); 2211 /* Remove all caps from Replica path filter */ 2212 e1e_wphy(hw, 0x2F52, 0x0000); 2213 /* Bias trimming for ADC, AFE and Driver (Default) */ 2214 e1e_wphy(hw, 0x2FB1, 0x8B24); 2215 /* Increase Hybrid poly bias */ 2216 e1e_wphy(hw, 0x2FB2, 0xF8F0); 2217 /* Add 4% to Tx amplitude in Gig mode */ 2218 e1e_wphy(hw, 0x2010, 0x10B0); 2219 /* Disable trimming (TTT) */ 2220 e1e_wphy(hw, 0x2011, 0x0000); 2221 /* Poly DC correction to 94.6% + 2% for all channels */ 2222 e1e_wphy(hw, 0x20DD, 0x249A); 2223 /* ABS DC correction to 95.9% */ 2224 e1e_wphy(hw, 0x20DE, 0x00D3); 2225 /* BG temp curve trim */ 2226 e1e_wphy(hw, 0x28B4, 0x04CE); 2227 /* Increasing ADC OPAMP stage 1 currents to max */ 2228 e1e_wphy(hw, 0x2F70, 0x29E4); 2229 /* Force 1000 ( required for enabling PHY regs configuration) */ 2230 e1e_wphy(hw, 0x0000, 0x0140); 2231 /* Set upd_freq to 6 */ 2232 e1e_wphy(hw, 0x1F30, 0x1606); 2233 /* Disable NPDFE */ 2234 e1e_wphy(hw, 0x1F31, 0xB814); 2235 /* Disable adaptive fixed FFE (Default) */ 2236 e1e_wphy(hw, 0x1F35, 0x002A); 2237 /* Enable FFE hysteresis */ 2238 e1e_wphy(hw, 0x1F3E, 0x0067); 2239 /* Fixed FFE for short cable lengths */ 2240 e1e_wphy(hw, 0x1F54, 0x0065); 2241 /* Fixed FFE for medium cable lengths */ 2242 e1e_wphy(hw, 0x1F55, 0x002A); 2243 /* Fixed FFE for long cable lengths */ 2244 e1e_wphy(hw, 0x1F56, 0x002A); 2245 /* Enable Adaptive Clip Threshold */ 2246 e1e_wphy(hw, 0x1F72, 0x3FB0); 2247 /* AHT reset limit to 1 */ 2248 e1e_wphy(hw, 0x1F76, 0xC0FF); 2249 /* Set AHT master delay to 127 msec */ 2250 e1e_wphy(hw, 0x1F77, 0x1DEC); 2251 /* Set scan bits for AHT */ 2252 e1e_wphy(hw, 0x1F78, 0xF9EF); 2253 /* Set AHT Preset bits */ 2254 e1e_wphy(hw, 0x1F79, 0x0210); 2255 /* Change integ_factor of channel A to 3 */ 2256 e1e_wphy(hw, 0x1895, 0x0003); 2257 /* Change prop_factor of channels BCD to 8 */ 2258 e1e_wphy(hw, 0x1796, 0x0008); 2259 /* Change cg_icount + enable integbp for channels BCD */ 2260 e1e_wphy(hw, 0x1798, 0xD008); 2261 /* 2262 * Change cg_icount + enable integbp + change prop_factor_master 2263 * to 8 for channel A 2264 */ 2265 e1e_wphy(hw, 0x1898, 0xD918); 2266 /* Disable AHT in Slave mode on channel A */ 2267 e1e_wphy(hw, 0x187A, 0x0800); 2268 /* 2269 * Enable LPLU and disable AN to 1000 in non-D0a states, 2270 * Enable SPD+B2B 2271 */ 2272 e1e_wphy(hw, 0x0019, 0x008D); 2273 /* Enable restart AN on an1000_dis change */ 2274 e1e_wphy(hw, 0x001B, 0x2080); 2275 /* Enable wh_fifo read clock in 10/100 modes */ 2276 e1e_wphy(hw, 0x0014, 0x0045); 2277 /* Restart AN, Speed selection is 1000 */ 2278 e1e_wphy(hw, 0x0000, 0x1340); 2279 2280 return 0; 2281 } 2282 2283 /* Internal function pointers */ 2284 2285 /** 2286 * e1000_get_phy_cfg_done - Generic PHY configuration done 2287 * @hw: pointer to the HW structure 2288 * 2289 * Return success if silicon family did not implement a family specific 2290 * get_cfg_done function. 2291 **/ 2292 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 2293 { 2294 if (hw->phy.ops.get_cfg_done) 2295 return hw->phy.ops.get_cfg_done(hw); 2296 2297 return 0; 2298 } 2299 2300 /** 2301 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex 2302 * @hw: pointer to the HW structure 2303 * 2304 * When the silicon family has not implemented a forced speed/duplex 2305 * function for the PHY, simply return 0. 2306 **/ 2307 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 2308 { 2309 if (hw->phy.ops.force_speed_duplex) 2310 return hw->phy.ops.force_speed_duplex(hw); 2311 2312 return 0; 2313 } 2314 2315 /** 2316 * e1000e_get_phy_type_from_id - Get PHY type from id 2317 * @phy_id: phy_id read from the phy 2318 * 2319 * Returns the phy type from the id. 2320 **/ 2321 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) 2322 { 2323 enum e1000_phy_type phy_type = e1000_phy_unknown; 2324 2325 switch (phy_id) { 2326 case M88E1000_I_PHY_ID: 2327 case M88E1000_E_PHY_ID: 2328 case M88E1111_I_PHY_ID: 2329 case M88E1011_I_PHY_ID: 2330 phy_type = e1000_phy_m88; 2331 break; 2332 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2333 phy_type = e1000_phy_igp_2; 2334 break; 2335 case GG82563_E_PHY_ID: 2336 phy_type = e1000_phy_gg82563; 2337 break; 2338 case IGP03E1000_E_PHY_ID: 2339 phy_type = e1000_phy_igp_3; 2340 break; 2341 case IFE_E_PHY_ID: 2342 case IFE_PLUS_E_PHY_ID: 2343 case IFE_C_E_PHY_ID: 2344 phy_type = e1000_phy_ife; 2345 break; 2346 case BME1000_E_PHY_ID: 2347 case BME1000_E_PHY_ID_R2: 2348 phy_type = e1000_phy_bm; 2349 break; 2350 case I82578_E_PHY_ID: 2351 phy_type = e1000_phy_82578; 2352 break; 2353 case I82577_E_PHY_ID: 2354 phy_type = e1000_phy_82577; 2355 break; 2356 case I82579_E_PHY_ID: 2357 phy_type = e1000_phy_82579; 2358 break; 2359 case I217_E_PHY_ID: 2360 phy_type = e1000_phy_i217; 2361 break; 2362 default: 2363 phy_type = e1000_phy_unknown; 2364 break; 2365 } 2366 return phy_type; 2367 } 2368 2369 /** 2370 * e1000e_determine_phy_address - Determines PHY address. 2371 * @hw: pointer to the HW structure 2372 * 2373 * This uses a trial and error method to loop through possible PHY 2374 * addresses. It tests each by reading the PHY ID registers and 2375 * checking for a match. 2376 **/ 2377 s32 e1000e_determine_phy_address(struct e1000_hw *hw) 2378 { 2379 u32 phy_addr = 0; 2380 u32 i; 2381 enum e1000_phy_type phy_type = e1000_phy_unknown; 2382 2383 hw->phy.id = phy_type; 2384 2385 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2386 hw->phy.addr = phy_addr; 2387 i = 0; 2388 2389 do { 2390 e1000e_get_phy_id(hw); 2391 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 2392 2393 /* 2394 * If phy_type is valid, break - we found our 2395 * PHY address 2396 */ 2397 if (phy_type != e1000_phy_unknown) 2398 return 0; 2399 2400 usleep_range(1000, 2000); 2401 i++; 2402 } while (i < 10); 2403 } 2404 2405 return -E1000_ERR_PHY_TYPE; 2406 } 2407 2408 /** 2409 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2410 * @page: page to access 2411 * 2412 * Returns the phy address for the page requested. 2413 **/ 2414 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2415 { 2416 u32 phy_addr = 2; 2417 2418 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2419 phy_addr = 1; 2420 2421 return phy_addr; 2422 } 2423 2424 /** 2425 * e1000e_write_phy_reg_bm - Write BM PHY register 2426 * @hw: pointer to the HW structure 2427 * @offset: register offset to write to 2428 * @data: data to write at register offset 2429 * 2430 * Acquires semaphore, if necessary, then writes the data to PHY register 2431 * at the offset. Release any acquired semaphores before exiting. 2432 **/ 2433 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2434 { 2435 s32 ret_val; 2436 u32 page = offset >> IGP_PAGE_SHIFT; 2437 2438 ret_val = hw->phy.ops.acquire(hw); 2439 if (ret_val) 2440 return ret_val; 2441 2442 /* Page 800 works differently than the rest so it has its own func */ 2443 if (page == BM_WUC_PAGE) { 2444 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2445 false, false); 2446 goto release; 2447 } 2448 2449 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2450 2451 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2452 u32 page_shift, page_select; 2453 2454 /* 2455 * Page select is register 31 for phy address 1 and 22 for 2456 * phy address 2 and 3. Page select is shifted only for 2457 * phy address 1. 2458 */ 2459 if (hw->phy.addr == 1) { 2460 page_shift = IGP_PAGE_SHIFT; 2461 page_select = IGP01E1000_PHY_PAGE_SELECT; 2462 } else { 2463 page_shift = 0; 2464 page_select = BM_PHY_PAGE_SELECT; 2465 } 2466 2467 /* Page is shifted left, PHY expects (page x 32) */ 2468 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 2469 (page << page_shift)); 2470 if (ret_val) 2471 goto release; 2472 } 2473 2474 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2475 data); 2476 2477 release: 2478 hw->phy.ops.release(hw); 2479 return ret_val; 2480 } 2481 2482 /** 2483 * e1000e_read_phy_reg_bm - Read BM PHY register 2484 * @hw: pointer to the HW structure 2485 * @offset: register offset to be read 2486 * @data: pointer to the read data 2487 * 2488 * Acquires semaphore, if necessary, then reads the PHY register at offset 2489 * and storing the retrieved information in data. Release any acquired 2490 * semaphores before exiting. 2491 **/ 2492 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2493 { 2494 s32 ret_val; 2495 u32 page = offset >> IGP_PAGE_SHIFT; 2496 2497 ret_val = hw->phy.ops.acquire(hw); 2498 if (ret_val) 2499 return ret_val; 2500 2501 /* Page 800 works differently than the rest so it has its own func */ 2502 if (page == BM_WUC_PAGE) { 2503 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2504 true, false); 2505 goto release; 2506 } 2507 2508 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2509 2510 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2511 u32 page_shift, page_select; 2512 2513 /* 2514 * Page select is register 31 for phy address 1 and 22 for 2515 * phy address 2 and 3. Page select is shifted only for 2516 * phy address 1. 2517 */ 2518 if (hw->phy.addr == 1) { 2519 page_shift = IGP_PAGE_SHIFT; 2520 page_select = IGP01E1000_PHY_PAGE_SELECT; 2521 } else { 2522 page_shift = 0; 2523 page_select = BM_PHY_PAGE_SELECT; 2524 } 2525 2526 /* Page is shifted left, PHY expects (page x 32) */ 2527 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 2528 (page << page_shift)); 2529 if (ret_val) 2530 goto release; 2531 } 2532 2533 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2534 data); 2535 release: 2536 hw->phy.ops.release(hw); 2537 return ret_val; 2538 } 2539 2540 /** 2541 * e1000e_read_phy_reg_bm2 - Read BM PHY register 2542 * @hw: pointer to the HW structure 2543 * @offset: register offset to be read 2544 * @data: pointer to the read data 2545 * 2546 * Acquires semaphore, if necessary, then reads the PHY register at offset 2547 * and storing the retrieved information in data. Release any acquired 2548 * semaphores before exiting. 2549 **/ 2550 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2551 { 2552 s32 ret_val; 2553 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2554 2555 ret_val = hw->phy.ops.acquire(hw); 2556 if (ret_val) 2557 return ret_val; 2558 2559 /* Page 800 works differently than the rest so it has its own func */ 2560 if (page == BM_WUC_PAGE) { 2561 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2562 true, false); 2563 goto release; 2564 } 2565 2566 hw->phy.addr = 1; 2567 2568 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2569 2570 /* Page is shifted left, PHY expects (page x 32) */ 2571 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2572 page); 2573 2574 if (ret_val) 2575 goto release; 2576 } 2577 2578 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2579 data); 2580 release: 2581 hw->phy.ops.release(hw); 2582 return ret_val; 2583 } 2584 2585 /** 2586 * e1000e_write_phy_reg_bm2 - Write BM PHY register 2587 * @hw: pointer to the HW structure 2588 * @offset: register offset to write to 2589 * @data: data to write at register offset 2590 * 2591 * Acquires semaphore, if necessary, then writes the data to PHY register 2592 * at the offset. Release any acquired semaphores before exiting. 2593 **/ 2594 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2595 { 2596 s32 ret_val; 2597 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2598 2599 ret_val = hw->phy.ops.acquire(hw); 2600 if (ret_val) 2601 return ret_val; 2602 2603 /* Page 800 works differently than the rest so it has its own func */ 2604 if (page == BM_WUC_PAGE) { 2605 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2606 false, false); 2607 goto release; 2608 } 2609 2610 hw->phy.addr = 1; 2611 2612 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2613 /* Page is shifted left, PHY expects (page x 32) */ 2614 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2615 page); 2616 2617 if (ret_val) 2618 goto release; 2619 } 2620 2621 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2622 data); 2623 2624 release: 2625 hw->phy.ops.release(hw); 2626 return ret_val; 2627 } 2628 2629 /** 2630 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 2631 * @hw: pointer to the HW structure 2632 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 2633 * 2634 * Assumes semaphore already acquired and phy_reg points to a valid memory 2635 * address to store contents of the BM_WUC_ENABLE_REG register. 2636 **/ 2637 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 2638 { 2639 s32 ret_val; 2640 u16 temp; 2641 2642 /* All page select, port ctrl and wakeup registers use phy address 1 */ 2643 hw->phy.addr = 1; 2644 2645 /* Select Port Control Registers page */ 2646 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2647 if (ret_val) { 2648 e_dbg("Could not set Port Control page\n"); 2649 return ret_val; 2650 } 2651 2652 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2653 if (ret_val) { 2654 e_dbg("Could not read PHY register %d.%d\n", 2655 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2656 return ret_val; 2657 } 2658 2659 /* 2660 * Enable both PHY wakeup mode and Wakeup register page writes. 2661 * Prevent a power state change by disabling ME and Host PHY wakeup. 2662 */ 2663 temp = *phy_reg; 2664 temp |= BM_WUC_ENABLE_BIT; 2665 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 2666 2667 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 2668 if (ret_val) { 2669 e_dbg("Could not write PHY register %d.%d\n", 2670 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2671 return ret_val; 2672 } 2673 2674 /* 2675 * Select Host Wakeup Registers page - caller now able to write 2676 * registers on the Wakeup registers page 2677 */ 2678 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2679 } 2680 2681 /** 2682 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 2683 * @hw: pointer to the HW structure 2684 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 2685 * 2686 * Restore BM_WUC_ENABLE_REG to its original value. 2687 * 2688 * Assumes semaphore already acquired and *phy_reg is the contents of the 2689 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 2690 * caller. 2691 **/ 2692 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 2693 { 2694 s32 ret_val = 0; 2695 2696 /* Select Port Control Registers page */ 2697 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2698 if (ret_val) { 2699 e_dbg("Could not set Port Control page\n"); 2700 return ret_val; 2701 } 2702 2703 /* Restore 769.17 to its original value */ 2704 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 2705 if (ret_val) 2706 e_dbg("Could not restore PHY register %d.%d\n", 2707 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2708 2709 return ret_val; 2710 } 2711 2712 /** 2713 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 2714 * @hw: pointer to the HW structure 2715 * @offset: register offset to be read or written 2716 * @data: pointer to the data to read or write 2717 * @read: determines if operation is read or write 2718 * @page_set: BM_WUC_PAGE already set and access enabled 2719 * 2720 * Read the PHY register at offset and store the retrieved information in 2721 * data, or write data to PHY register at offset. Note the procedure to 2722 * access the PHY wakeup registers is different than reading the other PHY 2723 * registers. It works as such: 2724 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 2725 * 2) Set page to 800 for host (801 if we were manageability) 2726 * 3) Write the address using the address opcode (0x11) 2727 * 4) Read or write the data using the data opcode (0x12) 2728 * 5) Restore 769.17.2 to its original value 2729 * 2730 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 2731 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 2732 * 2733 * Assumes semaphore is already acquired. When page_set==true, assumes 2734 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 2735 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 2736 **/ 2737 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 2738 u16 *data, bool read, bool page_set) 2739 { 2740 s32 ret_val; 2741 u16 reg = BM_PHY_REG_NUM(offset); 2742 u16 page = BM_PHY_REG_PAGE(offset); 2743 u16 phy_reg = 0; 2744 2745 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 2746 if ((hw->mac.type == e1000_pchlan) && 2747 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2748 e_dbg("Attempting to access page %d while gig enabled.\n", 2749 page); 2750 2751 if (!page_set) { 2752 /* Enable access to PHY wakeup registers */ 2753 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2754 if (ret_val) { 2755 e_dbg("Could not enable PHY wakeup reg access\n"); 2756 return ret_val; 2757 } 2758 } 2759 2760 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); 2761 2762 /* Write the Wakeup register page offset value using opcode 0x11 */ 2763 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2764 if (ret_val) { 2765 e_dbg("Could not write address opcode to page %d\n", page); 2766 return ret_val; 2767 } 2768 2769 if (read) { 2770 /* Read the Wakeup register page value using opcode 0x12 */ 2771 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2772 data); 2773 } else { 2774 /* Write the Wakeup register page value using opcode 0x12 */ 2775 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2776 *data); 2777 } 2778 2779 if (ret_val) { 2780 e_dbg("Could not access PHY reg %d.%d\n", page, reg); 2781 return ret_val; 2782 } 2783 2784 if (!page_set) 2785 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2786 2787 return ret_val; 2788 } 2789 2790 /** 2791 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2792 * @hw: pointer to the HW structure 2793 * 2794 * In the case of a PHY power down to save power, or to turn off link during a 2795 * driver unload, or wake on lan is not enabled, restore the link to previous 2796 * settings. 2797 **/ 2798 void e1000_power_up_phy_copper(struct e1000_hw *hw) 2799 { 2800 u16 mii_reg = 0; 2801 2802 /* The PHY will retain its settings across a power down/up cycle */ 2803 e1e_rphy(hw, PHY_CONTROL, &mii_reg); 2804 mii_reg &= ~MII_CR_POWER_DOWN; 2805 e1e_wphy(hw, PHY_CONTROL, mii_reg); 2806 } 2807 2808 /** 2809 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2810 * @hw: pointer to the HW structure 2811 * 2812 * In the case of a PHY power down to save power, or to turn off link during a 2813 * driver unload, or wake on lan is not enabled, restore the link to previous 2814 * settings. 2815 **/ 2816 void e1000_power_down_phy_copper(struct e1000_hw *hw) 2817 { 2818 u16 mii_reg = 0; 2819 2820 /* The PHY will retain its settings across a power down/up cycle */ 2821 e1e_rphy(hw, PHY_CONTROL, &mii_reg); 2822 mii_reg |= MII_CR_POWER_DOWN; 2823 e1e_wphy(hw, PHY_CONTROL, mii_reg); 2824 usleep_range(1000, 2000); 2825 } 2826 2827 /** 2828 * e1000e_commit_phy - Soft PHY reset 2829 * @hw: pointer to the HW structure 2830 * 2831 * Performs a soft PHY reset on those that apply. This is a function pointer 2832 * entry point called by drivers. 2833 **/ 2834 s32 e1000e_commit_phy(struct e1000_hw *hw) 2835 { 2836 if (hw->phy.ops.commit) 2837 return hw->phy.ops.commit(hw); 2838 2839 return 0; 2840 } 2841 2842 /** 2843 * e1000_set_d0_lplu_state - Sets low power link up state for D0 2844 * @hw: pointer to the HW structure 2845 * @active: boolean used to enable/disable lplu 2846 * 2847 * Success returns 0, Failure returns 1 2848 * 2849 * The low power link up (lplu) state is set to the power management level D0 2850 * and SmartSpeed is disabled when active is true, else clear lplu for D0 2851 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2852 * is used during Dx states where the power conservation is most important. 2853 * During driver activity, SmartSpeed should be enabled so performance is 2854 * maintained. This is a function pointer entry point called by drivers. 2855 **/ 2856 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2857 { 2858 if (hw->phy.ops.set_d0_lplu_state) 2859 return hw->phy.ops.set_d0_lplu_state(hw, active); 2860 2861 return 0; 2862 } 2863 2864 /** 2865 * __e1000_read_phy_reg_hv - Read HV PHY register 2866 * @hw: pointer to the HW structure 2867 * @offset: register offset to be read 2868 * @data: pointer to the read data 2869 * @locked: semaphore has already been acquired or not 2870 * 2871 * Acquires semaphore, if necessary, then reads the PHY register at offset 2872 * and stores the retrieved information in data. Release any acquired 2873 * semaphore before exiting. 2874 **/ 2875 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 2876 bool locked, bool page_set) 2877 { 2878 s32 ret_val; 2879 u16 page = BM_PHY_REG_PAGE(offset); 2880 u16 reg = BM_PHY_REG_NUM(offset); 2881 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2882 2883 if (!locked) { 2884 ret_val = hw->phy.ops.acquire(hw); 2885 if (ret_val) 2886 return ret_val; 2887 } 2888 2889 /* Page 800 works differently than the rest so it has its own func */ 2890 if (page == BM_WUC_PAGE) { 2891 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2892 true, page_set); 2893 goto out; 2894 } 2895 2896 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 2897 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 2898 data, true); 2899 goto out; 2900 } 2901 2902 if (!page_set) { 2903 if (page == HV_INTC_FC_PAGE_START) 2904 page = 0; 2905 2906 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2907 /* Page is shifted left, PHY expects (page x 32) */ 2908 ret_val = e1000_set_page_igp(hw, 2909 (page << IGP_PAGE_SHIFT)); 2910 2911 hw->phy.addr = phy_addr; 2912 2913 if (ret_val) 2914 goto out; 2915 } 2916 } 2917 2918 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 2919 page << IGP_PAGE_SHIFT, reg); 2920 2921 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2922 data); 2923 out: 2924 if (!locked) 2925 hw->phy.ops.release(hw); 2926 2927 return ret_val; 2928 } 2929 2930 /** 2931 * e1000_read_phy_reg_hv - Read HV PHY register 2932 * @hw: pointer to the HW structure 2933 * @offset: register offset to be read 2934 * @data: pointer to the read data 2935 * 2936 * Acquires semaphore then reads the PHY register at offset and stores 2937 * the retrieved information in data. Release the acquired semaphore 2938 * before exiting. 2939 **/ 2940 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2941 { 2942 return __e1000_read_phy_reg_hv(hw, offset, data, false, false); 2943 } 2944 2945 /** 2946 * e1000_read_phy_reg_hv_locked - Read HV PHY register 2947 * @hw: pointer to the HW structure 2948 * @offset: register offset to be read 2949 * @data: pointer to the read data 2950 * 2951 * Reads the PHY register at offset and stores the retrieved information 2952 * in data. Assumes semaphore already acquired. 2953 **/ 2954 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 2955 { 2956 return __e1000_read_phy_reg_hv(hw, offset, data, true, false); 2957 } 2958 2959 /** 2960 * e1000_read_phy_reg_page_hv - Read HV PHY register 2961 * @hw: pointer to the HW structure 2962 * @offset: register offset to write to 2963 * @data: data to write at register offset 2964 * 2965 * Reads the PHY register at offset and stores the retrieved information 2966 * in data. Assumes semaphore already acquired and page already set. 2967 **/ 2968 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2969 { 2970 return __e1000_read_phy_reg_hv(hw, offset, data, true, true); 2971 } 2972 2973 /** 2974 * __e1000_write_phy_reg_hv - Write HV PHY register 2975 * @hw: pointer to the HW structure 2976 * @offset: register offset to write to 2977 * @data: data to write at register offset 2978 * @locked: semaphore has already been acquired or not 2979 * 2980 * Acquires semaphore, if necessary, then writes the data to PHY register 2981 * at the offset. Release any acquired semaphores before exiting. 2982 **/ 2983 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 2984 bool locked, bool page_set) 2985 { 2986 s32 ret_val; 2987 u16 page = BM_PHY_REG_PAGE(offset); 2988 u16 reg = BM_PHY_REG_NUM(offset); 2989 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2990 2991 if (!locked) { 2992 ret_val = hw->phy.ops.acquire(hw); 2993 if (ret_val) 2994 return ret_val; 2995 } 2996 2997 /* Page 800 works differently than the rest so it has its own func */ 2998 if (page == BM_WUC_PAGE) { 2999 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3000 false, page_set); 3001 goto out; 3002 } 3003 3004 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3005 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3006 &data, false); 3007 goto out; 3008 } 3009 3010 if (!page_set) { 3011 if (page == HV_INTC_FC_PAGE_START) 3012 page = 0; 3013 3014 /* 3015 * Workaround MDIO accesses being disabled after entering IEEE 3016 * Power Down (when bit 11 of the PHY Control register is set) 3017 */ 3018 if ((hw->phy.type == e1000_phy_82578) && 3019 (hw->phy.revision >= 1) && 3020 (hw->phy.addr == 2) && 3021 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) { 3022 u16 data2 = 0x7EFF; 3023 ret_val = e1000_access_phy_debug_regs_hv(hw, 3024 (1 << 6) | 0x3, 3025 &data2, false); 3026 if (ret_val) 3027 goto out; 3028 } 3029 3030 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3031 /* Page is shifted left, PHY expects (page x 32) */ 3032 ret_val = e1000_set_page_igp(hw, 3033 (page << IGP_PAGE_SHIFT)); 3034 3035 hw->phy.addr = phy_addr; 3036 3037 if (ret_val) 3038 goto out; 3039 } 3040 } 3041 3042 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3043 page << IGP_PAGE_SHIFT, reg); 3044 3045 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3046 data); 3047 3048 out: 3049 if (!locked) 3050 hw->phy.ops.release(hw); 3051 3052 return ret_val; 3053 } 3054 3055 /** 3056 * e1000_write_phy_reg_hv - Write HV PHY register 3057 * @hw: pointer to the HW structure 3058 * @offset: register offset to write to 3059 * @data: data to write at register offset 3060 * 3061 * Acquires semaphore then writes the data to PHY register at the offset. 3062 * Release the acquired semaphores before exiting. 3063 **/ 3064 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3065 { 3066 return __e1000_write_phy_reg_hv(hw, offset, data, false, false); 3067 } 3068 3069 /** 3070 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3071 * @hw: pointer to the HW structure 3072 * @offset: register offset to write to 3073 * @data: data to write at register offset 3074 * 3075 * Writes the data to PHY register at the offset. Assumes semaphore 3076 * already acquired. 3077 **/ 3078 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3079 { 3080 return __e1000_write_phy_reg_hv(hw, offset, data, true, false); 3081 } 3082 3083 /** 3084 * e1000_write_phy_reg_page_hv - Write HV PHY register 3085 * @hw: pointer to the HW structure 3086 * @offset: register offset to write to 3087 * @data: data to write at register offset 3088 * 3089 * Writes the data to PHY register at the offset. Assumes semaphore 3090 * already acquired and page already set. 3091 **/ 3092 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3093 { 3094 return __e1000_write_phy_reg_hv(hw, offset, data, true, true); 3095 } 3096 3097 /** 3098 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page 3099 * @page: page to be accessed 3100 **/ 3101 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3102 { 3103 u32 phy_addr = 2; 3104 3105 if (page >= HV_INTC_FC_PAGE_START) 3106 phy_addr = 1; 3107 3108 return phy_addr; 3109 } 3110 3111 /** 3112 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3113 * @hw: pointer to the HW structure 3114 * @offset: register offset to be read or written 3115 * @data: pointer to the data to be read or written 3116 * @read: determines if operation is read or write 3117 * 3118 * Reads the PHY register at offset and stores the retreived information 3119 * in data. Assumes semaphore already acquired. Note that the procedure 3120 * to access these regs uses the address port and data port to read/write. 3121 * These accesses done with PHY address 2 and without using pages. 3122 **/ 3123 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3124 u16 *data, bool read) 3125 { 3126 s32 ret_val; 3127 u32 addr_reg = 0; 3128 u32 data_reg = 0; 3129 3130 /* This takes care of the difference with desktop vs mobile phy */ 3131 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3132 I82578_ADDR_REG : I82577_ADDR_REG; 3133 data_reg = addr_reg + 1; 3134 3135 /* All operations in this function are phy address 2 */ 3136 hw->phy.addr = 2; 3137 3138 /* masking with 0x3F to remove the page from offset */ 3139 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3140 if (ret_val) { 3141 e_dbg("Could not write the Address Offset port register\n"); 3142 return ret_val; 3143 } 3144 3145 /* Read or write the data value next */ 3146 if (read) 3147 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); 3148 else 3149 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); 3150 3151 if (ret_val) 3152 e_dbg("Could not access the Data port register\n"); 3153 3154 return ret_val; 3155 } 3156 3157 /** 3158 * e1000_link_stall_workaround_hv - Si workaround 3159 * @hw: pointer to the HW structure 3160 * 3161 * This function works around a Si bug where the link partner can get 3162 * a link up indication before the PHY does. If small packets are sent 3163 * by the link partner they can be placed in the packet buffer without 3164 * being properly accounted for by the PHY and will stall preventing 3165 * further packets from being received. The workaround is to clear the 3166 * packet buffer after the PHY detects link up. 3167 **/ 3168 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3169 { 3170 s32 ret_val = 0; 3171 u16 data; 3172 3173 if (hw->phy.type != e1000_phy_82578) 3174 return 0; 3175 3176 /* Do not apply workaround if in PHY loopback bit 14 set */ 3177 e1e_rphy(hw, PHY_CONTROL, &data); 3178 if (data & PHY_CONTROL_LB) 3179 return 0; 3180 3181 /* check if link is up and at 1Gbps */ 3182 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); 3183 if (ret_val) 3184 return ret_val; 3185 3186 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3187 BM_CS_STATUS_SPEED_MASK; 3188 3189 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3190 BM_CS_STATUS_SPEED_1000)) 3191 return 0; 3192 3193 msleep(200); 3194 3195 /* flush the packets in the fifo buffer */ 3196 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC | 3197 HV_MUX_DATA_CTRL_FORCE_SPEED); 3198 if (ret_val) 3199 return ret_val; 3200 3201 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); 3202 } 3203 3204 /** 3205 * e1000_check_polarity_82577 - Checks the polarity. 3206 * @hw: pointer to the HW structure 3207 * 3208 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3209 * 3210 * Polarity is determined based on the PHY specific status register. 3211 **/ 3212 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3213 { 3214 struct e1000_phy_info *phy = &hw->phy; 3215 s32 ret_val; 3216 u16 data; 3217 3218 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 3219 3220 if (!ret_val) 3221 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3222 ? e1000_rev_polarity_reversed 3223 : e1000_rev_polarity_normal; 3224 3225 return ret_val; 3226 } 3227 3228 /** 3229 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3230 * @hw: pointer to the HW structure 3231 * 3232 * Calls the PHY setup function to force speed and duplex. 3233 **/ 3234 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3235 { 3236 struct e1000_phy_info *phy = &hw->phy; 3237 s32 ret_val; 3238 u16 phy_data; 3239 bool link; 3240 3241 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 3242 if (ret_val) 3243 return ret_val; 3244 3245 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 3246 3247 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); 3248 if (ret_val) 3249 return ret_val; 3250 3251 udelay(1); 3252 3253 if (phy->autoneg_wait_to_complete) { 3254 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); 3255 3256 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3257 100000, &link); 3258 if (ret_val) 3259 return ret_val; 3260 3261 if (!link) 3262 e_dbg("Link taking longer than expected.\n"); 3263 3264 /* Try once more */ 3265 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3266 100000, &link); 3267 } 3268 3269 return ret_val; 3270 } 3271 3272 /** 3273 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3274 * @hw: pointer to the HW structure 3275 * 3276 * Read PHY status to determine if link is up. If link is up, then 3277 * set/determine 10base-T extended distance and polarity correction. Read 3278 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3279 * determine on the cable length, local and remote receiver. 3280 **/ 3281 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3282 { 3283 struct e1000_phy_info *phy = &hw->phy; 3284 s32 ret_val; 3285 u16 data; 3286 bool link; 3287 3288 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 3289 if (ret_val) 3290 return ret_val; 3291 3292 if (!link) { 3293 e_dbg("Phy info is only valid if link is up\n"); 3294 return -E1000_ERR_CONFIG; 3295 } 3296 3297 phy->polarity_correction = true; 3298 3299 ret_val = e1000_check_polarity_82577(hw); 3300 if (ret_val) 3301 return ret_val; 3302 3303 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 3304 if (ret_val) 3305 return ret_val; 3306 3307 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 3308 3309 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3310 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3311 ret_val = hw->phy.ops.get_cable_length(hw); 3312 if (ret_val) 3313 return ret_val; 3314 3315 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); 3316 if (ret_val) 3317 return ret_val; 3318 3319 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3320 ? e1000_1000t_rx_status_ok 3321 : e1000_1000t_rx_status_not_ok; 3322 3323 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3324 ? e1000_1000t_rx_status_ok 3325 : e1000_1000t_rx_status_not_ok; 3326 } else { 3327 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3328 phy->local_rx = e1000_1000t_rx_status_undefined; 3329 phy->remote_rx = e1000_1000t_rx_status_undefined; 3330 } 3331 3332 return 0; 3333 } 3334 3335 /** 3336 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3337 * @hw: pointer to the HW structure 3338 * 3339 * Reads the diagnostic status register and verifies result is valid before 3340 * placing it in the phy_cable_length field. 3341 **/ 3342 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3343 { 3344 struct e1000_phy_info *phy = &hw->phy; 3345 s32 ret_val; 3346 u16 phy_data, length; 3347 3348 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3349 if (ret_val) 3350 return ret_val; 3351 3352 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3353 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3354 3355 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3356 ret_val = -E1000_ERR_PHY; 3357 3358 phy->cable_length = length; 3359 3360 return 0; 3361 } 3362