1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/delay.h> 30 31 #include "e1000.h" 32 33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); 35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); 36 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read, bool page_set); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = { 46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 ARRAY_SIZE(e1000_m88_cable_length_table) 49 50 static const u16 e1000_igp_2_cable_length_table[] = { 51 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 58 124}; 59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 60 ARRAY_SIZE(e1000_igp_2_cable_length_table) 61 62 #define BM_PHY_REG_PAGE(offset) \ 63 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 64 #define BM_PHY_REG_NUM(offset) \ 65 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ 66 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 67 ~MAX_PHY_REG_ADDRESS))) 68 69 #define HV_INTC_FC_PAGE_START 768 70 #define I82578_ADDR_REG 29 71 #define I82577_ADDR_REG 16 72 #define I82577_CFG_REG 22 73 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 74 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ 75 #define I82577_CTRL_REG 23 76 77 /* 82577 specific PHY registers */ 78 #define I82577_PHY_CTRL_2 18 79 #define I82577_PHY_STATUS_2 26 80 #define I82577_PHY_DIAG_STATUS 31 81 82 /* I82577 PHY Status 2 */ 83 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 84 #define I82577_PHY_STATUS2_MDIX 0x0800 85 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 86 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 87 88 /* I82577 PHY Control 2 */ 89 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 90 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 91 92 /* I82577 PHY Diagnostics Status */ 93 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC 94 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 95 96 /* BM PHY Copper Specific Control 1 */ 97 #define BM_CS_CTRL1 16 98 99 #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 100 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 101 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 102 103 /** 104 * e1000e_check_reset_block_generic - Check if PHY reset is blocked 105 * @hw: pointer to the HW structure 106 * 107 * Read the PHY management control register and check whether a PHY reset 108 * is blocked. If a reset is not blocked return 0, otherwise 109 * return E1000_BLK_PHY_RESET (12). 110 **/ 111 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) 112 { 113 u32 manc; 114 115 manc = er32(MANC); 116 117 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 118 E1000_BLK_PHY_RESET : 0; 119 } 120 121 /** 122 * e1000e_get_phy_id - Retrieve the PHY ID and revision 123 * @hw: pointer to the HW structure 124 * 125 * Reads the PHY registers and stores the PHY ID and possibly the PHY 126 * revision in the hardware structure. 127 **/ 128 s32 e1000e_get_phy_id(struct e1000_hw *hw) 129 { 130 struct e1000_phy_info *phy = &hw->phy; 131 s32 ret_val = 0; 132 u16 phy_id; 133 u16 retry_count = 0; 134 135 if (!(phy->ops.read_reg)) 136 goto out; 137 138 while (retry_count < 2) { 139 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); 140 if (ret_val) 141 goto out; 142 143 phy->id = (u32)(phy_id << 16); 144 udelay(20); 145 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); 146 if (ret_val) 147 goto out; 148 149 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 150 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 151 152 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 153 goto out; 154 155 retry_count++; 156 } 157 out: 158 return ret_val; 159 } 160 161 /** 162 * e1000e_phy_reset_dsp - Reset PHY DSP 163 * @hw: pointer to the HW structure 164 * 165 * Reset the digital signal processor. 166 **/ 167 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) 168 { 169 s32 ret_val; 170 171 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 172 if (ret_val) 173 return ret_val; 174 175 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); 176 } 177 178 /** 179 * e1000e_read_phy_reg_mdic - Read MDI control register 180 * @hw: pointer to the HW structure 181 * @offset: register offset to be read 182 * @data: pointer to the read data 183 * 184 * Reads the MDI control register in the PHY at offset and stores the 185 * information read to data. 186 **/ 187 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 188 { 189 struct e1000_phy_info *phy = &hw->phy; 190 u32 i, mdic = 0; 191 192 if (offset > MAX_PHY_REG_ADDRESS) { 193 e_dbg("PHY Address %d is out of range\n", offset); 194 return -E1000_ERR_PARAM; 195 } 196 197 /* 198 * Set up Op-code, Phy Address, and register offset in the MDI 199 * Control register. The MAC will take care of interfacing with the 200 * PHY to retrieve the desired data. 201 */ 202 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 203 (phy->addr << E1000_MDIC_PHY_SHIFT) | 204 (E1000_MDIC_OP_READ)); 205 206 ew32(MDIC, mdic); 207 208 /* 209 * Poll the ready bit to see if the MDI read completed 210 * Increasing the time out as testing showed failures with 211 * the lower time out 212 */ 213 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 214 udelay(50); 215 mdic = er32(MDIC); 216 if (mdic & E1000_MDIC_READY) 217 break; 218 } 219 if (!(mdic & E1000_MDIC_READY)) { 220 e_dbg("MDI Read did not complete\n"); 221 return -E1000_ERR_PHY; 222 } 223 if (mdic & E1000_MDIC_ERROR) { 224 e_dbg("MDI Error\n"); 225 return -E1000_ERR_PHY; 226 } 227 *data = (u16) mdic; 228 229 /* 230 * Allow some time after each MDIC transaction to avoid 231 * reading duplicate data in the next MDIC transaction. 232 */ 233 if (hw->mac.type == e1000_pch2lan) 234 udelay(100); 235 236 return 0; 237 } 238 239 /** 240 * e1000e_write_phy_reg_mdic - Write MDI control register 241 * @hw: pointer to the HW structure 242 * @offset: register offset to write to 243 * @data: data to write to register at offset 244 * 245 * Writes data to MDI control register in the PHY at offset. 246 **/ 247 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 248 { 249 struct e1000_phy_info *phy = &hw->phy; 250 u32 i, mdic = 0; 251 252 if (offset > MAX_PHY_REG_ADDRESS) { 253 e_dbg("PHY Address %d is out of range\n", offset); 254 return -E1000_ERR_PARAM; 255 } 256 257 /* 258 * Set up Op-code, Phy Address, and register offset in the MDI 259 * Control register. The MAC will take care of interfacing with the 260 * PHY to retrieve the desired data. 261 */ 262 mdic = (((u32)data) | 263 (offset << E1000_MDIC_REG_SHIFT) | 264 (phy->addr << E1000_MDIC_PHY_SHIFT) | 265 (E1000_MDIC_OP_WRITE)); 266 267 ew32(MDIC, mdic); 268 269 /* 270 * Poll the ready bit to see if the MDI read completed 271 * Increasing the time out as testing showed failures with 272 * the lower time out 273 */ 274 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 275 udelay(50); 276 mdic = er32(MDIC); 277 if (mdic & E1000_MDIC_READY) 278 break; 279 } 280 if (!(mdic & E1000_MDIC_READY)) { 281 e_dbg("MDI Write did not complete\n"); 282 return -E1000_ERR_PHY; 283 } 284 if (mdic & E1000_MDIC_ERROR) { 285 e_dbg("MDI Error\n"); 286 return -E1000_ERR_PHY; 287 } 288 289 /* 290 * Allow some time after each MDIC transaction to avoid 291 * reading duplicate data in the next MDIC transaction. 292 */ 293 if (hw->mac.type == e1000_pch2lan) 294 udelay(100); 295 296 return 0; 297 } 298 299 /** 300 * e1000e_read_phy_reg_m88 - Read m88 PHY register 301 * @hw: pointer to the HW structure 302 * @offset: register offset to be read 303 * @data: pointer to the read data 304 * 305 * Acquires semaphore, if necessary, then reads the PHY register at offset 306 * and storing the retrieved information in data. Release any acquired 307 * semaphores before exiting. 308 **/ 309 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 310 { 311 s32 ret_val; 312 313 ret_val = hw->phy.ops.acquire(hw); 314 if (ret_val) 315 return ret_val; 316 317 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 318 data); 319 320 hw->phy.ops.release(hw); 321 322 return ret_val; 323 } 324 325 /** 326 * e1000e_write_phy_reg_m88 - Write m88 PHY register 327 * @hw: pointer to the HW structure 328 * @offset: register offset to write to 329 * @data: data to write at register offset 330 * 331 * Acquires semaphore, if necessary, then writes the data to PHY register 332 * at the offset. Release any acquired semaphores before exiting. 333 **/ 334 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 335 { 336 s32 ret_val; 337 338 ret_val = hw->phy.ops.acquire(hw); 339 if (ret_val) 340 return ret_val; 341 342 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 343 data); 344 345 hw->phy.ops.release(hw); 346 347 return ret_val; 348 } 349 350 /** 351 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 352 * @hw: pointer to the HW structure 353 * @page: page to set (shifted left when necessary) 354 * 355 * Sets PHY page required for PHY register access. Assumes semaphore is 356 * already acquired. Note, this function sets phy.addr to 1 so the caller 357 * must set it appropriately (if necessary) after this function returns. 358 **/ 359 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 360 { 361 e_dbg("Setting page 0x%x\n", page); 362 363 hw->phy.addr = 1; 364 365 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 366 } 367 368 /** 369 * __e1000e_read_phy_reg_igp - Read igp PHY register 370 * @hw: pointer to the HW structure 371 * @offset: register offset to be read 372 * @data: pointer to the read data 373 * @locked: semaphore has already been acquired or not 374 * 375 * Acquires semaphore, if necessary, then reads the PHY register at offset 376 * and stores the retrieved information in data. Release any acquired 377 * semaphores before exiting. 378 **/ 379 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 380 bool locked) 381 { 382 s32 ret_val = 0; 383 384 if (!locked) { 385 if (!(hw->phy.ops.acquire)) 386 goto out; 387 388 ret_val = hw->phy.ops.acquire(hw); 389 if (ret_val) 390 goto out; 391 } 392 393 if (offset > MAX_PHY_MULTI_PAGE_REG) { 394 ret_val = e1000e_write_phy_reg_mdic(hw, 395 IGP01E1000_PHY_PAGE_SELECT, 396 (u16)offset); 397 if (ret_val) 398 goto release; 399 } 400 401 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 402 data); 403 404 release: 405 if (!locked) 406 hw->phy.ops.release(hw); 407 out: 408 return ret_val; 409 } 410 411 /** 412 * e1000e_read_phy_reg_igp - Read igp PHY register 413 * @hw: pointer to the HW structure 414 * @offset: register offset to be read 415 * @data: pointer to the read data 416 * 417 * Acquires semaphore then reads the PHY register at offset and stores the 418 * retrieved information in data. 419 * Release the acquired semaphore before exiting. 420 **/ 421 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 422 { 423 return __e1000e_read_phy_reg_igp(hw, offset, data, false); 424 } 425 426 /** 427 * e1000e_read_phy_reg_igp_locked - Read igp PHY register 428 * @hw: pointer to the HW structure 429 * @offset: register offset to be read 430 * @data: pointer to the read data 431 * 432 * Reads the PHY register at offset and stores the retrieved information 433 * in data. Assumes semaphore already acquired. 434 **/ 435 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 436 { 437 return __e1000e_read_phy_reg_igp(hw, offset, data, true); 438 } 439 440 /** 441 * e1000e_write_phy_reg_igp - Write igp PHY register 442 * @hw: pointer to the HW structure 443 * @offset: register offset to write to 444 * @data: data to write at register offset 445 * @locked: semaphore has already been acquired or not 446 * 447 * Acquires semaphore, if necessary, then writes the data to PHY register 448 * at the offset. Release any acquired semaphores before exiting. 449 **/ 450 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 451 bool locked) 452 { 453 s32 ret_val = 0; 454 455 if (!locked) { 456 if (!(hw->phy.ops.acquire)) 457 goto out; 458 459 ret_val = hw->phy.ops.acquire(hw); 460 if (ret_val) 461 goto out; 462 } 463 464 if (offset > MAX_PHY_MULTI_PAGE_REG) { 465 ret_val = e1000e_write_phy_reg_mdic(hw, 466 IGP01E1000_PHY_PAGE_SELECT, 467 (u16)offset); 468 if (ret_val) 469 goto release; 470 } 471 472 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 473 data); 474 475 release: 476 if (!locked) 477 hw->phy.ops.release(hw); 478 479 out: 480 return ret_val; 481 } 482 483 /** 484 * e1000e_write_phy_reg_igp - Write igp PHY register 485 * @hw: pointer to the HW structure 486 * @offset: register offset to write to 487 * @data: data to write at register offset 488 * 489 * Acquires semaphore then writes the data to PHY register 490 * at the offset. Release any acquired semaphores before exiting. 491 **/ 492 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 493 { 494 return __e1000e_write_phy_reg_igp(hw, offset, data, false); 495 } 496 497 /** 498 * e1000e_write_phy_reg_igp_locked - Write igp PHY register 499 * @hw: pointer to the HW structure 500 * @offset: register offset to write to 501 * @data: data to write at register offset 502 * 503 * Writes the data to PHY register at the offset. 504 * Assumes semaphore already acquired. 505 **/ 506 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 507 { 508 return __e1000e_write_phy_reg_igp(hw, offset, data, true); 509 } 510 511 /** 512 * __e1000_read_kmrn_reg - Read kumeran register 513 * @hw: pointer to the HW structure 514 * @offset: register offset to be read 515 * @data: pointer to the read data 516 * @locked: semaphore has already been acquired or not 517 * 518 * Acquires semaphore, if necessary. Then reads the PHY register at offset 519 * using the kumeran interface. The information retrieved is stored in data. 520 * Release any acquired semaphores before exiting. 521 **/ 522 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 523 bool locked) 524 { 525 u32 kmrnctrlsta; 526 s32 ret_val = 0; 527 528 if (!locked) { 529 if (!(hw->phy.ops.acquire)) 530 goto out; 531 532 ret_val = hw->phy.ops.acquire(hw); 533 if (ret_val) 534 goto out; 535 } 536 537 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 538 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 539 ew32(KMRNCTRLSTA, kmrnctrlsta); 540 e1e_flush(); 541 542 udelay(2); 543 544 kmrnctrlsta = er32(KMRNCTRLSTA); 545 *data = (u16)kmrnctrlsta; 546 547 if (!locked) 548 hw->phy.ops.release(hw); 549 550 out: 551 return ret_val; 552 } 553 554 /** 555 * e1000e_read_kmrn_reg - Read kumeran register 556 * @hw: pointer to the HW structure 557 * @offset: register offset to be read 558 * @data: pointer to the read data 559 * 560 * Acquires semaphore then reads the PHY register at offset using the 561 * kumeran interface. The information retrieved is stored in data. 562 * Release the acquired semaphore before exiting. 563 **/ 564 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) 565 { 566 return __e1000_read_kmrn_reg(hw, offset, data, false); 567 } 568 569 /** 570 * e1000e_read_kmrn_reg_locked - Read kumeran register 571 * @hw: pointer to the HW structure 572 * @offset: register offset to be read 573 * @data: pointer to the read data 574 * 575 * Reads the PHY register at offset using the kumeran interface. The 576 * information retrieved is stored in data. 577 * Assumes semaphore already acquired. 578 **/ 579 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 580 { 581 return __e1000_read_kmrn_reg(hw, offset, data, true); 582 } 583 584 /** 585 * __e1000_write_kmrn_reg - Write kumeran register 586 * @hw: pointer to the HW structure 587 * @offset: register offset to write to 588 * @data: data to write at register offset 589 * @locked: semaphore has already been acquired or not 590 * 591 * Acquires semaphore, if necessary. Then write the data to PHY register 592 * at the offset using the kumeran interface. Release any acquired semaphores 593 * before exiting. 594 **/ 595 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 596 bool locked) 597 { 598 u32 kmrnctrlsta; 599 s32 ret_val = 0; 600 601 if (!locked) { 602 if (!(hw->phy.ops.acquire)) 603 goto out; 604 605 ret_val = hw->phy.ops.acquire(hw); 606 if (ret_val) 607 goto out; 608 } 609 610 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 611 E1000_KMRNCTRLSTA_OFFSET) | data; 612 ew32(KMRNCTRLSTA, kmrnctrlsta); 613 e1e_flush(); 614 615 udelay(2); 616 617 if (!locked) 618 hw->phy.ops.release(hw); 619 620 out: 621 return ret_val; 622 } 623 624 /** 625 * e1000e_write_kmrn_reg - Write kumeran register 626 * @hw: pointer to the HW structure 627 * @offset: register offset to write to 628 * @data: data to write at register offset 629 * 630 * Acquires semaphore then writes the data to the PHY register at the offset 631 * using the kumeran interface. Release the acquired semaphore before exiting. 632 **/ 633 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) 634 { 635 return __e1000_write_kmrn_reg(hw, offset, data, false); 636 } 637 638 /** 639 * e1000e_write_kmrn_reg_locked - Write kumeran register 640 * @hw: pointer to the HW structure 641 * @offset: register offset to write to 642 * @data: data to write at register offset 643 * 644 * Write the data to PHY register at the offset using the kumeran interface. 645 * Assumes semaphore already acquired. 646 **/ 647 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 648 { 649 return __e1000_write_kmrn_reg(hw, offset, data, true); 650 } 651 652 /** 653 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 654 * @hw: pointer to the HW structure 655 * 656 * Sets up Carrier-sense on Transmit and downshift values. 657 **/ 658 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 659 { 660 s32 ret_val; 661 u16 phy_data; 662 663 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 664 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); 665 if (ret_val) 666 goto out; 667 668 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 669 670 /* Enable downshift */ 671 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 672 673 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); 674 675 out: 676 return ret_val; 677 } 678 679 /** 680 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link 681 * @hw: pointer to the HW structure 682 * 683 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 684 * and downshift values are set also. 685 **/ 686 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) 687 { 688 struct e1000_phy_info *phy = &hw->phy; 689 s32 ret_val; 690 u16 phy_data; 691 692 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 693 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 694 if (ret_val) 695 return ret_val; 696 697 /* For BM PHY this bit is downshift enable */ 698 if (phy->type != e1000_phy_bm) 699 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 700 701 /* 702 * Options: 703 * MDI/MDI-X = 0 (default) 704 * 0 - Auto for all speeds 705 * 1 - MDI mode 706 * 2 - MDI-X mode 707 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 708 */ 709 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 710 711 switch (phy->mdix) { 712 case 1: 713 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 714 break; 715 case 2: 716 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 717 break; 718 case 3: 719 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 720 break; 721 case 0: 722 default: 723 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 724 break; 725 } 726 727 /* 728 * Options: 729 * disable_polarity_correction = 0 (default) 730 * Automatic Correction for Reversed Cable Polarity 731 * 0 - Disabled 732 * 1 - Enabled 733 */ 734 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 735 if (phy->disable_polarity_correction == 1) 736 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 737 738 /* Enable downshift on BM (disabled by default) */ 739 if (phy->type == e1000_phy_bm) 740 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 741 742 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 743 if (ret_val) 744 return ret_val; 745 746 if ((phy->type == e1000_phy_m88) && 747 (phy->revision < E1000_REVISION_4) && 748 (phy->id != BME1000_E_PHY_ID_R2)) { 749 /* 750 * Force TX_CLK in the Extended PHY Specific Control Register 751 * to 25MHz clock. 752 */ 753 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 754 if (ret_val) 755 return ret_val; 756 757 phy_data |= M88E1000_EPSCR_TX_CLK_25; 758 759 if ((phy->revision == 2) && 760 (phy->id == M88E1111_I_PHY_ID)) { 761 /* 82573L PHY - set the downshift counter to 5x. */ 762 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 763 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 764 } else { 765 /* Configure Master and Slave downshift values */ 766 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 767 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 768 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 769 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 770 } 771 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 772 if (ret_val) 773 return ret_val; 774 } 775 776 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 777 /* Set PHY page 0, register 29 to 0x0003 */ 778 ret_val = e1e_wphy(hw, 29, 0x0003); 779 if (ret_val) 780 return ret_val; 781 782 /* Set PHY page 0, register 30 to 0x0000 */ 783 ret_val = e1e_wphy(hw, 30, 0x0000); 784 if (ret_val) 785 return ret_val; 786 } 787 788 /* Commit the changes. */ 789 ret_val = e1000e_commit_phy(hw); 790 if (ret_val) { 791 e_dbg("Error committing the PHY changes\n"); 792 return ret_val; 793 } 794 795 if (phy->type == e1000_phy_82578) { 796 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 797 if (ret_val) 798 return ret_val; 799 800 /* 82578 PHY - set the downshift count to 1x. */ 801 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 802 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 803 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 804 if (ret_val) 805 return ret_val; 806 } 807 808 return 0; 809 } 810 811 /** 812 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link 813 * @hw: pointer to the HW structure 814 * 815 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 816 * igp PHY's. 817 **/ 818 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) 819 { 820 struct e1000_phy_info *phy = &hw->phy; 821 s32 ret_val; 822 u16 data; 823 824 ret_val = e1000_phy_hw_reset(hw); 825 if (ret_val) { 826 e_dbg("Error resetting the PHY.\n"); 827 return ret_val; 828 } 829 830 /* 831 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 832 * timeout issues when LFS is enabled. 833 */ 834 msleep(100); 835 836 /* disable lplu d0 during driver init */ 837 ret_val = e1000_set_d0_lplu_state(hw, false); 838 if (ret_val) { 839 e_dbg("Error Disabling LPLU D0\n"); 840 return ret_val; 841 } 842 /* Configure mdi-mdix settings */ 843 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); 844 if (ret_val) 845 return ret_val; 846 847 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 848 849 switch (phy->mdix) { 850 case 1: 851 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 852 break; 853 case 2: 854 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 855 break; 856 case 0: 857 default: 858 data |= IGP01E1000_PSCR_AUTO_MDIX; 859 break; 860 } 861 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); 862 if (ret_val) 863 return ret_val; 864 865 /* set auto-master slave resolution settings */ 866 if (hw->mac.autoneg) { 867 /* 868 * when autonegotiation advertisement is only 1000Mbps then we 869 * should disable SmartSpeed and enable Auto MasterSlave 870 * resolution as hardware default. 871 */ 872 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 873 /* Disable SmartSpeed */ 874 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 875 &data); 876 if (ret_val) 877 return ret_val; 878 879 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 880 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 881 data); 882 if (ret_val) 883 return ret_val; 884 885 /* Set auto Master/Slave resolution process */ 886 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); 887 if (ret_val) 888 return ret_val; 889 890 data &= ~CR_1000T_MS_ENABLE; 891 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); 892 if (ret_val) 893 return ret_val; 894 } 895 896 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); 897 if (ret_val) 898 return ret_val; 899 900 /* load defaults for future use */ 901 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 902 ((data & CR_1000T_MS_VALUE) ? 903 e1000_ms_force_master : 904 e1000_ms_force_slave) : 905 e1000_ms_auto; 906 907 switch (phy->ms_type) { 908 case e1000_ms_force_master: 909 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 910 break; 911 case e1000_ms_force_slave: 912 data |= CR_1000T_MS_ENABLE; 913 data &= ~(CR_1000T_MS_VALUE); 914 break; 915 case e1000_ms_auto: 916 data &= ~CR_1000T_MS_ENABLE; 917 default: 918 break; 919 } 920 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); 921 } 922 923 return ret_val; 924 } 925 926 /** 927 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 928 * @hw: pointer to the HW structure 929 * 930 * Reads the MII auto-neg advertisement register and/or the 1000T control 931 * register and if the PHY is already setup for auto-negotiation, then 932 * return successful. Otherwise, setup advertisement and flow control to 933 * the appropriate values for the wanted auto-negotiation. 934 **/ 935 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 936 { 937 struct e1000_phy_info *phy = &hw->phy; 938 s32 ret_val; 939 u16 mii_autoneg_adv_reg; 940 u16 mii_1000t_ctrl_reg = 0; 941 942 phy->autoneg_advertised &= phy->autoneg_mask; 943 944 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 945 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 946 if (ret_val) 947 return ret_val; 948 949 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 950 /* Read the MII 1000Base-T Control Register (Address 9). */ 951 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 952 if (ret_val) 953 return ret_val; 954 } 955 956 /* 957 * Need to parse both autoneg_advertised and fc and set up 958 * the appropriate PHY registers. First we will parse for 959 * autoneg_advertised software override. Since we can advertise 960 * a plethora of combinations, we need to check each bit 961 * individually. 962 */ 963 964 /* 965 * First we clear all the 10/100 mb speed bits in the Auto-Neg 966 * Advertisement Register (Address 4) and the 1000 mb speed bits in 967 * the 1000Base-T Control Register (Address 9). 968 */ 969 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 970 NWAY_AR_100TX_HD_CAPS | 971 NWAY_AR_10T_FD_CAPS | 972 NWAY_AR_10T_HD_CAPS); 973 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 974 975 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 976 977 /* Do we want to advertise 10 Mb Half Duplex? */ 978 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 979 e_dbg("Advertise 10mb Half duplex\n"); 980 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 981 } 982 983 /* Do we want to advertise 10 Mb Full Duplex? */ 984 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 985 e_dbg("Advertise 10mb Full duplex\n"); 986 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 987 } 988 989 /* Do we want to advertise 100 Mb Half Duplex? */ 990 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 991 e_dbg("Advertise 100mb Half duplex\n"); 992 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 993 } 994 995 /* Do we want to advertise 100 Mb Full Duplex? */ 996 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 997 e_dbg("Advertise 100mb Full duplex\n"); 998 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 999 } 1000 1001 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1002 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1003 e_dbg("Advertise 1000mb Half duplex request denied!\n"); 1004 1005 /* Do we want to advertise 1000 Mb Full Duplex? */ 1006 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1007 e_dbg("Advertise 1000mb Full duplex\n"); 1008 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1009 } 1010 1011 /* 1012 * Check for a software override of the flow control settings, and 1013 * setup the PHY advertisement registers accordingly. If 1014 * auto-negotiation is enabled, then software will have to set the 1015 * "PAUSE" bits to the correct value in the Auto-Negotiation 1016 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1017 * negotiation. 1018 * 1019 * The possible values of the "fc" parameter are: 1020 * 0: Flow control is completely disabled 1021 * 1: Rx flow control is enabled (we can receive pause frames 1022 * but not send pause frames). 1023 * 2: Tx flow control is enabled (we can send pause frames 1024 * but we do not support receiving pause frames). 1025 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1026 * other: No software override. The flow control configuration 1027 * in the EEPROM is used. 1028 */ 1029 switch (hw->fc.current_mode) { 1030 case e1000_fc_none: 1031 /* 1032 * Flow control (Rx & Tx) is completely disabled by a 1033 * software over-ride. 1034 */ 1035 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1036 break; 1037 case e1000_fc_rx_pause: 1038 /* 1039 * Rx Flow control is enabled, and Tx Flow control is 1040 * disabled, by a software over-ride. 1041 * 1042 * Since there really isn't a way to advertise that we are 1043 * capable of Rx Pause ONLY, we will advertise that we 1044 * support both symmetric and asymmetric Rx PAUSE. Later 1045 * (in e1000e_config_fc_after_link_up) we will disable the 1046 * hw's ability to send PAUSE frames. 1047 */ 1048 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1049 break; 1050 case e1000_fc_tx_pause: 1051 /* 1052 * Tx Flow control is enabled, and Rx Flow control is 1053 * disabled, by a software over-ride. 1054 */ 1055 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1056 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1057 break; 1058 case e1000_fc_full: 1059 /* 1060 * Flow control (both Rx and Tx) is enabled by a software 1061 * over-ride. 1062 */ 1063 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1064 break; 1065 default: 1066 e_dbg("Flow control param set incorrectly\n"); 1067 ret_val = -E1000_ERR_CONFIG; 1068 return ret_val; 1069 } 1070 1071 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1072 if (ret_val) 1073 return ret_val; 1074 1075 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1076 1077 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1078 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1079 1080 return ret_val; 1081 } 1082 1083 /** 1084 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1085 * @hw: pointer to the HW structure 1086 * 1087 * Performs initial bounds checking on autoneg advertisement parameter, then 1088 * configure to advertise the full capability. Setup the PHY to autoneg 1089 * and restart the negotiation process between the link partner. If 1090 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1091 **/ 1092 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1093 { 1094 struct e1000_phy_info *phy = &hw->phy; 1095 s32 ret_val; 1096 u16 phy_ctrl; 1097 1098 /* 1099 * Perform some bounds checking on the autoneg advertisement 1100 * parameter. 1101 */ 1102 phy->autoneg_advertised &= phy->autoneg_mask; 1103 1104 /* 1105 * If autoneg_advertised is zero, we assume it was not defaulted 1106 * by the calling code so we set to advertise full capability. 1107 */ 1108 if (phy->autoneg_advertised == 0) 1109 phy->autoneg_advertised = phy->autoneg_mask; 1110 1111 e_dbg("Reconfiguring auto-neg advertisement params\n"); 1112 ret_val = e1000_phy_setup_autoneg(hw); 1113 if (ret_val) { 1114 e_dbg("Error Setting up Auto-Negotiation\n"); 1115 return ret_val; 1116 } 1117 e_dbg("Restarting Auto-Neg\n"); 1118 1119 /* 1120 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1121 * the Auto Neg Restart bit in the PHY control register. 1122 */ 1123 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); 1124 if (ret_val) 1125 return ret_val; 1126 1127 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1128 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); 1129 if (ret_val) 1130 return ret_val; 1131 1132 /* 1133 * Does the user want to wait for Auto-Neg to complete here, or 1134 * check at a later time (for example, callback routine). 1135 */ 1136 if (phy->autoneg_wait_to_complete) { 1137 ret_val = e1000_wait_autoneg(hw); 1138 if (ret_val) { 1139 e_dbg("Error while waiting for autoneg to complete\n"); 1140 return ret_val; 1141 } 1142 } 1143 1144 hw->mac.get_link_status = 1; 1145 1146 return ret_val; 1147 } 1148 1149 /** 1150 * e1000e_setup_copper_link - Configure copper link settings 1151 * @hw: pointer to the HW structure 1152 * 1153 * Calls the appropriate function to configure the link for auto-neg or forced 1154 * speed and duplex. Then we check for link, once link is established calls 1155 * to configure collision distance and flow control are called. If link is 1156 * not established, we return -E1000_ERR_PHY (-2). 1157 **/ 1158 s32 e1000e_setup_copper_link(struct e1000_hw *hw) 1159 { 1160 s32 ret_val; 1161 bool link; 1162 1163 if (hw->mac.autoneg) { 1164 /* 1165 * Setup autoneg and flow control advertisement and perform 1166 * autonegotiation. 1167 */ 1168 ret_val = e1000_copper_link_autoneg(hw); 1169 if (ret_val) 1170 return ret_val; 1171 } else { 1172 /* 1173 * PHY will be set to 10H, 10F, 100H or 100F 1174 * depending on user settings. 1175 */ 1176 e_dbg("Forcing Speed and Duplex\n"); 1177 ret_val = e1000_phy_force_speed_duplex(hw); 1178 if (ret_val) { 1179 e_dbg("Error Forcing Speed and Duplex\n"); 1180 return ret_val; 1181 } 1182 } 1183 1184 /* 1185 * Check link status. Wait up to 100 microseconds for link to become 1186 * valid. 1187 */ 1188 ret_val = e1000e_phy_has_link_generic(hw, 1189 COPPER_LINK_UP_LIMIT, 1190 10, 1191 &link); 1192 if (ret_val) 1193 return ret_val; 1194 1195 if (link) { 1196 e_dbg("Valid link established!!!\n"); 1197 e1000e_config_collision_dist(hw); 1198 ret_val = e1000e_config_fc_after_link_up(hw); 1199 } else { 1200 e_dbg("Unable to establish link!!!\n"); 1201 } 1202 1203 return ret_val; 1204 } 1205 1206 /** 1207 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1208 * @hw: pointer to the HW structure 1209 * 1210 * Calls the PHY setup function to force speed and duplex. Clears the 1211 * auto-crossover to force MDI manually. Waits for link and returns 1212 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1213 **/ 1214 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1215 { 1216 struct e1000_phy_info *phy = &hw->phy; 1217 s32 ret_val; 1218 u16 phy_data; 1219 bool link; 1220 1221 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 1222 if (ret_val) 1223 return ret_val; 1224 1225 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 1226 1227 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); 1228 if (ret_val) 1229 return ret_val; 1230 1231 /* 1232 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1233 * forced whenever speed and duplex are forced. 1234 */ 1235 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1236 if (ret_val) 1237 return ret_val; 1238 1239 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1240 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1241 1242 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1243 if (ret_val) 1244 return ret_val; 1245 1246 e_dbg("IGP PSCR: %X\n", phy_data); 1247 1248 udelay(1); 1249 1250 if (phy->autoneg_wait_to_complete) { 1251 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1252 1253 ret_val = e1000e_phy_has_link_generic(hw, 1254 PHY_FORCE_LIMIT, 1255 100000, 1256 &link); 1257 if (ret_val) 1258 return ret_val; 1259 1260 if (!link) 1261 e_dbg("Link taking longer than expected.\n"); 1262 1263 /* Try once more */ 1264 ret_val = e1000e_phy_has_link_generic(hw, 1265 PHY_FORCE_LIMIT, 1266 100000, 1267 &link); 1268 if (ret_val) 1269 return ret_val; 1270 } 1271 1272 return ret_val; 1273 } 1274 1275 /** 1276 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1277 * @hw: pointer to the HW structure 1278 * 1279 * Calls the PHY setup function to force speed and duplex. Clears the 1280 * auto-crossover to force MDI manually. Resets the PHY to commit the 1281 * changes. If time expires while waiting for link up, we reset the DSP. 1282 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1283 * successful completion, else return corresponding error code. 1284 **/ 1285 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1286 { 1287 struct e1000_phy_info *phy = &hw->phy; 1288 s32 ret_val; 1289 u16 phy_data; 1290 bool link; 1291 1292 /* 1293 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1294 * forced whenever speed and duplex are forced. 1295 */ 1296 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1297 if (ret_val) 1298 return ret_val; 1299 1300 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1301 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1302 if (ret_val) 1303 return ret_val; 1304 1305 e_dbg("M88E1000 PSCR: %X\n", phy_data); 1306 1307 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 1308 if (ret_val) 1309 return ret_val; 1310 1311 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 1312 1313 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); 1314 if (ret_val) 1315 return ret_val; 1316 1317 /* Reset the phy to commit changes. */ 1318 ret_val = e1000e_commit_phy(hw); 1319 if (ret_val) 1320 return ret_val; 1321 1322 if (phy->autoneg_wait_to_complete) { 1323 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1324 1325 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1326 100000, &link); 1327 if (ret_val) 1328 return ret_val; 1329 1330 if (!link) { 1331 if (hw->phy.type != e1000_phy_m88) { 1332 e_dbg("Link taking longer than expected.\n"); 1333 } else { 1334 /* 1335 * We didn't get link. 1336 * Reset the DSP and cross our fingers. 1337 */ 1338 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 1339 0x001d); 1340 if (ret_val) 1341 return ret_val; 1342 ret_val = e1000e_phy_reset_dsp(hw); 1343 if (ret_val) 1344 return ret_val; 1345 } 1346 } 1347 1348 /* Try once more */ 1349 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1350 100000, &link); 1351 if (ret_val) 1352 return ret_val; 1353 } 1354 1355 if (hw->phy.type != e1000_phy_m88) 1356 return 0; 1357 1358 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1359 if (ret_val) 1360 return ret_val; 1361 1362 /* 1363 * Resetting the phy means we need to re-force TX_CLK in the 1364 * Extended PHY Specific Control Register to 25MHz clock from 1365 * the reset value of 2.5MHz. 1366 */ 1367 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1368 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1369 if (ret_val) 1370 return ret_val; 1371 1372 /* 1373 * In addition, we must re-enable CRS on Tx for both half and full 1374 * duplex. 1375 */ 1376 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1377 if (ret_val) 1378 return ret_val; 1379 1380 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1381 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1382 1383 return ret_val; 1384 } 1385 1386 /** 1387 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1388 * @hw: pointer to the HW structure 1389 * 1390 * Forces the speed and duplex settings of the PHY. 1391 * This is a function pointer entry point only called by 1392 * PHY setup routines. 1393 **/ 1394 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1395 { 1396 struct e1000_phy_info *phy = &hw->phy; 1397 s32 ret_val; 1398 u16 data; 1399 bool link; 1400 1401 ret_val = e1e_rphy(hw, PHY_CONTROL, &data); 1402 if (ret_val) 1403 goto out; 1404 1405 e1000e_phy_force_speed_duplex_setup(hw, &data); 1406 1407 ret_val = e1e_wphy(hw, PHY_CONTROL, data); 1408 if (ret_val) 1409 goto out; 1410 1411 /* Disable MDI-X support for 10/100 */ 1412 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 1413 if (ret_val) 1414 goto out; 1415 1416 data &= ~IFE_PMC_AUTO_MDIX; 1417 data &= ~IFE_PMC_FORCE_MDIX; 1418 1419 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); 1420 if (ret_val) 1421 goto out; 1422 1423 e_dbg("IFE PMC: %X\n", data); 1424 1425 udelay(1); 1426 1427 if (phy->autoneg_wait_to_complete) { 1428 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); 1429 1430 ret_val = e1000e_phy_has_link_generic(hw, 1431 PHY_FORCE_LIMIT, 1432 100000, 1433 &link); 1434 if (ret_val) 1435 goto out; 1436 1437 if (!link) 1438 e_dbg("Link taking longer than expected.\n"); 1439 1440 /* Try once more */ 1441 ret_val = e1000e_phy_has_link_generic(hw, 1442 PHY_FORCE_LIMIT, 1443 100000, 1444 &link); 1445 if (ret_val) 1446 goto out; 1447 } 1448 1449 out: 1450 return ret_val; 1451 } 1452 1453 /** 1454 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1455 * @hw: pointer to the HW structure 1456 * @phy_ctrl: pointer to current value of PHY_CONTROL 1457 * 1458 * Forces speed and duplex on the PHY by doing the following: disable flow 1459 * control, force speed/duplex on the MAC, disable auto speed detection, 1460 * disable auto-negotiation, configure duplex, configure speed, configure 1461 * the collision distance, write configuration to CTRL register. The 1462 * caller must write to the PHY_CONTROL register for these settings to 1463 * take affect. 1464 **/ 1465 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1466 { 1467 struct e1000_mac_info *mac = &hw->mac; 1468 u32 ctrl; 1469 1470 /* Turn off flow control when forcing speed/duplex */ 1471 hw->fc.current_mode = e1000_fc_none; 1472 1473 /* Force speed/duplex on the mac */ 1474 ctrl = er32(CTRL); 1475 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1476 ctrl &= ~E1000_CTRL_SPD_SEL; 1477 1478 /* Disable Auto Speed Detection */ 1479 ctrl &= ~E1000_CTRL_ASDE; 1480 1481 /* Disable autoneg on the phy */ 1482 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1483 1484 /* Forcing Full or Half Duplex? */ 1485 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1486 ctrl &= ~E1000_CTRL_FD; 1487 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1488 e_dbg("Half Duplex\n"); 1489 } else { 1490 ctrl |= E1000_CTRL_FD; 1491 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1492 e_dbg("Full Duplex\n"); 1493 } 1494 1495 /* Forcing 10mb or 100mb? */ 1496 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1497 ctrl |= E1000_CTRL_SPD_100; 1498 *phy_ctrl |= MII_CR_SPEED_100; 1499 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1500 e_dbg("Forcing 100mb\n"); 1501 } else { 1502 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1503 *phy_ctrl |= MII_CR_SPEED_10; 1504 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1505 e_dbg("Forcing 10mb\n"); 1506 } 1507 1508 e1000e_config_collision_dist(hw); 1509 1510 ew32(CTRL, ctrl); 1511 } 1512 1513 /** 1514 * e1000e_set_d3_lplu_state - Sets low power link up state for D3 1515 * @hw: pointer to the HW structure 1516 * @active: boolean used to enable/disable lplu 1517 * 1518 * Success returns 0, Failure returns 1 1519 * 1520 * The low power link up (lplu) state is set to the power management level D3 1521 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1522 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1523 * is used during Dx states where the power conservation is most important. 1524 * During driver activity, SmartSpeed should be enabled so performance is 1525 * maintained. 1526 **/ 1527 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1528 { 1529 struct e1000_phy_info *phy = &hw->phy; 1530 s32 ret_val; 1531 u16 data; 1532 1533 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1534 if (ret_val) 1535 return ret_val; 1536 1537 if (!active) { 1538 data &= ~IGP02E1000_PM_D3_LPLU; 1539 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1540 if (ret_val) 1541 return ret_val; 1542 /* 1543 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1544 * during Dx states where the power conservation is most 1545 * important. During driver activity we should enable 1546 * SmartSpeed, so performance is maintained. 1547 */ 1548 if (phy->smart_speed == e1000_smart_speed_on) { 1549 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1550 &data); 1551 if (ret_val) 1552 return ret_val; 1553 1554 data |= IGP01E1000_PSCFR_SMART_SPEED; 1555 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1556 data); 1557 if (ret_val) 1558 return ret_val; 1559 } else if (phy->smart_speed == e1000_smart_speed_off) { 1560 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1561 &data); 1562 if (ret_val) 1563 return ret_val; 1564 1565 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1566 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1567 data); 1568 if (ret_val) 1569 return ret_val; 1570 } 1571 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1572 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1573 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1574 data |= IGP02E1000_PM_D3_LPLU; 1575 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1576 if (ret_val) 1577 return ret_val; 1578 1579 /* When LPLU is enabled, we should disable SmartSpeed */ 1580 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 1581 if (ret_val) 1582 return ret_val; 1583 1584 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1585 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 1586 } 1587 1588 return ret_val; 1589 } 1590 1591 /** 1592 * e1000e_check_downshift - Checks whether a downshift in speed occurred 1593 * @hw: pointer to the HW structure 1594 * 1595 * Success returns 0, Failure returns 1 1596 * 1597 * A downshift is detected by querying the PHY link health. 1598 **/ 1599 s32 e1000e_check_downshift(struct e1000_hw *hw) 1600 { 1601 struct e1000_phy_info *phy = &hw->phy; 1602 s32 ret_val; 1603 u16 phy_data, offset, mask; 1604 1605 switch (phy->type) { 1606 case e1000_phy_m88: 1607 case e1000_phy_gg82563: 1608 case e1000_phy_bm: 1609 case e1000_phy_82578: 1610 offset = M88E1000_PHY_SPEC_STATUS; 1611 mask = M88E1000_PSSR_DOWNSHIFT; 1612 break; 1613 case e1000_phy_igp_2: 1614 case e1000_phy_igp_3: 1615 offset = IGP01E1000_PHY_LINK_HEALTH; 1616 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1617 break; 1618 default: 1619 /* speed downshift not supported */ 1620 phy->speed_downgraded = false; 1621 return 0; 1622 } 1623 1624 ret_val = e1e_rphy(hw, offset, &phy_data); 1625 1626 if (!ret_val) 1627 phy->speed_downgraded = (phy_data & mask); 1628 1629 return ret_val; 1630 } 1631 1632 /** 1633 * e1000_check_polarity_m88 - Checks the polarity. 1634 * @hw: pointer to the HW structure 1635 * 1636 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1637 * 1638 * Polarity is determined based on the PHY specific status register. 1639 **/ 1640 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1641 { 1642 struct e1000_phy_info *phy = &hw->phy; 1643 s32 ret_val; 1644 u16 data; 1645 1646 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); 1647 1648 if (!ret_val) 1649 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1650 ? e1000_rev_polarity_reversed 1651 : e1000_rev_polarity_normal; 1652 1653 return ret_val; 1654 } 1655 1656 /** 1657 * e1000_check_polarity_igp - Checks the polarity. 1658 * @hw: pointer to the HW structure 1659 * 1660 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1661 * 1662 * Polarity is determined based on the PHY port status register, and the 1663 * current speed (since there is no polarity at 100Mbps). 1664 **/ 1665 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1666 { 1667 struct e1000_phy_info *phy = &hw->phy; 1668 s32 ret_val; 1669 u16 data, offset, mask; 1670 1671 /* 1672 * Polarity is determined based on the speed of 1673 * our connection. 1674 */ 1675 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1676 if (ret_val) 1677 return ret_val; 1678 1679 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1680 IGP01E1000_PSSR_SPEED_1000MBPS) { 1681 offset = IGP01E1000_PHY_PCS_INIT_REG; 1682 mask = IGP01E1000_PHY_POLARITY_MASK; 1683 } else { 1684 /* 1685 * This really only applies to 10Mbps since 1686 * there is no polarity for 100Mbps (always 0). 1687 */ 1688 offset = IGP01E1000_PHY_PORT_STATUS; 1689 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1690 } 1691 1692 ret_val = e1e_rphy(hw, offset, &data); 1693 1694 if (!ret_val) 1695 phy->cable_polarity = (data & mask) 1696 ? e1000_rev_polarity_reversed 1697 : e1000_rev_polarity_normal; 1698 1699 return ret_val; 1700 } 1701 1702 /** 1703 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1704 * @hw: pointer to the HW structure 1705 * 1706 * Polarity is determined on the polarity reversal feature being enabled. 1707 **/ 1708 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 1709 { 1710 struct e1000_phy_info *phy = &hw->phy; 1711 s32 ret_val; 1712 u16 phy_data, offset, mask; 1713 1714 /* 1715 * Polarity is determined based on the reversal feature being enabled. 1716 */ 1717 if (phy->polarity_correction) { 1718 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1719 mask = IFE_PESC_POLARITY_REVERSED; 1720 } else { 1721 offset = IFE_PHY_SPECIAL_CONTROL; 1722 mask = IFE_PSC_FORCE_POLARITY; 1723 } 1724 1725 ret_val = e1e_rphy(hw, offset, &phy_data); 1726 1727 if (!ret_val) 1728 phy->cable_polarity = (phy_data & mask) 1729 ? e1000_rev_polarity_reversed 1730 : e1000_rev_polarity_normal; 1731 1732 return ret_val; 1733 } 1734 1735 /** 1736 * e1000_wait_autoneg - Wait for auto-neg completion 1737 * @hw: pointer to the HW structure 1738 * 1739 * Waits for auto-negotiation to complete or for the auto-negotiation time 1740 * limit to expire, which ever happens first. 1741 **/ 1742 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 1743 { 1744 s32 ret_val = 0; 1745 u16 i, phy_status; 1746 1747 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1748 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1749 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1750 if (ret_val) 1751 break; 1752 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1753 if (ret_val) 1754 break; 1755 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1756 break; 1757 msleep(100); 1758 } 1759 1760 /* 1761 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1762 * has completed. 1763 */ 1764 return ret_val; 1765 } 1766 1767 /** 1768 * e1000e_phy_has_link_generic - Polls PHY for link 1769 * @hw: pointer to the HW structure 1770 * @iterations: number of times to poll for link 1771 * @usec_interval: delay between polling attempts 1772 * @success: pointer to whether polling was successful or not 1773 * 1774 * Polls the PHY status register for link, 'iterations' number of times. 1775 **/ 1776 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1777 u32 usec_interval, bool *success) 1778 { 1779 s32 ret_val = 0; 1780 u16 i, phy_status; 1781 1782 for (i = 0; i < iterations; i++) { 1783 /* 1784 * Some PHYs require the PHY_STATUS register to be read 1785 * twice due to the link bit being sticky. No harm doing 1786 * it across the board. 1787 */ 1788 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1789 if (ret_val) 1790 /* 1791 * If the first read fails, another entity may have 1792 * ownership of the resources, wait and try again to 1793 * see if they have relinquished the resources yet. 1794 */ 1795 udelay(usec_interval); 1796 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1797 if (ret_val) 1798 break; 1799 if (phy_status & MII_SR_LINK_STATUS) 1800 break; 1801 if (usec_interval >= 1000) 1802 mdelay(usec_interval/1000); 1803 else 1804 udelay(usec_interval); 1805 } 1806 1807 *success = (i < iterations); 1808 1809 return ret_val; 1810 } 1811 1812 /** 1813 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY 1814 * @hw: pointer to the HW structure 1815 * 1816 * Reads the PHY specific status register to retrieve the cable length 1817 * information. The cable length is determined by averaging the minimum and 1818 * maximum values to get the "average" cable length. The m88 PHY has four 1819 * possible cable length values, which are: 1820 * Register Value Cable Length 1821 * 0 < 50 meters 1822 * 1 50 - 80 meters 1823 * 2 80 - 110 meters 1824 * 3 110 - 140 meters 1825 * 4 > 140 meters 1826 **/ 1827 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) 1828 { 1829 struct e1000_phy_info *phy = &hw->phy; 1830 s32 ret_val; 1831 u16 phy_data, index; 1832 1833 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1834 if (ret_val) 1835 goto out; 1836 1837 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1838 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1839 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1840 ret_val = -E1000_ERR_PHY; 1841 goto out; 1842 } 1843 1844 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1845 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1846 1847 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1848 1849 out: 1850 return ret_val; 1851 } 1852 1853 /** 1854 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1855 * @hw: pointer to the HW structure 1856 * 1857 * The automatic gain control (agc) normalizes the amplitude of the 1858 * received signal, adjusting for the attenuation produced by the 1859 * cable. By reading the AGC registers, which represent the 1860 * combination of coarse and fine gain value, the value can be put 1861 * into a lookup table to obtain the approximate cable length 1862 * for each channel. 1863 **/ 1864 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) 1865 { 1866 struct e1000_phy_info *phy = &hw->phy; 1867 s32 ret_val; 1868 u16 phy_data, i, agc_value = 0; 1869 u16 cur_agc_index, max_agc_index = 0; 1870 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1871 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1872 IGP02E1000_PHY_AGC_A, 1873 IGP02E1000_PHY_AGC_B, 1874 IGP02E1000_PHY_AGC_C, 1875 IGP02E1000_PHY_AGC_D 1876 }; 1877 1878 /* Read the AGC registers for all channels */ 1879 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1880 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); 1881 if (ret_val) 1882 return ret_val; 1883 1884 /* 1885 * Getting bits 15:9, which represent the combination of 1886 * coarse and fine gain values. The result is a number 1887 * that can be put into the lookup table to obtain the 1888 * approximate cable length. 1889 */ 1890 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1891 IGP02E1000_AGC_LENGTH_MASK; 1892 1893 /* Array index bound check. */ 1894 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1895 (cur_agc_index == 0)) 1896 return -E1000_ERR_PHY; 1897 1898 /* Remove min & max AGC values from calculation. */ 1899 if (e1000_igp_2_cable_length_table[min_agc_index] > 1900 e1000_igp_2_cable_length_table[cur_agc_index]) 1901 min_agc_index = cur_agc_index; 1902 if (e1000_igp_2_cable_length_table[max_agc_index] < 1903 e1000_igp_2_cable_length_table[cur_agc_index]) 1904 max_agc_index = cur_agc_index; 1905 1906 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1907 } 1908 1909 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1910 e1000_igp_2_cable_length_table[max_agc_index]); 1911 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1912 1913 /* Calculate cable length with the error range of +/- 10 meters. */ 1914 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1915 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1916 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1917 1918 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1919 1920 return ret_val; 1921 } 1922 1923 /** 1924 * e1000e_get_phy_info_m88 - Retrieve PHY information 1925 * @hw: pointer to the HW structure 1926 * 1927 * Valid for only copper links. Read the PHY status register (sticky read) 1928 * to verify that link is up. Read the PHY special control register to 1929 * determine the polarity and 10base-T extended distance. Read the PHY 1930 * special status register to determine MDI/MDIx and current speed. If 1931 * speed is 1000, then determine cable length, local and remote receiver. 1932 **/ 1933 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) 1934 { 1935 struct e1000_phy_info *phy = &hw->phy; 1936 s32 ret_val; 1937 u16 phy_data; 1938 bool link; 1939 1940 if (phy->media_type != e1000_media_type_copper) { 1941 e_dbg("Phy info is only valid for copper media\n"); 1942 return -E1000_ERR_CONFIG; 1943 } 1944 1945 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1946 if (ret_val) 1947 return ret_val; 1948 1949 if (!link) { 1950 e_dbg("Phy info is only valid if link is up\n"); 1951 return -E1000_ERR_CONFIG; 1952 } 1953 1954 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1955 if (ret_val) 1956 return ret_val; 1957 1958 phy->polarity_correction = (phy_data & 1959 M88E1000_PSCR_POLARITY_REVERSAL); 1960 1961 ret_val = e1000_check_polarity_m88(hw); 1962 if (ret_val) 1963 return ret_val; 1964 1965 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1966 if (ret_val) 1967 return ret_val; 1968 1969 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX); 1970 1971 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1972 ret_val = e1000_get_cable_length(hw); 1973 if (ret_val) 1974 return ret_val; 1975 1976 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); 1977 if (ret_val) 1978 return ret_val; 1979 1980 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1981 ? e1000_1000t_rx_status_ok 1982 : e1000_1000t_rx_status_not_ok; 1983 1984 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1985 ? e1000_1000t_rx_status_ok 1986 : e1000_1000t_rx_status_not_ok; 1987 } else { 1988 /* Set values to "undefined" */ 1989 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1990 phy->local_rx = e1000_1000t_rx_status_undefined; 1991 phy->remote_rx = e1000_1000t_rx_status_undefined; 1992 } 1993 1994 return ret_val; 1995 } 1996 1997 /** 1998 * e1000e_get_phy_info_igp - Retrieve igp PHY information 1999 * @hw: pointer to the HW structure 2000 * 2001 * Read PHY status to determine if link is up. If link is up, then 2002 * set/determine 10base-T extended distance and polarity correction. Read 2003 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2004 * determine on the cable length, local and remote receiver. 2005 **/ 2006 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) 2007 { 2008 struct e1000_phy_info *phy = &hw->phy; 2009 s32 ret_val; 2010 u16 data; 2011 bool link; 2012 2013 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 2014 if (ret_val) 2015 return ret_val; 2016 2017 if (!link) { 2018 e_dbg("Phy info is only valid if link is up\n"); 2019 return -E1000_ERR_CONFIG; 2020 } 2021 2022 phy->polarity_correction = true; 2023 2024 ret_val = e1000_check_polarity_igp(hw); 2025 if (ret_val) 2026 return ret_val; 2027 2028 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2029 if (ret_val) 2030 return ret_val; 2031 2032 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX); 2033 2034 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2035 IGP01E1000_PSSR_SPEED_1000MBPS) { 2036 ret_val = e1000_get_cable_length(hw); 2037 if (ret_val) 2038 return ret_val; 2039 2040 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); 2041 if (ret_val) 2042 return ret_val; 2043 2044 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2045 ? e1000_1000t_rx_status_ok 2046 : e1000_1000t_rx_status_not_ok; 2047 2048 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2049 ? e1000_1000t_rx_status_ok 2050 : e1000_1000t_rx_status_not_ok; 2051 } else { 2052 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2053 phy->local_rx = e1000_1000t_rx_status_undefined; 2054 phy->remote_rx = e1000_1000t_rx_status_undefined; 2055 } 2056 2057 return ret_val; 2058 } 2059 2060 /** 2061 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2062 * @hw: pointer to the HW structure 2063 * 2064 * Populates "phy" structure with various feature states. 2065 **/ 2066 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2067 { 2068 struct e1000_phy_info *phy = &hw->phy; 2069 s32 ret_val; 2070 u16 data; 2071 bool link; 2072 2073 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 2074 if (ret_val) 2075 goto out; 2076 2077 if (!link) { 2078 e_dbg("Phy info is only valid if link is up\n"); 2079 ret_val = -E1000_ERR_CONFIG; 2080 goto out; 2081 } 2082 2083 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2084 if (ret_val) 2085 goto out; 2086 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 2087 ? false : true; 2088 2089 if (phy->polarity_correction) { 2090 ret_val = e1000_check_polarity_ife(hw); 2091 if (ret_val) 2092 goto out; 2093 } else { 2094 /* Polarity is forced */ 2095 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 2096 ? e1000_rev_polarity_reversed 2097 : e1000_rev_polarity_normal; 2098 } 2099 2100 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 2101 if (ret_val) 2102 goto out; 2103 2104 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false; 2105 2106 /* The following parameters are undefined for 10/100 operation. */ 2107 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2108 phy->local_rx = e1000_1000t_rx_status_undefined; 2109 phy->remote_rx = e1000_1000t_rx_status_undefined; 2110 2111 out: 2112 return ret_val; 2113 } 2114 2115 /** 2116 * e1000e_phy_sw_reset - PHY software reset 2117 * @hw: pointer to the HW structure 2118 * 2119 * Does a software reset of the PHY by reading the PHY control register and 2120 * setting/write the control register reset bit to the PHY. 2121 **/ 2122 s32 e1000e_phy_sw_reset(struct e1000_hw *hw) 2123 { 2124 s32 ret_val; 2125 u16 phy_ctrl; 2126 2127 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); 2128 if (ret_val) 2129 return ret_val; 2130 2131 phy_ctrl |= MII_CR_RESET; 2132 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); 2133 if (ret_val) 2134 return ret_val; 2135 2136 udelay(1); 2137 2138 return ret_val; 2139 } 2140 2141 /** 2142 * e1000e_phy_hw_reset_generic - PHY hardware reset 2143 * @hw: pointer to the HW structure 2144 * 2145 * Verify the reset block is not blocking us from resetting. Acquire 2146 * semaphore (if necessary) and read/set/write the device control reset 2147 * bit in the PHY. Wait the appropriate delay time for the device to 2148 * reset and release the semaphore (if necessary). 2149 **/ 2150 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) 2151 { 2152 struct e1000_phy_info *phy = &hw->phy; 2153 s32 ret_val; 2154 u32 ctrl; 2155 2156 ret_val = e1000_check_reset_block(hw); 2157 if (ret_val) 2158 return 0; 2159 2160 ret_val = phy->ops.acquire(hw); 2161 if (ret_val) 2162 return ret_val; 2163 2164 ctrl = er32(CTRL); 2165 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 2166 e1e_flush(); 2167 2168 udelay(phy->reset_delay_us); 2169 2170 ew32(CTRL, ctrl); 2171 e1e_flush(); 2172 2173 udelay(150); 2174 2175 phy->ops.release(hw); 2176 2177 return e1000_get_phy_cfg_done(hw); 2178 } 2179 2180 /** 2181 * e1000e_get_cfg_done - Generic configuration done 2182 * @hw: pointer to the HW structure 2183 * 2184 * Generic function to wait 10 milli-seconds for configuration to complete 2185 * and return success. 2186 **/ 2187 s32 e1000e_get_cfg_done(struct e1000_hw *hw) 2188 { 2189 mdelay(10); 2190 return 0; 2191 } 2192 2193 /** 2194 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY 2195 * @hw: pointer to the HW structure 2196 * 2197 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2198 **/ 2199 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) 2200 { 2201 e_dbg("Running IGP 3 PHY init script\n"); 2202 2203 /* PHY init IGP 3 */ 2204 /* Enable rise/fall, 10-mode work in class-A */ 2205 e1e_wphy(hw, 0x2F5B, 0x9018); 2206 /* Remove all caps from Replica path filter */ 2207 e1e_wphy(hw, 0x2F52, 0x0000); 2208 /* Bias trimming for ADC, AFE and Driver (Default) */ 2209 e1e_wphy(hw, 0x2FB1, 0x8B24); 2210 /* Increase Hybrid poly bias */ 2211 e1e_wphy(hw, 0x2FB2, 0xF8F0); 2212 /* Add 4% to Tx amplitude in Gig mode */ 2213 e1e_wphy(hw, 0x2010, 0x10B0); 2214 /* Disable trimming (TTT) */ 2215 e1e_wphy(hw, 0x2011, 0x0000); 2216 /* Poly DC correction to 94.6% + 2% for all channels */ 2217 e1e_wphy(hw, 0x20DD, 0x249A); 2218 /* ABS DC correction to 95.9% */ 2219 e1e_wphy(hw, 0x20DE, 0x00D3); 2220 /* BG temp curve trim */ 2221 e1e_wphy(hw, 0x28B4, 0x04CE); 2222 /* Increasing ADC OPAMP stage 1 currents to max */ 2223 e1e_wphy(hw, 0x2F70, 0x29E4); 2224 /* Force 1000 ( required for enabling PHY regs configuration) */ 2225 e1e_wphy(hw, 0x0000, 0x0140); 2226 /* Set upd_freq to 6 */ 2227 e1e_wphy(hw, 0x1F30, 0x1606); 2228 /* Disable NPDFE */ 2229 e1e_wphy(hw, 0x1F31, 0xB814); 2230 /* Disable adaptive fixed FFE (Default) */ 2231 e1e_wphy(hw, 0x1F35, 0x002A); 2232 /* Enable FFE hysteresis */ 2233 e1e_wphy(hw, 0x1F3E, 0x0067); 2234 /* Fixed FFE for short cable lengths */ 2235 e1e_wphy(hw, 0x1F54, 0x0065); 2236 /* Fixed FFE for medium cable lengths */ 2237 e1e_wphy(hw, 0x1F55, 0x002A); 2238 /* Fixed FFE for long cable lengths */ 2239 e1e_wphy(hw, 0x1F56, 0x002A); 2240 /* Enable Adaptive Clip Threshold */ 2241 e1e_wphy(hw, 0x1F72, 0x3FB0); 2242 /* AHT reset limit to 1 */ 2243 e1e_wphy(hw, 0x1F76, 0xC0FF); 2244 /* Set AHT master delay to 127 msec */ 2245 e1e_wphy(hw, 0x1F77, 0x1DEC); 2246 /* Set scan bits for AHT */ 2247 e1e_wphy(hw, 0x1F78, 0xF9EF); 2248 /* Set AHT Preset bits */ 2249 e1e_wphy(hw, 0x1F79, 0x0210); 2250 /* Change integ_factor of channel A to 3 */ 2251 e1e_wphy(hw, 0x1895, 0x0003); 2252 /* Change prop_factor of channels BCD to 8 */ 2253 e1e_wphy(hw, 0x1796, 0x0008); 2254 /* Change cg_icount + enable integbp for channels BCD */ 2255 e1e_wphy(hw, 0x1798, 0xD008); 2256 /* 2257 * Change cg_icount + enable integbp + change prop_factor_master 2258 * to 8 for channel A 2259 */ 2260 e1e_wphy(hw, 0x1898, 0xD918); 2261 /* Disable AHT in Slave mode on channel A */ 2262 e1e_wphy(hw, 0x187A, 0x0800); 2263 /* 2264 * Enable LPLU and disable AN to 1000 in non-D0a states, 2265 * Enable SPD+B2B 2266 */ 2267 e1e_wphy(hw, 0x0019, 0x008D); 2268 /* Enable restart AN on an1000_dis change */ 2269 e1e_wphy(hw, 0x001B, 0x2080); 2270 /* Enable wh_fifo read clock in 10/100 modes */ 2271 e1e_wphy(hw, 0x0014, 0x0045); 2272 /* Restart AN, Speed selection is 1000 */ 2273 e1e_wphy(hw, 0x0000, 0x1340); 2274 2275 return 0; 2276 } 2277 2278 /* Internal function pointers */ 2279 2280 /** 2281 * e1000_get_phy_cfg_done - Generic PHY configuration done 2282 * @hw: pointer to the HW structure 2283 * 2284 * Return success if silicon family did not implement a family specific 2285 * get_cfg_done function. 2286 **/ 2287 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 2288 { 2289 if (hw->phy.ops.get_cfg_done) 2290 return hw->phy.ops.get_cfg_done(hw); 2291 2292 return 0; 2293 } 2294 2295 /** 2296 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex 2297 * @hw: pointer to the HW structure 2298 * 2299 * When the silicon family has not implemented a forced speed/duplex 2300 * function for the PHY, simply return 0. 2301 **/ 2302 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 2303 { 2304 if (hw->phy.ops.force_speed_duplex) 2305 return hw->phy.ops.force_speed_duplex(hw); 2306 2307 return 0; 2308 } 2309 2310 /** 2311 * e1000e_get_phy_type_from_id - Get PHY type from id 2312 * @phy_id: phy_id read from the phy 2313 * 2314 * Returns the phy type from the id. 2315 **/ 2316 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) 2317 { 2318 enum e1000_phy_type phy_type = e1000_phy_unknown; 2319 2320 switch (phy_id) { 2321 case M88E1000_I_PHY_ID: 2322 case M88E1000_E_PHY_ID: 2323 case M88E1111_I_PHY_ID: 2324 case M88E1011_I_PHY_ID: 2325 phy_type = e1000_phy_m88; 2326 break; 2327 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2328 phy_type = e1000_phy_igp_2; 2329 break; 2330 case GG82563_E_PHY_ID: 2331 phy_type = e1000_phy_gg82563; 2332 break; 2333 case IGP03E1000_E_PHY_ID: 2334 phy_type = e1000_phy_igp_3; 2335 break; 2336 case IFE_E_PHY_ID: 2337 case IFE_PLUS_E_PHY_ID: 2338 case IFE_C_E_PHY_ID: 2339 phy_type = e1000_phy_ife; 2340 break; 2341 case BME1000_E_PHY_ID: 2342 case BME1000_E_PHY_ID_R2: 2343 phy_type = e1000_phy_bm; 2344 break; 2345 case I82578_E_PHY_ID: 2346 phy_type = e1000_phy_82578; 2347 break; 2348 case I82577_E_PHY_ID: 2349 phy_type = e1000_phy_82577; 2350 break; 2351 case I82579_E_PHY_ID: 2352 phy_type = e1000_phy_82579; 2353 break; 2354 default: 2355 phy_type = e1000_phy_unknown; 2356 break; 2357 } 2358 return phy_type; 2359 } 2360 2361 /** 2362 * e1000e_determine_phy_address - Determines PHY address. 2363 * @hw: pointer to the HW structure 2364 * 2365 * This uses a trial and error method to loop through possible PHY 2366 * addresses. It tests each by reading the PHY ID registers and 2367 * checking for a match. 2368 **/ 2369 s32 e1000e_determine_phy_address(struct e1000_hw *hw) 2370 { 2371 s32 ret_val = -E1000_ERR_PHY_TYPE; 2372 u32 phy_addr = 0; 2373 u32 i; 2374 enum e1000_phy_type phy_type = e1000_phy_unknown; 2375 2376 hw->phy.id = phy_type; 2377 2378 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2379 hw->phy.addr = phy_addr; 2380 i = 0; 2381 2382 do { 2383 e1000e_get_phy_id(hw); 2384 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 2385 2386 /* 2387 * If phy_type is valid, break - we found our 2388 * PHY address 2389 */ 2390 if (phy_type != e1000_phy_unknown) { 2391 ret_val = 0; 2392 goto out; 2393 } 2394 usleep_range(1000, 2000); 2395 i++; 2396 } while (i < 10); 2397 } 2398 2399 out: 2400 return ret_val; 2401 } 2402 2403 /** 2404 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2405 * @page: page to access 2406 * 2407 * Returns the phy address for the page requested. 2408 **/ 2409 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2410 { 2411 u32 phy_addr = 2; 2412 2413 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2414 phy_addr = 1; 2415 2416 return phy_addr; 2417 } 2418 2419 /** 2420 * e1000e_write_phy_reg_bm - Write BM PHY register 2421 * @hw: pointer to the HW structure 2422 * @offset: register offset to write to 2423 * @data: data to write at register offset 2424 * 2425 * Acquires semaphore, if necessary, then writes the data to PHY register 2426 * at the offset. Release any acquired semaphores before exiting. 2427 **/ 2428 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2429 { 2430 s32 ret_val; 2431 u32 page = offset >> IGP_PAGE_SHIFT; 2432 2433 ret_val = hw->phy.ops.acquire(hw); 2434 if (ret_val) 2435 return ret_val; 2436 2437 /* Page 800 works differently than the rest so it has its own func */ 2438 if (page == BM_WUC_PAGE) { 2439 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2440 false, false); 2441 goto out; 2442 } 2443 2444 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2445 2446 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2447 u32 page_shift, page_select; 2448 2449 /* 2450 * Page select is register 31 for phy address 1 and 22 for 2451 * phy address 2 and 3. Page select is shifted only for 2452 * phy address 1. 2453 */ 2454 if (hw->phy.addr == 1) { 2455 page_shift = IGP_PAGE_SHIFT; 2456 page_select = IGP01E1000_PHY_PAGE_SELECT; 2457 } else { 2458 page_shift = 0; 2459 page_select = BM_PHY_PAGE_SELECT; 2460 } 2461 2462 /* Page is shifted left, PHY expects (page x 32) */ 2463 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 2464 (page << page_shift)); 2465 if (ret_val) 2466 goto out; 2467 } 2468 2469 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2470 data); 2471 2472 out: 2473 hw->phy.ops.release(hw); 2474 return ret_val; 2475 } 2476 2477 /** 2478 * e1000e_read_phy_reg_bm - Read BM PHY register 2479 * @hw: pointer to the HW structure 2480 * @offset: register offset to be read 2481 * @data: pointer to the read data 2482 * 2483 * Acquires semaphore, if necessary, then reads the PHY register at offset 2484 * and storing the retrieved information in data. Release any acquired 2485 * semaphores before exiting. 2486 **/ 2487 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2488 { 2489 s32 ret_val; 2490 u32 page = offset >> IGP_PAGE_SHIFT; 2491 2492 ret_val = hw->phy.ops.acquire(hw); 2493 if (ret_val) 2494 return ret_val; 2495 2496 /* Page 800 works differently than the rest so it has its own func */ 2497 if (page == BM_WUC_PAGE) { 2498 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2499 true, false); 2500 goto out; 2501 } 2502 2503 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2504 2505 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2506 u32 page_shift, page_select; 2507 2508 /* 2509 * Page select is register 31 for phy address 1 and 22 for 2510 * phy address 2 and 3. Page select is shifted only for 2511 * phy address 1. 2512 */ 2513 if (hw->phy.addr == 1) { 2514 page_shift = IGP_PAGE_SHIFT; 2515 page_select = IGP01E1000_PHY_PAGE_SELECT; 2516 } else { 2517 page_shift = 0; 2518 page_select = BM_PHY_PAGE_SELECT; 2519 } 2520 2521 /* Page is shifted left, PHY expects (page x 32) */ 2522 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 2523 (page << page_shift)); 2524 if (ret_val) 2525 goto out; 2526 } 2527 2528 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2529 data); 2530 out: 2531 hw->phy.ops.release(hw); 2532 return ret_val; 2533 } 2534 2535 /** 2536 * e1000e_read_phy_reg_bm2 - Read BM PHY register 2537 * @hw: pointer to the HW structure 2538 * @offset: register offset to be read 2539 * @data: pointer to the read data 2540 * 2541 * Acquires semaphore, if necessary, then reads the PHY register at offset 2542 * and storing the retrieved information in data. Release any acquired 2543 * semaphores before exiting. 2544 **/ 2545 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2546 { 2547 s32 ret_val; 2548 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2549 2550 ret_val = hw->phy.ops.acquire(hw); 2551 if (ret_val) 2552 return ret_val; 2553 2554 /* Page 800 works differently than the rest so it has its own func */ 2555 if (page == BM_WUC_PAGE) { 2556 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2557 true, false); 2558 goto out; 2559 } 2560 2561 hw->phy.addr = 1; 2562 2563 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2564 2565 /* Page is shifted left, PHY expects (page x 32) */ 2566 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2567 page); 2568 2569 if (ret_val) 2570 goto out; 2571 } 2572 2573 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2574 data); 2575 out: 2576 hw->phy.ops.release(hw); 2577 return ret_val; 2578 } 2579 2580 /** 2581 * e1000e_write_phy_reg_bm2 - Write BM PHY register 2582 * @hw: pointer to the HW structure 2583 * @offset: register offset to write to 2584 * @data: data to write at register offset 2585 * 2586 * Acquires semaphore, if necessary, then writes the data to PHY register 2587 * at the offset. Release any acquired semaphores before exiting. 2588 **/ 2589 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2590 { 2591 s32 ret_val; 2592 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2593 2594 ret_val = hw->phy.ops.acquire(hw); 2595 if (ret_val) 2596 return ret_val; 2597 2598 /* Page 800 works differently than the rest so it has its own func */ 2599 if (page == BM_WUC_PAGE) { 2600 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2601 false, false); 2602 goto out; 2603 } 2604 2605 hw->phy.addr = 1; 2606 2607 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2608 /* Page is shifted left, PHY expects (page x 32) */ 2609 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2610 page); 2611 2612 if (ret_val) 2613 goto out; 2614 } 2615 2616 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2617 data); 2618 2619 out: 2620 hw->phy.ops.release(hw); 2621 return ret_val; 2622 } 2623 2624 /** 2625 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 2626 * @hw: pointer to the HW structure 2627 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 2628 * 2629 * Assumes semaphore already acquired and phy_reg points to a valid memory 2630 * address to store contents of the BM_WUC_ENABLE_REG register. 2631 **/ 2632 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 2633 { 2634 s32 ret_val; 2635 u16 temp; 2636 2637 /* All page select, port ctrl and wakeup registers use phy address 1 */ 2638 hw->phy.addr = 1; 2639 2640 /* Select Port Control Registers page */ 2641 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2642 if (ret_val) { 2643 e_dbg("Could not set Port Control page\n"); 2644 goto out; 2645 } 2646 2647 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2648 if (ret_val) { 2649 e_dbg("Could not read PHY register %d.%d\n", 2650 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2651 goto out; 2652 } 2653 2654 /* 2655 * Enable both PHY wakeup mode and Wakeup register page writes. 2656 * Prevent a power state change by disabling ME and Host PHY wakeup. 2657 */ 2658 temp = *phy_reg; 2659 temp |= BM_WUC_ENABLE_BIT; 2660 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 2661 2662 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 2663 if (ret_val) { 2664 e_dbg("Could not write PHY register %d.%d\n", 2665 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2666 goto out; 2667 } 2668 2669 /* Select Host Wakeup Registers page */ 2670 ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2671 2672 /* caller now able to write registers on the Wakeup registers page */ 2673 out: 2674 return ret_val; 2675 } 2676 2677 /** 2678 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 2679 * @hw: pointer to the HW structure 2680 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 2681 * 2682 * Restore BM_WUC_ENABLE_REG to its original value. 2683 * 2684 * Assumes semaphore already acquired and *phy_reg is the contents of the 2685 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 2686 * caller. 2687 **/ 2688 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 2689 { 2690 s32 ret_val = 0; 2691 2692 /* Select Port Control Registers page */ 2693 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2694 if (ret_val) { 2695 e_dbg("Could not set Port Control page\n"); 2696 goto out; 2697 } 2698 2699 /* Restore 769.17 to its original value */ 2700 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 2701 if (ret_val) 2702 e_dbg("Could not restore PHY register %d.%d\n", 2703 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2704 out: 2705 return ret_val; 2706 } 2707 2708 /** 2709 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 2710 * @hw: pointer to the HW structure 2711 * @offset: register offset to be read or written 2712 * @data: pointer to the data to read or write 2713 * @read: determines if operation is read or write 2714 * @page_set: BM_WUC_PAGE already set and access enabled 2715 * 2716 * Read the PHY register at offset and store the retrieved information in 2717 * data, or write data to PHY register at offset. Note the procedure to 2718 * access the PHY wakeup registers is different than reading the other PHY 2719 * registers. It works as such: 2720 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 2721 * 2) Set page to 800 for host (801 if we were manageability) 2722 * 3) Write the address using the address opcode (0x11) 2723 * 4) Read or write the data using the data opcode (0x12) 2724 * 5) Restore 769.17.2 to its original value 2725 * 2726 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 2727 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 2728 * 2729 * Assumes semaphore is already acquired. When page_set==true, assumes 2730 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 2731 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 2732 **/ 2733 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 2734 u16 *data, bool read, bool page_set) 2735 { 2736 s32 ret_val; 2737 u16 reg = BM_PHY_REG_NUM(offset); 2738 u16 page = BM_PHY_REG_PAGE(offset); 2739 u16 phy_reg = 0; 2740 2741 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 2742 if ((hw->mac.type == e1000_pchlan) && 2743 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2744 e_dbg("Attempting to access page %d while gig enabled.\n", 2745 page); 2746 2747 if (!page_set) { 2748 /* Enable access to PHY wakeup registers */ 2749 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2750 if (ret_val) { 2751 e_dbg("Could not enable PHY wakeup reg access\n"); 2752 goto out; 2753 } 2754 } 2755 2756 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); 2757 2758 /* Write the Wakeup register page offset value using opcode 0x11 */ 2759 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2760 if (ret_val) { 2761 e_dbg("Could not write address opcode to page %d\n", page); 2762 goto out; 2763 } 2764 2765 if (read) { 2766 /* Read the Wakeup register page value using opcode 0x12 */ 2767 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2768 data); 2769 } else { 2770 /* Write the Wakeup register page value using opcode 0x12 */ 2771 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2772 *data); 2773 } 2774 2775 if (ret_val) { 2776 e_dbg("Could not access PHY reg %d.%d\n", page, reg); 2777 goto out; 2778 } 2779 2780 if (!page_set) 2781 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2782 2783 out: 2784 return ret_val; 2785 } 2786 2787 /** 2788 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2789 * @hw: pointer to the HW structure 2790 * 2791 * In the case of a PHY power down to save power, or to turn off link during a 2792 * driver unload, or wake on lan is not enabled, restore the link to previous 2793 * settings. 2794 **/ 2795 void e1000_power_up_phy_copper(struct e1000_hw *hw) 2796 { 2797 u16 mii_reg = 0; 2798 2799 /* The PHY will retain its settings across a power down/up cycle */ 2800 e1e_rphy(hw, PHY_CONTROL, &mii_reg); 2801 mii_reg &= ~MII_CR_POWER_DOWN; 2802 e1e_wphy(hw, PHY_CONTROL, mii_reg); 2803 } 2804 2805 /** 2806 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2807 * @hw: pointer to the HW structure 2808 * 2809 * In the case of a PHY power down to save power, or to turn off link during a 2810 * driver unload, or wake on lan is not enabled, restore the link to previous 2811 * settings. 2812 **/ 2813 void e1000_power_down_phy_copper(struct e1000_hw *hw) 2814 { 2815 u16 mii_reg = 0; 2816 2817 /* The PHY will retain its settings across a power down/up cycle */ 2818 e1e_rphy(hw, PHY_CONTROL, &mii_reg); 2819 mii_reg |= MII_CR_POWER_DOWN; 2820 e1e_wphy(hw, PHY_CONTROL, mii_reg); 2821 usleep_range(1000, 2000); 2822 } 2823 2824 /** 2825 * e1000e_commit_phy - Soft PHY reset 2826 * @hw: pointer to the HW structure 2827 * 2828 * Performs a soft PHY reset on those that apply. This is a function pointer 2829 * entry point called by drivers. 2830 **/ 2831 s32 e1000e_commit_phy(struct e1000_hw *hw) 2832 { 2833 if (hw->phy.ops.commit) 2834 return hw->phy.ops.commit(hw); 2835 2836 return 0; 2837 } 2838 2839 /** 2840 * e1000_set_d0_lplu_state - Sets low power link up state for D0 2841 * @hw: pointer to the HW structure 2842 * @active: boolean used to enable/disable lplu 2843 * 2844 * Success returns 0, Failure returns 1 2845 * 2846 * The low power link up (lplu) state is set to the power management level D0 2847 * and SmartSpeed is disabled when active is true, else clear lplu for D0 2848 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2849 * is used during Dx states where the power conservation is most important. 2850 * During driver activity, SmartSpeed should be enabled so performance is 2851 * maintained. This is a function pointer entry point called by drivers. 2852 **/ 2853 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2854 { 2855 if (hw->phy.ops.set_d0_lplu_state) 2856 return hw->phy.ops.set_d0_lplu_state(hw, active); 2857 2858 return 0; 2859 } 2860 2861 /** 2862 * __e1000_read_phy_reg_hv - Read HV PHY register 2863 * @hw: pointer to the HW structure 2864 * @offset: register offset to be read 2865 * @data: pointer to the read data 2866 * @locked: semaphore has already been acquired or not 2867 * 2868 * Acquires semaphore, if necessary, then reads the PHY register at offset 2869 * and stores the retrieved information in data. Release any acquired 2870 * semaphore before exiting. 2871 **/ 2872 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 2873 bool locked, bool page_set) 2874 { 2875 s32 ret_val; 2876 u16 page = BM_PHY_REG_PAGE(offset); 2877 u16 reg = BM_PHY_REG_NUM(offset); 2878 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2879 2880 if (!locked) { 2881 ret_val = hw->phy.ops.acquire(hw); 2882 if (ret_val) 2883 return ret_val; 2884 } 2885 2886 /* Page 800 works differently than the rest so it has its own func */ 2887 if (page == BM_WUC_PAGE) { 2888 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2889 true, page_set); 2890 goto out; 2891 } 2892 2893 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 2894 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 2895 data, true); 2896 goto out; 2897 } 2898 2899 if (!page_set) { 2900 if (page == HV_INTC_FC_PAGE_START) 2901 page = 0; 2902 2903 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2904 /* Page is shifted left, PHY expects (page x 32) */ 2905 ret_val = e1000_set_page_igp(hw, 2906 (page << IGP_PAGE_SHIFT)); 2907 2908 hw->phy.addr = phy_addr; 2909 2910 if (ret_val) 2911 goto out; 2912 } 2913 } 2914 2915 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 2916 page << IGP_PAGE_SHIFT, reg); 2917 2918 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2919 data); 2920 out: 2921 if (!locked) 2922 hw->phy.ops.release(hw); 2923 2924 return ret_val; 2925 } 2926 2927 /** 2928 * e1000_read_phy_reg_hv - Read HV PHY register 2929 * @hw: pointer to the HW structure 2930 * @offset: register offset to be read 2931 * @data: pointer to the read data 2932 * 2933 * Acquires semaphore then reads the PHY register at offset and stores 2934 * the retrieved information in data. Release the acquired semaphore 2935 * before exiting. 2936 **/ 2937 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2938 { 2939 return __e1000_read_phy_reg_hv(hw, offset, data, false, false); 2940 } 2941 2942 /** 2943 * e1000_read_phy_reg_hv_locked - Read HV PHY register 2944 * @hw: pointer to the HW structure 2945 * @offset: register offset to be read 2946 * @data: pointer to the read data 2947 * 2948 * Reads the PHY register at offset and stores the retrieved information 2949 * in data. Assumes semaphore already acquired. 2950 **/ 2951 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 2952 { 2953 return __e1000_read_phy_reg_hv(hw, offset, data, true, false); 2954 } 2955 2956 /** 2957 * e1000_read_phy_reg_page_hv - Read HV PHY register 2958 * @hw: pointer to the HW structure 2959 * @offset: register offset to write to 2960 * @data: data to write at register offset 2961 * 2962 * Reads the PHY register at offset and stores the retrieved information 2963 * in data. Assumes semaphore already acquired and page already set. 2964 **/ 2965 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2966 { 2967 return __e1000_read_phy_reg_hv(hw, offset, data, true, true); 2968 } 2969 2970 /** 2971 * __e1000_write_phy_reg_hv - Write HV PHY register 2972 * @hw: pointer to the HW structure 2973 * @offset: register offset to write to 2974 * @data: data to write at register offset 2975 * @locked: semaphore has already been acquired or not 2976 * 2977 * Acquires semaphore, if necessary, then writes the data to PHY register 2978 * at the offset. Release any acquired semaphores before exiting. 2979 **/ 2980 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 2981 bool locked, bool page_set) 2982 { 2983 s32 ret_val; 2984 u16 page = BM_PHY_REG_PAGE(offset); 2985 u16 reg = BM_PHY_REG_NUM(offset); 2986 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2987 2988 if (!locked) { 2989 ret_val = hw->phy.ops.acquire(hw); 2990 if (ret_val) 2991 return ret_val; 2992 } 2993 2994 /* Page 800 works differently than the rest so it has its own func */ 2995 if (page == BM_WUC_PAGE) { 2996 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2997 false, page_set); 2998 goto out; 2999 } 3000 3001 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3002 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3003 &data, false); 3004 goto out; 3005 } 3006 3007 if (!page_set) { 3008 if (page == HV_INTC_FC_PAGE_START) 3009 page = 0; 3010 3011 /* 3012 * Workaround MDIO accesses being disabled after entering IEEE 3013 * Power Down (when bit 11 of the PHY Control register is set) 3014 */ 3015 if ((hw->phy.type == e1000_phy_82578) && 3016 (hw->phy.revision >= 1) && 3017 (hw->phy.addr == 2) && 3018 ((MAX_PHY_REG_ADDRESS & reg) == 0) && (data & (1 << 11))) { 3019 u16 data2 = 0x7EFF; 3020 ret_val = e1000_access_phy_debug_regs_hv(hw, 3021 (1 << 6) | 0x3, 3022 &data2, false); 3023 if (ret_val) 3024 goto out; 3025 } 3026 3027 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3028 /* Page is shifted left, PHY expects (page x 32) */ 3029 ret_val = e1000_set_page_igp(hw, 3030 (page << IGP_PAGE_SHIFT)); 3031 3032 hw->phy.addr = phy_addr; 3033 3034 if (ret_val) 3035 goto out; 3036 } 3037 } 3038 3039 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3040 page << IGP_PAGE_SHIFT, reg); 3041 3042 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3043 data); 3044 3045 out: 3046 if (!locked) 3047 hw->phy.ops.release(hw); 3048 3049 return ret_val; 3050 } 3051 3052 /** 3053 * e1000_write_phy_reg_hv - Write HV PHY register 3054 * @hw: pointer to the HW structure 3055 * @offset: register offset to write to 3056 * @data: data to write at register offset 3057 * 3058 * Acquires semaphore then writes the data to PHY register at the offset. 3059 * Release the acquired semaphores before exiting. 3060 **/ 3061 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3062 { 3063 return __e1000_write_phy_reg_hv(hw, offset, data, false, false); 3064 } 3065 3066 /** 3067 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3068 * @hw: pointer to the HW structure 3069 * @offset: register offset to write to 3070 * @data: data to write at register offset 3071 * 3072 * Writes the data to PHY register at the offset. Assumes semaphore 3073 * already acquired. 3074 **/ 3075 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3076 { 3077 return __e1000_write_phy_reg_hv(hw, offset, data, true, false); 3078 } 3079 3080 /** 3081 * e1000_write_phy_reg_page_hv - Write HV PHY register 3082 * @hw: pointer to the HW structure 3083 * @offset: register offset to write to 3084 * @data: data to write at register offset 3085 * 3086 * Writes the data to PHY register at the offset. Assumes semaphore 3087 * already acquired and page already set. 3088 **/ 3089 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3090 { 3091 return __e1000_write_phy_reg_hv(hw, offset, data, true, true); 3092 } 3093 3094 /** 3095 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page 3096 * @page: page to be accessed 3097 **/ 3098 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3099 { 3100 u32 phy_addr = 2; 3101 3102 if (page >= HV_INTC_FC_PAGE_START) 3103 phy_addr = 1; 3104 3105 return phy_addr; 3106 } 3107 3108 /** 3109 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3110 * @hw: pointer to the HW structure 3111 * @offset: register offset to be read or written 3112 * @data: pointer to the data to be read or written 3113 * @read: determines if operation is read or write 3114 * 3115 * Reads the PHY register at offset and stores the retreived information 3116 * in data. Assumes semaphore already acquired. Note that the procedure 3117 * to access these regs uses the address port and data port to read/write. 3118 * These accesses done with PHY address 2 and without using pages. 3119 **/ 3120 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3121 u16 *data, bool read) 3122 { 3123 s32 ret_val; 3124 u32 addr_reg = 0; 3125 u32 data_reg = 0; 3126 3127 /* This takes care of the difference with desktop vs mobile phy */ 3128 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3129 I82578_ADDR_REG : I82577_ADDR_REG; 3130 data_reg = addr_reg + 1; 3131 3132 /* All operations in this function are phy address 2 */ 3133 hw->phy.addr = 2; 3134 3135 /* masking with 0x3F to remove the page from offset */ 3136 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3137 if (ret_val) { 3138 e_dbg("Could not write the Address Offset port register\n"); 3139 goto out; 3140 } 3141 3142 /* Read or write the data value next */ 3143 if (read) 3144 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); 3145 else 3146 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); 3147 3148 if (ret_val) { 3149 e_dbg("Could not access the Data port register\n"); 3150 goto out; 3151 } 3152 3153 out: 3154 return ret_val; 3155 } 3156 3157 /** 3158 * e1000_link_stall_workaround_hv - Si workaround 3159 * @hw: pointer to the HW structure 3160 * 3161 * This function works around a Si bug where the link partner can get 3162 * a link up indication before the PHY does. If small packets are sent 3163 * by the link partner they can be placed in the packet buffer without 3164 * being properly accounted for by the PHY and will stall preventing 3165 * further packets from being received. The workaround is to clear the 3166 * packet buffer after the PHY detects link up. 3167 **/ 3168 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3169 { 3170 s32 ret_val = 0; 3171 u16 data; 3172 3173 if (hw->phy.type != e1000_phy_82578) 3174 goto out; 3175 3176 /* Do not apply workaround if in PHY loopback bit 14 set */ 3177 e1e_rphy(hw, PHY_CONTROL, &data); 3178 if (data & PHY_CONTROL_LB) 3179 goto out; 3180 3181 /* check if link is up and at 1Gbps */ 3182 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); 3183 if (ret_val) 3184 goto out; 3185 3186 data &= BM_CS_STATUS_LINK_UP | 3187 BM_CS_STATUS_RESOLVED | 3188 BM_CS_STATUS_SPEED_MASK; 3189 3190 if (data != (BM_CS_STATUS_LINK_UP | 3191 BM_CS_STATUS_RESOLVED | 3192 BM_CS_STATUS_SPEED_1000)) 3193 goto out; 3194 3195 mdelay(200); 3196 3197 /* flush the packets in the fifo buffer */ 3198 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC | 3199 HV_MUX_DATA_CTRL_FORCE_SPEED); 3200 if (ret_val) 3201 goto out; 3202 3203 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); 3204 3205 out: 3206 return ret_val; 3207 } 3208 3209 /** 3210 * e1000_check_polarity_82577 - Checks the polarity. 3211 * @hw: pointer to the HW structure 3212 * 3213 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3214 * 3215 * Polarity is determined based on the PHY specific status register. 3216 **/ 3217 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3218 { 3219 struct e1000_phy_info *phy = &hw->phy; 3220 s32 ret_val; 3221 u16 data; 3222 3223 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 3224 3225 if (!ret_val) 3226 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3227 ? e1000_rev_polarity_reversed 3228 : e1000_rev_polarity_normal; 3229 3230 return ret_val; 3231 } 3232 3233 /** 3234 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3235 * @hw: pointer to the HW structure 3236 * 3237 * Calls the PHY setup function to force speed and duplex. 3238 **/ 3239 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3240 { 3241 struct e1000_phy_info *phy = &hw->phy; 3242 s32 ret_val; 3243 u16 phy_data; 3244 bool link; 3245 3246 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 3247 if (ret_val) 3248 goto out; 3249 3250 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 3251 3252 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); 3253 if (ret_val) 3254 goto out; 3255 3256 udelay(1); 3257 3258 if (phy->autoneg_wait_to_complete) { 3259 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); 3260 3261 ret_val = e1000e_phy_has_link_generic(hw, 3262 PHY_FORCE_LIMIT, 3263 100000, 3264 &link); 3265 if (ret_val) 3266 goto out; 3267 3268 if (!link) 3269 e_dbg("Link taking longer than expected.\n"); 3270 3271 /* Try once more */ 3272 ret_val = e1000e_phy_has_link_generic(hw, 3273 PHY_FORCE_LIMIT, 3274 100000, 3275 &link); 3276 if (ret_val) 3277 goto out; 3278 } 3279 3280 out: 3281 return ret_val; 3282 } 3283 3284 /** 3285 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3286 * @hw: pointer to the HW structure 3287 * 3288 * Read PHY status to determine if link is up. If link is up, then 3289 * set/determine 10base-T extended distance and polarity correction. Read 3290 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3291 * determine on the cable length, local and remote receiver. 3292 **/ 3293 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3294 { 3295 struct e1000_phy_info *phy = &hw->phy; 3296 s32 ret_val; 3297 u16 data; 3298 bool link; 3299 3300 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 3301 if (ret_val) 3302 goto out; 3303 3304 if (!link) { 3305 e_dbg("Phy info is only valid if link is up\n"); 3306 ret_val = -E1000_ERR_CONFIG; 3307 goto out; 3308 } 3309 3310 phy->polarity_correction = true; 3311 3312 ret_val = e1000_check_polarity_82577(hw); 3313 if (ret_val) 3314 goto out; 3315 3316 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 3317 if (ret_val) 3318 goto out; 3319 3320 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; 3321 3322 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3323 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3324 ret_val = hw->phy.ops.get_cable_length(hw); 3325 if (ret_val) 3326 goto out; 3327 3328 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); 3329 if (ret_val) 3330 goto out; 3331 3332 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3333 ? e1000_1000t_rx_status_ok 3334 : e1000_1000t_rx_status_not_ok; 3335 3336 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3337 ? e1000_1000t_rx_status_ok 3338 : e1000_1000t_rx_status_not_ok; 3339 } else { 3340 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3341 phy->local_rx = e1000_1000t_rx_status_undefined; 3342 phy->remote_rx = e1000_1000t_rx_status_undefined; 3343 } 3344 3345 out: 3346 return ret_val; 3347 } 3348 3349 /** 3350 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3351 * @hw: pointer to the HW structure 3352 * 3353 * Reads the diagnostic status register and verifies result is valid before 3354 * placing it in the phy_cable_length field. 3355 **/ 3356 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3357 { 3358 struct e1000_phy_info *phy = &hw->phy; 3359 s32 ret_val; 3360 u16 phy_data, length; 3361 3362 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3363 if (ret_val) 3364 goto out; 3365 3366 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3367 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3368 3369 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3370 ret_val = -E1000_ERR_PHY; 3371 3372 phy->cable_length = length; 3373 3374 out: 3375 return ret_val; 3376 } 3377