1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include "e1000.h" 30 31 /** 32 * e1000_raise_eec_clk - Raise EEPROM clock 33 * @hw: pointer to the HW structure 34 * @eecd: pointer to the EEPROM 35 * 36 * Enable/Raise the EEPROM clock bit. 37 **/ 38 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 39 { 40 *eecd = *eecd | E1000_EECD_SK; 41 ew32(EECD, *eecd); 42 e1e_flush(); 43 udelay(hw->nvm.delay_usec); 44 } 45 46 /** 47 * e1000_lower_eec_clk - Lower EEPROM clock 48 * @hw: pointer to the HW structure 49 * @eecd: pointer to the EEPROM 50 * 51 * Clear/Lower the EEPROM clock bit. 52 **/ 53 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 54 { 55 *eecd = *eecd & ~E1000_EECD_SK; 56 ew32(EECD, *eecd); 57 e1e_flush(); 58 udelay(hw->nvm.delay_usec); 59 } 60 61 /** 62 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 63 * @hw: pointer to the HW structure 64 * @data: data to send to the EEPROM 65 * @count: number of bits to shift out 66 * 67 * We need to shift 'count' bits out to the EEPROM. So, the value in the 68 * "data" parameter will be shifted out to the EEPROM one bit at a time. 69 * In order to do this, "data" must be broken down into bits. 70 **/ 71 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 72 { 73 struct e1000_nvm_info *nvm = &hw->nvm; 74 u32 eecd = er32(EECD); 75 u32 mask; 76 77 mask = 0x01 << (count - 1); 78 if (nvm->type == e1000_nvm_eeprom_spi) 79 eecd |= E1000_EECD_DO; 80 81 do { 82 eecd &= ~E1000_EECD_DI; 83 84 if (data & mask) 85 eecd |= E1000_EECD_DI; 86 87 ew32(EECD, eecd); 88 e1e_flush(); 89 90 udelay(nvm->delay_usec); 91 92 e1000_raise_eec_clk(hw, &eecd); 93 e1000_lower_eec_clk(hw, &eecd); 94 95 mask >>= 1; 96 } while (mask); 97 98 eecd &= ~E1000_EECD_DI; 99 ew32(EECD, eecd); 100 } 101 102 /** 103 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 104 * @hw: pointer to the HW structure 105 * @count: number of bits to shift in 106 * 107 * In order to read a register from the EEPROM, we need to shift 'count' bits 108 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 109 * the EEPROM (setting the SK bit), and then reading the value of the data out 110 * "DO" bit. During this "shifting in" process the data in "DI" bit should 111 * always be clear. 112 **/ 113 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 114 { 115 u32 eecd; 116 u32 i; 117 u16 data; 118 119 eecd = er32(EECD); 120 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 121 data = 0; 122 123 for (i = 0; i < count; i++) { 124 data <<= 1; 125 e1000_raise_eec_clk(hw, &eecd); 126 127 eecd = er32(EECD); 128 129 eecd &= ~E1000_EECD_DI; 130 if (eecd & E1000_EECD_DO) 131 data |= 1; 132 133 e1000_lower_eec_clk(hw, &eecd); 134 } 135 136 return data; 137 } 138 139 /** 140 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion 141 * @hw: pointer to the HW structure 142 * @ee_reg: EEPROM flag for polling 143 * 144 * Polls the EEPROM status bit for either read or write completion based 145 * upon the value of 'ee_reg'. 146 **/ 147 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 148 { 149 u32 attempts = 100000; 150 u32 i, reg = 0; 151 152 for (i = 0; i < attempts; i++) { 153 if (ee_reg == E1000_NVM_POLL_READ) 154 reg = er32(EERD); 155 else 156 reg = er32(EEWR); 157 158 if (reg & E1000_NVM_RW_REG_DONE) 159 return 0; 160 161 udelay(5); 162 } 163 164 return -E1000_ERR_NVM; 165 } 166 167 /** 168 * e1000e_acquire_nvm - Generic request for access to EEPROM 169 * @hw: pointer to the HW structure 170 * 171 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 172 * Return successful if access grant bit set, else clear the request for 173 * EEPROM access and return -E1000_ERR_NVM (-1). 174 **/ 175 s32 e1000e_acquire_nvm(struct e1000_hw *hw) 176 { 177 u32 eecd = er32(EECD); 178 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 179 180 ew32(EECD, eecd | E1000_EECD_REQ); 181 eecd = er32(EECD); 182 183 while (timeout) { 184 if (eecd & E1000_EECD_GNT) 185 break; 186 udelay(5); 187 eecd = er32(EECD); 188 timeout--; 189 } 190 191 if (!timeout) { 192 eecd &= ~E1000_EECD_REQ; 193 ew32(EECD, eecd); 194 e_dbg("Could not acquire NVM grant\n"); 195 return -E1000_ERR_NVM; 196 } 197 198 return 0; 199 } 200 201 /** 202 * e1000_standby_nvm - Return EEPROM to standby state 203 * @hw: pointer to the HW structure 204 * 205 * Return the EEPROM to a standby state. 206 **/ 207 static void e1000_standby_nvm(struct e1000_hw *hw) 208 { 209 struct e1000_nvm_info *nvm = &hw->nvm; 210 u32 eecd = er32(EECD); 211 212 if (nvm->type == e1000_nvm_eeprom_spi) { 213 /* Toggle CS to flush commands */ 214 eecd |= E1000_EECD_CS; 215 ew32(EECD, eecd); 216 e1e_flush(); 217 udelay(nvm->delay_usec); 218 eecd &= ~E1000_EECD_CS; 219 ew32(EECD, eecd); 220 e1e_flush(); 221 udelay(nvm->delay_usec); 222 } 223 } 224 225 /** 226 * e1000_stop_nvm - Terminate EEPROM command 227 * @hw: pointer to the HW structure 228 * 229 * Terminates the current command by inverting the EEPROM's chip select pin. 230 **/ 231 static void e1000_stop_nvm(struct e1000_hw *hw) 232 { 233 u32 eecd; 234 235 eecd = er32(EECD); 236 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 237 /* Pull CS high */ 238 eecd |= E1000_EECD_CS; 239 e1000_lower_eec_clk(hw, &eecd); 240 } 241 } 242 243 /** 244 * e1000e_release_nvm - Release exclusive access to EEPROM 245 * @hw: pointer to the HW structure 246 * 247 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 248 **/ 249 void e1000e_release_nvm(struct e1000_hw *hw) 250 { 251 u32 eecd; 252 253 e1000_stop_nvm(hw); 254 255 eecd = er32(EECD); 256 eecd &= ~E1000_EECD_REQ; 257 ew32(EECD, eecd); 258 } 259 260 /** 261 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 262 * @hw: pointer to the HW structure 263 * 264 * Setups the EEPROM for reading and writing. 265 **/ 266 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 267 { 268 struct e1000_nvm_info *nvm = &hw->nvm; 269 u32 eecd = er32(EECD); 270 u8 spi_stat_reg; 271 272 if (nvm->type == e1000_nvm_eeprom_spi) { 273 u16 timeout = NVM_MAX_RETRY_SPI; 274 275 /* Clear SK and CS */ 276 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 277 ew32(EECD, eecd); 278 e1e_flush(); 279 udelay(1); 280 281 /* Read "Status Register" repeatedly until the LSB is cleared. 282 * The EEPROM will signal that the command has been completed 283 * by clearing bit 0 of the internal status register. If it's 284 * not cleared within 'timeout', then error out. 285 */ 286 while (timeout) { 287 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 288 hw->nvm.opcode_bits); 289 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 290 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 291 break; 292 293 udelay(5); 294 e1000_standby_nvm(hw); 295 timeout--; 296 } 297 298 if (!timeout) { 299 e_dbg("SPI NVM Status error\n"); 300 return -E1000_ERR_NVM; 301 } 302 } 303 304 return 0; 305 } 306 307 /** 308 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register 309 * @hw: pointer to the HW structure 310 * @offset: offset of word in the EEPROM to read 311 * @words: number of words to read 312 * @data: word read from the EEPROM 313 * 314 * Reads a 16 bit word from the EEPROM using the EERD register. 315 **/ 316 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 317 { 318 struct e1000_nvm_info *nvm = &hw->nvm; 319 u32 i, eerd = 0; 320 s32 ret_val = 0; 321 322 /* A check for invalid values: offset too large, too many words, 323 * too many words for the offset, and not enough words. 324 */ 325 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 326 (words == 0)) { 327 e_dbg("nvm parameter(s) out of bounds\n"); 328 return -E1000_ERR_NVM; 329 } 330 331 for (i = 0; i < words; i++) { 332 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) + 333 E1000_NVM_RW_REG_START; 334 335 ew32(EERD, eerd); 336 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 337 if (ret_val) 338 break; 339 340 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA); 341 } 342 343 return ret_val; 344 } 345 346 /** 347 * e1000e_write_nvm_spi - Write to EEPROM using SPI 348 * @hw: pointer to the HW structure 349 * @offset: offset within the EEPROM to be written to 350 * @words: number of words to write 351 * @data: 16 bit word(s) to be written to the EEPROM 352 * 353 * Writes data to EEPROM at offset using SPI interface. 354 * 355 * If e1000e_update_nvm_checksum is not called after this function , the 356 * EEPROM will most likely contain an invalid checksum. 357 **/ 358 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 359 { 360 struct e1000_nvm_info *nvm = &hw->nvm; 361 s32 ret_val = -E1000_ERR_NVM; 362 u16 widx = 0; 363 364 /* A check for invalid values: offset too large, too many words, 365 * and not enough words. 366 */ 367 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 368 (words == 0)) { 369 e_dbg("nvm parameter(s) out of bounds\n"); 370 return -E1000_ERR_NVM; 371 } 372 373 while (widx < words) { 374 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 375 376 ret_val = nvm->ops.acquire(hw); 377 if (ret_val) 378 return ret_val; 379 380 ret_val = e1000_ready_nvm_eeprom(hw); 381 if (ret_val) { 382 nvm->ops.release(hw); 383 return ret_val; 384 } 385 386 e1000_standby_nvm(hw); 387 388 /* Send the WRITE ENABLE command (8 bit opcode) */ 389 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 390 nvm->opcode_bits); 391 392 e1000_standby_nvm(hw); 393 394 /* Some SPI eeproms use the 8th address bit embedded in the 395 * opcode 396 */ 397 if ((nvm->address_bits == 8) && (offset >= 128)) 398 write_opcode |= NVM_A8_OPCODE_SPI; 399 400 /* Send the Write command (8-bit opcode + addr) */ 401 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 402 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 403 nvm->address_bits); 404 405 /* Loop to allow for up to whole page write of eeprom */ 406 while (widx < words) { 407 u16 word_out = data[widx]; 408 word_out = (word_out >> 8) | (word_out << 8); 409 e1000_shift_out_eec_bits(hw, word_out, 16); 410 widx++; 411 412 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 413 e1000_standby_nvm(hw); 414 break; 415 } 416 } 417 usleep_range(10000, 20000); 418 nvm->ops.release(hw); 419 } 420 421 return ret_val; 422 } 423 424 /** 425 * e1000_read_pba_string_generic - Read device part number 426 * @hw: pointer to the HW structure 427 * @pba_num: pointer to device part number 428 * @pba_num_size: size of part number buffer 429 * 430 * Reads the product board assembly (PBA) number from the EEPROM and stores 431 * the value in pba_num. 432 **/ 433 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 434 u32 pba_num_size) 435 { 436 s32 ret_val; 437 u16 nvm_data; 438 u16 pba_ptr; 439 u16 offset; 440 u16 length; 441 442 if (pba_num == NULL) { 443 e_dbg("PBA string buffer was null\n"); 444 return -E1000_ERR_INVALID_ARGUMENT; 445 } 446 447 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 448 if (ret_val) { 449 e_dbg("NVM Read Error\n"); 450 return ret_val; 451 } 452 453 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 454 if (ret_val) { 455 e_dbg("NVM Read Error\n"); 456 return ret_val; 457 } 458 459 /* if nvm_data is not ptr guard the PBA must be in legacy format which 460 * means pba_ptr is actually our second data word for the PBA number 461 * and we can decode it into an ascii string 462 */ 463 if (nvm_data != NVM_PBA_PTR_GUARD) { 464 e_dbg("NVM PBA number is not stored as string\n"); 465 466 /* make sure callers buffer is big enough to store the PBA */ 467 if (pba_num_size < E1000_PBANUM_LENGTH) { 468 e_dbg("PBA string buffer too small\n"); 469 return E1000_ERR_NO_SPACE; 470 } 471 472 /* extract hex string from data and pba_ptr */ 473 pba_num[0] = (nvm_data >> 12) & 0xF; 474 pba_num[1] = (nvm_data >> 8) & 0xF; 475 pba_num[2] = (nvm_data >> 4) & 0xF; 476 pba_num[3] = nvm_data & 0xF; 477 pba_num[4] = (pba_ptr >> 12) & 0xF; 478 pba_num[5] = (pba_ptr >> 8) & 0xF; 479 pba_num[6] = '-'; 480 pba_num[7] = 0; 481 pba_num[8] = (pba_ptr >> 4) & 0xF; 482 pba_num[9] = pba_ptr & 0xF; 483 484 /* put a null character on the end of our string */ 485 pba_num[10] = '\0'; 486 487 /* switch all the data but the '-' to hex char */ 488 for (offset = 0; offset < 10; offset++) { 489 if (pba_num[offset] < 0xA) 490 pba_num[offset] += '0'; 491 else if (pba_num[offset] < 0x10) 492 pba_num[offset] += 'A' - 0xA; 493 } 494 495 return 0; 496 } 497 498 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length); 499 if (ret_val) { 500 e_dbg("NVM Read Error\n"); 501 return ret_val; 502 } 503 504 if (length == 0xFFFF || length == 0) { 505 e_dbg("NVM PBA number section invalid length\n"); 506 return -E1000_ERR_NVM_PBA_SECTION; 507 } 508 /* check if pba_num buffer is big enough */ 509 if (pba_num_size < (((u32)length * 2) - 1)) { 510 e_dbg("PBA string buffer too small\n"); 511 return -E1000_ERR_NO_SPACE; 512 } 513 514 /* trim pba length from start of string */ 515 pba_ptr++; 516 length--; 517 518 for (offset = 0; offset < length; offset++) { 519 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data); 520 if (ret_val) { 521 e_dbg("NVM Read Error\n"); 522 return ret_val; 523 } 524 pba_num[offset * 2] = (u8)(nvm_data >> 8); 525 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 526 } 527 pba_num[offset * 2] = '\0'; 528 529 return 0; 530 } 531 532 /** 533 * e1000_read_mac_addr_generic - Read device MAC address 534 * @hw: pointer to the HW structure 535 * 536 * Reads the device MAC address from the EEPROM and stores the value. 537 * Since devices with two ports use the same EEPROM, we increment the 538 * last bit in the MAC address for the second port. 539 **/ 540 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 541 { 542 u32 rar_high; 543 u32 rar_low; 544 u16 i; 545 546 rar_high = er32(RAH(0)); 547 rar_low = er32(RAL(0)); 548 549 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 550 hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8)); 551 552 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 553 hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8)); 554 555 for (i = 0; i < ETH_ALEN; i++) 556 hw->mac.addr[i] = hw->mac.perm_addr[i]; 557 558 return 0; 559 } 560 561 /** 562 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum 563 * @hw: pointer to the HW structure 564 * 565 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 566 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 567 **/ 568 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw) 569 { 570 s32 ret_val; 571 u16 checksum = 0; 572 u16 i, nvm_data; 573 574 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 575 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); 576 if (ret_val) { 577 e_dbg("NVM Read Error\n"); 578 return ret_val; 579 } 580 checksum += nvm_data; 581 } 582 583 if (checksum != (u16)NVM_SUM) { 584 e_dbg("NVM Checksum Invalid\n"); 585 return -E1000_ERR_NVM; 586 } 587 588 return 0; 589 } 590 591 /** 592 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum 593 * @hw: pointer to the HW structure 594 * 595 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 596 * up to the checksum. Then calculates the EEPROM checksum and writes the 597 * value to the EEPROM. 598 **/ 599 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw) 600 { 601 s32 ret_val; 602 u16 checksum = 0; 603 u16 i, nvm_data; 604 605 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 606 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); 607 if (ret_val) { 608 e_dbg("NVM Read Error while updating checksum.\n"); 609 return ret_val; 610 } 611 checksum += nvm_data; 612 } 613 checksum = (u16)NVM_SUM - checksum; 614 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); 615 if (ret_val) 616 e_dbg("NVM Write Error while updating checksum.\n"); 617 618 return ret_val; 619 } 620 621 /** 622 * e1000e_reload_nvm_generic - Reloads EEPROM 623 * @hw: pointer to the HW structure 624 * 625 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 626 * extended control register. 627 **/ 628 void e1000e_reload_nvm_generic(struct e1000_hw *hw) 629 { 630 u32 ctrl_ext; 631 632 usleep_range(10, 20); 633 ctrl_ext = er32(CTRL_EXT); 634 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 635 ew32(CTRL_EXT, ctrl_ext); 636 e1e_flush(); 637 } 638