1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/aer.h> 27 #include <linux/prefetch.h> 28 #include <linux/suspend.h> 29 30 #include "e1000.h" 31 32 char e1000e_driver_name[] = "e1000e"; 33 34 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 35 static int debug = -1; 36 module_param(debug, int, 0); 37 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 38 39 static const struct e1000_info *e1000_info_tbl[] = { 40 [board_82571] = &e1000_82571_info, 41 [board_82572] = &e1000_82572_info, 42 [board_82573] = &e1000_82573_info, 43 [board_82574] = &e1000_82574_info, 44 [board_82583] = &e1000_82583_info, 45 [board_80003es2lan] = &e1000_es2_info, 46 [board_ich8lan] = &e1000_ich8_info, 47 [board_ich9lan] = &e1000_ich9_info, 48 [board_ich10lan] = &e1000_ich10_info, 49 [board_pchlan] = &e1000_pch_info, 50 [board_pch2lan] = &e1000_pch2_info, 51 [board_pch_lpt] = &e1000_pch_lpt_info, 52 [board_pch_spt] = &e1000_pch_spt_info, 53 [board_pch_cnp] = &e1000_pch_cnp_info, 54 [board_pch_tgp] = &e1000_pch_tgp_info, 55 }; 56 57 struct e1000_reg_info { 58 u32 ofs; 59 char *name; 60 }; 61 62 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 63 /* General Registers */ 64 {E1000_CTRL, "CTRL"}, 65 {E1000_STATUS, "STATUS"}, 66 {E1000_CTRL_EXT, "CTRL_EXT"}, 67 68 /* Interrupt Registers */ 69 {E1000_ICR, "ICR"}, 70 71 /* Rx Registers */ 72 {E1000_RCTL, "RCTL"}, 73 {E1000_RDLEN(0), "RDLEN"}, 74 {E1000_RDH(0), "RDH"}, 75 {E1000_RDT(0), "RDT"}, 76 {E1000_RDTR, "RDTR"}, 77 {E1000_RXDCTL(0), "RXDCTL"}, 78 {E1000_ERT, "ERT"}, 79 {E1000_RDBAL(0), "RDBAL"}, 80 {E1000_RDBAH(0), "RDBAH"}, 81 {E1000_RDFH, "RDFH"}, 82 {E1000_RDFT, "RDFT"}, 83 {E1000_RDFHS, "RDFHS"}, 84 {E1000_RDFTS, "RDFTS"}, 85 {E1000_RDFPC, "RDFPC"}, 86 87 /* Tx Registers */ 88 {E1000_TCTL, "TCTL"}, 89 {E1000_TDBAL(0), "TDBAL"}, 90 {E1000_TDBAH(0), "TDBAH"}, 91 {E1000_TDLEN(0), "TDLEN"}, 92 {E1000_TDH(0), "TDH"}, 93 {E1000_TDT(0), "TDT"}, 94 {E1000_TIDV, "TIDV"}, 95 {E1000_TXDCTL(0), "TXDCTL"}, 96 {E1000_TADV, "TADV"}, 97 {E1000_TARC(0), "TARC"}, 98 {E1000_TDFH, "TDFH"}, 99 {E1000_TDFT, "TDFT"}, 100 {E1000_TDFHS, "TDFHS"}, 101 {E1000_TDFTS, "TDFTS"}, 102 {E1000_TDFPC, "TDFPC"}, 103 104 /* List Terminator */ 105 {0, NULL} 106 }; 107 108 /** 109 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 110 * @hw: pointer to the HW structure 111 * 112 * When updating the MAC CSR registers, the Manageability Engine (ME) could 113 * be accessing the registers at the same time. Normally, this is handled in 114 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 115 * accesses later than it should which could result in the register to have 116 * an incorrect value. Workaround this by checking the FWSM register which 117 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 118 * and try again a number of times. 119 **/ 120 static void __ew32_prepare(struct e1000_hw *hw) 121 { 122 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 123 124 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 125 udelay(50); 126 } 127 128 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 129 { 130 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 131 __ew32_prepare(hw); 132 133 writel(val, hw->hw_addr + reg); 134 } 135 136 /** 137 * e1000_regdump - register printout routine 138 * @hw: pointer to the HW structure 139 * @reginfo: pointer to the register info table 140 **/ 141 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 142 { 143 int n = 0; 144 char rname[16]; 145 u32 regs[8]; 146 147 switch (reginfo->ofs) { 148 case E1000_RXDCTL(0): 149 for (n = 0; n < 2; n++) 150 regs[n] = __er32(hw, E1000_RXDCTL(n)); 151 break; 152 case E1000_TXDCTL(0): 153 for (n = 0; n < 2; n++) 154 regs[n] = __er32(hw, E1000_TXDCTL(n)); 155 break; 156 case E1000_TARC(0): 157 for (n = 0; n < 2; n++) 158 regs[n] = __er32(hw, E1000_TARC(n)); 159 break; 160 default: 161 pr_info("%-15s %08x\n", 162 reginfo->name, __er32(hw, reginfo->ofs)); 163 return; 164 } 165 166 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 167 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 168 } 169 170 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 171 struct e1000_buffer *bi) 172 { 173 int i; 174 struct e1000_ps_page *ps_page; 175 176 for (i = 0; i < adapter->rx_ps_pages; i++) { 177 ps_page = &bi->ps_pages[i]; 178 179 if (ps_page->page) { 180 pr_info("packet dump for ps_page %d:\n", i); 181 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 182 16, 1, page_address(ps_page->page), 183 PAGE_SIZE, true); 184 } 185 } 186 } 187 188 /** 189 * e1000e_dump - Print registers, Tx-ring and Rx-ring 190 * @adapter: board private structure 191 **/ 192 static void e1000e_dump(struct e1000_adapter *adapter) 193 { 194 struct net_device *netdev = adapter->netdev; 195 struct e1000_hw *hw = &adapter->hw; 196 struct e1000_reg_info *reginfo; 197 struct e1000_ring *tx_ring = adapter->tx_ring; 198 struct e1000_tx_desc *tx_desc; 199 struct my_u0 { 200 __le64 a; 201 __le64 b; 202 } *u0; 203 struct e1000_buffer *buffer_info; 204 struct e1000_ring *rx_ring = adapter->rx_ring; 205 union e1000_rx_desc_packet_split *rx_desc_ps; 206 union e1000_rx_desc_extended *rx_desc; 207 struct my_u1 { 208 __le64 a; 209 __le64 b; 210 __le64 c; 211 __le64 d; 212 } *u1; 213 u32 staterr; 214 int i = 0; 215 216 if (!netif_msg_hw(adapter)) 217 return; 218 219 /* Print netdevice Info */ 220 if (netdev) { 221 dev_info(&adapter->pdev->dev, "Net device Info\n"); 222 pr_info("Device Name state trans_start\n"); 223 pr_info("%-15s %016lX %016lX\n", netdev->name, 224 netdev->state, dev_trans_start(netdev)); 225 } 226 227 /* Print Registers */ 228 dev_info(&adapter->pdev->dev, "Register Dump\n"); 229 pr_info(" Register Name Value\n"); 230 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 231 reginfo->name; reginfo++) { 232 e1000_regdump(hw, reginfo); 233 } 234 235 /* Print Tx Ring Summary */ 236 if (!netdev || !netif_running(netdev)) 237 return; 238 239 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 240 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 241 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 242 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 243 0, tx_ring->next_to_use, tx_ring->next_to_clean, 244 (unsigned long long)buffer_info->dma, 245 buffer_info->length, 246 buffer_info->next_to_watch, 247 (unsigned long long)buffer_info->time_stamp); 248 249 /* Print Tx Ring */ 250 if (!netif_msg_tx_done(adapter)) 251 goto rx_ring_summary; 252 253 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 254 255 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 256 * 257 * Legacy Transmit Descriptor 258 * +--------------------------------------------------------------+ 259 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 260 * +--------------------------------------------------------------+ 261 * 8 | Special | CSS | Status | CMD | CSO | Length | 262 * +--------------------------------------------------------------+ 263 * 63 48 47 36 35 32 31 24 23 16 15 0 264 * 265 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 266 * 63 48 47 40 39 32 31 16 15 8 7 0 267 * +----------------------------------------------------------------+ 268 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 269 * +----------------------------------------------------------------+ 270 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 271 * +----------------------------------------------------------------+ 272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 273 * 274 * Extended Data Descriptor (DTYP=0x1) 275 * +----------------------------------------------------------------+ 276 * 0 | Buffer Address [63:0] | 277 * +----------------------------------------------------------------+ 278 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 279 * +----------------------------------------------------------------+ 280 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 281 */ 282 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 283 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 284 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 285 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 286 const char *next_desc; 287 tx_desc = E1000_TX_DESC(*tx_ring, i); 288 buffer_info = &tx_ring->buffer_info[i]; 289 u0 = (struct my_u0 *)tx_desc; 290 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 291 next_desc = " NTC/U"; 292 else if (i == tx_ring->next_to_use) 293 next_desc = " NTU"; 294 else if (i == tx_ring->next_to_clean) 295 next_desc = " NTC"; 296 else 297 next_desc = ""; 298 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 299 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 300 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 301 i, 302 (unsigned long long)le64_to_cpu(u0->a), 303 (unsigned long long)le64_to_cpu(u0->b), 304 (unsigned long long)buffer_info->dma, 305 buffer_info->length, buffer_info->next_to_watch, 306 (unsigned long long)buffer_info->time_stamp, 307 buffer_info->skb, next_desc); 308 309 if (netif_msg_pktdata(adapter) && buffer_info->skb) 310 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 311 16, 1, buffer_info->skb->data, 312 buffer_info->skb->len, true); 313 } 314 315 /* Print Rx Ring Summary */ 316 rx_ring_summary: 317 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 318 pr_info("Queue [NTU] [NTC]\n"); 319 pr_info(" %5d %5X %5X\n", 320 0, rx_ring->next_to_use, rx_ring->next_to_clean); 321 322 /* Print Rx Ring */ 323 if (!netif_msg_rx_status(adapter)) 324 return; 325 326 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 327 switch (adapter->rx_ps_pages) { 328 case 1: 329 case 2: 330 case 3: 331 /* [Extended] Packet Split Receive Descriptor Format 332 * 333 * +-----------------------------------------------------+ 334 * 0 | Buffer Address 0 [63:0] | 335 * +-----------------------------------------------------+ 336 * 8 | Buffer Address 1 [63:0] | 337 * +-----------------------------------------------------+ 338 * 16 | Buffer Address 2 [63:0] | 339 * +-----------------------------------------------------+ 340 * 24 | Buffer Address 3 [63:0] | 341 * +-----------------------------------------------------+ 342 */ 343 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 344 /* [Extended] Receive Descriptor (Write-Back) Format 345 * 346 * 63 48 47 32 31 13 12 8 7 4 3 0 347 * +------------------------------------------------------+ 348 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 349 * | Checksum | Ident | | Queue | | Type | 350 * +------------------------------------------------------+ 351 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 352 * +------------------------------------------------------+ 353 * 63 48 47 32 31 20 19 0 354 */ 355 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 356 for (i = 0; i < rx_ring->count; i++) { 357 const char *next_desc; 358 buffer_info = &rx_ring->buffer_info[i]; 359 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 360 u1 = (struct my_u1 *)rx_desc_ps; 361 staterr = 362 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 363 364 if (i == rx_ring->next_to_use) 365 next_desc = " NTU"; 366 else if (i == rx_ring->next_to_clean) 367 next_desc = " NTC"; 368 else 369 next_desc = ""; 370 371 if (staterr & E1000_RXD_STAT_DD) { 372 /* Descriptor Done */ 373 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 374 "RWB", i, 375 (unsigned long long)le64_to_cpu(u1->a), 376 (unsigned long long)le64_to_cpu(u1->b), 377 (unsigned long long)le64_to_cpu(u1->c), 378 (unsigned long long)le64_to_cpu(u1->d), 379 buffer_info->skb, next_desc); 380 } else { 381 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 382 "R ", i, 383 (unsigned long long)le64_to_cpu(u1->a), 384 (unsigned long long)le64_to_cpu(u1->b), 385 (unsigned long long)le64_to_cpu(u1->c), 386 (unsigned long long)le64_to_cpu(u1->d), 387 (unsigned long long)buffer_info->dma, 388 buffer_info->skb, next_desc); 389 390 if (netif_msg_pktdata(adapter)) 391 e1000e_dump_ps_pages(adapter, 392 buffer_info); 393 } 394 } 395 break; 396 default: 397 case 0: 398 /* Extended Receive Descriptor (Read) Format 399 * 400 * +-----------------------------------------------------+ 401 * 0 | Buffer Address [63:0] | 402 * +-----------------------------------------------------+ 403 * 8 | Reserved | 404 * +-----------------------------------------------------+ 405 */ 406 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 407 /* Extended Receive Descriptor (Write-Back) Format 408 * 409 * 63 48 47 32 31 24 23 4 3 0 410 * +------------------------------------------------------+ 411 * | RSS Hash | | | | 412 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 413 * | Packet | IP | | | Type | 414 * | Checksum | Ident | | | | 415 * +------------------------------------------------------+ 416 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 417 * +------------------------------------------------------+ 418 * 63 48 47 32 31 20 19 0 419 */ 420 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 421 422 for (i = 0; i < rx_ring->count; i++) { 423 const char *next_desc; 424 425 buffer_info = &rx_ring->buffer_info[i]; 426 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 427 u1 = (struct my_u1 *)rx_desc; 428 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 429 430 if (i == rx_ring->next_to_use) 431 next_desc = " NTU"; 432 else if (i == rx_ring->next_to_clean) 433 next_desc = " NTC"; 434 else 435 next_desc = ""; 436 437 if (staterr & E1000_RXD_STAT_DD) { 438 /* Descriptor Done */ 439 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 440 "RWB", i, 441 (unsigned long long)le64_to_cpu(u1->a), 442 (unsigned long long)le64_to_cpu(u1->b), 443 buffer_info->skb, next_desc); 444 } else { 445 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 446 "R ", i, 447 (unsigned long long)le64_to_cpu(u1->a), 448 (unsigned long long)le64_to_cpu(u1->b), 449 (unsigned long long)buffer_info->dma, 450 buffer_info->skb, next_desc); 451 452 if (netif_msg_pktdata(adapter) && 453 buffer_info->skb) 454 print_hex_dump(KERN_INFO, "", 455 DUMP_PREFIX_ADDRESS, 16, 456 1, 457 buffer_info->skb->data, 458 adapter->rx_buffer_len, 459 true); 460 } 461 } 462 } 463 } 464 465 /** 466 * e1000_desc_unused - calculate if we have unused descriptors 467 * @ring: pointer to ring struct to perform calculation on 468 **/ 469 static int e1000_desc_unused(struct e1000_ring *ring) 470 { 471 if (ring->next_to_clean > ring->next_to_use) 472 return ring->next_to_clean - ring->next_to_use - 1; 473 474 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 475 } 476 477 /** 478 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 479 * @adapter: board private structure 480 * @hwtstamps: time stamp structure to update 481 * @systim: unsigned 64bit system time value. 482 * 483 * Convert the system time value stored in the RX/TXSTMP registers into a 484 * hwtstamp which can be used by the upper level time stamping functions. 485 * 486 * The 'systim_lock' spinlock is used to protect the consistency of the 487 * system time value. This is needed because reading the 64 bit time 488 * value involves reading two 32 bit registers. The first read latches the 489 * value. 490 **/ 491 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 492 struct skb_shared_hwtstamps *hwtstamps, 493 u64 systim) 494 { 495 u64 ns; 496 unsigned long flags; 497 498 spin_lock_irqsave(&adapter->systim_lock, flags); 499 ns = timecounter_cyc2time(&adapter->tc, systim); 500 spin_unlock_irqrestore(&adapter->systim_lock, flags); 501 502 memset(hwtstamps, 0, sizeof(*hwtstamps)); 503 hwtstamps->hwtstamp = ns_to_ktime(ns); 504 } 505 506 /** 507 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 508 * @adapter: board private structure 509 * @status: descriptor extended error and status field 510 * @skb: particular skb to include time stamp 511 * 512 * If the time stamp is valid, convert it into the timecounter ns value 513 * and store that result into the shhwtstamps structure which is passed 514 * up the network stack. 515 **/ 516 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 517 struct sk_buff *skb) 518 { 519 struct e1000_hw *hw = &adapter->hw; 520 u64 rxstmp; 521 522 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 523 !(status & E1000_RXDEXT_STATERR_TST) || 524 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 525 return; 526 527 /* The Rx time stamp registers contain the time stamp. No other 528 * received packet will be time stamped until the Rx time stamp 529 * registers are read. Because only one packet can be time stamped 530 * at a time, the register values must belong to this packet and 531 * therefore none of the other additional attributes need to be 532 * compared. 533 */ 534 rxstmp = (u64)er32(RXSTMPL); 535 rxstmp |= (u64)er32(RXSTMPH) << 32; 536 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 537 538 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 539 } 540 541 /** 542 * e1000_receive_skb - helper function to handle Rx indications 543 * @adapter: board private structure 544 * @netdev: pointer to netdev struct 545 * @staterr: descriptor extended error and status field as written by hardware 546 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 547 * @skb: pointer to sk_buff to be indicated to stack 548 **/ 549 static void e1000_receive_skb(struct e1000_adapter *adapter, 550 struct net_device *netdev, struct sk_buff *skb, 551 u32 staterr, __le16 vlan) 552 { 553 u16 tag = le16_to_cpu(vlan); 554 555 e1000e_rx_hwtstamp(adapter, staterr, skb); 556 557 skb->protocol = eth_type_trans(skb, netdev); 558 559 if (staterr & E1000_RXD_STAT_VP) 560 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 561 562 napi_gro_receive(&adapter->napi, skb); 563 } 564 565 /** 566 * e1000_rx_checksum - Receive Checksum Offload 567 * @adapter: board private structure 568 * @status_err: receive descriptor status and error fields 569 * @skb: socket buffer with received data 570 **/ 571 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 572 struct sk_buff *skb) 573 { 574 u16 status = (u16)status_err; 575 u8 errors = (u8)(status_err >> 24); 576 577 skb_checksum_none_assert(skb); 578 579 /* Rx checksum disabled */ 580 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 581 return; 582 583 /* Ignore Checksum bit is set */ 584 if (status & E1000_RXD_STAT_IXSM) 585 return; 586 587 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 588 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 589 /* let the stack verify checksum errors */ 590 adapter->hw_csum_err++; 591 return; 592 } 593 594 /* TCP/UDP Checksum has not been calculated */ 595 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 596 return; 597 598 /* It must be a TCP or UDP packet with a valid checksum */ 599 skb->ip_summed = CHECKSUM_UNNECESSARY; 600 adapter->hw_csum_good++; 601 } 602 603 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 604 { 605 struct e1000_adapter *adapter = rx_ring->adapter; 606 struct e1000_hw *hw = &adapter->hw; 607 608 __ew32_prepare(hw); 609 writel(i, rx_ring->tail); 610 611 if (unlikely(i != readl(rx_ring->tail))) { 612 u32 rctl = er32(RCTL); 613 614 ew32(RCTL, rctl & ~E1000_RCTL_EN); 615 e_err("ME firmware caused invalid RDT - resetting\n"); 616 schedule_work(&adapter->reset_task); 617 } 618 } 619 620 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 621 { 622 struct e1000_adapter *adapter = tx_ring->adapter; 623 struct e1000_hw *hw = &adapter->hw; 624 625 __ew32_prepare(hw); 626 writel(i, tx_ring->tail); 627 628 if (unlikely(i != readl(tx_ring->tail))) { 629 u32 tctl = er32(TCTL); 630 631 ew32(TCTL, tctl & ~E1000_TCTL_EN); 632 e_err("ME firmware caused invalid TDT - resetting\n"); 633 schedule_work(&adapter->reset_task); 634 } 635 } 636 637 /** 638 * e1000_alloc_rx_buffers - Replace used receive buffers 639 * @rx_ring: Rx descriptor ring 640 * @cleaned_count: number to reallocate 641 * @gfp: flags for allocation 642 **/ 643 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 644 int cleaned_count, gfp_t gfp) 645 { 646 struct e1000_adapter *adapter = rx_ring->adapter; 647 struct net_device *netdev = adapter->netdev; 648 struct pci_dev *pdev = adapter->pdev; 649 union e1000_rx_desc_extended *rx_desc; 650 struct e1000_buffer *buffer_info; 651 struct sk_buff *skb; 652 unsigned int i; 653 unsigned int bufsz = adapter->rx_buffer_len; 654 655 i = rx_ring->next_to_use; 656 buffer_info = &rx_ring->buffer_info[i]; 657 658 while (cleaned_count--) { 659 skb = buffer_info->skb; 660 if (skb) { 661 skb_trim(skb, 0); 662 goto map_skb; 663 } 664 665 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 666 if (!skb) { 667 /* Better luck next round */ 668 adapter->alloc_rx_buff_failed++; 669 break; 670 } 671 672 buffer_info->skb = skb; 673 map_skb: 674 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 675 adapter->rx_buffer_len, 676 DMA_FROM_DEVICE); 677 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 678 dev_err(&pdev->dev, "Rx DMA map failed\n"); 679 adapter->rx_dma_failed++; 680 break; 681 } 682 683 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 684 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 685 686 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 687 /* Force memory writes to complete before letting h/w 688 * know there are new descriptors to fetch. (Only 689 * applicable for weak-ordered memory model archs, 690 * such as IA-64). 691 */ 692 wmb(); 693 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 694 e1000e_update_rdt_wa(rx_ring, i); 695 else 696 writel(i, rx_ring->tail); 697 } 698 i++; 699 if (i == rx_ring->count) 700 i = 0; 701 buffer_info = &rx_ring->buffer_info[i]; 702 } 703 704 rx_ring->next_to_use = i; 705 } 706 707 /** 708 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 709 * @rx_ring: Rx descriptor ring 710 * @cleaned_count: number to reallocate 711 * @gfp: flags for allocation 712 **/ 713 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 714 int cleaned_count, gfp_t gfp) 715 { 716 struct e1000_adapter *adapter = rx_ring->adapter; 717 struct net_device *netdev = adapter->netdev; 718 struct pci_dev *pdev = adapter->pdev; 719 union e1000_rx_desc_packet_split *rx_desc; 720 struct e1000_buffer *buffer_info; 721 struct e1000_ps_page *ps_page; 722 struct sk_buff *skb; 723 unsigned int i, j; 724 725 i = rx_ring->next_to_use; 726 buffer_info = &rx_ring->buffer_info[i]; 727 728 while (cleaned_count--) { 729 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 730 731 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 732 ps_page = &buffer_info->ps_pages[j]; 733 if (j >= adapter->rx_ps_pages) { 734 /* all unused desc entries get hw null ptr */ 735 rx_desc->read.buffer_addr[j + 1] = 736 ~cpu_to_le64(0); 737 continue; 738 } 739 if (!ps_page->page) { 740 ps_page->page = alloc_page(gfp); 741 if (!ps_page->page) { 742 adapter->alloc_rx_buff_failed++; 743 goto no_buffers; 744 } 745 ps_page->dma = dma_map_page(&pdev->dev, 746 ps_page->page, 747 0, PAGE_SIZE, 748 DMA_FROM_DEVICE); 749 if (dma_mapping_error(&pdev->dev, 750 ps_page->dma)) { 751 dev_err(&adapter->pdev->dev, 752 "Rx DMA page map failed\n"); 753 adapter->rx_dma_failed++; 754 goto no_buffers; 755 } 756 } 757 /* Refresh the desc even if buffer_addrs 758 * didn't change because each write-back 759 * erases this info. 760 */ 761 rx_desc->read.buffer_addr[j + 1] = 762 cpu_to_le64(ps_page->dma); 763 } 764 765 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 766 gfp); 767 768 if (!skb) { 769 adapter->alloc_rx_buff_failed++; 770 break; 771 } 772 773 buffer_info->skb = skb; 774 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 775 adapter->rx_ps_bsize0, 776 DMA_FROM_DEVICE); 777 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 778 dev_err(&pdev->dev, "Rx DMA map failed\n"); 779 adapter->rx_dma_failed++; 780 /* cleanup skb */ 781 dev_kfree_skb_any(skb); 782 buffer_info->skb = NULL; 783 break; 784 } 785 786 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 787 788 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 789 /* Force memory writes to complete before letting h/w 790 * know there are new descriptors to fetch. (Only 791 * applicable for weak-ordered memory model archs, 792 * such as IA-64). 793 */ 794 wmb(); 795 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 796 e1000e_update_rdt_wa(rx_ring, i << 1); 797 else 798 writel(i << 1, rx_ring->tail); 799 } 800 801 i++; 802 if (i == rx_ring->count) 803 i = 0; 804 buffer_info = &rx_ring->buffer_info[i]; 805 } 806 807 no_buffers: 808 rx_ring->next_to_use = i; 809 } 810 811 /** 812 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 813 * @rx_ring: Rx descriptor ring 814 * @cleaned_count: number of buffers to allocate this pass 815 * @gfp: flags for allocation 816 **/ 817 818 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 819 int cleaned_count, gfp_t gfp) 820 { 821 struct e1000_adapter *adapter = rx_ring->adapter; 822 struct net_device *netdev = adapter->netdev; 823 struct pci_dev *pdev = adapter->pdev; 824 union e1000_rx_desc_extended *rx_desc; 825 struct e1000_buffer *buffer_info; 826 struct sk_buff *skb; 827 unsigned int i; 828 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 829 830 i = rx_ring->next_to_use; 831 buffer_info = &rx_ring->buffer_info[i]; 832 833 while (cleaned_count--) { 834 skb = buffer_info->skb; 835 if (skb) { 836 skb_trim(skb, 0); 837 goto check_page; 838 } 839 840 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 841 if (unlikely(!skb)) { 842 /* Better luck next round */ 843 adapter->alloc_rx_buff_failed++; 844 break; 845 } 846 847 buffer_info->skb = skb; 848 check_page: 849 /* allocate a new page if necessary */ 850 if (!buffer_info->page) { 851 buffer_info->page = alloc_page(gfp); 852 if (unlikely(!buffer_info->page)) { 853 adapter->alloc_rx_buff_failed++; 854 break; 855 } 856 } 857 858 if (!buffer_info->dma) { 859 buffer_info->dma = dma_map_page(&pdev->dev, 860 buffer_info->page, 0, 861 PAGE_SIZE, 862 DMA_FROM_DEVICE); 863 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 864 adapter->alloc_rx_buff_failed++; 865 break; 866 } 867 } 868 869 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 870 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 871 872 if (unlikely(++i == rx_ring->count)) 873 i = 0; 874 buffer_info = &rx_ring->buffer_info[i]; 875 } 876 877 if (likely(rx_ring->next_to_use != i)) { 878 rx_ring->next_to_use = i; 879 if (unlikely(i-- == 0)) 880 i = (rx_ring->count - 1); 881 882 /* Force memory writes to complete before letting h/w 883 * know there are new descriptors to fetch. (Only 884 * applicable for weak-ordered memory model archs, 885 * such as IA-64). 886 */ 887 wmb(); 888 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 889 e1000e_update_rdt_wa(rx_ring, i); 890 else 891 writel(i, rx_ring->tail); 892 } 893 } 894 895 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 896 struct sk_buff *skb) 897 { 898 if (netdev->features & NETIF_F_RXHASH) 899 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 900 } 901 902 /** 903 * e1000_clean_rx_irq - Send received data up the network stack 904 * @rx_ring: Rx descriptor ring 905 * @work_done: output parameter for indicating completed work 906 * @work_to_do: how many packets we can clean 907 * 908 * the return value indicates whether actual cleaning was done, there 909 * is no guarantee that everything was cleaned 910 **/ 911 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 912 int work_to_do) 913 { 914 struct e1000_adapter *adapter = rx_ring->adapter; 915 struct net_device *netdev = adapter->netdev; 916 struct pci_dev *pdev = adapter->pdev; 917 struct e1000_hw *hw = &adapter->hw; 918 union e1000_rx_desc_extended *rx_desc, *next_rxd; 919 struct e1000_buffer *buffer_info, *next_buffer; 920 u32 length, staterr; 921 unsigned int i; 922 int cleaned_count = 0; 923 bool cleaned = false; 924 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 925 926 i = rx_ring->next_to_clean; 927 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 928 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 929 buffer_info = &rx_ring->buffer_info[i]; 930 931 while (staterr & E1000_RXD_STAT_DD) { 932 struct sk_buff *skb; 933 934 if (*work_done >= work_to_do) 935 break; 936 (*work_done)++; 937 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 938 939 skb = buffer_info->skb; 940 buffer_info->skb = NULL; 941 942 prefetch(skb->data - NET_IP_ALIGN); 943 944 i++; 945 if (i == rx_ring->count) 946 i = 0; 947 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 948 prefetch(next_rxd); 949 950 next_buffer = &rx_ring->buffer_info[i]; 951 952 cleaned = true; 953 cleaned_count++; 954 dma_unmap_single(&pdev->dev, buffer_info->dma, 955 adapter->rx_buffer_len, DMA_FROM_DEVICE); 956 buffer_info->dma = 0; 957 958 length = le16_to_cpu(rx_desc->wb.upper.length); 959 960 /* !EOP means multiple descriptors were used to store a single 961 * packet, if that's the case we need to toss it. In fact, we 962 * need to toss every packet with the EOP bit clear and the 963 * next frame that _does_ have the EOP bit set, as it is by 964 * definition only a frame fragment 965 */ 966 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 967 adapter->flags2 |= FLAG2_IS_DISCARDING; 968 969 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 970 /* All receives must fit into a single buffer */ 971 e_dbg("Receive packet consumed multiple buffers\n"); 972 /* recycle */ 973 buffer_info->skb = skb; 974 if (staterr & E1000_RXD_STAT_EOP) 975 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 976 goto next_desc; 977 } 978 979 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 980 !(netdev->features & NETIF_F_RXALL))) { 981 /* recycle */ 982 buffer_info->skb = skb; 983 goto next_desc; 984 } 985 986 /* adjust length to remove Ethernet CRC */ 987 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 988 /* If configured to store CRC, don't subtract FCS, 989 * but keep the FCS bytes out of the total_rx_bytes 990 * counter 991 */ 992 if (netdev->features & NETIF_F_RXFCS) 993 total_rx_bytes -= 4; 994 else 995 length -= 4; 996 } 997 998 total_rx_bytes += length; 999 total_rx_packets++; 1000 1001 /* code added for copybreak, this should improve 1002 * performance for small packets with large amounts 1003 * of reassembly being done in the stack 1004 */ 1005 if (length < copybreak) { 1006 struct sk_buff *new_skb = 1007 napi_alloc_skb(&adapter->napi, length); 1008 if (new_skb) { 1009 skb_copy_to_linear_data_offset(new_skb, 1010 -NET_IP_ALIGN, 1011 (skb->data - 1012 NET_IP_ALIGN), 1013 (length + 1014 NET_IP_ALIGN)); 1015 /* save the skb in buffer_info as good */ 1016 buffer_info->skb = skb; 1017 skb = new_skb; 1018 } 1019 /* else just continue with the old one */ 1020 } 1021 /* end copybreak code */ 1022 skb_put(skb, length); 1023 1024 /* Receive Checksum Offload */ 1025 e1000_rx_checksum(adapter, staterr, skb); 1026 1027 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1028 1029 e1000_receive_skb(adapter, netdev, skb, staterr, 1030 rx_desc->wb.upper.vlan); 1031 1032 next_desc: 1033 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1034 1035 /* return some buffers to hardware, one at a time is too slow */ 1036 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1037 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1038 GFP_ATOMIC); 1039 cleaned_count = 0; 1040 } 1041 1042 /* use prefetched values */ 1043 rx_desc = next_rxd; 1044 buffer_info = next_buffer; 1045 1046 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1047 } 1048 rx_ring->next_to_clean = i; 1049 1050 cleaned_count = e1000_desc_unused(rx_ring); 1051 if (cleaned_count) 1052 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1053 1054 adapter->total_rx_bytes += total_rx_bytes; 1055 adapter->total_rx_packets += total_rx_packets; 1056 return cleaned; 1057 } 1058 1059 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1060 struct e1000_buffer *buffer_info, 1061 bool drop) 1062 { 1063 struct e1000_adapter *adapter = tx_ring->adapter; 1064 1065 if (buffer_info->dma) { 1066 if (buffer_info->mapped_as_page) 1067 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1068 buffer_info->length, DMA_TO_DEVICE); 1069 else 1070 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1071 buffer_info->length, DMA_TO_DEVICE); 1072 buffer_info->dma = 0; 1073 } 1074 if (buffer_info->skb) { 1075 if (drop) 1076 dev_kfree_skb_any(buffer_info->skb); 1077 else 1078 dev_consume_skb_any(buffer_info->skb); 1079 buffer_info->skb = NULL; 1080 } 1081 buffer_info->time_stamp = 0; 1082 } 1083 1084 static void e1000_print_hw_hang(struct work_struct *work) 1085 { 1086 struct e1000_adapter *adapter = container_of(work, 1087 struct e1000_adapter, 1088 print_hang_task); 1089 struct net_device *netdev = adapter->netdev; 1090 struct e1000_ring *tx_ring = adapter->tx_ring; 1091 unsigned int i = tx_ring->next_to_clean; 1092 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1093 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1094 struct e1000_hw *hw = &adapter->hw; 1095 u16 phy_status, phy_1000t_status, phy_ext_status; 1096 u16 pci_status; 1097 1098 if (test_bit(__E1000_DOWN, &adapter->state)) 1099 return; 1100 1101 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1102 /* May be block on write-back, flush and detect again 1103 * flush pending descriptor writebacks to memory 1104 */ 1105 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1106 /* execute the writes immediately */ 1107 e1e_flush(); 1108 /* Due to rare timing issues, write to TIDV again to ensure 1109 * the write is successful 1110 */ 1111 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1112 /* execute the writes immediately */ 1113 e1e_flush(); 1114 adapter->tx_hang_recheck = true; 1115 return; 1116 } 1117 adapter->tx_hang_recheck = false; 1118 1119 if (er32(TDH(0)) == er32(TDT(0))) { 1120 e_dbg("false hang detected, ignoring\n"); 1121 return; 1122 } 1123 1124 /* Real hang detected */ 1125 netif_stop_queue(netdev); 1126 1127 e1e_rphy(hw, MII_BMSR, &phy_status); 1128 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1129 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1130 1131 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1132 1133 /* detected Hardware unit hang */ 1134 e_err("Detected Hardware Unit Hang:\n" 1135 " TDH <%x>\n" 1136 " TDT <%x>\n" 1137 " next_to_use <%x>\n" 1138 " next_to_clean <%x>\n" 1139 "buffer_info[next_to_clean]:\n" 1140 " time_stamp <%lx>\n" 1141 " next_to_watch <%x>\n" 1142 " jiffies <%lx>\n" 1143 " next_to_watch.status <%x>\n" 1144 "MAC Status <%x>\n" 1145 "PHY Status <%x>\n" 1146 "PHY 1000BASE-T Status <%x>\n" 1147 "PHY Extended Status <%x>\n" 1148 "PCI Status <%x>\n", 1149 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1150 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1151 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1152 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1153 1154 e1000e_dump(adapter); 1155 1156 /* Suggest workaround for known h/w issue */ 1157 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1158 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1159 } 1160 1161 /** 1162 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1163 * @work: pointer to work struct 1164 * 1165 * This work function polls the TSYNCTXCTL valid bit to determine when a 1166 * timestamp has been taken for the current stored skb. The timestamp must 1167 * be for this skb because only one such packet is allowed in the queue. 1168 */ 1169 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1170 { 1171 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1172 tx_hwtstamp_work); 1173 struct e1000_hw *hw = &adapter->hw; 1174 1175 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1176 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1177 struct skb_shared_hwtstamps shhwtstamps; 1178 u64 txstmp; 1179 1180 txstmp = er32(TXSTMPL); 1181 txstmp |= (u64)er32(TXSTMPH) << 32; 1182 1183 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1184 1185 /* Clear the global tx_hwtstamp_skb pointer and force writes 1186 * prior to notifying the stack of a Tx timestamp. 1187 */ 1188 adapter->tx_hwtstamp_skb = NULL; 1189 wmb(); /* force write prior to skb_tstamp_tx */ 1190 1191 skb_tstamp_tx(skb, &shhwtstamps); 1192 dev_consume_skb_any(skb); 1193 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1194 + adapter->tx_timeout_factor * HZ)) { 1195 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1196 adapter->tx_hwtstamp_skb = NULL; 1197 adapter->tx_hwtstamp_timeouts++; 1198 e_warn("clearing Tx timestamp hang\n"); 1199 } else { 1200 /* reschedule to check later */ 1201 schedule_work(&adapter->tx_hwtstamp_work); 1202 } 1203 } 1204 1205 /** 1206 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1207 * @tx_ring: Tx descriptor ring 1208 * 1209 * the return value indicates whether actual cleaning was done, there 1210 * is no guarantee that everything was cleaned 1211 **/ 1212 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1213 { 1214 struct e1000_adapter *adapter = tx_ring->adapter; 1215 struct net_device *netdev = adapter->netdev; 1216 struct e1000_hw *hw = &adapter->hw; 1217 struct e1000_tx_desc *tx_desc, *eop_desc; 1218 struct e1000_buffer *buffer_info; 1219 unsigned int i, eop; 1220 unsigned int count = 0; 1221 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1222 unsigned int bytes_compl = 0, pkts_compl = 0; 1223 1224 i = tx_ring->next_to_clean; 1225 eop = tx_ring->buffer_info[i].next_to_watch; 1226 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1227 1228 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1229 (count < tx_ring->count)) { 1230 bool cleaned = false; 1231 1232 dma_rmb(); /* read buffer_info after eop_desc */ 1233 for (; !cleaned; count++) { 1234 tx_desc = E1000_TX_DESC(*tx_ring, i); 1235 buffer_info = &tx_ring->buffer_info[i]; 1236 cleaned = (i == eop); 1237 1238 if (cleaned) { 1239 total_tx_packets += buffer_info->segs; 1240 total_tx_bytes += buffer_info->bytecount; 1241 if (buffer_info->skb) { 1242 bytes_compl += buffer_info->skb->len; 1243 pkts_compl++; 1244 } 1245 } 1246 1247 e1000_put_txbuf(tx_ring, buffer_info, false); 1248 tx_desc->upper.data = 0; 1249 1250 i++; 1251 if (i == tx_ring->count) 1252 i = 0; 1253 } 1254 1255 if (i == tx_ring->next_to_use) 1256 break; 1257 eop = tx_ring->buffer_info[i].next_to_watch; 1258 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1259 } 1260 1261 tx_ring->next_to_clean = i; 1262 1263 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1264 1265 #define TX_WAKE_THRESHOLD 32 1266 if (count && netif_carrier_ok(netdev) && 1267 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1268 /* Make sure that anybody stopping the queue after this 1269 * sees the new next_to_clean. 1270 */ 1271 smp_mb(); 1272 1273 if (netif_queue_stopped(netdev) && 1274 !(test_bit(__E1000_DOWN, &adapter->state))) { 1275 netif_wake_queue(netdev); 1276 ++adapter->restart_queue; 1277 } 1278 } 1279 1280 if (adapter->detect_tx_hung) { 1281 /* Detect a transmit hang in hardware, this serializes the 1282 * check with the clearing of time_stamp and movement of i 1283 */ 1284 adapter->detect_tx_hung = false; 1285 if (tx_ring->buffer_info[i].time_stamp && 1286 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1287 + (adapter->tx_timeout_factor * HZ)) && 1288 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1289 schedule_work(&adapter->print_hang_task); 1290 else 1291 adapter->tx_hang_recheck = false; 1292 } 1293 adapter->total_tx_bytes += total_tx_bytes; 1294 adapter->total_tx_packets += total_tx_packets; 1295 return count < tx_ring->count; 1296 } 1297 1298 /** 1299 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1300 * @rx_ring: Rx descriptor ring 1301 * @work_done: output parameter for indicating completed work 1302 * @work_to_do: how many packets we can clean 1303 * 1304 * the return value indicates whether actual cleaning was done, there 1305 * is no guarantee that everything was cleaned 1306 **/ 1307 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1308 int work_to_do) 1309 { 1310 struct e1000_adapter *adapter = rx_ring->adapter; 1311 struct e1000_hw *hw = &adapter->hw; 1312 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1313 struct net_device *netdev = adapter->netdev; 1314 struct pci_dev *pdev = adapter->pdev; 1315 struct e1000_buffer *buffer_info, *next_buffer; 1316 struct e1000_ps_page *ps_page; 1317 struct sk_buff *skb; 1318 unsigned int i, j; 1319 u32 length, staterr; 1320 int cleaned_count = 0; 1321 bool cleaned = false; 1322 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1323 1324 i = rx_ring->next_to_clean; 1325 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1326 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1327 buffer_info = &rx_ring->buffer_info[i]; 1328 1329 while (staterr & E1000_RXD_STAT_DD) { 1330 if (*work_done >= work_to_do) 1331 break; 1332 (*work_done)++; 1333 skb = buffer_info->skb; 1334 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1335 1336 /* in the packet split case this is header only */ 1337 prefetch(skb->data - NET_IP_ALIGN); 1338 1339 i++; 1340 if (i == rx_ring->count) 1341 i = 0; 1342 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1343 prefetch(next_rxd); 1344 1345 next_buffer = &rx_ring->buffer_info[i]; 1346 1347 cleaned = true; 1348 cleaned_count++; 1349 dma_unmap_single(&pdev->dev, buffer_info->dma, 1350 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1351 buffer_info->dma = 0; 1352 1353 /* see !EOP comment in other Rx routine */ 1354 if (!(staterr & E1000_RXD_STAT_EOP)) 1355 adapter->flags2 |= FLAG2_IS_DISCARDING; 1356 1357 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1358 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1359 dev_kfree_skb_irq(skb); 1360 if (staterr & E1000_RXD_STAT_EOP) 1361 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1362 goto next_desc; 1363 } 1364 1365 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1366 !(netdev->features & NETIF_F_RXALL))) { 1367 dev_kfree_skb_irq(skb); 1368 goto next_desc; 1369 } 1370 1371 length = le16_to_cpu(rx_desc->wb.middle.length0); 1372 1373 if (!length) { 1374 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1375 dev_kfree_skb_irq(skb); 1376 goto next_desc; 1377 } 1378 1379 /* Good Receive */ 1380 skb_put(skb, length); 1381 1382 { 1383 /* this looks ugly, but it seems compiler issues make 1384 * it more efficient than reusing j 1385 */ 1386 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1387 1388 /* page alloc/put takes too long and effects small 1389 * packet throughput, so unsplit small packets and 1390 * save the alloc/put only valid in softirq (napi) 1391 * context to call kmap_* 1392 */ 1393 if (l1 && (l1 <= copybreak) && 1394 ((length + l1) <= adapter->rx_ps_bsize0)) { 1395 u8 *vaddr; 1396 1397 ps_page = &buffer_info->ps_pages[0]; 1398 1399 /* there is no documentation about how to call 1400 * kmap_atomic, so we can't hold the mapping 1401 * very long 1402 */ 1403 dma_sync_single_for_cpu(&pdev->dev, 1404 ps_page->dma, 1405 PAGE_SIZE, 1406 DMA_FROM_DEVICE); 1407 vaddr = kmap_atomic(ps_page->page); 1408 memcpy(skb_tail_pointer(skb), vaddr, l1); 1409 kunmap_atomic(vaddr); 1410 dma_sync_single_for_device(&pdev->dev, 1411 ps_page->dma, 1412 PAGE_SIZE, 1413 DMA_FROM_DEVICE); 1414 1415 /* remove the CRC */ 1416 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1417 if (!(netdev->features & NETIF_F_RXFCS)) 1418 l1 -= 4; 1419 } 1420 1421 skb_put(skb, l1); 1422 goto copydone; 1423 } /* if */ 1424 } 1425 1426 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1427 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1428 if (!length) 1429 break; 1430 1431 ps_page = &buffer_info->ps_pages[j]; 1432 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1433 DMA_FROM_DEVICE); 1434 ps_page->dma = 0; 1435 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1436 ps_page->page = NULL; 1437 skb->len += length; 1438 skb->data_len += length; 1439 skb->truesize += PAGE_SIZE; 1440 } 1441 1442 /* strip the ethernet crc, problem is we're using pages now so 1443 * this whole operation can get a little cpu intensive 1444 */ 1445 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1446 if (!(netdev->features & NETIF_F_RXFCS)) 1447 pskb_trim(skb, skb->len - 4); 1448 } 1449 1450 copydone: 1451 total_rx_bytes += skb->len; 1452 total_rx_packets++; 1453 1454 e1000_rx_checksum(adapter, staterr, skb); 1455 1456 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1457 1458 if (rx_desc->wb.upper.header_status & 1459 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1460 adapter->rx_hdr_split++; 1461 1462 e1000_receive_skb(adapter, netdev, skb, staterr, 1463 rx_desc->wb.middle.vlan); 1464 1465 next_desc: 1466 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1467 buffer_info->skb = NULL; 1468 1469 /* return some buffers to hardware, one at a time is too slow */ 1470 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1471 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1472 GFP_ATOMIC); 1473 cleaned_count = 0; 1474 } 1475 1476 /* use prefetched values */ 1477 rx_desc = next_rxd; 1478 buffer_info = next_buffer; 1479 1480 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1481 } 1482 rx_ring->next_to_clean = i; 1483 1484 cleaned_count = e1000_desc_unused(rx_ring); 1485 if (cleaned_count) 1486 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1487 1488 adapter->total_rx_bytes += total_rx_bytes; 1489 adapter->total_rx_packets += total_rx_packets; 1490 return cleaned; 1491 } 1492 1493 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1494 u16 length) 1495 { 1496 bi->page = NULL; 1497 skb->len += length; 1498 skb->data_len += length; 1499 skb->truesize += PAGE_SIZE; 1500 } 1501 1502 /** 1503 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1504 * @rx_ring: Rx descriptor ring 1505 * @work_done: output parameter for indicating completed work 1506 * @work_to_do: how many packets we can clean 1507 * 1508 * the return value indicates whether actual cleaning was done, there 1509 * is no guarantee that everything was cleaned 1510 **/ 1511 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1512 int work_to_do) 1513 { 1514 struct e1000_adapter *adapter = rx_ring->adapter; 1515 struct net_device *netdev = adapter->netdev; 1516 struct pci_dev *pdev = adapter->pdev; 1517 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1518 struct e1000_buffer *buffer_info, *next_buffer; 1519 u32 length, staterr; 1520 unsigned int i; 1521 int cleaned_count = 0; 1522 bool cleaned = false; 1523 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1524 struct skb_shared_info *shinfo; 1525 1526 i = rx_ring->next_to_clean; 1527 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1528 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1529 buffer_info = &rx_ring->buffer_info[i]; 1530 1531 while (staterr & E1000_RXD_STAT_DD) { 1532 struct sk_buff *skb; 1533 1534 if (*work_done >= work_to_do) 1535 break; 1536 (*work_done)++; 1537 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1538 1539 skb = buffer_info->skb; 1540 buffer_info->skb = NULL; 1541 1542 ++i; 1543 if (i == rx_ring->count) 1544 i = 0; 1545 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1546 prefetch(next_rxd); 1547 1548 next_buffer = &rx_ring->buffer_info[i]; 1549 1550 cleaned = true; 1551 cleaned_count++; 1552 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1553 DMA_FROM_DEVICE); 1554 buffer_info->dma = 0; 1555 1556 length = le16_to_cpu(rx_desc->wb.upper.length); 1557 1558 /* errors is only valid for DD + EOP descriptors */ 1559 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1560 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1561 !(netdev->features & NETIF_F_RXALL)))) { 1562 /* recycle both page and skb */ 1563 buffer_info->skb = skb; 1564 /* an error means any chain goes out the window too */ 1565 if (rx_ring->rx_skb_top) 1566 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1567 rx_ring->rx_skb_top = NULL; 1568 goto next_desc; 1569 } 1570 #define rxtop (rx_ring->rx_skb_top) 1571 if (!(staterr & E1000_RXD_STAT_EOP)) { 1572 /* this descriptor is only the beginning (or middle) */ 1573 if (!rxtop) { 1574 /* this is the beginning of a chain */ 1575 rxtop = skb; 1576 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1577 0, length); 1578 } else { 1579 /* this is the middle of a chain */ 1580 shinfo = skb_shinfo(rxtop); 1581 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1582 buffer_info->page, 0, 1583 length); 1584 /* re-use the skb, only consumed the page */ 1585 buffer_info->skb = skb; 1586 } 1587 e1000_consume_page(buffer_info, rxtop, length); 1588 goto next_desc; 1589 } else { 1590 if (rxtop) { 1591 /* end of the chain */ 1592 shinfo = skb_shinfo(rxtop); 1593 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1594 buffer_info->page, 0, 1595 length); 1596 /* re-use the current skb, we only consumed the 1597 * page 1598 */ 1599 buffer_info->skb = skb; 1600 skb = rxtop; 1601 rxtop = NULL; 1602 e1000_consume_page(buffer_info, skb, length); 1603 } else { 1604 /* no chain, got EOP, this buf is the packet 1605 * copybreak to save the put_page/alloc_page 1606 */ 1607 if (length <= copybreak && 1608 skb_tailroom(skb) >= length) { 1609 u8 *vaddr; 1610 vaddr = kmap_atomic(buffer_info->page); 1611 memcpy(skb_tail_pointer(skb), vaddr, 1612 length); 1613 kunmap_atomic(vaddr); 1614 /* re-use the page, so don't erase 1615 * buffer_info->page 1616 */ 1617 skb_put(skb, length); 1618 } else { 1619 skb_fill_page_desc(skb, 0, 1620 buffer_info->page, 0, 1621 length); 1622 e1000_consume_page(buffer_info, skb, 1623 length); 1624 } 1625 } 1626 } 1627 1628 /* Receive Checksum Offload */ 1629 e1000_rx_checksum(adapter, staterr, skb); 1630 1631 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1632 1633 /* probably a little skewed due to removing CRC */ 1634 total_rx_bytes += skb->len; 1635 total_rx_packets++; 1636 1637 /* eth type trans needs skb->data to point to something */ 1638 if (!pskb_may_pull(skb, ETH_HLEN)) { 1639 e_err("pskb_may_pull failed.\n"); 1640 dev_kfree_skb_irq(skb); 1641 goto next_desc; 1642 } 1643 1644 e1000_receive_skb(adapter, netdev, skb, staterr, 1645 rx_desc->wb.upper.vlan); 1646 1647 next_desc: 1648 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1649 1650 /* return some buffers to hardware, one at a time is too slow */ 1651 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1652 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1653 GFP_ATOMIC); 1654 cleaned_count = 0; 1655 } 1656 1657 /* use prefetched values */ 1658 rx_desc = next_rxd; 1659 buffer_info = next_buffer; 1660 1661 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1662 } 1663 rx_ring->next_to_clean = i; 1664 1665 cleaned_count = e1000_desc_unused(rx_ring); 1666 if (cleaned_count) 1667 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1668 1669 adapter->total_rx_bytes += total_rx_bytes; 1670 adapter->total_rx_packets += total_rx_packets; 1671 return cleaned; 1672 } 1673 1674 /** 1675 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1676 * @rx_ring: Rx descriptor ring 1677 **/ 1678 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1679 { 1680 struct e1000_adapter *adapter = rx_ring->adapter; 1681 struct e1000_buffer *buffer_info; 1682 struct e1000_ps_page *ps_page; 1683 struct pci_dev *pdev = adapter->pdev; 1684 unsigned int i, j; 1685 1686 /* Free all the Rx ring sk_buffs */ 1687 for (i = 0; i < rx_ring->count; i++) { 1688 buffer_info = &rx_ring->buffer_info[i]; 1689 if (buffer_info->dma) { 1690 if (adapter->clean_rx == e1000_clean_rx_irq) 1691 dma_unmap_single(&pdev->dev, buffer_info->dma, 1692 adapter->rx_buffer_len, 1693 DMA_FROM_DEVICE); 1694 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1695 dma_unmap_page(&pdev->dev, buffer_info->dma, 1696 PAGE_SIZE, DMA_FROM_DEVICE); 1697 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1698 dma_unmap_single(&pdev->dev, buffer_info->dma, 1699 adapter->rx_ps_bsize0, 1700 DMA_FROM_DEVICE); 1701 buffer_info->dma = 0; 1702 } 1703 1704 if (buffer_info->page) { 1705 put_page(buffer_info->page); 1706 buffer_info->page = NULL; 1707 } 1708 1709 if (buffer_info->skb) { 1710 dev_kfree_skb(buffer_info->skb); 1711 buffer_info->skb = NULL; 1712 } 1713 1714 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1715 ps_page = &buffer_info->ps_pages[j]; 1716 if (!ps_page->page) 1717 break; 1718 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1719 DMA_FROM_DEVICE); 1720 ps_page->dma = 0; 1721 put_page(ps_page->page); 1722 ps_page->page = NULL; 1723 } 1724 } 1725 1726 /* there also may be some cached data from a chained receive */ 1727 if (rx_ring->rx_skb_top) { 1728 dev_kfree_skb(rx_ring->rx_skb_top); 1729 rx_ring->rx_skb_top = NULL; 1730 } 1731 1732 /* Zero out the descriptor ring */ 1733 memset(rx_ring->desc, 0, rx_ring->size); 1734 1735 rx_ring->next_to_clean = 0; 1736 rx_ring->next_to_use = 0; 1737 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1738 } 1739 1740 static void e1000e_downshift_workaround(struct work_struct *work) 1741 { 1742 struct e1000_adapter *adapter = container_of(work, 1743 struct e1000_adapter, 1744 downshift_task); 1745 1746 if (test_bit(__E1000_DOWN, &adapter->state)) 1747 return; 1748 1749 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1750 } 1751 1752 /** 1753 * e1000_intr_msi - Interrupt Handler 1754 * @irq: interrupt number 1755 * @data: pointer to a network interface device structure 1756 **/ 1757 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1758 { 1759 struct net_device *netdev = data; 1760 struct e1000_adapter *adapter = netdev_priv(netdev); 1761 struct e1000_hw *hw = &adapter->hw; 1762 u32 icr = er32(ICR); 1763 1764 /* read ICR disables interrupts using IAM */ 1765 if (icr & E1000_ICR_LSC) { 1766 hw->mac.get_link_status = true; 1767 /* ICH8 workaround-- Call gig speed drop workaround on cable 1768 * disconnect (LSC) before accessing any PHY registers 1769 */ 1770 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1771 (!(er32(STATUS) & E1000_STATUS_LU))) 1772 schedule_work(&adapter->downshift_task); 1773 1774 /* 80003ES2LAN workaround-- For packet buffer work-around on 1775 * link down event; disable receives here in the ISR and reset 1776 * adapter in watchdog 1777 */ 1778 if (netif_carrier_ok(netdev) && 1779 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1780 /* disable receives */ 1781 u32 rctl = er32(RCTL); 1782 1783 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1784 adapter->flags |= FLAG_RESTART_NOW; 1785 } 1786 /* guard against interrupt when we're going down */ 1787 if (!test_bit(__E1000_DOWN, &adapter->state)) 1788 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1789 } 1790 1791 /* Reset on uncorrectable ECC error */ 1792 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1793 u32 pbeccsts = er32(PBECCSTS); 1794 1795 adapter->corr_errors += 1796 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1797 adapter->uncorr_errors += 1798 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1799 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1800 1801 /* Do the reset outside of interrupt context */ 1802 schedule_work(&adapter->reset_task); 1803 1804 /* return immediately since reset is imminent */ 1805 return IRQ_HANDLED; 1806 } 1807 1808 if (napi_schedule_prep(&adapter->napi)) { 1809 adapter->total_tx_bytes = 0; 1810 adapter->total_tx_packets = 0; 1811 adapter->total_rx_bytes = 0; 1812 adapter->total_rx_packets = 0; 1813 __napi_schedule(&adapter->napi); 1814 } 1815 1816 return IRQ_HANDLED; 1817 } 1818 1819 /** 1820 * e1000_intr - Interrupt Handler 1821 * @irq: interrupt number 1822 * @data: pointer to a network interface device structure 1823 **/ 1824 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1825 { 1826 struct net_device *netdev = data; 1827 struct e1000_adapter *adapter = netdev_priv(netdev); 1828 struct e1000_hw *hw = &adapter->hw; 1829 u32 rctl, icr = er32(ICR); 1830 1831 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1832 return IRQ_NONE; /* Not our interrupt */ 1833 1834 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1835 * not set, then the adapter didn't send an interrupt 1836 */ 1837 if (!(icr & E1000_ICR_INT_ASSERTED)) 1838 return IRQ_NONE; 1839 1840 /* Interrupt Auto-Mask...upon reading ICR, 1841 * interrupts are masked. No need for the 1842 * IMC write 1843 */ 1844 1845 if (icr & E1000_ICR_LSC) { 1846 hw->mac.get_link_status = true; 1847 /* ICH8 workaround-- Call gig speed drop workaround on cable 1848 * disconnect (LSC) before accessing any PHY registers 1849 */ 1850 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1851 (!(er32(STATUS) & E1000_STATUS_LU))) 1852 schedule_work(&adapter->downshift_task); 1853 1854 /* 80003ES2LAN workaround-- 1855 * For packet buffer work-around on link down event; 1856 * disable receives here in the ISR and 1857 * reset adapter in watchdog 1858 */ 1859 if (netif_carrier_ok(netdev) && 1860 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1861 /* disable receives */ 1862 rctl = er32(RCTL); 1863 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1864 adapter->flags |= FLAG_RESTART_NOW; 1865 } 1866 /* guard against interrupt when we're going down */ 1867 if (!test_bit(__E1000_DOWN, &adapter->state)) 1868 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1869 } 1870 1871 /* Reset on uncorrectable ECC error */ 1872 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1873 u32 pbeccsts = er32(PBECCSTS); 1874 1875 adapter->corr_errors += 1876 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1877 adapter->uncorr_errors += 1878 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1879 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1880 1881 /* Do the reset outside of interrupt context */ 1882 schedule_work(&adapter->reset_task); 1883 1884 /* return immediately since reset is imminent */ 1885 return IRQ_HANDLED; 1886 } 1887 1888 if (napi_schedule_prep(&adapter->napi)) { 1889 adapter->total_tx_bytes = 0; 1890 adapter->total_tx_packets = 0; 1891 adapter->total_rx_bytes = 0; 1892 adapter->total_rx_packets = 0; 1893 __napi_schedule(&adapter->napi); 1894 } 1895 1896 return IRQ_HANDLED; 1897 } 1898 1899 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1900 { 1901 struct net_device *netdev = data; 1902 struct e1000_adapter *adapter = netdev_priv(netdev); 1903 struct e1000_hw *hw = &adapter->hw; 1904 u32 icr = er32(ICR); 1905 1906 if (icr & adapter->eiac_mask) 1907 ew32(ICS, (icr & adapter->eiac_mask)); 1908 1909 if (icr & E1000_ICR_LSC) { 1910 hw->mac.get_link_status = true; 1911 /* guard against interrupt when we're going down */ 1912 if (!test_bit(__E1000_DOWN, &adapter->state)) 1913 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1914 } 1915 1916 if (!test_bit(__E1000_DOWN, &adapter->state)) 1917 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1918 1919 return IRQ_HANDLED; 1920 } 1921 1922 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1923 { 1924 struct net_device *netdev = data; 1925 struct e1000_adapter *adapter = netdev_priv(netdev); 1926 struct e1000_hw *hw = &adapter->hw; 1927 struct e1000_ring *tx_ring = adapter->tx_ring; 1928 1929 adapter->total_tx_bytes = 0; 1930 adapter->total_tx_packets = 0; 1931 1932 if (!e1000_clean_tx_irq(tx_ring)) 1933 /* Ring was not completely cleaned, so fire another interrupt */ 1934 ew32(ICS, tx_ring->ims_val); 1935 1936 if (!test_bit(__E1000_DOWN, &adapter->state)) 1937 ew32(IMS, adapter->tx_ring->ims_val); 1938 1939 return IRQ_HANDLED; 1940 } 1941 1942 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1943 { 1944 struct net_device *netdev = data; 1945 struct e1000_adapter *adapter = netdev_priv(netdev); 1946 struct e1000_ring *rx_ring = adapter->rx_ring; 1947 1948 /* Write the ITR value calculated at the end of the 1949 * previous interrupt. 1950 */ 1951 if (rx_ring->set_itr) { 1952 u32 itr = rx_ring->itr_val ? 1953 1000000000 / (rx_ring->itr_val * 256) : 0; 1954 1955 writel(itr, rx_ring->itr_register); 1956 rx_ring->set_itr = 0; 1957 } 1958 1959 if (napi_schedule_prep(&adapter->napi)) { 1960 adapter->total_rx_bytes = 0; 1961 adapter->total_rx_packets = 0; 1962 __napi_schedule(&adapter->napi); 1963 } 1964 return IRQ_HANDLED; 1965 } 1966 1967 /** 1968 * e1000_configure_msix - Configure MSI-X hardware 1969 * @adapter: board private structure 1970 * 1971 * e1000_configure_msix sets up the hardware to properly 1972 * generate MSI-X interrupts. 1973 **/ 1974 static void e1000_configure_msix(struct e1000_adapter *adapter) 1975 { 1976 struct e1000_hw *hw = &adapter->hw; 1977 struct e1000_ring *rx_ring = adapter->rx_ring; 1978 struct e1000_ring *tx_ring = adapter->tx_ring; 1979 int vector = 0; 1980 u32 ctrl_ext, ivar = 0; 1981 1982 adapter->eiac_mask = 0; 1983 1984 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1985 if (hw->mac.type == e1000_82574) { 1986 u32 rfctl = er32(RFCTL); 1987 1988 rfctl |= E1000_RFCTL_ACK_DIS; 1989 ew32(RFCTL, rfctl); 1990 } 1991 1992 /* Configure Rx vector */ 1993 rx_ring->ims_val = E1000_IMS_RXQ0; 1994 adapter->eiac_mask |= rx_ring->ims_val; 1995 if (rx_ring->itr_val) 1996 writel(1000000000 / (rx_ring->itr_val * 256), 1997 rx_ring->itr_register); 1998 else 1999 writel(1, rx_ring->itr_register); 2000 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 2001 2002 /* Configure Tx vector */ 2003 tx_ring->ims_val = E1000_IMS_TXQ0; 2004 vector++; 2005 if (tx_ring->itr_val) 2006 writel(1000000000 / (tx_ring->itr_val * 256), 2007 tx_ring->itr_register); 2008 else 2009 writel(1, tx_ring->itr_register); 2010 adapter->eiac_mask |= tx_ring->ims_val; 2011 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2012 2013 /* set vector for Other Causes, e.g. link changes */ 2014 vector++; 2015 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2016 if (rx_ring->itr_val) 2017 writel(1000000000 / (rx_ring->itr_val * 256), 2018 hw->hw_addr + E1000_EITR_82574(vector)); 2019 else 2020 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2021 2022 /* Cause Tx interrupts on every write back */ 2023 ivar |= BIT(31); 2024 2025 ew32(IVAR, ivar); 2026 2027 /* enable MSI-X PBA support */ 2028 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2029 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2030 ew32(CTRL_EXT, ctrl_ext); 2031 e1e_flush(); 2032 } 2033 2034 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2035 { 2036 if (adapter->msix_entries) { 2037 pci_disable_msix(adapter->pdev); 2038 kfree(adapter->msix_entries); 2039 adapter->msix_entries = NULL; 2040 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2041 pci_disable_msi(adapter->pdev); 2042 adapter->flags &= ~FLAG_MSI_ENABLED; 2043 } 2044 } 2045 2046 /** 2047 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2048 * @adapter: board private structure 2049 * 2050 * Attempt to configure interrupts using the best available 2051 * capabilities of the hardware and kernel. 2052 **/ 2053 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2054 { 2055 int err; 2056 int i; 2057 2058 switch (adapter->int_mode) { 2059 case E1000E_INT_MODE_MSIX: 2060 if (adapter->flags & FLAG_HAS_MSIX) { 2061 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2062 adapter->msix_entries = kcalloc(adapter->num_vectors, 2063 sizeof(struct 2064 msix_entry), 2065 GFP_KERNEL); 2066 if (adapter->msix_entries) { 2067 struct e1000_adapter *a = adapter; 2068 2069 for (i = 0; i < adapter->num_vectors; i++) 2070 adapter->msix_entries[i].entry = i; 2071 2072 err = pci_enable_msix_range(a->pdev, 2073 a->msix_entries, 2074 a->num_vectors, 2075 a->num_vectors); 2076 if (err > 0) 2077 return; 2078 } 2079 /* MSI-X failed, so fall through and try MSI */ 2080 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2081 e1000e_reset_interrupt_capability(adapter); 2082 } 2083 adapter->int_mode = E1000E_INT_MODE_MSI; 2084 fallthrough; 2085 case E1000E_INT_MODE_MSI: 2086 if (!pci_enable_msi(adapter->pdev)) { 2087 adapter->flags |= FLAG_MSI_ENABLED; 2088 } else { 2089 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2090 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2091 } 2092 fallthrough; 2093 case E1000E_INT_MODE_LEGACY: 2094 /* Don't do anything; this is the system default */ 2095 break; 2096 } 2097 2098 /* store the number of vectors being used */ 2099 adapter->num_vectors = 1; 2100 } 2101 2102 /** 2103 * e1000_request_msix - Initialize MSI-X interrupts 2104 * @adapter: board private structure 2105 * 2106 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2107 * kernel. 2108 **/ 2109 static int e1000_request_msix(struct e1000_adapter *adapter) 2110 { 2111 struct net_device *netdev = adapter->netdev; 2112 int err = 0, vector = 0; 2113 2114 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2115 snprintf(adapter->rx_ring->name, 2116 sizeof(adapter->rx_ring->name) - 1, 2117 "%.14s-rx-0", netdev->name); 2118 else 2119 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2120 err = request_irq(adapter->msix_entries[vector].vector, 2121 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2122 netdev); 2123 if (err) 2124 return err; 2125 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2126 E1000_EITR_82574(vector); 2127 adapter->rx_ring->itr_val = adapter->itr; 2128 vector++; 2129 2130 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2131 snprintf(adapter->tx_ring->name, 2132 sizeof(adapter->tx_ring->name) - 1, 2133 "%.14s-tx-0", netdev->name); 2134 else 2135 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2136 err = request_irq(adapter->msix_entries[vector].vector, 2137 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2138 netdev); 2139 if (err) 2140 return err; 2141 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2142 E1000_EITR_82574(vector); 2143 adapter->tx_ring->itr_val = adapter->itr; 2144 vector++; 2145 2146 err = request_irq(adapter->msix_entries[vector].vector, 2147 e1000_msix_other, 0, netdev->name, netdev); 2148 if (err) 2149 return err; 2150 2151 e1000_configure_msix(adapter); 2152 2153 return 0; 2154 } 2155 2156 /** 2157 * e1000_request_irq - initialize interrupts 2158 * @adapter: board private structure 2159 * 2160 * Attempts to configure interrupts using the best available 2161 * capabilities of the hardware and kernel. 2162 **/ 2163 static int e1000_request_irq(struct e1000_adapter *adapter) 2164 { 2165 struct net_device *netdev = adapter->netdev; 2166 int err; 2167 2168 if (adapter->msix_entries) { 2169 err = e1000_request_msix(adapter); 2170 if (!err) 2171 return err; 2172 /* fall back to MSI */ 2173 e1000e_reset_interrupt_capability(adapter); 2174 adapter->int_mode = E1000E_INT_MODE_MSI; 2175 e1000e_set_interrupt_capability(adapter); 2176 } 2177 if (adapter->flags & FLAG_MSI_ENABLED) { 2178 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2179 netdev->name, netdev); 2180 if (!err) 2181 return err; 2182 2183 /* fall back to legacy interrupt */ 2184 e1000e_reset_interrupt_capability(adapter); 2185 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2186 } 2187 2188 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2189 netdev->name, netdev); 2190 if (err) 2191 e_err("Unable to allocate interrupt, Error: %d\n", err); 2192 2193 return err; 2194 } 2195 2196 static void e1000_free_irq(struct e1000_adapter *adapter) 2197 { 2198 struct net_device *netdev = adapter->netdev; 2199 2200 if (adapter->msix_entries) { 2201 int vector = 0; 2202 2203 free_irq(adapter->msix_entries[vector].vector, netdev); 2204 vector++; 2205 2206 free_irq(adapter->msix_entries[vector].vector, netdev); 2207 vector++; 2208 2209 /* Other Causes interrupt vector */ 2210 free_irq(adapter->msix_entries[vector].vector, netdev); 2211 return; 2212 } 2213 2214 free_irq(adapter->pdev->irq, netdev); 2215 } 2216 2217 /** 2218 * e1000_irq_disable - Mask off interrupt generation on the NIC 2219 * @adapter: board private structure 2220 **/ 2221 static void e1000_irq_disable(struct e1000_adapter *adapter) 2222 { 2223 struct e1000_hw *hw = &adapter->hw; 2224 2225 ew32(IMC, ~0); 2226 if (adapter->msix_entries) 2227 ew32(EIAC_82574, 0); 2228 e1e_flush(); 2229 2230 if (adapter->msix_entries) { 2231 int i; 2232 2233 for (i = 0; i < adapter->num_vectors; i++) 2234 synchronize_irq(adapter->msix_entries[i].vector); 2235 } else { 2236 synchronize_irq(adapter->pdev->irq); 2237 } 2238 } 2239 2240 /** 2241 * e1000_irq_enable - Enable default interrupt generation settings 2242 * @adapter: board private structure 2243 **/ 2244 static void e1000_irq_enable(struct e1000_adapter *adapter) 2245 { 2246 struct e1000_hw *hw = &adapter->hw; 2247 2248 if (adapter->msix_entries) { 2249 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2250 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2251 IMS_OTHER_MASK); 2252 } else if (hw->mac.type >= e1000_pch_lpt) { 2253 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2254 } else { 2255 ew32(IMS, IMS_ENABLE_MASK); 2256 } 2257 e1e_flush(); 2258 } 2259 2260 /** 2261 * e1000e_get_hw_control - get control of the h/w from f/w 2262 * @adapter: address of board private structure 2263 * 2264 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2265 * For ASF and Pass Through versions of f/w this means that 2266 * the driver is loaded. For AMT version (only with 82573) 2267 * of the f/w this means that the network i/f is open. 2268 **/ 2269 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2270 { 2271 struct e1000_hw *hw = &adapter->hw; 2272 u32 ctrl_ext; 2273 u32 swsm; 2274 2275 /* Let firmware know the driver has taken over */ 2276 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2277 swsm = er32(SWSM); 2278 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2279 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2280 ctrl_ext = er32(CTRL_EXT); 2281 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2282 } 2283 } 2284 2285 /** 2286 * e1000e_release_hw_control - release control of the h/w to f/w 2287 * @adapter: address of board private structure 2288 * 2289 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2290 * For ASF and Pass Through versions of f/w this means that the 2291 * driver is no longer loaded. For AMT version (only with 82573) i 2292 * of the f/w this means that the network i/f is closed. 2293 * 2294 **/ 2295 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2296 { 2297 struct e1000_hw *hw = &adapter->hw; 2298 u32 ctrl_ext; 2299 u32 swsm; 2300 2301 /* Let firmware taken over control of h/w */ 2302 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2303 swsm = er32(SWSM); 2304 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2305 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2306 ctrl_ext = er32(CTRL_EXT); 2307 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2308 } 2309 } 2310 2311 /** 2312 * e1000_alloc_ring_dma - allocate memory for a ring structure 2313 * @adapter: board private structure 2314 * @ring: ring struct for which to allocate dma 2315 **/ 2316 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2317 struct e1000_ring *ring) 2318 { 2319 struct pci_dev *pdev = adapter->pdev; 2320 2321 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2322 GFP_KERNEL); 2323 if (!ring->desc) 2324 return -ENOMEM; 2325 2326 return 0; 2327 } 2328 2329 /** 2330 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2331 * @tx_ring: Tx descriptor ring 2332 * 2333 * Return 0 on success, negative on failure 2334 **/ 2335 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2336 { 2337 struct e1000_adapter *adapter = tx_ring->adapter; 2338 int err = -ENOMEM, size; 2339 2340 size = sizeof(struct e1000_buffer) * tx_ring->count; 2341 tx_ring->buffer_info = vzalloc(size); 2342 if (!tx_ring->buffer_info) 2343 goto err; 2344 2345 /* round up to nearest 4K */ 2346 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2347 tx_ring->size = ALIGN(tx_ring->size, 4096); 2348 2349 err = e1000_alloc_ring_dma(adapter, tx_ring); 2350 if (err) 2351 goto err; 2352 2353 tx_ring->next_to_use = 0; 2354 tx_ring->next_to_clean = 0; 2355 2356 return 0; 2357 err: 2358 vfree(tx_ring->buffer_info); 2359 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2360 return err; 2361 } 2362 2363 /** 2364 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2365 * @rx_ring: Rx descriptor ring 2366 * 2367 * Returns 0 on success, negative on failure 2368 **/ 2369 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2370 { 2371 struct e1000_adapter *adapter = rx_ring->adapter; 2372 struct e1000_buffer *buffer_info; 2373 int i, size, desc_len, err = -ENOMEM; 2374 2375 size = sizeof(struct e1000_buffer) * rx_ring->count; 2376 rx_ring->buffer_info = vzalloc(size); 2377 if (!rx_ring->buffer_info) 2378 goto err; 2379 2380 for (i = 0; i < rx_ring->count; i++) { 2381 buffer_info = &rx_ring->buffer_info[i]; 2382 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2383 sizeof(struct e1000_ps_page), 2384 GFP_KERNEL); 2385 if (!buffer_info->ps_pages) 2386 goto err_pages; 2387 } 2388 2389 desc_len = sizeof(union e1000_rx_desc_packet_split); 2390 2391 /* Round up to nearest 4K */ 2392 rx_ring->size = rx_ring->count * desc_len; 2393 rx_ring->size = ALIGN(rx_ring->size, 4096); 2394 2395 err = e1000_alloc_ring_dma(adapter, rx_ring); 2396 if (err) 2397 goto err_pages; 2398 2399 rx_ring->next_to_clean = 0; 2400 rx_ring->next_to_use = 0; 2401 rx_ring->rx_skb_top = NULL; 2402 2403 return 0; 2404 2405 err_pages: 2406 for (i = 0; i < rx_ring->count; i++) { 2407 buffer_info = &rx_ring->buffer_info[i]; 2408 kfree(buffer_info->ps_pages); 2409 } 2410 err: 2411 vfree(rx_ring->buffer_info); 2412 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2413 return err; 2414 } 2415 2416 /** 2417 * e1000_clean_tx_ring - Free Tx Buffers 2418 * @tx_ring: Tx descriptor ring 2419 **/ 2420 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2421 { 2422 struct e1000_adapter *adapter = tx_ring->adapter; 2423 struct e1000_buffer *buffer_info; 2424 unsigned long size; 2425 unsigned int i; 2426 2427 for (i = 0; i < tx_ring->count; i++) { 2428 buffer_info = &tx_ring->buffer_info[i]; 2429 e1000_put_txbuf(tx_ring, buffer_info, false); 2430 } 2431 2432 netdev_reset_queue(adapter->netdev); 2433 size = sizeof(struct e1000_buffer) * tx_ring->count; 2434 memset(tx_ring->buffer_info, 0, size); 2435 2436 memset(tx_ring->desc, 0, tx_ring->size); 2437 2438 tx_ring->next_to_use = 0; 2439 tx_ring->next_to_clean = 0; 2440 } 2441 2442 /** 2443 * e1000e_free_tx_resources - Free Tx Resources per Queue 2444 * @tx_ring: Tx descriptor ring 2445 * 2446 * Free all transmit software resources 2447 **/ 2448 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2449 { 2450 struct e1000_adapter *adapter = tx_ring->adapter; 2451 struct pci_dev *pdev = adapter->pdev; 2452 2453 e1000_clean_tx_ring(tx_ring); 2454 2455 vfree(tx_ring->buffer_info); 2456 tx_ring->buffer_info = NULL; 2457 2458 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2459 tx_ring->dma); 2460 tx_ring->desc = NULL; 2461 } 2462 2463 /** 2464 * e1000e_free_rx_resources - Free Rx Resources 2465 * @rx_ring: Rx descriptor ring 2466 * 2467 * Free all receive software resources 2468 **/ 2469 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2470 { 2471 struct e1000_adapter *adapter = rx_ring->adapter; 2472 struct pci_dev *pdev = adapter->pdev; 2473 int i; 2474 2475 e1000_clean_rx_ring(rx_ring); 2476 2477 for (i = 0; i < rx_ring->count; i++) 2478 kfree(rx_ring->buffer_info[i].ps_pages); 2479 2480 vfree(rx_ring->buffer_info); 2481 rx_ring->buffer_info = NULL; 2482 2483 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2484 rx_ring->dma); 2485 rx_ring->desc = NULL; 2486 } 2487 2488 /** 2489 * e1000_update_itr - update the dynamic ITR value based on statistics 2490 * @itr_setting: current adapter->itr 2491 * @packets: the number of packets during this measurement interval 2492 * @bytes: the number of bytes during this measurement interval 2493 * 2494 * Stores a new ITR value based on packets and byte 2495 * counts during the last interrupt. The advantage of per interrupt 2496 * computation is faster updates and more accurate ITR for the current 2497 * traffic pattern. Constants in this function were computed 2498 * based on theoretical maximum wire speed and thresholds were set based 2499 * on testing data as well as attempting to minimize response time 2500 * while increasing bulk throughput. This functionality is controlled 2501 * by the InterruptThrottleRate module parameter. 2502 **/ 2503 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2504 { 2505 unsigned int retval = itr_setting; 2506 2507 if (packets == 0) 2508 return itr_setting; 2509 2510 switch (itr_setting) { 2511 case lowest_latency: 2512 /* handle TSO and jumbo frames */ 2513 if (bytes / packets > 8000) 2514 retval = bulk_latency; 2515 else if ((packets < 5) && (bytes > 512)) 2516 retval = low_latency; 2517 break; 2518 case low_latency: /* 50 usec aka 20000 ints/s */ 2519 if (bytes > 10000) { 2520 /* this if handles the TSO accounting */ 2521 if (bytes / packets > 8000) 2522 retval = bulk_latency; 2523 else if ((packets < 10) || ((bytes / packets) > 1200)) 2524 retval = bulk_latency; 2525 else if ((packets > 35)) 2526 retval = lowest_latency; 2527 } else if (bytes / packets > 2000) { 2528 retval = bulk_latency; 2529 } else if (packets <= 2 && bytes < 512) { 2530 retval = lowest_latency; 2531 } 2532 break; 2533 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2534 if (bytes > 25000) { 2535 if (packets > 35) 2536 retval = low_latency; 2537 } else if (bytes < 6000) { 2538 retval = low_latency; 2539 } 2540 break; 2541 } 2542 2543 return retval; 2544 } 2545 2546 static void e1000_set_itr(struct e1000_adapter *adapter) 2547 { 2548 u16 current_itr; 2549 u32 new_itr = adapter->itr; 2550 2551 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2552 if (adapter->link_speed != SPEED_1000) { 2553 current_itr = 0; 2554 new_itr = 4000; 2555 goto set_itr_now; 2556 } 2557 2558 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2559 new_itr = 0; 2560 goto set_itr_now; 2561 } 2562 2563 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2564 adapter->total_tx_packets, 2565 adapter->total_tx_bytes); 2566 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2567 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2568 adapter->tx_itr = low_latency; 2569 2570 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2571 adapter->total_rx_packets, 2572 adapter->total_rx_bytes); 2573 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2574 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2575 adapter->rx_itr = low_latency; 2576 2577 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2578 2579 /* counts and packets in update_itr are dependent on these numbers */ 2580 switch (current_itr) { 2581 case lowest_latency: 2582 new_itr = 70000; 2583 break; 2584 case low_latency: 2585 new_itr = 20000; /* aka hwitr = ~200 */ 2586 break; 2587 case bulk_latency: 2588 new_itr = 4000; 2589 break; 2590 default: 2591 break; 2592 } 2593 2594 set_itr_now: 2595 if (new_itr != adapter->itr) { 2596 /* this attempts to bias the interrupt rate towards Bulk 2597 * by adding intermediate steps when interrupt rate is 2598 * increasing 2599 */ 2600 new_itr = new_itr > adapter->itr ? 2601 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2602 adapter->itr = new_itr; 2603 adapter->rx_ring->itr_val = new_itr; 2604 if (adapter->msix_entries) 2605 adapter->rx_ring->set_itr = 1; 2606 else 2607 e1000e_write_itr(adapter, new_itr); 2608 } 2609 } 2610 2611 /** 2612 * e1000e_write_itr - write the ITR value to the appropriate registers 2613 * @adapter: address of board private structure 2614 * @itr: new ITR value to program 2615 * 2616 * e1000e_write_itr determines if the adapter is in MSI-X mode 2617 * and, if so, writes the EITR registers with the ITR value. 2618 * Otherwise, it writes the ITR value into the ITR register. 2619 **/ 2620 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2621 { 2622 struct e1000_hw *hw = &adapter->hw; 2623 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2624 2625 if (adapter->msix_entries) { 2626 int vector; 2627 2628 for (vector = 0; vector < adapter->num_vectors; vector++) 2629 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2630 } else { 2631 ew32(ITR, new_itr); 2632 } 2633 } 2634 2635 /** 2636 * e1000_alloc_queues - Allocate memory for all rings 2637 * @adapter: board private structure to initialize 2638 **/ 2639 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2640 { 2641 int size = sizeof(struct e1000_ring); 2642 2643 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2644 if (!adapter->tx_ring) 2645 goto err; 2646 adapter->tx_ring->count = adapter->tx_ring_count; 2647 adapter->tx_ring->adapter = adapter; 2648 2649 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2650 if (!adapter->rx_ring) 2651 goto err; 2652 adapter->rx_ring->count = adapter->rx_ring_count; 2653 adapter->rx_ring->adapter = adapter; 2654 2655 return 0; 2656 err: 2657 e_err("Unable to allocate memory for queues\n"); 2658 kfree(adapter->rx_ring); 2659 kfree(adapter->tx_ring); 2660 return -ENOMEM; 2661 } 2662 2663 /** 2664 * e1000e_poll - NAPI Rx polling callback 2665 * @napi: struct associated with this polling callback 2666 * @budget: number of packets driver is allowed to process this poll 2667 **/ 2668 static int e1000e_poll(struct napi_struct *napi, int budget) 2669 { 2670 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2671 napi); 2672 struct e1000_hw *hw = &adapter->hw; 2673 struct net_device *poll_dev = adapter->netdev; 2674 int tx_cleaned = 1, work_done = 0; 2675 2676 adapter = netdev_priv(poll_dev); 2677 2678 if (!adapter->msix_entries || 2679 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2680 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2681 2682 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2683 2684 if (!tx_cleaned || work_done == budget) 2685 return budget; 2686 2687 /* Exit the polling mode, but don't re-enable interrupts if stack might 2688 * poll us due to busy-polling 2689 */ 2690 if (likely(napi_complete_done(napi, work_done))) { 2691 if (adapter->itr_setting & 3) 2692 e1000_set_itr(adapter); 2693 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2694 if (adapter->msix_entries) 2695 ew32(IMS, adapter->rx_ring->ims_val); 2696 else 2697 e1000_irq_enable(adapter); 2698 } 2699 } 2700 2701 return work_done; 2702 } 2703 2704 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2705 __always_unused __be16 proto, u16 vid) 2706 { 2707 struct e1000_adapter *adapter = netdev_priv(netdev); 2708 struct e1000_hw *hw = &adapter->hw; 2709 u32 vfta, index; 2710 2711 /* don't update vlan cookie if already programmed */ 2712 if ((adapter->hw.mng_cookie.status & 2713 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2714 (vid == adapter->mng_vlan_id)) 2715 return 0; 2716 2717 /* add VID to filter table */ 2718 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2719 index = (vid >> 5) & 0x7F; 2720 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2721 vfta |= BIT((vid & 0x1F)); 2722 hw->mac.ops.write_vfta(hw, index, vfta); 2723 } 2724 2725 set_bit(vid, adapter->active_vlans); 2726 2727 return 0; 2728 } 2729 2730 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2731 __always_unused __be16 proto, u16 vid) 2732 { 2733 struct e1000_adapter *adapter = netdev_priv(netdev); 2734 struct e1000_hw *hw = &adapter->hw; 2735 u32 vfta, index; 2736 2737 if ((adapter->hw.mng_cookie.status & 2738 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2739 (vid == adapter->mng_vlan_id)) { 2740 /* release control to f/w */ 2741 e1000e_release_hw_control(adapter); 2742 return 0; 2743 } 2744 2745 /* remove VID from filter table */ 2746 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2747 index = (vid >> 5) & 0x7F; 2748 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2749 vfta &= ~BIT((vid & 0x1F)); 2750 hw->mac.ops.write_vfta(hw, index, vfta); 2751 } 2752 2753 clear_bit(vid, adapter->active_vlans); 2754 2755 return 0; 2756 } 2757 2758 /** 2759 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2760 * @adapter: board private structure to initialize 2761 **/ 2762 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2763 { 2764 struct net_device *netdev = adapter->netdev; 2765 struct e1000_hw *hw = &adapter->hw; 2766 u32 rctl; 2767 2768 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2769 /* disable VLAN receive filtering */ 2770 rctl = er32(RCTL); 2771 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2772 ew32(RCTL, rctl); 2773 2774 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2775 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2776 adapter->mng_vlan_id); 2777 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2778 } 2779 } 2780 } 2781 2782 /** 2783 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2784 * @adapter: board private structure to initialize 2785 **/ 2786 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2787 { 2788 struct e1000_hw *hw = &adapter->hw; 2789 u32 rctl; 2790 2791 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2792 /* enable VLAN receive filtering */ 2793 rctl = er32(RCTL); 2794 rctl |= E1000_RCTL_VFE; 2795 rctl &= ~E1000_RCTL_CFIEN; 2796 ew32(RCTL, rctl); 2797 } 2798 } 2799 2800 /** 2801 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2802 * @adapter: board private structure to initialize 2803 **/ 2804 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2805 { 2806 struct e1000_hw *hw = &adapter->hw; 2807 u32 ctrl; 2808 2809 /* disable VLAN tag insert/strip */ 2810 ctrl = er32(CTRL); 2811 ctrl &= ~E1000_CTRL_VME; 2812 ew32(CTRL, ctrl); 2813 } 2814 2815 /** 2816 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2817 * @adapter: board private structure to initialize 2818 **/ 2819 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2820 { 2821 struct e1000_hw *hw = &adapter->hw; 2822 u32 ctrl; 2823 2824 /* enable VLAN tag insert/strip */ 2825 ctrl = er32(CTRL); 2826 ctrl |= E1000_CTRL_VME; 2827 ew32(CTRL, ctrl); 2828 } 2829 2830 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2831 { 2832 struct net_device *netdev = adapter->netdev; 2833 u16 vid = adapter->hw.mng_cookie.vlan_id; 2834 u16 old_vid = adapter->mng_vlan_id; 2835 2836 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2837 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2838 adapter->mng_vlan_id = vid; 2839 } 2840 2841 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2842 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2843 } 2844 2845 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2846 { 2847 u16 vid; 2848 2849 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2850 2851 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2852 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2853 } 2854 2855 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2856 { 2857 struct e1000_hw *hw = &adapter->hw; 2858 u32 manc, manc2h, mdef, i, j; 2859 2860 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2861 return; 2862 2863 manc = er32(MANC); 2864 2865 /* enable receiving management packets to the host. this will probably 2866 * generate destination unreachable messages from the host OS, but 2867 * the packets will be handled on SMBUS 2868 */ 2869 manc |= E1000_MANC_EN_MNG2HOST; 2870 manc2h = er32(MANC2H); 2871 2872 switch (hw->mac.type) { 2873 default: 2874 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2875 break; 2876 case e1000_82574: 2877 case e1000_82583: 2878 /* Check if IPMI pass-through decision filter already exists; 2879 * if so, enable it. 2880 */ 2881 for (i = 0, j = 0; i < 8; i++) { 2882 mdef = er32(MDEF(i)); 2883 2884 /* Ignore filters with anything other than IPMI ports */ 2885 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2886 continue; 2887 2888 /* Enable this decision filter in MANC2H */ 2889 if (mdef) 2890 manc2h |= BIT(i); 2891 2892 j |= mdef; 2893 } 2894 2895 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2896 break; 2897 2898 /* Create new decision filter in an empty filter */ 2899 for (i = 0, j = 0; i < 8; i++) 2900 if (er32(MDEF(i)) == 0) { 2901 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2902 E1000_MDEF_PORT_664)); 2903 manc2h |= BIT(1); 2904 j++; 2905 break; 2906 } 2907 2908 if (!j) 2909 e_warn("Unable to create IPMI pass-through filter\n"); 2910 break; 2911 } 2912 2913 ew32(MANC2H, manc2h); 2914 ew32(MANC, manc); 2915 } 2916 2917 /** 2918 * e1000_configure_tx - Configure Transmit Unit after Reset 2919 * @adapter: board private structure 2920 * 2921 * Configure the Tx unit of the MAC after a reset. 2922 **/ 2923 static void e1000_configure_tx(struct e1000_adapter *adapter) 2924 { 2925 struct e1000_hw *hw = &adapter->hw; 2926 struct e1000_ring *tx_ring = adapter->tx_ring; 2927 u64 tdba; 2928 u32 tdlen, tctl, tarc; 2929 2930 /* Setup the HW Tx Head and Tail descriptor pointers */ 2931 tdba = tx_ring->dma; 2932 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2933 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2934 ew32(TDBAH(0), (tdba >> 32)); 2935 ew32(TDLEN(0), tdlen); 2936 ew32(TDH(0), 0); 2937 ew32(TDT(0), 0); 2938 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2939 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2940 2941 writel(0, tx_ring->head); 2942 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2943 e1000e_update_tdt_wa(tx_ring, 0); 2944 else 2945 writel(0, tx_ring->tail); 2946 2947 /* Set the Tx Interrupt Delay register */ 2948 ew32(TIDV, adapter->tx_int_delay); 2949 /* Tx irq moderation */ 2950 ew32(TADV, adapter->tx_abs_int_delay); 2951 2952 if (adapter->flags2 & FLAG2_DMA_BURST) { 2953 u32 txdctl = er32(TXDCTL(0)); 2954 2955 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2956 E1000_TXDCTL_WTHRESH); 2957 /* set up some performance related parameters to encourage the 2958 * hardware to use the bus more efficiently in bursts, depends 2959 * on the tx_int_delay to be enabled, 2960 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2961 * hthresh = 1 ==> prefetch when one or more available 2962 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2963 * BEWARE: this seems to work but should be considered first if 2964 * there are Tx hangs or other Tx related bugs 2965 */ 2966 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2967 ew32(TXDCTL(0), txdctl); 2968 } 2969 /* erratum work around: set txdctl the same for both queues */ 2970 ew32(TXDCTL(1), er32(TXDCTL(0))); 2971 2972 /* Program the Transmit Control Register */ 2973 tctl = er32(TCTL); 2974 tctl &= ~E1000_TCTL_CT; 2975 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2976 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2977 2978 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2979 tarc = er32(TARC(0)); 2980 /* set the speed mode bit, we'll clear it if we're not at 2981 * gigabit link later 2982 */ 2983 #define SPEED_MODE_BIT BIT(21) 2984 tarc |= SPEED_MODE_BIT; 2985 ew32(TARC(0), tarc); 2986 } 2987 2988 /* errata: program both queues to unweighted RR */ 2989 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2990 tarc = er32(TARC(0)); 2991 tarc |= 1; 2992 ew32(TARC(0), tarc); 2993 tarc = er32(TARC(1)); 2994 tarc |= 1; 2995 ew32(TARC(1), tarc); 2996 } 2997 2998 /* Setup Transmit Descriptor Settings for eop descriptor */ 2999 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 3000 3001 /* only set IDE if we are delaying interrupts using the timers */ 3002 if (adapter->tx_int_delay) 3003 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3004 3005 /* enable Report Status bit */ 3006 adapter->txd_cmd |= E1000_TXD_CMD_RS; 3007 3008 ew32(TCTL, tctl); 3009 3010 hw->mac.ops.config_collision_dist(hw); 3011 3012 /* SPT and KBL Si errata workaround to avoid data corruption */ 3013 if (hw->mac.type == e1000_pch_spt) { 3014 u32 reg_val; 3015 3016 reg_val = er32(IOSFPC); 3017 reg_val |= E1000_RCTL_RDMTS_HEX; 3018 ew32(IOSFPC, reg_val); 3019 3020 reg_val = er32(TARC(0)); 3021 /* SPT and KBL Si errata workaround to avoid Tx hang. 3022 * Dropping the number of outstanding requests from 3023 * 3 to 2 in order to avoid a buffer overrun. 3024 */ 3025 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3026 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3027 ew32(TARC(0), reg_val); 3028 } 3029 } 3030 3031 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3032 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3033 3034 /** 3035 * e1000_setup_rctl - configure the receive control registers 3036 * @adapter: Board private structure 3037 **/ 3038 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3039 { 3040 struct e1000_hw *hw = &adapter->hw; 3041 u32 rctl, rfctl; 3042 u32 pages = 0; 3043 3044 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3045 * If jumbo frames not set, program related MAC/PHY registers 3046 * to h/w defaults 3047 */ 3048 if (hw->mac.type >= e1000_pch2lan) { 3049 s32 ret_val; 3050 3051 if (adapter->netdev->mtu > ETH_DATA_LEN) 3052 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3053 else 3054 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3055 3056 if (ret_val) 3057 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3058 } 3059 3060 /* Program MC offset vector base */ 3061 rctl = er32(RCTL); 3062 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3063 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3064 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3065 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3066 3067 /* Do not Store bad packets */ 3068 rctl &= ~E1000_RCTL_SBP; 3069 3070 /* Enable Long Packet receive */ 3071 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3072 rctl &= ~E1000_RCTL_LPE; 3073 else 3074 rctl |= E1000_RCTL_LPE; 3075 3076 /* Some systems expect that the CRC is included in SMBUS traffic. The 3077 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3078 * host memory when this is enabled 3079 */ 3080 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3081 rctl |= E1000_RCTL_SECRC; 3082 3083 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3084 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3085 u16 phy_data; 3086 3087 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3088 phy_data &= 0xfff8; 3089 phy_data |= BIT(2); 3090 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3091 3092 e1e_rphy(hw, 22, &phy_data); 3093 phy_data &= 0x0fff; 3094 phy_data |= BIT(14); 3095 e1e_wphy(hw, 0x10, 0x2823); 3096 e1e_wphy(hw, 0x11, 0x0003); 3097 e1e_wphy(hw, 22, phy_data); 3098 } 3099 3100 /* Setup buffer sizes */ 3101 rctl &= ~E1000_RCTL_SZ_4096; 3102 rctl |= E1000_RCTL_BSEX; 3103 switch (adapter->rx_buffer_len) { 3104 case 2048: 3105 default: 3106 rctl |= E1000_RCTL_SZ_2048; 3107 rctl &= ~E1000_RCTL_BSEX; 3108 break; 3109 case 4096: 3110 rctl |= E1000_RCTL_SZ_4096; 3111 break; 3112 case 8192: 3113 rctl |= E1000_RCTL_SZ_8192; 3114 break; 3115 case 16384: 3116 rctl |= E1000_RCTL_SZ_16384; 3117 break; 3118 } 3119 3120 /* Enable Extended Status in all Receive Descriptors */ 3121 rfctl = er32(RFCTL); 3122 rfctl |= E1000_RFCTL_EXTEN; 3123 ew32(RFCTL, rfctl); 3124 3125 /* 82571 and greater support packet-split where the protocol 3126 * header is placed in skb->data and the packet data is 3127 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3128 * In the case of a non-split, skb->data is linearly filled, 3129 * followed by the page buffers. Therefore, skb->data is 3130 * sized to hold the largest protocol header. 3131 * 3132 * allocations using alloc_page take too long for regular MTU 3133 * so only enable packet split for jumbo frames 3134 * 3135 * Using pages when the page size is greater than 16k wastes 3136 * a lot of memory, since we allocate 3 pages at all times 3137 * per packet. 3138 */ 3139 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3140 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3141 adapter->rx_ps_pages = pages; 3142 else 3143 adapter->rx_ps_pages = 0; 3144 3145 if (adapter->rx_ps_pages) { 3146 u32 psrctl = 0; 3147 3148 /* Enable Packet split descriptors */ 3149 rctl |= E1000_RCTL_DTYP_PS; 3150 3151 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3152 3153 switch (adapter->rx_ps_pages) { 3154 case 3: 3155 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3156 fallthrough; 3157 case 2: 3158 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3159 fallthrough; 3160 case 1: 3161 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3162 break; 3163 } 3164 3165 ew32(PSRCTL, psrctl); 3166 } 3167 3168 /* This is useful for sniffing bad packets. */ 3169 if (adapter->netdev->features & NETIF_F_RXALL) { 3170 /* UPE and MPE will be handled by normal PROMISC logic 3171 * in e1000e_set_rx_mode 3172 */ 3173 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3174 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3175 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3176 3177 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3178 E1000_RCTL_DPF | /* Allow filtered pause */ 3179 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3180 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3181 * and that breaks VLANs. 3182 */ 3183 } 3184 3185 ew32(RCTL, rctl); 3186 /* just started the receive unit, no need to restart */ 3187 adapter->flags &= ~FLAG_RESTART_NOW; 3188 } 3189 3190 /** 3191 * e1000_configure_rx - Configure Receive Unit after Reset 3192 * @adapter: board private structure 3193 * 3194 * Configure the Rx unit of the MAC after a reset. 3195 **/ 3196 static void e1000_configure_rx(struct e1000_adapter *adapter) 3197 { 3198 struct e1000_hw *hw = &adapter->hw; 3199 struct e1000_ring *rx_ring = adapter->rx_ring; 3200 u64 rdba; 3201 u32 rdlen, rctl, rxcsum, ctrl_ext; 3202 3203 if (adapter->rx_ps_pages) { 3204 /* this is a 32 byte descriptor */ 3205 rdlen = rx_ring->count * 3206 sizeof(union e1000_rx_desc_packet_split); 3207 adapter->clean_rx = e1000_clean_rx_irq_ps; 3208 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3209 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3210 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3211 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3212 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3213 } else { 3214 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3215 adapter->clean_rx = e1000_clean_rx_irq; 3216 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3217 } 3218 3219 /* disable receives while setting up the descriptors */ 3220 rctl = er32(RCTL); 3221 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3222 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3223 e1e_flush(); 3224 usleep_range(10000, 11000); 3225 3226 if (adapter->flags2 & FLAG2_DMA_BURST) { 3227 /* set the writeback threshold (only takes effect if the RDTR 3228 * is set). set GRAN=1 and write back up to 0x4 worth, and 3229 * enable prefetching of 0x20 Rx descriptors 3230 * granularity = 01 3231 * wthresh = 04, 3232 * hthresh = 04, 3233 * pthresh = 0x20 3234 */ 3235 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3236 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3237 } 3238 3239 /* set the Receive Delay Timer Register */ 3240 ew32(RDTR, adapter->rx_int_delay); 3241 3242 /* irq moderation */ 3243 ew32(RADV, adapter->rx_abs_int_delay); 3244 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3245 e1000e_write_itr(adapter, adapter->itr); 3246 3247 ctrl_ext = er32(CTRL_EXT); 3248 /* Auto-Mask interrupts upon ICR access */ 3249 ctrl_ext |= E1000_CTRL_EXT_IAME; 3250 ew32(IAM, 0xffffffff); 3251 ew32(CTRL_EXT, ctrl_ext); 3252 e1e_flush(); 3253 3254 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3255 * the Base and Length of the Rx Descriptor Ring 3256 */ 3257 rdba = rx_ring->dma; 3258 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3259 ew32(RDBAH(0), (rdba >> 32)); 3260 ew32(RDLEN(0), rdlen); 3261 ew32(RDH(0), 0); 3262 ew32(RDT(0), 0); 3263 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3264 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3265 3266 writel(0, rx_ring->head); 3267 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3268 e1000e_update_rdt_wa(rx_ring, 0); 3269 else 3270 writel(0, rx_ring->tail); 3271 3272 /* Enable Receive Checksum Offload for TCP and UDP */ 3273 rxcsum = er32(RXCSUM); 3274 if (adapter->netdev->features & NETIF_F_RXCSUM) 3275 rxcsum |= E1000_RXCSUM_TUOFL; 3276 else 3277 rxcsum &= ~E1000_RXCSUM_TUOFL; 3278 ew32(RXCSUM, rxcsum); 3279 3280 /* With jumbo frames, excessive C-state transition latencies result 3281 * in dropped transactions. 3282 */ 3283 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3284 u32 lat = 3285 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3286 adapter->max_frame_size) * 8 / 1000; 3287 3288 if (adapter->flags & FLAG_IS_ICH) { 3289 u32 rxdctl = er32(RXDCTL(0)); 3290 3291 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3292 } 3293 3294 dev_info(&adapter->pdev->dev, 3295 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3296 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat); 3297 } else { 3298 cpu_latency_qos_update_request(&adapter->pm_qos_req, 3299 PM_QOS_DEFAULT_VALUE); 3300 } 3301 3302 /* Enable Receives */ 3303 ew32(RCTL, rctl); 3304 } 3305 3306 /** 3307 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3308 * @netdev: network interface device structure 3309 * 3310 * Writes multicast address list to the MTA hash table. 3311 * Returns: -ENOMEM on failure 3312 * 0 on no addresses written 3313 * X on writing X addresses to MTA 3314 */ 3315 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3316 { 3317 struct e1000_adapter *adapter = netdev_priv(netdev); 3318 struct e1000_hw *hw = &adapter->hw; 3319 struct netdev_hw_addr *ha; 3320 u8 *mta_list; 3321 int i; 3322 3323 if (netdev_mc_empty(netdev)) { 3324 /* nothing to program, so clear mc list */ 3325 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3326 return 0; 3327 } 3328 3329 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3330 if (!mta_list) 3331 return -ENOMEM; 3332 3333 /* update_mc_addr_list expects a packed array of only addresses. */ 3334 i = 0; 3335 netdev_for_each_mc_addr(ha, netdev) 3336 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3337 3338 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3339 kfree(mta_list); 3340 3341 return netdev_mc_count(netdev); 3342 } 3343 3344 /** 3345 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3346 * @netdev: network interface device structure 3347 * 3348 * Writes unicast address list to the RAR table. 3349 * Returns: -ENOMEM on failure/insufficient address space 3350 * 0 on no addresses written 3351 * X on writing X addresses to the RAR table 3352 **/ 3353 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3354 { 3355 struct e1000_adapter *adapter = netdev_priv(netdev); 3356 struct e1000_hw *hw = &adapter->hw; 3357 unsigned int rar_entries; 3358 int count = 0; 3359 3360 rar_entries = hw->mac.ops.rar_get_count(hw); 3361 3362 /* save a rar entry for our hardware address */ 3363 rar_entries--; 3364 3365 /* save a rar entry for the LAA workaround */ 3366 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3367 rar_entries--; 3368 3369 /* return ENOMEM indicating insufficient memory for addresses */ 3370 if (netdev_uc_count(netdev) > rar_entries) 3371 return -ENOMEM; 3372 3373 if (!netdev_uc_empty(netdev) && rar_entries) { 3374 struct netdev_hw_addr *ha; 3375 3376 /* write the addresses in reverse order to avoid write 3377 * combining 3378 */ 3379 netdev_for_each_uc_addr(ha, netdev) { 3380 int ret_val; 3381 3382 if (!rar_entries) 3383 break; 3384 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3385 if (ret_val < 0) 3386 return -ENOMEM; 3387 count++; 3388 } 3389 } 3390 3391 /* zero out the remaining RAR entries not used above */ 3392 for (; rar_entries > 0; rar_entries--) { 3393 ew32(RAH(rar_entries), 0); 3394 ew32(RAL(rar_entries), 0); 3395 } 3396 e1e_flush(); 3397 3398 return count; 3399 } 3400 3401 /** 3402 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3403 * @netdev: network interface device structure 3404 * 3405 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3406 * address list or the network interface flags are updated. This routine is 3407 * responsible for configuring the hardware for proper unicast, multicast, 3408 * promiscuous mode, and all-multi behavior. 3409 **/ 3410 static void e1000e_set_rx_mode(struct net_device *netdev) 3411 { 3412 struct e1000_adapter *adapter = netdev_priv(netdev); 3413 struct e1000_hw *hw = &adapter->hw; 3414 u32 rctl; 3415 3416 if (pm_runtime_suspended(netdev->dev.parent)) 3417 return; 3418 3419 /* Check for Promiscuous and All Multicast modes */ 3420 rctl = er32(RCTL); 3421 3422 /* clear the affected bits */ 3423 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3424 3425 if (netdev->flags & IFF_PROMISC) { 3426 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3427 /* Do not hardware filter VLANs in promisc mode */ 3428 e1000e_vlan_filter_disable(adapter); 3429 } else { 3430 int count; 3431 3432 if (netdev->flags & IFF_ALLMULTI) { 3433 rctl |= E1000_RCTL_MPE; 3434 } else { 3435 /* Write addresses to the MTA, if the attempt fails 3436 * then we should just turn on promiscuous mode so 3437 * that we can at least receive multicast traffic 3438 */ 3439 count = e1000e_write_mc_addr_list(netdev); 3440 if (count < 0) 3441 rctl |= E1000_RCTL_MPE; 3442 } 3443 e1000e_vlan_filter_enable(adapter); 3444 /* Write addresses to available RAR registers, if there is not 3445 * sufficient space to store all the addresses then enable 3446 * unicast promiscuous mode 3447 */ 3448 count = e1000e_write_uc_addr_list(netdev); 3449 if (count < 0) 3450 rctl |= E1000_RCTL_UPE; 3451 } 3452 3453 ew32(RCTL, rctl); 3454 3455 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3456 e1000e_vlan_strip_enable(adapter); 3457 else 3458 e1000e_vlan_strip_disable(adapter); 3459 } 3460 3461 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3462 { 3463 struct e1000_hw *hw = &adapter->hw; 3464 u32 mrqc, rxcsum; 3465 u32 rss_key[10]; 3466 int i; 3467 3468 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3469 for (i = 0; i < 10; i++) 3470 ew32(RSSRK(i), rss_key[i]); 3471 3472 /* Direct all traffic to queue 0 */ 3473 for (i = 0; i < 32; i++) 3474 ew32(RETA(i), 0); 3475 3476 /* Disable raw packet checksumming so that RSS hash is placed in 3477 * descriptor on writeback. 3478 */ 3479 rxcsum = er32(RXCSUM); 3480 rxcsum |= E1000_RXCSUM_PCSD; 3481 3482 ew32(RXCSUM, rxcsum); 3483 3484 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3485 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3486 E1000_MRQC_RSS_FIELD_IPV6 | 3487 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3488 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3489 3490 ew32(MRQC, mrqc); 3491 } 3492 3493 /** 3494 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3495 * @adapter: board private structure 3496 * @timinca: pointer to returned time increment attributes 3497 * 3498 * Get attributes for incrementing the System Time Register SYSTIML/H at 3499 * the default base frequency, and set the cyclecounter shift value. 3500 **/ 3501 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3502 { 3503 struct e1000_hw *hw = &adapter->hw; 3504 u32 incvalue, incperiod, shift; 3505 3506 /* Make sure clock is enabled on I217/I218/I219 before checking 3507 * the frequency 3508 */ 3509 if ((hw->mac.type >= e1000_pch_lpt) && 3510 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3511 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3512 u32 fextnvm7 = er32(FEXTNVM7); 3513 3514 if (!(fextnvm7 & BIT(0))) { 3515 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3516 e1e_flush(); 3517 } 3518 } 3519 3520 switch (hw->mac.type) { 3521 case e1000_pch2lan: 3522 /* Stable 96MHz frequency */ 3523 incperiod = INCPERIOD_96MHZ; 3524 incvalue = INCVALUE_96MHZ; 3525 shift = INCVALUE_SHIFT_96MHZ; 3526 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3527 break; 3528 case e1000_pch_lpt: 3529 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3530 /* Stable 96MHz frequency */ 3531 incperiod = INCPERIOD_96MHZ; 3532 incvalue = INCVALUE_96MHZ; 3533 shift = INCVALUE_SHIFT_96MHZ; 3534 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3535 } else { 3536 /* Stable 25MHz frequency */ 3537 incperiod = INCPERIOD_25MHZ; 3538 incvalue = INCVALUE_25MHZ; 3539 shift = INCVALUE_SHIFT_25MHZ; 3540 adapter->cc.shift = shift; 3541 } 3542 break; 3543 case e1000_pch_spt: 3544 /* Stable 24MHz frequency */ 3545 incperiod = INCPERIOD_24MHZ; 3546 incvalue = INCVALUE_24MHZ; 3547 shift = INCVALUE_SHIFT_24MHZ; 3548 adapter->cc.shift = shift; 3549 break; 3550 case e1000_pch_cnp: 3551 case e1000_pch_tgp: 3552 case e1000_pch_adp: 3553 case e1000_pch_mtp: 3554 case e1000_pch_lnp: 3555 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3556 /* Stable 24MHz frequency */ 3557 incperiod = INCPERIOD_24MHZ; 3558 incvalue = INCVALUE_24MHZ; 3559 shift = INCVALUE_SHIFT_24MHZ; 3560 adapter->cc.shift = shift; 3561 } else { 3562 /* Stable 38400KHz frequency */ 3563 incperiod = INCPERIOD_38400KHZ; 3564 incvalue = INCVALUE_38400KHZ; 3565 shift = INCVALUE_SHIFT_38400KHZ; 3566 adapter->cc.shift = shift; 3567 } 3568 break; 3569 case e1000_82574: 3570 case e1000_82583: 3571 /* Stable 25MHz frequency */ 3572 incperiod = INCPERIOD_25MHZ; 3573 incvalue = INCVALUE_25MHZ; 3574 shift = INCVALUE_SHIFT_25MHZ; 3575 adapter->cc.shift = shift; 3576 break; 3577 default: 3578 return -EINVAL; 3579 } 3580 3581 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3582 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3583 3584 return 0; 3585 } 3586 3587 /** 3588 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3589 * @adapter: board private structure 3590 * @config: timestamp configuration 3591 * 3592 * Outgoing time stamping can be enabled and disabled. Play nice and 3593 * disable it when requested, although it shouldn't cause any overhead 3594 * when no packet needs it. At most one packet in the queue may be 3595 * marked for time stamping, otherwise it would be impossible to tell 3596 * for sure to which packet the hardware time stamp belongs. 3597 * 3598 * Incoming time stamping has to be configured via the hardware filters. 3599 * Not all combinations are supported, in particular event type has to be 3600 * specified. Matching the kind of event packet is not supported, with the 3601 * exception of "all V2 events regardless of level 2 or 4". 3602 **/ 3603 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3604 struct hwtstamp_config *config) 3605 { 3606 struct e1000_hw *hw = &adapter->hw; 3607 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3608 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3609 u32 rxmtrl = 0; 3610 u16 rxudp = 0; 3611 bool is_l4 = false; 3612 bool is_l2 = false; 3613 u32 regval; 3614 3615 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3616 return -EINVAL; 3617 3618 /* flags reserved for future extensions - must be zero */ 3619 if (config->flags) 3620 return -EINVAL; 3621 3622 switch (config->tx_type) { 3623 case HWTSTAMP_TX_OFF: 3624 tsync_tx_ctl = 0; 3625 break; 3626 case HWTSTAMP_TX_ON: 3627 break; 3628 default: 3629 return -ERANGE; 3630 } 3631 3632 switch (config->rx_filter) { 3633 case HWTSTAMP_FILTER_NONE: 3634 tsync_rx_ctl = 0; 3635 break; 3636 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3637 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3638 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3639 is_l4 = true; 3640 break; 3641 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3642 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3643 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3644 is_l4 = true; 3645 break; 3646 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3647 /* Also time stamps V2 L2 Path Delay Request/Response */ 3648 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3649 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3650 is_l2 = true; 3651 break; 3652 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3653 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3654 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3655 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3656 is_l2 = true; 3657 break; 3658 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3659 /* Hardware cannot filter just V2 L4 Sync messages */ 3660 fallthrough; 3661 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3662 /* Also time stamps V2 Path Delay Request/Response. */ 3663 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3664 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3665 is_l2 = true; 3666 is_l4 = true; 3667 break; 3668 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3669 /* Hardware cannot filter just V2 L4 Delay Request messages */ 3670 fallthrough; 3671 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3672 /* Also time stamps V2 Path Delay Request/Response. */ 3673 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3674 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3675 is_l2 = true; 3676 is_l4 = true; 3677 break; 3678 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3679 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3680 /* Hardware cannot filter just V2 L4 or L2 Event messages */ 3681 fallthrough; 3682 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3683 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3684 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3685 is_l2 = true; 3686 is_l4 = true; 3687 break; 3688 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3689 /* For V1, the hardware can only filter Sync messages or 3690 * Delay Request messages but not both so fall-through to 3691 * time stamp all packets. 3692 */ 3693 fallthrough; 3694 case HWTSTAMP_FILTER_NTP_ALL: 3695 case HWTSTAMP_FILTER_ALL: 3696 is_l2 = true; 3697 is_l4 = true; 3698 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3699 config->rx_filter = HWTSTAMP_FILTER_ALL; 3700 break; 3701 default: 3702 return -ERANGE; 3703 } 3704 3705 adapter->hwtstamp_config = *config; 3706 3707 /* enable/disable Tx h/w time stamping */ 3708 regval = er32(TSYNCTXCTL); 3709 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3710 regval |= tsync_tx_ctl; 3711 ew32(TSYNCTXCTL, regval); 3712 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3713 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3714 e_err("Timesync Tx Control register not set as expected\n"); 3715 return -EAGAIN; 3716 } 3717 3718 /* enable/disable Rx h/w time stamping */ 3719 regval = er32(TSYNCRXCTL); 3720 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3721 regval |= tsync_rx_ctl; 3722 ew32(TSYNCRXCTL, regval); 3723 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3724 E1000_TSYNCRXCTL_TYPE_MASK)) != 3725 (regval & (E1000_TSYNCRXCTL_ENABLED | 3726 E1000_TSYNCRXCTL_TYPE_MASK))) { 3727 e_err("Timesync Rx Control register not set as expected\n"); 3728 return -EAGAIN; 3729 } 3730 3731 /* L2: define ethertype filter for time stamped packets */ 3732 if (is_l2) 3733 rxmtrl |= ETH_P_1588; 3734 3735 /* define which PTP packets get time stamped */ 3736 ew32(RXMTRL, rxmtrl); 3737 3738 /* Filter by destination port */ 3739 if (is_l4) { 3740 rxudp = PTP_EV_PORT; 3741 cpu_to_be16s(&rxudp); 3742 } 3743 ew32(RXUDP, rxudp); 3744 3745 e1e_flush(); 3746 3747 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3748 er32(RXSTMPH); 3749 er32(TXSTMPH); 3750 3751 return 0; 3752 } 3753 3754 /** 3755 * e1000_configure - configure the hardware for Rx and Tx 3756 * @adapter: private board structure 3757 **/ 3758 static void e1000_configure(struct e1000_adapter *adapter) 3759 { 3760 struct e1000_ring *rx_ring = adapter->rx_ring; 3761 3762 e1000e_set_rx_mode(adapter->netdev); 3763 3764 e1000_restore_vlan(adapter); 3765 e1000_init_manageability_pt(adapter); 3766 3767 e1000_configure_tx(adapter); 3768 3769 if (adapter->netdev->features & NETIF_F_RXHASH) 3770 e1000e_setup_rss_hash(adapter); 3771 e1000_setup_rctl(adapter); 3772 e1000_configure_rx(adapter); 3773 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3774 } 3775 3776 /** 3777 * e1000e_power_up_phy - restore link in case the phy was powered down 3778 * @adapter: address of board private structure 3779 * 3780 * The phy may be powered down to save power and turn off link when the 3781 * driver is unloaded and wake on lan is not enabled (among others) 3782 * *** this routine MUST be followed by a call to e1000e_reset *** 3783 **/ 3784 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3785 { 3786 if (adapter->hw.phy.ops.power_up) 3787 adapter->hw.phy.ops.power_up(&adapter->hw); 3788 3789 adapter->hw.mac.ops.setup_link(&adapter->hw); 3790 } 3791 3792 /** 3793 * e1000_power_down_phy - Power down the PHY 3794 * @adapter: board private structure 3795 * 3796 * Power down the PHY so no link is implied when interface is down. 3797 * The PHY cannot be powered down if management or WoL is active. 3798 */ 3799 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3800 { 3801 if (adapter->hw.phy.ops.power_down) 3802 adapter->hw.phy.ops.power_down(&adapter->hw); 3803 } 3804 3805 /** 3806 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3807 * @adapter: board private structure 3808 * 3809 * We want to clear all pending descriptors from the TX ring. 3810 * zeroing happens when the HW reads the regs. We assign the ring itself as 3811 * the data of the next descriptor. We don't care about the data we are about 3812 * to reset the HW. 3813 */ 3814 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3815 { 3816 struct e1000_hw *hw = &adapter->hw; 3817 struct e1000_ring *tx_ring = adapter->tx_ring; 3818 struct e1000_tx_desc *tx_desc = NULL; 3819 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3820 u16 size = 512; 3821 3822 tctl = er32(TCTL); 3823 ew32(TCTL, tctl | E1000_TCTL_EN); 3824 tdt = er32(TDT(0)); 3825 BUG_ON(tdt != tx_ring->next_to_use); 3826 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3827 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma); 3828 3829 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3830 tx_desc->upper.data = 0; 3831 /* flush descriptors to memory before notifying the HW */ 3832 wmb(); 3833 tx_ring->next_to_use++; 3834 if (tx_ring->next_to_use == tx_ring->count) 3835 tx_ring->next_to_use = 0; 3836 ew32(TDT(0), tx_ring->next_to_use); 3837 usleep_range(200, 250); 3838 } 3839 3840 /** 3841 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3842 * @adapter: board private structure 3843 * 3844 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3845 */ 3846 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3847 { 3848 u32 rctl, rxdctl; 3849 struct e1000_hw *hw = &adapter->hw; 3850 3851 rctl = er32(RCTL); 3852 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3853 e1e_flush(); 3854 usleep_range(100, 150); 3855 3856 rxdctl = er32(RXDCTL(0)); 3857 /* zero the lower 14 bits (prefetch and host thresholds) */ 3858 rxdctl &= 0xffffc000; 3859 3860 /* update thresholds: prefetch threshold to 31, host threshold to 1 3861 * and make sure the granularity is "descriptors" and not "cache lines" 3862 */ 3863 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3864 3865 ew32(RXDCTL(0), rxdctl); 3866 /* momentarily enable the RX ring for the changes to take effect */ 3867 ew32(RCTL, rctl | E1000_RCTL_EN); 3868 e1e_flush(); 3869 usleep_range(100, 150); 3870 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3871 } 3872 3873 /** 3874 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3875 * @adapter: board private structure 3876 * 3877 * In i219, the descriptor rings must be emptied before resetting the HW 3878 * or before changing the device state to D3 during runtime (runtime PM). 3879 * 3880 * Failure to do this will cause the HW to enter a unit hang state which can 3881 * only be released by PCI reset on the device 3882 * 3883 */ 3884 3885 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3886 { 3887 u16 hang_state; 3888 u32 fext_nvm11, tdlen; 3889 struct e1000_hw *hw = &adapter->hw; 3890 3891 /* First, disable MULR fix in FEXTNVM11 */ 3892 fext_nvm11 = er32(FEXTNVM11); 3893 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3894 ew32(FEXTNVM11, fext_nvm11); 3895 /* do nothing if we're not in faulty state, or if the queue is empty */ 3896 tdlen = er32(TDLEN(0)); 3897 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3898 &hang_state); 3899 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3900 return; 3901 e1000_flush_tx_ring(adapter); 3902 /* recheck, maybe the fault is caused by the rx ring */ 3903 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3904 &hang_state); 3905 if (hang_state & FLUSH_DESC_REQUIRED) 3906 e1000_flush_rx_ring(adapter); 3907 } 3908 3909 /** 3910 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3911 * @adapter: board private structure 3912 * 3913 * When the MAC is reset, all hardware bits for timesync will be reset to the 3914 * default values. This function will restore the settings last in place. 3915 * Since the clock SYSTIME registers are reset, we will simply restore the 3916 * cyclecounter to the kernel real clock time. 3917 **/ 3918 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3919 { 3920 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3921 struct e1000_hw *hw = &adapter->hw; 3922 unsigned long flags; 3923 u32 timinca; 3924 s32 ret_val; 3925 3926 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3927 return; 3928 3929 if (info->adjfreq) { 3930 /* restore the previous ptp frequency delta */ 3931 ret_val = info->adjfreq(info, adapter->ptp_delta); 3932 } else { 3933 /* set the default base frequency if no adjustment possible */ 3934 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3935 if (!ret_val) 3936 ew32(TIMINCA, timinca); 3937 } 3938 3939 if (ret_val) { 3940 dev_warn(&adapter->pdev->dev, 3941 "Failed to restore TIMINCA clock rate delta: %d\n", 3942 ret_val); 3943 return; 3944 } 3945 3946 /* reset the systim ns time counter */ 3947 spin_lock_irqsave(&adapter->systim_lock, flags); 3948 timecounter_init(&adapter->tc, &adapter->cc, 3949 ktime_to_ns(ktime_get_real())); 3950 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3951 3952 /* restore the previous hwtstamp configuration settings */ 3953 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3954 } 3955 3956 /** 3957 * e1000e_reset - bring the hardware into a known good state 3958 * @adapter: board private structure 3959 * 3960 * This function boots the hardware and enables some settings that 3961 * require a configuration cycle of the hardware - those cannot be 3962 * set/changed during runtime. After reset the device needs to be 3963 * properly configured for Rx, Tx etc. 3964 */ 3965 void e1000e_reset(struct e1000_adapter *adapter) 3966 { 3967 struct e1000_mac_info *mac = &adapter->hw.mac; 3968 struct e1000_fc_info *fc = &adapter->hw.fc; 3969 struct e1000_hw *hw = &adapter->hw; 3970 u32 tx_space, min_tx_space, min_rx_space; 3971 u32 pba = adapter->pba; 3972 u16 hwm; 3973 3974 /* reset Packet Buffer Allocation to default */ 3975 ew32(PBA, pba); 3976 3977 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3978 /* To maintain wire speed transmits, the Tx FIFO should be 3979 * large enough to accommodate two full transmit packets, 3980 * rounded up to the next 1KB and expressed in KB. Likewise, 3981 * the Rx FIFO should be large enough to accommodate at least 3982 * one full receive packet and is similarly rounded up and 3983 * expressed in KB. 3984 */ 3985 pba = er32(PBA); 3986 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3987 tx_space = pba >> 16; 3988 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3989 pba &= 0xffff; 3990 /* the Tx fifo also stores 16 bytes of information about the Tx 3991 * but don't include ethernet FCS because hardware appends it 3992 */ 3993 min_tx_space = (adapter->max_frame_size + 3994 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 3995 min_tx_space = ALIGN(min_tx_space, 1024); 3996 min_tx_space >>= 10; 3997 /* software strips receive CRC, so leave room for it */ 3998 min_rx_space = adapter->max_frame_size; 3999 min_rx_space = ALIGN(min_rx_space, 1024); 4000 min_rx_space >>= 10; 4001 4002 /* If current Tx allocation is less than the min Tx FIFO size, 4003 * and the min Tx FIFO size is less than the current Rx FIFO 4004 * allocation, take space away from current Rx allocation 4005 */ 4006 if ((tx_space < min_tx_space) && 4007 ((min_tx_space - tx_space) < pba)) { 4008 pba -= min_tx_space - tx_space; 4009 4010 /* if short on Rx space, Rx wins and must trump Tx 4011 * adjustment 4012 */ 4013 if (pba < min_rx_space) 4014 pba = min_rx_space; 4015 } 4016 4017 ew32(PBA, pba); 4018 } 4019 4020 /* flow control settings 4021 * 4022 * The high water mark must be low enough to fit one full frame 4023 * (or the size used for early receive) above it in the Rx FIFO. 4024 * Set it to the lower of: 4025 * - 90% of the Rx FIFO size, and 4026 * - the full Rx FIFO size minus one full frame 4027 */ 4028 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4029 fc->pause_time = 0xFFFF; 4030 else 4031 fc->pause_time = E1000_FC_PAUSE_TIME; 4032 fc->send_xon = true; 4033 fc->current_mode = fc->requested_mode; 4034 4035 switch (hw->mac.type) { 4036 case e1000_ich9lan: 4037 case e1000_ich10lan: 4038 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4039 pba = 14; 4040 ew32(PBA, pba); 4041 fc->high_water = 0x2800; 4042 fc->low_water = fc->high_water - 8; 4043 break; 4044 } 4045 fallthrough; 4046 default: 4047 hwm = min(((pba << 10) * 9 / 10), 4048 ((pba << 10) - adapter->max_frame_size)); 4049 4050 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4051 fc->low_water = fc->high_water - 8; 4052 break; 4053 case e1000_pchlan: 4054 /* Workaround PCH LOM adapter hangs with certain network 4055 * loads. If hangs persist, try disabling Tx flow control. 4056 */ 4057 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4058 fc->high_water = 0x3500; 4059 fc->low_water = 0x1500; 4060 } else { 4061 fc->high_water = 0x5000; 4062 fc->low_water = 0x3000; 4063 } 4064 fc->refresh_time = 0x1000; 4065 break; 4066 case e1000_pch2lan: 4067 case e1000_pch_lpt: 4068 case e1000_pch_spt: 4069 case e1000_pch_cnp: 4070 case e1000_pch_tgp: 4071 case e1000_pch_adp: 4072 case e1000_pch_mtp: 4073 case e1000_pch_lnp: 4074 fc->refresh_time = 0xFFFF; 4075 fc->pause_time = 0xFFFF; 4076 4077 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4078 fc->high_water = 0x05C20; 4079 fc->low_water = 0x05048; 4080 break; 4081 } 4082 4083 pba = 14; 4084 ew32(PBA, pba); 4085 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4086 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4087 break; 4088 } 4089 4090 /* Alignment of Tx data is on an arbitrary byte boundary with the 4091 * maximum size per Tx descriptor limited only to the transmit 4092 * allocation of the packet buffer minus 96 bytes with an upper 4093 * limit of 24KB due to receive synchronization limitations. 4094 */ 4095 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4096 24 << 10); 4097 4098 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4099 * fit in receive buffer. 4100 */ 4101 if (adapter->itr_setting & 0x3) { 4102 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4103 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4104 dev_info(&adapter->pdev->dev, 4105 "Interrupt Throttle Rate off\n"); 4106 adapter->flags2 |= FLAG2_DISABLE_AIM; 4107 e1000e_write_itr(adapter, 0); 4108 } 4109 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4110 dev_info(&adapter->pdev->dev, 4111 "Interrupt Throttle Rate on\n"); 4112 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4113 adapter->itr = 20000; 4114 e1000e_write_itr(adapter, adapter->itr); 4115 } 4116 } 4117 4118 if (hw->mac.type >= e1000_pch_spt) 4119 e1000_flush_desc_rings(adapter); 4120 /* Allow time for pending master requests to run */ 4121 mac->ops.reset_hw(hw); 4122 4123 /* For parts with AMT enabled, let the firmware know 4124 * that the network interface is in control 4125 */ 4126 if (adapter->flags & FLAG_HAS_AMT) 4127 e1000e_get_hw_control(adapter); 4128 4129 ew32(WUC, 0); 4130 4131 if (mac->ops.init_hw(hw)) 4132 e_err("Hardware Error\n"); 4133 4134 e1000_update_mng_vlan(adapter); 4135 4136 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4137 ew32(VET, ETH_P_8021Q); 4138 4139 e1000e_reset_adaptive(hw); 4140 4141 /* restore systim and hwtstamp settings */ 4142 e1000e_systim_reset(adapter); 4143 4144 /* Set EEE advertisement as appropriate */ 4145 if (adapter->flags2 & FLAG2_HAS_EEE) { 4146 s32 ret_val; 4147 u16 adv_addr; 4148 4149 switch (hw->phy.type) { 4150 case e1000_phy_82579: 4151 adv_addr = I82579_EEE_ADVERTISEMENT; 4152 break; 4153 case e1000_phy_i217: 4154 adv_addr = I217_EEE_ADVERTISEMENT; 4155 break; 4156 default: 4157 dev_err(&adapter->pdev->dev, 4158 "Invalid PHY type setting EEE advertisement\n"); 4159 return; 4160 } 4161 4162 ret_val = hw->phy.ops.acquire(hw); 4163 if (ret_val) { 4164 dev_err(&adapter->pdev->dev, 4165 "EEE advertisement - unable to acquire PHY\n"); 4166 return; 4167 } 4168 4169 e1000_write_emi_reg_locked(hw, adv_addr, 4170 hw->dev_spec.ich8lan.eee_disable ? 4171 0 : adapter->eee_advert); 4172 4173 hw->phy.ops.release(hw); 4174 } 4175 4176 if (!netif_running(adapter->netdev) && 4177 !test_bit(__E1000_TESTING, &adapter->state)) 4178 e1000_power_down_phy(adapter); 4179 4180 e1000_get_phy_info(hw); 4181 4182 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4183 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4184 u16 phy_data = 0; 4185 /* speed up time to link by disabling smart power down, ignore 4186 * the return value of this function because there is nothing 4187 * different we would do if it failed 4188 */ 4189 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4190 phy_data &= ~IGP02E1000_PM_SPD; 4191 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4192 } 4193 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4194 u32 reg; 4195 4196 /* Fextnvm7 @ 0xe4[2] = 1 */ 4197 reg = er32(FEXTNVM7); 4198 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4199 ew32(FEXTNVM7, reg); 4200 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4201 reg = er32(FEXTNVM9); 4202 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4203 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4204 ew32(FEXTNVM9, reg); 4205 } 4206 4207 } 4208 4209 /** 4210 * e1000e_trigger_lsc - trigger an LSC interrupt 4211 * @adapter: 4212 * 4213 * Fire a link status change interrupt to start the watchdog. 4214 **/ 4215 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4216 { 4217 struct e1000_hw *hw = &adapter->hw; 4218 4219 if (adapter->msix_entries) 4220 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4221 else 4222 ew32(ICS, E1000_ICS_LSC); 4223 } 4224 4225 void e1000e_up(struct e1000_adapter *adapter) 4226 { 4227 /* hardware has been reset, we need to reload some things */ 4228 e1000_configure(adapter); 4229 4230 clear_bit(__E1000_DOWN, &adapter->state); 4231 4232 if (adapter->msix_entries) 4233 e1000_configure_msix(adapter); 4234 e1000_irq_enable(adapter); 4235 4236 /* Tx queue started by watchdog timer when link is up */ 4237 4238 e1000e_trigger_lsc(adapter); 4239 } 4240 4241 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4242 { 4243 struct e1000_hw *hw = &adapter->hw; 4244 4245 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4246 return; 4247 4248 /* flush pending descriptor writebacks to memory */ 4249 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4250 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4251 4252 /* execute the writes immediately */ 4253 e1e_flush(); 4254 4255 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4256 * write is successful 4257 */ 4258 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4259 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4260 4261 /* execute the writes immediately */ 4262 e1e_flush(); 4263 } 4264 4265 static void e1000e_update_stats(struct e1000_adapter *adapter); 4266 4267 /** 4268 * e1000e_down - quiesce the device and optionally reset the hardware 4269 * @adapter: board private structure 4270 * @reset: boolean flag to reset the hardware or not 4271 */ 4272 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4273 { 4274 struct net_device *netdev = adapter->netdev; 4275 struct e1000_hw *hw = &adapter->hw; 4276 u32 tctl, rctl; 4277 4278 /* signal that we're down so the interrupt handler does not 4279 * reschedule our watchdog timer 4280 */ 4281 set_bit(__E1000_DOWN, &adapter->state); 4282 4283 netif_carrier_off(netdev); 4284 4285 /* disable receives in the hardware */ 4286 rctl = er32(RCTL); 4287 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4288 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4289 /* flush and sleep below */ 4290 4291 netif_stop_queue(netdev); 4292 4293 /* disable transmits in the hardware */ 4294 tctl = er32(TCTL); 4295 tctl &= ~E1000_TCTL_EN; 4296 ew32(TCTL, tctl); 4297 4298 /* flush both disables and wait for them to finish */ 4299 e1e_flush(); 4300 usleep_range(10000, 11000); 4301 4302 e1000_irq_disable(adapter); 4303 4304 napi_synchronize(&adapter->napi); 4305 4306 del_timer_sync(&adapter->watchdog_timer); 4307 del_timer_sync(&adapter->phy_info_timer); 4308 4309 spin_lock(&adapter->stats64_lock); 4310 e1000e_update_stats(adapter); 4311 spin_unlock(&adapter->stats64_lock); 4312 4313 e1000e_flush_descriptors(adapter); 4314 4315 adapter->link_speed = 0; 4316 adapter->link_duplex = 0; 4317 4318 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4319 if ((hw->mac.type >= e1000_pch2lan) && 4320 (adapter->netdev->mtu > ETH_DATA_LEN) && 4321 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4322 e_dbg("failed to disable jumbo frame workaround mode\n"); 4323 4324 if (!pci_channel_offline(adapter->pdev)) { 4325 if (reset) 4326 e1000e_reset(adapter); 4327 else if (hw->mac.type >= e1000_pch_spt) 4328 e1000_flush_desc_rings(adapter); 4329 } 4330 e1000_clean_tx_ring(adapter->tx_ring); 4331 e1000_clean_rx_ring(adapter->rx_ring); 4332 } 4333 4334 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4335 { 4336 might_sleep(); 4337 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4338 usleep_range(1000, 1100); 4339 e1000e_down(adapter, true); 4340 e1000e_up(adapter); 4341 clear_bit(__E1000_RESETTING, &adapter->state); 4342 } 4343 4344 /** 4345 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4346 * @hw: pointer to the HW structure 4347 * @systim: PHC time value read, sanitized and returned 4348 * @sts: structure to hold system time before and after reading SYSTIML, 4349 * may be NULL 4350 * 4351 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4352 * check to see that the time is incrementing at a reasonable 4353 * rate and is a multiple of incvalue. 4354 **/ 4355 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4356 struct ptp_system_timestamp *sts) 4357 { 4358 u64 time_delta, rem, temp; 4359 u64 systim_next; 4360 u32 incvalue; 4361 int i; 4362 4363 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4364 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4365 /* latch SYSTIMH on read of SYSTIML */ 4366 ptp_read_system_prets(sts); 4367 systim_next = (u64)er32(SYSTIML); 4368 ptp_read_system_postts(sts); 4369 systim_next |= (u64)er32(SYSTIMH) << 32; 4370 4371 time_delta = systim_next - systim; 4372 temp = time_delta; 4373 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4374 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4375 4376 systim = systim_next; 4377 4378 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4379 break; 4380 } 4381 4382 return systim; 4383 } 4384 4385 /** 4386 * e1000e_read_systim - read SYSTIM register 4387 * @adapter: board private structure 4388 * @sts: structure which will contain system time before and after reading 4389 * SYSTIML, may be NULL 4390 **/ 4391 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4392 struct ptp_system_timestamp *sts) 4393 { 4394 struct e1000_hw *hw = &adapter->hw; 4395 u32 systimel, systimel_2, systimeh; 4396 u64 systim; 4397 /* SYSTIMH latching upon SYSTIML read does not work well. 4398 * This means that if SYSTIML overflows after we read it but before 4399 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4400 * will experience a huge non linear increment in the systime value 4401 * to fix that we test for overflow and if true, we re-read systime. 4402 */ 4403 ptp_read_system_prets(sts); 4404 systimel = er32(SYSTIML); 4405 ptp_read_system_postts(sts); 4406 systimeh = er32(SYSTIMH); 4407 /* Is systimel is so large that overflow is possible? */ 4408 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4409 ptp_read_system_prets(sts); 4410 systimel_2 = er32(SYSTIML); 4411 ptp_read_system_postts(sts); 4412 if (systimel > systimel_2) { 4413 /* There was an overflow, read again SYSTIMH, and use 4414 * systimel_2 4415 */ 4416 systimeh = er32(SYSTIMH); 4417 systimel = systimel_2; 4418 } 4419 } 4420 systim = (u64)systimel; 4421 systim |= (u64)systimeh << 32; 4422 4423 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4424 systim = e1000e_sanitize_systim(hw, systim, sts); 4425 4426 return systim; 4427 } 4428 4429 /** 4430 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4431 * @cc: cyclecounter structure 4432 **/ 4433 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4434 { 4435 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4436 cc); 4437 4438 return e1000e_read_systim(adapter, NULL); 4439 } 4440 4441 /** 4442 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4443 * @adapter: board private structure to initialize 4444 * 4445 * e1000_sw_init initializes the Adapter private data structure. 4446 * Fields are initialized based on PCI device information and 4447 * OS network device settings (MTU size). 4448 **/ 4449 static int e1000_sw_init(struct e1000_adapter *adapter) 4450 { 4451 struct net_device *netdev = adapter->netdev; 4452 4453 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4454 adapter->rx_ps_bsize0 = 128; 4455 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4456 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4457 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4458 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4459 4460 spin_lock_init(&adapter->stats64_lock); 4461 4462 e1000e_set_interrupt_capability(adapter); 4463 4464 if (e1000_alloc_queues(adapter)) 4465 return -ENOMEM; 4466 4467 /* Setup hardware time stamping cyclecounter */ 4468 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4469 adapter->cc.read = e1000e_cyclecounter_read; 4470 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4471 adapter->cc.mult = 1; 4472 /* cc.shift set in e1000e_get_base_tininca() */ 4473 4474 spin_lock_init(&adapter->systim_lock); 4475 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4476 } 4477 4478 /* Explicitly disable IRQ since the NIC can be in any state. */ 4479 e1000_irq_disable(adapter); 4480 4481 set_bit(__E1000_DOWN, &adapter->state); 4482 return 0; 4483 } 4484 4485 /** 4486 * e1000_intr_msi_test - Interrupt Handler 4487 * @irq: interrupt number 4488 * @data: pointer to a network interface device structure 4489 **/ 4490 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4491 { 4492 struct net_device *netdev = data; 4493 struct e1000_adapter *adapter = netdev_priv(netdev); 4494 struct e1000_hw *hw = &adapter->hw; 4495 u32 icr = er32(ICR); 4496 4497 e_dbg("icr is %08X\n", icr); 4498 if (icr & E1000_ICR_RXSEQ) { 4499 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4500 /* Force memory writes to complete before acknowledging the 4501 * interrupt is handled. 4502 */ 4503 wmb(); 4504 } 4505 4506 return IRQ_HANDLED; 4507 } 4508 4509 /** 4510 * e1000_test_msi_interrupt - Returns 0 for successful test 4511 * @adapter: board private struct 4512 * 4513 * code flow taken from tg3.c 4514 **/ 4515 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4516 { 4517 struct net_device *netdev = adapter->netdev; 4518 struct e1000_hw *hw = &adapter->hw; 4519 int err; 4520 4521 /* poll_enable hasn't been called yet, so don't need disable */ 4522 /* clear any pending events */ 4523 er32(ICR); 4524 4525 /* free the real vector and request a test handler */ 4526 e1000_free_irq(adapter); 4527 e1000e_reset_interrupt_capability(adapter); 4528 4529 /* Assume that the test fails, if it succeeds then the test 4530 * MSI irq handler will unset this flag 4531 */ 4532 adapter->flags |= FLAG_MSI_TEST_FAILED; 4533 4534 err = pci_enable_msi(adapter->pdev); 4535 if (err) 4536 goto msi_test_failed; 4537 4538 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4539 netdev->name, netdev); 4540 if (err) { 4541 pci_disable_msi(adapter->pdev); 4542 goto msi_test_failed; 4543 } 4544 4545 /* Force memory writes to complete before enabling and firing an 4546 * interrupt. 4547 */ 4548 wmb(); 4549 4550 e1000_irq_enable(adapter); 4551 4552 /* fire an unusual interrupt on the test handler */ 4553 ew32(ICS, E1000_ICS_RXSEQ); 4554 e1e_flush(); 4555 msleep(100); 4556 4557 e1000_irq_disable(adapter); 4558 4559 rmb(); /* read flags after interrupt has been fired */ 4560 4561 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4562 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4563 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4564 } else { 4565 e_dbg("MSI interrupt test succeeded!\n"); 4566 } 4567 4568 free_irq(adapter->pdev->irq, netdev); 4569 pci_disable_msi(adapter->pdev); 4570 4571 msi_test_failed: 4572 e1000e_set_interrupt_capability(adapter); 4573 return e1000_request_irq(adapter); 4574 } 4575 4576 /** 4577 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4578 * @adapter: board private struct 4579 * 4580 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4581 **/ 4582 static int e1000_test_msi(struct e1000_adapter *adapter) 4583 { 4584 int err; 4585 u16 pci_cmd; 4586 4587 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4588 return 0; 4589 4590 /* disable SERR in case the MSI write causes a master abort */ 4591 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4592 if (pci_cmd & PCI_COMMAND_SERR) 4593 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4594 pci_cmd & ~PCI_COMMAND_SERR); 4595 4596 err = e1000_test_msi_interrupt(adapter); 4597 4598 /* re-enable SERR */ 4599 if (pci_cmd & PCI_COMMAND_SERR) { 4600 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4601 pci_cmd |= PCI_COMMAND_SERR; 4602 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4603 } 4604 4605 return err; 4606 } 4607 4608 /** 4609 * e1000e_open - Called when a network interface is made active 4610 * @netdev: network interface device structure 4611 * 4612 * Returns 0 on success, negative value on failure 4613 * 4614 * The open entry point is called when a network interface is made 4615 * active by the system (IFF_UP). At this point all resources needed 4616 * for transmit and receive operations are allocated, the interrupt 4617 * handler is registered with the OS, the watchdog timer is started, 4618 * and the stack is notified that the interface is ready. 4619 **/ 4620 int e1000e_open(struct net_device *netdev) 4621 { 4622 struct e1000_adapter *adapter = netdev_priv(netdev); 4623 struct e1000_hw *hw = &adapter->hw; 4624 struct pci_dev *pdev = adapter->pdev; 4625 int err; 4626 4627 /* disallow open during test */ 4628 if (test_bit(__E1000_TESTING, &adapter->state)) 4629 return -EBUSY; 4630 4631 pm_runtime_get_sync(&pdev->dev); 4632 4633 netif_carrier_off(netdev); 4634 netif_stop_queue(netdev); 4635 4636 /* allocate transmit descriptors */ 4637 err = e1000e_setup_tx_resources(adapter->tx_ring); 4638 if (err) 4639 goto err_setup_tx; 4640 4641 /* allocate receive descriptors */ 4642 err = e1000e_setup_rx_resources(adapter->rx_ring); 4643 if (err) 4644 goto err_setup_rx; 4645 4646 /* If AMT is enabled, let the firmware know that the network 4647 * interface is now open and reset the part to a known state. 4648 */ 4649 if (adapter->flags & FLAG_HAS_AMT) { 4650 e1000e_get_hw_control(adapter); 4651 e1000e_reset(adapter); 4652 } 4653 4654 e1000e_power_up_phy(adapter); 4655 4656 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4657 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4658 e1000_update_mng_vlan(adapter); 4659 4660 /* DMA latency requirement to workaround jumbo issue */ 4661 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE); 4662 4663 /* before we allocate an interrupt, we must be ready to handle it. 4664 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4665 * as soon as we call pci_request_irq, so we have to setup our 4666 * clean_rx handler before we do so. 4667 */ 4668 e1000_configure(adapter); 4669 4670 err = e1000_request_irq(adapter); 4671 if (err) 4672 goto err_req_irq; 4673 4674 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4675 * ignore e1000e MSI messages, which means we need to test our MSI 4676 * interrupt now 4677 */ 4678 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4679 err = e1000_test_msi(adapter); 4680 if (err) { 4681 e_err("Interrupt allocation failed\n"); 4682 goto err_req_irq; 4683 } 4684 } 4685 4686 /* From here on the code is the same as e1000e_up() */ 4687 clear_bit(__E1000_DOWN, &adapter->state); 4688 4689 napi_enable(&adapter->napi); 4690 4691 e1000_irq_enable(adapter); 4692 4693 adapter->tx_hang_recheck = false; 4694 4695 hw->mac.get_link_status = true; 4696 pm_runtime_put(&pdev->dev); 4697 4698 e1000e_trigger_lsc(adapter); 4699 4700 return 0; 4701 4702 err_req_irq: 4703 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4704 e1000e_release_hw_control(adapter); 4705 e1000_power_down_phy(adapter); 4706 e1000e_free_rx_resources(adapter->rx_ring); 4707 err_setup_rx: 4708 e1000e_free_tx_resources(adapter->tx_ring); 4709 err_setup_tx: 4710 e1000e_reset(adapter); 4711 pm_runtime_put_sync(&pdev->dev); 4712 4713 return err; 4714 } 4715 4716 /** 4717 * e1000e_close - Disables a network interface 4718 * @netdev: network interface device structure 4719 * 4720 * Returns 0, this is not allowed to fail 4721 * 4722 * The close entry point is called when an interface is de-activated 4723 * by the OS. The hardware is still under the drivers control, but 4724 * needs to be disabled. A global MAC reset is issued to stop the 4725 * hardware, and all transmit and receive resources are freed. 4726 **/ 4727 int e1000e_close(struct net_device *netdev) 4728 { 4729 struct e1000_adapter *adapter = netdev_priv(netdev); 4730 struct pci_dev *pdev = adapter->pdev; 4731 int count = E1000_CHECK_RESET_COUNT; 4732 4733 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4734 usleep_range(10000, 11000); 4735 4736 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4737 4738 pm_runtime_get_sync(&pdev->dev); 4739 4740 if (netif_device_present(netdev)) { 4741 e1000e_down(adapter, true); 4742 e1000_free_irq(adapter); 4743 4744 /* Link status message must follow this format */ 4745 netdev_info(netdev, "NIC Link is Down\n"); 4746 } 4747 4748 napi_disable(&adapter->napi); 4749 4750 e1000e_free_tx_resources(adapter->tx_ring); 4751 e1000e_free_rx_resources(adapter->rx_ring); 4752 4753 /* kill manageability vlan ID if supported, but not if a vlan with 4754 * the same ID is registered on the host OS (let 8021q kill it) 4755 */ 4756 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4757 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4758 adapter->mng_vlan_id); 4759 4760 /* If AMT is enabled, let the firmware know that the network 4761 * interface is now closed 4762 */ 4763 if ((adapter->flags & FLAG_HAS_AMT) && 4764 !test_bit(__E1000_TESTING, &adapter->state)) 4765 e1000e_release_hw_control(adapter); 4766 4767 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4768 4769 pm_runtime_put_sync(&pdev->dev); 4770 4771 return 0; 4772 } 4773 4774 /** 4775 * e1000_set_mac - Change the Ethernet Address of the NIC 4776 * @netdev: network interface device structure 4777 * @p: pointer to an address structure 4778 * 4779 * Returns 0 on success, negative on failure 4780 **/ 4781 static int e1000_set_mac(struct net_device *netdev, void *p) 4782 { 4783 struct e1000_adapter *adapter = netdev_priv(netdev); 4784 struct e1000_hw *hw = &adapter->hw; 4785 struct sockaddr *addr = p; 4786 4787 if (!is_valid_ether_addr(addr->sa_data)) 4788 return -EADDRNOTAVAIL; 4789 4790 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4791 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4792 4793 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4794 4795 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4796 /* activate the work around */ 4797 e1000e_set_laa_state_82571(&adapter->hw, 1); 4798 4799 /* Hold a copy of the LAA in RAR[14] This is done so that 4800 * between the time RAR[0] gets clobbered and the time it 4801 * gets fixed (in e1000_watchdog), the actual LAA is in one 4802 * of the RARs and no incoming packets directed to this port 4803 * are dropped. Eventually the LAA will be in RAR[0] and 4804 * RAR[14] 4805 */ 4806 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4807 adapter->hw.mac.rar_entry_count - 1); 4808 } 4809 4810 return 0; 4811 } 4812 4813 /** 4814 * e1000e_update_phy_task - work thread to update phy 4815 * @work: pointer to our work struct 4816 * 4817 * this worker thread exists because we must acquire a 4818 * semaphore to read the phy, which we could msleep while 4819 * waiting for it, and we can't msleep in a timer. 4820 **/ 4821 static void e1000e_update_phy_task(struct work_struct *work) 4822 { 4823 struct e1000_adapter *adapter = container_of(work, 4824 struct e1000_adapter, 4825 update_phy_task); 4826 struct e1000_hw *hw = &adapter->hw; 4827 4828 if (test_bit(__E1000_DOWN, &adapter->state)) 4829 return; 4830 4831 e1000_get_phy_info(hw); 4832 4833 /* Enable EEE on 82579 after link up */ 4834 if (hw->phy.type >= e1000_phy_82579) 4835 e1000_set_eee_pchlan(hw); 4836 } 4837 4838 /** 4839 * e1000_update_phy_info - timre call-back to update PHY info 4840 * @t: pointer to timer_list containing private info adapter 4841 * 4842 * Need to wait a few seconds after link up to get diagnostic information from 4843 * the phy 4844 **/ 4845 static void e1000_update_phy_info(struct timer_list *t) 4846 { 4847 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4848 4849 if (test_bit(__E1000_DOWN, &adapter->state)) 4850 return; 4851 4852 schedule_work(&adapter->update_phy_task); 4853 } 4854 4855 /** 4856 * e1000e_update_phy_stats - Update the PHY statistics counters 4857 * @adapter: board private structure 4858 * 4859 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4860 **/ 4861 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4862 { 4863 struct e1000_hw *hw = &adapter->hw; 4864 s32 ret_val; 4865 u16 phy_data; 4866 4867 ret_val = hw->phy.ops.acquire(hw); 4868 if (ret_val) 4869 return; 4870 4871 /* A page set is expensive so check if already on desired page. 4872 * If not, set to the page with the PHY status registers. 4873 */ 4874 hw->phy.addr = 1; 4875 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4876 &phy_data); 4877 if (ret_val) 4878 goto release; 4879 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4880 ret_val = hw->phy.ops.set_page(hw, 4881 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4882 if (ret_val) 4883 goto release; 4884 } 4885 4886 /* Single Collision Count */ 4887 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4888 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4889 if (!ret_val) 4890 adapter->stats.scc += phy_data; 4891 4892 /* Excessive Collision Count */ 4893 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4894 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4895 if (!ret_val) 4896 adapter->stats.ecol += phy_data; 4897 4898 /* Multiple Collision Count */ 4899 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4900 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4901 if (!ret_val) 4902 adapter->stats.mcc += phy_data; 4903 4904 /* Late Collision Count */ 4905 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4906 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4907 if (!ret_val) 4908 adapter->stats.latecol += phy_data; 4909 4910 /* Collision Count - also used for adaptive IFS */ 4911 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4912 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4913 if (!ret_val) 4914 hw->mac.collision_delta = phy_data; 4915 4916 /* Defer Count */ 4917 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4918 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4919 if (!ret_val) 4920 adapter->stats.dc += phy_data; 4921 4922 /* Transmit with no CRS */ 4923 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4924 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4925 if (!ret_val) 4926 adapter->stats.tncrs += phy_data; 4927 4928 release: 4929 hw->phy.ops.release(hw); 4930 } 4931 4932 /** 4933 * e1000e_update_stats - Update the board statistics counters 4934 * @adapter: board private structure 4935 **/ 4936 static void e1000e_update_stats(struct e1000_adapter *adapter) 4937 { 4938 struct net_device *netdev = adapter->netdev; 4939 struct e1000_hw *hw = &adapter->hw; 4940 struct pci_dev *pdev = adapter->pdev; 4941 4942 /* Prevent stats update while adapter is being reset, or if the pci 4943 * connection is down. 4944 */ 4945 if (adapter->link_speed == 0) 4946 return; 4947 if (pci_channel_offline(pdev)) 4948 return; 4949 4950 adapter->stats.crcerrs += er32(CRCERRS); 4951 adapter->stats.gprc += er32(GPRC); 4952 adapter->stats.gorc += er32(GORCL); 4953 er32(GORCH); /* Clear gorc */ 4954 adapter->stats.bprc += er32(BPRC); 4955 adapter->stats.mprc += er32(MPRC); 4956 adapter->stats.roc += er32(ROC); 4957 4958 adapter->stats.mpc += er32(MPC); 4959 4960 /* Half-duplex statistics */ 4961 if (adapter->link_duplex == HALF_DUPLEX) { 4962 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4963 e1000e_update_phy_stats(adapter); 4964 } else { 4965 adapter->stats.scc += er32(SCC); 4966 adapter->stats.ecol += er32(ECOL); 4967 adapter->stats.mcc += er32(MCC); 4968 adapter->stats.latecol += er32(LATECOL); 4969 adapter->stats.dc += er32(DC); 4970 4971 hw->mac.collision_delta = er32(COLC); 4972 4973 if ((hw->mac.type != e1000_82574) && 4974 (hw->mac.type != e1000_82583)) 4975 adapter->stats.tncrs += er32(TNCRS); 4976 } 4977 adapter->stats.colc += hw->mac.collision_delta; 4978 } 4979 4980 adapter->stats.xonrxc += er32(XONRXC); 4981 adapter->stats.xontxc += er32(XONTXC); 4982 adapter->stats.xoffrxc += er32(XOFFRXC); 4983 adapter->stats.xofftxc += er32(XOFFTXC); 4984 adapter->stats.gptc += er32(GPTC); 4985 adapter->stats.gotc += er32(GOTCL); 4986 er32(GOTCH); /* Clear gotc */ 4987 adapter->stats.rnbc += er32(RNBC); 4988 adapter->stats.ruc += er32(RUC); 4989 4990 adapter->stats.mptc += er32(MPTC); 4991 adapter->stats.bptc += er32(BPTC); 4992 4993 /* used for adaptive IFS */ 4994 4995 hw->mac.tx_packet_delta = er32(TPT); 4996 adapter->stats.tpt += hw->mac.tx_packet_delta; 4997 4998 adapter->stats.algnerrc += er32(ALGNERRC); 4999 adapter->stats.rxerrc += er32(RXERRC); 5000 adapter->stats.cexterr += er32(CEXTERR); 5001 adapter->stats.tsctc += er32(TSCTC); 5002 adapter->stats.tsctfc += er32(TSCTFC); 5003 5004 /* Fill out the OS statistics structure */ 5005 netdev->stats.multicast = adapter->stats.mprc; 5006 netdev->stats.collisions = adapter->stats.colc; 5007 5008 /* Rx Errors */ 5009 5010 /* RLEC on some newer hardware can be incorrect so build 5011 * our own version based on RUC and ROC 5012 */ 5013 netdev->stats.rx_errors = adapter->stats.rxerrc + 5014 adapter->stats.crcerrs + adapter->stats.algnerrc + 5015 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5016 netdev->stats.rx_length_errors = adapter->stats.ruc + 5017 adapter->stats.roc; 5018 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5019 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5020 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5021 5022 /* Tx Errors */ 5023 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5024 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5025 netdev->stats.tx_window_errors = adapter->stats.latecol; 5026 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5027 5028 /* Tx Dropped needs to be maintained elsewhere */ 5029 5030 /* Management Stats */ 5031 adapter->stats.mgptc += er32(MGTPTC); 5032 adapter->stats.mgprc += er32(MGTPRC); 5033 adapter->stats.mgpdc += er32(MGTPDC); 5034 5035 /* Correctable ECC Errors */ 5036 if (hw->mac.type >= e1000_pch_lpt) { 5037 u32 pbeccsts = er32(PBECCSTS); 5038 5039 adapter->corr_errors += 5040 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5041 adapter->uncorr_errors += 5042 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5043 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5044 } 5045 } 5046 5047 /** 5048 * e1000_phy_read_status - Update the PHY register status snapshot 5049 * @adapter: board private structure 5050 **/ 5051 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5052 { 5053 struct e1000_hw *hw = &adapter->hw; 5054 struct e1000_phy_regs *phy = &adapter->phy_regs; 5055 5056 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5057 (er32(STATUS) & E1000_STATUS_LU) && 5058 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5059 int ret_val; 5060 5061 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5062 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5063 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5064 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5065 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5066 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5067 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5068 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5069 if (ret_val) 5070 e_warn("Error reading PHY register\n"); 5071 } else { 5072 /* Do not read PHY registers if link is not up 5073 * Set values to typical power-on defaults 5074 */ 5075 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5076 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5077 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5078 BMSR_ERCAP); 5079 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5080 ADVERTISE_ALL | ADVERTISE_CSMA); 5081 phy->lpa = 0; 5082 phy->expansion = EXPANSION_ENABLENPAGE; 5083 phy->ctrl1000 = ADVERTISE_1000FULL; 5084 phy->stat1000 = 0; 5085 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5086 } 5087 } 5088 5089 static void e1000_print_link_info(struct e1000_adapter *adapter) 5090 { 5091 struct e1000_hw *hw = &adapter->hw; 5092 u32 ctrl = er32(CTRL); 5093 5094 /* Link status message must follow this format for user tools */ 5095 netdev_info(adapter->netdev, 5096 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5097 adapter->link_speed, 5098 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5099 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5100 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5101 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5102 } 5103 5104 static bool e1000e_has_link(struct e1000_adapter *adapter) 5105 { 5106 struct e1000_hw *hw = &adapter->hw; 5107 bool link_active = false; 5108 s32 ret_val = 0; 5109 5110 /* get_link_status is set on LSC (link status) interrupt or 5111 * Rx sequence error interrupt. get_link_status will stay 5112 * true until the check_for_link establishes link 5113 * for copper adapters ONLY 5114 */ 5115 switch (hw->phy.media_type) { 5116 case e1000_media_type_copper: 5117 if (hw->mac.get_link_status) { 5118 ret_val = hw->mac.ops.check_for_link(hw); 5119 link_active = !hw->mac.get_link_status; 5120 } else { 5121 link_active = true; 5122 } 5123 break; 5124 case e1000_media_type_fiber: 5125 ret_val = hw->mac.ops.check_for_link(hw); 5126 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5127 break; 5128 case e1000_media_type_internal_serdes: 5129 ret_val = hw->mac.ops.check_for_link(hw); 5130 link_active = hw->mac.serdes_has_link; 5131 break; 5132 default: 5133 case e1000_media_type_unknown: 5134 break; 5135 } 5136 5137 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5138 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5139 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5140 e_info("Gigabit has been disabled, downgrading speed\n"); 5141 } 5142 5143 return link_active; 5144 } 5145 5146 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5147 { 5148 /* make sure the receive unit is started */ 5149 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5150 (adapter->flags & FLAG_RESTART_NOW)) { 5151 struct e1000_hw *hw = &adapter->hw; 5152 u32 rctl = er32(RCTL); 5153 5154 ew32(RCTL, rctl | E1000_RCTL_EN); 5155 adapter->flags &= ~FLAG_RESTART_NOW; 5156 } 5157 } 5158 5159 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5160 { 5161 struct e1000_hw *hw = &adapter->hw; 5162 5163 /* With 82574 controllers, PHY needs to be checked periodically 5164 * for hung state and reset, if two calls return true 5165 */ 5166 if (e1000_check_phy_82574(hw)) 5167 adapter->phy_hang_count++; 5168 else 5169 adapter->phy_hang_count = 0; 5170 5171 if (adapter->phy_hang_count > 1) { 5172 adapter->phy_hang_count = 0; 5173 e_dbg("PHY appears hung - resetting\n"); 5174 schedule_work(&adapter->reset_task); 5175 } 5176 } 5177 5178 /** 5179 * e1000_watchdog - Timer Call-back 5180 * @t: pointer to timer_list containing private info adapter 5181 **/ 5182 static void e1000_watchdog(struct timer_list *t) 5183 { 5184 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5185 5186 /* Do the rest outside of interrupt context */ 5187 schedule_work(&adapter->watchdog_task); 5188 5189 /* TODO: make this use queue_delayed_work() */ 5190 } 5191 5192 static void e1000_watchdog_task(struct work_struct *work) 5193 { 5194 struct e1000_adapter *adapter = container_of(work, 5195 struct e1000_adapter, 5196 watchdog_task); 5197 struct net_device *netdev = adapter->netdev; 5198 struct e1000_mac_info *mac = &adapter->hw.mac; 5199 struct e1000_phy_info *phy = &adapter->hw.phy; 5200 struct e1000_ring *tx_ring = adapter->tx_ring; 5201 u32 dmoff_exit_timeout = 100, tries = 0; 5202 struct e1000_hw *hw = &adapter->hw; 5203 u32 link, tctl, pcim_state; 5204 5205 if (test_bit(__E1000_DOWN, &adapter->state)) 5206 return; 5207 5208 link = e1000e_has_link(adapter); 5209 if ((netif_carrier_ok(netdev)) && link) { 5210 /* Cancel scheduled suspend requests. */ 5211 pm_runtime_resume(netdev->dev.parent); 5212 5213 e1000e_enable_receives(adapter); 5214 goto link_up; 5215 } 5216 5217 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5218 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5219 e1000_update_mng_vlan(adapter); 5220 5221 if (link) { 5222 if (!netif_carrier_ok(netdev)) { 5223 bool txb2b = true; 5224 5225 /* Cancel scheduled suspend requests. */ 5226 pm_runtime_resume(netdev->dev.parent); 5227 5228 /* Checking if MAC is in DMoff state*/ 5229 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 5230 pcim_state = er32(STATUS); 5231 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5232 if (tries++ == dmoff_exit_timeout) { 5233 e_dbg("Error in exiting dmoff\n"); 5234 break; 5235 } 5236 usleep_range(10000, 20000); 5237 pcim_state = er32(STATUS); 5238 5239 /* Checking if MAC exited DMoff state */ 5240 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5241 e1000_phy_hw_reset(&adapter->hw); 5242 } 5243 } 5244 5245 /* update snapshot of PHY registers on LSC */ 5246 e1000_phy_read_status(adapter); 5247 mac->ops.get_link_up_info(&adapter->hw, 5248 &adapter->link_speed, 5249 &adapter->link_duplex); 5250 e1000_print_link_info(adapter); 5251 5252 /* check if SmartSpeed worked */ 5253 e1000e_check_downshift(hw); 5254 if (phy->speed_downgraded) 5255 netdev_warn(netdev, 5256 "Link Speed was downgraded by SmartSpeed\n"); 5257 5258 /* On supported PHYs, check for duplex mismatch only 5259 * if link has autonegotiated at 10/100 half 5260 */ 5261 if ((hw->phy.type == e1000_phy_igp_3 || 5262 hw->phy.type == e1000_phy_bm) && 5263 hw->mac.autoneg && 5264 (adapter->link_speed == SPEED_10 || 5265 adapter->link_speed == SPEED_100) && 5266 (adapter->link_duplex == HALF_DUPLEX)) { 5267 u16 autoneg_exp; 5268 5269 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5270 5271 if (!(autoneg_exp & EXPANSION_NWAY)) 5272 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5273 } 5274 5275 /* adjust timeout factor according to speed/duplex */ 5276 adapter->tx_timeout_factor = 1; 5277 switch (adapter->link_speed) { 5278 case SPEED_10: 5279 txb2b = false; 5280 adapter->tx_timeout_factor = 16; 5281 break; 5282 case SPEED_100: 5283 txb2b = false; 5284 adapter->tx_timeout_factor = 10; 5285 break; 5286 } 5287 5288 /* workaround: re-program speed mode bit after 5289 * link-up event 5290 */ 5291 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5292 !txb2b) { 5293 u32 tarc0; 5294 5295 tarc0 = er32(TARC(0)); 5296 tarc0 &= ~SPEED_MODE_BIT; 5297 ew32(TARC(0), tarc0); 5298 } 5299 5300 /* disable TSO for pcie and 10/100 speeds, to avoid 5301 * some hardware issues 5302 */ 5303 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5304 switch (adapter->link_speed) { 5305 case SPEED_10: 5306 case SPEED_100: 5307 e_info("10/100 speed: disabling TSO\n"); 5308 netdev->features &= ~NETIF_F_TSO; 5309 netdev->features &= ~NETIF_F_TSO6; 5310 break; 5311 case SPEED_1000: 5312 netdev->features |= NETIF_F_TSO; 5313 netdev->features |= NETIF_F_TSO6; 5314 break; 5315 default: 5316 /* oops */ 5317 break; 5318 } 5319 if (hw->mac.type == e1000_pch_spt) { 5320 netdev->features &= ~NETIF_F_TSO; 5321 netdev->features &= ~NETIF_F_TSO6; 5322 } 5323 } 5324 5325 /* enable transmits in the hardware, need to do this 5326 * after setting TARC(0) 5327 */ 5328 tctl = er32(TCTL); 5329 tctl |= E1000_TCTL_EN; 5330 ew32(TCTL, tctl); 5331 5332 /* Perform any post-link-up configuration before 5333 * reporting link up. 5334 */ 5335 if (phy->ops.cfg_on_link_up) 5336 phy->ops.cfg_on_link_up(hw); 5337 5338 netif_wake_queue(netdev); 5339 netif_carrier_on(netdev); 5340 5341 if (!test_bit(__E1000_DOWN, &adapter->state)) 5342 mod_timer(&adapter->phy_info_timer, 5343 round_jiffies(jiffies + 2 * HZ)); 5344 } 5345 } else { 5346 if (netif_carrier_ok(netdev)) { 5347 adapter->link_speed = 0; 5348 adapter->link_duplex = 0; 5349 /* Link status message must follow this format */ 5350 netdev_info(netdev, "NIC Link is Down\n"); 5351 netif_carrier_off(netdev); 5352 netif_stop_queue(netdev); 5353 if (!test_bit(__E1000_DOWN, &adapter->state)) 5354 mod_timer(&adapter->phy_info_timer, 5355 round_jiffies(jiffies + 2 * HZ)); 5356 5357 /* 8000ES2LAN requires a Rx packet buffer work-around 5358 * on link down event; reset the controller to flush 5359 * the Rx packet buffer. 5360 */ 5361 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5362 adapter->flags |= FLAG_RESTART_NOW; 5363 else 5364 pm_schedule_suspend(netdev->dev.parent, 5365 LINK_TIMEOUT); 5366 } 5367 } 5368 5369 link_up: 5370 spin_lock(&adapter->stats64_lock); 5371 e1000e_update_stats(adapter); 5372 5373 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5374 adapter->tpt_old = adapter->stats.tpt; 5375 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5376 adapter->colc_old = adapter->stats.colc; 5377 5378 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5379 adapter->gorc_old = adapter->stats.gorc; 5380 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5381 adapter->gotc_old = adapter->stats.gotc; 5382 spin_unlock(&adapter->stats64_lock); 5383 5384 /* If the link is lost the controller stops DMA, but 5385 * if there is queued Tx work it cannot be done. So 5386 * reset the controller to flush the Tx packet buffers. 5387 */ 5388 if (!netif_carrier_ok(netdev) && 5389 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5390 adapter->flags |= FLAG_RESTART_NOW; 5391 5392 /* If reset is necessary, do it outside of interrupt context. */ 5393 if (adapter->flags & FLAG_RESTART_NOW) { 5394 schedule_work(&adapter->reset_task); 5395 /* return immediately since reset is imminent */ 5396 return; 5397 } 5398 5399 e1000e_update_adaptive(&adapter->hw); 5400 5401 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5402 if (adapter->itr_setting == 4) { 5403 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5404 * Total asymmetrical Tx or Rx gets ITR=8000; 5405 * everyone else is between 2000-8000. 5406 */ 5407 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5408 u32 dif = (adapter->gotc > adapter->gorc ? 5409 adapter->gotc - adapter->gorc : 5410 adapter->gorc - adapter->gotc) / 10000; 5411 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5412 5413 e1000e_write_itr(adapter, itr); 5414 } 5415 5416 /* Cause software interrupt to ensure Rx ring is cleaned */ 5417 if (adapter->msix_entries) 5418 ew32(ICS, adapter->rx_ring->ims_val); 5419 else 5420 ew32(ICS, E1000_ICS_RXDMT0); 5421 5422 /* flush pending descriptors to memory before detecting Tx hang */ 5423 e1000e_flush_descriptors(adapter); 5424 5425 /* Force detection of hung controller every watchdog period */ 5426 adapter->detect_tx_hung = true; 5427 5428 /* With 82571 controllers, LAA may be overwritten due to controller 5429 * reset from the other port. Set the appropriate LAA in RAR[0] 5430 */ 5431 if (e1000e_get_laa_state_82571(hw)) 5432 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5433 5434 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5435 e1000e_check_82574_phy_workaround(adapter); 5436 5437 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5438 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5439 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5440 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5441 er32(RXSTMPH); 5442 adapter->rx_hwtstamp_cleared++; 5443 } else { 5444 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5445 } 5446 } 5447 5448 /* Reset the timer */ 5449 if (!test_bit(__E1000_DOWN, &adapter->state)) 5450 mod_timer(&adapter->watchdog_timer, 5451 round_jiffies(jiffies + 2 * HZ)); 5452 } 5453 5454 #define E1000_TX_FLAGS_CSUM 0x00000001 5455 #define E1000_TX_FLAGS_VLAN 0x00000002 5456 #define E1000_TX_FLAGS_TSO 0x00000004 5457 #define E1000_TX_FLAGS_IPV4 0x00000008 5458 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5459 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5460 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5461 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5462 5463 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5464 __be16 protocol) 5465 { 5466 struct e1000_context_desc *context_desc; 5467 struct e1000_buffer *buffer_info; 5468 unsigned int i; 5469 u32 cmd_length = 0; 5470 u16 ipcse = 0, mss; 5471 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5472 int err; 5473 5474 if (!skb_is_gso(skb)) 5475 return 0; 5476 5477 err = skb_cow_head(skb, 0); 5478 if (err < 0) 5479 return err; 5480 5481 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5482 mss = skb_shinfo(skb)->gso_size; 5483 if (protocol == htons(ETH_P_IP)) { 5484 struct iphdr *iph = ip_hdr(skb); 5485 iph->tot_len = 0; 5486 iph->check = 0; 5487 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5488 0, IPPROTO_TCP, 0); 5489 cmd_length = E1000_TXD_CMD_IP; 5490 ipcse = skb_transport_offset(skb) - 1; 5491 } else if (skb_is_gso_v6(skb)) { 5492 tcp_v6_gso_csum_prep(skb); 5493 ipcse = 0; 5494 } 5495 ipcss = skb_network_offset(skb); 5496 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5497 tucss = skb_transport_offset(skb); 5498 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5499 5500 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5501 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5502 5503 i = tx_ring->next_to_use; 5504 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5505 buffer_info = &tx_ring->buffer_info[i]; 5506 5507 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5508 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5509 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5510 context_desc->upper_setup.tcp_fields.tucss = tucss; 5511 context_desc->upper_setup.tcp_fields.tucso = tucso; 5512 context_desc->upper_setup.tcp_fields.tucse = 0; 5513 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5514 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5515 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5516 5517 buffer_info->time_stamp = jiffies; 5518 buffer_info->next_to_watch = i; 5519 5520 i++; 5521 if (i == tx_ring->count) 5522 i = 0; 5523 tx_ring->next_to_use = i; 5524 5525 return 1; 5526 } 5527 5528 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5529 __be16 protocol) 5530 { 5531 struct e1000_adapter *adapter = tx_ring->adapter; 5532 struct e1000_context_desc *context_desc; 5533 struct e1000_buffer *buffer_info; 5534 unsigned int i; 5535 u8 css; 5536 u32 cmd_len = E1000_TXD_CMD_DEXT; 5537 5538 if (skb->ip_summed != CHECKSUM_PARTIAL) 5539 return false; 5540 5541 switch (protocol) { 5542 case cpu_to_be16(ETH_P_IP): 5543 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5544 cmd_len |= E1000_TXD_CMD_TCP; 5545 break; 5546 case cpu_to_be16(ETH_P_IPV6): 5547 /* XXX not handling all IPV6 headers */ 5548 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5549 cmd_len |= E1000_TXD_CMD_TCP; 5550 break; 5551 default: 5552 if (unlikely(net_ratelimit())) 5553 e_warn("checksum_partial proto=%x!\n", 5554 be16_to_cpu(protocol)); 5555 break; 5556 } 5557 5558 css = skb_checksum_start_offset(skb); 5559 5560 i = tx_ring->next_to_use; 5561 buffer_info = &tx_ring->buffer_info[i]; 5562 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5563 5564 context_desc->lower_setup.ip_config = 0; 5565 context_desc->upper_setup.tcp_fields.tucss = css; 5566 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5567 context_desc->upper_setup.tcp_fields.tucse = 0; 5568 context_desc->tcp_seg_setup.data = 0; 5569 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5570 5571 buffer_info->time_stamp = jiffies; 5572 buffer_info->next_to_watch = i; 5573 5574 i++; 5575 if (i == tx_ring->count) 5576 i = 0; 5577 tx_ring->next_to_use = i; 5578 5579 return true; 5580 } 5581 5582 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5583 unsigned int first, unsigned int max_per_txd, 5584 unsigned int nr_frags) 5585 { 5586 struct e1000_adapter *adapter = tx_ring->adapter; 5587 struct pci_dev *pdev = adapter->pdev; 5588 struct e1000_buffer *buffer_info; 5589 unsigned int len = skb_headlen(skb); 5590 unsigned int offset = 0, size, count = 0, i; 5591 unsigned int f, bytecount, segs; 5592 5593 i = tx_ring->next_to_use; 5594 5595 while (len) { 5596 buffer_info = &tx_ring->buffer_info[i]; 5597 size = min(len, max_per_txd); 5598 5599 buffer_info->length = size; 5600 buffer_info->time_stamp = jiffies; 5601 buffer_info->next_to_watch = i; 5602 buffer_info->dma = dma_map_single(&pdev->dev, 5603 skb->data + offset, 5604 size, DMA_TO_DEVICE); 5605 buffer_info->mapped_as_page = false; 5606 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5607 goto dma_error; 5608 5609 len -= size; 5610 offset += size; 5611 count++; 5612 5613 if (len) { 5614 i++; 5615 if (i == tx_ring->count) 5616 i = 0; 5617 } 5618 } 5619 5620 for (f = 0; f < nr_frags; f++) { 5621 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5622 5623 len = skb_frag_size(frag); 5624 offset = 0; 5625 5626 while (len) { 5627 i++; 5628 if (i == tx_ring->count) 5629 i = 0; 5630 5631 buffer_info = &tx_ring->buffer_info[i]; 5632 size = min(len, max_per_txd); 5633 5634 buffer_info->length = size; 5635 buffer_info->time_stamp = jiffies; 5636 buffer_info->next_to_watch = i; 5637 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5638 offset, size, 5639 DMA_TO_DEVICE); 5640 buffer_info->mapped_as_page = true; 5641 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5642 goto dma_error; 5643 5644 len -= size; 5645 offset += size; 5646 count++; 5647 } 5648 } 5649 5650 segs = skb_shinfo(skb)->gso_segs ? : 1; 5651 /* multiply data chunks by size of headers */ 5652 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5653 5654 tx_ring->buffer_info[i].skb = skb; 5655 tx_ring->buffer_info[i].segs = segs; 5656 tx_ring->buffer_info[i].bytecount = bytecount; 5657 tx_ring->buffer_info[first].next_to_watch = i; 5658 5659 return count; 5660 5661 dma_error: 5662 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5663 buffer_info->dma = 0; 5664 if (count) 5665 count--; 5666 5667 while (count--) { 5668 if (i == 0) 5669 i += tx_ring->count; 5670 i--; 5671 buffer_info = &tx_ring->buffer_info[i]; 5672 e1000_put_txbuf(tx_ring, buffer_info, true); 5673 } 5674 5675 return 0; 5676 } 5677 5678 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5679 { 5680 struct e1000_adapter *adapter = tx_ring->adapter; 5681 struct e1000_tx_desc *tx_desc = NULL; 5682 struct e1000_buffer *buffer_info; 5683 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5684 unsigned int i; 5685 5686 if (tx_flags & E1000_TX_FLAGS_TSO) { 5687 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5688 E1000_TXD_CMD_TSE; 5689 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5690 5691 if (tx_flags & E1000_TX_FLAGS_IPV4) 5692 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5693 } 5694 5695 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5696 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5697 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5698 } 5699 5700 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5701 txd_lower |= E1000_TXD_CMD_VLE; 5702 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5703 } 5704 5705 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5706 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5707 5708 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5709 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5710 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5711 } 5712 5713 i = tx_ring->next_to_use; 5714 5715 do { 5716 buffer_info = &tx_ring->buffer_info[i]; 5717 tx_desc = E1000_TX_DESC(*tx_ring, i); 5718 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5719 tx_desc->lower.data = cpu_to_le32(txd_lower | 5720 buffer_info->length); 5721 tx_desc->upper.data = cpu_to_le32(txd_upper); 5722 5723 i++; 5724 if (i == tx_ring->count) 5725 i = 0; 5726 } while (--count > 0); 5727 5728 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5729 5730 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5731 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5732 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5733 5734 /* Force memory writes to complete before letting h/w 5735 * know there are new descriptors to fetch. (Only 5736 * applicable for weak-ordered memory model archs, 5737 * such as IA-64). 5738 */ 5739 wmb(); 5740 5741 tx_ring->next_to_use = i; 5742 } 5743 5744 #define MINIMUM_DHCP_PACKET_SIZE 282 5745 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5746 struct sk_buff *skb) 5747 { 5748 struct e1000_hw *hw = &adapter->hw; 5749 u16 length, offset; 5750 5751 if (skb_vlan_tag_present(skb) && 5752 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5753 (adapter->hw.mng_cookie.status & 5754 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5755 return 0; 5756 5757 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5758 return 0; 5759 5760 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5761 return 0; 5762 5763 { 5764 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5765 struct udphdr *udp; 5766 5767 if (ip->protocol != IPPROTO_UDP) 5768 return 0; 5769 5770 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5771 if (ntohs(udp->dest) != 67) 5772 return 0; 5773 5774 offset = (u8 *)udp + 8 - skb->data; 5775 length = skb->len - offset; 5776 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5777 } 5778 5779 return 0; 5780 } 5781 5782 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5783 { 5784 struct e1000_adapter *adapter = tx_ring->adapter; 5785 5786 netif_stop_queue(adapter->netdev); 5787 /* Herbert's original patch had: 5788 * smp_mb__after_netif_stop_queue(); 5789 * but since that doesn't exist yet, just open code it. 5790 */ 5791 smp_mb(); 5792 5793 /* We need to check again in a case another CPU has just 5794 * made room available. 5795 */ 5796 if (e1000_desc_unused(tx_ring) < size) 5797 return -EBUSY; 5798 5799 /* A reprieve! */ 5800 netif_start_queue(adapter->netdev); 5801 ++adapter->restart_queue; 5802 return 0; 5803 } 5804 5805 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5806 { 5807 BUG_ON(size > tx_ring->count); 5808 5809 if (e1000_desc_unused(tx_ring) >= size) 5810 return 0; 5811 return __e1000_maybe_stop_tx(tx_ring, size); 5812 } 5813 5814 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5815 struct net_device *netdev) 5816 { 5817 struct e1000_adapter *adapter = netdev_priv(netdev); 5818 struct e1000_ring *tx_ring = adapter->tx_ring; 5819 unsigned int first; 5820 unsigned int tx_flags = 0; 5821 unsigned int len = skb_headlen(skb); 5822 unsigned int nr_frags; 5823 unsigned int mss; 5824 int count = 0; 5825 int tso; 5826 unsigned int f; 5827 __be16 protocol = vlan_get_protocol(skb); 5828 5829 if (test_bit(__E1000_DOWN, &adapter->state)) { 5830 dev_kfree_skb_any(skb); 5831 return NETDEV_TX_OK; 5832 } 5833 5834 if (skb->len <= 0) { 5835 dev_kfree_skb_any(skb); 5836 return NETDEV_TX_OK; 5837 } 5838 5839 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5840 * pad skb in order to meet this minimum size requirement 5841 */ 5842 if (skb_put_padto(skb, 17)) 5843 return NETDEV_TX_OK; 5844 5845 mss = skb_shinfo(skb)->gso_size; 5846 if (mss) { 5847 u8 hdr_len; 5848 5849 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5850 * points to just header, pull a few bytes of payload from 5851 * frags into skb->data 5852 */ 5853 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5854 /* we do this workaround for ES2LAN, but it is un-necessary, 5855 * avoiding it could save a lot of cycles 5856 */ 5857 if (skb->data_len && (hdr_len == len)) { 5858 unsigned int pull_size; 5859 5860 pull_size = min_t(unsigned int, 4, skb->data_len); 5861 if (!__pskb_pull_tail(skb, pull_size)) { 5862 e_err("__pskb_pull_tail failed.\n"); 5863 dev_kfree_skb_any(skb); 5864 return NETDEV_TX_OK; 5865 } 5866 len = skb_headlen(skb); 5867 } 5868 } 5869 5870 /* reserve a descriptor for the offload context */ 5871 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5872 count++; 5873 count++; 5874 5875 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5876 5877 nr_frags = skb_shinfo(skb)->nr_frags; 5878 for (f = 0; f < nr_frags; f++) 5879 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5880 adapter->tx_fifo_limit); 5881 5882 if (adapter->hw.mac.tx_pkt_filtering) 5883 e1000_transfer_dhcp_info(adapter, skb); 5884 5885 /* need: count + 2 desc gap to keep tail from touching 5886 * head, otherwise try next time 5887 */ 5888 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5889 return NETDEV_TX_BUSY; 5890 5891 if (skb_vlan_tag_present(skb)) { 5892 tx_flags |= E1000_TX_FLAGS_VLAN; 5893 tx_flags |= (skb_vlan_tag_get(skb) << 5894 E1000_TX_FLAGS_VLAN_SHIFT); 5895 } 5896 5897 first = tx_ring->next_to_use; 5898 5899 tso = e1000_tso(tx_ring, skb, protocol); 5900 if (tso < 0) { 5901 dev_kfree_skb_any(skb); 5902 return NETDEV_TX_OK; 5903 } 5904 5905 if (tso) 5906 tx_flags |= E1000_TX_FLAGS_TSO; 5907 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5908 tx_flags |= E1000_TX_FLAGS_CSUM; 5909 5910 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5911 * 82571 hardware supports TSO capabilities for IPv6 as well... 5912 * no longer assume, we must. 5913 */ 5914 if (protocol == htons(ETH_P_IP)) 5915 tx_flags |= E1000_TX_FLAGS_IPV4; 5916 5917 if (unlikely(skb->no_fcs)) 5918 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5919 5920 /* if count is 0 then mapping error has occurred */ 5921 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5922 nr_frags); 5923 if (count) { 5924 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5925 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5926 if (!adapter->tx_hwtstamp_skb) { 5927 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5928 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5929 adapter->tx_hwtstamp_skb = skb_get(skb); 5930 adapter->tx_hwtstamp_start = jiffies; 5931 schedule_work(&adapter->tx_hwtstamp_work); 5932 } else { 5933 adapter->tx_hwtstamp_skipped++; 5934 } 5935 } 5936 5937 skb_tx_timestamp(skb); 5938 5939 netdev_sent_queue(netdev, skb->len); 5940 e1000_tx_queue(tx_ring, tx_flags, count); 5941 /* Make sure there is space in the ring for the next send. */ 5942 e1000_maybe_stop_tx(tx_ring, 5943 (MAX_SKB_FRAGS * 5944 DIV_ROUND_UP(PAGE_SIZE, 5945 adapter->tx_fifo_limit) + 2)); 5946 5947 if (!netdev_xmit_more() || 5948 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5949 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5950 e1000e_update_tdt_wa(tx_ring, 5951 tx_ring->next_to_use); 5952 else 5953 writel(tx_ring->next_to_use, tx_ring->tail); 5954 } 5955 } else { 5956 dev_kfree_skb_any(skb); 5957 tx_ring->buffer_info[first].time_stamp = 0; 5958 tx_ring->next_to_use = first; 5959 } 5960 5961 return NETDEV_TX_OK; 5962 } 5963 5964 /** 5965 * e1000_tx_timeout - Respond to a Tx Hang 5966 * @netdev: network interface device structure 5967 * @txqueue: index of the hung queue (unused) 5968 **/ 5969 static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 5970 { 5971 struct e1000_adapter *adapter = netdev_priv(netdev); 5972 5973 /* Do the reset outside of interrupt context */ 5974 adapter->tx_timeout_count++; 5975 schedule_work(&adapter->reset_task); 5976 } 5977 5978 static void e1000_reset_task(struct work_struct *work) 5979 { 5980 struct e1000_adapter *adapter; 5981 adapter = container_of(work, struct e1000_adapter, reset_task); 5982 5983 rtnl_lock(); 5984 /* don't run the task if already down */ 5985 if (test_bit(__E1000_DOWN, &adapter->state)) { 5986 rtnl_unlock(); 5987 return; 5988 } 5989 5990 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5991 e1000e_dump(adapter); 5992 e_err("Reset adapter unexpectedly\n"); 5993 } 5994 e1000e_reinit_locked(adapter); 5995 rtnl_unlock(); 5996 } 5997 5998 /** 5999 * e1000e_get_stats64 - Get System Network Statistics 6000 * @netdev: network interface device structure 6001 * @stats: rtnl_link_stats64 pointer 6002 * 6003 * Returns the address of the device statistics structure. 6004 **/ 6005 void e1000e_get_stats64(struct net_device *netdev, 6006 struct rtnl_link_stats64 *stats) 6007 { 6008 struct e1000_adapter *adapter = netdev_priv(netdev); 6009 6010 spin_lock(&adapter->stats64_lock); 6011 e1000e_update_stats(adapter); 6012 /* Fill out the OS statistics structure */ 6013 stats->rx_bytes = adapter->stats.gorc; 6014 stats->rx_packets = adapter->stats.gprc; 6015 stats->tx_bytes = adapter->stats.gotc; 6016 stats->tx_packets = adapter->stats.gptc; 6017 stats->multicast = adapter->stats.mprc; 6018 stats->collisions = adapter->stats.colc; 6019 6020 /* Rx Errors */ 6021 6022 /* RLEC on some newer hardware can be incorrect so build 6023 * our own version based on RUC and ROC 6024 */ 6025 stats->rx_errors = adapter->stats.rxerrc + 6026 adapter->stats.crcerrs + adapter->stats.algnerrc + 6027 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 6028 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 6029 stats->rx_crc_errors = adapter->stats.crcerrs; 6030 stats->rx_frame_errors = adapter->stats.algnerrc; 6031 stats->rx_missed_errors = adapter->stats.mpc; 6032 6033 /* Tx Errors */ 6034 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6035 stats->tx_aborted_errors = adapter->stats.ecol; 6036 stats->tx_window_errors = adapter->stats.latecol; 6037 stats->tx_carrier_errors = adapter->stats.tncrs; 6038 6039 /* Tx Dropped needs to be maintained elsewhere */ 6040 6041 spin_unlock(&adapter->stats64_lock); 6042 } 6043 6044 /** 6045 * e1000_change_mtu - Change the Maximum Transfer Unit 6046 * @netdev: network interface device structure 6047 * @new_mtu: new value for maximum frame size 6048 * 6049 * Returns 0 on success, negative on failure 6050 **/ 6051 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6052 { 6053 struct e1000_adapter *adapter = netdev_priv(netdev); 6054 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6055 6056 /* Jumbo frame support */ 6057 if ((new_mtu > ETH_DATA_LEN) && 6058 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6059 e_err("Jumbo Frames not supported.\n"); 6060 return -EINVAL; 6061 } 6062 6063 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6064 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6065 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6066 (new_mtu > ETH_DATA_LEN)) { 6067 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6068 return -EINVAL; 6069 } 6070 6071 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6072 usleep_range(1000, 1100); 6073 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6074 adapter->max_frame_size = max_frame; 6075 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6076 netdev->mtu, new_mtu); 6077 netdev->mtu = new_mtu; 6078 6079 pm_runtime_get_sync(netdev->dev.parent); 6080 6081 if (netif_running(netdev)) 6082 e1000e_down(adapter, true); 6083 6084 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6085 * means we reserve 2 more, this pushes us to allocate from the next 6086 * larger slab size. 6087 * i.e. RXBUFFER_2048 --> size-4096 slab 6088 * However with the new *_jumbo_rx* routines, jumbo receives will use 6089 * fragmented skbs 6090 */ 6091 6092 if (max_frame <= 2048) 6093 adapter->rx_buffer_len = 2048; 6094 else 6095 adapter->rx_buffer_len = 4096; 6096 6097 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6098 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6099 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6100 6101 if (netif_running(netdev)) 6102 e1000e_up(adapter); 6103 else 6104 e1000e_reset(adapter); 6105 6106 pm_runtime_put_sync(netdev->dev.parent); 6107 6108 clear_bit(__E1000_RESETTING, &adapter->state); 6109 6110 return 0; 6111 } 6112 6113 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6114 int cmd) 6115 { 6116 struct e1000_adapter *adapter = netdev_priv(netdev); 6117 struct mii_ioctl_data *data = if_mii(ifr); 6118 6119 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6120 return -EOPNOTSUPP; 6121 6122 switch (cmd) { 6123 case SIOCGMIIPHY: 6124 data->phy_id = adapter->hw.phy.addr; 6125 break; 6126 case SIOCGMIIREG: 6127 e1000_phy_read_status(adapter); 6128 6129 switch (data->reg_num & 0x1F) { 6130 case MII_BMCR: 6131 data->val_out = adapter->phy_regs.bmcr; 6132 break; 6133 case MII_BMSR: 6134 data->val_out = adapter->phy_regs.bmsr; 6135 break; 6136 case MII_PHYSID1: 6137 data->val_out = (adapter->hw.phy.id >> 16); 6138 break; 6139 case MII_PHYSID2: 6140 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6141 break; 6142 case MII_ADVERTISE: 6143 data->val_out = adapter->phy_regs.advertise; 6144 break; 6145 case MII_LPA: 6146 data->val_out = adapter->phy_regs.lpa; 6147 break; 6148 case MII_EXPANSION: 6149 data->val_out = adapter->phy_regs.expansion; 6150 break; 6151 case MII_CTRL1000: 6152 data->val_out = adapter->phy_regs.ctrl1000; 6153 break; 6154 case MII_STAT1000: 6155 data->val_out = adapter->phy_regs.stat1000; 6156 break; 6157 case MII_ESTATUS: 6158 data->val_out = adapter->phy_regs.estatus; 6159 break; 6160 default: 6161 return -EIO; 6162 } 6163 break; 6164 case SIOCSMIIREG: 6165 default: 6166 return -EOPNOTSUPP; 6167 } 6168 return 0; 6169 } 6170 6171 /** 6172 * e1000e_hwtstamp_set - control hardware time stamping 6173 * @netdev: network interface device structure 6174 * @ifr: interface request 6175 * 6176 * Outgoing time stamping can be enabled and disabled. Play nice and 6177 * disable it when requested, although it shouldn't cause any overhead 6178 * when no packet needs it. At most one packet in the queue may be 6179 * marked for time stamping, otherwise it would be impossible to tell 6180 * for sure to which packet the hardware time stamp belongs. 6181 * 6182 * Incoming time stamping has to be configured via the hardware filters. 6183 * Not all combinations are supported, in particular event type has to be 6184 * specified. Matching the kind of event packet is not supported, with the 6185 * exception of "all V2 events regardless of level 2 or 4". 6186 **/ 6187 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6188 { 6189 struct e1000_adapter *adapter = netdev_priv(netdev); 6190 struct hwtstamp_config config; 6191 int ret_val; 6192 6193 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6194 return -EFAULT; 6195 6196 ret_val = e1000e_config_hwtstamp(adapter, &config); 6197 if (ret_val) 6198 return ret_val; 6199 6200 switch (config.rx_filter) { 6201 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6202 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6203 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6204 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6205 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6206 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6207 /* With V2 type filters which specify a Sync or Delay Request, 6208 * Path Delay Request/Response messages are also time stamped 6209 * by hardware so notify the caller the requested packets plus 6210 * some others are time stamped. 6211 */ 6212 config.rx_filter = HWTSTAMP_FILTER_SOME; 6213 break; 6214 default: 6215 break; 6216 } 6217 6218 return copy_to_user(ifr->ifr_data, &config, 6219 sizeof(config)) ? -EFAULT : 0; 6220 } 6221 6222 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6223 { 6224 struct e1000_adapter *adapter = netdev_priv(netdev); 6225 6226 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6227 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6228 } 6229 6230 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6231 { 6232 switch (cmd) { 6233 case SIOCGMIIPHY: 6234 case SIOCGMIIREG: 6235 case SIOCSMIIREG: 6236 return e1000_mii_ioctl(netdev, ifr, cmd); 6237 case SIOCSHWTSTAMP: 6238 return e1000e_hwtstamp_set(netdev, ifr); 6239 case SIOCGHWTSTAMP: 6240 return e1000e_hwtstamp_get(netdev, ifr); 6241 default: 6242 return -EOPNOTSUPP; 6243 } 6244 } 6245 6246 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6247 { 6248 struct e1000_hw *hw = &adapter->hw; 6249 u32 i, mac_reg, wuc; 6250 u16 phy_reg, wuc_enable; 6251 int retval; 6252 6253 /* copy MAC RARs to PHY RARs */ 6254 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6255 6256 retval = hw->phy.ops.acquire(hw); 6257 if (retval) { 6258 e_err("Could not acquire PHY\n"); 6259 return retval; 6260 } 6261 6262 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6263 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6264 if (retval) 6265 goto release; 6266 6267 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6268 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6269 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6270 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6271 (u16)(mac_reg & 0xFFFF)); 6272 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6273 (u16)((mac_reg >> 16) & 0xFFFF)); 6274 } 6275 6276 /* configure PHY Rx Control register */ 6277 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6278 mac_reg = er32(RCTL); 6279 if (mac_reg & E1000_RCTL_UPE) 6280 phy_reg |= BM_RCTL_UPE; 6281 if (mac_reg & E1000_RCTL_MPE) 6282 phy_reg |= BM_RCTL_MPE; 6283 phy_reg &= ~(BM_RCTL_MO_MASK); 6284 if (mac_reg & E1000_RCTL_MO_3) 6285 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6286 << BM_RCTL_MO_SHIFT); 6287 if (mac_reg & E1000_RCTL_BAM) 6288 phy_reg |= BM_RCTL_BAM; 6289 if (mac_reg & E1000_RCTL_PMCF) 6290 phy_reg |= BM_RCTL_PMCF; 6291 mac_reg = er32(CTRL); 6292 if (mac_reg & E1000_CTRL_RFCE) 6293 phy_reg |= BM_RCTL_RFCE; 6294 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6295 6296 wuc = E1000_WUC_PME_EN; 6297 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6298 wuc |= E1000_WUC_APME; 6299 6300 /* enable PHY wakeup in MAC register */ 6301 ew32(WUFC, wufc); 6302 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6303 E1000_WUC_PME_STATUS | wuc)); 6304 6305 /* configure and enable PHY wakeup in PHY registers */ 6306 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6307 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6308 6309 /* activate PHY wakeup */ 6310 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6311 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6312 if (retval) 6313 e_err("Could not set PHY Host Wakeup bit\n"); 6314 release: 6315 hw->phy.ops.release(hw); 6316 6317 return retval; 6318 } 6319 6320 static void e1000e_flush_lpic(struct pci_dev *pdev) 6321 { 6322 struct net_device *netdev = pci_get_drvdata(pdev); 6323 struct e1000_adapter *adapter = netdev_priv(netdev); 6324 struct e1000_hw *hw = &adapter->hw; 6325 u32 ret_val; 6326 6327 pm_runtime_get_sync(netdev->dev.parent); 6328 6329 ret_val = hw->phy.ops.acquire(hw); 6330 if (ret_val) 6331 goto fl_out; 6332 6333 pr_info("EEE TX LPI TIMER: %08X\n", 6334 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6335 6336 hw->phy.ops.release(hw); 6337 6338 fl_out: 6339 pm_runtime_put_sync(netdev->dev.parent); 6340 } 6341 6342 /* S0ix implementation */ 6343 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6344 { 6345 struct e1000_hw *hw = &adapter->hw; 6346 u32 mac_data; 6347 u16 phy_data; 6348 6349 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 6350 /* Request ME configure the device for S0ix */ 6351 mac_data = er32(H2ME); 6352 mac_data |= E1000_H2ME_START_DPG; 6353 mac_data &= ~E1000_H2ME_EXIT_DPG; 6354 ew32(H2ME, mac_data); 6355 } else { 6356 /* Request driver configure the device to S0ix */ 6357 /* Disable the periodic inband message, 6358 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6359 */ 6360 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6361 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6362 phy_data |= BIT(10); 6363 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6364 6365 /* Make sure we don't exit K1 every time a new packet arrives 6366 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6367 */ 6368 e1e_rphy(hw, I217_CGFREG, &phy_data); 6369 phy_data |= BIT(5); 6370 e1e_wphy(hw, I217_CGFREG, phy_data); 6371 6372 /* Change the MAC/PHY interface to SMBus 6373 * Force the SMBus in PHY page769_23[0] = 1 6374 * Force the SMBus in MAC CTRL_EXT[11] = 1 6375 */ 6376 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6377 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6378 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6379 mac_data = er32(CTRL_EXT); 6380 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6381 ew32(CTRL_EXT, mac_data); 6382 6383 /* DFT control: PHY bit: page769_20[0] = 1 6384 * page769_20[7] - PHY PLL stop 6385 * page769_20[8] - PHY go to the electrical idle 6386 * page769_20[9] - PHY serdes disable 6387 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6388 */ 6389 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6390 phy_data |= BIT(0); 6391 phy_data |= BIT(7); 6392 phy_data |= BIT(8); 6393 phy_data |= BIT(9); 6394 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6395 6396 mac_data = er32(EXTCNF_CTRL); 6397 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6398 ew32(EXTCNF_CTRL, mac_data); 6399 6400 /* Enable the Dynamic Power Gating in the MAC */ 6401 mac_data = er32(FEXTNVM7); 6402 mac_data |= BIT(22); 6403 ew32(FEXTNVM7, mac_data); 6404 6405 /* Disable disconnected cable conditioning for Power Gating */ 6406 mac_data = er32(DPGFR); 6407 mac_data |= BIT(2); 6408 ew32(DPGFR, mac_data); 6409 6410 /* Don't wake from dynamic Power Gating with clock request */ 6411 mac_data = er32(FEXTNVM12); 6412 mac_data |= BIT(12); 6413 ew32(FEXTNVM12, mac_data); 6414 6415 /* Ungate PGCB clock */ 6416 mac_data = er32(FEXTNVM9); 6417 mac_data &= ~BIT(28); 6418 ew32(FEXTNVM9, mac_data); 6419 6420 /* Enable K1 off to enable mPHY Power Gating */ 6421 mac_data = er32(FEXTNVM6); 6422 mac_data |= BIT(31); 6423 ew32(FEXTNVM6, mac_data); 6424 6425 /* Enable mPHY power gating for any link and speed */ 6426 mac_data = er32(FEXTNVM8); 6427 mac_data |= BIT(9); 6428 ew32(FEXTNVM8, mac_data); 6429 6430 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6431 mac_data = er32(CTRL_EXT); 6432 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6433 ew32(CTRL_EXT, mac_data); 6434 6435 /* No MAC DPG gating SLP_S0 in modern standby 6436 * Switch the logic of the lanphypc to use PMC counter 6437 */ 6438 mac_data = er32(FEXTNVM5); 6439 mac_data |= BIT(7); 6440 ew32(FEXTNVM5, mac_data); 6441 } 6442 6443 /* Disable the time synchronization clock */ 6444 mac_data = er32(FEXTNVM7); 6445 mac_data |= BIT(31); 6446 mac_data &= ~BIT(0); 6447 ew32(FEXTNVM7, mac_data); 6448 6449 /* Dynamic Power Gating Enable */ 6450 mac_data = er32(CTRL_EXT); 6451 mac_data |= BIT(3); 6452 ew32(CTRL_EXT, mac_data); 6453 6454 /* Check MAC Tx/Rx packet buffer pointers. 6455 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6456 * pending traffic indication that would prevent power gating. 6457 */ 6458 mac_data = er32(TDFH); 6459 if (mac_data) 6460 ew32(TDFH, 0); 6461 mac_data = er32(TDFT); 6462 if (mac_data) 6463 ew32(TDFT, 0); 6464 mac_data = er32(TDFHS); 6465 if (mac_data) 6466 ew32(TDFHS, 0); 6467 mac_data = er32(TDFTS); 6468 if (mac_data) 6469 ew32(TDFTS, 0); 6470 mac_data = er32(TDFPC); 6471 if (mac_data) 6472 ew32(TDFPC, 0); 6473 mac_data = er32(RDFH); 6474 if (mac_data) 6475 ew32(RDFH, 0); 6476 mac_data = er32(RDFT); 6477 if (mac_data) 6478 ew32(RDFT, 0); 6479 mac_data = er32(RDFHS); 6480 if (mac_data) 6481 ew32(RDFHS, 0); 6482 mac_data = er32(RDFTS); 6483 if (mac_data) 6484 ew32(RDFTS, 0); 6485 mac_data = er32(RDFPC); 6486 if (mac_data) 6487 ew32(RDFPC, 0); 6488 } 6489 6490 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6491 { 6492 struct e1000_hw *hw = &adapter->hw; 6493 bool firmware_bug = false; 6494 u32 mac_data; 6495 u16 phy_data; 6496 u32 i = 0; 6497 6498 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 6499 /* Request ME unconfigure the device from S0ix */ 6500 mac_data = er32(H2ME); 6501 mac_data &= ~E1000_H2ME_START_DPG; 6502 mac_data |= E1000_H2ME_EXIT_DPG; 6503 ew32(H2ME, mac_data); 6504 6505 /* Poll up to 2.5 seconds for ME to unconfigure DPG. 6506 * If this takes more than 1 second, show a warning indicating a 6507 * firmware bug 6508 */ 6509 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) { 6510 if (i > 100 && !firmware_bug) 6511 firmware_bug = true; 6512 6513 if (i++ == 250) { 6514 e_dbg("Timeout (firmware bug): %d msec\n", 6515 i * 10); 6516 break; 6517 } 6518 6519 usleep_range(10000, 11000); 6520 } 6521 if (firmware_bug) 6522 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n", 6523 i * 10); 6524 else 6525 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10); 6526 } else { 6527 /* Request driver unconfigure the device from S0ix */ 6528 6529 /* Disable the Dynamic Power Gating in the MAC */ 6530 mac_data = er32(FEXTNVM7); 6531 mac_data &= 0xFFBFFFFF; 6532 ew32(FEXTNVM7, mac_data); 6533 6534 /* Disable mPHY power gating for any link and speed */ 6535 mac_data = er32(FEXTNVM8); 6536 mac_data &= ~BIT(9); 6537 ew32(FEXTNVM8, mac_data); 6538 6539 /* Disable K1 off */ 6540 mac_data = er32(FEXTNVM6); 6541 mac_data &= ~BIT(31); 6542 ew32(FEXTNVM6, mac_data); 6543 6544 /* Disable Ungate PGCB clock */ 6545 mac_data = er32(FEXTNVM9); 6546 mac_data |= BIT(28); 6547 ew32(FEXTNVM9, mac_data); 6548 6549 /* Cancel not waking from dynamic 6550 * Power Gating with clock request 6551 */ 6552 mac_data = er32(FEXTNVM12); 6553 mac_data &= ~BIT(12); 6554 ew32(FEXTNVM12, mac_data); 6555 6556 /* Cancel disable disconnected cable conditioning 6557 * for Power Gating 6558 */ 6559 mac_data = er32(DPGFR); 6560 mac_data &= ~BIT(2); 6561 ew32(DPGFR, mac_data); 6562 6563 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6564 mac_data = er32(CTRL_EXT); 6565 mac_data &= 0xFFF7FFFF; 6566 ew32(CTRL_EXT, mac_data); 6567 6568 /* Revert the lanphypc logic to use the internal Gbe counter 6569 * and not the PMC counter 6570 */ 6571 mac_data = er32(FEXTNVM5); 6572 mac_data &= 0xFFFFFF7F; 6573 ew32(FEXTNVM5, mac_data); 6574 6575 /* Enable the periodic inband message, 6576 * Request PCIe clock in K1 page770_17[10:9] =01b 6577 */ 6578 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6579 phy_data &= 0xFBFF; 6580 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6581 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6582 6583 /* Return back configuration 6584 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6585 */ 6586 e1e_rphy(hw, I217_CGFREG, &phy_data); 6587 phy_data &= 0xFFDF; 6588 e1e_wphy(hw, I217_CGFREG, phy_data); 6589 6590 /* Change the MAC/PHY interface to Kumeran 6591 * Unforce the SMBus in PHY page769_23[0] = 0 6592 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6593 */ 6594 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6595 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6596 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6597 mac_data = er32(CTRL_EXT); 6598 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6599 ew32(CTRL_EXT, mac_data); 6600 } 6601 6602 /* Disable Dynamic Power Gating */ 6603 mac_data = er32(CTRL_EXT); 6604 mac_data &= 0xFFFFFFF7; 6605 ew32(CTRL_EXT, mac_data); 6606 6607 /* Enable the time synchronization clock */ 6608 mac_data = er32(FEXTNVM7); 6609 mac_data &= ~BIT(31); 6610 mac_data |= BIT(0); 6611 ew32(FEXTNVM7, mac_data); 6612 } 6613 6614 static int e1000e_pm_freeze(struct device *dev) 6615 { 6616 struct net_device *netdev = dev_get_drvdata(dev); 6617 struct e1000_adapter *adapter = netdev_priv(netdev); 6618 bool present; 6619 6620 rtnl_lock(); 6621 6622 present = netif_device_present(netdev); 6623 netif_device_detach(netdev); 6624 6625 if (present && netif_running(netdev)) { 6626 int count = E1000_CHECK_RESET_COUNT; 6627 6628 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6629 usleep_range(10000, 11000); 6630 6631 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6632 6633 /* Quiesce the device without resetting the hardware */ 6634 e1000e_down(adapter, false); 6635 e1000_free_irq(adapter); 6636 } 6637 rtnl_unlock(); 6638 6639 e1000e_reset_interrupt_capability(adapter); 6640 6641 /* Allow time for pending master requests to run */ 6642 e1000e_disable_pcie_master(&adapter->hw); 6643 6644 return 0; 6645 } 6646 6647 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6648 { 6649 struct net_device *netdev = pci_get_drvdata(pdev); 6650 struct e1000_adapter *adapter = netdev_priv(netdev); 6651 struct e1000_hw *hw = &adapter->hw; 6652 u32 ctrl, ctrl_ext, rctl, status, wufc; 6653 int retval = 0; 6654 6655 /* Runtime suspend should only enable wakeup for link changes */ 6656 if (runtime) 6657 wufc = E1000_WUFC_LNKC; 6658 else if (device_may_wakeup(&pdev->dev)) 6659 wufc = adapter->wol; 6660 else 6661 wufc = 0; 6662 6663 status = er32(STATUS); 6664 if (status & E1000_STATUS_LU) 6665 wufc &= ~E1000_WUFC_LNKC; 6666 6667 if (wufc) { 6668 e1000_setup_rctl(adapter); 6669 e1000e_set_rx_mode(netdev); 6670 6671 /* turn on all-multi mode if wake on multicast is enabled */ 6672 if (wufc & E1000_WUFC_MC) { 6673 rctl = er32(RCTL); 6674 rctl |= E1000_RCTL_MPE; 6675 ew32(RCTL, rctl); 6676 } 6677 6678 ctrl = er32(CTRL); 6679 ctrl |= E1000_CTRL_ADVD3WUC; 6680 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6681 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6682 ew32(CTRL, ctrl); 6683 6684 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6685 adapter->hw.phy.media_type == 6686 e1000_media_type_internal_serdes) { 6687 /* keep the laser running in D3 */ 6688 ctrl_ext = er32(CTRL_EXT); 6689 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6690 ew32(CTRL_EXT, ctrl_ext); 6691 } 6692 6693 if (!runtime) 6694 e1000e_power_up_phy(adapter); 6695 6696 if (adapter->flags & FLAG_IS_ICH) 6697 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6698 6699 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6700 /* enable wakeup by the PHY */ 6701 retval = e1000_init_phy_wakeup(adapter, wufc); 6702 if (retval) 6703 return retval; 6704 } else { 6705 /* enable wakeup by the MAC */ 6706 ew32(WUFC, wufc); 6707 ew32(WUC, E1000_WUC_PME_EN); 6708 } 6709 } else { 6710 ew32(WUC, 0); 6711 ew32(WUFC, 0); 6712 6713 e1000_power_down_phy(adapter); 6714 } 6715 6716 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6717 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6718 } else if (hw->mac.type >= e1000_pch_lpt) { 6719 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6720 /* ULP does not support wake from unicast, multicast 6721 * or broadcast. 6722 */ 6723 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6724 6725 if (retval) 6726 return retval; 6727 } 6728 6729 /* Ensure that the appropriate bits are set in LPI_CTRL 6730 * for EEE in Sx 6731 */ 6732 if ((hw->phy.type >= e1000_phy_i217) && 6733 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6734 u16 lpi_ctrl = 0; 6735 6736 retval = hw->phy.ops.acquire(hw); 6737 if (!retval) { 6738 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6739 &lpi_ctrl); 6740 if (!retval) { 6741 if (adapter->eee_advert & 6742 hw->dev_spec.ich8lan.eee_lp_ability & 6743 I82579_EEE_100_SUPPORTED) 6744 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6745 if (adapter->eee_advert & 6746 hw->dev_spec.ich8lan.eee_lp_ability & 6747 I82579_EEE_1000_SUPPORTED) 6748 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6749 6750 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6751 lpi_ctrl); 6752 } 6753 } 6754 hw->phy.ops.release(hw); 6755 } 6756 6757 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6758 * would have already happened in close and is redundant. 6759 */ 6760 e1000e_release_hw_control(adapter); 6761 6762 pci_clear_master(pdev); 6763 6764 /* The pci-e switch on some quad port adapters will report a 6765 * correctable error when the MAC transitions from D0 to D3. To 6766 * prevent this we need to mask off the correctable errors on the 6767 * downstream port of the pci-e switch. 6768 * 6769 * We don't have the associated upstream bridge while assigning 6770 * the PCI device into guest. For example, the KVM on power is 6771 * one of the cases. 6772 */ 6773 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6774 struct pci_dev *us_dev = pdev->bus->self; 6775 u16 devctl; 6776 6777 if (!us_dev) 6778 return 0; 6779 6780 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6781 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6782 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6783 6784 pci_save_state(pdev); 6785 pci_prepare_to_sleep(pdev); 6786 6787 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6788 } 6789 6790 return 0; 6791 } 6792 6793 /** 6794 * __e1000e_disable_aspm - Disable ASPM states 6795 * @pdev: pointer to PCI device struct 6796 * @state: bit-mask of ASPM states to disable 6797 * @locked: indication if this context holds pci_bus_sem locked. 6798 * 6799 * Some devices *must* have certain ASPM states disabled per hardware errata. 6800 **/ 6801 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6802 { 6803 struct pci_dev *parent = pdev->bus->self; 6804 u16 aspm_dis_mask = 0; 6805 u16 pdev_aspmc, parent_aspmc; 6806 6807 switch (state) { 6808 case PCIE_LINK_STATE_L0S: 6809 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6810 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6811 fallthrough; /* can't have L1 without L0s */ 6812 case PCIE_LINK_STATE_L1: 6813 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6814 break; 6815 default: 6816 return; 6817 } 6818 6819 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6820 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6821 6822 if (parent) { 6823 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6824 &parent_aspmc); 6825 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6826 } 6827 6828 /* Nothing to do if the ASPM states to be disabled already are */ 6829 if (!(pdev_aspmc & aspm_dis_mask) && 6830 (!parent || !(parent_aspmc & aspm_dis_mask))) 6831 return; 6832 6833 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6834 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6835 "L0s" : "", 6836 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6837 "L1" : ""); 6838 6839 #ifdef CONFIG_PCIEASPM 6840 if (locked) 6841 pci_disable_link_state_locked(pdev, state); 6842 else 6843 pci_disable_link_state(pdev, state); 6844 6845 /* Double-check ASPM control. If not disabled by the above, the 6846 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6847 * not enabled); override by writing PCI config space directly. 6848 */ 6849 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6850 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6851 6852 if (!(aspm_dis_mask & pdev_aspmc)) 6853 return; 6854 #endif 6855 6856 /* Both device and parent should have the same ASPM setting. 6857 * Disable ASPM in downstream component first and then upstream. 6858 */ 6859 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6860 6861 if (parent) 6862 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6863 aspm_dis_mask); 6864 } 6865 6866 /** 6867 * e1000e_disable_aspm - Disable ASPM states. 6868 * @pdev: pointer to PCI device struct 6869 * @state: bit-mask of ASPM states to disable 6870 * 6871 * This function acquires the pci_bus_sem! 6872 * Some devices *must* have certain ASPM states disabled per hardware errata. 6873 **/ 6874 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6875 { 6876 __e1000e_disable_aspm(pdev, state, 0); 6877 } 6878 6879 /** 6880 * e1000e_disable_aspm_locked - Disable ASPM states. 6881 * @pdev: pointer to PCI device struct 6882 * @state: bit-mask of ASPM states to disable 6883 * 6884 * This function must be called with pci_bus_sem acquired! 6885 * Some devices *must* have certain ASPM states disabled per hardware errata. 6886 **/ 6887 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6888 { 6889 __e1000e_disable_aspm(pdev, state, 1); 6890 } 6891 6892 static int e1000e_pm_thaw(struct device *dev) 6893 { 6894 struct net_device *netdev = dev_get_drvdata(dev); 6895 struct e1000_adapter *adapter = netdev_priv(netdev); 6896 int rc = 0; 6897 6898 e1000e_set_interrupt_capability(adapter); 6899 6900 rtnl_lock(); 6901 if (netif_running(netdev)) { 6902 rc = e1000_request_irq(adapter); 6903 if (rc) 6904 goto err_irq; 6905 6906 e1000e_up(adapter); 6907 } 6908 6909 netif_device_attach(netdev); 6910 err_irq: 6911 rtnl_unlock(); 6912 6913 return rc; 6914 } 6915 6916 static int __e1000_resume(struct pci_dev *pdev) 6917 { 6918 struct net_device *netdev = pci_get_drvdata(pdev); 6919 struct e1000_adapter *adapter = netdev_priv(netdev); 6920 struct e1000_hw *hw = &adapter->hw; 6921 u16 aspm_disable_flag = 0; 6922 6923 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6924 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6925 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6926 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6927 if (aspm_disable_flag) 6928 e1000e_disable_aspm(pdev, aspm_disable_flag); 6929 6930 pci_set_master(pdev); 6931 6932 if (hw->mac.type >= e1000_pch2lan) 6933 e1000_resume_workarounds_pchlan(&adapter->hw); 6934 6935 e1000e_power_up_phy(adapter); 6936 6937 /* report the system wakeup cause from S3/S4 */ 6938 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6939 u16 phy_data; 6940 6941 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6942 if (phy_data) { 6943 e_info("PHY Wakeup cause - %s\n", 6944 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6945 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6946 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6947 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6948 phy_data & E1000_WUS_LNKC ? 6949 "Link Status Change" : "other"); 6950 } 6951 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6952 } else { 6953 u32 wus = er32(WUS); 6954 6955 if (wus) { 6956 e_info("MAC Wakeup cause - %s\n", 6957 wus & E1000_WUS_EX ? "Unicast Packet" : 6958 wus & E1000_WUS_MC ? "Multicast Packet" : 6959 wus & E1000_WUS_BC ? "Broadcast Packet" : 6960 wus & E1000_WUS_MAG ? "Magic Packet" : 6961 wus & E1000_WUS_LNKC ? "Link Status Change" : 6962 "other"); 6963 } 6964 ew32(WUS, ~0); 6965 } 6966 6967 e1000e_reset(adapter); 6968 6969 e1000_init_manageability_pt(adapter); 6970 6971 /* If the controller has AMT, do not set DRV_LOAD until the interface 6972 * is up. For all other cases, let the f/w know that the h/w is now 6973 * under the control of the driver. 6974 */ 6975 if (!(adapter->flags & FLAG_HAS_AMT)) 6976 e1000e_get_hw_control(adapter); 6977 6978 return 0; 6979 } 6980 6981 static __maybe_unused int e1000e_pm_prepare(struct device *dev) 6982 { 6983 return pm_runtime_suspended(dev) && 6984 pm_suspend_via_firmware(); 6985 } 6986 6987 static __maybe_unused int e1000e_pm_suspend(struct device *dev) 6988 { 6989 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6990 struct e1000_adapter *adapter = netdev_priv(netdev); 6991 struct pci_dev *pdev = to_pci_dev(dev); 6992 int rc; 6993 6994 e1000e_flush_lpic(pdev); 6995 6996 e1000e_pm_freeze(dev); 6997 6998 rc = __e1000_shutdown(pdev, false); 6999 if (rc) { 7000 e1000e_pm_thaw(dev); 7001 } else { 7002 /* Introduce S0ix implementation */ 7003 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 7004 e1000e_s0ix_entry_flow(adapter); 7005 } 7006 7007 return rc; 7008 } 7009 7010 static __maybe_unused int e1000e_pm_resume(struct device *dev) 7011 { 7012 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 7013 struct e1000_adapter *adapter = netdev_priv(netdev); 7014 struct pci_dev *pdev = to_pci_dev(dev); 7015 int rc; 7016 7017 /* Introduce S0ix implementation */ 7018 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 7019 e1000e_s0ix_exit_flow(adapter); 7020 7021 rc = __e1000_resume(pdev); 7022 if (rc) 7023 return rc; 7024 7025 return e1000e_pm_thaw(dev); 7026 } 7027 7028 static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev) 7029 { 7030 struct net_device *netdev = dev_get_drvdata(dev); 7031 struct e1000_adapter *adapter = netdev_priv(netdev); 7032 u16 eee_lp; 7033 7034 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 7035 7036 if (!e1000e_has_link(adapter)) { 7037 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 7038 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 7039 } 7040 7041 return -EBUSY; 7042 } 7043 7044 static __maybe_unused int e1000e_pm_runtime_resume(struct device *dev) 7045 { 7046 struct pci_dev *pdev = to_pci_dev(dev); 7047 struct net_device *netdev = pci_get_drvdata(pdev); 7048 struct e1000_adapter *adapter = netdev_priv(netdev); 7049 int rc; 7050 7051 rc = __e1000_resume(pdev); 7052 if (rc) 7053 return rc; 7054 7055 if (netdev->flags & IFF_UP) 7056 e1000e_up(adapter); 7057 7058 return rc; 7059 } 7060 7061 static __maybe_unused int e1000e_pm_runtime_suspend(struct device *dev) 7062 { 7063 struct pci_dev *pdev = to_pci_dev(dev); 7064 struct net_device *netdev = pci_get_drvdata(pdev); 7065 struct e1000_adapter *adapter = netdev_priv(netdev); 7066 7067 if (netdev->flags & IFF_UP) { 7068 int count = E1000_CHECK_RESET_COUNT; 7069 7070 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 7071 usleep_range(10000, 11000); 7072 7073 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 7074 7075 /* Down the device without resetting the hardware */ 7076 e1000e_down(adapter, false); 7077 } 7078 7079 if (__e1000_shutdown(pdev, true)) { 7080 e1000e_pm_runtime_resume(dev); 7081 return -EBUSY; 7082 } 7083 7084 return 0; 7085 } 7086 7087 static void e1000_shutdown(struct pci_dev *pdev) 7088 { 7089 e1000e_flush_lpic(pdev); 7090 7091 e1000e_pm_freeze(&pdev->dev); 7092 7093 __e1000_shutdown(pdev, false); 7094 } 7095 7096 #ifdef CONFIG_NET_POLL_CONTROLLER 7097 7098 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 7099 { 7100 struct net_device *netdev = data; 7101 struct e1000_adapter *adapter = netdev_priv(netdev); 7102 7103 if (adapter->msix_entries) { 7104 int vector, msix_irq; 7105 7106 vector = 0; 7107 msix_irq = adapter->msix_entries[vector].vector; 7108 if (disable_hardirq(msix_irq)) 7109 e1000_intr_msix_rx(msix_irq, netdev); 7110 enable_irq(msix_irq); 7111 7112 vector++; 7113 msix_irq = adapter->msix_entries[vector].vector; 7114 if (disable_hardirq(msix_irq)) 7115 e1000_intr_msix_tx(msix_irq, netdev); 7116 enable_irq(msix_irq); 7117 7118 vector++; 7119 msix_irq = adapter->msix_entries[vector].vector; 7120 if (disable_hardirq(msix_irq)) 7121 e1000_msix_other(msix_irq, netdev); 7122 enable_irq(msix_irq); 7123 } 7124 7125 return IRQ_HANDLED; 7126 } 7127 7128 /** 7129 * e1000_netpoll 7130 * @netdev: network interface device structure 7131 * 7132 * Polling 'interrupt' - used by things like netconsole to send skbs 7133 * without having to re-enable interrupts. It's not called while 7134 * the interrupt routine is executing. 7135 */ 7136 static void e1000_netpoll(struct net_device *netdev) 7137 { 7138 struct e1000_adapter *adapter = netdev_priv(netdev); 7139 7140 switch (adapter->int_mode) { 7141 case E1000E_INT_MODE_MSIX: 7142 e1000_intr_msix(adapter->pdev->irq, netdev); 7143 break; 7144 case E1000E_INT_MODE_MSI: 7145 if (disable_hardirq(adapter->pdev->irq)) 7146 e1000_intr_msi(adapter->pdev->irq, netdev); 7147 enable_irq(adapter->pdev->irq); 7148 break; 7149 default: /* E1000E_INT_MODE_LEGACY */ 7150 if (disable_hardirq(adapter->pdev->irq)) 7151 e1000_intr(adapter->pdev->irq, netdev); 7152 enable_irq(adapter->pdev->irq); 7153 break; 7154 } 7155 } 7156 #endif 7157 7158 /** 7159 * e1000_io_error_detected - called when PCI error is detected 7160 * @pdev: Pointer to PCI device 7161 * @state: The current pci connection state 7162 * 7163 * This function is called after a PCI bus error affecting 7164 * this device has been detected. 7165 */ 7166 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7167 pci_channel_state_t state) 7168 { 7169 e1000e_pm_freeze(&pdev->dev); 7170 7171 if (state == pci_channel_io_perm_failure) 7172 return PCI_ERS_RESULT_DISCONNECT; 7173 7174 pci_disable_device(pdev); 7175 7176 /* Request a slot reset. */ 7177 return PCI_ERS_RESULT_NEED_RESET; 7178 } 7179 7180 /** 7181 * e1000_io_slot_reset - called after the pci bus has been reset. 7182 * @pdev: Pointer to PCI device 7183 * 7184 * Restart the card from scratch, as if from a cold-boot. Implementation 7185 * resembles the first-half of the e1000e_pm_resume routine. 7186 */ 7187 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7188 { 7189 struct net_device *netdev = pci_get_drvdata(pdev); 7190 struct e1000_adapter *adapter = netdev_priv(netdev); 7191 struct e1000_hw *hw = &adapter->hw; 7192 u16 aspm_disable_flag = 0; 7193 int err; 7194 pci_ers_result_t result; 7195 7196 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7197 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7198 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7199 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7200 if (aspm_disable_flag) 7201 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7202 7203 err = pci_enable_device_mem(pdev); 7204 if (err) { 7205 dev_err(&pdev->dev, 7206 "Cannot re-enable PCI device after reset.\n"); 7207 result = PCI_ERS_RESULT_DISCONNECT; 7208 } else { 7209 pdev->state_saved = true; 7210 pci_restore_state(pdev); 7211 pci_set_master(pdev); 7212 7213 pci_enable_wake(pdev, PCI_D3hot, 0); 7214 pci_enable_wake(pdev, PCI_D3cold, 0); 7215 7216 e1000e_reset(adapter); 7217 ew32(WUS, ~0); 7218 result = PCI_ERS_RESULT_RECOVERED; 7219 } 7220 7221 return result; 7222 } 7223 7224 /** 7225 * e1000_io_resume - called when traffic can start flowing again. 7226 * @pdev: Pointer to PCI device 7227 * 7228 * This callback is called when the error recovery driver tells us that 7229 * its OK to resume normal operation. Implementation resembles the 7230 * second-half of the e1000e_pm_resume routine. 7231 */ 7232 static void e1000_io_resume(struct pci_dev *pdev) 7233 { 7234 struct net_device *netdev = pci_get_drvdata(pdev); 7235 struct e1000_adapter *adapter = netdev_priv(netdev); 7236 7237 e1000_init_manageability_pt(adapter); 7238 7239 e1000e_pm_thaw(&pdev->dev); 7240 7241 /* If the controller has AMT, do not set DRV_LOAD until the interface 7242 * is up. For all other cases, let the f/w know that the h/w is now 7243 * under the control of the driver. 7244 */ 7245 if (!(adapter->flags & FLAG_HAS_AMT)) 7246 e1000e_get_hw_control(adapter); 7247 } 7248 7249 static void e1000_print_device_info(struct e1000_adapter *adapter) 7250 { 7251 struct e1000_hw *hw = &adapter->hw; 7252 struct net_device *netdev = adapter->netdev; 7253 u32 ret_val; 7254 u8 pba_str[E1000_PBANUM_LENGTH]; 7255 7256 /* print bus type/speed/width info */ 7257 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7258 /* bus width */ 7259 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7260 "Width x1"), 7261 /* MAC address */ 7262 netdev->dev_addr); 7263 e_info("Intel(R) PRO/%s Network Connection\n", 7264 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7265 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7266 E1000_PBANUM_LENGTH); 7267 if (ret_val) 7268 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7269 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7270 hw->mac.type, hw->phy.type, pba_str); 7271 } 7272 7273 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7274 { 7275 struct e1000_hw *hw = &adapter->hw; 7276 int ret_val; 7277 u16 buf = 0; 7278 7279 if (hw->mac.type != e1000_82573) 7280 return; 7281 7282 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7283 le16_to_cpus(&buf); 7284 if (!ret_val && (!(buf & BIT(0)))) { 7285 /* Deep Smart Power Down (DSPD) */ 7286 dev_warn(&adapter->pdev->dev, 7287 "Warning: detected DSPD enabled in EEPROM\n"); 7288 } 7289 } 7290 7291 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7292 netdev_features_t features) 7293 { 7294 struct e1000_adapter *adapter = netdev_priv(netdev); 7295 struct e1000_hw *hw = &adapter->hw; 7296 7297 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7298 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7299 features &= ~NETIF_F_RXFCS; 7300 7301 /* Since there is no support for separate Rx/Tx vlan accel 7302 * enable/disable make sure Tx flag is always in same state as Rx. 7303 */ 7304 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7305 features |= NETIF_F_HW_VLAN_CTAG_TX; 7306 else 7307 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7308 7309 return features; 7310 } 7311 7312 static int e1000_set_features(struct net_device *netdev, 7313 netdev_features_t features) 7314 { 7315 struct e1000_adapter *adapter = netdev_priv(netdev); 7316 netdev_features_t changed = features ^ netdev->features; 7317 7318 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7319 adapter->flags |= FLAG_TSO_FORCE; 7320 7321 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7322 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7323 NETIF_F_RXALL))) 7324 return 0; 7325 7326 if (changed & NETIF_F_RXFCS) { 7327 if (features & NETIF_F_RXFCS) { 7328 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7329 } else { 7330 /* We need to take it back to defaults, which might mean 7331 * stripping is still disabled at the adapter level. 7332 */ 7333 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7334 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7335 else 7336 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7337 } 7338 } 7339 7340 netdev->features = features; 7341 7342 if (netif_running(netdev)) 7343 e1000e_reinit_locked(adapter); 7344 else 7345 e1000e_reset(adapter); 7346 7347 return 1; 7348 } 7349 7350 static const struct net_device_ops e1000e_netdev_ops = { 7351 .ndo_open = e1000e_open, 7352 .ndo_stop = e1000e_close, 7353 .ndo_start_xmit = e1000_xmit_frame, 7354 .ndo_get_stats64 = e1000e_get_stats64, 7355 .ndo_set_rx_mode = e1000e_set_rx_mode, 7356 .ndo_set_mac_address = e1000_set_mac, 7357 .ndo_change_mtu = e1000_change_mtu, 7358 .ndo_eth_ioctl = e1000_ioctl, 7359 .ndo_tx_timeout = e1000_tx_timeout, 7360 .ndo_validate_addr = eth_validate_addr, 7361 7362 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7363 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7364 #ifdef CONFIG_NET_POLL_CONTROLLER 7365 .ndo_poll_controller = e1000_netpoll, 7366 #endif 7367 .ndo_set_features = e1000_set_features, 7368 .ndo_fix_features = e1000_fix_features, 7369 .ndo_features_check = passthru_features_check, 7370 }; 7371 7372 /** 7373 * e1000_probe - Device Initialization Routine 7374 * @pdev: PCI device information struct 7375 * @ent: entry in e1000_pci_tbl 7376 * 7377 * Returns 0 on success, negative on failure 7378 * 7379 * e1000_probe initializes an adapter identified by a pci_dev structure. 7380 * The OS initialization, configuring of the adapter private structure, 7381 * and a hardware reset occur. 7382 **/ 7383 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7384 { 7385 struct net_device *netdev; 7386 struct e1000_adapter *adapter; 7387 struct e1000_hw *hw; 7388 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7389 resource_size_t mmio_start, mmio_len; 7390 resource_size_t flash_start, flash_len; 7391 static int cards_found; 7392 u16 aspm_disable_flag = 0; 7393 int bars, i, err, pci_using_dac; 7394 u16 eeprom_data = 0; 7395 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7396 s32 ret_val = 0; 7397 7398 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7399 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7400 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7401 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7402 if (aspm_disable_flag) 7403 e1000e_disable_aspm(pdev, aspm_disable_flag); 7404 7405 err = pci_enable_device_mem(pdev); 7406 if (err) 7407 return err; 7408 7409 pci_using_dac = 0; 7410 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7411 if (!err) { 7412 pci_using_dac = 1; 7413 } else { 7414 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 7415 if (err) { 7416 dev_err(&pdev->dev, 7417 "No usable DMA configuration, aborting\n"); 7418 goto err_dma; 7419 } 7420 } 7421 7422 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7423 err = pci_request_selected_regions_exclusive(pdev, bars, 7424 e1000e_driver_name); 7425 if (err) 7426 goto err_pci_reg; 7427 7428 /* AER (Advanced Error Reporting) hooks */ 7429 pci_enable_pcie_error_reporting(pdev); 7430 7431 pci_set_master(pdev); 7432 /* PCI config space info */ 7433 err = pci_save_state(pdev); 7434 if (err) 7435 goto err_alloc_etherdev; 7436 7437 err = -ENOMEM; 7438 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7439 if (!netdev) 7440 goto err_alloc_etherdev; 7441 7442 SET_NETDEV_DEV(netdev, &pdev->dev); 7443 7444 netdev->irq = pdev->irq; 7445 7446 pci_set_drvdata(pdev, netdev); 7447 adapter = netdev_priv(netdev); 7448 hw = &adapter->hw; 7449 adapter->netdev = netdev; 7450 adapter->pdev = pdev; 7451 adapter->ei = ei; 7452 adapter->pba = ei->pba; 7453 adapter->flags = ei->flags; 7454 adapter->flags2 = ei->flags2; 7455 adapter->hw.adapter = adapter; 7456 adapter->hw.mac.type = ei->mac; 7457 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7458 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7459 7460 mmio_start = pci_resource_start(pdev, 0); 7461 mmio_len = pci_resource_len(pdev, 0); 7462 7463 err = -EIO; 7464 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7465 if (!adapter->hw.hw_addr) 7466 goto err_ioremap; 7467 7468 if ((adapter->flags & FLAG_HAS_FLASH) && 7469 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7470 (hw->mac.type < e1000_pch_spt)) { 7471 flash_start = pci_resource_start(pdev, 1); 7472 flash_len = pci_resource_len(pdev, 1); 7473 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7474 if (!adapter->hw.flash_address) 7475 goto err_flashmap; 7476 } 7477 7478 /* Set default EEE advertisement */ 7479 if (adapter->flags2 & FLAG2_HAS_EEE) 7480 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7481 7482 /* construct the net_device struct */ 7483 netdev->netdev_ops = &e1000e_netdev_ops; 7484 e1000e_set_ethtool_ops(netdev); 7485 netdev->watchdog_timeo = 5 * HZ; 7486 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 7487 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7488 7489 netdev->mem_start = mmio_start; 7490 netdev->mem_end = mmio_start + mmio_len; 7491 7492 adapter->bd_number = cards_found++; 7493 7494 e1000e_check_options(adapter); 7495 7496 /* setup adapter struct */ 7497 err = e1000_sw_init(adapter); 7498 if (err) 7499 goto err_sw_init; 7500 7501 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7502 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7503 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7504 7505 err = ei->get_variants(adapter); 7506 if (err) 7507 goto err_hw_init; 7508 7509 if ((adapter->flags & FLAG_IS_ICH) && 7510 (adapter->flags & FLAG_READ_ONLY_NVM) && 7511 (hw->mac.type < e1000_pch_spt)) 7512 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7513 7514 hw->mac.ops.get_bus_info(&adapter->hw); 7515 7516 adapter->hw.phy.autoneg_wait_to_complete = 0; 7517 7518 /* Copper options */ 7519 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7520 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7521 adapter->hw.phy.disable_polarity_correction = 0; 7522 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7523 } 7524 7525 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7526 dev_info(&pdev->dev, 7527 "PHY reset is blocked due to SOL/IDER session.\n"); 7528 7529 /* Set initial default active device features */ 7530 netdev->features = (NETIF_F_SG | 7531 NETIF_F_HW_VLAN_CTAG_RX | 7532 NETIF_F_HW_VLAN_CTAG_TX | 7533 NETIF_F_TSO | 7534 NETIF_F_TSO6 | 7535 NETIF_F_RXHASH | 7536 NETIF_F_RXCSUM | 7537 NETIF_F_HW_CSUM); 7538 7539 /* Set user-changeable features (subset of all device features) */ 7540 netdev->hw_features = netdev->features; 7541 netdev->hw_features |= NETIF_F_RXFCS; 7542 netdev->priv_flags |= IFF_SUPP_NOFCS; 7543 netdev->hw_features |= NETIF_F_RXALL; 7544 7545 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7546 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7547 7548 netdev->vlan_features |= (NETIF_F_SG | 7549 NETIF_F_TSO | 7550 NETIF_F_TSO6 | 7551 NETIF_F_HW_CSUM); 7552 7553 netdev->priv_flags |= IFF_UNICAST_FLT; 7554 7555 if (pci_using_dac) { 7556 netdev->features |= NETIF_F_HIGHDMA; 7557 netdev->vlan_features |= NETIF_F_HIGHDMA; 7558 } 7559 7560 /* MTU range: 68 - max_hw_frame_size */ 7561 netdev->min_mtu = ETH_MIN_MTU; 7562 netdev->max_mtu = adapter->max_hw_frame_size - 7563 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7564 7565 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7566 adapter->flags |= FLAG_MNG_PT_ENABLED; 7567 7568 /* before reading the NVM, reset the controller to 7569 * put the device in a known good starting state 7570 */ 7571 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7572 7573 /* systems with ASPM and others may see the checksum fail on the first 7574 * attempt. Let's give it a few tries 7575 */ 7576 for (i = 0;; i++) { 7577 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7578 break; 7579 if (i == 2) { 7580 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7581 err = -EIO; 7582 goto err_eeprom; 7583 } 7584 } 7585 7586 e1000_eeprom_checks(adapter); 7587 7588 /* copy the MAC address */ 7589 if (e1000e_read_mac_addr(&adapter->hw)) 7590 dev_err(&pdev->dev, 7591 "NVM Read Error while reading MAC address\n"); 7592 7593 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 7594 7595 if (!is_valid_ether_addr(netdev->dev_addr)) { 7596 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7597 netdev->dev_addr); 7598 err = -EIO; 7599 goto err_eeprom; 7600 } 7601 7602 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7603 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7604 7605 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7606 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7607 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7608 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7609 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7610 7611 /* Initialize link parameters. User can change them with ethtool */ 7612 adapter->hw.mac.autoneg = 1; 7613 adapter->fc_autoneg = true; 7614 adapter->hw.fc.requested_mode = e1000_fc_default; 7615 adapter->hw.fc.current_mode = e1000_fc_default; 7616 adapter->hw.phy.autoneg_advertised = 0x2f; 7617 7618 /* Initial Wake on LAN setting - If APM wake is enabled in 7619 * the EEPROM, enable the ACPI Magic Packet filter 7620 */ 7621 if (adapter->flags & FLAG_APME_IN_WUC) { 7622 /* APME bit in EEPROM is mapped to WUC.APME */ 7623 eeprom_data = er32(WUC); 7624 eeprom_apme_mask = E1000_WUC_APME; 7625 if ((hw->mac.type > e1000_ich10lan) && 7626 (eeprom_data & E1000_WUC_PHY_WAKE)) 7627 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7628 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7629 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7630 (adapter->hw.bus.func == 1)) 7631 ret_val = e1000_read_nvm(&adapter->hw, 7632 NVM_INIT_CONTROL3_PORT_B, 7633 1, &eeprom_data); 7634 else 7635 ret_val = e1000_read_nvm(&adapter->hw, 7636 NVM_INIT_CONTROL3_PORT_A, 7637 1, &eeprom_data); 7638 } 7639 7640 /* fetch WoL from EEPROM */ 7641 if (ret_val) 7642 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7643 else if (eeprom_data & eeprom_apme_mask) 7644 adapter->eeprom_wol |= E1000_WUFC_MAG; 7645 7646 /* now that we have the eeprom settings, apply the special cases 7647 * where the eeprom may be wrong or the board simply won't support 7648 * wake on lan on a particular port 7649 */ 7650 if (!(adapter->flags & FLAG_HAS_WOL)) 7651 adapter->eeprom_wol = 0; 7652 7653 /* initialize the wol settings based on the eeprom settings */ 7654 adapter->wol = adapter->eeprom_wol; 7655 7656 /* make sure adapter isn't asleep if manageability is enabled */ 7657 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7658 (hw->mac.ops.check_mng_mode(hw))) 7659 device_wakeup_enable(&pdev->dev); 7660 7661 /* save off EEPROM version number */ 7662 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7663 7664 if (ret_val) { 7665 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7666 adapter->eeprom_vers = 0; 7667 } 7668 7669 /* init PTP hardware clock */ 7670 e1000e_ptp_init(adapter); 7671 7672 /* reset the hardware with the new settings */ 7673 e1000e_reset(adapter); 7674 7675 /* If the controller has AMT, do not set DRV_LOAD until the interface 7676 * is up. For all other cases, let the f/w know that the h/w is now 7677 * under the control of the driver. 7678 */ 7679 if (!(adapter->flags & FLAG_HAS_AMT)) 7680 e1000e_get_hw_control(adapter); 7681 7682 if (hw->mac.type >= e1000_pch_cnp) 7683 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS; 7684 7685 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7686 err = register_netdev(netdev); 7687 if (err) 7688 goto err_register; 7689 7690 /* carrier off reporting is important to ethtool even BEFORE open */ 7691 netif_carrier_off(netdev); 7692 7693 e1000_print_device_info(adapter); 7694 7695 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE); 7696 7697 if (pci_dev_run_wake(pdev) && hw->mac.type != e1000_pch_cnp) 7698 pm_runtime_put_noidle(&pdev->dev); 7699 7700 return 0; 7701 7702 err_register: 7703 if (!(adapter->flags & FLAG_HAS_AMT)) 7704 e1000e_release_hw_control(adapter); 7705 err_eeprom: 7706 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7707 e1000_phy_hw_reset(&adapter->hw); 7708 err_hw_init: 7709 kfree(adapter->tx_ring); 7710 kfree(adapter->rx_ring); 7711 err_sw_init: 7712 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7713 iounmap(adapter->hw.flash_address); 7714 e1000e_reset_interrupt_capability(adapter); 7715 err_flashmap: 7716 iounmap(adapter->hw.hw_addr); 7717 err_ioremap: 7718 free_netdev(netdev); 7719 err_alloc_etherdev: 7720 pci_disable_pcie_error_reporting(pdev); 7721 pci_release_mem_regions(pdev); 7722 err_pci_reg: 7723 err_dma: 7724 pci_disable_device(pdev); 7725 return err; 7726 } 7727 7728 /** 7729 * e1000_remove - Device Removal Routine 7730 * @pdev: PCI device information struct 7731 * 7732 * e1000_remove is called by the PCI subsystem to alert the driver 7733 * that it should release a PCI device. This could be caused by a 7734 * Hot-Plug event, or because the driver is going to be removed from 7735 * memory. 7736 **/ 7737 static void e1000_remove(struct pci_dev *pdev) 7738 { 7739 struct net_device *netdev = pci_get_drvdata(pdev); 7740 struct e1000_adapter *adapter = netdev_priv(netdev); 7741 7742 e1000e_ptp_remove(adapter); 7743 7744 /* The timers may be rescheduled, so explicitly disable them 7745 * from being rescheduled. 7746 */ 7747 set_bit(__E1000_DOWN, &adapter->state); 7748 del_timer_sync(&adapter->watchdog_timer); 7749 del_timer_sync(&adapter->phy_info_timer); 7750 7751 cancel_work_sync(&adapter->reset_task); 7752 cancel_work_sync(&adapter->watchdog_task); 7753 cancel_work_sync(&adapter->downshift_task); 7754 cancel_work_sync(&adapter->update_phy_task); 7755 cancel_work_sync(&adapter->print_hang_task); 7756 7757 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7758 cancel_work_sync(&adapter->tx_hwtstamp_work); 7759 if (adapter->tx_hwtstamp_skb) { 7760 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7761 adapter->tx_hwtstamp_skb = NULL; 7762 } 7763 } 7764 7765 unregister_netdev(netdev); 7766 7767 if (pci_dev_run_wake(pdev)) 7768 pm_runtime_get_noresume(&pdev->dev); 7769 7770 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7771 * would have already happened in close and is redundant. 7772 */ 7773 e1000e_release_hw_control(adapter); 7774 7775 e1000e_reset_interrupt_capability(adapter); 7776 kfree(adapter->tx_ring); 7777 kfree(adapter->rx_ring); 7778 7779 iounmap(adapter->hw.hw_addr); 7780 if ((adapter->hw.flash_address) && 7781 (adapter->hw.mac.type < e1000_pch_spt)) 7782 iounmap(adapter->hw.flash_address); 7783 pci_release_mem_regions(pdev); 7784 7785 free_netdev(netdev); 7786 7787 /* AER disable */ 7788 pci_disable_pcie_error_reporting(pdev); 7789 7790 pci_disable_device(pdev); 7791 } 7792 7793 /* PCI Error Recovery (ERS) */ 7794 static const struct pci_error_handlers e1000_err_handler = { 7795 .error_detected = e1000_io_error_detected, 7796 .slot_reset = e1000_io_slot_reset, 7797 .resume = e1000_io_resume, 7798 }; 7799 7800 static const struct pci_device_id e1000_pci_tbl[] = { 7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7805 board_82571 }, 7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7811 7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7813 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7816 7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7820 7821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7824 7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7826 board_80003es2lan }, 7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7828 board_80003es2lan }, 7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7830 board_80003es2lan }, 7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7832 board_80003es2lan }, 7833 7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7842 7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7852 7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7856 7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7860 7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7865 7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7868 7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp }, 7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp }, 7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp }, 7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, 7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, 7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, 7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp }, 7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp }, 7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp }, 7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp }, 7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp }, 7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp }, 7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_tgp }, 7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_tgp }, 7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_tgp }, 7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_tgp }, 7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_tgp }, 7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_tgp }, 7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_tgp }, 7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_tgp }, 7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_tgp }, 7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_tgp }, 7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_tgp }, 7917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_tgp }, 7918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_tgp }, 7919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_tgp }, 7920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_tgp }, 7921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_tgp }, 7922 7923 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7924 }; 7925 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7926 7927 static const struct dev_pm_ops e1000_pm_ops = { 7928 #ifdef CONFIG_PM_SLEEP 7929 .prepare = e1000e_pm_prepare, 7930 .suspend = e1000e_pm_suspend, 7931 .resume = e1000e_pm_resume, 7932 .freeze = e1000e_pm_freeze, 7933 .thaw = e1000e_pm_thaw, 7934 .poweroff = e1000e_pm_suspend, 7935 .restore = e1000e_pm_resume, 7936 #endif 7937 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7938 e1000e_pm_runtime_idle) 7939 }; 7940 7941 /* PCI Device API Driver */ 7942 static struct pci_driver e1000_driver = { 7943 .name = e1000e_driver_name, 7944 .id_table = e1000_pci_tbl, 7945 .probe = e1000_probe, 7946 .remove = e1000_remove, 7947 .driver = { 7948 .pm = &e1000_pm_ops, 7949 }, 7950 .shutdown = e1000_shutdown, 7951 .err_handler = &e1000_err_handler 7952 }; 7953 7954 /** 7955 * e1000_init_module - Driver Registration Routine 7956 * 7957 * e1000_init_module is the first routine called when the driver is 7958 * loaded. All it does is register with the PCI subsystem. 7959 **/ 7960 static int __init e1000_init_module(void) 7961 { 7962 pr_info("Intel(R) PRO/1000 Network Driver\n"); 7963 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7964 7965 return pci_register_driver(&e1000_driver); 7966 } 7967 module_init(e1000_init_module); 7968 7969 /** 7970 * e1000_exit_module - Driver Exit Cleanup Routine 7971 * 7972 * e1000_exit_module is called just before the driver is removed 7973 * from memory. 7974 **/ 7975 static void __exit e1000_exit_module(void) 7976 { 7977 pci_unregister_driver(&e1000_driver); 7978 } 7979 module_exit(e1000_exit_module); 7980 7981 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7982 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7983 MODULE_LICENSE("GPL v2"); 7984 7985 /* netdev.c */ 7986