1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/aer.h> 27 #include <linux/prefetch.h> 28 29 #include "e1000.h" 30 31 #define DRV_EXTRAVERSION "-k" 32 33 #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION 34 char e1000e_driver_name[] = "e1000e"; 35 const char e1000e_driver_version[] = DRV_VERSION; 36 37 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 38 static int debug = -1; 39 module_param(debug, int, 0); 40 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 41 42 static const struct e1000_info *e1000_info_tbl[] = { 43 [board_82571] = &e1000_82571_info, 44 [board_82572] = &e1000_82572_info, 45 [board_82573] = &e1000_82573_info, 46 [board_82574] = &e1000_82574_info, 47 [board_82583] = &e1000_82583_info, 48 [board_80003es2lan] = &e1000_es2_info, 49 [board_ich8lan] = &e1000_ich8_info, 50 [board_ich9lan] = &e1000_ich9_info, 51 [board_ich10lan] = &e1000_ich10_info, 52 [board_pchlan] = &e1000_pch_info, 53 [board_pch2lan] = &e1000_pch2_info, 54 [board_pch_lpt] = &e1000_pch_lpt_info, 55 [board_pch_spt] = &e1000_pch_spt_info, 56 [board_pch_cnp] = &e1000_pch_cnp_info, 57 }; 58 59 struct e1000_reg_info { 60 u32 ofs; 61 char *name; 62 }; 63 64 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 65 /* General Registers */ 66 {E1000_CTRL, "CTRL"}, 67 {E1000_STATUS, "STATUS"}, 68 {E1000_CTRL_EXT, "CTRL_EXT"}, 69 70 /* Interrupt Registers */ 71 {E1000_ICR, "ICR"}, 72 73 /* Rx Registers */ 74 {E1000_RCTL, "RCTL"}, 75 {E1000_RDLEN(0), "RDLEN"}, 76 {E1000_RDH(0), "RDH"}, 77 {E1000_RDT(0), "RDT"}, 78 {E1000_RDTR, "RDTR"}, 79 {E1000_RXDCTL(0), "RXDCTL"}, 80 {E1000_ERT, "ERT"}, 81 {E1000_RDBAL(0), "RDBAL"}, 82 {E1000_RDBAH(0), "RDBAH"}, 83 {E1000_RDFH, "RDFH"}, 84 {E1000_RDFT, "RDFT"}, 85 {E1000_RDFHS, "RDFHS"}, 86 {E1000_RDFTS, "RDFTS"}, 87 {E1000_RDFPC, "RDFPC"}, 88 89 /* Tx Registers */ 90 {E1000_TCTL, "TCTL"}, 91 {E1000_TDBAL(0), "TDBAL"}, 92 {E1000_TDBAH(0), "TDBAH"}, 93 {E1000_TDLEN(0), "TDLEN"}, 94 {E1000_TDH(0), "TDH"}, 95 {E1000_TDT(0), "TDT"}, 96 {E1000_TIDV, "TIDV"}, 97 {E1000_TXDCTL(0), "TXDCTL"}, 98 {E1000_TADV, "TADV"}, 99 {E1000_TARC(0), "TARC"}, 100 {E1000_TDFH, "TDFH"}, 101 {E1000_TDFT, "TDFT"}, 102 {E1000_TDFHS, "TDFHS"}, 103 {E1000_TDFTS, "TDFTS"}, 104 {E1000_TDFPC, "TDFPC"}, 105 106 /* List Terminator */ 107 {0, NULL} 108 }; 109 110 struct e1000e_me_supported { 111 u16 device_id; /* supported device ID */ 112 }; 113 114 static const struct e1000e_me_supported me_supported[] = { 115 {E1000_DEV_ID_PCH_LPT_I217_LM}, 116 {E1000_DEV_ID_PCH_LPTLP_I218_LM}, 117 {E1000_DEV_ID_PCH_I218_LM2}, 118 {E1000_DEV_ID_PCH_I218_LM3}, 119 {E1000_DEV_ID_PCH_SPT_I219_LM}, 120 {E1000_DEV_ID_PCH_SPT_I219_LM2}, 121 {E1000_DEV_ID_PCH_LBG_I219_LM3}, 122 {E1000_DEV_ID_PCH_SPT_I219_LM4}, 123 {E1000_DEV_ID_PCH_SPT_I219_LM5}, 124 {E1000_DEV_ID_PCH_CNP_I219_LM6}, 125 {E1000_DEV_ID_PCH_CNP_I219_LM7}, 126 {E1000_DEV_ID_PCH_ICP_I219_LM8}, 127 {E1000_DEV_ID_PCH_ICP_I219_LM9}, 128 {E1000_DEV_ID_PCH_CMP_I219_LM10}, 129 {E1000_DEV_ID_PCH_CMP_I219_LM11}, 130 {E1000_DEV_ID_PCH_CMP_I219_LM12}, 131 {E1000_DEV_ID_PCH_TGP_I219_LM13}, 132 {E1000_DEV_ID_PCH_TGP_I219_LM14}, 133 {E1000_DEV_ID_PCH_TGP_I219_LM15}, 134 {0} 135 }; 136 137 static bool e1000e_check_me(u16 device_id) 138 { 139 struct e1000e_me_supported *id; 140 141 for (id = (struct e1000e_me_supported *)me_supported; 142 id->device_id; id++) 143 if (device_id == id->device_id) 144 return true; 145 146 return false; 147 } 148 149 /** 150 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 151 * @hw: pointer to the HW structure 152 * 153 * When updating the MAC CSR registers, the Manageability Engine (ME) could 154 * be accessing the registers at the same time. Normally, this is handled in 155 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 156 * accesses later than it should which could result in the register to have 157 * an incorrect value. Workaround this by checking the FWSM register which 158 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 159 * and try again a number of times. 160 **/ 161 s32 __ew32_prepare(struct e1000_hw *hw) 162 { 163 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 164 165 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 166 udelay(50); 167 168 return i; 169 } 170 171 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 172 { 173 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 174 __ew32_prepare(hw); 175 176 writel(val, hw->hw_addr + reg); 177 } 178 179 /** 180 * e1000_regdump - register printout routine 181 * @hw: pointer to the HW structure 182 * @reginfo: pointer to the register info table 183 **/ 184 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 185 { 186 int n = 0; 187 char rname[16]; 188 u32 regs[8]; 189 190 switch (reginfo->ofs) { 191 case E1000_RXDCTL(0): 192 for (n = 0; n < 2; n++) 193 regs[n] = __er32(hw, E1000_RXDCTL(n)); 194 break; 195 case E1000_TXDCTL(0): 196 for (n = 0; n < 2; n++) 197 regs[n] = __er32(hw, E1000_TXDCTL(n)); 198 break; 199 case E1000_TARC(0): 200 for (n = 0; n < 2; n++) 201 regs[n] = __er32(hw, E1000_TARC(n)); 202 break; 203 default: 204 pr_info("%-15s %08x\n", 205 reginfo->name, __er32(hw, reginfo->ofs)); 206 return; 207 } 208 209 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 210 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 211 } 212 213 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 214 struct e1000_buffer *bi) 215 { 216 int i; 217 struct e1000_ps_page *ps_page; 218 219 for (i = 0; i < adapter->rx_ps_pages; i++) { 220 ps_page = &bi->ps_pages[i]; 221 222 if (ps_page->page) { 223 pr_info("packet dump for ps_page %d:\n", i); 224 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 225 16, 1, page_address(ps_page->page), 226 PAGE_SIZE, true); 227 } 228 } 229 } 230 231 /** 232 * e1000e_dump - Print registers, Tx-ring and Rx-ring 233 * @adapter: board private structure 234 **/ 235 static void e1000e_dump(struct e1000_adapter *adapter) 236 { 237 struct net_device *netdev = adapter->netdev; 238 struct e1000_hw *hw = &adapter->hw; 239 struct e1000_reg_info *reginfo; 240 struct e1000_ring *tx_ring = adapter->tx_ring; 241 struct e1000_tx_desc *tx_desc; 242 struct my_u0 { 243 __le64 a; 244 __le64 b; 245 } *u0; 246 struct e1000_buffer *buffer_info; 247 struct e1000_ring *rx_ring = adapter->rx_ring; 248 union e1000_rx_desc_packet_split *rx_desc_ps; 249 union e1000_rx_desc_extended *rx_desc; 250 struct my_u1 { 251 __le64 a; 252 __le64 b; 253 __le64 c; 254 __le64 d; 255 } *u1; 256 u32 staterr; 257 int i = 0; 258 259 if (!netif_msg_hw(adapter)) 260 return; 261 262 /* Print netdevice Info */ 263 if (netdev) { 264 dev_info(&adapter->pdev->dev, "Net device Info\n"); 265 pr_info("Device Name state trans_start\n"); 266 pr_info("%-15s %016lX %016lX\n", netdev->name, 267 netdev->state, dev_trans_start(netdev)); 268 } 269 270 /* Print Registers */ 271 dev_info(&adapter->pdev->dev, "Register Dump\n"); 272 pr_info(" Register Name Value\n"); 273 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 274 reginfo->name; reginfo++) { 275 e1000_regdump(hw, reginfo); 276 } 277 278 /* Print Tx Ring Summary */ 279 if (!netdev || !netif_running(netdev)) 280 return; 281 282 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 283 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 284 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 285 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 286 0, tx_ring->next_to_use, tx_ring->next_to_clean, 287 (unsigned long long)buffer_info->dma, 288 buffer_info->length, 289 buffer_info->next_to_watch, 290 (unsigned long long)buffer_info->time_stamp); 291 292 /* Print Tx Ring */ 293 if (!netif_msg_tx_done(adapter)) 294 goto rx_ring_summary; 295 296 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 297 298 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 299 * 300 * Legacy Transmit Descriptor 301 * +--------------------------------------------------------------+ 302 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 303 * +--------------------------------------------------------------+ 304 * 8 | Special | CSS | Status | CMD | CSO | Length | 305 * +--------------------------------------------------------------+ 306 * 63 48 47 36 35 32 31 24 23 16 15 0 307 * 308 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 309 * 63 48 47 40 39 32 31 16 15 8 7 0 310 * +----------------------------------------------------------------+ 311 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 312 * +----------------------------------------------------------------+ 313 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 314 * +----------------------------------------------------------------+ 315 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 316 * 317 * Extended Data Descriptor (DTYP=0x1) 318 * +----------------------------------------------------------------+ 319 * 0 | Buffer Address [63:0] | 320 * +----------------------------------------------------------------+ 321 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 322 * +----------------------------------------------------------------+ 323 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 324 */ 325 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 326 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 327 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 328 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 329 const char *next_desc; 330 tx_desc = E1000_TX_DESC(*tx_ring, i); 331 buffer_info = &tx_ring->buffer_info[i]; 332 u0 = (struct my_u0 *)tx_desc; 333 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 334 next_desc = " NTC/U"; 335 else if (i == tx_ring->next_to_use) 336 next_desc = " NTU"; 337 else if (i == tx_ring->next_to_clean) 338 next_desc = " NTC"; 339 else 340 next_desc = ""; 341 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 342 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 343 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 344 i, 345 (unsigned long long)le64_to_cpu(u0->a), 346 (unsigned long long)le64_to_cpu(u0->b), 347 (unsigned long long)buffer_info->dma, 348 buffer_info->length, buffer_info->next_to_watch, 349 (unsigned long long)buffer_info->time_stamp, 350 buffer_info->skb, next_desc); 351 352 if (netif_msg_pktdata(adapter) && buffer_info->skb) 353 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 354 16, 1, buffer_info->skb->data, 355 buffer_info->skb->len, true); 356 } 357 358 /* Print Rx Ring Summary */ 359 rx_ring_summary: 360 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 361 pr_info("Queue [NTU] [NTC]\n"); 362 pr_info(" %5d %5X %5X\n", 363 0, rx_ring->next_to_use, rx_ring->next_to_clean); 364 365 /* Print Rx Ring */ 366 if (!netif_msg_rx_status(adapter)) 367 return; 368 369 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 370 switch (adapter->rx_ps_pages) { 371 case 1: 372 case 2: 373 case 3: 374 /* [Extended] Packet Split Receive Descriptor Format 375 * 376 * +-----------------------------------------------------+ 377 * 0 | Buffer Address 0 [63:0] | 378 * +-----------------------------------------------------+ 379 * 8 | Buffer Address 1 [63:0] | 380 * +-----------------------------------------------------+ 381 * 16 | Buffer Address 2 [63:0] | 382 * +-----------------------------------------------------+ 383 * 24 | Buffer Address 3 [63:0] | 384 * +-----------------------------------------------------+ 385 */ 386 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 387 /* [Extended] Receive Descriptor (Write-Back) Format 388 * 389 * 63 48 47 32 31 13 12 8 7 4 3 0 390 * +------------------------------------------------------+ 391 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 392 * | Checksum | Ident | | Queue | | Type | 393 * +------------------------------------------------------+ 394 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 395 * +------------------------------------------------------+ 396 * 63 48 47 32 31 20 19 0 397 */ 398 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 399 for (i = 0; i < rx_ring->count; i++) { 400 const char *next_desc; 401 buffer_info = &rx_ring->buffer_info[i]; 402 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 403 u1 = (struct my_u1 *)rx_desc_ps; 404 staterr = 405 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 406 407 if (i == rx_ring->next_to_use) 408 next_desc = " NTU"; 409 else if (i == rx_ring->next_to_clean) 410 next_desc = " NTC"; 411 else 412 next_desc = ""; 413 414 if (staterr & E1000_RXD_STAT_DD) { 415 /* Descriptor Done */ 416 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 417 "RWB", i, 418 (unsigned long long)le64_to_cpu(u1->a), 419 (unsigned long long)le64_to_cpu(u1->b), 420 (unsigned long long)le64_to_cpu(u1->c), 421 (unsigned long long)le64_to_cpu(u1->d), 422 buffer_info->skb, next_desc); 423 } else { 424 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 425 "R ", i, 426 (unsigned long long)le64_to_cpu(u1->a), 427 (unsigned long long)le64_to_cpu(u1->b), 428 (unsigned long long)le64_to_cpu(u1->c), 429 (unsigned long long)le64_to_cpu(u1->d), 430 (unsigned long long)buffer_info->dma, 431 buffer_info->skb, next_desc); 432 433 if (netif_msg_pktdata(adapter)) 434 e1000e_dump_ps_pages(adapter, 435 buffer_info); 436 } 437 } 438 break; 439 default: 440 case 0: 441 /* Extended Receive Descriptor (Read) Format 442 * 443 * +-----------------------------------------------------+ 444 * 0 | Buffer Address [63:0] | 445 * +-----------------------------------------------------+ 446 * 8 | Reserved | 447 * +-----------------------------------------------------+ 448 */ 449 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 450 /* Extended Receive Descriptor (Write-Back) Format 451 * 452 * 63 48 47 32 31 24 23 4 3 0 453 * +------------------------------------------------------+ 454 * | RSS Hash | | | | 455 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 456 * | Packet | IP | | | Type | 457 * | Checksum | Ident | | | | 458 * +------------------------------------------------------+ 459 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 460 * +------------------------------------------------------+ 461 * 63 48 47 32 31 20 19 0 462 */ 463 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 464 465 for (i = 0; i < rx_ring->count; i++) { 466 const char *next_desc; 467 468 buffer_info = &rx_ring->buffer_info[i]; 469 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 470 u1 = (struct my_u1 *)rx_desc; 471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 472 473 if (i == rx_ring->next_to_use) 474 next_desc = " NTU"; 475 else if (i == rx_ring->next_to_clean) 476 next_desc = " NTC"; 477 else 478 next_desc = ""; 479 480 if (staterr & E1000_RXD_STAT_DD) { 481 /* Descriptor Done */ 482 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 483 "RWB", i, 484 (unsigned long long)le64_to_cpu(u1->a), 485 (unsigned long long)le64_to_cpu(u1->b), 486 buffer_info->skb, next_desc); 487 } else { 488 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 489 "R ", i, 490 (unsigned long long)le64_to_cpu(u1->a), 491 (unsigned long long)le64_to_cpu(u1->b), 492 (unsigned long long)buffer_info->dma, 493 buffer_info->skb, next_desc); 494 495 if (netif_msg_pktdata(adapter) && 496 buffer_info->skb) 497 print_hex_dump(KERN_INFO, "", 498 DUMP_PREFIX_ADDRESS, 16, 499 1, 500 buffer_info->skb->data, 501 adapter->rx_buffer_len, 502 true); 503 } 504 } 505 } 506 } 507 508 /** 509 * e1000_desc_unused - calculate if we have unused descriptors 510 **/ 511 static int e1000_desc_unused(struct e1000_ring *ring) 512 { 513 if (ring->next_to_clean > ring->next_to_use) 514 return ring->next_to_clean - ring->next_to_use - 1; 515 516 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 517 } 518 519 /** 520 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 521 * @adapter: board private structure 522 * @hwtstamps: time stamp structure to update 523 * @systim: unsigned 64bit system time value. 524 * 525 * Convert the system time value stored in the RX/TXSTMP registers into a 526 * hwtstamp which can be used by the upper level time stamping functions. 527 * 528 * The 'systim_lock' spinlock is used to protect the consistency of the 529 * system time value. This is needed because reading the 64 bit time 530 * value involves reading two 32 bit registers. The first read latches the 531 * value. 532 **/ 533 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 534 struct skb_shared_hwtstamps *hwtstamps, 535 u64 systim) 536 { 537 u64 ns; 538 unsigned long flags; 539 540 spin_lock_irqsave(&adapter->systim_lock, flags); 541 ns = timecounter_cyc2time(&adapter->tc, systim); 542 spin_unlock_irqrestore(&adapter->systim_lock, flags); 543 544 memset(hwtstamps, 0, sizeof(*hwtstamps)); 545 hwtstamps->hwtstamp = ns_to_ktime(ns); 546 } 547 548 /** 549 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 550 * @adapter: board private structure 551 * @status: descriptor extended error and status field 552 * @skb: particular skb to include time stamp 553 * 554 * If the time stamp is valid, convert it into the timecounter ns value 555 * and store that result into the shhwtstamps structure which is passed 556 * up the network stack. 557 **/ 558 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 559 struct sk_buff *skb) 560 { 561 struct e1000_hw *hw = &adapter->hw; 562 u64 rxstmp; 563 564 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 565 !(status & E1000_RXDEXT_STATERR_TST) || 566 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 567 return; 568 569 /* The Rx time stamp registers contain the time stamp. No other 570 * received packet will be time stamped until the Rx time stamp 571 * registers are read. Because only one packet can be time stamped 572 * at a time, the register values must belong to this packet and 573 * therefore none of the other additional attributes need to be 574 * compared. 575 */ 576 rxstmp = (u64)er32(RXSTMPL); 577 rxstmp |= (u64)er32(RXSTMPH) << 32; 578 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 579 580 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 581 } 582 583 /** 584 * e1000_receive_skb - helper function to handle Rx indications 585 * @adapter: board private structure 586 * @staterr: descriptor extended error and status field as written by hardware 587 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 588 * @skb: pointer to sk_buff to be indicated to stack 589 **/ 590 static void e1000_receive_skb(struct e1000_adapter *adapter, 591 struct net_device *netdev, struct sk_buff *skb, 592 u32 staterr, __le16 vlan) 593 { 594 u16 tag = le16_to_cpu(vlan); 595 596 e1000e_rx_hwtstamp(adapter, staterr, skb); 597 598 skb->protocol = eth_type_trans(skb, netdev); 599 600 if (staterr & E1000_RXD_STAT_VP) 601 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 602 603 napi_gro_receive(&adapter->napi, skb); 604 } 605 606 /** 607 * e1000_rx_checksum - Receive Checksum Offload 608 * @adapter: board private structure 609 * @status_err: receive descriptor status and error fields 610 * @csum: receive descriptor csum field 611 * @sk_buff: socket buffer with received data 612 **/ 613 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 614 struct sk_buff *skb) 615 { 616 u16 status = (u16)status_err; 617 u8 errors = (u8)(status_err >> 24); 618 619 skb_checksum_none_assert(skb); 620 621 /* Rx checksum disabled */ 622 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 623 return; 624 625 /* Ignore Checksum bit is set */ 626 if (status & E1000_RXD_STAT_IXSM) 627 return; 628 629 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 630 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 631 /* let the stack verify checksum errors */ 632 adapter->hw_csum_err++; 633 return; 634 } 635 636 /* TCP/UDP Checksum has not been calculated */ 637 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 638 return; 639 640 /* It must be a TCP or UDP packet with a valid checksum */ 641 skb->ip_summed = CHECKSUM_UNNECESSARY; 642 adapter->hw_csum_good++; 643 } 644 645 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 646 { 647 struct e1000_adapter *adapter = rx_ring->adapter; 648 struct e1000_hw *hw = &adapter->hw; 649 s32 ret_val = __ew32_prepare(hw); 650 651 writel(i, rx_ring->tail); 652 653 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { 654 u32 rctl = er32(RCTL); 655 656 ew32(RCTL, rctl & ~E1000_RCTL_EN); 657 e_err("ME firmware caused invalid RDT - resetting\n"); 658 schedule_work(&adapter->reset_task); 659 } 660 } 661 662 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 663 { 664 struct e1000_adapter *adapter = tx_ring->adapter; 665 struct e1000_hw *hw = &adapter->hw; 666 s32 ret_val = __ew32_prepare(hw); 667 668 writel(i, tx_ring->tail); 669 670 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { 671 u32 tctl = er32(TCTL); 672 673 ew32(TCTL, tctl & ~E1000_TCTL_EN); 674 e_err("ME firmware caused invalid TDT - resetting\n"); 675 schedule_work(&adapter->reset_task); 676 } 677 } 678 679 /** 680 * e1000_alloc_rx_buffers - Replace used receive buffers 681 * @rx_ring: Rx descriptor ring 682 **/ 683 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 684 int cleaned_count, gfp_t gfp) 685 { 686 struct e1000_adapter *adapter = rx_ring->adapter; 687 struct net_device *netdev = adapter->netdev; 688 struct pci_dev *pdev = adapter->pdev; 689 union e1000_rx_desc_extended *rx_desc; 690 struct e1000_buffer *buffer_info; 691 struct sk_buff *skb; 692 unsigned int i; 693 unsigned int bufsz = adapter->rx_buffer_len; 694 695 i = rx_ring->next_to_use; 696 buffer_info = &rx_ring->buffer_info[i]; 697 698 while (cleaned_count--) { 699 skb = buffer_info->skb; 700 if (skb) { 701 skb_trim(skb, 0); 702 goto map_skb; 703 } 704 705 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 706 if (!skb) { 707 /* Better luck next round */ 708 adapter->alloc_rx_buff_failed++; 709 break; 710 } 711 712 buffer_info->skb = skb; 713 map_skb: 714 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 715 adapter->rx_buffer_len, 716 DMA_FROM_DEVICE); 717 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 718 dev_err(&pdev->dev, "Rx DMA map failed\n"); 719 adapter->rx_dma_failed++; 720 break; 721 } 722 723 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 724 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 725 726 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 727 /* Force memory writes to complete before letting h/w 728 * know there are new descriptors to fetch. (Only 729 * applicable for weak-ordered memory model archs, 730 * such as IA-64). 731 */ 732 wmb(); 733 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 734 e1000e_update_rdt_wa(rx_ring, i); 735 else 736 writel(i, rx_ring->tail); 737 } 738 i++; 739 if (i == rx_ring->count) 740 i = 0; 741 buffer_info = &rx_ring->buffer_info[i]; 742 } 743 744 rx_ring->next_to_use = i; 745 } 746 747 /** 748 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 749 * @rx_ring: Rx descriptor ring 750 **/ 751 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 752 int cleaned_count, gfp_t gfp) 753 { 754 struct e1000_adapter *adapter = rx_ring->adapter; 755 struct net_device *netdev = adapter->netdev; 756 struct pci_dev *pdev = adapter->pdev; 757 union e1000_rx_desc_packet_split *rx_desc; 758 struct e1000_buffer *buffer_info; 759 struct e1000_ps_page *ps_page; 760 struct sk_buff *skb; 761 unsigned int i, j; 762 763 i = rx_ring->next_to_use; 764 buffer_info = &rx_ring->buffer_info[i]; 765 766 while (cleaned_count--) { 767 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 768 769 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 770 ps_page = &buffer_info->ps_pages[j]; 771 if (j >= adapter->rx_ps_pages) { 772 /* all unused desc entries get hw null ptr */ 773 rx_desc->read.buffer_addr[j + 1] = 774 ~cpu_to_le64(0); 775 continue; 776 } 777 if (!ps_page->page) { 778 ps_page->page = alloc_page(gfp); 779 if (!ps_page->page) { 780 adapter->alloc_rx_buff_failed++; 781 goto no_buffers; 782 } 783 ps_page->dma = dma_map_page(&pdev->dev, 784 ps_page->page, 785 0, PAGE_SIZE, 786 DMA_FROM_DEVICE); 787 if (dma_mapping_error(&pdev->dev, 788 ps_page->dma)) { 789 dev_err(&adapter->pdev->dev, 790 "Rx DMA page map failed\n"); 791 adapter->rx_dma_failed++; 792 goto no_buffers; 793 } 794 } 795 /* Refresh the desc even if buffer_addrs 796 * didn't change because each write-back 797 * erases this info. 798 */ 799 rx_desc->read.buffer_addr[j + 1] = 800 cpu_to_le64(ps_page->dma); 801 } 802 803 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 804 gfp); 805 806 if (!skb) { 807 adapter->alloc_rx_buff_failed++; 808 break; 809 } 810 811 buffer_info->skb = skb; 812 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 813 adapter->rx_ps_bsize0, 814 DMA_FROM_DEVICE); 815 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 816 dev_err(&pdev->dev, "Rx DMA map failed\n"); 817 adapter->rx_dma_failed++; 818 /* cleanup skb */ 819 dev_kfree_skb_any(skb); 820 buffer_info->skb = NULL; 821 break; 822 } 823 824 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 825 826 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 827 /* Force memory writes to complete before letting h/w 828 * know there are new descriptors to fetch. (Only 829 * applicable for weak-ordered memory model archs, 830 * such as IA-64). 831 */ 832 wmb(); 833 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 834 e1000e_update_rdt_wa(rx_ring, i << 1); 835 else 836 writel(i << 1, rx_ring->tail); 837 } 838 839 i++; 840 if (i == rx_ring->count) 841 i = 0; 842 buffer_info = &rx_ring->buffer_info[i]; 843 } 844 845 no_buffers: 846 rx_ring->next_to_use = i; 847 } 848 849 /** 850 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 851 * @rx_ring: Rx descriptor ring 852 * @cleaned_count: number of buffers to allocate this pass 853 **/ 854 855 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 856 int cleaned_count, gfp_t gfp) 857 { 858 struct e1000_adapter *adapter = rx_ring->adapter; 859 struct net_device *netdev = adapter->netdev; 860 struct pci_dev *pdev = adapter->pdev; 861 union e1000_rx_desc_extended *rx_desc; 862 struct e1000_buffer *buffer_info; 863 struct sk_buff *skb; 864 unsigned int i; 865 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 866 867 i = rx_ring->next_to_use; 868 buffer_info = &rx_ring->buffer_info[i]; 869 870 while (cleaned_count--) { 871 skb = buffer_info->skb; 872 if (skb) { 873 skb_trim(skb, 0); 874 goto check_page; 875 } 876 877 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 878 if (unlikely(!skb)) { 879 /* Better luck next round */ 880 adapter->alloc_rx_buff_failed++; 881 break; 882 } 883 884 buffer_info->skb = skb; 885 check_page: 886 /* allocate a new page if necessary */ 887 if (!buffer_info->page) { 888 buffer_info->page = alloc_page(gfp); 889 if (unlikely(!buffer_info->page)) { 890 adapter->alloc_rx_buff_failed++; 891 break; 892 } 893 } 894 895 if (!buffer_info->dma) { 896 buffer_info->dma = dma_map_page(&pdev->dev, 897 buffer_info->page, 0, 898 PAGE_SIZE, 899 DMA_FROM_DEVICE); 900 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 901 adapter->alloc_rx_buff_failed++; 902 break; 903 } 904 } 905 906 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 907 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 908 909 if (unlikely(++i == rx_ring->count)) 910 i = 0; 911 buffer_info = &rx_ring->buffer_info[i]; 912 } 913 914 if (likely(rx_ring->next_to_use != i)) { 915 rx_ring->next_to_use = i; 916 if (unlikely(i-- == 0)) 917 i = (rx_ring->count - 1); 918 919 /* Force memory writes to complete before letting h/w 920 * know there are new descriptors to fetch. (Only 921 * applicable for weak-ordered memory model archs, 922 * such as IA-64). 923 */ 924 wmb(); 925 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 926 e1000e_update_rdt_wa(rx_ring, i); 927 else 928 writel(i, rx_ring->tail); 929 } 930 } 931 932 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 933 struct sk_buff *skb) 934 { 935 if (netdev->features & NETIF_F_RXHASH) 936 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 937 } 938 939 /** 940 * e1000_clean_rx_irq - Send received data up the network stack 941 * @rx_ring: Rx descriptor ring 942 * 943 * the return value indicates whether actual cleaning was done, there 944 * is no guarantee that everything was cleaned 945 **/ 946 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 947 int work_to_do) 948 { 949 struct e1000_adapter *adapter = rx_ring->adapter; 950 struct net_device *netdev = adapter->netdev; 951 struct pci_dev *pdev = adapter->pdev; 952 struct e1000_hw *hw = &adapter->hw; 953 union e1000_rx_desc_extended *rx_desc, *next_rxd; 954 struct e1000_buffer *buffer_info, *next_buffer; 955 u32 length, staterr; 956 unsigned int i; 957 int cleaned_count = 0; 958 bool cleaned = false; 959 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 960 961 i = rx_ring->next_to_clean; 962 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 963 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 964 buffer_info = &rx_ring->buffer_info[i]; 965 966 while (staterr & E1000_RXD_STAT_DD) { 967 struct sk_buff *skb; 968 969 if (*work_done >= work_to_do) 970 break; 971 (*work_done)++; 972 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 973 974 skb = buffer_info->skb; 975 buffer_info->skb = NULL; 976 977 prefetch(skb->data - NET_IP_ALIGN); 978 979 i++; 980 if (i == rx_ring->count) 981 i = 0; 982 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 983 prefetch(next_rxd); 984 985 next_buffer = &rx_ring->buffer_info[i]; 986 987 cleaned = true; 988 cleaned_count++; 989 dma_unmap_single(&pdev->dev, buffer_info->dma, 990 adapter->rx_buffer_len, DMA_FROM_DEVICE); 991 buffer_info->dma = 0; 992 993 length = le16_to_cpu(rx_desc->wb.upper.length); 994 995 /* !EOP means multiple descriptors were used to store a single 996 * packet, if that's the case we need to toss it. In fact, we 997 * need to toss every packet with the EOP bit clear and the 998 * next frame that _does_ have the EOP bit set, as it is by 999 * definition only a frame fragment 1000 */ 1001 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 1002 adapter->flags2 |= FLAG2_IS_DISCARDING; 1003 1004 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1005 /* All receives must fit into a single buffer */ 1006 e_dbg("Receive packet consumed multiple buffers\n"); 1007 /* recycle */ 1008 buffer_info->skb = skb; 1009 if (staterr & E1000_RXD_STAT_EOP) 1010 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1011 goto next_desc; 1012 } 1013 1014 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1015 !(netdev->features & NETIF_F_RXALL))) { 1016 /* recycle */ 1017 buffer_info->skb = skb; 1018 goto next_desc; 1019 } 1020 1021 /* adjust length to remove Ethernet CRC */ 1022 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1023 /* If configured to store CRC, don't subtract FCS, 1024 * but keep the FCS bytes out of the total_rx_bytes 1025 * counter 1026 */ 1027 if (netdev->features & NETIF_F_RXFCS) 1028 total_rx_bytes -= 4; 1029 else 1030 length -= 4; 1031 } 1032 1033 total_rx_bytes += length; 1034 total_rx_packets++; 1035 1036 /* code added for copybreak, this should improve 1037 * performance for small packets with large amounts 1038 * of reassembly being done in the stack 1039 */ 1040 if (length < copybreak) { 1041 struct sk_buff *new_skb = 1042 napi_alloc_skb(&adapter->napi, length); 1043 if (new_skb) { 1044 skb_copy_to_linear_data_offset(new_skb, 1045 -NET_IP_ALIGN, 1046 (skb->data - 1047 NET_IP_ALIGN), 1048 (length + 1049 NET_IP_ALIGN)); 1050 /* save the skb in buffer_info as good */ 1051 buffer_info->skb = skb; 1052 skb = new_skb; 1053 } 1054 /* else just continue with the old one */ 1055 } 1056 /* end copybreak code */ 1057 skb_put(skb, length); 1058 1059 /* Receive Checksum Offload */ 1060 e1000_rx_checksum(adapter, staterr, skb); 1061 1062 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1063 1064 e1000_receive_skb(adapter, netdev, skb, staterr, 1065 rx_desc->wb.upper.vlan); 1066 1067 next_desc: 1068 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1069 1070 /* return some buffers to hardware, one at a time is too slow */ 1071 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1072 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1073 GFP_ATOMIC); 1074 cleaned_count = 0; 1075 } 1076 1077 /* use prefetched values */ 1078 rx_desc = next_rxd; 1079 buffer_info = next_buffer; 1080 1081 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1082 } 1083 rx_ring->next_to_clean = i; 1084 1085 cleaned_count = e1000_desc_unused(rx_ring); 1086 if (cleaned_count) 1087 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1088 1089 adapter->total_rx_bytes += total_rx_bytes; 1090 adapter->total_rx_packets += total_rx_packets; 1091 return cleaned; 1092 } 1093 1094 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1095 struct e1000_buffer *buffer_info, 1096 bool drop) 1097 { 1098 struct e1000_adapter *adapter = tx_ring->adapter; 1099 1100 if (buffer_info->dma) { 1101 if (buffer_info->mapped_as_page) 1102 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1103 buffer_info->length, DMA_TO_DEVICE); 1104 else 1105 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1106 buffer_info->length, DMA_TO_DEVICE); 1107 buffer_info->dma = 0; 1108 } 1109 if (buffer_info->skb) { 1110 if (drop) 1111 dev_kfree_skb_any(buffer_info->skb); 1112 else 1113 dev_consume_skb_any(buffer_info->skb); 1114 buffer_info->skb = NULL; 1115 } 1116 buffer_info->time_stamp = 0; 1117 } 1118 1119 static void e1000_print_hw_hang(struct work_struct *work) 1120 { 1121 struct e1000_adapter *adapter = container_of(work, 1122 struct e1000_adapter, 1123 print_hang_task); 1124 struct net_device *netdev = adapter->netdev; 1125 struct e1000_ring *tx_ring = adapter->tx_ring; 1126 unsigned int i = tx_ring->next_to_clean; 1127 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1128 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1129 struct e1000_hw *hw = &adapter->hw; 1130 u16 phy_status, phy_1000t_status, phy_ext_status; 1131 u16 pci_status; 1132 1133 if (test_bit(__E1000_DOWN, &adapter->state)) 1134 return; 1135 1136 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1137 /* May be block on write-back, flush and detect again 1138 * flush pending descriptor writebacks to memory 1139 */ 1140 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1141 /* execute the writes immediately */ 1142 e1e_flush(); 1143 /* Due to rare timing issues, write to TIDV again to ensure 1144 * the write is successful 1145 */ 1146 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1147 /* execute the writes immediately */ 1148 e1e_flush(); 1149 adapter->tx_hang_recheck = true; 1150 return; 1151 } 1152 adapter->tx_hang_recheck = false; 1153 1154 if (er32(TDH(0)) == er32(TDT(0))) { 1155 e_dbg("false hang detected, ignoring\n"); 1156 return; 1157 } 1158 1159 /* Real hang detected */ 1160 netif_stop_queue(netdev); 1161 1162 e1e_rphy(hw, MII_BMSR, &phy_status); 1163 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1164 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1165 1166 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1167 1168 /* detected Hardware unit hang */ 1169 e_err("Detected Hardware Unit Hang:\n" 1170 " TDH <%x>\n" 1171 " TDT <%x>\n" 1172 " next_to_use <%x>\n" 1173 " next_to_clean <%x>\n" 1174 "buffer_info[next_to_clean]:\n" 1175 " time_stamp <%lx>\n" 1176 " next_to_watch <%x>\n" 1177 " jiffies <%lx>\n" 1178 " next_to_watch.status <%x>\n" 1179 "MAC Status <%x>\n" 1180 "PHY Status <%x>\n" 1181 "PHY 1000BASE-T Status <%x>\n" 1182 "PHY Extended Status <%x>\n" 1183 "PCI Status <%x>\n", 1184 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1185 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1186 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1187 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1188 1189 e1000e_dump(adapter); 1190 1191 /* Suggest workaround for known h/w issue */ 1192 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1193 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1194 } 1195 1196 /** 1197 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1198 * @work: pointer to work struct 1199 * 1200 * This work function polls the TSYNCTXCTL valid bit to determine when a 1201 * timestamp has been taken for the current stored skb. The timestamp must 1202 * be for this skb because only one such packet is allowed in the queue. 1203 */ 1204 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1205 { 1206 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1207 tx_hwtstamp_work); 1208 struct e1000_hw *hw = &adapter->hw; 1209 1210 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1211 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1212 struct skb_shared_hwtstamps shhwtstamps; 1213 u64 txstmp; 1214 1215 txstmp = er32(TXSTMPL); 1216 txstmp |= (u64)er32(TXSTMPH) << 32; 1217 1218 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1219 1220 /* Clear the global tx_hwtstamp_skb pointer and force writes 1221 * prior to notifying the stack of a Tx timestamp. 1222 */ 1223 adapter->tx_hwtstamp_skb = NULL; 1224 wmb(); /* force write prior to skb_tstamp_tx */ 1225 1226 skb_tstamp_tx(skb, &shhwtstamps); 1227 dev_consume_skb_any(skb); 1228 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1229 + adapter->tx_timeout_factor * HZ)) { 1230 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1231 adapter->tx_hwtstamp_skb = NULL; 1232 adapter->tx_hwtstamp_timeouts++; 1233 e_warn("clearing Tx timestamp hang\n"); 1234 } else { 1235 /* reschedule to check later */ 1236 schedule_work(&adapter->tx_hwtstamp_work); 1237 } 1238 } 1239 1240 /** 1241 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1242 * @tx_ring: Tx descriptor ring 1243 * 1244 * the return value indicates whether actual cleaning was done, there 1245 * is no guarantee that everything was cleaned 1246 **/ 1247 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1248 { 1249 struct e1000_adapter *adapter = tx_ring->adapter; 1250 struct net_device *netdev = adapter->netdev; 1251 struct e1000_hw *hw = &adapter->hw; 1252 struct e1000_tx_desc *tx_desc, *eop_desc; 1253 struct e1000_buffer *buffer_info; 1254 unsigned int i, eop; 1255 unsigned int count = 0; 1256 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1257 unsigned int bytes_compl = 0, pkts_compl = 0; 1258 1259 i = tx_ring->next_to_clean; 1260 eop = tx_ring->buffer_info[i].next_to_watch; 1261 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1262 1263 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1264 (count < tx_ring->count)) { 1265 bool cleaned = false; 1266 1267 dma_rmb(); /* read buffer_info after eop_desc */ 1268 for (; !cleaned; count++) { 1269 tx_desc = E1000_TX_DESC(*tx_ring, i); 1270 buffer_info = &tx_ring->buffer_info[i]; 1271 cleaned = (i == eop); 1272 1273 if (cleaned) { 1274 total_tx_packets += buffer_info->segs; 1275 total_tx_bytes += buffer_info->bytecount; 1276 if (buffer_info->skb) { 1277 bytes_compl += buffer_info->skb->len; 1278 pkts_compl++; 1279 } 1280 } 1281 1282 e1000_put_txbuf(tx_ring, buffer_info, false); 1283 tx_desc->upper.data = 0; 1284 1285 i++; 1286 if (i == tx_ring->count) 1287 i = 0; 1288 } 1289 1290 if (i == tx_ring->next_to_use) 1291 break; 1292 eop = tx_ring->buffer_info[i].next_to_watch; 1293 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1294 } 1295 1296 tx_ring->next_to_clean = i; 1297 1298 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1299 1300 #define TX_WAKE_THRESHOLD 32 1301 if (count && netif_carrier_ok(netdev) && 1302 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1303 /* Make sure that anybody stopping the queue after this 1304 * sees the new next_to_clean. 1305 */ 1306 smp_mb(); 1307 1308 if (netif_queue_stopped(netdev) && 1309 !(test_bit(__E1000_DOWN, &adapter->state))) { 1310 netif_wake_queue(netdev); 1311 ++adapter->restart_queue; 1312 } 1313 } 1314 1315 if (adapter->detect_tx_hung) { 1316 /* Detect a transmit hang in hardware, this serializes the 1317 * check with the clearing of time_stamp and movement of i 1318 */ 1319 adapter->detect_tx_hung = false; 1320 if (tx_ring->buffer_info[i].time_stamp && 1321 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1322 + (adapter->tx_timeout_factor * HZ)) && 1323 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1324 schedule_work(&adapter->print_hang_task); 1325 else 1326 adapter->tx_hang_recheck = false; 1327 } 1328 adapter->total_tx_bytes += total_tx_bytes; 1329 adapter->total_tx_packets += total_tx_packets; 1330 return count < tx_ring->count; 1331 } 1332 1333 /** 1334 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1335 * @rx_ring: Rx descriptor ring 1336 * 1337 * the return value indicates whether actual cleaning was done, there 1338 * is no guarantee that everything was cleaned 1339 **/ 1340 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1341 int work_to_do) 1342 { 1343 struct e1000_adapter *adapter = rx_ring->adapter; 1344 struct e1000_hw *hw = &adapter->hw; 1345 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1346 struct net_device *netdev = adapter->netdev; 1347 struct pci_dev *pdev = adapter->pdev; 1348 struct e1000_buffer *buffer_info, *next_buffer; 1349 struct e1000_ps_page *ps_page; 1350 struct sk_buff *skb; 1351 unsigned int i, j; 1352 u32 length, staterr; 1353 int cleaned_count = 0; 1354 bool cleaned = false; 1355 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1356 1357 i = rx_ring->next_to_clean; 1358 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1359 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1360 buffer_info = &rx_ring->buffer_info[i]; 1361 1362 while (staterr & E1000_RXD_STAT_DD) { 1363 if (*work_done >= work_to_do) 1364 break; 1365 (*work_done)++; 1366 skb = buffer_info->skb; 1367 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1368 1369 /* in the packet split case this is header only */ 1370 prefetch(skb->data - NET_IP_ALIGN); 1371 1372 i++; 1373 if (i == rx_ring->count) 1374 i = 0; 1375 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1376 prefetch(next_rxd); 1377 1378 next_buffer = &rx_ring->buffer_info[i]; 1379 1380 cleaned = true; 1381 cleaned_count++; 1382 dma_unmap_single(&pdev->dev, buffer_info->dma, 1383 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1384 buffer_info->dma = 0; 1385 1386 /* see !EOP comment in other Rx routine */ 1387 if (!(staterr & E1000_RXD_STAT_EOP)) 1388 adapter->flags2 |= FLAG2_IS_DISCARDING; 1389 1390 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1391 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1392 dev_kfree_skb_irq(skb); 1393 if (staterr & E1000_RXD_STAT_EOP) 1394 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1395 goto next_desc; 1396 } 1397 1398 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1399 !(netdev->features & NETIF_F_RXALL))) { 1400 dev_kfree_skb_irq(skb); 1401 goto next_desc; 1402 } 1403 1404 length = le16_to_cpu(rx_desc->wb.middle.length0); 1405 1406 if (!length) { 1407 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1408 dev_kfree_skb_irq(skb); 1409 goto next_desc; 1410 } 1411 1412 /* Good Receive */ 1413 skb_put(skb, length); 1414 1415 { 1416 /* this looks ugly, but it seems compiler issues make 1417 * it more efficient than reusing j 1418 */ 1419 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1420 1421 /* page alloc/put takes too long and effects small 1422 * packet throughput, so unsplit small packets and 1423 * save the alloc/put only valid in softirq (napi) 1424 * context to call kmap_* 1425 */ 1426 if (l1 && (l1 <= copybreak) && 1427 ((length + l1) <= adapter->rx_ps_bsize0)) { 1428 u8 *vaddr; 1429 1430 ps_page = &buffer_info->ps_pages[0]; 1431 1432 /* there is no documentation about how to call 1433 * kmap_atomic, so we can't hold the mapping 1434 * very long 1435 */ 1436 dma_sync_single_for_cpu(&pdev->dev, 1437 ps_page->dma, 1438 PAGE_SIZE, 1439 DMA_FROM_DEVICE); 1440 vaddr = kmap_atomic(ps_page->page); 1441 memcpy(skb_tail_pointer(skb), vaddr, l1); 1442 kunmap_atomic(vaddr); 1443 dma_sync_single_for_device(&pdev->dev, 1444 ps_page->dma, 1445 PAGE_SIZE, 1446 DMA_FROM_DEVICE); 1447 1448 /* remove the CRC */ 1449 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1450 if (!(netdev->features & NETIF_F_RXFCS)) 1451 l1 -= 4; 1452 } 1453 1454 skb_put(skb, l1); 1455 goto copydone; 1456 } /* if */ 1457 } 1458 1459 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1460 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1461 if (!length) 1462 break; 1463 1464 ps_page = &buffer_info->ps_pages[j]; 1465 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1466 DMA_FROM_DEVICE); 1467 ps_page->dma = 0; 1468 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1469 ps_page->page = NULL; 1470 skb->len += length; 1471 skb->data_len += length; 1472 skb->truesize += PAGE_SIZE; 1473 } 1474 1475 /* strip the ethernet crc, problem is we're using pages now so 1476 * this whole operation can get a little cpu intensive 1477 */ 1478 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1479 if (!(netdev->features & NETIF_F_RXFCS)) 1480 pskb_trim(skb, skb->len - 4); 1481 } 1482 1483 copydone: 1484 total_rx_bytes += skb->len; 1485 total_rx_packets++; 1486 1487 e1000_rx_checksum(adapter, staterr, skb); 1488 1489 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1490 1491 if (rx_desc->wb.upper.header_status & 1492 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1493 adapter->rx_hdr_split++; 1494 1495 e1000_receive_skb(adapter, netdev, skb, staterr, 1496 rx_desc->wb.middle.vlan); 1497 1498 next_desc: 1499 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1500 buffer_info->skb = NULL; 1501 1502 /* return some buffers to hardware, one at a time is too slow */ 1503 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1504 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1505 GFP_ATOMIC); 1506 cleaned_count = 0; 1507 } 1508 1509 /* use prefetched values */ 1510 rx_desc = next_rxd; 1511 buffer_info = next_buffer; 1512 1513 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1514 } 1515 rx_ring->next_to_clean = i; 1516 1517 cleaned_count = e1000_desc_unused(rx_ring); 1518 if (cleaned_count) 1519 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1520 1521 adapter->total_rx_bytes += total_rx_bytes; 1522 adapter->total_rx_packets += total_rx_packets; 1523 return cleaned; 1524 } 1525 1526 /** 1527 * e1000_consume_page - helper function 1528 **/ 1529 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1530 u16 length) 1531 { 1532 bi->page = NULL; 1533 skb->len += length; 1534 skb->data_len += length; 1535 skb->truesize += PAGE_SIZE; 1536 } 1537 1538 /** 1539 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1540 * @adapter: board private structure 1541 * 1542 * the return value indicates whether actual cleaning was done, there 1543 * is no guarantee that everything was cleaned 1544 **/ 1545 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1546 int work_to_do) 1547 { 1548 struct e1000_adapter *adapter = rx_ring->adapter; 1549 struct net_device *netdev = adapter->netdev; 1550 struct pci_dev *pdev = adapter->pdev; 1551 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1552 struct e1000_buffer *buffer_info, *next_buffer; 1553 u32 length, staterr; 1554 unsigned int i; 1555 int cleaned_count = 0; 1556 bool cleaned = false; 1557 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1558 struct skb_shared_info *shinfo; 1559 1560 i = rx_ring->next_to_clean; 1561 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1562 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1563 buffer_info = &rx_ring->buffer_info[i]; 1564 1565 while (staterr & E1000_RXD_STAT_DD) { 1566 struct sk_buff *skb; 1567 1568 if (*work_done >= work_to_do) 1569 break; 1570 (*work_done)++; 1571 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1572 1573 skb = buffer_info->skb; 1574 buffer_info->skb = NULL; 1575 1576 ++i; 1577 if (i == rx_ring->count) 1578 i = 0; 1579 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1580 prefetch(next_rxd); 1581 1582 next_buffer = &rx_ring->buffer_info[i]; 1583 1584 cleaned = true; 1585 cleaned_count++; 1586 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1587 DMA_FROM_DEVICE); 1588 buffer_info->dma = 0; 1589 1590 length = le16_to_cpu(rx_desc->wb.upper.length); 1591 1592 /* errors is only valid for DD + EOP descriptors */ 1593 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1594 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1595 !(netdev->features & NETIF_F_RXALL)))) { 1596 /* recycle both page and skb */ 1597 buffer_info->skb = skb; 1598 /* an error means any chain goes out the window too */ 1599 if (rx_ring->rx_skb_top) 1600 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1601 rx_ring->rx_skb_top = NULL; 1602 goto next_desc; 1603 } 1604 #define rxtop (rx_ring->rx_skb_top) 1605 if (!(staterr & E1000_RXD_STAT_EOP)) { 1606 /* this descriptor is only the beginning (or middle) */ 1607 if (!rxtop) { 1608 /* this is the beginning of a chain */ 1609 rxtop = skb; 1610 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1611 0, length); 1612 } else { 1613 /* this is the middle of a chain */ 1614 shinfo = skb_shinfo(rxtop); 1615 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1616 buffer_info->page, 0, 1617 length); 1618 /* re-use the skb, only consumed the page */ 1619 buffer_info->skb = skb; 1620 } 1621 e1000_consume_page(buffer_info, rxtop, length); 1622 goto next_desc; 1623 } else { 1624 if (rxtop) { 1625 /* end of the chain */ 1626 shinfo = skb_shinfo(rxtop); 1627 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1628 buffer_info->page, 0, 1629 length); 1630 /* re-use the current skb, we only consumed the 1631 * page 1632 */ 1633 buffer_info->skb = skb; 1634 skb = rxtop; 1635 rxtop = NULL; 1636 e1000_consume_page(buffer_info, skb, length); 1637 } else { 1638 /* no chain, got EOP, this buf is the packet 1639 * copybreak to save the put_page/alloc_page 1640 */ 1641 if (length <= copybreak && 1642 skb_tailroom(skb) >= length) { 1643 u8 *vaddr; 1644 vaddr = kmap_atomic(buffer_info->page); 1645 memcpy(skb_tail_pointer(skb), vaddr, 1646 length); 1647 kunmap_atomic(vaddr); 1648 /* re-use the page, so don't erase 1649 * buffer_info->page 1650 */ 1651 skb_put(skb, length); 1652 } else { 1653 skb_fill_page_desc(skb, 0, 1654 buffer_info->page, 0, 1655 length); 1656 e1000_consume_page(buffer_info, skb, 1657 length); 1658 } 1659 } 1660 } 1661 1662 /* Receive Checksum Offload */ 1663 e1000_rx_checksum(adapter, staterr, skb); 1664 1665 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1666 1667 /* probably a little skewed due to removing CRC */ 1668 total_rx_bytes += skb->len; 1669 total_rx_packets++; 1670 1671 /* eth type trans needs skb->data to point to something */ 1672 if (!pskb_may_pull(skb, ETH_HLEN)) { 1673 e_err("pskb_may_pull failed.\n"); 1674 dev_kfree_skb_irq(skb); 1675 goto next_desc; 1676 } 1677 1678 e1000_receive_skb(adapter, netdev, skb, staterr, 1679 rx_desc->wb.upper.vlan); 1680 1681 next_desc: 1682 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1683 1684 /* return some buffers to hardware, one at a time is too slow */ 1685 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1686 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1687 GFP_ATOMIC); 1688 cleaned_count = 0; 1689 } 1690 1691 /* use prefetched values */ 1692 rx_desc = next_rxd; 1693 buffer_info = next_buffer; 1694 1695 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1696 } 1697 rx_ring->next_to_clean = i; 1698 1699 cleaned_count = e1000_desc_unused(rx_ring); 1700 if (cleaned_count) 1701 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1702 1703 adapter->total_rx_bytes += total_rx_bytes; 1704 adapter->total_rx_packets += total_rx_packets; 1705 return cleaned; 1706 } 1707 1708 /** 1709 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1710 * @rx_ring: Rx descriptor ring 1711 **/ 1712 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1713 { 1714 struct e1000_adapter *adapter = rx_ring->adapter; 1715 struct e1000_buffer *buffer_info; 1716 struct e1000_ps_page *ps_page; 1717 struct pci_dev *pdev = adapter->pdev; 1718 unsigned int i, j; 1719 1720 /* Free all the Rx ring sk_buffs */ 1721 for (i = 0; i < rx_ring->count; i++) { 1722 buffer_info = &rx_ring->buffer_info[i]; 1723 if (buffer_info->dma) { 1724 if (adapter->clean_rx == e1000_clean_rx_irq) 1725 dma_unmap_single(&pdev->dev, buffer_info->dma, 1726 adapter->rx_buffer_len, 1727 DMA_FROM_DEVICE); 1728 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1729 dma_unmap_page(&pdev->dev, buffer_info->dma, 1730 PAGE_SIZE, DMA_FROM_DEVICE); 1731 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1732 dma_unmap_single(&pdev->dev, buffer_info->dma, 1733 adapter->rx_ps_bsize0, 1734 DMA_FROM_DEVICE); 1735 buffer_info->dma = 0; 1736 } 1737 1738 if (buffer_info->page) { 1739 put_page(buffer_info->page); 1740 buffer_info->page = NULL; 1741 } 1742 1743 if (buffer_info->skb) { 1744 dev_kfree_skb(buffer_info->skb); 1745 buffer_info->skb = NULL; 1746 } 1747 1748 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1749 ps_page = &buffer_info->ps_pages[j]; 1750 if (!ps_page->page) 1751 break; 1752 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1753 DMA_FROM_DEVICE); 1754 ps_page->dma = 0; 1755 put_page(ps_page->page); 1756 ps_page->page = NULL; 1757 } 1758 } 1759 1760 /* there also may be some cached data from a chained receive */ 1761 if (rx_ring->rx_skb_top) { 1762 dev_kfree_skb(rx_ring->rx_skb_top); 1763 rx_ring->rx_skb_top = NULL; 1764 } 1765 1766 /* Zero out the descriptor ring */ 1767 memset(rx_ring->desc, 0, rx_ring->size); 1768 1769 rx_ring->next_to_clean = 0; 1770 rx_ring->next_to_use = 0; 1771 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1772 } 1773 1774 static void e1000e_downshift_workaround(struct work_struct *work) 1775 { 1776 struct e1000_adapter *adapter = container_of(work, 1777 struct e1000_adapter, 1778 downshift_task); 1779 1780 if (test_bit(__E1000_DOWN, &adapter->state)) 1781 return; 1782 1783 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1784 } 1785 1786 /** 1787 * e1000_intr_msi - Interrupt Handler 1788 * @irq: interrupt number 1789 * @data: pointer to a network interface device structure 1790 **/ 1791 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1792 { 1793 struct net_device *netdev = data; 1794 struct e1000_adapter *adapter = netdev_priv(netdev); 1795 struct e1000_hw *hw = &adapter->hw; 1796 u32 icr = er32(ICR); 1797 1798 /* read ICR disables interrupts using IAM */ 1799 if (icr & E1000_ICR_LSC) { 1800 hw->mac.get_link_status = true; 1801 /* ICH8 workaround-- Call gig speed drop workaround on cable 1802 * disconnect (LSC) before accessing any PHY registers 1803 */ 1804 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1805 (!(er32(STATUS) & E1000_STATUS_LU))) 1806 schedule_work(&adapter->downshift_task); 1807 1808 /* 80003ES2LAN workaround-- For packet buffer work-around on 1809 * link down event; disable receives here in the ISR and reset 1810 * adapter in watchdog 1811 */ 1812 if (netif_carrier_ok(netdev) && 1813 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1814 /* disable receives */ 1815 u32 rctl = er32(RCTL); 1816 1817 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1818 adapter->flags |= FLAG_RESTART_NOW; 1819 } 1820 /* guard against interrupt when we're going down */ 1821 if (!test_bit(__E1000_DOWN, &adapter->state)) 1822 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1823 } 1824 1825 /* Reset on uncorrectable ECC error */ 1826 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1827 u32 pbeccsts = er32(PBECCSTS); 1828 1829 adapter->corr_errors += 1830 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1831 adapter->uncorr_errors += 1832 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1833 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1834 1835 /* Do the reset outside of interrupt context */ 1836 schedule_work(&adapter->reset_task); 1837 1838 /* return immediately since reset is imminent */ 1839 return IRQ_HANDLED; 1840 } 1841 1842 if (napi_schedule_prep(&adapter->napi)) { 1843 adapter->total_tx_bytes = 0; 1844 adapter->total_tx_packets = 0; 1845 adapter->total_rx_bytes = 0; 1846 adapter->total_rx_packets = 0; 1847 __napi_schedule(&adapter->napi); 1848 } 1849 1850 return IRQ_HANDLED; 1851 } 1852 1853 /** 1854 * e1000_intr - Interrupt Handler 1855 * @irq: interrupt number 1856 * @data: pointer to a network interface device structure 1857 **/ 1858 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1859 { 1860 struct net_device *netdev = data; 1861 struct e1000_adapter *adapter = netdev_priv(netdev); 1862 struct e1000_hw *hw = &adapter->hw; 1863 u32 rctl, icr = er32(ICR); 1864 1865 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1866 return IRQ_NONE; /* Not our interrupt */ 1867 1868 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1869 * not set, then the adapter didn't send an interrupt 1870 */ 1871 if (!(icr & E1000_ICR_INT_ASSERTED)) 1872 return IRQ_NONE; 1873 1874 /* Interrupt Auto-Mask...upon reading ICR, 1875 * interrupts are masked. No need for the 1876 * IMC write 1877 */ 1878 1879 if (icr & E1000_ICR_LSC) { 1880 hw->mac.get_link_status = true; 1881 /* ICH8 workaround-- Call gig speed drop workaround on cable 1882 * disconnect (LSC) before accessing any PHY registers 1883 */ 1884 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1885 (!(er32(STATUS) & E1000_STATUS_LU))) 1886 schedule_work(&adapter->downshift_task); 1887 1888 /* 80003ES2LAN workaround-- 1889 * For packet buffer work-around on link down event; 1890 * disable receives here in the ISR and 1891 * reset adapter in watchdog 1892 */ 1893 if (netif_carrier_ok(netdev) && 1894 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1895 /* disable receives */ 1896 rctl = er32(RCTL); 1897 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1898 adapter->flags |= FLAG_RESTART_NOW; 1899 } 1900 /* guard against interrupt when we're going down */ 1901 if (!test_bit(__E1000_DOWN, &adapter->state)) 1902 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1903 } 1904 1905 /* Reset on uncorrectable ECC error */ 1906 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1907 u32 pbeccsts = er32(PBECCSTS); 1908 1909 adapter->corr_errors += 1910 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1911 adapter->uncorr_errors += 1912 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1913 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1914 1915 /* Do the reset outside of interrupt context */ 1916 schedule_work(&adapter->reset_task); 1917 1918 /* return immediately since reset is imminent */ 1919 return IRQ_HANDLED; 1920 } 1921 1922 if (napi_schedule_prep(&adapter->napi)) { 1923 adapter->total_tx_bytes = 0; 1924 adapter->total_tx_packets = 0; 1925 adapter->total_rx_bytes = 0; 1926 adapter->total_rx_packets = 0; 1927 __napi_schedule(&adapter->napi); 1928 } 1929 1930 return IRQ_HANDLED; 1931 } 1932 1933 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1934 { 1935 struct net_device *netdev = data; 1936 struct e1000_adapter *adapter = netdev_priv(netdev); 1937 struct e1000_hw *hw = &adapter->hw; 1938 u32 icr = er32(ICR); 1939 1940 if (icr & adapter->eiac_mask) 1941 ew32(ICS, (icr & adapter->eiac_mask)); 1942 1943 if (icr & E1000_ICR_LSC) { 1944 hw->mac.get_link_status = true; 1945 /* guard against interrupt when we're going down */ 1946 if (!test_bit(__E1000_DOWN, &adapter->state)) 1947 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1948 } 1949 1950 if (!test_bit(__E1000_DOWN, &adapter->state)) 1951 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1952 1953 return IRQ_HANDLED; 1954 } 1955 1956 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1957 { 1958 struct net_device *netdev = data; 1959 struct e1000_adapter *adapter = netdev_priv(netdev); 1960 struct e1000_hw *hw = &adapter->hw; 1961 struct e1000_ring *tx_ring = adapter->tx_ring; 1962 1963 adapter->total_tx_bytes = 0; 1964 adapter->total_tx_packets = 0; 1965 1966 if (!e1000_clean_tx_irq(tx_ring)) 1967 /* Ring was not completely cleaned, so fire another interrupt */ 1968 ew32(ICS, tx_ring->ims_val); 1969 1970 if (!test_bit(__E1000_DOWN, &adapter->state)) 1971 ew32(IMS, adapter->tx_ring->ims_val); 1972 1973 return IRQ_HANDLED; 1974 } 1975 1976 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1977 { 1978 struct net_device *netdev = data; 1979 struct e1000_adapter *adapter = netdev_priv(netdev); 1980 struct e1000_ring *rx_ring = adapter->rx_ring; 1981 1982 /* Write the ITR value calculated at the end of the 1983 * previous interrupt. 1984 */ 1985 if (rx_ring->set_itr) { 1986 u32 itr = rx_ring->itr_val ? 1987 1000000000 / (rx_ring->itr_val * 256) : 0; 1988 1989 writel(itr, rx_ring->itr_register); 1990 rx_ring->set_itr = 0; 1991 } 1992 1993 if (napi_schedule_prep(&adapter->napi)) { 1994 adapter->total_rx_bytes = 0; 1995 adapter->total_rx_packets = 0; 1996 __napi_schedule(&adapter->napi); 1997 } 1998 return IRQ_HANDLED; 1999 } 2000 2001 /** 2002 * e1000_configure_msix - Configure MSI-X hardware 2003 * 2004 * e1000_configure_msix sets up the hardware to properly 2005 * generate MSI-X interrupts. 2006 **/ 2007 static void e1000_configure_msix(struct e1000_adapter *adapter) 2008 { 2009 struct e1000_hw *hw = &adapter->hw; 2010 struct e1000_ring *rx_ring = adapter->rx_ring; 2011 struct e1000_ring *tx_ring = adapter->tx_ring; 2012 int vector = 0; 2013 u32 ctrl_ext, ivar = 0; 2014 2015 adapter->eiac_mask = 0; 2016 2017 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 2018 if (hw->mac.type == e1000_82574) { 2019 u32 rfctl = er32(RFCTL); 2020 2021 rfctl |= E1000_RFCTL_ACK_DIS; 2022 ew32(RFCTL, rfctl); 2023 } 2024 2025 /* Configure Rx vector */ 2026 rx_ring->ims_val = E1000_IMS_RXQ0; 2027 adapter->eiac_mask |= rx_ring->ims_val; 2028 if (rx_ring->itr_val) 2029 writel(1000000000 / (rx_ring->itr_val * 256), 2030 rx_ring->itr_register); 2031 else 2032 writel(1, rx_ring->itr_register); 2033 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 2034 2035 /* Configure Tx vector */ 2036 tx_ring->ims_val = E1000_IMS_TXQ0; 2037 vector++; 2038 if (tx_ring->itr_val) 2039 writel(1000000000 / (tx_ring->itr_val * 256), 2040 tx_ring->itr_register); 2041 else 2042 writel(1, tx_ring->itr_register); 2043 adapter->eiac_mask |= tx_ring->ims_val; 2044 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2045 2046 /* set vector for Other Causes, e.g. link changes */ 2047 vector++; 2048 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2049 if (rx_ring->itr_val) 2050 writel(1000000000 / (rx_ring->itr_val * 256), 2051 hw->hw_addr + E1000_EITR_82574(vector)); 2052 else 2053 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2054 2055 /* Cause Tx interrupts on every write back */ 2056 ivar |= BIT(31); 2057 2058 ew32(IVAR, ivar); 2059 2060 /* enable MSI-X PBA support */ 2061 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2062 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2063 ew32(CTRL_EXT, ctrl_ext); 2064 e1e_flush(); 2065 } 2066 2067 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2068 { 2069 if (adapter->msix_entries) { 2070 pci_disable_msix(adapter->pdev); 2071 kfree(adapter->msix_entries); 2072 adapter->msix_entries = NULL; 2073 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2074 pci_disable_msi(adapter->pdev); 2075 adapter->flags &= ~FLAG_MSI_ENABLED; 2076 } 2077 } 2078 2079 /** 2080 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2081 * 2082 * Attempt to configure interrupts using the best available 2083 * capabilities of the hardware and kernel. 2084 **/ 2085 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2086 { 2087 int err; 2088 int i; 2089 2090 switch (adapter->int_mode) { 2091 case E1000E_INT_MODE_MSIX: 2092 if (adapter->flags & FLAG_HAS_MSIX) { 2093 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2094 adapter->msix_entries = kcalloc(adapter->num_vectors, 2095 sizeof(struct 2096 msix_entry), 2097 GFP_KERNEL); 2098 if (adapter->msix_entries) { 2099 struct e1000_adapter *a = adapter; 2100 2101 for (i = 0; i < adapter->num_vectors; i++) 2102 adapter->msix_entries[i].entry = i; 2103 2104 err = pci_enable_msix_range(a->pdev, 2105 a->msix_entries, 2106 a->num_vectors, 2107 a->num_vectors); 2108 if (err > 0) 2109 return; 2110 } 2111 /* MSI-X failed, so fall through and try MSI */ 2112 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2113 e1000e_reset_interrupt_capability(adapter); 2114 } 2115 adapter->int_mode = E1000E_INT_MODE_MSI; 2116 /* Fall through */ 2117 case E1000E_INT_MODE_MSI: 2118 if (!pci_enable_msi(adapter->pdev)) { 2119 adapter->flags |= FLAG_MSI_ENABLED; 2120 } else { 2121 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2122 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2123 } 2124 /* Fall through */ 2125 case E1000E_INT_MODE_LEGACY: 2126 /* Don't do anything; this is the system default */ 2127 break; 2128 } 2129 2130 /* store the number of vectors being used */ 2131 adapter->num_vectors = 1; 2132 } 2133 2134 /** 2135 * e1000_request_msix - Initialize MSI-X interrupts 2136 * 2137 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2138 * kernel. 2139 **/ 2140 static int e1000_request_msix(struct e1000_adapter *adapter) 2141 { 2142 struct net_device *netdev = adapter->netdev; 2143 int err = 0, vector = 0; 2144 2145 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2146 snprintf(adapter->rx_ring->name, 2147 sizeof(adapter->rx_ring->name) - 1, 2148 "%.14s-rx-0", netdev->name); 2149 else 2150 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2151 err = request_irq(adapter->msix_entries[vector].vector, 2152 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2153 netdev); 2154 if (err) 2155 return err; 2156 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2157 E1000_EITR_82574(vector); 2158 adapter->rx_ring->itr_val = adapter->itr; 2159 vector++; 2160 2161 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2162 snprintf(adapter->tx_ring->name, 2163 sizeof(adapter->tx_ring->name) - 1, 2164 "%.14s-tx-0", netdev->name); 2165 else 2166 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2167 err = request_irq(adapter->msix_entries[vector].vector, 2168 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2169 netdev); 2170 if (err) 2171 return err; 2172 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2173 E1000_EITR_82574(vector); 2174 adapter->tx_ring->itr_val = adapter->itr; 2175 vector++; 2176 2177 err = request_irq(adapter->msix_entries[vector].vector, 2178 e1000_msix_other, 0, netdev->name, netdev); 2179 if (err) 2180 return err; 2181 2182 e1000_configure_msix(adapter); 2183 2184 return 0; 2185 } 2186 2187 /** 2188 * e1000_request_irq - initialize interrupts 2189 * 2190 * Attempts to configure interrupts using the best available 2191 * capabilities of the hardware and kernel. 2192 **/ 2193 static int e1000_request_irq(struct e1000_adapter *adapter) 2194 { 2195 struct net_device *netdev = adapter->netdev; 2196 int err; 2197 2198 if (adapter->msix_entries) { 2199 err = e1000_request_msix(adapter); 2200 if (!err) 2201 return err; 2202 /* fall back to MSI */ 2203 e1000e_reset_interrupt_capability(adapter); 2204 adapter->int_mode = E1000E_INT_MODE_MSI; 2205 e1000e_set_interrupt_capability(adapter); 2206 } 2207 if (adapter->flags & FLAG_MSI_ENABLED) { 2208 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2209 netdev->name, netdev); 2210 if (!err) 2211 return err; 2212 2213 /* fall back to legacy interrupt */ 2214 e1000e_reset_interrupt_capability(adapter); 2215 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2216 } 2217 2218 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2219 netdev->name, netdev); 2220 if (err) 2221 e_err("Unable to allocate interrupt, Error: %d\n", err); 2222 2223 return err; 2224 } 2225 2226 static void e1000_free_irq(struct e1000_adapter *adapter) 2227 { 2228 struct net_device *netdev = adapter->netdev; 2229 2230 if (adapter->msix_entries) { 2231 int vector = 0; 2232 2233 free_irq(adapter->msix_entries[vector].vector, netdev); 2234 vector++; 2235 2236 free_irq(adapter->msix_entries[vector].vector, netdev); 2237 vector++; 2238 2239 /* Other Causes interrupt vector */ 2240 free_irq(adapter->msix_entries[vector].vector, netdev); 2241 return; 2242 } 2243 2244 free_irq(adapter->pdev->irq, netdev); 2245 } 2246 2247 /** 2248 * e1000_irq_disable - Mask off interrupt generation on the NIC 2249 **/ 2250 static void e1000_irq_disable(struct e1000_adapter *adapter) 2251 { 2252 struct e1000_hw *hw = &adapter->hw; 2253 2254 ew32(IMC, ~0); 2255 if (adapter->msix_entries) 2256 ew32(EIAC_82574, 0); 2257 e1e_flush(); 2258 2259 if (adapter->msix_entries) { 2260 int i; 2261 2262 for (i = 0; i < adapter->num_vectors; i++) 2263 synchronize_irq(adapter->msix_entries[i].vector); 2264 } else { 2265 synchronize_irq(adapter->pdev->irq); 2266 } 2267 } 2268 2269 /** 2270 * e1000_irq_enable - Enable default interrupt generation settings 2271 **/ 2272 static void e1000_irq_enable(struct e1000_adapter *adapter) 2273 { 2274 struct e1000_hw *hw = &adapter->hw; 2275 2276 if (adapter->msix_entries) { 2277 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2278 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2279 IMS_OTHER_MASK); 2280 } else if (hw->mac.type >= e1000_pch_lpt) { 2281 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2282 } else { 2283 ew32(IMS, IMS_ENABLE_MASK); 2284 } 2285 e1e_flush(); 2286 } 2287 2288 /** 2289 * e1000e_get_hw_control - get control of the h/w from f/w 2290 * @adapter: address of board private structure 2291 * 2292 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2293 * For ASF and Pass Through versions of f/w this means that 2294 * the driver is loaded. For AMT version (only with 82573) 2295 * of the f/w this means that the network i/f is open. 2296 **/ 2297 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2298 { 2299 struct e1000_hw *hw = &adapter->hw; 2300 u32 ctrl_ext; 2301 u32 swsm; 2302 2303 /* Let firmware know the driver has taken over */ 2304 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2305 swsm = er32(SWSM); 2306 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2307 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2308 ctrl_ext = er32(CTRL_EXT); 2309 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2310 } 2311 } 2312 2313 /** 2314 * e1000e_release_hw_control - release control of the h/w to f/w 2315 * @adapter: address of board private structure 2316 * 2317 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2318 * For ASF and Pass Through versions of f/w this means that the 2319 * driver is no longer loaded. For AMT version (only with 82573) i 2320 * of the f/w this means that the network i/f is closed. 2321 * 2322 **/ 2323 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2324 { 2325 struct e1000_hw *hw = &adapter->hw; 2326 u32 ctrl_ext; 2327 u32 swsm; 2328 2329 /* Let firmware taken over control of h/w */ 2330 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2331 swsm = er32(SWSM); 2332 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2333 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2334 ctrl_ext = er32(CTRL_EXT); 2335 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2336 } 2337 } 2338 2339 /** 2340 * e1000_alloc_ring_dma - allocate memory for a ring structure 2341 **/ 2342 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2343 struct e1000_ring *ring) 2344 { 2345 struct pci_dev *pdev = adapter->pdev; 2346 2347 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2348 GFP_KERNEL); 2349 if (!ring->desc) 2350 return -ENOMEM; 2351 2352 return 0; 2353 } 2354 2355 /** 2356 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2357 * @tx_ring: Tx descriptor ring 2358 * 2359 * Return 0 on success, negative on failure 2360 **/ 2361 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2362 { 2363 struct e1000_adapter *adapter = tx_ring->adapter; 2364 int err = -ENOMEM, size; 2365 2366 size = sizeof(struct e1000_buffer) * tx_ring->count; 2367 tx_ring->buffer_info = vzalloc(size); 2368 if (!tx_ring->buffer_info) 2369 goto err; 2370 2371 /* round up to nearest 4K */ 2372 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2373 tx_ring->size = ALIGN(tx_ring->size, 4096); 2374 2375 err = e1000_alloc_ring_dma(adapter, tx_ring); 2376 if (err) 2377 goto err; 2378 2379 tx_ring->next_to_use = 0; 2380 tx_ring->next_to_clean = 0; 2381 2382 return 0; 2383 err: 2384 vfree(tx_ring->buffer_info); 2385 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2386 return err; 2387 } 2388 2389 /** 2390 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2391 * @rx_ring: Rx descriptor ring 2392 * 2393 * Returns 0 on success, negative on failure 2394 **/ 2395 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2396 { 2397 struct e1000_adapter *adapter = rx_ring->adapter; 2398 struct e1000_buffer *buffer_info; 2399 int i, size, desc_len, err = -ENOMEM; 2400 2401 size = sizeof(struct e1000_buffer) * rx_ring->count; 2402 rx_ring->buffer_info = vzalloc(size); 2403 if (!rx_ring->buffer_info) 2404 goto err; 2405 2406 for (i = 0; i < rx_ring->count; i++) { 2407 buffer_info = &rx_ring->buffer_info[i]; 2408 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2409 sizeof(struct e1000_ps_page), 2410 GFP_KERNEL); 2411 if (!buffer_info->ps_pages) 2412 goto err_pages; 2413 } 2414 2415 desc_len = sizeof(union e1000_rx_desc_packet_split); 2416 2417 /* Round up to nearest 4K */ 2418 rx_ring->size = rx_ring->count * desc_len; 2419 rx_ring->size = ALIGN(rx_ring->size, 4096); 2420 2421 err = e1000_alloc_ring_dma(adapter, rx_ring); 2422 if (err) 2423 goto err_pages; 2424 2425 rx_ring->next_to_clean = 0; 2426 rx_ring->next_to_use = 0; 2427 rx_ring->rx_skb_top = NULL; 2428 2429 return 0; 2430 2431 err_pages: 2432 for (i = 0; i < rx_ring->count; i++) { 2433 buffer_info = &rx_ring->buffer_info[i]; 2434 kfree(buffer_info->ps_pages); 2435 } 2436 err: 2437 vfree(rx_ring->buffer_info); 2438 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2439 return err; 2440 } 2441 2442 /** 2443 * e1000_clean_tx_ring - Free Tx Buffers 2444 * @tx_ring: Tx descriptor ring 2445 **/ 2446 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2447 { 2448 struct e1000_adapter *adapter = tx_ring->adapter; 2449 struct e1000_buffer *buffer_info; 2450 unsigned long size; 2451 unsigned int i; 2452 2453 for (i = 0; i < tx_ring->count; i++) { 2454 buffer_info = &tx_ring->buffer_info[i]; 2455 e1000_put_txbuf(tx_ring, buffer_info, false); 2456 } 2457 2458 netdev_reset_queue(adapter->netdev); 2459 size = sizeof(struct e1000_buffer) * tx_ring->count; 2460 memset(tx_ring->buffer_info, 0, size); 2461 2462 memset(tx_ring->desc, 0, tx_ring->size); 2463 2464 tx_ring->next_to_use = 0; 2465 tx_ring->next_to_clean = 0; 2466 } 2467 2468 /** 2469 * e1000e_free_tx_resources - Free Tx Resources per Queue 2470 * @tx_ring: Tx descriptor ring 2471 * 2472 * Free all transmit software resources 2473 **/ 2474 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2475 { 2476 struct e1000_adapter *adapter = tx_ring->adapter; 2477 struct pci_dev *pdev = adapter->pdev; 2478 2479 e1000_clean_tx_ring(tx_ring); 2480 2481 vfree(tx_ring->buffer_info); 2482 tx_ring->buffer_info = NULL; 2483 2484 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2485 tx_ring->dma); 2486 tx_ring->desc = NULL; 2487 } 2488 2489 /** 2490 * e1000e_free_rx_resources - Free Rx Resources 2491 * @rx_ring: Rx descriptor ring 2492 * 2493 * Free all receive software resources 2494 **/ 2495 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2496 { 2497 struct e1000_adapter *adapter = rx_ring->adapter; 2498 struct pci_dev *pdev = adapter->pdev; 2499 int i; 2500 2501 e1000_clean_rx_ring(rx_ring); 2502 2503 for (i = 0; i < rx_ring->count; i++) 2504 kfree(rx_ring->buffer_info[i].ps_pages); 2505 2506 vfree(rx_ring->buffer_info); 2507 rx_ring->buffer_info = NULL; 2508 2509 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2510 rx_ring->dma); 2511 rx_ring->desc = NULL; 2512 } 2513 2514 /** 2515 * e1000_update_itr - update the dynamic ITR value based on statistics 2516 * @adapter: pointer to adapter 2517 * @itr_setting: current adapter->itr 2518 * @packets: the number of packets during this measurement interval 2519 * @bytes: the number of bytes during this measurement interval 2520 * 2521 * Stores a new ITR value based on packets and byte 2522 * counts during the last interrupt. The advantage of per interrupt 2523 * computation is faster updates and more accurate ITR for the current 2524 * traffic pattern. Constants in this function were computed 2525 * based on theoretical maximum wire speed and thresholds were set based 2526 * on testing data as well as attempting to minimize response time 2527 * while increasing bulk throughput. This functionality is controlled 2528 * by the InterruptThrottleRate module parameter. 2529 **/ 2530 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2531 { 2532 unsigned int retval = itr_setting; 2533 2534 if (packets == 0) 2535 return itr_setting; 2536 2537 switch (itr_setting) { 2538 case lowest_latency: 2539 /* handle TSO and jumbo frames */ 2540 if (bytes / packets > 8000) 2541 retval = bulk_latency; 2542 else if ((packets < 5) && (bytes > 512)) 2543 retval = low_latency; 2544 break; 2545 case low_latency: /* 50 usec aka 20000 ints/s */ 2546 if (bytes > 10000) { 2547 /* this if handles the TSO accounting */ 2548 if (bytes / packets > 8000) 2549 retval = bulk_latency; 2550 else if ((packets < 10) || ((bytes / packets) > 1200)) 2551 retval = bulk_latency; 2552 else if ((packets > 35)) 2553 retval = lowest_latency; 2554 } else if (bytes / packets > 2000) { 2555 retval = bulk_latency; 2556 } else if (packets <= 2 && bytes < 512) { 2557 retval = lowest_latency; 2558 } 2559 break; 2560 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2561 if (bytes > 25000) { 2562 if (packets > 35) 2563 retval = low_latency; 2564 } else if (bytes < 6000) { 2565 retval = low_latency; 2566 } 2567 break; 2568 } 2569 2570 return retval; 2571 } 2572 2573 static void e1000_set_itr(struct e1000_adapter *adapter) 2574 { 2575 u16 current_itr; 2576 u32 new_itr = adapter->itr; 2577 2578 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2579 if (adapter->link_speed != SPEED_1000) { 2580 current_itr = 0; 2581 new_itr = 4000; 2582 goto set_itr_now; 2583 } 2584 2585 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2586 new_itr = 0; 2587 goto set_itr_now; 2588 } 2589 2590 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2591 adapter->total_tx_packets, 2592 adapter->total_tx_bytes); 2593 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2594 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2595 adapter->tx_itr = low_latency; 2596 2597 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2598 adapter->total_rx_packets, 2599 adapter->total_rx_bytes); 2600 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2601 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2602 adapter->rx_itr = low_latency; 2603 2604 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2605 2606 /* counts and packets in update_itr are dependent on these numbers */ 2607 switch (current_itr) { 2608 case lowest_latency: 2609 new_itr = 70000; 2610 break; 2611 case low_latency: 2612 new_itr = 20000; /* aka hwitr = ~200 */ 2613 break; 2614 case bulk_latency: 2615 new_itr = 4000; 2616 break; 2617 default: 2618 break; 2619 } 2620 2621 set_itr_now: 2622 if (new_itr != adapter->itr) { 2623 /* this attempts to bias the interrupt rate towards Bulk 2624 * by adding intermediate steps when interrupt rate is 2625 * increasing 2626 */ 2627 new_itr = new_itr > adapter->itr ? 2628 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2629 adapter->itr = new_itr; 2630 adapter->rx_ring->itr_val = new_itr; 2631 if (adapter->msix_entries) 2632 adapter->rx_ring->set_itr = 1; 2633 else 2634 e1000e_write_itr(adapter, new_itr); 2635 } 2636 } 2637 2638 /** 2639 * e1000e_write_itr - write the ITR value to the appropriate registers 2640 * @adapter: address of board private structure 2641 * @itr: new ITR value to program 2642 * 2643 * e1000e_write_itr determines if the adapter is in MSI-X mode 2644 * and, if so, writes the EITR registers with the ITR value. 2645 * Otherwise, it writes the ITR value into the ITR register. 2646 **/ 2647 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2648 { 2649 struct e1000_hw *hw = &adapter->hw; 2650 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2651 2652 if (adapter->msix_entries) { 2653 int vector; 2654 2655 for (vector = 0; vector < adapter->num_vectors; vector++) 2656 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2657 } else { 2658 ew32(ITR, new_itr); 2659 } 2660 } 2661 2662 /** 2663 * e1000_alloc_queues - Allocate memory for all rings 2664 * @adapter: board private structure to initialize 2665 **/ 2666 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2667 { 2668 int size = sizeof(struct e1000_ring); 2669 2670 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2671 if (!adapter->tx_ring) 2672 goto err; 2673 adapter->tx_ring->count = adapter->tx_ring_count; 2674 adapter->tx_ring->adapter = adapter; 2675 2676 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2677 if (!adapter->rx_ring) 2678 goto err; 2679 adapter->rx_ring->count = adapter->rx_ring_count; 2680 adapter->rx_ring->adapter = adapter; 2681 2682 return 0; 2683 err: 2684 e_err("Unable to allocate memory for queues\n"); 2685 kfree(adapter->rx_ring); 2686 kfree(adapter->tx_ring); 2687 return -ENOMEM; 2688 } 2689 2690 /** 2691 * e1000e_poll - NAPI Rx polling callback 2692 * @napi: struct associated with this polling callback 2693 * @budget: number of packets driver is allowed to process this poll 2694 **/ 2695 static int e1000e_poll(struct napi_struct *napi, int budget) 2696 { 2697 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2698 napi); 2699 struct e1000_hw *hw = &adapter->hw; 2700 struct net_device *poll_dev = adapter->netdev; 2701 int tx_cleaned = 1, work_done = 0; 2702 2703 adapter = netdev_priv(poll_dev); 2704 2705 if (!adapter->msix_entries || 2706 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2707 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2708 2709 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2710 2711 if (!tx_cleaned || work_done == budget) 2712 return budget; 2713 2714 /* Exit the polling mode, but don't re-enable interrupts if stack might 2715 * poll us due to busy-polling 2716 */ 2717 if (likely(napi_complete_done(napi, work_done))) { 2718 if (adapter->itr_setting & 3) 2719 e1000_set_itr(adapter); 2720 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2721 if (adapter->msix_entries) 2722 ew32(IMS, adapter->rx_ring->ims_val); 2723 else 2724 e1000_irq_enable(adapter); 2725 } 2726 } 2727 2728 return work_done; 2729 } 2730 2731 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2732 __always_unused __be16 proto, u16 vid) 2733 { 2734 struct e1000_adapter *adapter = netdev_priv(netdev); 2735 struct e1000_hw *hw = &adapter->hw; 2736 u32 vfta, index; 2737 2738 /* don't update vlan cookie if already programmed */ 2739 if ((adapter->hw.mng_cookie.status & 2740 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2741 (vid == adapter->mng_vlan_id)) 2742 return 0; 2743 2744 /* add VID to filter table */ 2745 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2746 index = (vid >> 5) & 0x7F; 2747 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2748 vfta |= BIT((vid & 0x1F)); 2749 hw->mac.ops.write_vfta(hw, index, vfta); 2750 } 2751 2752 set_bit(vid, adapter->active_vlans); 2753 2754 return 0; 2755 } 2756 2757 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2758 __always_unused __be16 proto, u16 vid) 2759 { 2760 struct e1000_adapter *adapter = netdev_priv(netdev); 2761 struct e1000_hw *hw = &adapter->hw; 2762 u32 vfta, index; 2763 2764 if ((adapter->hw.mng_cookie.status & 2765 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2766 (vid == adapter->mng_vlan_id)) { 2767 /* release control to f/w */ 2768 e1000e_release_hw_control(adapter); 2769 return 0; 2770 } 2771 2772 /* remove VID from filter table */ 2773 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2774 index = (vid >> 5) & 0x7F; 2775 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2776 vfta &= ~BIT((vid & 0x1F)); 2777 hw->mac.ops.write_vfta(hw, index, vfta); 2778 } 2779 2780 clear_bit(vid, adapter->active_vlans); 2781 2782 return 0; 2783 } 2784 2785 /** 2786 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2787 * @adapter: board private structure to initialize 2788 **/ 2789 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2790 { 2791 struct net_device *netdev = adapter->netdev; 2792 struct e1000_hw *hw = &adapter->hw; 2793 u32 rctl; 2794 2795 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2796 /* disable VLAN receive filtering */ 2797 rctl = er32(RCTL); 2798 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2799 ew32(RCTL, rctl); 2800 2801 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2802 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2803 adapter->mng_vlan_id); 2804 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2805 } 2806 } 2807 } 2808 2809 /** 2810 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2811 * @adapter: board private structure to initialize 2812 **/ 2813 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2814 { 2815 struct e1000_hw *hw = &adapter->hw; 2816 u32 rctl; 2817 2818 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2819 /* enable VLAN receive filtering */ 2820 rctl = er32(RCTL); 2821 rctl |= E1000_RCTL_VFE; 2822 rctl &= ~E1000_RCTL_CFIEN; 2823 ew32(RCTL, rctl); 2824 } 2825 } 2826 2827 /** 2828 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2829 * @adapter: board private structure to initialize 2830 **/ 2831 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2832 { 2833 struct e1000_hw *hw = &adapter->hw; 2834 u32 ctrl; 2835 2836 /* disable VLAN tag insert/strip */ 2837 ctrl = er32(CTRL); 2838 ctrl &= ~E1000_CTRL_VME; 2839 ew32(CTRL, ctrl); 2840 } 2841 2842 /** 2843 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2844 * @adapter: board private structure to initialize 2845 **/ 2846 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2847 { 2848 struct e1000_hw *hw = &adapter->hw; 2849 u32 ctrl; 2850 2851 /* enable VLAN tag insert/strip */ 2852 ctrl = er32(CTRL); 2853 ctrl |= E1000_CTRL_VME; 2854 ew32(CTRL, ctrl); 2855 } 2856 2857 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2858 { 2859 struct net_device *netdev = adapter->netdev; 2860 u16 vid = adapter->hw.mng_cookie.vlan_id; 2861 u16 old_vid = adapter->mng_vlan_id; 2862 2863 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2864 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2865 adapter->mng_vlan_id = vid; 2866 } 2867 2868 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2869 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2870 } 2871 2872 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2873 { 2874 u16 vid; 2875 2876 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2877 2878 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2879 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2880 } 2881 2882 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2883 { 2884 struct e1000_hw *hw = &adapter->hw; 2885 u32 manc, manc2h, mdef, i, j; 2886 2887 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2888 return; 2889 2890 manc = er32(MANC); 2891 2892 /* enable receiving management packets to the host. this will probably 2893 * generate destination unreachable messages from the host OS, but 2894 * the packets will be handled on SMBUS 2895 */ 2896 manc |= E1000_MANC_EN_MNG2HOST; 2897 manc2h = er32(MANC2H); 2898 2899 switch (hw->mac.type) { 2900 default: 2901 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2902 break; 2903 case e1000_82574: 2904 case e1000_82583: 2905 /* Check if IPMI pass-through decision filter already exists; 2906 * if so, enable it. 2907 */ 2908 for (i = 0, j = 0; i < 8; i++) { 2909 mdef = er32(MDEF(i)); 2910 2911 /* Ignore filters with anything other than IPMI ports */ 2912 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2913 continue; 2914 2915 /* Enable this decision filter in MANC2H */ 2916 if (mdef) 2917 manc2h |= BIT(i); 2918 2919 j |= mdef; 2920 } 2921 2922 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2923 break; 2924 2925 /* Create new decision filter in an empty filter */ 2926 for (i = 0, j = 0; i < 8; i++) 2927 if (er32(MDEF(i)) == 0) { 2928 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2929 E1000_MDEF_PORT_664)); 2930 manc2h |= BIT(1); 2931 j++; 2932 break; 2933 } 2934 2935 if (!j) 2936 e_warn("Unable to create IPMI pass-through filter\n"); 2937 break; 2938 } 2939 2940 ew32(MANC2H, manc2h); 2941 ew32(MANC, manc); 2942 } 2943 2944 /** 2945 * e1000_configure_tx - Configure Transmit Unit after Reset 2946 * @adapter: board private structure 2947 * 2948 * Configure the Tx unit of the MAC after a reset. 2949 **/ 2950 static void e1000_configure_tx(struct e1000_adapter *adapter) 2951 { 2952 struct e1000_hw *hw = &adapter->hw; 2953 struct e1000_ring *tx_ring = adapter->tx_ring; 2954 u64 tdba; 2955 u32 tdlen, tctl, tarc; 2956 2957 /* Setup the HW Tx Head and Tail descriptor pointers */ 2958 tdba = tx_ring->dma; 2959 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2960 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2961 ew32(TDBAH(0), (tdba >> 32)); 2962 ew32(TDLEN(0), tdlen); 2963 ew32(TDH(0), 0); 2964 ew32(TDT(0), 0); 2965 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2966 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2967 2968 writel(0, tx_ring->head); 2969 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2970 e1000e_update_tdt_wa(tx_ring, 0); 2971 else 2972 writel(0, tx_ring->tail); 2973 2974 /* Set the Tx Interrupt Delay register */ 2975 ew32(TIDV, adapter->tx_int_delay); 2976 /* Tx irq moderation */ 2977 ew32(TADV, adapter->tx_abs_int_delay); 2978 2979 if (adapter->flags2 & FLAG2_DMA_BURST) { 2980 u32 txdctl = er32(TXDCTL(0)); 2981 2982 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2983 E1000_TXDCTL_WTHRESH); 2984 /* set up some performance related parameters to encourage the 2985 * hardware to use the bus more efficiently in bursts, depends 2986 * on the tx_int_delay to be enabled, 2987 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2988 * hthresh = 1 ==> prefetch when one or more available 2989 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2990 * BEWARE: this seems to work but should be considered first if 2991 * there are Tx hangs or other Tx related bugs 2992 */ 2993 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2994 ew32(TXDCTL(0), txdctl); 2995 } 2996 /* erratum work around: set txdctl the same for both queues */ 2997 ew32(TXDCTL(1), er32(TXDCTL(0))); 2998 2999 /* Program the Transmit Control Register */ 3000 tctl = er32(TCTL); 3001 tctl &= ~E1000_TCTL_CT; 3002 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3003 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3004 3005 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 3006 tarc = er32(TARC(0)); 3007 /* set the speed mode bit, we'll clear it if we're not at 3008 * gigabit link later 3009 */ 3010 #define SPEED_MODE_BIT BIT(21) 3011 tarc |= SPEED_MODE_BIT; 3012 ew32(TARC(0), tarc); 3013 } 3014 3015 /* errata: program both queues to unweighted RR */ 3016 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 3017 tarc = er32(TARC(0)); 3018 tarc |= 1; 3019 ew32(TARC(0), tarc); 3020 tarc = er32(TARC(1)); 3021 tarc |= 1; 3022 ew32(TARC(1), tarc); 3023 } 3024 3025 /* Setup Transmit Descriptor Settings for eop descriptor */ 3026 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 3027 3028 /* only set IDE if we are delaying interrupts using the timers */ 3029 if (adapter->tx_int_delay) 3030 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3031 3032 /* enable Report Status bit */ 3033 adapter->txd_cmd |= E1000_TXD_CMD_RS; 3034 3035 ew32(TCTL, tctl); 3036 3037 hw->mac.ops.config_collision_dist(hw); 3038 3039 /* SPT and KBL Si errata workaround to avoid data corruption */ 3040 if (hw->mac.type == e1000_pch_spt) { 3041 u32 reg_val; 3042 3043 reg_val = er32(IOSFPC); 3044 reg_val |= E1000_RCTL_RDMTS_HEX; 3045 ew32(IOSFPC, reg_val); 3046 3047 reg_val = er32(TARC(0)); 3048 /* SPT and KBL Si errata workaround to avoid Tx hang. 3049 * Dropping the number of outstanding requests from 3050 * 3 to 2 in order to avoid a buffer overrun. 3051 */ 3052 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3053 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3054 ew32(TARC(0), reg_val); 3055 } 3056 } 3057 3058 /** 3059 * e1000_setup_rctl - configure the receive control registers 3060 * @adapter: Board private structure 3061 **/ 3062 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3063 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3064 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3065 { 3066 struct e1000_hw *hw = &adapter->hw; 3067 u32 rctl, rfctl; 3068 u32 pages = 0; 3069 3070 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3071 * If jumbo frames not set, program related MAC/PHY registers 3072 * to h/w defaults 3073 */ 3074 if (hw->mac.type >= e1000_pch2lan) { 3075 s32 ret_val; 3076 3077 if (adapter->netdev->mtu > ETH_DATA_LEN) 3078 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3079 else 3080 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3081 3082 if (ret_val) 3083 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3084 } 3085 3086 /* Program MC offset vector base */ 3087 rctl = er32(RCTL); 3088 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3089 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3090 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3091 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3092 3093 /* Do not Store bad packets */ 3094 rctl &= ~E1000_RCTL_SBP; 3095 3096 /* Enable Long Packet receive */ 3097 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3098 rctl &= ~E1000_RCTL_LPE; 3099 else 3100 rctl |= E1000_RCTL_LPE; 3101 3102 /* Some systems expect that the CRC is included in SMBUS traffic. The 3103 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3104 * host memory when this is enabled 3105 */ 3106 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3107 rctl |= E1000_RCTL_SECRC; 3108 3109 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3110 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3111 u16 phy_data; 3112 3113 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3114 phy_data &= 0xfff8; 3115 phy_data |= BIT(2); 3116 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3117 3118 e1e_rphy(hw, 22, &phy_data); 3119 phy_data &= 0x0fff; 3120 phy_data |= BIT(14); 3121 e1e_wphy(hw, 0x10, 0x2823); 3122 e1e_wphy(hw, 0x11, 0x0003); 3123 e1e_wphy(hw, 22, phy_data); 3124 } 3125 3126 /* Setup buffer sizes */ 3127 rctl &= ~E1000_RCTL_SZ_4096; 3128 rctl |= E1000_RCTL_BSEX; 3129 switch (adapter->rx_buffer_len) { 3130 case 2048: 3131 default: 3132 rctl |= E1000_RCTL_SZ_2048; 3133 rctl &= ~E1000_RCTL_BSEX; 3134 break; 3135 case 4096: 3136 rctl |= E1000_RCTL_SZ_4096; 3137 break; 3138 case 8192: 3139 rctl |= E1000_RCTL_SZ_8192; 3140 break; 3141 case 16384: 3142 rctl |= E1000_RCTL_SZ_16384; 3143 break; 3144 } 3145 3146 /* Enable Extended Status in all Receive Descriptors */ 3147 rfctl = er32(RFCTL); 3148 rfctl |= E1000_RFCTL_EXTEN; 3149 ew32(RFCTL, rfctl); 3150 3151 /* 82571 and greater support packet-split where the protocol 3152 * header is placed in skb->data and the packet data is 3153 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3154 * In the case of a non-split, skb->data is linearly filled, 3155 * followed by the page buffers. Therefore, skb->data is 3156 * sized to hold the largest protocol header. 3157 * 3158 * allocations using alloc_page take too long for regular MTU 3159 * so only enable packet split for jumbo frames 3160 * 3161 * Using pages when the page size is greater than 16k wastes 3162 * a lot of memory, since we allocate 3 pages at all times 3163 * per packet. 3164 */ 3165 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3166 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3167 adapter->rx_ps_pages = pages; 3168 else 3169 adapter->rx_ps_pages = 0; 3170 3171 if (adapter->rx_ps_pages) { 3172 u32 psrctl = 0; 3173 3174 /* Enable Packet split descriptors */ 3175 rctl |= E1000_RCTL_DTYP_PS; 3176 3177 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3178 3179 switch (adapter->rx_ps_pages) { 3180 case 3: 3181 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3182 /* fall-through */ 3183 case 2: 3184 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3185 /* fall-through */ 3186 case 1: 3187 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3188 break; 3189 } 3190 3191 ew32(PSRCTL, psrctl); 3192 } 3193 3194 /* This is useful for sniffing bad packets. */ 3195 if (adapter->netdev->features & NETIF_F_RXALL) { 3196 /* UPE and MPE will be handled by normal PROMISC logic 3197 * in e1000e_set_rx_mode 3198 */ 3199 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3200 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3201 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3202 3203 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3204 E1000_RCTL_DPF | /* Allow filtered pause */ 3205 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3206 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3207 * and that breaks VLANs. 3208 */ 3209 } 3210 3211 ew32(RCTL, rctl); 3212 /* just started the receive unit, no need to restart */ 3213 adapter->flags &= ~FLAG_RESTART_NOW; 3214 } 3215 3216 /** 3217 * e1000_configure_rx - Configure Receive Unit after Reset 3218 * @adapter: board private structure 3219 * 3220 * Configure the Rx unit of the MAC after a reset. 3221 **/ 3222 static void e1000_configure_rx(struct e1000_adapter *adapter) 3223 { 3224 struct e1000_hw *hw = &adapter->hw; 3225 struct e1000_ring *rx_ring = adapter->rx_ring; 3226 u64 rdba; 3227 u32 rdlen, rctl, rxcsum, ctrl_ext; 3228 3229 if (adapter->rx_ps_pages) { 3230 /* this is a 32 byte descriptor */ 3231 rdlen = rx_ring->count * 3232 sizeof(union e1000_rx_desc_packet_split); 3233 adapter->clean_rx = e1000_clean_rx_irq_ps; 3234 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3235 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3236 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3237 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3238 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3239 } else { 3240 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3241 adapter->clean_rx = e1000_clean_rx_irq; 3242 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3243 } 3244 3245 /* disable receives while setting up the descriptors */ 3246 rctl = er32(RCTL); 3247 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3248 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3249 e1e_flush(); 3250 usleep_range(10000, 11000); 3251 3252 if (adapter->flags2 & FLAG2_DMA_BURST) { 3253 /* set the writeback threshold (only takes effect if the RDTR 3254 * is set). set GRAN=1 and write back up to 0x4 worth, and 3255 * enable prefetching of 0x20 Rx descriptors 3256 * granularity = 01 3257 * wthresh = 04, 3258 * hthresh = 04, 3259 * pthresh = 0x20 3260 */ 3261 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3262 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3263 } 3264 3265 /* set the Receive Delay Timer Register */ 3266 ew32(RDTR, adapter->rx_int_delay); 3267 3268 /* irq moderation */ 3269 ew32(RADV, adapter->rx_abs_int_delay); 3270 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3271 e1000e_write_itr(adapter, adapter->itr); 3272 3273 ctrl_ext = er32(CTRL_EXT); 3274 /* Auto-Mask interrupts upon ICR access */ 3275 ctrl_ext |= E1000_CTRL_EXT_IAME; 3276 ew32(IAM, 0xffffffff); 3277 ew32(CTRL_EXT, ctrl_ext); 3278 e1e_flush(); 3279 3280 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3281 * the Base and Length of the Rx Descriptor Ring 3282 */ 3283 rdba = rx_ring->dma; 3284 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3285 ew32(RDBAH(0), (rdba >> 32)); 3286 ew32(RDLEN(0), rdlen); 3287 ew32(RDH(0), 0); 3288 ew32(RDT(0), 0); 3289 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3290 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3291 3292 writel(0, rx_ring->head); 3293 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3294 e1000e_update_rdt_wa(rx_ring, 0); 3295 else 3296 writel(0, rx_ring->tail); 3297 3298 /* Enable Receive Checksum Offload for TCP and UDP */ 3299 rxcsum = er32(RXCSUM); 3300 if (adapter->netdev->features & NETIF_F_RXCSUM) 3301 rxcsum |= E1000_RXCSUM_TUOFL; 3302 else 3303 rxcsum &= ~E1000_RXCSUM_TUOFL; 3304 ew32(RXCSUM, rxcsum); 3305 3306 /* With jumbo frames, excessive C-state transition latencies result 3307 * in dropped transactions. 3308 */ 3309 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3310 u32 lat = 3311 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3312 adapter->max_frame_size) * 8 / 1000; 3313 3314 if (adapter->flags & FLAG_IS_ICH) { 3315 u32 rxdctl = er32(RXDCTL(0)); 3316 3317 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3318 } 3319 3320 dev_info(&adapter->pdev->dev, 3321 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3322 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat); 3323 } else { 3324 cpu_latency_qos_update_request(&adapter->pm_qos_req, 3325 PM_QOS_DEFAULT_VALUE); 3326 } 3327 3328 /* Enable Receives */ 3329 ew32(RCTL, rctl); 3330 } 3331 3332 /** 3333 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3334 * @netdev: network interface device structure 3335 * 3336 * Writes multicast address list to the MTA hash table. 3337 * Returns: -ENOMEM on failure 3338 * 0 on no addresses written 3339 * X on writing X addresses to MTA 3340 */ 3341 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3342 { 3343 struct e1000_adapter *adapter = netdev_priv(netdev); 3344 struct e1000_hw *hw = &adapter->hw; 3345 struct netdev_hw_addr *ha; 3346 u8 *mta_list; 3347 int i; 3348 3349 if (netdev_mc_empty(netdev)) { 3350 /* nothing to program, so clear mc list */ 3351 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3352 return 0; 3353 } 3354 3355 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3356 if (!mta_list) 3357 return -ENOMEM; 3358 3359 /* update_mc_addr_list expects a packed array of only addresses. */ 3360 i = 0; 3361 netdev_for_each_mc_addr(ha, netdev) 3362 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3363 3364 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3365 kfree(mta_list); 3366 3367 return netdev_mc_count(netdev); 3368 } 3369 3370 /** 3371 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3372 * @netdev: network interface device structure 3373 * 3374 * Writes unicast address list to the RAR table. 3375 * Returns: -ENOMEM on failure/insufficient address space 3376 * 0 on no addresses written 3377 * X on writing X addresses to the RAR table 3378 **/ 3379 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3380 { 3381 struct e1000_adapter *adapter = netdev_priv(netdev); 3382 struct e1000_hw *hw = &adapter->hw; 3383 unsigned int rar_entries; 3384 int count = 0; 3385 3386 rar_entries = hw->mac.ops.rar_get_count(hw); 3387 3388 /* save a rar entry for our hardware address */ 3389 rar_entries--; 3390 3391 /* save a rar entry for the LAA workaround */ 3392 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3393 rar_entries--; 3394 3395 /* return ENOMEM indicating insufficient memory for addresses */ 3396 if (netdev_uc_count(netdev) > rar_entries) 3397 return -ENOMEM; 3398 3399 if (!netdev_uc_empty(netdev) && rar_entries) { 3400 struct netdev_hw_addr *ha; 3401 3402 /* write the addresses in reverse order to avoid write 3403 * combining 3404 */ 3405 netdev_for_each_uc_addr(ha, netdev) { 3406 int ret_val; 3407 3408 if (!rar_entries) 3409 break; 3410 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3411 if (ret_val < 0) 3412 return -ENOMEM; 3413 count++; 3414 } 3415 } 3416 3417 /* zero out the remaining RAR entries not used above */ 3418 for (; rar_entries > 0; rar_entries--) { 3419 ew32(RAH(rar_entries), 0); 3420 ew32(RAL(rar_entries), 0); 3421 } 3422 e1e_flush(); 3423 3424 return count; 3425 } 3426 3427 /** 3428 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3429 * @netdev: network interface device structure 3430 * 3431 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3432 * address list or the network interface flags are updated. This routine is 3433 * responsible for configuring the hardware for proper unicast, multicast, 3434 * promiscuous mode, and all-multi behavior. 3435 **/ 3436 static void e1000e_set_rx_mode(struct net_device *netdev) 3437 { 3438 struct e1000_adapter *adapter = netdev_priv(netdev); 3439 struct e1000_hw *hw = &adapter->hw; 3440 u32 rctl; 3441 3442 if (pm_runtime_suspended(netdev->dev.parent)) 3443 return; 3444 3445 /* Check for Promiscuous and All Multicast modes */ 3446 rctl = er32(RCTL); 3447 3448 /* clear the affected bits */ 3449 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3450 3451 if (netdev->flags & IFF_PROMISC) { 3452 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3453 /* Do not hardware filter VLANs in promisc mode */ 3454 e1000e_vlan_filter_disable(adapter); 3455 } else { 3456 int count; 3457 3458 if (netdev->flags & IFF_ALLMULTI) { 3459 rctl |= E1000_RCTL_MPE; 3460 } else { 3461 /* Write addresses to the MTA, if the attempt fails 3462 * then we should just turn on promiscuous mode so 3463 * that we can at least receive multicast traffic 3464 */ 3465 count = e1000e_write_mc_addr_list(netdev); 3466 if (count < 0) 3467 rctl |= E1000_RCTL_MPE; 3468 } 3469 e1000e_vlan_filter_enable(adapter); 3470 /* Write addresses to available RAR registers, if there is not 3471 * sufficient space to store all the addresses then enable 3472 * unicast promiscuous mode 3473 */ 3474 count = e1000e_write_uc_addr_list(netdev); 3475 if (count < 0) 3476 rctl |= E1000_RCTL_UPE; 3477 } 3478 3479 ew32(RCTL, rctl); 3480 3481 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3482 e1000e_vlan_strip_enable(adapter); 3483 else 3484 e1000e_vlan_strip_disable(adapter); 3485 } 3486 3487 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3488 { 3489 struct e1000_hw *hw = &adapter->hw; 3490 u32 mrqc, rxcsum; 3491 u32 rss_key[10]; 3492 int i; 3493 3494 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3495 for (i = 0; i < 10; i++) 3496 ew32(RSSRK(i), rss_key[i]); 3497 3498 /* Direct all traffic to queue 0 */ 3499 for (i = 0; i < 32; i++) 3500 ew32(RETA(i), 0); 3501 3502 /* Disable raw packet checksumming so that RSS hash is placed in 3503 * descriptor on writeback. 3504 */ 3505 rxcsum = er32(RXCSUM); 3506 rxcsum |= E1000_RXCSUM_PCSD; 3507 3508 ew32(RXCSUM, rxcsum); 3509 3510 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3511 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3512 E1000_MRQC_RSS_FIELD_IPV6 | 3513 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3514 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3515 3516 ew32(MRQC, mrqc); 3517 } 3518 3519 /** 3520 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3521 * @adapter: board private structure 3522 * @timinca: pointer to returned time increment attributes 3523 * 3524 * Get attributes for incrementing the System Time Register SYSTIML/H at 3525 * the default base frequency, and set the cyclecounter shift value. 3526 **/ 3527 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3528 { 3529 struct e1000_hw *hw = &adapter->hw; 3530 u32 incvalue, incperiod, shift; 3531 3532 /* Make sure clock is enabled on I217/I218/I219 before checking 3533 * the frequency 3534 */ 3535 if ((hw->mac.type >= e1000_pch_lpt) && 3536 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3537 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3538 u32 fextnvm7 = er32(FEXTNVM7); 3539 3540 if (!(fextnvm7 & BIT(0))) { 3541 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3542 e1e_flush(); 3543 } 3544 } 3545 3546 switch (hw->mac.type) { 3547 case e1000_pch2lan: 3548 /* Stable 96MHz frequency */ 3549 incperiod = INCPERIOD_96MHZ; 3550 incvalue = INCVALUE_96MHZ; 3551 shift = INCVALUE_SHIFT_96MHZ; 3552 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3553 break; 3554 case e1000_pch_lpt: 3555 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3556 /* Stable 96MHz frequency */ 3557 incperiod = INCPERIOD_96MHZ; 3558 incvalue = INCVALUE_96MHZ; 3559 shift = INCVALUE_SHIFT_96MHZ; 3560 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3561 } else { 3562 /* Stable 25MHz frequency */ 3563 incperiod = INCPERIOD_25MHZ; 3564 incvalue = INCVALUE_25MHZ; 3565 shift = INCVALUE_SHIFT_25MHZ; 3566 adapter->cc.shift = shift; 3567 } 3568 break; 3569 case e1000_pch_spt: 3570 /* Stable 24MHz frequency */ 3571 incperiod = INCPERIOD_24MHZ; 3572 incvalue = INCVALUE_24MHZ; 3573 shift = INCVALUE_SHIFT_24MHZ; 3574 adapter->cc.shift = shift; 3575 break; 3576 case e1000_pch_cnp: 3577 case e1000_pch_tgp: 3578 case e1000_pch_adp: 3579 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3580 /* Stable 24MHz frequency */ 3581 incperiod = INCPERIOD_24MHZ; 3582 incvalue = INCVALUE_24MHZ; 3583 shift = INCVALUE_SHIFT_24MHZ; 3584 adapter->cc.shift = shift; 3585 } else { 3586 /* Stable 38400KHz frequency */ 3587 incperiod = INCPERIOD_38400KHZ; 3588 incvalue = INCVALUE_38400KHZ; 3589 shift = INCVALUE_SHIFT_38400KHZ; 3590 adapter->cc.shift = shift; 3591 } 3592 break; 3593 case e1000_82574: 3594 case e1000_82583: 3595 /* Stable 25MHz frequency */ 3596 incperiod = INCPERIOD_25MHZ; 3597 incvalue = INCVALUE_25MHZ; 3598 shift = INCVALUE_SHIFT_25MHZ; 3599 adapter->cc.shift = shift; 3600 break; 3601 default: 3602 return -EINVAL; 3603 } 3604 3605 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3606 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3607 3608 return 0; 3609 } 3610 3611 /** 3612 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3613 * @adapter: board private structure 3614 * 3615 * Outgoing time stamping can be enabled and disabled. Play nice and 3616 * disable it when requested, although it shouldn't cause any overhead 3617 * when no packet needs it. At most one packet in the queue may be 3618 * marked for time stamping, otherwise it would be impossible to tell 3619 * for sure to which packet the hardware time stamp belongs. 3620 * 3621 * Incoming time stamping has to be configured via the hardware filters. 3622 * Not all combinations are supported, in particular event type has to be 3623 * specified. Matching the kind of event packet is not supported, with the 3624 * exception of "all V2 events regardless of level 2 or 4". 3625 **/ 3626 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3627 struct hwtstamp_config *config) 3628 { 3629 struct e1000_hw *hw = &adapter->hw; 3630 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3631 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3632 u32 rxmtrl = 0; 3633 u16 rxudp = 0; 3634 bool is_l4 = false; 3635 bool is_l2 = false; 3636 u32 regval; 3637 3638 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3639 return -EINVAL; 3640 3641 /* flags reserved for future extensions - must be zero */ 3642 if (config->flags) 3643 return -EINVAL; 3644 3645 switch (config->tx_type) { 3646 case HWTSTAMP_TX_OFF: 3647 tsync_tx_ctl = 0; 3648 break; 3649 case HWTSTAMP_TX_ON: 3650 break; 3651 default: 3652 return -ERANGE; 3653 } 3654 3655 switch (config->rx_filter) { 3656 case HWTSTAMP_FILTER_NONE: 3657 tsync_rx_ctl = 0; 3658 break; 3659 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3660 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3661 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3662 is_l4 = true; 3663 break; 3664 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3665 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3666 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3667 is_l4 = true; 3668 break; 3669 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3670 /* Also time stamps V2 L2 Path Delay Request/Response */ 3671 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3672 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3673 is_l2 = true; 3674 break; 3675 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3676 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3677 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3678 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3679 is_l2 = true; 3680 break; 3681 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3682 /* Hardware cannot filter just V2 L4 Sync messages; 3683 * fall-through to V2 (both L2 and L4) Sync. 3684 */ 3685 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3686 /* Also time stamps V2 Path Delay Request/Response. */ 3687 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3688 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3689 is_l2 = true; 3690 is_l4 = true; 3691 break; 3692 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3693 /* Hardware cannot filter just V2 L4 Delay Request messages; 3694 * fall-through to V2 (both L2 and L4) Delay Request. 3695 */ 3696 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3697 /* Also time stamps V2 Path Delay Request/Response. */ 3698 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3699 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3700 is_l2 = true; 3701 is_l4 = true; 3702 break; 3703 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3704 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3705 /* Hardware cannot filter just V2 L4 or L2 Event messages; 3706 * fall-through to all V2 (both L2 and L4) Events. 3707 */ 3708 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3709 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3710 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3711 is_l2 = true; 3712 is_l4 = true; 3713 break; 3714 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3715 /* For V1, the hardware can only filter Sync messages or 3716 * Delay Request messages but not both so fall-through to 3717 * time stamp all packets. 3718 */ 3719 case HWTSTAMP_FILTER_NTP_ALL: 3720 case HWTSTAMP_FILTER_ALL: 3721 is_l2 = true; 3722 is_l4 = true; 3723 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3724 config->rx_filter = HWTSTAMP_FILTER_ALL; 3725 break; 3726 default: 3727 return -ERANGE; 3728 } 3729 3730 adapter->hwtstamp_config = *config; 3731 3732 /* enable/disable Tx h/w time stamping */ 3733 regval = er32(TSYNCTXCTL); 3734 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3735 regval |= tsync_tx_ctl; 3736 ew32(TSYNCTXCTL, regval); 3737 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3738 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3739 e_err("Timesync Tx Control register not set as expected\n"); 3740 return -EAGAIN; 3741 } 3742 3743 /* enable/disable Rx h/w time stamping */ 3744 regval = er32(TSYNCRXCTL); 3745 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3746 regval |= tsync_rx_ctl; 3747 ew32(TSYNCRXCTL, regval); 3748 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3749 E1000_TSYNCRXCTL_TYPE_MASK)) != 3750 (regval & (E1000_TSYNCRXCTL_ENABLED | 3751 E1000_TSYNCRXCTL_TYPE_MASK))) { 3752 e_err("Timesync Rx Control register not set as expected\n"); 3753 return -EAGAIN; 3754 } 3755 3756 /* L2: define ethertype filter for time stamped packets */ 3757 if (is_l2) 3758 rxmtrl |= ETH_P_1588; 3759 3760 /* define which PTP packets get time stamped */ 3761 ew32(RXMTRL, rxmtrl); 3762 3763 /* Filter by destination port */ 3764 if (is_l4) { 3765 rxudp = PTP_EV_PORT; 3766 cpu_to_be16s(&rxudp); 3767 } 3768 ew32(RXUDP, rxudp); 3769 3770 e1e_flush(); 3771 3772 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3773 er32(RXSTMPH); 3774 er32(TXSTMPH); 3775 3776 return 0; 3777 } 3778 3779 /** 3780 * e1000_configure - configure the hardware for Rx and Tx 3781 * @adapter: private board structure 3782 **/ 3783 static void e1000_configure(struct e1000_adapter *adapter) 3784 { 3785 struct e1000_ring *rx_ring = adapter->rx_ring; 3786 3787 e1000e_set_rx_mode(adapter->netdev); 3788 3789 e1000_restore_vlan(adapter); 3790 e1000_init_manageability_pt(adapter); 3791 3792 e1000_configure_tx(adapter); 3793 3794 if (adapter->netdev->features & NETIF_F_RXHASH) 3795 e1000e_setup_rss_hash(adapter); 3796 e1000_setup_rctl(adapter); 3797 e1000_configure_rx(adapter); 3798 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3799 } 3800 3801 /** 3802 * e1000e_power_up_phy - restore link in case the phy was powered down 3803 * @adapter: address of board private structure 3804 * 3805 * The phy may be powered down to save power and turn off link when the 3806 * driver is unloaded and wake on lan is not enabled (among others) 3807 * *** this routine MUST be followed by a call to e1000e_reset *** 3808 **/ 3809 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3810 { 3811 if (adapter->hw.phy.ops.power_up) 3812 adapter->hw.phy.ops.power_up(&adapter->hw); 3813 3814 adapter->hw.mac.ops.setup_link(&adapter->hw); 3815 } 3816 3817 /** 3818 * e1000_power_down_phy - Power down the PHY 3819 * 3820 * Power down the PHY so no link is implied when interface is down. 3821 * The PHY cannot be powered down if management or WoL is active. 3822 */ 3823 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3824 { 3825 if (adapter->hw.phy.ops.power_down) 3826 adapter->hw.phy.ops.power_down(&adapter->hw); 3827 } 3828 3829 /** 3830 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3831 * 3832 * We want to clear all pending descriptors from the TX ring. 3833 * zeroing happens when the HW reads the regs. We assign the ring itself as 3834 * the data of the next descriptor. We don't care about the data we are about 3835 * to reset the HW. 3836 */ 3837 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3838 { 3839 struct e1000_hw *hw = &adapter->hw; 3840 struct e1000_ring *tx_ring = adapter->tx_ring; 3841 struct e1000_tx_desc *tx_desc = NULL; 3842 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3843 u16 size = 512; 3844 3845 tctl = er32(TCTL); 3846 ew32(TCTL, tctl | E1000_TCTL_EN); 3847 tdt = er32(TDT(0)); 3848 BUG_ON(tdt != tx_ring->next_to_use); 3849 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3850 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma); 3851 3852 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3853 tx_desc->upper.data = 0; 3854 /* flush descriptors to memory before notifying the HW */ 3855 wmb(); 3856 tx_ring->next_to_use++; 3857 if (tx_ring->next_to_use == tx_ring->count) 3858 tx_ring->next_to_use = 0; 3859 ew32(TDT(0), tx_ring->next_to_use); 3860 usleep_range(200, 250); 3861 } 3862 3863 /** 3864 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3865 * 3866 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3867 */ 3868 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3869 { 3870 u32 rctl, rxdctl; 3871 struct e1000_hw *hw = &adapter->hw; 3872 3873 rctl = er32(RCTL); 3874 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3875 e1e_flush(); 3876 usleep_range(100, 150); 3877 3878 rxdctl = er32(RXDCTL(0)); 3879 /* zero the lower 14 bits (prefetch and host thresholds) */ 3880 rxdctl &= 0xffffc000; 3881 3882 /* update thresholds: prefetch threshold to 31, host threshold to 1 3883 * and make sure the granularity is "descriptors" and not "cache lines" 3884 */ 3885 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3886 3887 ew32(RXDCTL(0), rxdctl); 3888 /* momentarily enable the RX ring for the changes to take effect */ 3889 ew32(RCTL, rctl | E1000_RCTL_EN); 3890 e1e_flush(); 3891 usleep_range(100, 150); 3892 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3893 } 3894 3895 /** 3896 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3897 * 3898 * In i219, the descriptor rings must be emptied before resetting the HW 3899 * or before changing the device state to D3 during runtime (runtime PM). 3900 * 3901 * Failure to do this will cause the HW to enter a unit hang state which can 3902 * only be released by PCI reset on the device 3903 * 3904 */ 3905 3906 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3907 { 3908 u16 hang_state; 3909 u32 fext_nvm11, tdlen; 3910 struct e1000_hw *hw = &adapter->hw; 3911 3912 /* First, disable MULR fix in FEXTNVM11 */ 3913 fext_nvm11 = er32(FEXTNVM11); 3914 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3915 ew32(FEXTNVM11, fext_nvm11); 3916 /* do nothing if we're not in faulty state, or if the queue is empty */ 3917 tdlen = er32(TDLEN(0)); 3918 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3919 &hang_state); 3920 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3921 return; 3922 e1000_flush_tx_ring(adapter); 3923 /* recheck, maybe the fault is caused by the rx ring */ 3924 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3925 &hang_state); 3926 if (hang_state & FLUSH_DESC_REQUIRED) 3927 e1000_flush_rx_ring(adapter); 3928 } 3929 3930 /** 3931 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3932 * @adapter: board private structure 3933 * 3934 * When the MAC is reset, all hardware bits for timesync will be reset to the 3935 * default values. This function will restore the settings last in place. 3936 * Since the clock SYSTIME registers are reset, we will simply restore the 3937 * cyclecounter to the kernel real clock time. 3938 **/ 3939 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3940 { 3941 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3942 struct e1000_hw *hw = &adapter->hw; 3943 unsigned long flags; 3944 u32 timinca; 3945 s32 ret_val; 3946 3947 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3948 return; 3949 3950 if (info->adjfreq) { 3951 /* restore the previous ptp frequency delta */ 3952 ret_val = info->adjfreq(info, adapter->ptp_delta); 3953 } else { 3954 /* set the default base frequency if no adjustment possible */ 3955 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3956 if (!ret_val) 3957 ew32(TIMINCA, timinca); 3958 } 3959 3960 if (ret_val) { 3961 dev_warn(&adapter->pdev->dev, 3962 "Failed to restore TIMINCA clock rate delta: %d\n", 3963 ret_val); 3964 return; 3965 } 3966 3967 /* reset the systim ns time counter */ 3968 spin_lock_irqsave(&adapter->systim_lock, flags); 3969 timecounter_init(&adapter->tc, &adapter->cc, 3970 ktime_to_ns(ktime_get_real())); 3971 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3972 3973 /* restore the previous hwtstamp configuration settings */ 3974 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3975 } 3976 3977 /** 3978 * e1000e_reset - bring the hardware into a known good state 3979 * 3980 * This function boots the hardware and enables some settings that 3981 * require a configuration cycle of the hardware - those cannot be 3982 * set/changed during runtime. After reset the device needs to be 3983 * properly configured for Rx, Tx etc. 3984 */ 3985 void e1000e_reset(struct e1000_adapter *adapter) 3986 { 3987 struct e1000_mac_info *mac = &adapter->hw.mac; 3988 struct e1000_fc_info *fc = &adapter->hw.fc; 3989 struct e1000_hw *hw = &adapter->hw; 3990 u32 tx_space, min_tx_space, min_rx_space; 3991 u32 pba = adapter->pba; 3992 u16 hwm; 3993 3994 /* reset Packet Buffer Allocation to default */ 3995 ew32(PBA, pba); 3996 3997 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3998 /* To maintain wire speed transmits, the Tx FIFO should be 3999 * large enough to accommodate two full transmit packets, 4000 * rounded up to the next 1KB and expressed in KB. Likewise, 4001 * the Rx FIFO should be large enough to accommodate at least 4002 * one full receive packet and is similarly rounded up and 4003 * expressed in KB. 4004 */ 4005 pba = er32(PBA); 4006 /* upper 16 bits has Tx packet buffer allocation size in KB */ 4007 tx_space = pba >> 16; 4008 /* lower 16 bits has Rx packet buffer allocation size in KB */ 4009 pba &= 0xffff; 4010 /* the Tx fifo also stores 16 bytes of information about the Tx 4011 * but don't include ethernet FCS because hardware appends it 4012 */ 4013 min_tx_space = (adapter->max_frame_size + 4014 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 4015 min_tx_space = ALIGN(min_tx_space, 1024); 4016 min_tx_space >>= 10; 4017 /* software strips receive CRC, so leave room for it */ 4018 min_rx_space = adapter->max_frame_size; 4019 min_rx_space = ALIGN(min_rx_space, 1024); 4020 min_rx_space >>= 10; 4021 4022 /* If current Tx allocation is less than the min Tx FIFO size, 4023 * and the min Tx FIFO size is less than the current Rx FIFO 4024 * allocation, take space away from current Rx allocation 4025 */ 4026 if ((tx_space < min_tx_space) && 4027 ((min_tx_space - tx_space) < pba)) { 4028 pba -= min_tx_space - tx_space; 4029 4030 /* if short on Rx space, Rx wins and must trump Tx 4031 * adjustment 4032 */ 4033 if (pba < min_rx_space) 4034 pba = min_rx_space; 4035 } 4036 4037 ew32(PBA, pba); 4038 } 4039 4040 /* flow control settings 4041 * 4042 * The high water mark must be low enough to fit one full frame 4043 * (or the size used for early receive) above it in the Rx FIFO. 4044 * Set it to the lower of: 4045 * - 90% of the Rx FIFO size, and 4046 * - the full Rx FIFO size minus one full frame 4047 */ 4048 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4049 fc->pause_time = 0xFFFF; 4050 else 4051 fc->pause_time = E1000_FC_PAUSE_TIME; 4052 fc->send_xon = true; 4053 fc->current_mode = fc->requested_mode; 4054 4055 switch (hw->mac.type) { 4056 case e1000_ich9lan: 4057 case e1000_ich10lan: 4058 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4059 pba = 14; 4060 ew32(PBA, pba); 4061 fc->high_water = 0x2800; 4062 fc->low_water = fc->high_water - 8; 4063 break; 4064 } 4065 /* fall-through */ 4066 default: 4067 hwm = min(((pba << 10) * 9 / 10), 4068 ((pba << 10) - adapter->max_frame_size)); 4069 4070 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4071 fc->low_water = fc->high_water - 8; 4072 break; 4073 case e1000_pchlan: 4074 /* Workaround PCH LOM adapter hangs with certain network 4075 * loads. If hangs persist, try disabling Tx flow control. 4076 */ 4077 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4078 fc->high_water = 0x3500; 4079 fc->low_water = 0x1500; 4080 } else { 4081 fc->high_water = 0x5000; 4082 fc->low_water = 0x3000; 4083 } 4084 fc->refresh_time = 0x1000; 4085 break; 4086 case e1000_pch2lan: 4087 case e1000_pch_lpt: 4088 case e1000_pch_spt: 4089 case e1000_pch_cnp: 4090 /* fall-through */ 4091 case e1000_pch_tgp: 4092 case e1000_pch_adp: 4093 fc->refresh_time = 0xFFFF; 4094 fc->pause_time = 0xFFFF; 4095 4096 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4097 fc->high_water = 0x05C20; 4098 fc->low_water = 0x05048; 4099 break; 4100 } 4101 4102 pba = 14; 4103 ew32(PBA, pba); 4104 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4105 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4106 break; 4107 } 4108 4109 /* Alignment of Tx data is on an arbitrary byte boundary with the 4110 * maximum size per Tx descriptor limited only to the transmit 4111 * allocation of the packet buffer minus 96 bytes with an upper 4112 * limit of 24KB due to receive synchronization limitations. 4113 */ 4114 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4115 24 << 10); 4116 4117 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4118 * fit in receive buffer. 4119 */ 4120 if (adapter->itr_setting & 0x3) { 4121 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4122 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4123 dev_info(&adapter->pdev->dev, 4124 "Interrupt Throttle Rate off\n"); 4125 adapter->flags2 |= FLAG2_DISABLE_AIM; 4126 e1000e_write_itr(adapter, 0); 4127 } 4128 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4129 dev_info(&adapter->pdev->dev, 4130 "Interrupt Throttle Rate on\n"); 4131 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4132 adapter->itr = 20000; 4133 e1000e_write_itr(adapter, adapter->itr); 4134 } 4135 } 4136 4137 if (hw->mac.type >= e1000_pch_spt) 4138 e1000_flush_desc_rings(adapter); 4139 /* Allow time for pending master requests to run */ 4140 mac->ops.reset_hw(hw); 4141 4142 /* For parts with AMT enabled, let the firmware know 4143 * that the network interface is in control 4144 */ 4145 if (adapter->flags & FLAG_HAS_AMT) 4146 e1000e_get_hw_control(adapter); 4147 4148 ew32(WUC, 0); 4149 4150 if (mac->ops.init_hw(hw)) 4151 e_err("Hardware Error\n"); 4152 4153 e1000_update_mng_vlan(adapter); 4154 4155 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4156 ew32(VET, ETH_P_8021Q); 4157 4158 e1000e_reset_adaptive(hw); 4159 4160 /* restore systim and hwtstamp settings */ 4161 e1000e_systim_reset(adapter); 4162 4163 /* Set EEE advertisement as appropriate */ 4164 if (adapter->flags2 & FLAG2_HAS_EEE) { 4165 s32 ret_val; 4166 u16 adv_addr; 4167 4168 switch (hw->phy.type) { 4169 case e1000_phy_82579: 4170 adv_addr = I82579_EEE_ADVERTISEMENT; 4171 break; 4172 case e1000_phy_i217: 4173 adv_addr = I217_EEE_ADVERTISEMENT; 4174 break; 4175 default: 4176 dev_err(&adapter->pdev->dev, 4177 "Invalid PHY type setting EEE advertisement\n"); 4178 return; 4179 } 4180 4181 ret_val = hw->phy.ops.acquire(hw); 4182 if (ret_val) { 4183 dev_err(&adapter->pdev->dev, 4184 "EEE advertisement - unable to acquire PHY\n"); 4185 return; 4186 } 4187 4188 e1000_write_emi_reg_locked(hw, adv_addr, 4189 hw->dev_spec.ich8lan.eee_disable ? 4190 0 : adapter->eee_advert); 4191 4192 hw->phy.ops.release(hw); 4193 } 4194 4195 if (!netif_running(adapter->netdev) && 4196 !test_bit(__E1000_TESTING, &adapter->state)) 4197 e1000_power_down_phy(adapter); 4198 4199 e1000_get_phy_info(hw); 4200 4201 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4202 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4203 u16 phy_data = 0; 4204 /* speed up time to link by disabling smart power down, ignore 4205 * the return value of this function because there is nothing 4206 * different we would do if it failed 4207 */ 4208 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4209 phy_data &= ~IGP02E1000_PM_SPD; 4210 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4211 } 4212 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4213 u32 reg; 4214 4215 /* Fextnvm7 @ 0xe4[2] = 1 */ 4216 reg = er32(FEXTNVM7); 4217 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4218 ew32(FEXTNVM7, reg); 4219 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4220 reg = er32(FEXTNVM9); 4221 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4222 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4223 ew32(FEXTNVM9, reg); 4224 } 4225 4226 } 4227 4228 /** 4229 * e1000e_trigger_lsc - trigger an LSC interrupt 4230 * @adapter: 4231 * 4232 * Fire a link status change interrupt to start the watchdog. 4233 **/ 4234 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4235 { 4236 struct e1000_hw *hw = &adapter->hw; 4237 4238 if (adapter->msix_entries) 4239 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4240 else 4241 ew32(ICS, E1000_ICS_LSC); 4242 } 4243 4244 void e1000e_up(struct e1000_adapter *adapter) 4245 { 4246 /* hardware has been reset, we need to reload some things */ 4247 e1000_configure(adapter); 4248 4249 clear_bit(__E1000_DOWN, &adapter->state); 4250 4251 if (adapter->msix_entries) 4252 e1000_configure_msix(adapter); 4253 e1000_irq_enable(adapter); 4254 4255 /* Tx queue started by watchdog timer when link is up */ 4256 4257 e1000e_trigger_lsc(adapter); 4258 } 4259 4260 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4261 { 4262 struct e1000_hw *hw = &adapter->hw; 4263 4264 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4265 return; 4266 4267 /* flush pending descriptor writebacks to memory */ 4268 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4269 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4270 4271 /* execute the writes immediately */ 4272 e1e_flush(); 4273 4274 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4275 * write is successful 4276 */ 4277 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4278 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4279 4280 /* execute the writes immediately */ 4281 e1e_flush(); 4282 } 4283 4284 static void e1000e_update_stats(struct e1000_adapter *adapter); 4285 4286 /** 4287 * e1000e_down - quiesce the device and optionally reset the hardware 4288 * @adapter: board private structure 4289 * @reset: boolean flag to reset the hardware or not 4290 */ 4291 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4292 { 4293 struct net_device *netdev = adapter->netdev; 4294 struct e1000_hw *hw = &adapter->hw; 4295 u32 tctl, rctl; 4296 4297 /* signal that we're down so the interrupt handler does not 4298 * reschedule our watchdog timer 4299 */ 4300 set_bit(__E1000_DOWN, &adapter->state); 4301 4302 netif_carrier_off(netdev); 4303 4304 /* disable receives in the hardware */ 4305 rctl = er32(RCTL); 4306 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4307 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4308 /* flush and sleep below */ 4309 4310 netif_stop_queue(netdev); 4311 4312 /* disable transmits in the hardware */ 4313 tctl = er32(TCTL); 4314 tctl &= ~E1000_TCTL_EN; 4315 ew32(TCTL, tctl); 4316 4317 /* flush both disables and wait for them to finish */ 4318 e1e_flush(); 4319 usleep_range(10000, 11000); 4320 4321 e1000_irq_disable(adapter); 4322 4323 napi_synchronize(&adapter->napi); 4324 4325 del_timer_sync(&adapter->watchdog_timer); 4326 del_timer_sync(&adapter->phy_info_timer); 4327 4328 spin_lock(&adapter->stats64_lock); 4329 e1000e_update_stats(adapter); 4330 spin_unlock(&adapter->stats64_lock); 4331 4332 e1000e_flush_descriptors(adapter); 4333 4334 adapter->link_speed = 0; 4335 adapter->link_duplex = 0; 4336 4337 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4338 if ((hw->mac.type >= e1000_pch2lan) && 4339 (adapter->netdev->mtu > ETH_DATA_LEN) && 4340 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4341 e_dbg("failed to disable jumbo frame workaround mode\n"); 4342 4343 if (!pci_channel_offline(adapter->pdev)) { 4344 if (reset) 4345 e1000e_reset(adapter); 4346 else if (hw->mac.type >= e1000_pch_spt) 4347 e1000_flush_desc_rings(adapter); 4348 } 4349 e1000_clean_tx_ring(adapter->tx_ring); 4350 e1000_clean_rx_ring(adapter->rx_ring); 4351 } 4352 4353 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4354 { 4355 might_sleep(); 4356 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4357 usleep_range(1000, 1100); 4358 e1000e_down(adapter, true); 4359 e1000e_up(adapter); 4360 clear_bit(__E1000_RESETTING, &adapter->state); 4361 } 4362 4363 /** 4364 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4365 * @hw: pointer to the HW structure 4366 * @systim: PHC time value read, sanitized and returned 4367 * @sts: structure to hold system time before and after reading SYSTIML, 4368 * may be NULL 4369 * 4370 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4371 * check to see that the time is incrementing at a reasonable 4372 * rate and is a multiple of incvalue. 4373 **/ 4374 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4375 struct ptp_system_timestamp *sts) 4376 { 4377 u64 time_delta, rem, temp; 4378 u64 systim_next; 4379 u32 incvalue; 4380 int i; 4381 4382 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4383 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4384 /* latch SYSTIMH on read of SYSTIML */ 4385 ptp_read_system_prets(sts); 4386 systim_next = (u64)er32(SYSTIML); 4387 ptp_read_system_postts(sts); 4388 systim_next |= (u64)er32(SYSTIMH) << 32; 4389 4390 time_delta = systim_next - systim; 4391 temp = time_delta; 4392 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4393 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4394 4395 systim = systim_next; 4396 4397 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4398 break; 4399 } 4400 4401 return systim; 4402 } 4403 4404 /** 4405 * e1000e_read_systim - read SYSTIM register 4406 * @adapter: board private structure 4407 * @sts: structure which will contain system time before and after reading 4408 * SYSTIML, may be NULL 4409 **/ 4410 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4411 struct ptp_system_timestamp *sts) 4412 { 4413 struct e1000_hw *hw = &adapter->hw; 4414 u32 systimel, systimel_2, systimeh; 4415 u64 systim; 4416 /* SYSTIMH latching upon SYSTIML read does not work well. 4417 * This means that if SYSTIML overflows after we read it but before 4418 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4419 * will experience a huge non linear increment in the systime value 4420 * to fix that we test for overflow and if true, we re-read systime. 4421 */ 4422 ptp_read_system_prets(sts); 4423 systimel = er32(SYSTIML); 4424 ptp_read_system_postts(sts); 4425 systimeh = er32(SYSTIMH); 4426 /* Is systimel is so large that overflow is possible? */ 4427 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4428 ptp_read_system_prets(sts); 4429 systimel_2 = er32(SYSTIML); 4430 ptp_read_system_postts(sts); 4431 if (systimel > systimel_2) { 4432 /* There was an overflow, read again SYSTIMH, and use 4433 * systimel_2 4434 */ 4435 systimeh = er32(SYSTIMH); 4436 systimel = systimel_2; 4437 } 4438 } 4439 systim = (u64)systimel; 4440 systim |= (u64)systimeh << 32; 4441 4442 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4443 systim = e1000e_sanitize_systim(hw, systim, sts); 4444 4445 return systim; 4446 } 4447 4448 /** 4449 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4450 * @cc: cyclecounter structure 4451 **/ 4452 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4453 { 4454 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4455 cc); 4456 4457 return e1000e_read_systim(adapter, NULL); 4458 } 4459 4460 /** 4461 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4462 * @adapter: board private structure to initialize 4463 * 4464 * e1000_sw_init initializes the Adapter private data structure. 4465 * Fields are initialized based on PCI device information and 4466 * OS network device settings (MTU size). 4467 **/ 4468 static int e1000_sw_init(struct e1000_adapter *adapter) 4469 { 4470 struct net_device *netdev = adapter->netdev; 4471 4472 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4473 adapter->rx_ps_bsize0 = 128; 4474 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4475 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4476 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4477 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4478 4479 spin_lock_init(&adapter->stats64_lock); 4480 4481 e1000e_set_interrupt_capability(adapter); 4482 4483 if (e1000_alloc_queues(adapter)) 4484 return -ENOMEM; 4485 4486 /* Setup hardware time stamping cyclecounter */ 4487 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4488 adapter->cc.read = e1000e_cyclecounter_read; 4489 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4490 adapter->cc.mult = 1; 4491 /* cc.shift set in e1000e_get_base_tininca() */ 4492 4493 spin_lock_init(&adapter->systim_lock); 4494 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4495 } 4496 4497 /* Explicitly disable IRQ since the NIC can be in any state. */ 4498 e1000_irq_disable(adapter); 4499 4500 set_bit(__E1000_DOWN, &adapter->state); 4501 return 0; 4502 } 4503 4504 /** 4505 * e1000_intr_msi_test - Interrupt Handler 4506 * @irq: interrupt number 4507 * @data: pointer to a network interface device structure 4508 **/ 4509 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4510 { 4511 struct net_device *netdev = data; 4512 struct e1000_adapter *adapter = netdev_priv(netdev); 4513 struct e1000_hw *hw = &adapter->hw; 4514 u32 icr = er32(ICR); 4515 4516 e_dbg("icr is %08X\n", icr); 4517 if (icr & E1000_ICR_RXSEQ) { 4518 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4519 /* Force memory writes to complete before acknowledging the 4520 * interrupt is handled. 4521 */ 4522 wmb(); 4523 } 4524 4525 return IRQ_HANDLED; 4526 } 4527 4528 /** 4529 * e1000_test_msi_interrupt - Returns 0 for successful test 4530 * @adapter: board private struct 4531 * 4532 * code flow taken from tg3.c 4533 **/ 4534 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4535 { 4536 struct net_device *netdev = adapter->netdev; 4537 struct e1000_hw *hw = &adapter->hw; 4538 int err; 4539 4540 /* poll_enable hasn't been called yet, so don't need disable */ 4541 /* clear any pending events */ 4542 er32(ICR); 4543 4544 /* free the real vector and request a test handler */ 4545 e1000_free_irq(adapter); 4546 e1000e_reset_interrupt_capability(adapter); 4547 4548 /* Assume that the test fails, if it succeeds then the test 4549 * MSI irq handler will unset this flag 4550 */ 4551 adapter->flags |= FLAG_MSI_TEST_FAILED; 4552 4553 err = pci_enable_msi(adapter->pdev); 4554 if (err) 4555 goto msi_test_failed; 4556 4557 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4558 netdev->name, netdev); 4559 if (err) { 4560 pci_disable_msi(adapter->pdev); 4561 goto msi_test_failed; 4562 } 4563 4564 /* Force memory writes to complete before enabling and firing an 4565 * interrupt. 4566 */ 4567 wmb(); 4568 4569 e1000_irq_enable(adapter); 4570 4571 /* fire an unusual interrupt on the test handler */ 4572 ew32(ICS, E1000_ICS_RXSEQ); 4573 e1e_flush(); 4574 msleep(100); 4575 4576 e1000_irq_disable(adapter); 4577 4578 rmb(); /* read flags after interrupt has been fired */ 4579 4580 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4581 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4582 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4583 } else { 4584 e_dbg("MSI interrupt test succeeded!\n"); 4585 } 4586 4587 free_irq(adapter->pdev->irq, netdev); 4588 pci_disable_msi(adapter->pdev); 4589 4590 msi_test_failed: 4591 e1000e_set_interrupt_capability(adapter); 4592 return e1000_request_irq(adapter); 4593 } 4594 4595 /** 4596 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4597 * @adapter: board private struct 4598 * 4599 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4600 **/ 4601 static int e1000_test_msi(struct e1000_adapter *adapter) 4602 { 4603 int err; 4604 u16 pci_cmd; 4605 4606 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4607 return 0; 4608 4609 /* disable SERR in case the MSI write causes a master abort */ 4610 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4611 if (pci_cmd & PCI_COMMAND_SERR) 4612 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4613 pci_cmd & ~PCI_COMMAND_SERR); 4614 4615 err = e1000_test_msi_interrupt(adapter); 4616 4617 /* re-enable SERR */ 4618 if (pci_cmd & PCI_COMMAND_SERR) { 4619 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4620 pci_cmd |= PCI_COMMAND_SERR; 4621 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4622 } 4623 4624 return err; 4625 } 4626 4627 /** 4628 * e1000e_open - Called when a network interface is made active 4629 * @netdev: network interface device structure 4630 * 4631 * Returns 0 on success, negative value on failure 4632 * 4633 * The open entry point is called when a network interface is made 4634 * active by the system (IFF_UP). At this point all resources needed 4635 * for transmit and receive operations are allocated, the interrupt 4636 * handler is registered with the OS, the watchdog timer is started, 4637 * and the stack is notified that the interface is ready. 4638 **/ 4639 int e1000e_open(struct net_device *netdev) 4640 { 4641 struct e1000_adapter *adapter = netdev_priv(netdev); 4642 struct e1000_hw *hw = &adapter->hw; 4643 struct pci_dev *pdev = adapter->pdev; 4644 int err; 4645 4646 /* disallow open during test */ 4647 if (test_bit(__E1000_TESTING, &adapter->state)) 4648 return -EBUSY; 4649 4650 pm_runtime_get_sync(&pdev->dev); 4651 4652 netif_carrier_off(netdev); 4653 netif_stop_queue(netdev); 4654 4655 /* allocate transmit descriptors */ 4656 err = e1000e_setup_tx_resources(adapter->tx_ring); 4657 if (err) 4658 goto err_setup_tx; 4659 4660 /* allocate receive descriptors */ 4661 err = e1000e_setup_rx_resources(adapter->rx_ring); 4662 if (err) 4663 goto err_setup_rx; 4664 4665 /* If AMT is enabled, let the firmware know that the network 4666 * interface is now open and reset the part to a known state. 4667 */ 4668 if (adapter->flags & FLAG_HAS_AMT) { 4669 e1000e_get_hw_control(adapter); 4670 e1000e_reset(adapter); 4671 } 4672 4673 e1000e_power_up_phy(adapter); 4674 4675 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4676 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4677 e1000_update_mng_vlan(adapter); 4678 4679 /* DMA latency requirement to workaround jumbo issue */ 4680 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE); 4681 4682 /* before we allocate an interrupt, we must be ready to handle it. 4683 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4684 * as soon as we call pci_request_irq, so we have to setup our 4685 * clean_rx handler before we do so. 4686 */ 4687 e1000_configure(adapter); 4688 4689 err = e1000_request_irq(adapter); 4690 if (err) 4691 goto err_req_irq; 4692 4693 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4694 * ignore e1000e MSI messages, which means we need to test our MSI 4695 * interrupt now 4696 */ 4697 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4698 err = e1000_test_msi(adapter); 4699 if (err) { 4700 e_err("Interrupt allocation failed\n"); 4701 goto err_req_irq; 4702 } 4703 } 4704 4705 /* From here on the code is the same as e1000e_up() */ 4706 clear_bit(__E1000_DOWN, &adapter->state); 4707 4708 napi_enable(&adapter->napi); 4709 4710 e1000_irq_enable(adapter); 4711 4712 adapter->tx_hang_recheck = false; 4713 4714 hw->mac.get_link_status = true; 4715 pm_runtime_put(&pdev->dev); 4716 4717 e1000e_trigger_lsc(adapter); 4718 4719 return 0; 4720 4721 err_req_irq: 4722 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4723 e1000e_release_hw_control(adapter); 4724 e1000_power_down_phy(adapter); 4725 e1000e_free_rx_resources(adapter->rx_ring); 4726 err_setup_rx: 4727 e1000e_free_tx_resources(adapter->tx_ring); 4728 err_setup_tx: 4729 e1000e_reset(adapter); 4730 pm_runtime_put_sync(&pdev->dev); 4731 4732 return err; 4733 } 4734 4735 /** 4736 * e1000e_close - Disables a network interface 4737 * @netdev: network interface device structure 4738 * 4739 * Returns 0, this is not allowed to fail 4740 * 4741 * The close entry point is called when an interface is de-activated 4742 * by the OS. The hardware is still under the drivers control, but 4743 * needs to be disabled. A global MAC reset is issued to stop the 4744 * hardware, and all transmit and receive resources are freed. 4745 **/ 4746 int e1000e_close(struct net_device *netdev) 4747 { 4748 struct e1000_adapter *adapter = netdev_priv(netdev); 4749 struct pci_dev *pdev = adapter->pdev; 4750 int count = E1000_CHECK_RESET_COUNT; 4751 4752 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4753 usleep_range(10000, 11000); 4754 4755 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4756 4757 pm_runtime_get_sync(&pdev->dev); 4758 4759 if (netif_device_present(netdev)) { 4760 e1000e_down(adapter, true); 4761 e1000_free_irq(adapter); 4762 4763 /* Link status message must follow this format */ 4764 netdev_info(netdev, "NIC Link is Down\n"); 4765 } 4766 4767 napi_disable(&adapter->napi); 4768 4769 e1000e_free_tx_resources(adapter->tx_ring); 4770 e1000e_free_rx_resources(adapter->rx_ring); 4771 4772 /* kill manageability vlan ID if supported, but not if a vlan with 4773 * the same ID is registered on the host OS (let 8021q kill it) 4774 */ 4775 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4776 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4777 adapter->mng_vlan_id); 4778 4779 /* If AMT is enabled, let the firmware know that the network 4780 * interface is now closed 4781 */ 4782 if ((adapter->flags & FLAG_HAS_AMT) && 4783 !test_bit(__E1000_TESTING, &adapter->state)) 4784 e1000e_release_hw_control(adapter); 4785 4786 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4787 4788 pm_runtime_put_sync(&pdev->dev); 4789 4790 return 0; 4791 } 4792 4793 /** 4794 * e1000_set_mac - Change the Ethernet Address of the NIC 4795 * @netdev: network interface device structure 4796 * @p: pointer to an address structure 4797 * 4798 * Returns 0 on success, negative on failure 4799 **/ 4800 static int e1000_set_mac(struct net_device *netdev, void *p) 4801 { 4802 struct e1000_adapter *adapter = netdev_priv(netdev); 4803 struct e1000_hw *hw = &adapter->hw; 4804 struct sockaddr *addr = p; 4805 4806 if (!is_valid_ether_addr(addr->sa_data)) 4807 return -EADDRNOTAVAIL; 4808 4809 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4810 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4811 4812 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4813 4814 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4815 /* activate the work around */ 4816 e1000e_set_laa_state_82571(&adapter->hw, 1); 4817 4818 /* Hold a copy of the LAA in RAR[14] This is done so that 4819 * between the time RAR[0] gets clobbered and the time it 4820 * gets fixed (in e1000_watchdog), the actual LAA is in one 4821 * of the RARs and no incoming packets directed to this port 4822 * are dropped. Eventually the LAA will be in RAR[0] and 4823 * RAR[14] 4824 */ 4825 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4826 adapter->hw.mac.rar_entry_count - 1); 4827 } 4828 4829 return 0; 4830 } 4831 4832 /** 4833 * e1000e_update_phy_task - work thread to update phy 4834 * @work: pointer to our work struct 4835 * 4836 * this worker thread exists because we must acquire a 4837 * semaphore to read the phy, which we could msleep while 4838 * waiting for it, and we can't msleep in a timer. 4839 **/ 4840 static void e1000e_update_phy_task(struct work_struct *work) 4841 { 4842 struct e1000_adapter *adapter = container_of(work, 4843 struct e1000_adapter, 4844 update_phy_task); 4845 struct e1000_hw *hw = &adapter->hw; 4846 4847 if (test_bit(__E1000_DOWN, &adapter->state)) 4848 return; 4849 4850 e1000_get_phy_info(hw); 4851 4852 /* Enable EEE on 82579 after link up */ 4853 if (hw->phy.type >= e1000_phy_82579) 4854 e1000_set_eee_pchlan(hw); 4855 } 4856 4857 /** 4858 * e1000_update_phy_info - timre call-back to update PHY info 4859 * @data: pointer to adapter cast into an unsigned long 4860 * 4861 * Need to wait a few seconds after link up to get diagnostic information from 4862 * the phy 4863 **/ 4864 static void e1000_update_phy_info(struct timer_list *t) 4865 { 4866 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4867 4868 if (test_bit(__E1000_DOWN, &adapter->state)) 4869 return; 4870 4871 schedule_work(&adapter->update_phy_task); 4872 } 4873 4874 /** 4875 * e1000e_update_phy_stats - Update the PHY statistics counters 4876 * @adapter: board private structure 4877 * 4878 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4879 **/ 4880 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4881 { 4882 struct e1000_hw *hw = &adapter->hw; 4883 s32 ret_val; 4884 u16 phy_data; 4885 4886 ret_val = hw->phy.ops.acquire(hw); 4887 if (ret_val) 4888 return; 4889 4890 /* A page set is expensive so check if already on desired page. 4891 * If not, set to the page with the PHY status registers. 4892 */ 4893 hw->phy.addr = 1; 4894 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4895 &phy_data); 4896 if (ret_val) 4897 goto release; 4898 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4899 ret_val = hw->phy.ops.set_page(hw, 4900 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4901 if (ret_val) 4902 goto release; 4903 } 4904 4905 /* Single Collision Count */ 4906 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4907 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4908 if (!ret_val) 4909 adapter->stats.scc += phy_data; 4910 4911 /* Excessive Collision Count */ 4912 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4913 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4914 if (!ret_val) 4915 adapter->stats.ecol += phy_data; 4916 4917 /* Multiple Collision Count */ 4918 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4919 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4920 if (!ret_val) 4921 adapter->stats.mcc += phy_data; 4922 4923 /* Late Collision Count */ 4924 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4925 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4926 if (!ret_val) 4927 adapter->stats.latecol += phy_data; 4928 4929 /* Collision Count - also used for adaptive IFS */ 4930 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4931 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4932 if (!ret_val) 4933 hw->mac.collision_delta = phy_data; 4934 4935 /* Defer Count */ 4936 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4937 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4938 if (!ret_val) 4939 adapter->stats.dc += phy_data; 4940 4941 /* Transmit with no CRS */ 4942 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4943 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4944 if (!ret_val) 4945 adapter->stats.tncrs += phy_data; 4946 4947 release: 4948 hw->phy.ops.release(hw); 4949 } 4950 4951 /** 4952 * e1000e_update_stats - Update the board statistics counters 4953 * @adapter: board private structure 4954 **/ 4955 static void e1000e_update_stats(struct e1000_adapter *adapter) 4956 { 4957 struct net_device *netdev = adapter->netdev; 4958 struct e1000_hw *hw = &adapter->hw; 4959 struct pci_dev *pdev = adapter->pdev; 4960 4961 /* Prevent stats update while adapter is being reset, or if the pci 4962 * connection is down. 4963 */ 4964 if (adapter->link_speed == 0) 4965 return; 4966 if (pci_channel_offline(pdev)) 4967 return; 4968 4969 adapter->stats.crcerrs += er32(CRCERRS); 4970 adapter->stats.gprc += er32(GPRC); 4971 adapter->stats.gorc += er32(GORCL); 4972 er32(GORCH); /* Clear gorc */ 4973 adapter->stats.bprc += er32(BPRC); 4974 adapter->stats.mprc += er32(MPRC); 4975 adapter->stats.roc += er32(ROC); 4976 4977 adapter->stats.mpc += er32(MPC); 4978 4979 /* Half-duplex statistics */ 4980 if (adapter->link_duplex == HALF_DUPLEX) { 4981 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4982 e1000e_update_phy_stats(adapter); 4983 } else { 4984 adapter->stats.scc += er32(SCC); 4985 adapter->stats.ecol += er32(ECOL); 4986 adapter->stats.mcc += er32(MCC); 4987 adapter->stats.latecol += er32(LATECOL); 4988 adapter->stats.dc += er32(DC); 4989 4990 hw->mac.collision_delta = er32(COLC); 4991 4992 if ((hw->mac.type != e1000_82574) && 4993 (hw->mac.type != e1000_82583)) 4994 adapter->stats.tncrs += er32(TNCRS); 4995 } 4996 adapter->stats.colc += hw->mac.collision_delta; 4997 } 4998 4999 adapter->stats.xonrxc += er32(XONRXC); 5000 adapter->stats.xontxc += er32(XONTXC); 5001 adapter->stats.xoffrxc += er32(XOFFRXC); 5002 adapter->stats.xofftxc += er32(XOFFTXC); 5003 adapter->stats.gptc += er32(GPTC); 5004 adapter->stats.gotc += er32(GOTCL); 5005 er32(GOTCH); /* Clear gotc */ 5006 adapter->stats.rnbc += er32(RNBC); 5007 adapter->stats.ruc += er32(RUC); 5008 5009 adapter->stats.mptc += er32(MPTC); 5010 adapter->stats.bptc += er32(BPTC); 5011 5012 /* used for adaptive IFS */ 5013 5014 hw->mac.tx_packet_delta = er32(TPT); 5015 adapter->stats.tpt += hw->mac.tx_packet_delta; 5016 5017 adapter->stats.algnerrc += er32(ALGNERRC); 5018 adapter->stats.rxerrc += er32(RXERRC); 5019 adapter->stats.cexterr += er32(CEXTERR); 5020 adapter->stats.tsctc += er32(TSCTC); 5021 adapter->stats.tsctfc += er32(TSCTFC); 5022 5023 /* Fill out the OS statistics structure */ 5024 netdev->stats.multicast = adapter->stats.mprc; 5025 netdev->stats.collisions = adapter->stats.colc; 5026 5027 /* Rx Errors */ 5028 5029 /* RLEC on some newer hardware can be incorrect so build 5030 * our own version based on RUC and ROC 5031 */ 5032 netdev->stats.rx_errors = adapter->stats.rxerrc + 5033 adapter->stats.crcerrs + adapter->stats.algnerrc + 5034 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5035 netdev->stats.rx_length_errors = adapter->stats.ruc + 5036 adapter->stats.roc; 5037 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5038 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5039 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5040 5041 /* Tx Errors */ 5042 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5043 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5044 netdev->stats.tx_window_errors = adapter->stats.latecol; 5045 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5046 5047 /* Tx Dropped needs to be maintained elsewhere */ 5048 5049 /* Management Stats */ 5050 adapter->stats.mgptc += er32(MGTPTC); 5051 adapter->stats.mgprc += er32(MGTPRC); 5052 adapter->stats.mgpdc += er32(MGTPDC); 5053 5054 /* Correctable ECC Errors */ 5055 if (hw->mac.type >= e1000_pch_lpt) { 5056 u32 pbeccsts = er32(PBECCSTS); 5057 5058 adapter->corr_errors += 5059 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5060 adapter->uncorr_errors += 5061 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5062 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5063 } 5064 } 5065 5066 /** 5067 * e1000_phy_read_status - Update the PHY register status snapshot 5068 * @adapter: board private structure 5069 **/ 5070 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5071 { 5072 struct e1000_hw *hw = &adapter->hw; 5073 struct e1000_phy_regs *phy = &adapter->phy_regs; 5074 5075 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5076 (er32(STATUS) & E1000_STATUS_LU) && 5077 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5078 int ret_val; 5079 5080 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5081 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5082 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5083 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5084 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5085 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5086 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5087 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5088 if (ret_val) 5089 e_warn("Error reading PHY register\n"); 5090 } else { 5091 /* Do not read PHY registers if link is not up 5092 * Set values to typical power-on defaults 5093 */ 5094 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5095 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5096 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5097 BMSR_ERCAP); 5098 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5099 ADVERTISE_ALL | ADVERTISE_CSMA); 5100 phy->lpa = 0; 5101 phy->expansion = EXPANSION_ENABLENPAGE; 5102 phy->ctrl1000 = ADVERTISE_1000FULL; 5103 phy->stat1000 = 0; 5104 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5105 } 5106 } 5107 5108 static void e1000_print_link_info(struct e1000_adapter *adapter) 5109 { 5110 struct e1000_hw *hw = &adapter->hw; 5111 u32 ctrl = er32(CTRL); 5112 5113 /* Link status message must follow this format for user tools */ 5114 netdev_info(adapter->netdev, 5115 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5116 adapter->link_speed, 5117 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5118 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5119 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5120 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5121 } 5122 5123 static bool e1000e_has_link(struct e1000_adapter *adapter) 5124 { 5125 struct e1000_hw *hw = &adapter->hw; 5126 bool link_active = false; 5127 s32 ret_val = 0; 5128 5129 /* get_link_status is set on LSC (link status) interrupt or 5130 * Rx sequence error interrupt. get_link_status will stay 5131 * true until the check_for_link establishes link 5132 * for copper adapters ONLY 5133 */ 5134 switch (hw->phy.media_type) { 5135 case e1000_media_type_copper: 5136 if (hw->mac.get_link_status) { 5137 ret_val = hw->mac.ops.check_for_link(hw); 5138 link_active = !hw->mac.get_link_status; 5139 } else { 5140 link_active = true; 5141 } 5142 break; 5143 case e1000_media_type_fiber: 5144 ret_val = hw->mac.ops.check_for_link(hw); 5145 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5146 break; 5147 case e1000_media_type_internal_serdes: 5148 ret_val = hw->mac.ops.check_for_link(hw); 5149 link_active = hw->mac.serdes_has_link; 5150 break; 5151 default: 5152 case e1000_media_type_unknown: 5153 break; 5154 } 5155 5156 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5157 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5158 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5159 e_info("Gigabit has been disabled, downgrading speed\n"); 5160 } 5161 5162 return link_active; 5163 } 5164 5165 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5166 { 5167 /* make sure the receive unit is started */ 5168 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5169 (adapter->flags & FLAG_RESTART_NOW)) { 5170 struct e1000_hw *hw = &adapter->hw; 5171 u32 rctl = er32(RCTL); 5172 5173 ew32(RCTL, rctl | E1000_RCTL_EN); 5174 adapter->flags &= ~FLAG_RESTART_NOW; 5175 } 5176 } 5177 5178 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5179 { 5180 struct e1000_hw *hw = &adapter->hw; 5181 5182 /* With 82574 controllers, PHY needs to be checked periodically 5183 * for hung state and reset, if two calls return true 5184 */ 5185 if (e1000_check_phy_82574(hw)) 5186 adapter->phy_hang_count++; 5187 else 5188 adapter->phy_hang_count = 0; 5189 5190 if (adapter->phy_hang_count > 1) { 5191 adapter->phy_hang_count = 0; 5192 e_dbg("PHY appears hung - resetting\n"); 5193 schedule_work(&adapter->reset_task); 5194 } 5195 } 5196 5197 /** 5198 * e1000_watchdog - Timer Call-back 5199 * @data: pointer to adapter cast into an unsigned long 5200 **/ 5201 static void e1000_watchdog(struct timer_list *t) 5202 { 5203 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5204 5205 /* Do the rest outside of interrupt context */ 5206 schedule_work(&adapter->watchdog_task); 5207 5208 /* TODO: make this use queue_delayed_work() */ 5209 } 5210 5211 static void e1000_watchdog_task(struct work_struct *work) 5212 { 5213 struct e1000_adapter *adapter = container_of(work, 5214 struct e1000_adapter, 5215 watchdog_task); 5216 struct net_device *netdev = adapter->netdev; 5217 struct e1000_mac_info *mac = &adapter->hw.mac; 5218 struct e1000_phy_info *phy = &adapter->hw.phy; 5219 struct e1000_ring *tx_ring = adapter->tx_ring; 5220 u32 dmoff_exit_timeout = 100, tries = 0; 5221 struct e1000_hw *hw = &adapter->hw; 5222 u32 link, tctl, pcim_state; 5223 5224 if (test_bit(__E1000_DOWN, &adapter->state)) 5225 return; 5226 5227 link = e1000e_has_link(adapter); 5228 if ((netif_carrier_ok(netdev)) && link) { 5229 /* Cancel scheduled suspend requests. */ 5230 pm_runtime_resume(netdev->dev.parent); 5231 5232 e1000e_enable_receives(adapter); 5233 goto link_up; 5234 } 5235 5236 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5237 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5238 e1000_update_mng_vlan(adapter); 5239 5240 if (link) { 5241 if (!netif_carrier_ok(netdev)) { 5242 bool txb2b = true; 5243 5244 /* Cancel scheduled suspend requests. */ 5245 pm_runtime_resume(netdev->dev.parent); 5246 5247 /* Checking if MAC is in DMoff state*/ 5248 pcim_state = er32(STATUS); 5249 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5250 if (tries++ == dmoff_exit_timeout) { 5251 e_dbg("Error in exiting dmoff\n"); 5252 break; 5253 } 5254 usleep_range(10000, 20000); 5255 pcim_state = er32(STATUS); 5256 5257 /* Checking if MAC exited DMoff state */ 5258 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5259 e1000_phy_hw_reset(&adapter->hw); 5260 } 5261 5262 /* update snapshot of PHY registers on LSC */ 5263 e1000_phy_read_status(adapter); 5264 mac->ops.get_link_up_info(&adapter->hw, 5265 &adapter->link_speed, 5266 &adapter->link_duplex); 5267 e1000_print_link_info(adapter); 5268 5269 /* check if SmartSpeed worked */ 5270 e1000e_check_downshift(hw); 5271 if (phy->speed_downgraded) 5272 netdev_warn(netdev, 5273 "Link Speed was downgraded by SmartSpeed\n"); 5274 5275 /* On supported PHYs, check for duplex mismatch only 5276 * if link has autonegotiated at 10/100 half 5277 */ 5278 if ((hw->phy.type == e1000_phy_igp_3 || 5279 hw->phy.type == e1000_phy_bm) && 5280 hw->mac.autoneg && 5281 (adapter->link_speed == SPEED_10 || 5282 adapter->link_speed == SPEED_100) && 5283 (adapter->link_duplex == HALF_DUPLEX)) { 5284 u16 autoneg_exp; 5285 5286 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5287 5288 if (!(autoneg_exp & EXPANSION_NWAY)) 5289 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5290 } 5291 5292 /* adjust timeout factor according to speed/duplex */ 5293 adapter->tx_timeout_factor = 1; 5294 switch (adapter->link_speed) { 5295 case SPEED_10: 5296 txb2b = false; 5297 adapter->tx_timeout_factor = 16; 5298 break; 5299 case SPEED_100: 5300 txb2b = false; 5301 adapter->tx_timeout_factor = 10; 5302 break; 5303 } 5304 5305 /* workaround: re-program speed mode bit after 5306 * link-up event 5307 */ 5308 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5309 !txb2b) { 5310 u32 tarc0; 5311 5312 tarc0 = er32(TARC(0)); 5313 tarc0 &= ~SPEED_MODE_BIT; 5314 ew32(TARC(0), tarc0); 5315 } 5316 5317 /* disable TSO for pcie and 10/100 speeds, to avoid 5318 * some hardware issues 5319 */ 5320 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5321 switch (adapter->link_speed) { 5322 case SPEED_10: 5323 case SPEED_100: 5324 e_info("10/100 speed: disabling TSO\n"); 5325 netdev->features &= ~NETIF_F_TSO; 5326 netdev->features &= ~NETIF_F_TSO6; 5327 break; 5328 case SPEED_1000: 5329 netdev->features |= NETIF_F_TSO; 5330 netdev->features |= NETIF_F_TSO6; 5331 break; 5332 default: 5333 /* oops */ 5334 break; 5335 } 5336 if (hw->mac.type == e1000_pch_spt) { 5337 netdev->features &= ~NETIF_F_TSO; 5338 netdev->features &= ~NETIF_F_TSO6; 5339 } 5340 } 5341 5342 /* enable transmits in the hardware, need to do this 5343 * after setting TARC(0) 5344 */ 5345 tctl = er32(TCTL); 5346 tctl |= E1000_TCTL_EN; 5347 ew32(TCTL, tctl); 5348 5349 /* Perform any post-link-up configuration before 5350 * reporting link up. 5351 */ 5352 if (phy->ops.cfg_on_link_up) 5353 phy->ops.cfg_on_link_up(hw); 5354 5355 netif_wake_queue(netdev); 5356 netif_carrier_on(netdev); 5357 5358 if (!test_bit(__E1000_DOWN, &adapter->state)) 5359 mod_timer(&adapter->phy_info_timer, 5360 round_jiffies(jiffies + 2 * HZ)); 5361 } 5362 } else { 5363 if (netif_carrier_ok(netdev)) { 5364 adapter->link_speed = 0; 5365 adapter->link_duplex = 0; 5366 /* Link status message must follow this format */ 5367 netdev_info(netdev, "NIC Link is Down\n"); 5368 netif_carrier_off(netdev); 5369 netif_stop_queue(netdev); 5370 if (!test_bit(__E1000_DOWN, &adapter->state)) 5371 mod_timer(&adapter->phy_info_timer, 5372 round_jiffies(jiffies + 2 * HZ)); 5373 5374 /* 8000ES2LAN requires a Rx packet buffer work-around 5375 * on link down event; reset the controller to flush 5376 * the Rx packet buffer. 5377 */ 5378 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5379 adapter->flags |= FLAG_RESTART_NOW; 5380 else 5381 pm_schedule_suspend(netdev->dev.parent, 5382 LINK_TIMEOUT); 5383 } 5384 } 5385 5386 link_up: 5387 spin_lock(&adapter->stats64_lock); 5388 e1000e_update_stats(adapter); 5389 5390 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5391 adapter->tpt_old = adapter->stats.tpt; 5392 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5393 adapter->colc_old = adapter->stats.colc; 5394 5395 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5396 adapter->gorc_old = adapter->stats.gorc; 5397 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5398 adapter->gotc_old = adapter->stats.gotc; 5399 spin_unlock(&adapter->stats64_lock); 5400 5401 /* If the link is lost the controller stops DMA, but 5402 * if there is queued Tx work it cannot be done. So 5403 * reset the controller to flush the Tx packet buffers. 5404 */ 5405 if (!netif_carrier_ok(netdev) && 5406 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5407 adapter->flags |= FLAG_RESTART_NOW; 5408 5409 /* If reset is necessary, do it outside of interrupt context. */ 5410 if (adapter->flags & FLAG_RESTART_NOW) { 5411 schedule_work(&adapter->reset_task); 5412 /* return immediately since reset is imminent */ 5413 return; 5414 } 5415 5416 e1000e_update_adaptive(&adapter->hw); 5417 5418 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5419 if (adapter->itr_setting == 4) { 5420 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5421 * Total asymmetrical Tx or Rx gets ITR=8000; 5422 * everyone else is between 2000-8000. 5423 */ 5424 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5425 u32 dif = (adapter->gotc > adapter->gorc ? 5426 adapter->gotc - adapter->gorc : 5427 adapter->gorc - adapter->gotc) / 10000; 5428 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5429 5430 e1000e_write_itr(adapter, itr); 5431 } 5432 5433 /* Cause software interrupt to ensure Rx ring is cleaned */ 5434 if (adapter->msix_entries) 5435 ew32(ICS, adapter->rx_ring->ims_val); 5436 else 5437 ew32(ICS, E1000_ICS_RXDMT0); 5438 5439 /* flush pending descriptors to memory before detecting Tx hang */ 5440 e1000e_flush_descriptors(adapter); 5441 5442 /* Force detection of hung controller every watchdog period */ 5443 adapter->detect_tx_hung = true; 5444 5445 /* With 82571 controllers, LAA may be overwritten due to controller 5446 * reset from the other port. Set the appropriate LAA in RAR[0] 5447 */ 5448 if (e1000e_get_laa_state_82571(hw)) 5449 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5450 5451 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5452 e1000e_check_82574_phy_workaround(adapter); 5453 5454 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5455 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5456 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5457 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5458 er32(RXSTMPH); 5459 adapter->rx_hwtstamp_cleared++; 5460 } else { 5461 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5462 } 5463 } 5464 5465 /* Reset the timer */ 5466 if (!test_bit(__E1000_DOWN, &adapter->state)) 5467 mod_timer(&adapter->watchdog_timer, 5468 round_jiffies(jiffies + 2 * HZ)); 5469 } 5470 5471 #define E1000_TX_FLAGS_CSUM 0x00000001 5472 #define E1000_TX_FLAGS_VLAN 0x00000002 5473 #define E1000_TX_FLAGS_TSO 0x00000004 5474 #define E1000_TX_FLAGS_IPV4 0x00000008 5475 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5476 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5477 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5478 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5479 5480 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5481 __be16 protocol) 5482 { 5483 struct e1000_context_desc *context_desc; 5484 struct e1000_buffer *buffer_info; 5485 unsigned int i; 5486 u32 cmd_length = 0; 5487 u16 ipcse = 0, mss; 5488 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5489 int err; 5490 5491 if (!skb_is_gso(skb)) 5492 return 0; 5493 5494 err = skb_cow_head(skb, 0); 5495 if (err < 0) 5496 return err; 5497 5498 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5499 mss = skb_shinfo(skb)->gso_size; 5500 if (protocol == htons(ETH_P_IP)) { 5501 struct iphdr *iph = ip_hdr(skb); 5502 iph->tot_len = 0; 5503 iph->check = 0; 5504 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5505 0, IPPROTO_TCP, 0); 5506 cmd_length = E1000_TXD_CMD_IP; 5507 ipcse = skb_transport_offset(skb) - 1; 5508 } else if (skb_is_gso_v6(skb)) { 5509 tcp_v6_gso_csum_prep(skb); 5510 ipcse = 0; 5511 } 5512 ipcss = skb_network_offset(skb); 5513 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5514 tucss = skb_transport_offset(skb); 5515 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5516 5517 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5518 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5519 5520 i = tx_ring->next_to_use; 5521 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5522 buffer_info = &tx_ring->buffer_info[i]; 5523 5524 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5525 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5526 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5527 context_desc->upper_setup.tcp_fields.tucss = tucss; 5528 context_desc->upper_setup.tcp_fields.tucso = tucso; 5529 context_desc->upper_setup.tcp_fields.tucse = 0; 5530 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5531 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5532 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5533 5534 buffer_info->time_stamp = jiffies; 5535 buffer_info->next_to_watch = i; 5536 5537 i++; 5538 if (i == tx_ring->count) 5539 i = 0; 5540 tx_ring->next_to_use = i; 5541 5542 return 1; 5543 } 5544 5545 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5546 __be16 protocol) 5547 { 5548 struct e1000_adapter *adapter = tx_ring->adapter; 5549 struct e1000_context_desc *context_desc; 5550 struct e1000_buffer *buffer_info; 5551 unsigned int i; 5552 u8 css; 5553 u32 cmd_len = E1000_TXD_CMD_DEXT; 5554 5555 if (skb->ip_summed != CHECKSUM_PARTIAL) 5556 return false; 5557 5558 switch (protocol) { 5559 case cpu_to_be16(ETH_P_IP): 5560 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5561 cmd_len |= E1000_TXD_CMD_TCP; 5562 break; 5563 case cpu_to_be16(ETH_P_IPV6): 5564 /* XXX not handling all IPV6 headers */ 5565 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5566 cmd_len |= E1000_TXD_CMD_TCP; 5567 break; 5568 default: 5569 if (unlikely(net_ratelimit())) 5570 e_warn("checksum_partial proto=%x!\n", 5571 be16_to_cpu(protocol)); 5572 break; 5573 } 5574 5575 css = skb_checksum_start_offset(skb); 5576 5577 i = tx_ring->next_to_use; 5578 buffer_info = &tx_ring->buffer_info[i]; 5579 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5580 5581 context_desc->lower_setup.ip_config = 0; 5582 context_desc->upper_setup.tcp_fields.tucss = css; 5583 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5584 context_desc->upper_setup.tcp_fields.tucse = 0; 5585 context_desc->tcp_seg_setup.data = 0; 5586 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5587 5588 buffer_info->time_stamp = jiffies; 5589 buffer_info->next_to_watch = i; 5590 5591 i++; 5592 if (i == tx_ring->count) 5593 i = 0; 5594 tx_ring->next_to_use = i; 5595 5596 return true; 5597 } 5598 5599 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5600 unsigned int first, unsigned int max_per_txd, 5601 unsigned int nr_frags) 5602 { 5603 struct e1000_adapter *adapter = tx_ring->adapter; 5604 struct pci_dev *pdev = adapter->pdev; 5605 struct e1000_buffer *buffer_info; 5606 unsigned int len = skb_headlen(skb); 5607 unsigned int offset = 0, size, count = 0, i; 5608 unsigned int f, bytecount, segs; 5609 5610 i = tx_ring->next_to_use; 5611 5612 while (len) { 5613 buffer_info = &tx_ring->buffer_info[i]; 5614 size = min(len, max_per_txd); 5615 5616 buffer_info->length = size; 5617 buffer_info->time_stamp = jiffies; 5618 buffer_info->next_to_watch = i; 5619 buffer_info->dma = dma_map_single(&pdev->dev, 5620 skb->data + offset, 5621 size, DMA_TO_DEVICE); 5622 buffer_info->mapped_as_page = false; 5623 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5624 goto dma_error; 5625 5626 len -= size; 5627 offset += size; 5628 count++; 5629 5630 if (len) { 5631 i++; 5632 if (i == tx_ring->count) 5633 i = 0; 5634 } 5635 } 5636 5637 for (f = 0; f < nr_frags; f++) { 5638 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5639 5640 len = skb_frag_size(frag); 5641 offset = 0; 5642 5643 while (len) { 5644 i++; 5645 if (i == tx_ring->count) 5646 i = 0; 5647 5648 buffer_info = &tx_ring->buffer_info[i]; 5649 size = min(len, max_per_txd); 5650 5651 buffer_info->length = size; 5652 buffer_info->time_stamp = jiffies; 5653 buffer_info->next_to_watch = i; 5654 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5655 offset, size, 5656 DMA_TO_DEVICE); 5657 buffer_info->mapped_as_page = true; 5658 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5659 goto dma_error; 5660 5661 len -= size; 5662 offset += size; 5663 count++; 5664 } 5665 } 5666 5667 segs = skb_shinfo(skb)->gso_segs ? : 1; 5668 /* multiply data chunks by size of headers */ 5669 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5670 5671 tx_ring->buffer_info[i].skb = skb; 5672 tx_ring->buffer_info[i].segs = segs; 5673 tx_ring->buffer_info[i].bytecount = bytecount; 5674 tx_ring->buffer_info[first].next_to_watch = i; 5675 5676 return count; 5677 5678 dma_error: 5679 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5680 buffer_info->dma = 0; 5681 if (count) 5682 count--; 5683 5684 while (count--) { 5685 if (i == 0) 5686 i += tx_ring->count; 5687 i--; 5688 buffer_info = &tx_ring->buffer_info[i]; 5689 e1000_put_txbuf(tx_ring, buffer_info, true); 5690 } 5691 5692 return 0; 5693 } 5694 5695 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5696 { 5697 struct e1000_adapter *adapter = tx_ring->adapter; 5698 struct e1000_tx_desc *tx_desc = NULL; 5699 struct e1000_buffer *buffer_info; 5700 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5701 unsigned int i; 5702 5703 if (tx_flags & E1000_TX_FLAGS_TSO) { 5704 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5705 E1000_TXD_CMD_TSE; 5706 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5707 5708 if (tx_flags & E1000_TX_FLAGS_IPV4) 5709 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5710 } 5711 5712 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5713 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5714 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5715 } 5716 5717 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5718 txd_lower |= E1000_TXD_CMD_VLE; 5719 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5720 } 5721 5722 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5723 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5724 5725 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5726 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5727 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5728 } 5729 5730 i = tx_ring->next_to_use; 5731 5732 do { 5733 buffer_info = &tx_ring->buffer_info[i]; 5734 tx_desc = E1000_TX_DESC(*tx_ring, i); 5735 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5736 tx_desc->lower.data = cpu_to_le32(txd_lower | 5737 buffer_info->length); 5738 tx_desc->upper.data = cpu_to_le32(txd_upper); 5739 5740 i++; 5741 if (i == tx_ring->count) 5742 i = 0; 5743 } while (--count > 0); 5744 5745 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5746 5747 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5748 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5749 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5750 5751 /* Force memory writes to complete before letting h/w 5752 * know there are new descriptors to fetch. (Only 5753 * applicable for weak-ordered memory model archs, 5754 * such as IA-64). 5755 */ 5756 wmb(); 5757 5758 tx_ring->next_to_use = i; 5759 } 5760 5761 #define MINIMUM_DHCP_PACKET_SIZE 282 5762 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5763 struct sk_buff *skb) 5764 { 5765 struct e1000_hw *hw = &adapter->hw; 5766 u16 length, offset; 5767 5768 if (skb_vlan_tag_present(skb) && 5769 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5770 (adapter->hw.mng_cookie.status & 5771 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5772 return 0; 5773 5774 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5775 return 0; 5776 5777 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5778 return 0; 5779 5780 { 5781 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5782 struct udphdr *udp; 5783 5784 if (ip->protocol != IPPROTO_UDP) 5785 return 0; 5786 5787 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5788 if (ntohs(udp->dest) != 67) 5789 return 0; 5790 5791 offset = (u8 *)udp + 8 - skb->data; 5792 length = skb->len - offset; 5793 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5794 } 5795 5796 return 0; 5797 } 5798 5799 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5800 { 5801 struct e1000_adapter *adapter = tx_ring->adapter; 5802 5803 netif_stop_queue(adapter->netdev); 5804 /* Herbert's original patch had: 5805 * smp_mb__after_netif_stop_queue(); 5806 * but since that doesn't exist yet, just open code it. 5807 */ 5808 smp_mb(); 5809 5810 /* We need to check again in a case another CPU has just 5811 * made room available. 5812 */ 5813 if (e1000_desc_unused(tx_ring) < size) 5814 return -EBUSY; 5815 5816 /* A reprieve! */ 5817 netif_start_queue(adapter->netdev); 5818 ++adapter->restart_queue; 5819 return 0; 5820 } 5821 5822 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5823 { 5824 BUG_ON(size > tx_ring->count); 5825 5826 if (e1000_desc_unused(tx_ring) >= size) 5827 return 0; 5828 return __e1000_maybe_stop_tx(tx_ring, size); 5829 } 5830 5831 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5832 struct net_device *netdev) 5833 { 5834 struct e1000_adapter *adapter = netdev_priv(netdev); 5835 struct e1000_ring *tx_ring = adapter->tx_ring; 5836 unsigned int first; 5837 unsigned int tx_flags = 0; 5838 unsigned int len = skb_headlen(skb); 5839 unsigned int nr_frags; 5840 unsigned int mss; 5841 int count = 0; 5842 int tso; 5843 unsigned int f; 5844 __be16 protocol = vlan_get_protocol(skb); 5845 5846 if (test_bit(__E1000_DOWN, &adapter->state)) { 5847 dev_kfree_skb_any(skb); 5848 return NETDEV_TX_OK; 5849 } 5850 5851 if (skb->len <= 0) { 5852 dev_kfree_skb_any(skb); 5853 return NETDEV_TX_OK; 5854 } 5855 5856 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5857 * pad skb in order to meet this minimum size requirement 5858 */ 5859 if (skb_put_padto(skb, 17)) 5860 return NETDEV_TX_OK; 5861 5862 mss = skb_shinfo(skb)->gso_size; 5863 if (mss) { 5864 u8 hdr_len; 5865 5866 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5867 * points to just header, pull a few bytes of payload from 5868 * frags into skb->data 5869 */ 5870 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5871 /* we do this workaround for ES2LAN, but it is un-necessary, 5872 * avoiding it could save a lot of cycles 5873 */ 5874 if (skb->data_len && (hdr_len == len)) { 5875 unsigned int pull_size; 5876 5877 pull_size = min_t(unsigned int, 4, skb->data_len); 5878 if (!__pskb_pull_tail(skb, pull_size)) { 5879 e_err("__pskb_pull_tail failed.\n"); 5880 dev_kfree_skb_any(skb); 5881 return NETDEV_TX_OK; 5882 } 5883 len = skb_headlen(skb); 5884 } 5885 } 5886 5887 /* reserve a descriptor for the offload context */ 5888 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5889 count++; 5890 count++; 5891 5892 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5893 5894 nr_frags = skb_shinfo(skb)->nr_frags; 5895 for (f = 0; f < nr_frags; f++) 5896 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5897 adapter->tx_fifo_limit); 5898 5899 if (adapter->hw.mac.tx_pkt_filtering) 5900 e1000_transfer_dhcp_info(adapter, skb); 5901 5902 /* need: count + 2 desc gap to keep tail from touching 5903 * head, otherwise try next time 5904 */ 5905 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5906 return NETDEV_TX_BUSY; 5907 5908 if (skb_vlan_tag_present(skb)) { 5909 tx_flags |= E1000_TX_FLAGS_VLAN; 5910 tx_flags |= (skb_vlan_tag_get(skb) << 5911 E1000_TX_FLAGS_VLAN_SHIFT); 5912 } 5913 5914 first = tx_ring->next_to_use; 5915 5916 tso = e1000_tso(tx_ring, skb, protocol); 5917 if (tso < 0) { 5918 dev_kfree_skb_any(skb); 5919 return NETDEV_TX_OK; 5920 } 5921 5922 if (tso) 5923 tx_flags |= E1000_TX_FLAGS_TSO; 5924 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5925 tx_flags |= E1000_TX_FLAGS_CSUM; 5926 5927 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5928 * 82571 hardware supports TSO capabilities for IPv6 as well... 5929 * no longer assume, we must. 5930 */ 5931 if (protocol == htons(ETH_P_IP)) 5932 tx_flags |= E1000_TX_FLAGS_IPV4; 5933 5934 if (unlikely(skb->no_fcs)) 5935 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5936 5937 /* if count is 0 then mapping error has occurred */ 5938 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5939 nr_frags); 5940 if (count) { 5941 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5942 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5943 if (!adapter->tx_hwtstamp_skb) { 5944 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5945 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5946 adapter->tx_hwtstamp_skb = skb_get(skb); 5947 adapter->tx_hwtstamp_start = jiffies; 5948 schedule_work(&adapter->tx_hwtstamp_work); 5949 } else { 5950 adapter->tx_hwtstamp_skipped++; 5951 } 5952 } 5953 5954 skb_tx_timestamp(skb); 5955 5956 netdev_sent_queue(netdev, skb->len); 5957 e1000_tx_queue(tx_ring, tx_flags, count); 5958 /* Make sure there is space in the ring for the next send. */ 5959 e1000_maybe_stop_tx(tx_ring, 5960 (MAX_SKB_FRAGS * 5961 DIV_ROUND_UP(PAGE_SIZE, 5962 adapter->tx_fifo_limit) + 2)); 5963 5964 if (!netdev_xmit_more() || 5965 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5966 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5967 e1000e_update_tdt_wa(tx_ring, 5968 tx_ring->next_to_use); 5969 else 5970 writel(tx_ring->next_to_use, tx_ring->tail); 5971 } 5972 } else { 5973 dev_kfree_skb_any(skb); 5974 tx_ring->buffer_info[first].time_stamp = 0; 5975 tx_ring->next_to_use = first; 5976 } 5977 5978 return NETDEV_TX_OK; 5979 } 5980 5981 /** 5982 * e1000_tx_timeout - Respond to a Tx Hang 5983 * @netdev: network interface device structure 5984 **/ 5985 static void e1000_tx_timeout(struct net_device *netdev, unsigned int txqueue) 5986 { 5987 struct e1000_adapter *adapter = netdev_priv(netdev); 5988 5989 /* Do the reset outside of interrupt context */ 5990 adapter->tx_timeout_count++; 5991 schedule_work(&adapter->reset_task); 5992 } 5993 5994 static void e1000_reset_task(struct work_struct *work) 5995 { 5996 struct e1000_adapter *adapter; 5997 adapter = container_of(work, struct e1000_adapter, reset_task); 5998 5999 /* don't run the task if already down */ 6000 if (test_bit(__E1000_DOWN, &adapter->state)) 6001 return; 6002 6003 if (!(adapter->flags & FLAG_RESTART_NOW)) { 6004 e1000e_dump(adapter); 6005 e_err("Reset adapter unexpectedly\n"); 6006 } 6007 e1000e_reinit_locked(adapter); 6008 } 6009 6010 /** 6011 * e1000_get_stats64 - Get System Network Statistics 6012 * @netdev: network interface device structure 6013 * @stats: rtnl_link_stats64 pointer 6014 * 6015 * Returns the address of the device statistics structure. 6016 **/ 6017 void e1000e_get_stats64(struct net_device *netdev, 6018 struct rtnl_link_stats64 *stats) 6019 { 6020 struct e1000_adapter *adapter = netdev_priv(netdev); 6021 6022 spin_lock(&adapter->stats64_lock); 6023 e1000e_update_stats(adapter); 6024 /* Fill out the OS statistics structure */ 6025 stats->rx_bytes = adapter->stats.gorc; 6026 stats->rx_packets = adapter->stats.gprc; 6027 stats->tx_bytes = adapter->stats.gotc; 6028 stats->tx_packets = adapter->stats.gptc; 6029 stats->multicast = adapter->stats.mprc; 6030 stats->collisions = adapter->stats.colc; 6031 6032 /* Rx Errors */ 6033 6034 /* RLEC on some newer hardware can be incorrect so build 6035 * our own version based on RUC and ROC 6036 */ 6037 stats->rx_errors = adapter->stats.rxerrc + 6038 adapter->stats.crcerrs + adapter->stats.algnerrc + 6039 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 6040 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 6041 stats->rx_crc_errors = adapter->stats.crcerrs; 6042 stats->rx_frame_errors = adapter->stats.algnerrc; 6043 stats->rx_missed_errors = adapter->stats.mpc; 6044 6045 /* Tx Errors */ 6046 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6047 stats->tx_aborted_errors = adapter->stats.ecol; 6048 stats->tx_window_errors = adapter->stats.latecol; 6049 stats->tx_carrier_errors = adapter->stats.tncrs; 6050 6051 /* Tx Dropped needs to be maintained elsewhere */ 6052 6053 spin_unlock(&adapter->stats64_lock); 6054 } 6055 6056 /** 6057 * e1000_change_mtu - Change the Maximum Transfer Unit 6058 * @netdev: network interface device structure 6059 * @new_mtu: new value for maximum frame size 6060 * 6061 * Returns 0 on success, negative on failure 6062 **/ 6063 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6064 { 6065 struct e1000_adapter *adapter = netdev_priv(netdev); 6066 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6067 6068 /* Jumbo frame support */ 6069 if ((new_mtu > ETH_DATA_LEN) && 6070 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6071 e_err("Jumbo Frames not supported.\n"); 6072 return -EINVAL; 6073 } 6074 6075 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6076 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6077 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6078 (new_mtu > ETH_DATA_LEN)) { 6079 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6080 return -EINVAL; 6081 } 6082 6083 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6084 usleep_range(1000, 1100); 6085 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6086 adapter->max_frame_size = max_frame; 6087 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6088 netdev->mtu, new_mtu); 6089 netdev->mtu = new_mtu; 6090 6091 pm_runtime_get_sync(netdev->dev.parent); 6092 6093 if (netif_running(netdev)) 6094 e1000e_down(adapter, true); 6095 6096 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6097 * means we reserve 2 more, this pushes us to allocate from the next 6098 * larger slab size. 6099 * i.e. RXBUFFER_2048 --> size-4096 slab 6100 * However with the new *_jumbo_rx* routines, jumbo receives will use 6101 * fragmented skbs 6102 */ 6103 6104 if (max_frame <= 2048) 6105 adapter->rx_buffer_len = 2048; 6106 else 6107 adapter->rx_buffer_len = 4096; 6108 6109 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6110 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6111 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6112 6113 if (netif_running(netdev)) 6114 e1000e_up(adapter); 6115 else 6116 e1000e_reset(adapter); 6117 6118 pm_runtime_put_sync(netdev->dev.parent); 6119 6120 clear_bit(__E1000_RESETTING, &adapter->state); 6121 6122 return 0; 6123 } 6124 6125 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6126 int cmd) 6127 { 6128 struct e1000_adapter *adapter = netdev_priv(netdev); 6129 struct mii_ioctl_data *data = if_mii(ifr); 6130 6131 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6132 return -EOPNOTSUPP; 6133 6134 switch (cmd) { 6135 case SIOCGMIIPHY: 6136 data->phy_id = adapter->hw.phy.addr; 6137 break; 6138 case SIOCGMIIREG: 6139 e1000_phy_read_status(adapter); 6140 6141 switch (data->reg_num & 0x1F) { 6142 case MII_BMCR: 6143 data->val_out = adapter->phy_regs.bmcr; 6144 break; 6145 case MII_BMSR: 6146 data->val_out = adapter->phy_regs.bmsr; 6147 break; 6148 case MII_PHYSID1: 6149 data->val_out = (adapter->hw.phy.id >> 16); 6150 break; 6151 case MII_PHYSID2: 6152 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6153 break; 6154 case MII_ADVERTISE: 6155 data->val_out = adapter->phy_regs.advertise; 6156 break; 6157 case MII_LPA: 6158 data->val_out = adapter->phy_regs.lpa; 6159 break; 6160 case MII_EXPANSION: 6161 data->val_out = adapter->phy_regs.expansion; 6162 break; 6163 case MII_CTRL1000: 6164 data->val_out = adapter->phy_regs.ctrl1000; 6165 break; 6166 case MII_STAT1000: 6167 data->val_out = adapter->phy_regs.stat1000; 6168 break; 6169 case MII_ESTATUS: 6170 data->val_out = adapter->phy_regs.estatus; 6171 break; 6172 default: 6173 return -EIO; 6174 } 6175 break; 6176 case SIOCSMIIREG: 6177 default: 6178 return -EOPNOTSUPP; 6179 } 6180 return 0; 6181 } 6182 6183 /** 6184 * e1000e_hwtstamp_ioctl - control hardware time stamping 6185 * @netdev: network interface device structure 6186 * @ifreq: interface request 6187 * 6188 * Outgoing time stamping can be enabled and disabled. Play nice and 6189 * disable it when requested, although it shouldn't cause any overhead 6190 * when no packet needs it. At most one packet in the queue may be 6191 * marked for time stamping, otherwise it would be impossible to tell 6192 * for sure to which packet the hardware time stamp belongs. 6193 * 6194 * Incoming time stamping has to be configured via the hardware filters. 6195 * Not all combinations are supported, in particular event type has to be 6196 * specified. Matching the kind of event packet is not supported, with the 6197 * exception of "all V2 events regardless of level 2 or 4". 6198 **/ 6199 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6200 { 6201 struct e1000_adapter *adapter = netdev_priv(netdev); 6202 struct hwtstamp_config config; 6203 int ret_val; 6204 6205 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6206 return -EFAULT; 6207 6208 ret_val = e1000e_config_hwtstamp(adapter, &config); 6209 if (ret_val) 6210 return ret_val; 6211 6212 switch (config.rx_filter) { 6213 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6214 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6215 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6216 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6217 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6218 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6219 /* With V2 type filters which specify a Sync or Delay Request, 6220 * Path Delay Request/Response messages are also time stamped 6221 * by hardware so notify the caller the requested packets plus 6222 * some others are time stamped. 6223 */ 6224 config.rx_filter = HWTSTAMP_FILTER_SOME; 6225 break; 6226 default: 6227 break; 6228 } 6229 6230 return copy_to_user(ifr->ifr_data, &config, 6231 sizeof(config)) ? -EFAULT : 0; 6232 } 6233 6234 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6235 { 6236 struct e1000_adapter *adapter = netdev_priv(netdev); 6237 6238 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6239 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6240 } 6241 6242 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6243 { 6244 switch (cmd) { 6245 case SIOCGMIIPHY: 6246 case SIOCGMIIREG: 6247 case SIOCSMIIREG: 6248 return e1000_mii_ioctl(netdev, ifr, cmd); 6249 case SIOCSHWTSTAMP: 6250 return e1000e_hwtstamp_set(netdev, ifr); 6251 case SIOCGHWTSTAMP: 6252 return e1000e_hwtstamp_get(netdev, ifr); 6253 default: 6254 return -EOPNOTSUPP; 6255 } 6256 } 6257 6258 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6259 { 6260 struct e1000_hw *hw = &adapter->hw; 6261 u32 i, mac_reg, wuc; 6262 u16 phy_reg, wuc_enable; 6263 int retval; 6264 6265 /* copy MAC RARs to PHY RARs */ 6266 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6267 6268 retval = hw->phy.ops.acquire(hw); 6269 if (retval) { 6270 e_err("Could not acquire PHY\n"); 6271 return retval; 6272 } 6273 6274 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6275 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6276 if (retval) 6277 goto release; 6278 6279 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6280 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6281 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6282 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6283 (u16)(mac_reg & 0xFFFF)); 6284 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6285 (u16)((mac_reg >> 16) & 0xFFFF)); 6286 } 6287 6288 /* configure PHY Rx Control register */ 6289 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6290 mac_reg = er32(RCTL); 6291 if (mac_reg & E1000_RCTL_UPE) 6292 phy_reg |= BM_RCTL_UPE; 6293 if (mac_reg & E1000_RCTL_MPE) 6294 phy_reg |= BM_RCTL_MPE; 6295 phy_reg &= ~(BM_RCTL_MO_MASK); 6296 if (mac_reg & E1000_RCTL_MO_3) 6297 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6298 << BM_RCTL_MO_SHIFT); 6299 if (mac_reg & E1000_RCTL_BAM) 6300 phy_reg |= BM_RCTL_BAM; 6301 if (mac_reg & E1000_RCTL_PMCF) 6302 phy_reg |= BM_RCTL_PMCF; 6303 mac_reg = er32(CTRL); 6304 if (mac_reg & E1000_CTRL_RFCE) 6305 phy_reg |= BM_RCTL_RFCE; 6306 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6307 6308 wuc = E1000_WUC_PME_EN; 6309 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6310 wuc |= E1000_WUC_APME; 6311 6312 /* enable PHY wakeup in MAC register */ 6313 ew32(WUFC, wufc); 6314 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6315 E1000_WUC_PME_STATUS | wuc)); 6316 6317 /* configure and enable PHY wakeup in PHY registers */ 6318 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6319 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6320 6321 /* activate PHY wakeup */ 6322 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6323 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6324 if (retval) 6325 e_err("Could not set PHY Host Wakeup bit\n"); 6326 release: 6327 hw->phy.ops.release(hw); 6328 6329 return retval; 6330 } 6331 6332 static void e1000e_flush_lpic(struct pci_dev *pdev) 6333 { 6334 struct net_device *netdev = pci_get_drvdata(pdev); 6335 struct e1000_adapter *adapter = netdev_priv(netdev); 6336 struct e1000_hw *hw = &adapter->hw; 6337 u32 ret_val; 6338 6339 pm_runtime_get_sync(netdev->dev.parent); 6340 6341 ret_val = hw->phy.ops.acquire(hw); 6342 if (ret_val) 6343 goto fl_out; 6344 6345 pr_info("EEE TX LPI TIMER: %08X\n", 6346 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6347 6348 hw->phy.ops.release(hw); 6349 6350 fl_out: 6351 pm_runtime_put_sync(netdev->dev.parent); 6352 } 6353 6354 #ifdef CONFIG_PM_SLEEP 6355 /* S0ix implementation */ 6356 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6357 { 6358 struct e1000_hw *hw = &adapter->hw; 6359 u32 mac_data; 6360 u16 phy_data; 6361 6362 /* Disable the periodic inband message, 6363 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6364 */ 6365 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6366 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6367 phy_data |= BIT(10); 6368 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6369 6370 /* Make sure we don't exit K1 every time a new packet arrives 6371 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6372 */ 6373 e1e_rphy(hw, I217_CGFREG, &phy_data); 6374 phy_data |= BIT(5); 6375 e1e_wphy(hw, I217_CGFREG, phy_data); 6376 6377 /* Change the MAC/PHY interface to SMBus 6378 * Force the SMBus in PHY page769_23[0] = 1 6379 * Force the SMBus in MAC CTRL_EXT[11] = 1 6380 */ 6381 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6382 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6383 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6384 mac_data = er32(CTRL_EXT); 6385 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6386 ew32(CTRL_EXT, mac_data); 6387 6388 /* DFT control: PHY bit: page769_20[0] = 1 6389 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6390 */ 6391 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6392 phy_data |= BIT(0); 6393 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6394 6395 mac_data = er32(EXTCNF_CTRL); 6396 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6397 ew32(EXTCNF_CTRL, mac_data); 6398 6399 /* Check MAC Tx/Rx packet buffer pointers. 6400 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6401 * pending traffic indication that would prevent power gating. 6402 */ 6403 mac_data = er32(TDFH); 6404 if (mac_data) 6405 ew32(TDFH, 0); 6406 mac_data = er32(TDFT); 6407 if (mac_data) 6408 ew32(TDFT, 0); 6409 mac_data = er32(TDFHS); 6410 if (mac_data) 6411 ew32(TDFHS, 0); 6412 mac_data = er32(TDFTS); 6413 if (mac_data) 6414 ew32(TDFTS, 0); 6415 mac_data = er32(TDFPC); 6416 if (mac_data) 6417 ew32(TDFPC, 0); 6418 mac_data = er32(RDFH); 6419 if (mac_data) 6420 ew32(RDFH, 0); 6421 mac_data = er32(RDFT); 6422 if (mac_data) 6423 ew32(RDFT, 0); 6424 mac_data = er32(RDFHS); 6425 if (mac_data) 6426 ew32(RDFHS, 0); 6427 mac_data = er32(RDFTS); 6428 if (mac_data) 6429 ew32(RDFTS, 0); 6430 mac_data = er32(RDFPC); 6431 if (mac_data) 6432 ew32(RDFPC, 0); 6433 6434 /* Enable the Dynamic Power Gating in the MAC */ 6435 mac_data = er32(FEXTNVM7); 6436 mac_data |= BIT(22); 6437 ew32(FEXTNVM7, mac_data); 6438 6439 /* Disable the time synchronization clock */ 6440 mac_data = er32(FEXTNVM7); 6441 mac_data |= BIT(31); 6442 mac_data &= ~BIT(0); 6443 ew32(FEXTNVM7, mac_data); 6444 6445 /* Dynamic Power Gating Enable */ 6446 mac_data = er32(CTRL_EXT); 6447 mac_data |= BIT(3); 6448 ew32(CTRL_EXT, mac_data); 6449 6450 /* Disable disconnected cable conditioning for Power Gating */ 6451 mac_data = er32(DPGFR); 6452 mac_data |= BIT(2); 6453 ew32(DPGFR, mac_data); 6454 6455 /* Don't wake from dynamic Power Gating with clock request */ 6456 mac_data = er32(FEXTNVM12); 6457 mac_data |= BIT(12); 6458 ew32(FEXTNVM12, mac_data); 6459 6460 /* Ungate PGCB clock */ 6461 mac_data = er32(FEXTNVM9); 6462 mac_data |= BIT(28); 6463 ew32(FEXTNVM9, mac_data); 6464 6465 /* Enable K1 off to enable mPHY Power Gating */ 6466 mac_data = er32(FEXTNVM6); 6467 mac_data |= BIT(31); 6468 ew32(FEXTNVM12, mac_data); 6469 6470 /* Enable mPHY power gating for any link and speed */ 6471 mac_data = er32(FEXTNVM8); 6472 mac_data |= BIT(9); 6473 ew32(FEXTNVM8, mac_data); 6474 6475 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6476 mac_data = er32(CTRL_EXT); 6477 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6478 ew32(CTRL_EXT, mac_data); 6479 6480 /* No MAC DPG gating SLP_S0 in modern standby 6481 * Switch the logic of the lanphypc to use PMC counter 6482 */ 6483 mac_data = er32(FEXTNVM5); 6484 mac_data |= BIT(7); 6485 ew32(FEXTNVM5, mac_data); 6486 } 6487 6488 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6489 { 6490 struct e1000_hw *hw = &adapter->hw; 6491 u32 mac_data; 6492 u16 phy_data; 6493 6494 /* Disable the Dynamic Power Gating in the MAC */ 6495 mac_data = er32(FEXTNVM7); 6496 mac_data &= 0xFFBFFFFF; 6497 ew32(FEXTNVM7, mac_data); 6498 6499 /* Enable the time synchronization clock */ 6500 mac_data = er32(FEXTNVM7); 6501 mac_data |= BIT(0); 6502 ew32(FEXTNVM7, mac_data); 6503 6504 /* Disable mPHY power gating for any link and speed */ 6505 mac_data = er32(FEXTNVM8); 6506 mac_data &= ~BIT(9); 6507 ew32(FEXTNVM8, mac_data); 6508 6509 /* Disable K1 off */ 6510 mac_data = er32(FEXTNVM6); 6511 mac_data &= ~BIT(31); 6512 ew32(FEXTNVM12, mac_data); 6513 6514 /* Disable Ungate PGCB clock */ 6515 mac_data = er32(FEXTNVM9); 6516 mac_data &= ~BIT(28); 6517 ew32(FEXTNVM9, mac_data); 6518 6519 /* Cancel not waking from dynamic 6520 * Power Gating with clock request 6521 */ 6522 mac_data = er32(FEXTNVM12); 6523 mac_data &= ~BIT(12); 6524 ew32(FEXTNVM12, mac_data); 6525 6526 /* Cancel disable disconnected cable conditioning 6527 * for Power Gating 6528 */ 6529 mac_data = er32(DPGFR); 6530 mac_data &= ~BIT(2); 6531 ew32(DPGFR, mac_data); 6532 6533 /* Disable Dynamic Power Gating */ 6534 mac_data = er32(CTRL_EXT); 6535 mac_data &= 0xFFFFFFF7; 6536 ew32(CTRL_EXT, mac_data); 6537 6538 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6539 mac_data = er32(CTRL_EXT); 6540 mac_data &= 0xFFF7FFFF; 6541 ew32(CTRL_EXT, mac_data); 6542 6543 /* Revert the lanphypc logic to use the internal Gbe counter 6544 * and not the PMC counter 6545 */ 6546 mac_data = er32(FEXTNVM5); 6547 mac_data &= 0xFFFFFF7F; 6548 ew32(FEXTNVM5, mac_data); 6549 6550 /* Enable the periodic inband message, 6551 * Request PCIe clock in K1 page770_17[10:9] =01b 6552 */ 6553 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6554 phy_data &= 0xFBFF; 6555 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6556 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6557 6558 /* Return back configuration 6559 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6560 */ 6561 e1e_rphy(hw, I217_CGFREG, &phy_data); 6562 phy_data &= 0xFFDF; 6563 e1e_wphy(hw, I217_CGFREG, phy_data); 6564 6565 /* Change the MAC/PHY interface to Kumeran 6566 * Unforce the SMBus in PHY page769_23[0] = 0 6567 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6568 */ 6569 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6570 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6571 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6572 mac_data = er32(CTRL_EXT); 6573 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6574 ew32(CTRL_EXT, mac_data); 6575 } 6576 #endif /* CONFIG_PM_SLEEP */ 6577 6578 static int e1000e_pm_freeze(struct device *dev) 6579 { 6580 struct net_device *netdev = dev_get_drvdata(dev); 6581 struct e1000_adapter *adapter = netdev_priv(netdev); 6582 bool present; 6583 6584 rtnl_lock(); 6585 6586 present = netif_device_present(netdev); 6587 netif_device_detach(netdev); 6588 6589 if (present && netif_running(netdev)) { 6590 int count = E1000_CHECK_RESET_COUNT; 6591 6592 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6593 usleep_range(10000, 11000); 6594 6595 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6596 6597 /* Quiesce the device without resetting the hardware */ 6598 e1000e_down(adapter, false); 6599 e1000_free_irq(adapter); 6600 } 6601 rtnl_unlock(); 6602 6603 e1000e_reset_interrupt_capability(adapter); 6604 6605 /* Allow time for pending master requests to run */ 6606 e1000e_disable_pcie_master(&adapter->hw); 6607 6608 return 0; 6609 } 6610 6611 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6612 { 6613 struct net_device *netdev = pci_get_drvdata(pdev); 6614 struct e1000_adapter *adapter = netdev_priv(netdev); 6615 struct e1000_hw *hw = &adapter->hw; 6616 u32 ctrl, ctrl_ext, rctl, status; 6617 /* Runtime suspend should only enable wakeup for link changes */ 6618 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6619 int retval = 0; 6620 6621 status = er32(STATUS); 6622 if (status & E1000_STATUS_LU) 6623 wufc &= ~E1000_WUFC_LNKC; 6624 6625 if (wufc) { 6626 e1000_setup_rctl(adapter); 6627 e1000e_set_rx_mode(netdev); 6628 6629 /* turn on all-multi mode if wake on multicast is enabled */ 6630 if (wufc & E1000_WUFC_MC) { 6631 rctl = er32(RCTL); 6632 rctl |= E1000_RCTL_MPE; 6633 ew32(RCTL, rctl); 6634 } 6635 6636 ctrl = er32(CTRL); 6637 ctrl |= E1000_CTRL_ADVD3WUC; 6638 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6639 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6640 ew32(CTRL, ctrl); 6641 6642 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6643 adapter->hw.phy.media_type == 6644 e1000_media_type_internal_serdes) { 6645 /* keep the laser running in D3 */ 6646 ctrl_ext = er32(CTRL_EXT); 6647 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6648 ew32(CTRL_EXT, ctrl_ext); 6649 } 6650 6651 if (!runtime) 6652 e1000e_power_up_phy(adapter); 6653 6654 if (adapter->flags & FLAG_IS_ICH) 6655 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6656 6657 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6658 /* enable wakeup by the PHY */ 6659 retval = e1000_init_phy_wakeup(adapter, wufc); 6660 if (retval) 6661 return retval; 6662 } else { 6663 /* enable wakeup by the MAC */ 6664 ew32(WUFC, wufc); 6665 ew32(WUC, E1000_WUC_PME_EN); 6666 } 6667 } else { 6668 ew32(WUC, 0); 6669 ew32(WUFC, 0); 6670 6671 e1000_power_down_phy(adapter); 6672 } 6673 6674 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6675 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6676 } else if (hw->mac.type >= e1000_pch_lpt) { 6677 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6678 /* ULP does not support wake from unicast, multicast 6679 * or broadcast. 6680 */ 6681 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6682 6683 if (retval) 6684 return retval; 6685 } 6686 6687 /* Ensure that the appropriate bits are set in LPI_CTRL 6688 * for EEE in Sx 6689 */ 6690 if ((hw->phy.type >= e1000_phy_i217) && 6691 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6692 u16 lpi_ctrl = 0; 6693 6694 retval = hw->phy.ops.acquire(hw); 6695 if (!retval) { 6696 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6697 &lpi_ctrl); 6698 if (!retval) { 6699 if (adapter->eee_advert & 6700 hw->dev_spec.ich8lan.eee_lp_ability & 6701 I82579_EEE_100_SUPPORTED) 6702 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6703 if (adapter->eee_advert & 6704 hw->dev_spec.ich8lan.eee_lp_ability & 6705 I82579_EEE_1000_SUPPORTED) 6706 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6707 6708 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6709 lpi_ctrl); 6710 } 6711 } 6712 hw->phy.ops.release(hw); 6713 } 6714 6715 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6716 * would have already happened in close and is redundant. 6717 */ 6718 e1000e_release_hw_control(adapter); 6719 6720 pci_clear_master(pdev); 6721 6722 /* The pci-e switch on some quad port adapters will report a 6723 * correctable error when the MAC transitions from D0 to D3. To 6724 * prevent this we need to mask off the correctable errors on the 6725 * downstream port of the pci-e switch. 6726 * 6727 * We don't have the associated upstream bridge while assigning 6728 * the PCI device into guest. For example, the KVM on power is 6729 * one of the cases. 6730 */ 6731 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6732 struct pci_dev *us_dev = pdev->bus->self; 6733 u16 devctl; 6734 6735 if (!us_dev) 6736 return 0; 6737 6738 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6739 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6740 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6741 6742 pci_save_state(pdev); 6743 pci_prepare_to_sleep(pdev); 6744 6745 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6746 } 6747 6748 return 0; 6749 } 6750 6751 /** 6752 * __e1000e_disable_aspm - Disable ASPM states 6753 * @pdev: pointer to PCI device struct 6754 * @state: bit-mask of ASPM states to disable 6755 * @locked: indication if this context holds pci_bus_sem locked. 6756 * 6757 * Some devices *must* have certain ASPM states disabled per hardware errata. 6758 **/ 6759 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6760 { 6761 struct pci_dev *parent = pdev->bus->self; 6762 u16 aspm_dis_mask = 0; 6763 u16 pdev_aspmc, parent_aspmc; 6764 6765 switch (state) { 6766 case PCIE_LINK_STATE_L0S: 6767 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6768 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6769 /* fall-through - can't have L1 without L0s */ 6770 case PCIE_LINK_STATE_L1: 6771 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6772 break; 6773 default: 6774 return; 6775 } 6776 6777 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6778 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6779 6780 if (parent) { 6781 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6782 &parent_aspmc); 6783 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6784 } 6785 6786 /* Nothing to do if the ASPM states to be disabled already are */ 6787 if (!(pdev_aspmc & aspm_dis_mask) && 6788 (!parent || !(parent_aspmc & aspm_dis_mask))) 6789 return; 6790 6791 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6792 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6793 "L0s" : "", 6794 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6795 "L1" : ""); 6796 6797 #ifdef CONFIG_PCIEASPM 6798 if (locked) 6799 pci_disable_link_state_locked(pdev, state); 6800 else 6801 pci_disable_link_state(pdev, state); 6802 6803 /* Double-check ASPM control. If not disabled by the above, the 6804 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6805 * not enabled); override by writing PCI config space directly. 6806 */ 6807 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6808 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6809 6810 if (!(aspm_dis_mask & pdev_aspmc)) 6811 return; 6812 #endif 6813 6814 /* Both device and parent should have the same ASPM setting. 6815 * Disable ASPM in downstream component first and then upstream. 6816 */ 6817 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6818 6819 if (parent) 6820 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6821 aspm_dis_mask); 6822 } 6823 6824 /** 6825 * e1000e_disable_aspm - Disable ASPM states. 6826 * @pdev: pointer to PCI device struct 6827 * @state: bit-mask of ASPM states to disable 6828 * 6829 * This function acquires the pci_bus_sem! 6830 * Some devices *must* have certain ASPM states disabled per hardware errata. 6831 **/ 6832 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6833 { 6834 __e1000e_disable_aspm(pdev, state, 0); 6835 } 6836 6837 /** 6838 * e1000e_disable_aspm_locked Disable ASPM states. 6839 * @pdev: pointer to PCI device struct 6840 * @state: bit-mask of ASPM states to disable 6841 * 6842 * This function must be called with pci_bus_sem acquired! 6843 * Some devices *must* have certain ASPM states disabled per hardware errata. 6844 **/ 6845 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6846 { 6847 __e1000e_disable_aspm(pdev, state, 1); 6848 } 6849 6850 static int e1000e_pm_thaw(struct device *dev) 6851 { 6852 struct net_device *netdev = dev_get_drvdata(dev); 6853 struct e1000_adapter *adapter = netdev_priv(netdev); 6854 int rc = 0; 6855 6856 e1000e_set_interrupt_capability(adapter); 6857 6858 rtnl_lock(); 6859 if (netif_running(netdev)) { 6860 rc = e1000_request_irq(adapter); 6861 if (rc) 6862 goto err_irq; 6863 6864 e1000e_up(adapter); 6865 } 6866 6867 netif_device_attach(netdev); 6868 err_irq: 6869 rtnl_unlock(); 6870 6871 return rc; 6872 } 6873 6874 #ifdef CONFIG_PM 6875 static int __e1000_resume(struct pci_dev *pdev) 6876 { 6877 struct net_device *netdev = pci_get_drvdata(pdev); 6878 struct e1000_adapter *adapter = netdev_priv(netdev); 6879 struct e1000_hw *hw = &adapter->hw; 6880 u16 aspm_disable_flag = 0; 6881 6882 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6883 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6884 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6885 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6886 if (aspm_disable_flag) 6887 e1000e_disable_aspm(pdev, aspm_disable_flag); 6888 6889 pci_set_master(pdev); 6890 6891 if (hw->mac.type >= e1000_pch2lan) 6892 e1000_resume_workarounds_pchlan(&adapter->hw); 6893 6894 e1000e_power_up_phy(adapter); 6895 6896 /* report the system wakeup cause from S3/S4 */ 6897 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6898 u16 phy_data; 6899 6900 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6901 if (phy_data) { 6902 e_info("PHY Wakeup cause - %s\n", 6903 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6904 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6905 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6906 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6907 phy_data & E1000_WUS_LNKC ? 6908 "Link Status Change" : "other"); 6909 } 6910 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6911 } else { 6912 u32 wus = er32(WUS); 6913 6914 if (wus) { 6915 e_info("MAC Wakeup cause - %s\n", 6916 wus & E1000_WUS_EX ? "Unicast Packet" : 6917 wus & E1000_WUS_MC ? "Multicast Packet" : 6918 wus & E1000_WUS_BC ? "Broadcast Packet" : 6919 wus & E1000_WUS_MAG ? "Magic Packet" : 6920 wus & E1000_WUS_LNKC ? "Link Status Change" : 6921 "other"); 6922 } 6923 ew32(WUS, ~0); 6924 } 6925 6926 e1000e_reset(adapter); 6927 6928 e1000_init_manageability_pt(adapter); 6929 6930 /* If the controller has AMT, do not set DRV_LOAD until the interface 6931 * is up. For all other cases, let the f/w know that the h/w is now 6932 * under the control of the driver. 6933 */ 6934 if (!(adapter->flags & FLAG_HAS_AMT)) 6935 e1000e_get_hw_control(adapter); 6936 6937 return 0; 6938 } 6939 6940 #ifdef CONFIG_PM_SLEEP 6941 static int e1000e_pm_suspend(struct device *dev) 6942 { 6943 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6944 struct e1000_adapter *adapter = netdev_priv(netdev); 6945 struct pci_dev *pdev = to_pci_dev(dev); 6946 struct e1000_hw *hw = &adapter->hw; 6947 int rc; 6948 6949 e1000e_flush_lpic(pdev); 6950 6951 e1000e_pm_freeze(dev); 6952 6953 rc = __e1000_shutdown(pdev, false); 6954 if (rc) 6955 e1000e_pm_thaw(dev); 6956 6957 /* Introduce S0ix implementation */ 6958 if (hw->mac.type >= e1000_pch_cnp && 6959 !e1000e_check_me(hw->adapter->pdev->device)) 6960 e1000e_s0ix_entry_flow(adapter); 6961 6962 return rc; 6963 } 6964 6965 static int e1000e_pm_resume(struct device *dev) 6966 { 6967 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6968 struct e1000_adapter *adapter = netdev_priv(netdev); 6969 struct pci_dev *pdev = to_pci_dev(dev); 6970 struct e1000_hw *hw = &adapter->hw; 6971 int rc; 6972 6973 /* Introduce S0ix implementation */ 6974 if (hw->mac.type >= e1000_pch_cnp && 6975 !e1000e_check_me(hw->adapter->pdev->device)) 6976 e1000e_s0ix_exit_flow(adapter); 6977 6978 rc = __e1000_resume(pdev); 6979 if (rc) 6980 return rc; 6981 6982 return e1000e_pm_thaw(dev); 6983 } 6984 #endif /* CONFIG_PM_SLEEP */ 6985 6986 static int e1000e_pm_runtime_idle(struct device *dev) 6987 { 6988 struct net_device *netdev = dev_get_drvdata(dev); 6989 struct e1000_adapter *adapter = netdev_priv(netdev); 6990 u16 eee_lp; 6991 6992 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 6993 6994 if (!e1000e_has_link(adapter)) { 6995 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 6996 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 6997 } 6998 6999 return -EBUSY; 7000 } 7001 7002 static int e1000e_pm_runtime_resume(struct device *dev) 7003 { 7004 struct pci_dev *pdev = to_pci_dev(dev); 7005 struct net_device *netdev = pci_get_drvdata(pdev); 7006 struct e1000_adapter *adapter = netdev_priv(netdev); 7007 int rc; 7008 7009 rc = __e1000_resume(pdev); 7010 if (rc) 7011 return rc; 7012 7013 if (netdev->flags & IFF_UP) 7014 e1000e_up(adapter); 7015 7016 return rc; 7017 } 7018 7019 static int e1000e_pm_runtime_suspend(struct device *dev) 7020 { 7021 struct pci_dev *pdev = to_pci_dev(dev); 7022 struct net_device *netdev = pci_get_drvdata(pdev); 7023 struct e1000_adapter *adapter = netdev_priv(netdev); 7024 7025 if (netdev->flags & IFF_UP) { 7026 int count = E1000_CHECK_RESET_COUNT; 7027 7028 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 7029 usleep_range(10000, 11000); 7030 7031 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 7032 7033 /* Down the device without resetting the hardware */ 7034 e1000e_down(adapter, false); 7035 } 7036 7037 if (__e1000_shutdown(pdev, true)) { 7038 e1000e_pm_runtime_resume(dev); 7039 return -EBUSY; 7040 } 7041 7042 return 0; 7043 } 7044 #endif /* CONFIG_PM */ 7045 7046 static void e1000_shutdown(struct pci_dev *pdev) 7047 { 7048 e1000e_flush_lpic(pdev); 7049 7050 e1000e_pm_freeze(&pdev->dev); 7051 7052 __e1000_shutdown(pdev, false); 7053 } 7054 7055 #ifdef CONFIG_NET_POLL_CONTROLLER 7056 7057 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 7058 { 7059 struct net_device *netdev = data; 7060 struct e1000_adapter *adapter = netdev_priv(netdev); 7061 7062 if (adapter->msix_entries) { 7063 int vector, msix_irq; 7064 7065 vector = 0; 7066 msix_irq = adapter->msix_entries[vector].vector; 7067 if (disable_hardirq(msix_irq)) 7068 e1000_intr_msix_rx(msix_irq, netdev); 7069 enable_irq(msix_irq); 7070 7071 vector++; 7072 msix_irq = adapter->msix_entries[vector].vector; 7073 if (disable_hardirq(msix_irq)) 7074 e1000_intr_msix_tx(msix_irq, netdev); 7075 enable_irq(msix_irq); 7076 7077 vector++; 7078 msix_irq = adapter->msix_entries[vector].vector; 7079 if (disable_hardirq(msix_irq)) 7080 e1000_msix_other(msix_irq, netdev); 7081 enable_irq(msix_irq); 7082 } 7083 7084 return IRQ_HANDLED; 7085 } 7086 7087 /** 7088 * e1000_netpoll 7089 * @netdev: network interface device structure 7090 * 7091 * Polling 'interrupt' - used by things like netconsole to send skbs 7092 * without having to re-enable interrupts. It's not called while 7093 * the interrupt routine is executing. 7094 */ 7095 static void e1000_netpoll(struct net_device *netdev) 7096 { 7097 struct e1000_adapter *adapter = netdev_priv(netdev); 7098 7099 switch (adapter->int_mode) { 7100 case E1000E_INT_MODE_MSIX: 7101 e1000_intr_msix(adapter->pdev->irq, netdev); 7102 break; 7103 case E1000E_INT_MODE_MSI: 7104 if (disable_hardirq(adapter->pdev->irq)) 7105 e1000_intr_msi(adapter->pdev->irq, netdev); 7106 enable_irq(adapter->pdev->irq); 7107 break; 7108 default: /* E1000E_INT_MODE_LEGACY */ 7109 if (disable_hardirq(adapter->pdev->irq)) 7110 e1000_intr(adapter->pdev->irq, netdev); 7111 enable_irq(adapter->pdev->irq); 7112 break; 7113 } 7114 } 7115 #endif 7116 7117 /** 7118 * e1000_io_error_detected - called when PCI error is detected 7119 * @pdev: Pointer to PCI device 7120 * @state: The current pci connection state 7121 * 7122 * This function is called after a PCI bus error affecting 7123 * this device has been detected. 7124 */ 7125 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7126 pci_channel_state_t state) 7127 { 7128 e1000e_pm_freeze(&pdev->dev); 7129 7130 if (state == pci_channel_io_perm_failure) 7131 return PCI_ERS_RESULT_DISCONNECT; 7132 7133 pci_disable_device(pdev); 7134 7135 /* Request a slot slot reset. */ 7136 return PCI_ERS_RESULT_NEED_RESET; 7137 } 7138 7139 /** 7140 * e1000_io_slot_reset - called after the pci bus has been reset. 7141 * @pdev: Pointer to PCI device 7142 * 7143 * Restart the card from scratch, as if from a cold-boot. Implementation 7144 * resembles the first-half of the e1000e_pm_resume routine. 7145 */ 7146 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7147 { 7148 struct net_device *netdev = pci_get_drvdata(pdev); 7149 struct e1000_adapter *adapter = netdev_priv(netdev); 7150 struct e1000_hw *hw = &adapter->hw; 7151 u16 aspm_disable_flag = 0; 7152 int err; 7153 pci_ers_result_t result; 7154 7155 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7156 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7157 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7158 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7159 if (aspm_disable_flag) 7160 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7161 7162 err = pci_enable_device_mem(pdev); 7163 if (err) { 7164 dev_err(&pdev->dev, 7165 "Cannot re-enable PCI device after reset.\n"); 7166 result = PCI_ERS_RESULT_DISCONNECT; 7167 } else { 7168 pdev->state_saved = true; 7169 pci_restore_state(pdev); 7170 pci_set_master(pdev); 7171 7172 pci_enable_wake(pdev, PCI_D3hot, 0); 7173 pci_enable_wake(pdev, PCI_D3cold, 0); 7174 7175 e1000e_reset(adapter); 7176 ew32(WUS, ~0); 7177 result = PCI_ERS_RESULT_RECOVERED; 7178 } 7179 7180 return result; 7181 } 7182 7183 /** 7184 * e1000_io_resume - called when traffic can start flowing again. 7185 * @pdev: Pointer to PCI device 7186 * 7187 * This callback is called when the error recovery driver tells us that 7188 * its OK to resume normal operation. Implementation resembles the 7189 * second-half of the e1000e_pm_resume routine. 7190 */ 7191 static void e1000_io_resume(struct pci_dev *pdev) 7192 { 7193 struct net_device *netdev = pci_get_drvdata(pdev); 7194 struct e1000_adapter *adapter = netdev_priv(netdev); 7195 7196 e1000_init_manageability_pt(adapter); 7197 7198 e1000e_pm_thaw(&pdev->dev); 7199 7200 /* If the controller has AMT, do not set DRV_LOAD until the interface 7201 * is up. For all other cases, let the f/w know that the h/w is now 7202 * under the control of the driver. 7203 */ 7204 if (!(adapter->flags & FLAG_HAS_AMT)) 7205 e1000e_get_hw_control(adapter); 7206 } 7207 7208 static void e1000_print_device_info(struct e1000_adapter *adapter) 7209 { 7210 struct e1000_hw *hw = &adapter->hw; 7211 struct net_device *netdev = adapter->netdev; 7212 u32 ret_val; 7213 u8 pba_str[E1000_PBANUM_LENGTH]; 7214 7215 /* print bus type/speed/width info */ 7216 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7217 /* bus width */ 7218 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7219 "Width x1"), 7220 /* MAC address */ 7221 netdev->dev_addr); 7222 e_info("Intel(R) PRO/%s Network Connection\n", 7223 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7224 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7225 E1000_PBANUM_LENGTH); 7226 if (ret_val) 7227 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7228 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7229 hw->mac.type, hw->phy.type, pba_str); 7230 } 7231 7232 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7233 { 7234 struct e1000_hw *hw = &adapter->hw; 7235 int ret_val; 7236 u16 buf = 0; 7237 7238 if (hw->mac.type != e1000_82573) 7239 return; 7240 7241 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7242 le16_to_cpus(&buf); 7243 if (!ret_val && (!(buf & BIT(0)))) { 7244 /* Deep Smart Power Down (DSPD) */ 7245 dev_warn(&adapter->pdev->dev, 7246 "Warning: detected DSPD enabled in EEPROM\n"); 7247 } 7248 } 7249 7250 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7251 netdev_features_t features) 7252 { 7253 struct e1000_adapter *adapter = netdev_priv(netdev); 7254 struct e1000_hw *hw = &adapter->hw; 7255 7256 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7257 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7258 features &= ~NETIF_F_RXFCS; 7259 7260 /* Since there is no support for separate Rx/Tx vlan accel 7261 * enable/disable make sure Tx flag is always in same state as Rx. 7262 */ 7263 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7264 features |= NETIF_F_HW_VLAN_CTAG_TX; 7265 else 7266 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7267 7268 return features; 7269 } 7270 7271 static int e1000_set_features(struct net_device *netdev, 7272 netdev_features_t features) 7273 { 7274 struct e1000_adapter *adapter = netdev_priv(netdev); 7275 netdev_features_t changed = features ^ netdev->features; 7276 7277 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7278 adapter->flags |= FLAG_TSO_FORCE; 7279 7280 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7281 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7282 NETIF_F_RXALL))) 7283 return 0; 7284 7285 if (changed & NETIF_F_RXFCS) { 7286 if (features & NETIF_F_RXFCS) { 7287 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7288 } else { 7289 /* We need to take it back to defaults, which might mean 7290 * stripping is still disabled at the adapter level. 7291 */ 7292 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7293 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7294 else 7295 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7296 } 7297 } 7298 7299 netdev->features = features; 7300 7301 if (netif_running(netdev)) 7302 e1000e_reinit_locked(adapter); 7303 else 7304 e1000e_reset(adapter); 7305 7306 return 1; 7307 } 7308 7309 static const struct net_device_ops e1000e_netdev_ops = { 7310 .ndo_open = e1000e_open, 7311 .ndo_stop = e1000e_close, 7312 .ndo_start_xmit = e1000_xmit_frame, 7313 .ndo_get_stats64 = e1000e_get_stats64, 7314 .ndo_set_rx_mode = e1000e_set_rx_mode, 7315 .ndo_set_mac_address = e1000_set_mac, 7316 .ndo_change_mtu = e1000_change_mtu, 7317 .ndo_do_ioctl = e1000_ioctl, 7318 .ndo_tx_timeout = e1000_tx_timeout, 7319 .ndo_validate_addr = eth_validate_addr, 7320 7321 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7322 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7323 #ifdef CONFIG_NET_POLL_CONTROLLER 7324 .ndo_poll_controller = e1000_netpoll, 7325 #endif 7326 .ndo_set_features = e1000_set_features, 7327 .ndo_fix_features = e1000_fix_features, 7328 .ndo_features_check = passthru_features_check, 7329 }; 7330 7331 /** 7332 * e1000_probe - Device Initialization Routine 7333 * @pdev: PCI device information struct 7334 * @ent: entry in e1000_pci_tbl 7335 * 7336 * Returns 0 on success, negative on failure 7337 * 7338 * e1000_probe initializes an adapter identified by a pci_dev structure. 7339 * The OS initialization, configuring of the adapter private structure, 7340 * and a hardware reset occur. 7341 **/ 7342 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7343 { 7344 struct net_device *netdev; 7345 struct e1000_adapter *adapter; 7346 struct e1000_hw *hw; 7347 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7348 resource_size_t mmio_start, mmio_len; 7349 resource_size_t flash_start, flash_len; 7350 static int cards_found; 7351 u16 aspm_disable_flag = 0; 7352 int bars, i, err, pci_using_dac; 7353 u16 eeprom_data = 0; 7354 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7355 s32 ret_val = 0; 7356 7357 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7358 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7359 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7360 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7361 if (aspm_disable_flag) 7362 e1000e_disable_aspm(pdev, aspm_disable_flag); 7363 7364 err = pci_enable_device_mem(pdev); 7365 if (err) 7366 return err; 7367 7368 pci_using_dac = 0; 7369 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7370 if (!err) { 7371 pci_using_dac = 1; 7372 } else { 7373 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 7374 if (err) { 7375 dev_err(&pdev->dev, 7376 "No usable DMA configuration, aborting\n"); 7377 goto err_dma; 7378 } 7379 } 7380 7381 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7382 err = pci_request_selected_regions_exclusive(pdev, bars, 7383 e1000e_driver_name); 7384 if (err) 7385 goto err_pci_reg; 7386 7387 /* AER (Advanced Error Reporting) hooks */ 7388 pci_enable_pcie_error_reporting(pdev); 7389 7390 pci_set_master(pdev); 7391 /* PCI config space info */ 7392 err = pci_save_state(pdev); 7393 if (err) 7394 goto err_alloc_etherdev; 7395 7396 err = -ENOMEM; 7397 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7398 if (!netdev) 7399 goto err_alloc_etherdev; 7400 7401 SET_NETDEV_DEV(netdev, &pdev->dev); 7402 7403 netdev->irq = pdev->irq; 7404 7405 pci_set_drvdata(pdev, netdev); 7406 adapter = netdev_priv(netdev); 7407 hw = &adapter->hw; 7408 adapter->netdev = netdev; 7409 adapter->pdev = pdev; 7410 adapter->ei = ei; 7411 adapter->pba = ei->pba; 7412 adapter->flags = ei->flags; 7413 adapter->flags2 = ei->flags2; 7414 adapter->hw.adapter = adapter; 7415 adapter->hw.mac.type = ei->mac; 7416 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7417 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7418 7419 mmio_start = pci_resource_start(pdev, 0); 7420 mmio_len = pci_resource_len(pdev, 0); 7421 7422 err = -EIO; 7423 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7424 if (!adapter->hw.hw_addr) 7425 goto err_ioremap; 7426 7427 if ((adapter->flags & FLAG_HAS_FLASH) && 7428 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7429 (hw->mac.type < e1000_pch_spt)) { 7430 flash_start = pci_resource_start(pdev, 1); 7431 flash_len = pci_resource_len(pdev, 1); 7432 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7433 if (!adapter->hw.flash_address) 7434 goto err_flashmap; 7435 } 7436 7437 /* Set default EEE advertisement */ 7438 if (adapter->flags2 & FLAG2_HAS_EEE) 7439 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7440 7441 /* construct the net_device struct */ 7442 netdev->netdev_ops = &e1000e_netdev_ops; 7443 e1000e_set_ethtool_ops(netdev); 7444 netdev->watchdog_timeo = 5 * HZ; 7445 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 7446 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7447 7448 netdev->mem_start = mmio_start; 7449 netdev->mem_end = mmio_start + mmio_len; 7450 7451 adapter->bd_number = cards_found++; 7452 7453 e1000e_check_options(adapter); 7454 7455 /* setup adapter struct */ 7456 err = e1000_sw_init(adapter); 7457 if (err) 7458 goto err_sw_init; 7459 7460 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7461 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7462 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7463 7464 err = ei->get_variants(adapter); 7465 if (err) 7466 goto err_hw_init; 7467 7468 if ((adapter->flags & FLAG_IS_ICH) && 7469 (adapter->flags & FLAG_READ_ONLY_NVM) && 7470 (hw->mac.type < e1000_pch_spt)) 7471 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7472 7473 hw->mac.ops.get_bus_info(&adapter->hw); 7474 7475 adapter->hw.phy.autoneg_wait_to_complete = 0; 7476 7477 /* Copper options */ 7478 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7479 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7480 adapter->hw.phy.disable_polarity_correction = 0; 7481 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7482 } 7483 7484 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7485 dev_info(&pdev->dev, 7486 "PHY reset is blocked due to SOL/IDER session.\n"); 7487 7488 /* Set initial default active device features */ 7489 netdev->features = (NETIF_F_SG | 7490 NETIF_F_HW_VLAN_CTAG_RX | 7491 NETIF_F_HW_VLAN_CTAG_TX | 7492 NETIF_F_TSO | 7493 NETIF_F_TSO6 | 7494 NETIF_F_RXHASH | 7495 NETIF_F_RXCSUM | 7496 NETIF_F_HW_CSUM); 7497 7498 /* Set user-changeable features (subset of all device features) */ 7499 netdev->hw_features = netdev->features; 7500 netdev->hw_features |= NETIF_F_RXFCS; 7501 netdev->priv_flags |= IFF_SUPP_NOFCS; 7502 netdev->hw_features |= NETIF_F_RXALL; 7503 7504 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7505 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7506 7507 netdev->vlan_features |= (NETIF_F_SG | 7508 NETIF_F_TSO | 7509 NETIF_F_TSO6 | 7510 NETIF_F_HW_CSUM); 7511 7512 netdev->priv_flags |= IFF_UNICAST_FLT; 7513 7514 if (pci_using_dac) { 7515 netdev->features |= NETIF_F_HIGHDMA; 7516 netdev->vlan_features |= NETIF_F_HIGHDMA; 7517 } 7518 7519 /* MTU range: 68 - max_hw_frame_size */ 7520 netdev->min_mtu = ETH_MIN_MTU; 7521 netdev->max_mtu = adapter->max_hw_frame_size - 7522 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7523 7524 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7525 adapter->flags |= FLAG_MNG_PT_ENABLED; 7526 7527 /* before reading the NVM, reset the controller to 7528 * put the device in a known good starting state 7529 */ 7530 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7531 7532 /* systems with ASPM and others may see the checksum fail on the first 7533 * attempt. Let's give it a few tries 7534 */ 7535 for (i = 0;; i++) { 7536 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7537 break; 7538 if (i == 2) { 7539 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7540 err = -EIO; 7541 goto err_eeprom; 7542 } 7543 } 7544 7545 e1000_eeprom_checks(adapter); 7546 7547 /* copy the MAC address */ 7548 if (e1000e_read_mac_addr(&adapter->hw)) 7549 dev_err(&pdev->dev, 7550 "NVM Read Error while reading MAC address\n"); 7551 7552 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 7553 7554 if (!is_valid_ether_addr(netdev->dev_addr)) { 7555 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7556 netdev->dev_addr); 7557 err = -EIO; 7558 goto err_eeprom; 7559 } 7560 7561 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7562 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7563 7564 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7565 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7566 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7567 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7568 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7569 7570 /* Initialize link parameters. User can change them with ethtool */ 7571 adapter->hw.mac.autoneg = 1; 7572 adapter->fc_autoneg = true; 7573 adapter->hw.fc.requested_mode = e1000_fc_default; 7574 adapter->hw.fc.current_mode = e1000_fc_default; 7575 adapter->hw.phy.autoneg_advertised = 0x2f; 7576 7577 /* Initial Wake on LAN setting - If APM wake is enabled in 7578 * the EEPROM, enable the ACPI Magic Packet filter 7579 */ 7580 if (adapter->flags & FLAG_APME_IN_WUC) { 7581 /* APME bit in EEPROM is mapped to WUC.APME */ 7582 eeprom_data = er32(WUC); 7583 eeprom_apme_mask = E1000_WUC_APME; 7584 if ((hw->mac.type > e1000_ich10lan) && 7585 (eeprom_data & E1000_WUC_PHY_WAKE)) 7586 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7587 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7588 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7589 (adapter->hw.bus.func == 1)) 7590 ret_val = e1000_read_nvm(&adapter->hw, 7591 NVM_INIT_CONTROL3_PORT_B, 7592 1, &eeprom_data); 7593 else 7594 ret_val = e1000_read_nvm(&adapter->hw, 7595 NVM_INIT_CONTROL3_PORT_A, 7596 1, &eeprom_data); 7597 } 7598 7599 /* fetch WoL from EEPROM */ 7600 if (ret_val) 7601 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7602 else if (eeprom_data & eeprom_apme_mask) 7603 adapter->eeprom_wol |= E1000_WUFC_MAG; 7604 7605 /* now that we have the eeprom settings, apply the special cases 7606 * where the eeprom may be wrong or the board simply won't support 7607 * wake on lan on a particular port 7608 */ 7609 if (!(adapter->flags & FLAG_HAS_WOL)) 7610 adapter->eeprom_wol = 0; 7611 7612 /* initialize the wol settings based on the eeprom settings */ 7613 adapter->wol = adapter->eeprom_wol; 7614 7615 /* make sure adapter isn't asleep if manageability is enabled */ 7616 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7617 (hw->mac.ops.check_mng_mode(hw))) 7618 device_wakeup_enable(&pdev->dev); 7619 7620 /* save off EEPROM version number */ 7621 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7622 7623 if (ret_val) { 7624 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7625 adapter->eeprom_vers = 0; 7626 } 7627 7628 /* init PTP hardware clock */ 7629 e1000e_ptp_init(adapter); 7630 7631 /* reset the hardware with the new settings */ 7632 e1000e_reset(adapter); 7633 7634 /* If the controller has AMT, do not set DRV_LOAD until the interface 7635 * is up. For all other cases, let the f/w know that the h/w is now 7636 * under the control of the driver. 7637 */ 7638 if (!(adapter->flags & FLAG_HAS_AMT)) 7639 e1000e_get_hw_control(adapter); 7640 7641 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7642 err = register_netdev(netdev); 7643 if (err) 7644 goto err_register; 7645 7646 /* carrier off reporting is important to ethtool even BEFORE open */ 7647 netif_carrier_off(netdev); 7648 7649 e1000_print_device_info(adapter); 7650 7651 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); 7652 7653 if (pci_dev_run_wake(pdev) && hw->mac.type < e1000_pch_cnp) 7654 pm_runtime_put_noidle(&pdev->dev); 7655 7656 return 0; 7657 7658 err_register: 7659 if (!(adapter->flags & FLAG_HAS_AMT)) 7660 e1000e_release_hw_control(adapter); 7661 err_eeprom: 7662 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7663 e1000_phy_hw_reset(&adapter->hw); 7664 err_hw_init: 7665 kfree(adapter->tx_ring); 7666 kfree(adapter->rx_ring); 7667 err_sw_init: 7668 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7669 iounmap(adapter->hw.flash_address); 7670 e1000e_reset_interrupt_capability(adapter); 7671 err_flashmap: 7672 iounmap(adapter->hw.hw_addr); 7673 err_ioremap: 7674 free_netdev(netdev); 7675 err_alloc_etherdev: 7676 pci_release_mem_regions(pdev); 7677 err_pci_reg: 7678 err_dma: 7679 pci_disable_device(pdev); 7680 return err; 7681 } 7682 7683 /** 7684 * e1000_remove - Device Removal Routine 7685 * @pdev: PCI device information struct 7686 * 7687 * e1000_remove is called by the PCI subsystem to alert the driver 7688 * that it should release a PCI device. The could be caused by a 7689 * Hot-Plug event, or because the driver is going to be removed from 7690 * memory. 7691 **/ 7692 static void e1000_remove(struct pci_dev *pdev) 7693 { 7694 struct net_device *netdev = pci_get_drvdata(pdev); 7695 struct e1000_adapter *adapter = netdev_priv(netdev); 7696 7697 e1000e_ptp_remove(adapter); 7698 7699 /* The timers may be rescheduled, so explicitly disable them 7700 * from being rescheduled. 7701 */ 7702 set_bit(__E1000_DOWN, &adapter->state); 7703 del_timer_sync(&adapter->watchdog_timer); 7704 del_timer_sync(&adapter->phy_info_timer); 7705 7706 cancel_work_sync(&adapter->reset_task); 7707 cancel_work_sync(&adapter->watchdog_task); 7708 cancel_work_sync(&adapter->downshift_task); 7709 cancel_work_sync(&adapter->update_phy_task); 7710 cancel_work_sync(&adapter->print_hang_task); 7711 7712 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7713 cancel_work_sync(&adapter->tx_hwtstamp_work); 7714 if (adapter->tx_hwtstamp_skb) { 7715 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7716 adapter->tx_hwtstamp_skb = NULL; 7717 } 7718 } 7719 7720 unregister_netdev(netdev); 7721 7722 if (pci_dev_run_wake(pdev)) 7723 pm_runtime_get_noresume(&pdev->dev); 7724 7725 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7726 * would have already happened in close and is redundant. 7727 */ 7728 e1000e_release_hw_control(adapter); 7729 7730 e1000e_reset_interrupt_capability(adapter); 7731 kfree(adapter->tx_ring); 7732 kfree(adapter->rx_ring); 7733 7734 iounmap(adapter->hw.hw_addr); 7735 if ((adapter->hw.flash_address) && 7736 (adapter->hw.mac.type < e1000_pch_spt)) 7737 iounmap(adapter->hw.flash_address); 7738 pci_release_mem_regions(pdev); 7739 7740 free_netdev(netdev); 7741 7742 /* AER disable */ 7743 pci_disable_pcie_error_reporting(pdev); 7744 7745 pci_disable_device(pdev); 7746 } 7747 7748 /* PCI Error Recovery (ERS) */ 7749 static const struct pci_error_handlers e1000_err_handler = { 7750 .error_detected = e1000_io_error_detected, 7751 .slot_reset = e1000_io_slot_reset, 7752 .resume = e1000_io_resume, 7753 }; 7754 7755 static const struct pci_device_id e1000_pci_tbl[] = { 7756 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7757 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7758 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7759 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7760 board_82571 }, 7761 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7762 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7763 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7764 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7765 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7766 7767 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7768 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7769 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7770 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7771 7772 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7773 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7774 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7775 7776 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7777 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7778 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7779 7780 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7781 board_80003es2lan }, 7782 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7783 board_80003es2lan }, 7784 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7785 board_80003es2lan }, 7786 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7787 board_80003es2lan }, 7788 7789 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7790 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7791 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7792 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7793 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7794 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7796 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7797 7798 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7799 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7807 7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7811 7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7813 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7815 7816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7820 7821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7823 7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp }, 7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp }, 7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp }, 7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, 7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, 7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, 7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_cnp }, 7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_cnp }, 7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_cnp }, 7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp }, 7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp }, 7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_cnp }, 7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_cnp }, 7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_cnp }, 7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_cnp }, 7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_cnp }, 7865 7866 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7867 }; 7868 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7869 7870 static const struct dev_pm_ops e1000_pm_ops = { 7871 #ifdef CONFIG_PM_SLEEP 7872 .suspend = e1000e_pm_suspend, 7873 .resume = e1000e_pm_resume, 7874 .freeze = e1000e_pm_freeze, 7875 .thaw = e1000e_pm_thaw, 7876 .poweroff = e1000e_pm_suspend, 7877 .restore = e1000e_pm_resume, 7878 #endif 7879 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7880 e1000e_pm_runtime_idle) 7881 }; 7882 7883 /* PCI Device API Driver */ 7884 static struct pci_driver e1000_driver = { 7885 .name = e1000e_driver_name, 7886 .id_table = e1000_pci_tbl, 7887 .probe = e1000_probe, 7888 .remove = e1000_remove, 7889 .driver = { 7890 .pm = &e1000_pm_ops, 7891 }, 7892 .shutdown = e1000_shutdown, 7893 .err_handler = &e1000_err_handler 7894 }; 7895 7896 /** 7897 * e1000_init_module - Driver Registration Routine 7898 * 7899 * e1000_init_module is the first routine called when the driver is 7900 * loaded. All it does is register with the PCI subsystem. 7901 **/ 7902 static int __init e1000_init_module(void) 7903 { 7904 pr_info("Intel(R) PRO/1000 Network Driver - %s\n", 7905 e1000e_driver_version); 7906 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7907 7908 return pci_register_driver(&e1000_driver); 7909 } 7910 module_init(e1000_init_module); 7911 7912 /** 7913 * e1000_exit_module - Driver Exit Cleanup Routine 7914 * 7915 * e1000_exit_module is called just before the driver is removed 7916 * from memory. 7917 **/ 7918 static void __exit e1000_exit_module(void) 7919 { 7920 pci_unregister_driver(&e1000_driver); 7921 } 7922 module_exit(e1000_exit_module); 7923 7924 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7925 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7926 MODULE_LICENSE("GPL v2"); 7927 MODULE_VERSION(DRV_VERSION); 7928 7929 /* netdev.c */ 7930