1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/prefetch.h> 27 #include <linux/suspend.h> 28 29 #include "e1000.h" 30 #define CREATE_TRACE_POINTS 31 #include "e1000e_trace.h" 32 33 char e1000e_driver_name[] = "e1000e"; 34 35 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 36 static int debug = -1; 37 module_param(debug, int, 0); 38 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 39 40 static const struct e1000_info *e1000_info_tbl[] = { 41 [board_82571] = &e1000_82571_info, 42 [board_82572] = &e1000_82572_info, 43 [board_82573] = &e1000_82573_info, 44 [board_82574] = &e1000_82574_info, 45 [board_82583] = &e1000_82583_info, 46 [board_80003es2lan] = &e1000_es2_info, 47 [board_ich8lan] = &e1000_ich8_info, 48 [board_ich9lan] = &e1000_ich9_info, 49 [board_ich10lan] = &e1000_ich10_info, 50 [board_pchlan] = &e1000_pch_info, 51 [board_pch2lan] = &e1000_pch2_info, 52 [board_pch_lpt] = &e1000_pch_lpt_info, 53 [board_pch_spt] = &e1000_pch_spt_info, 54 [board_pch_cnp] = &e1000_pch_cnp_info, 55 [board_pch_tgp] = &e1000_pch_tgp_info, 56 [board_pch_adp] = &e1000_pch_adp_info, 57 [board_pch_mtp] = &e1000_pch_mtp_info, 58 }; 59 60 struct e1000_reg_info { 61 u32 ofs; 62 char *name; 63 }; 64 65 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 66 /* General Registers */ 67 {E1000_CTRL, "CTRL"}, 68 {E1000_STATUS, "STATUS"}, 69 {E1000_CTRL_EXT, "CTRL_EXT"}, 70 71 /* Interrupt Registers */ 72 {E1000_ICR, "ICR"}, 73 74 /* Rx Registers */ 75 {E1000_RCTL, "RCTL"}, 76 {E1000_RDLEN(0), "RDLEN"}, 77 {E1000_RDH(0), "RDH"}, 78 {E1000_RDT(0), "RDT"}, 79 {E1000_RDTR, "RDTR"}, 80 {E1000_RXDCTL(0), "RXDCTL"}, 81 {E1000_ERT, "ERT"}, 82 {E1000_RDBAL(0), "RDBAL"}, 83 {E1000_RDBAH(0), "RDBAH"}, 84 {E1000_RDFH, "RDFH"}, 85 {E1000_RDFT, "RDFT"}, 86 {E1000_RDFHS, "RDFHS"}, 87 {E1000_RDFTS, "RDFTS"}, 88 {E1000_RDFPC, "RDFPC"}, 89 90 /* Tx Registers */ 91 {E1000_TCTL, "TCTL"}, 92 {E1000_TDBAL(0), "TDBAL"}, 93 {E1000_TDBAH(0), "TDBAH"}, 94 {E1000_TDLEN(0), "TDLEN"}, 95 {E1000_TDH(0), "TDH"}, 96 {E1000_TDT(0), "TDT"}, 97 {E1000_TIDV, "TIDV"}, 98 {E1000_TXDCTL(0), "TXDCTL"}, 99 {E1000_TADV, "TADV"}, 100 {E1000_TARC(0), "TARC"}, 101 {E1000_TDFH, "TDFH"}, 102 {E1000_TDFT, "TDFT"}, 103 {E1000_TDFHS, "TDFHS"}, 104 {E1000_TDFTS, "TDFTS"}, 105 {E1000_TDFPC, "TDFPC"}, 106 107 /* List Terminator */ 108 {0, NULL} 109 }; 110 111 /** 112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 113 * @hw: pointer to the HW structure 114 * 115 * When updating the MAC CSR registers, the Manageability Engine (ME) could 116 * be accessing the registers at the same time. Normally, this is handled in 117 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 118 * accesses later than it should which could result in the register to have 119 * an incorrect value. Workaround this by checking the FWSM register which 120 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 121 * and try again a number of times. 122 **/ 123 static void __ew32_prepare(struct e1000_hw *hw) 124 { 125 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 126 127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 128 udelay(50); 129 } 130 131 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 132 { 133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 134 __ew32_prepare(hw); 135 136 writel(val, hw->hw_addr + reg); 137 } 138 139 /** 140 * e1000_regdump - register printout routine 141 * @hw: pointer to the HW structure 142 * @reginfo: pointer to the register info table 143 **/ 144 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 145 { 146 int n = 0; 147 char rname[16]; 148 u32 regs[8]; 149 150 switch (reginfo->ofs) { 151 case E1000_RXDCTL(0): 152 for (n = 0; n < 2; n++) 153 regs[n] = __er32(hw, E1000_RXDCTL(n)); 154 break; 155 case E1000_TXDCTL(0): 156 for (n = 0; n < 2; n++) 157 regs[n] = __er32(hw, E1000_TXDCTL(n)); 158 break; 159 case E1000_TARC(0): 160 for (n = 0; n < 2; n++) 161 regs[n] = __er32(hw, E1000_TARC(n)); 162 break; 163 default: 164 pr_info("%-15s %08x\n", 165 reginfo->name, __er32(hw, reginfo->ofs)); 166 return; 167 } 168 169 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 170 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 171 } 172 173 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 174 struct e1000_buffer *bi) 175 { 176 int i; 177 struct e1000_ps_page *ps_page; 178 179 for (i = 0; i < adapter->rx_ps_pages; i++) { 180 ps_page = &bi->ps_pages[i]; 181 182 if (ps_page->page) { 183 pr_info("packet dump for ps_page %d:\n", i); 184 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 185 16, 1, page_address(ps_page->page), 186 PAGE_SIZE, true); 187 } 188 } 189 } 190 191 /** 192 * e1000e_dump - Print registers, Tx-ring and Rx-ring 193 * @adapter: board private structure 194 **/ 195 static void e1000e_dump(struct e1000_adapter *adapter) 196 { 197 struct net_device *netdev = adapter->netdev; 198 struct e1000_hw *hw = &adapter->hw; 199 struct e1000_reg_info *reginfo; 200 struct e1000_ring *tx_ring = adapter->tx_ring; 201 struct e1000_tx_desc *tx_desc; 202 struct my_u0 { 203 __le64 a; 204 __le64 b; 205 } *u0; 206 struct e1000_buffer *buffer_info; 207 struct e1000_ring *rx_ring = adapter->rx_ring; 208 union e1000_rx_desc_packet_split *rx_desc_ps; 209 union e1000_rx_desc_extended *rx_desc; 210 struct my_u1 { 211 __le64 a; 212 __le64 b; 213 __le64 c; 214 __le64 d; 215 } *u1; 216 u32 staterr; 217 int i = 0; 218 219 if (!netif_msg_hw(adapter)) 220 return; 221 222 /* Print netdevice Info */ 223 if (netdev) { 224 dev_info(&adapter->pdev->dev, "Net device Info\n"); 225 pr_info("Device Name state trans_start\n"); 226 pr_info("%-15s %016lX %016lX\n", netdev->name, 227 netdev->state, dev_trans_start(netdev)); 228 } 229 230 /* Print Registers */ 231 dev_info(&adapter->pdev->dev, "Register Dump\n"); 232 pr_info(" Register Name Value\n"); 233 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 234 reginfo->name; reginfo++) { 235 e1000_regdump(hw, reginfo); 236 } 237 238 /* Print Tx Ring Summary */ 239 if (!netdev || !netif_running(netdev)) 240 return; 241 242 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 243 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 244 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 245 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 246 0, tx_ring->next_to_use, tx_ring->next_to_clean, 247 (unsigned long long)buffer_info->dma, 248 buffer_info->length, 249 buffer_info->next_to_watch, 250 (unsigned long long)buffer_info->time_stamp); 251 252 /* Print Tx Ring */ 253 if (!netif_msg_tx_done(adapter)) 254 goto rx_ring_summary; 255 256 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 257 258 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 259 * 260 * Legacy Transmit Descriptor 261 * +--------------------------------------------------------------+ 262 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 263 * +--------------------------------------------------------------+ 264 * 8 | Special | CSS | Status | CMD | CSO | Length | 265 * +--------------------------------------------------------------+ 266 * 63 48 47 36 35 32 31 24 23 16 15 0 267 * 268 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 269 * 63 48 47 40 39 32 31 16 15 8 7 0 270 * +----------------------------------------------------------------+ 271 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 272 * +----------------------------------------------------------------+ 273 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 274 * +----------------------------------------------------------------+ 275 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 276 * 277 * Extended Data Descriptor (DTYP=0x1) 278 * +----------------------------------------------------------------+ 279 * 0 | Buffer Address [63:0] | 280 * +----------------------------------------------------------------+ 281 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 282 * +----------------------------------------------------------------+ 283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 284 */ 285 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 286 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 287 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 288 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 289 const char *next_desc; 290 tx_desc = E1000_TX_DESC(*tx_ring, i); 291 buffer_info = &tx_ring->buffer_info[i]; 292 u0 = (struct my_u0 *)tx_desc; 293 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 294 next_desc = " NTC/U"; 295 else if (i == tx_ring->next_to_use) 296 next_desc = " NTU"; 297 else if (i == tx_ring->next_to_clean) 298 next_desc = " NTC"; 299 else 300 next_desc = ""; 301 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 302 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 303 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 304 i, 305 (unsigned long long)le64_to_cpu(u0->a), 306 (unsigned long long)le64_to_cpu(u0->b), 307 (unsigned long long)buffer_info->dma, 308 buffer_info->length, buffer_info->next_to_watch, 309 (unsigned long long)buffer_info->time_stamp, 310 buffer_info->skb, next_desc); 311 312 if (netif_msg_pktdata(adapter) && buffer_info->skb) 313 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 314 16, 1, buffer_info->skb->data, 315 buffer_info->skb->len, true); 316 } 317 318 /* Print Rx Ring Summary */ 319 rx_ring_summary: 320 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 321 pr_info("Queue [NTU] [NTC]\n"); 322 pr_info(" %5d %5X %5X\n", 323 0, rx_ring->next_to_use, rx_ring->next_to_clean); 324 325 /* Print Rx Ring */ 326 if (!netif_msg_rx_status(adapter)) 327 return; 328 329 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 330 switch (adapter->rx_ps_pages) { 331 case 1: 332 case 2: 333 case 3: 334 /* [Extended] Packet Split Receive Descriptor Format 335 * 336 * +-----------------------------------------------------+ 337 * 0 | Buffer Address 0 [63:0] | 338 * +-----------------------------------------------------+ 339 * 8 | Buffer Address 1 [63:0] | 340 * +-----------------------------------------------------+ 341 * 16 | Buffer Address 2 [63:0] | 342 * +-----------------------------------------------------+ 343 * 24 | Buffer Address 3 [63:0] | 344 * +-----------------------------------------------------+ 345 */ 346 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 347 /* [Extended] Receive Descriptor (Write-Back) Format 348 * 349 * 63 48 47 32 31 13 12 8 7 4 3 0 350 * +------------------------------------------------------+ 351 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 352 * | Checksum | Ident | | Queue | | Type | 353 * +------------------------------------------------------+ 354 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 355 * +------------------------------------------------------+ 356 * 63 48 47 32 31 20 19 0 357 */ 358 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 359 for (i = 0; i < rx_ring->count; i++) { 360 const char *next_desc; 361 buffer_info = &rx_ring->buffer_info[i]; 362 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 363 u1 = (struct my_u1 *)rx_desc_ps; 364 staterr = 365 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 366 367 if (i == rx_ring->next_to_use) 368 next_desc = " NTU"; 369 else if (i == rx_ring->next_to_clean) 370 next_desc = " NTC"; 371 else 372 next_desc = ""; 373 374 if (staterr & E1000_RXD_STAT_DD) { 375 /* Descriptor Done */ 376 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 377 "RWB", i, 378 (unsigned long long)le64_to_cpu(u1->a), 379 (unsigned long long)le64_to_cpu(u1->b), 380 (unsigned long long)le64_to_cpu(u1->c), 381 (unsigned long long)le64_to_cpu(u1->d), 382 buffer_info->skb, next_desc); 383 } else { 384 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 385 "R ", i, 386 (unsigned long long)le64_to_cpu(u1->a), 387 (unsigned long long)le64_to_cpu(u1->b), 388 (unsigned long long)le64_to_cpu(u1->c), 389 (unsigned long long)le64_to_cpu(u1->d), 390 (unsigned long long)buffer_info->dma, 391 buffer_info->skb, next_desc); 392 393 if (netif_msg_pktdata(adapter)) 394 e1000e_dump_ps_pages(adapter, 395 buffer_info); 396 } 397 } 398 break; 399 default: 400 case 0: 401 /* Extended Receive Descriptor (Read) Format 402 * 403 * +-----------------------------------------------------+ 404 * 0 | Buffer Address [63:0] | 405 * +-----------------------------------------------------+ 406 * 8 | Reserved | 407 * +-----------------------------------------------------+ 408 */ 409 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 410 /* Extended Receive Descriptor (Write-Back) Format 411 * 412 * 63 48 47 32 31 24 23 4 3 0 413 * +------------------------------------------------------+ 414 * | RSS Hash | | | | 415 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 416 * | Packet | IP | | | Type | 417 * | Checksum | Ident | | | | 418 * +------------------------------------------------------+ 419 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 420 * +------------------------------------------------------+ 421 * 63 48 47 32 31 20 19 0 422 */ 423 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 424 425 for (i = 0; i < rx_ring->count; i++) { 426 const char *next_desc; 427 428 buffer_info = &rx_ring->buffer_info[i]; 429 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 430 u1 = (struct my_u1 *)rx_desc; 431 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 432 433 if (i == rx_ring->next_to_use) 434 next_desc = " NTU"; 435 else if (i == rx_ring->next_to_clean) 436 next_desc = " NTC"; 437 else 438 next_desc = ""; 439 440 if (staterr & E1000_RXD_STAT_DD) { 441 /* Descriptor Done */ 442 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 443 "RWB", i, 444 (unsigned long long)le64_to_cpu(u1->a), 445 (unsigned long long)le64_to_cpu(u1->b), 446 buffer_info->skb, next_desc); 447 } else { 448 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 449 "R ", i, 450 (unsigned long long)le64_to_cpu(u1->a), 451 (unsigned long long)le64_to_cpu(u1->b), 452 (unsigned long long)buffer_info->dma, 453 buffer_info->skb, next_desc); 454 455 if (netif_msg_pktdata(adapter) && 456 buffer_info->skb) 457 print_hex_dump(KERN_INFO, "", 458 DUMP_PREFIX_ADDRESS, 16, 459 1, 460 buffer_info->skb->data, 461 adapter->rx_buffer_len, 462 true); 463 } 464 } 465 } 466 } 467 468 /** 469 * e1000_desc_unused - calculate if we have unused descriptors 470 * @ring: pointer to ring struct to perform calculation on 471 **/ 472 static int e1000_desc_unused(struct e1000_ring *ring) 473 { 474 if (ring->next_to_clean > ring->next_to_use) 475 return ring->next_to_clean - ring->next_to_use - 1; 476 477 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 478 } 479 480 /** 481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 482 * @adapter: board private structure 483 * @hwtstamps: time stamp structure to update 484 * @systim: unsigned 64bit system time value. 485 * 486 * Convert the system time value stored in the RX/TXSTMP registers into a 487 * hwtstamp which can be used by the upper level time stamping functions. 488 * 489 * The 'systim_lock' spinlock is used to protect the consistency of the 490 * system time value. This is needed because reading the 64 bit time 491 * value involves reading two 32 bit registers. The first read latches the 492 * value. 493 **/ 494 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 495 struct skb_shared_hwtstamps *hwtstamps, 496 u64 systim) 497 { 498 u64 ns; 499 unsigned long flags; 500 501 spin_lock_irqsave(&adapter->systim_lock, flags); 502 ns = timecounter_cyc2time(&adapter->tc, systim); 503 spin_unlock_irqrestore(&adapter->systim_lock, flags); 504 505 memset(hwtstamps, 0, sizeof(*hwtstamps)); 506 hwtstamps->hwtstamp = ns_to_ktime(ns); 507 } 508 509 /** 510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 511 * @adapter: board private structure 512 * @status: descriptor extended error and status field 513 * @skb: particular skb to include time stamp 514 * 515 * If the time stamp is valid, convert it into the timecounter ns value 516 * and store that result into the shhwtstamps structure which is passed 517 * up the network stack. 518 **/ 519 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 520 struct sk_buff *skb) 521 { 522 struct e1000_hw *hw = &adapter->hw; 523 u64 rxstmp; 524 525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 526 !(status & E1000_RXDEXT_STATERR_TST) || 527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 528 return; 529 530 /* The Rx time stamp registers contain the time stamp. No other 531 * received packet will be time stamped until the Rx time stamp 532 * registers are read. Because only one packet can be time stamped 533 * at a time, the register values must belong to this packet and 534 * therefore none of the other additional attributes need to be 535 * compared. 536 */ 537 rxstmp = (u64)er32(RXSTMPL); 538 rxstmp |= (u64)er32(RXSTMPH) << 32; 539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 540 541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 542 } 543 544 /** 545 * e1000_receive_skb - helper function to handle Rx indications 546 * @adapter: board private structure 547 * @netdev: pointer to netdev struct 548 * @staterr: descriptor extended error and status field as written by hardware 549 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 550 * @skb: pointer to sk_buff to be indicated to stack 551 **/ 552 static void e1000_receive_skb(struct e1000_adapter *adapter, 553 struct net_device *netdev, struct sk_buff *skb, 554 u32 staterr, __le16 vlan) 555 { 556 u16 tag = le16_to_cpu(vlan); 557 558 e1000e_rx_hwtstamp(adapter, staterr, skb); 559 560 skb->protocol = eth_type_trans(skb, netdev); 561 562 if (staterr & E1000_RXD_STAT_VP) 563 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 564 565 napi_gro_receive(&adapter->napi, skb); 566 } 567 568 /** 569 * e1000_rx_checksum - Receive Checksum Offload 570 * @adapter: board private structure 571 * @status_err: receive descriptor status and error fields 572 * @skb: socket buffer with received data 573 **/ 574 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 575 struct sk_buff *skb) 576 { 577 u16 status = (u16)status_err; 578 u8 errors = (u8)(status_err >> 24); 579 580 skb_checksum_none_assert(skb); 581 582 /* Rx checksum disabled */ 583 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 584 return; 585 586 /* Ignore Checksum bit is set */ 587 if (status & E1000_RXD_STAT_IXSM) 588 return; 589 590 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 592 /* let the stack verify checksum errors */ 593 adapter->hw_csum_err++; 594 return; 595 } 596 597 /* TCP/UDP Checksum has not been calculated */ 598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 599 return; 600 601 /* It must be a TCP or UDP packet with a valid checksum */ 602 skb->ip_summed = CHECKSUM_UNNECESSARY; 603 adapter->hw_csum_good++; 604 } 605 606 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 607 { 608 struct e1000_adapter *adapter = rx_ring->adapter; 609 struct e1000_hw *hw = &adapter->hw; 610 611 __ew32_prepare(hw); 612 writel(i, rx_ring->tail); 613 614 if (unlikely(i != readl(rx_ring->tail))) { 615 u32 rctl = er32(RCTL); 616 617 ew32(RCTL, rctl & ~E1000_RCTL_EN); 618 e_err("ME firmware caused invalid RDT - resetting\n"); 619 schedule_work(&adapter->reset_task); 620 } 621 } 622 623 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 624 { 625 struct e1000_adapter *adapter = tx_ring->adapter; 626 struct e1000_hw *hw = &adapter->hw; 627 628 __ew32_prepare(hw); 629 writel(i, tx_ring->tail); 630 631 if (unlikely(i != readl(tx_ring->tail))) { 632 u32 tctl = er32(TCTL); 633 634 ew32(TCTL, tctl & ~E1000_TCTL_EN); 635 e_err("ME firmware caused invalid TDT - resetting\n"); 636 schedule_work(&adapter->reset_task); 637 } 638 } 639 640 /** 641 * e1000_alloc_rx_buffers - Replace used receive buffers 642 * @rx_ring: Rx descriptor ring 643 * @cleaned_count: number to reallocate 644 * @gfp: flags for allocation 645 **/ 646 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 647 int cleaned_count, gfp_t gfp) 648 { 649 struct e1000_adapter *adapter = rx_ring->adapter; 650 struct net_device *netdev = adapter->netdev; 651 struct pci_dev *pdev = adapter->pdev; 652 union e1000_rx_desc_extended *rx_desc; 653 struct e1000_buffer *buffer_info; 654 struct sk_buff *skb; 655 unsigned int i; 656 unsigned int bufsz = adapter->rx_buffer_len; 657 658 i = rx_ring->next_to_use; 659 buffer_info = &rx_ring->buffer_info[i]; 660 661 while (cleaned_count--) { 662 skb = buffer_info->skb; 663 if (skb) { 664 skb_trim(skb, 0); 665 goto map_skb; 666 } 667 668 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 669 if (!skb) { 670 /* Better luck next round */ 671 adapter->alloc_rx_buff_failed++; 672 break; 673 } 674 675 buffer_info->skb = skb; 676 map_skb: 677 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 678 adapter->rx_buffer_len, 679 DMA_FROM_DEVICE); 680 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 681 dev_err(&pdev->dev, "Rx DMA map failed\n"); 682 adapter->rx_dma_failed++; 683 break; 684 } 685 686 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 687 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 688 689 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 690 /* Force memory writes to complete before letting h/w 691 * know there are new descriptors to fetch. (Only 692 * applicable for weak-ordered memory model archs, 693 * such as IA-64). 694 */ 695 wmb(); 696 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 697 e1000e_update_rdt_wa(rx_ring, i); 698 else 699 writel(i, rx_ring->tail); 700 } 701 i++; 702 if (i == rx_ring->count) 703 i = 0; 704 buffer_info = &rx_ring->buffer_info[i]; 705 } 706 707 rx_ring->next_to_use = i; 708 } 709 710 /** 711 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 712 * @rx_ring: Rx descriptor ring 713 * @cleaned_count: number to reallocate 714 * @gfp: flags for allocation 715 **/ 716 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 717 int cleaned_count, gfp_t gfp) 718 { 719 struct e1000_adapter *adapter = rx_ring->adapter; 720 struct net_device *netdev = adapter->netdev; 721 struct pci_dev *pdev = adapter->pdev; 722 union e1000_rx_desc_packet_split *rx_desc; 723 struct e1000_buffer *buffer_info; 724 struct e1000_ps_page *ps_page; 725 struct sk_buff *skb; 726 unsigned int i, j; 727 728 i = rx_ring->next_to_use; 729 buffer_info = &rx_ring->buffer_info[i]; 730 731 while (cleaned_count--) { 732 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 733 734 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 735 ps_page = &buffer_info->ps_pages[j]; 736 if (j >= adapter->rx_ps_pages) { 737 /* all unused desc entries get hw null ptr */ 738 rx_desc->read.buffer_addr[j + 1] = 739 ~cpu_to_le64(0); 740 continue; 741 } 742 if (!ps_page->page) { 743 ps_page->page = alloc_page(gfp); 744 if (!ps_page->page) { 745 adapter->alloc_rx_buff_failed++; 746 goto no_buffers; 747 } 748 ps_page->dma = dma_map_page(&pdev->dev, 749 ps_page->page, 750 0, PAGE_SIZE, 751 DMA_FROM_DEVICE); 752 if (dma_mapping_error(&pdev->dev, 753 ps_page->dma)) { 754 dev_err(&adapter->pdev->dev, 755 "Rx DMA page map failed\n"); 756 adapter->rx_dma_failed++; 757 goto no_buffers; 758 } 759 } 760 /* Refresh the desc even if buffer_addrs 761 * didn't change because each write-back 762 * erases this info. 763 */ 764 rx_desc->read.buffer_addr[j + 1] = 765 cpu_to_le64(ps_page->dma); 766 } 767 768 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 769 gfp); 770 771 if (!skb) { 772 adapter->alloc_rx_buff_failed++; 773 break; 774 } 775 776 buffer_info->skb = skb; 777 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 778 adapter->rx_ps_bsize0, 779 DMA_FROM_DEVICE); 780 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 781 dev_err(&pdev->dev, "Rx DMA map failed\n"); 782 adapter->rx_dma_failed++; 783 /* cleanup skb */ 784 dev_kfree_skb_any(skb); 785 buffer_info->skb = NULL; 786 break; 787 } 788 789 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 790 791 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 792 /* Force memory writes to complete before letting h/w 793 * know there are new descriptors to fetch. (Only 794 * applicable for weak-ordered memory model archs, 795 * such as IA-64). 796 */ 797 wmb(); 798 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 799 e1000e_update_rdt_wa(rx_ring, i << 1); 800 else 801 writel(i << 1, rx_ring->tail); 802 } 803 804 i++; 805 if (i == rx_ring->count) 806 i = 0; 807 buffer_info = &rx_ring->buffer_info[i]; 808 } 809 810 no_buffers: 811 rx_ring->next_to_use = i; 812 } 813 814 /** 815 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 816 * @rx_ring: Rx descriptor ring 817 * @cleaned_count: number of buffers to allocate this pass 818 * @gfp: flags for allocation 819 **/ 820 821 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 822 int cleaned_count, gfp_t gfp) 823 { 824 struct e1000_adapter *adapter = rx_ring->adapter; 825 struct net_device *netdev = adapter->netdev; 826 struct pci_dev *pdev = adapter->pdev; 827 union e1000_rx_desc_extended *rx_desc; 828 struct e1000_buffer *buffer_info; 829 struct sk_buff *skb; 830 unsigned int i; 831 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 832 833 i = rx_ring->next_to_use; 834 buffer_info = &rx_ring->buffer_info[i]; 835 836 while (cleaned_count--) { 837 skb = buffer_info->skb; 838 if (skb) { 839 skb_trim(skb, 0); 840 goto check_page; 841 } 842 843 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 844 if (unlikely(!skb)) { 845 /* Better luck next round */ 846 adapter->alloc_rx_buff_failed++; 847 break; 848 } 849 850 buffer_info->skb = skb; 851 check_page: 852 /* allocate a new page if necessary */ 853 if (!buffer_info->page) { 854 buffer_info->page = alloc_page(gfp); 855 if (unlikely(!buffer_info->page)) { 856 adapter->alloc_rx_buff_failed++; 857 break; 858 } 859 } 860 861 if (!buffer_info->dma) { 862 buffer_info->dma = dma_map_page(&pdev->dev, 863 buffer_info->page, 0, 864 PAGE_SIZE, 865 DMA_FROM_DEVICE); 866 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 867 adapter->alloc_rx_buff_failed++; 868 break; 869 } 870 } 871 872 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 873 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 874 875 if (unlikely(++i == rx_ring->count)) 876 i = 0; 877 buffer_info = &rx_ring->buffer_info[i]; 878 } 879 880 if (likely(rx_ring->next_to_use != i)) { 881 rx_ring->next_to_use = i; 882 if (unlikely(i-- == 0)) 883 i = (rx_ring->count - 1); 884 885 /* Force memory writes to complete before letting h/w 886 * know there are new descriptors to fetch. (Only 887 * applicable for weak-ordered memory model archs, 888 * such as IA-64). 889 */ 890 wmb(); 891 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 892 e1000e_update_rdt_wa(rx_ring, i); 893 else 894 writel(i, rx_ring->tail); 895 } 896 } 897 898 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 899 struct sk_buff *skb) 900 { 901 if (netdev->features & NETIF_F_RXHASH) 902 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 903 } 904 905 /** 906 * e1000_clean_rx_irq - Send received data up the network stack 907 * @rx_ring: Rx descriptor ring 908 * @work_done: output parameter for indicating completed work 909 * @work_to_do: how many packets we can clean 910 * 911 * the return value indicates whether actual cleaning was done, there 912 * is no guarantee that everything was cleaned 913 **/ 914 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 915 int work_to_do) 916 { 917 struct e1000_adapter *adapter = rx_ring->adapter; 918 struct net_device *netdev = adapter->netdev; 919 struct pci_dev *pdev = adapter->pdev; 920 struct e1000_hw *hw = &adapter->hw; 921 union e1000_rx_desc_extended *rx_desc, *next_rxd; 922 struct e1000_buffer *buffer_info, *next_buffer; 923 u32 length, staterr; 924 unsigned int i; 925 int cleaned_count = 0; 926 bool cleaned = false; 927 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 928 929 i = rx_ring->next_to_clean; 930 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 931 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 932 buffer_info = &rx_ring->buffer_info[i]; 933 934 while (staterr & E1000_RXD_STAT_DD) { 935 struct sk_buff *skb; 936 937 if (*work_done >= work_to_do) 938 break; 939 (*work_done)++; 940 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 941 942 skb = buffer_info->skb; 943 buffer_info->skb = NULL; 944 945 prefetch(skb->data - NET_IP_ALIGN); 946 947 i++; 948 if (i == rx_ring->count) 949 i = 0; 950 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 951 prefetch(next_rxd); 952 953 next_buffer = &rx_ring->buffer_info[i]; 954 955 cleaned = true; 956 cleaned_count++; 957 dma_unmap_single(&pdev->dev, buffer_info->dma, 958 adapter->rx_buffer_len, DMA_FROM_DEVICE); 959 buffer_info->dma = 0; 960 961 length = le16_to_cpu(rx_desc->wb.upper.length); 962 963 /* !EOP means multiple descriptors were used to store a single 964 * packet, if that's the case we need to toss it. In fact, we 965 * need to toss every packet with the EOP bit clear and the 966 * next frame that _does_ have the EOP bit set, as it is by 967 * definition only a frame fragment 968 */ 969 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 970 adapter->flags2 |= FLAG2_IS_DISCARDING; 971 972 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 973 /* All receives must fit into a single buffer */ 974 e_dbg("Receive packet consumed multiple buffers\n"); 975 /* recycle */ 976 buffer_info->skb = skb; 977 if (staterr & E1000_RXD_STAT_EOP) 978 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 979 goto next_desc; 980 } 981 982 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 983 !(netdev->features & NETIF_F_RXALL))) { 984 /* recycle */ 985 buffer_info->skb = skb; 986 goto next_desc; 987 } 988 989 /* adjust length to remove Ethernet CRC */ 990 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 991 /* If configured to store CRC, don't subtract FCS, 992 * but keep the FCS bytes out of the total_rx_bytes 993 * counter 994 */ 995 if (netdev->features & NETIF_F_RXFCS) 996 total_rx_bytes -= 4; 997 else 998 length -= 4; 999 } 1000 1001 total_rx_bytes += length; 1002 total_rx_packets++; 1003 1004 /* code added for copybreak, this should improve 1005 * performance for small packets with large amounts 1006 * of reassembly being done in the stack 1007 */ 1008 if (length < copybreak) { 1009 struct sk_buff *new_skb = 1010 napi_alloc_skb(&adapter->napi, length); 1011 if (new_skb) { 1012 skb_copy_to_linear_data_offset(new_skb, 1013 -NET_IP_ALIGN, 1014 (skb->data - 1015 NET_IP_ALIGN), 1016 (length + 1017 NET_IP_ALIGN)); 1018 /* save the skb in buffer_info as good */ 1019 buffer_info->skb = skb; 1020 skb = new_skb; 1021 } 1022 /* else just continue with the old one */ 1023 } 1024 /* end copybreak code */ 1025 skb_put(skb, length); 1026 1027 /* Receive Checksum Offload */ 1028 e1000_rx_checksum(adapter, staterr, skb); 1029 1030 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1031 1032 e1000_receive_skb(adapter, netdev, skb, staterr, 1033 rx_desc->wb.upper.vlan); 1034 1035 next_desc: 1036 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1037 1038 /* return some buffers to hardware, one at a time is too slow */ 1039 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1040 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1041 GFP_ATOMIC); 1042 cleaned_count = 0; 1043 } 1044 1045 /* use prefetched values */ 1046 rx_desc = next_rxd; 1047 buffer_info = next_buffer; 1048 1049 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1050 } 1051 rx_ring->next_to_clean = i; 1052 1053 cleaned_count = e1000_desc_unused(rx_ring); 1054 if (cleaned_count) 1055 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1056 1057 adapter->total_rx_bytes += total_rx_bytes; 1058 adapter->total_rx_packets += total_rx_packets; 1059 return cleaned; 1060 } 1061 1062 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1063 struct e1000_buffer *buffer_info, 1064 bool drop) 1065 { 1066 struct e1000_adapter *adapter = tx_ring->adapter; 1067 1068 if (buffer_info->dma) { 1069 if (buffer_info->mapped_as_page) 1070 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1071 buffer_info->length, DMA_TO_DEVICE); 1072 else 1073 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1074 buffer_info->length, DMA_TO_DEVICE); 1075 buffer_info->dma = 0; 1076 } 1077 if (buffer_info->skb) { 1078 if (drop) 1079 dev_kfree_skb_any(buffer_info->skb); 1080 else 1081 dev_consume_skb_any(buffer_info->skb); 1082 buffer_info->skb = NULL; 1083 } 1084 buffer_info->time_stamp = 0; 1085 } 1086 1087 static void e1000_print_hw_hang(struct work_struct *work) 1088 { 1089 struct e1000_adapter *adapter = container_of(work, 1090 struct e1000_adapter, 1091 print_hang_task); 1092 struct net_device *netdev = adapter->netdev; 1093 struct e1000_ring *tx_ring = adapter->tx_ring; 1094 unsigned int i = tx_ring->next_to_clean; 1095 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1096 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1097 struct e1000_hw *hw = &adapter->hw; 1098 u16 phy_status, phy_1000t_status, phy_ext_status; 1099 u16 pci_status; 1100 1101 if (test_bit(__E1000_DOWN, &adapter->state)) 1102 return; 1103 1104 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1105 /* May be block on write-back, flush and detect again 1106 * flush pending descriptor writebacks to memory 1107 */ 1108 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1109 /* execute the writes immediately */ 1110 e1e_flush(); 1111 /* Due to rare timing issues, write to TIDV again to ensure 1112 * the write is successful 1113 */ 1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1115 /* execute the writes immediately */ 1116 e1e_flush(); 1117 adapter->tx_hang_recheck = true; 1118 return; 1119 } 1120 adapter->tx_hang_recheck = false; 1121 1122 if (er32(TDH(0)) == er32(TDT(0))) { 1123 e_dbg("false hang detected, ignoring\n"); 1124 return; 1125 } 1126 1127 /* Real hang detected */ 1128 netif_stop_queue(netdev); 1129 1130 e1e_rphy(hw, MII_BMSR, &phy_status); 1131 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1132 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1133 1134 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1135 1136 /* detected Hardware unit hang */ 1137 e_err("Detected Hardware Unit Hang:\n" 1138 " TDH <%x>\n" 1139 " TDT <%x>\n" 1140 " next_to_use <%x>\n" 1141 " next_to_clean <%x>\n" 1142 "buffer_info[next_to_clean]:\n" 1143 " time_stamp <%lx>\n" 1144 " next_to_watch <%x>\n" 1145 " jiffies <%lx>\n" 1146 " next_to_watch.status <%x>\n" 1147 "MAC Status <%x>\n" 1148 "PHY Status <%x>\n" 1149 "PHY 1000BASE-T Status <%x>\n" 1150 "PHY Extended Status <%x>\n" 1151 "PCI Status <%x>\n", 1152 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1153 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1154 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1155 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1156 1157 e1000e_dump(adapter); 1158 1159 /* Suggest workaround for known h/w issue */ 1160 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1161 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1162 } 1163 1164 /** 1165 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1166 * @work: pointer to work struct 1167 * 1168 * This work function polls the TSYNCTXCTL valid bit to determine when a 1169 * timestamp has been taken for the current stored skb. The timestamp must 1170 * be for this skb because only one such packet is allowed in the queue. 1171 */ 1172 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1173 { 1174 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1175 tx_hwtstamp_work); 1176 struct e1000_hw *hw = &adapter->hw; 1177 1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1179 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1180 struct skb_shared_hwtstamps shhwtstamps; 1181 u64 txstmp; 1182 1183 txstmp = er32(TXSTMPL); 1184 txstmp |= (u64)er32(TXSTMPH) << 32; 1185 1186 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1187 1188 /* Clear the global tx_hwtstamp_skb pointer and force writes 1189 * prior to notifying the stack of a Tx timestamp. 1190 */ 1191 adapter->tx_hwtstamp_skb = NULL; 1192 wmb(); /* force write prior to skb_tstamp_tx */ 1193 1194 skb_tstamp_tx(skb, &shhwtstamps); 1195 dev_consume_skb_any(skb); 1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1197 + adapter->tx_timeout_factor * HZ)) { 1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1199 adapter->tx_hwtstamp_skb = NULL; 1200 adapter->tx_hwtstamp_timeouts++; 1201 e_warn("clearing Tx timestamp hang\n"); 1202 } else { 1203 /* reschedule to check later */ 1204 schedule_work(&adapter->tx_hwtstamp_work); 1205 } 1206 } 1207 1208 /** 1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1210 * @tx_ring: Tx descriptor ring 1211 * 1212 * the return value indicates whether actual cleaning was done, there 1213 * is no guarantee that everything was cleaned 1214 **/ 1215 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1216 { 1217 struct e1000_adapter *adapter = tx_ring->adapter; 1218 struct net_device *netdev = adapter->netdev; 1219 struct e1000_hw *hw = &adapter->hw; 1220 struct e1000_tx_desc *tx_desc, *eop_desc; 1221 struct e1000_buffer *buffer_info; 1222 unsigned int i, eop; 1223 unsigned int count = 0; 1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1225 unsigned int bytes_compl = 0, pkts_compl = 0; 1226 1227 i = tx_ring->next_to_clean; 1228 eop = tx_ring->buffer_info[i].next_to_watch; 1229 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1230 1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1232 (count < tx_ring->count)) { 1233 bool cleaned = false; 1234 1235 dma_rmb(); /* read buffer_info after eop_desc */ 1236 for (; !cleaned; count++) { 1237 tx_desc = E1000_TX_DESC(*tx_ring, i); 1238 buffer_info = &tx_ring->buffer_info[i]; 1239 cleaned = (i == eop); 1240 1241 if (cleaned) { 1242 total_tx_packets += buffer_info->segs; 1243 total_tx_bytes += buffer_info->bytecount; 1244 if (buffer_info->skb) { 1245 bytes_compl += buffer_info->skb->len; 1246 pkts_compl++; 1247 } 1248 } 1249 1250 e1000_put_txbuf(tx_ring, buffer_info, false); 1251 tx_desc->upper.data = 0; 1252 1253 i++; 1254 if (i == tx_ring->count) 1255 i = 0; 1256 } 1257 1258 if (i == tx_ring->next_to_use) 1259 break; 1260 eop = tx_ring->buffer_info[i].next_to_watch; 1261 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1262 } 1263 1264 tx_ring->next_to_clean = i; 1265 1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1267 1268 #define TX_WAKE_THRESHOLD 32 1269 if (count && netif_carrier_ok(netdev) && 1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1271 /* Make sure that anybody stopping the queue after this 1272 * sees the new next_to_clean. 1273 */ 1274 smp_mb(); 1275 1276 if (netif_queue_stopped(netdev) && 1277 !(test_bit(__E1000_DOWN, &adapter->state))) { 1278 netif_wake_queue(netdev); 1279 ++adapter->restart_queue; 1280 } 1281 } 1282 1283 if (adapter->detect_tx_hung) { 1284 /* Detect a transmit hang in hardware, this serializes the 1285 * check with the clearing of time_stamp and movement of i 1286 */ 1287 adapter->detect_tx_hung = false; 1288 if (tx_ring->buffer_info[i].time_stamp && 1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1290 + (adapter->tx_timeout_factor * HZ)) && 1291 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1292 schedule_work(&adapter->print_hang_task); 1293 else 1294 adapter->tx_hang_recheck = false; 1295 } 1296 adapter->total_tx_bytes += total_tx_bytes; 1297 adapter->total_tx_packets += total_tx_packets; 1298 return count < tx_ring->count; 1299 } 1300 1301 /** 1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1303 * @rx_ring: Rx descriptor ring 1304 * @work_done: output parameter for indicating completed work 1305 * @work_to_do: how many packets we can clean 1306 * 1307 * the return value indicates whether actual cleaning was done, there 1308 * is no guarantee that everything was cleaned 1309 **/ 1310 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1311 int work_to_do) 1312 { 1313 struct e1000_adapter *adapter = rx_ring->adapter; 1314 struct e1000_hw *hw = &adapter->hw; 1315 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1316 struct net_device *netdev = adapter->netdev; 1317 struct pci_dev *pdev = adapter->pdev; 1318 struct e1000_buffer *buffer_info, *next_buffer; 1319 struct e1000_ps_page *ps_page; 1320 struct sk_buff *skb; 1321 unsigned int i, j; 1322 u32 length, staterr; 1323 int cleaned_count = 0; 1324 bool cleaned = false; 1325 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1326 1327 i = rx_ring->next_to_clean; 1328 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1329 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1330 buffer_info = &rx_ring->buffer_info[i]; 1331 1332 while (staterr & E1000_RXD_STAT_DD) { 1333 if (*work_done >= work_to_do) 1334 break; 1335 (*work_done)++; 1336 skb = buffer_info->skb; 1337 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1338 1339 /* in the packet split case this is header only */ 1340 prefetch(skb->data - NET_IP_ALIGN); 1341 1342 i++; 1343 if (i == rx_ring->count) 1344 i = 0; 1345 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1346 prefetch(next_rxd); 1347 1348 next_buffer = &rx_ring->buffer_info[i]; 1349 1350 cleaned = true; 1351 cleaned_count++; 1352 dma_unmap_single(&pdev->dev, buffer_info->dma, 1353 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1354 buffer_info->dma = 0; 1355 1356 /* see !EOP comment in other Rx routine */ 1357 if (!(staterr & E1000_RXD_STAT_EOP)) 1358 adapter->flags2 |= FLAG2_IS_DISCARDING; 1359 1360 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1361 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1362 dev_kfree_skb_irq(skb); 1363 if (staterr & E1000_RXD_STAT_EOP) 1364 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1365 goto next_desc; 1366 } 1367 1368 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1369 !(netdev->features & NETIF_F_RXALL))) { 1370 dev_kfree_skb_irq(skb); 1371 goto next_desc; 1372 } 1373 1374 length = le16_to_cpu(rx_desc->wb.middle.length0); 1375 1376 if (!length) { 1377 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1378 dev_kfree_skb_irq(skb); 1379 goto next_desc; 1380 } 1381 1382 /* Good Receive */ 1383 skb_put(skb, length); 1384 1385 { 1386 /* this looks ugly, but it seems compiler issues make 1387 * it more efficient than reusing j 1388 */ 1389 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1390 1391 /* page alloc/put takes too long and effects small 1392 * packet throughput, so unsplit small packets and 1393 * save the alloc/put 1394 */ 1395 if (l1 && (l1 <= copybreak) && 1396 ((length + l1) <= adapter->rx_ps_bsize0)) { 1397 ps_page = &buffer_info->ps_pages[0]; 1398 1399 dma_sync_single_for_cpu(&pdev->dev, 1400 ps_page->dma, 1401 PAGE_SIZE, 1402 DMA_FROM_DEVICE); 1403 memcpy(skb_tail_pointer(skb), 1404 page_address(ps_page->page), l1); 1405 dma_sync_single_for_device(&pdev->dev, 1406 ps_page->dma, 1407 PAGE_SIZE, 1408 DMA_FROM_DEVICE); 1409 1410 /* remove the CRC */ 1411 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1412 if (!(netdev->features & NETIF_F_RXFCS)) 1413 l1 -= 4; 1414 } 1415 1416 skb_put(skb, l1); 1417 goto copydone; 1418 } /* if */ 1419 } 1420 1421 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1422 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1423 if (!length) 1424 break; 1425 1426 ps_page = &buffer_info->ps_pages[j]; 1427 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1428 DMA_FROM_DEVICE); 1429 ps_page->dma = 0; 1430 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1431 ps_page->page = NULL; 1432 skb->len += length; 1433 skb->data_len += length; 1434 skb->truesize += PAGE_SIZE; 1435 } 1436 1437 /* strip the ethernet crc, problem is we're using pages now so 1438 * this whole operation can get a little cpu intensive 1439 */ 1440 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1441 if (!(netdev->features & NETIF_F_RXFCS)) 1442 pskb_trim(skb, skb->len - 4); 1443 } 1444 1445 copydone: 1446 total_rx_bytes += skb->len; 1447 total_rx_packets++; 1448 1449 e1000_rx_checksum(adapter, staterr, skb); 1450 1451 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1452 1453 if (rx_desc->wb.upper.header_status & 1454 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1455 adapter->rx_hdr_split++; 1456 1457 e1000_receive_skb(adapter, netdev, skb, staterr, 1458 rx_desc->wb.middle.vlan); 1459 1460 next_desc: 1461 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1462 buffer_info->skb = NULL; 1463 1464 /* return some buffers to hardware, one at a time is too slow */ 1465 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1466 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1467 GFP_ATOMIC); 1468 cleaned_count = 0; 1469 } 1470 1471 /* use prefetched values */ 1472 rx_desc = next_rxd; 1473 buffer_info = next_buffer; 1474 1475 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1476 } 1477 rx_ring->next_to_clean = i; 1478 1479 cleaned_count = e1000_desc_unused(rx_ring); 1480 if (cleaned_count) 1481 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1482 1483 adapter->total_rx_bytes += total_rx_bytes; 1484 adapter->total_rx_packets += total_rx_packets; 1485 return cleaned; 1486 } 1487 1488 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1489 u16 length) 1490 { 1491 bi->page = NULL; 1492 skb->len += length; 1493 skb->data_len += length; 1494 skb->truesize += PAGE_SIZE; 1495 } 1496 1497 /** 1498 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1499 * @rx_ring: Rx descriptor ring 1500 * @work_done: output parameter for indicating completed work 1501 * @work_to_do: how many packets we can clean 1502 * 1503 * the return value indicates whether actual cleaning was done, there 1504 * is no guarantee that everything was cleaned 1505 **/ 1506 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1507 int work_to_do) 1508 { 1509 struct e1000_adapter *adapter = rx_ring->adapter; 1510 struct net_device *netdev = adapter->netdev; 1511 struct pci_dev *pdev = adapter->pdev; 1512 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1513 struct e1000_buffer *buffer_info, *next_buffer; 1514 u32 length, staterr; 1515 unsigned int i; 1516 int cleaned_count = 0; 1517 bool cleaned = false; 1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1519 struct skb_shared_info *shinfo; 1520 1521 i = rx_ring->next_to_clean; 1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1524 buffer_info = &rx_ring->buffer_info[i]; 1525 1526 while (staterr & E1000_RXD_STAT_DD) { 1527 struct sk_buff *skb; 1528 1529 if (*work_done >= work_to_do) 1530 break; 1531 (*work_done)++; 1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1533 1534 skb = buffer_info->skb; 1535 buffer_info->skb = NULL; 1536 1537 ++i; 1538 if (i == rx_ring->count) 1539 i = 0; 1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1541 prefetch(next_rxd); 1542 1543 next_buffer = &rx_ring->buffer_info[i]; 1544 1545 cleaned = true; 1546 cleaned_count++; 1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1548 DMA_FROM_DEVICE); 1549 buffer_info->dma = 0; 1550 1551 length = le16_to_cpu(rx_desc->wb.upper.length); 1552 1553 /* errors is only valid for DD + EOP descriptors */ 1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1556 !(netdev->features & NETIF_F_RXALL)))) { 1557 /* recycle both page and skb */ 1558 buffer_info->skb = skb; 1559 /* an error means any chain goes out the window too */ 1560 if (rx_ring->rx_skb_top) 1561 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1562 rx_ring->rx_skb_top = NULL; 1563 goto next_desc; 1564 } 1565 #define rxtop (rx_ring->rx_skb_top) 1566 if (!(staterr & E1000_RXD_STAT_EOP)) { 1567 /* this descriptor is only the beginning (or middle) */ 1568 if (!rxtop) { 1569 /* this is the beginning of a chain */ 1570 rxtop = skb; 1571 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1572 0, length); 1573 } else { 1574 /* this is the middle of a chain */ 1575 shinfo = skb_shinfo(rxtop); 1576 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1577 buffer_info->page, 0, 1578 length); 1579 /* re-use the skb, only consumed the page */ 1580 buffer_info->skb = skb; 1581 } 1582 e1000_consume_page(buffer_info, rxtop, length); 1583 goto next_desc; 1584 } else { 1585 if (rxtop) { 1586 /* end of the chain */ 1587 shinfo = skb_shinfo(rxtop); 1588 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1589 buffer_info->page, 0, 1590 length); 1591 /* re-use the current skb, we only consumed the 1592 * page 1593 */ 1594 buffer_info->skb = skb; 1595 skb = rxtop; 1596 rxtop = NULL; 1597 e1000_consume_page(buffer_info, skb, length); 1598 } else { 1599 /* no chain, got EOP, this buf is the packet 1600 * copybreak to save the put_page/alloc_page 1601 */ 1602 if (length <= copybreak && 1603 skb_tailroom(skb) >= length) { 1604 memcpy(skb_tail_pointer(skb), 1605 page_address(buffer_info->page), 1606 length); 1607 /* re-use the page, so don't erase 1608 * buffer_info->page 1609 */ 1610 skb_put(skb, length); 1611 } else { 1612 skb_fill_page_desc(skb, 0, 1613 buffer_info->page, 0, 1614 length); 1615 e1000_consume_page(buffer_info, skb, 1616 length); 1617 } 1618 } 1619 } 1620 1621 /* Receive Checksum Offload */ 1622 e1000_rx_checksum(adapter, staterr, skb); 1623 1624 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1625 1626 /* probably a little skewed due to removing CRC */ 1627 total_rx_bytes += skb->len; 1628 total_rx_packets++; 1629 1630 /* eth type trans needs skb->data to point to something */ 1631 if (!pskb_may_pull(skb, ETH_HLEN)) { 1632 e_err("pskb_may_pull failed.\n"); 1633 dev_kfree_skb_irq(skb); 1634 goto next_desc; 1635 } 1636 1637 e1000_receive_skb(adapter, netdev, skb, staterr, 1638 rx_desc->wb.upper.vlan); 1639 1640 next_desc: 1641 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1642 1643 /* return some buffers to hardware, one at a time is too slow */ 1644 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1645 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1646 GFP_ATOMIC); 1647 cleaned_count = 0; 1648 } 1649 1650 /* use prefetched values */ 1651 rx_desc = next_rxd; 1652 buffer_info = next_buffer; 1653 1654 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1655 } 1656 rx_ring->next_to_clean = i; 1657 1658 cleaned_count = e1000_desc_unused(rx_ring); 1659 if (cleaned_count) 1660 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1661 1662 adapter->total_rx_bytes += total_rx_bytes; 1663 adapter->total_rx_packets += total_rx_packets; 1664 return cleaned; 1665 } 1666 1667 /** 1668 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1669 * @rx_ring: Rx descriptor ring 1670 **/ 1671 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1672 { 1673 struct e1000_adapter *adapter = rx_ring->adapter; 1674 struct e1000_buffer *buffer_info; 1675 struct e1000_ps_page *ps_page; 1676 struct pci_dev *pdev = adapter->pdev; 1677 unsigned int i, j; 1678 1679 /* Free all the Rx ring sk_buffs */ 1680 for (i = 0; i < rx_ring->count; i++) { 1681 buffer_info = &rx_ring->buffer_info[i]; 1682 if (buffer_info->dma) { 1683 if (adapter->clean_rx == e1000_clean_rx_irq) 1684 dma_unmap_single(&pdev->dev, buffer_info->dma, 1685 adapter->rx_buffer_len, 1686 DMA_FROM_DEVICE); 1687 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1688 dma_unmap_page(&pdev->dev, buffer_info->dma, 1689 PAGE_SIZE, DMA_FROM_DEVICE); 1690 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1691 dma_unmap_single(&pdev->dev, buffer_info->dma, 1692 adapter->rx_ps_bsize0, 1693 DMA_FROM_DEVICE); 1694 buffer_info->dma = 0; 1695 } 1696 1697 if (buffer_info->page) { 1698 put_page(buffer_info->page); 1699 buffer_info->page = NULL; 1700 } 1701 1702 if (buffer_info->skb) { 1703 dev_kfree_skb(buffer_info->skb); 1704 buffer_info->skb = NULL; 1705 } 1706 1707 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1708 ps_page = &buffer_info->ps_pages[j]; 1709 if (!ps_page->page) 1710 break; 1711 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1712 DMA_FROM_DEVICE); 1713 ps_page->dma = 0; 1714 put_page(ps_page->page); 1715 ps_page->page = NULL; 1716 } 1717 } 1718 1719 /* there also may be some cached data from a chained receive */ 1720 if (rx_ring->rx_skb_top) { 1721 dev_kfree_skb(rx_ring->rx_skb_top); 1722 rx_ring->rx_skb_top = NULL; 1723 } 1724 1725 /* Zero out the descriptor ring */ 1726 memset(rx_ring->desc, 0, rx_ring->size); 1727 1728 rx_ring->next_to_clean = 0; 1729 rx_ring->next_to_use = 0; 1730 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1731 } 1732 1733 static void e1000e_downshift_workaround(struct work_struct *work) 1734 { 1735 struct e1000_adapter *adapter = container_of(work, 1736 struct e1000_adapter, 1737 downshift_task); 1738 1739 if (test_bit(__E1000_DOWN, &adapter->state)) 1740 return; 1741 1742 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1743 } 1744 1745 /** 1746 * e1000_intr_msi - Interrupt Handler 1747 * @irq: interrupt number 1748 * @data: pointer to a network interface device structure 1749 **/ 1750 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1751 { 1752 struct net_device *netdev = data; 1753 struct e1000_adapter *adapter = netdev_priv(netdev); 1754 struct e1000_hw *hw = &adapter->hw; 1755 u32 icr = er32(ICR); 1756 1757 /* read ICR disables interrupts using IAM */ 1758 if (icr & E1000_ICR_LSC) { 1759 hw->mac.get_link_status = true; 1760 /* ICH8 workaround-- Call gig speed drop workaround on cable 1761 * disconnect (LSC) before accessing any PHY registers 1762 */ 1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1764 (!(er32(STATUS) & E1000_STATUS_LU))) 1765 schedule_work(&adapter->downshift_task); 1766 1767 /* 80003ES2LAN workaround-- For packet buffer work-around on 1768 * link down event; disable receives here in the ISR and reset 1769 * adapter in watchdog 1770 */ 1771 if (netif_carrier_ok(netdev) && 1772 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1773 /* disable receives */ 1774 u32 rctl = er32(RCTL); 1775 1776 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1777 adapter->flags |= FLAG_RESTART_NOW; 1778 } 1779 /* guard against interrupt when we're going down */ 1780 if (!test_bit(__E1000_DOWN, &adapter->state)) 1781 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1782 } 1783 1784 /* Reset on uncorrectable ECC error */ 1785 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1786 u32 pbeccsts = er32(PBECCSTS); 1787 1788 adapter->corr_errors += 1789 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1790 adapter->uncorr_errors += 1791 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1792 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1793 1794 /* Do the reset outside of interrupt context */ 1795 schedule_work(&adapter->reset_task); 1796 1797 /* return immediately since reset is imminent */ 1798 return IRQ_HANDLED; 1799 } 1800 1801 if (napi_schedule_prep(&adapter->napi)) { 1802 adapter->total_tx_bytes = 0; 1803 adapter->total_tx_packets = 0; 1804 adapter->total_rx_bytes = 0; 1805 adapter->total_rx_packets = 0; 1806 __napi_schedule(&adapter->napi); 1807 } 1808 1809 return IRQ_HANDLED; 1810 } 1811 1812 /** 1813 * e1000_intr - Interrupt Handler 1814 * @irq: interrupt number 1815 * @data: pointer to a network interface device structure 1816 **/ 1817 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1818 { 1819 struct net_device *netdev = data; 1820 struct e1000_adapter *adapter = netdev_priv(netdev); 1821 struct e1000_hw *hw = &adapter->hw; 1822 u32 rctl, icr = er32(ICR); 1823 1824 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1825 return IRQ_NONE; /* Not our interrupt */ 1826 1827 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1828 * not set, then the adapter didn't send an interrupt 1829 */ 1830 if (!(icr & E1000_ICR_INT_ASSERTED)) 1831 return IRQ_NONE; 1832 1833 /* Interrupt Auto-Mask...upon reading ICR, 1834 * interrupts are masked. No need for the 1835 * IMC write 1836 */ 1837 1838 if (icr & E1000_ICR_LSC) { 1839 hw->mac.get_link_status = true; 1840 /* ICH8 workaround-- Call gig speed drop workaround on cable 1841 * disconnect (LSC) before accessing any PHY registers 1842 */ 1843 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1844 (!(er32(STATUS) & E1000_STATUS_LU))) 1845 schedule_work(&adapter->downshift_task); 1846 1847 /* 80003ES2LAN workaround-- 1848 * For packet buffer work-around on link down event; 1849 * disable receives here in the ISR and 1850 * reset adapter in watchdog 1851 */ 1852 if (netif_carrier_ok(netdev) && 1853 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1854 /* disable receives */ 1855 rctl = er32(RCTL); 1856 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1857 adapter->flags |= FLAG_RESTART_NOW; 1858 } 1859 /* guard against interrupt when we're going down */ 1860 if (!test_bit(__E1000_DOWN, &adapter->state)) 1861 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1862 } 1863 1864 /* Reset on uncorrectable ECC error */ 1865 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1866 u32 pbeccsts = er32(PBECCSTS); 1867 1868 adapter->corr_errors += 1869 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1870 adapter->uncorr_errors += 1871 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1872 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1873 1874 /* Do the reset outside of interrupt context */ 1875 schedule_work(&adapter->reset_task); 1876 1877 /* return immediately since reset is imminent */ 1878 return IRQ_HANDLED; 1879 } 1880 1881 if (napi_schedule_prep(&adapter->napi)) { 1882 adapter->total_tx_bytes = 0; 1883 adapter->total_tx_packets = 0; 1884 adapter->total_rx_bytes = 0; 1885 adapter->total_rx_packets = 0; 1886 __napi_schedule(&adapter->napi); 1887 } 1888 1889 return IRQ_HANDLED; 1890 } 1891 1892 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1893 { 1894 struct net_device *netdev = data; 1895 struct e1000_adapter *adapter = netdev_priv(netdev); 1896 struct e1000_hw *hw = &adapter->hw; 1897 u32 icr = er32(ICR); 1898 1899 if (icr & adapter->eiac_mask) 1900 ew32(ICS, (icr & adapter->eiac_mask)); 1901 1902 if (icr & E1000_ICR_LSC) { 1903 hw->mac.get_link_status = true; 1904 /* guard against interrupt when we're going down */ 1905 if (!test_bit(__E1000_DOWN, &adapter->state)) 1906 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1907 } 1908 1909 if (!test_bit(__E1000_DOWN, &adapter->state)) 1910 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1911 1912 return IRQ_HANDLED; 1913 } 1914 1915 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1916 { 1917 struct net_device *netdev = data; 1918 struct e1000_adapter *adapter = netdev_priv(netdev); 1919 struct e1000_hw *hw = &adapter->hw; 1920 struct e1000_ring *tx_ring = adapter->tx_ring; 1921 1922 adapter->total_tx_bytes = 0; 1923 adapter->total_tx_packets = 0; 1924 1925 if (!e1000_clean_tx_irq(tx_ring)) 1926 /* Ring was not completely cleaned, so fire another interrupt */ 1927 ew32(ICS, tx_ring->ims_val); 1928 1929 if (!test_bit(__E1000_DOWN, &adapter->state)) 1930 ew32(IMS, adapter->tx_ring->ims_val); 1931 1932 return IRQ_HANDLED; 1933 } 1934 1935 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1936 { 1937 struct net_device *netdev = data; 1938 struct e1000_adapter *adapter = netdev_priv(netdev); 1939 struct e1000_ring *rx_ring = adapter->rx_ring; 1940 1941 /* Write the ITR value calculated at the end of the 1942 * previous interrupt. 1943 */ 1944 if (rx_ring->set_itr) { 1945 u32 itr = rx_ring->itr_val ? 1946 1000000000 / (rx_ring->itr_val * 256) : 0; 1947 1948 writel(itr, rx_ring->itr_register); 1949 rx_ring->set_itr = 0; 1950 } 1951 1952 if (napi_schedule_prep(&adapter->napi)) { 1953 adapter->total_rx_bytes = 0; 1954 adapter->total_rx_packets = 0; 1955 __napi_schedule(&adapter->napi); 1956 } 1957 return IRQ_HANDLED; 1958 } 1959 1960 /** 1961 * e1000_configure_msix - Configure MSI-X hardware 1962 * @adapter: board private structure 1963 * 1964 * e1000_configure_msix sets up the hardware to properly 1965 * generate MSI-X interrupts. 1966 **/ 1967 static void e1000_configure_msix(struct e1000_adapter *adapter) 1968 { 1969 struct e1000_hw *hw = &adapter->hw; 1970 struct e1000_ring *rx_ring = adapter->rx_ring; 1971 struct e1000_ring *tx_ring = adapter->tx_ring; 1972 int vector = 0; 1973 u32 ctrl_ext, ivar = 0; 1974 1975 adapter->eiac_mask = 0; 1976 1977 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1978 if (hw->mac.type == e1000_82574) { 1979 u32 rfctl = er32(RFCTL); 1980 1981 rfctl |= E1000_RFCTL_ACK_DIS; 1982 ew32(RFCTL, rfctl); 1983 } 1984 1985 /* Configure Rx vector */ 1986 rx_ring->ims_val = E1000_IMS_RXQ0; 1987 adapter->eiac_mask |= rx_ring->ims_val; 1988 if (rx_ring->itr_val) 1989 writel(1000000000 / (rx_ring->itr_val * 256), 1990 rx_ring->itr_register); 1991 else 1992 writel(1, rx_ring->itr_register); 1993 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 1994 1995 /* Configure Tx vector */ 1996 tx_ring->ims_val = E1000_IMS_TXQ0; 1997 vector++; 1998 if (tx_ring->itr_val) 1999 writel(1000000000 / (tx_ring->itr_val * 256), 2000 tx_ring->itr_register); 2001 else 2002 writel(1, tx_ring->itr_register); 2003 adapter->eiac_mask |= tx_ring->ims_val; 2004 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2005 2006 /* set vector for Other Causes, e.g. link changes */ 2007 vector++; 2008 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2009 if (rx_ring->itr_val) 2010 writel(1000000000 / (rx_ring->itr_val * 256), 2011 hw->hw_addr + E1000_EITR_82574(vector)); 2012 else 2013 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2014 2015 /* Cause Tx interrupts on every write back */ 2016 ivar |= BIT(31); 2017 2018 ew32(IVAR, ivar); 2019 2020 /* enable MSI-X PBA support */ 2021 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2022 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2023 ew32(CTRL_EXT, ctrl_ext); 2024 e1e_flush(); 2025 } 2026 2027 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2028 { 2029 if (adapter->msix_entries) { 2030 pci_disable_msix(adapter->pdev); 2031 kfree(adapter->msix_entries); 2032 adapter->msix_entries = NULL; 2033 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2034 pci_disable_msi(adapter->pdev); 2035 adapter->flags &= ~FLAG_MSI_ENABLED; 2036 } 2037 } 2038 2039 /** 2040 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2041 * @adapter: board private structure 2042 * 2043 * Attempt to configure interrupts using the best available 2044 * capabilities of the hardware and kernel. 2045 **/ 2046 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2047 { 2048 int err; 2049 int i; 2050 2051 switch (adapter->int_mode) { 2052 case E1000E_INT_MODE_MSIX: 2053 if (adapter->flags & FLAG_HAS_MSIX) { 2054 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2055 adapter->msix_entries = kcalloc(adapter->num_vectors, 2056 sizeof(struct 2057 msix_entry), 2058 GFP_KERNEL); 2059 if (adapter->msix_entries) { 2060 struct e1000_adapter *a = adapter; 2061 2062 for (i = 0; i < adapter->num_vectors; i++) 2063 adapter->msix_entries[i].entry = i; 2064 2065 err = pci_enable_msix_range(a->pdev, 2066 a->msix_entries, 2067 a->num_vectors, 2068 a->num_vectors); 2069 if (err > 0) 2070 return; 2071 } 2072 /* MSI-X failed, so fall through and try MSI */ 2073 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2074 e1000e_reset_interrupt_capability(adapter); 2075 } 2076 adapter->int_mode = E1000E_INT_MODE_MSI; 2077 fallthrough; 2078 case E1000E_INT_MODE_MSI: 2079 if (!pci_enable_msi(adapter->pdev)) { 2080 adapter->flags |= FLAG_MSI_ENABLED; 2081 } else { 2082 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2083 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2084 } 2085 fallthrough; 2086 case E1000E_INT_MODE_LEGACY: 2087 /* Don't do anything; this is the system default */ 2088 break; 2089 } 2090 2091 /* store the number of vectors being used */ 2092 adapter->num_vectors = 1; 2093 } 2094 2095 /** 2096 * e1000_request_msix - Initialize MSI-X interrupts 2097 * @adapter: board private structure 2098 * 2099 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2100 * kernel. 2101 **/ 2102 static int e1000_request_msix(struct e1000_adapter *adapter) 2103 { 2104 struct net_device *netdev = adapter->netdev; 2105 int err = 0, vector = 0; 2106 2107 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2108 snprintf(adapter->rx_ring->name, 2109 sizeof(adapter->rx_ring->name) - 1, 2110 "%.14s-rx-0", netdev->name); 2111 else 2112 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2113 err = request_irq(adapter->msix_entries[vector].vector, 2114 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2115 netdev); 2116 if (err) 2117 return err; 2118 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2119 E1000_EITR_82574(vector); 2120 adapter->rx_ring->itr_val = adapter->itr; 2121 vector++; 2122 2123 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2124 snprintf(adapter->tx_ring->name, 2125 sizeof(adapter->tx_ring->name) - 1, 2126 "%.14s-tx-0", netdev->name); 2127 else 2128 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2129 err = request_irq(adapter->msix_entries[vector].vector, 2130 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2131 netdev); 2132 if (err) 2133 return err; 2134 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2135 E1000_EITR_82574(vector); 2136 adapter->tx_ring->itr_val = adapter->itr; 2137 vector++; 2138 2139 err = request_irq(adapter->msix_entries[vector].vector, 2140 e1000_msix_other, 0, netdev->name, netdev); 2141 if (err) 2142 return err; 2143 2144 e1000_configure_msix(adapter); 2145 2146 return 0; 2147 } 2148 2149 /** 2150 * e1000_request_irq - initialize interrupts 2151 * @adapter: board private structure 2152 * 2153 * Attempts to configure interrupts using the best available 2154 * capabilities of the hardware and kernel. 2155 **/ 2156 static int e1000_request_irq(struct e1000_adapter *adapter) 2157 { 2158 struct net_device *netdev = adapter->netdev; 2159 int err; 2160 2161 if (adapter->msix_entries) { 2162 err = e1000_request_msix(adapter); 2163 if (!err) 2164 return err; 2165 /* fall back to MSI */ 2166 e1000e_reset_interrupt_capability(adapter); 2167 adapter->int_mode = E1000E_INT_MODE_MSI; 2168 e1000e_set_interrupt_capability(adapter); 2169 } 2170 if (adapter->flags & FLAG_MSI_ENABLED) { 2171 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2172 netdev->name, netdev); 2173 if (!err) 2174 return err; 2175 2176 /* fall back to legacy interrupt */ 2177 e1000e_reset_interrupt_capability(adapter); 2178 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2179 } 2180 2181 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2182 netdev->name, netdev); 2183 if (err) 2184 e_err("Unable to allocate interrupt, Error: %d\n", err); 2185 2186 return err; 2187 } 2188 2189 static void e1000_free_irq(struct e1000_adapter *adapter) 2190 { 2191 struct net_device *netdev = adapter->netdev; 2192 2193 if (adapter->msix_entries) { 2194 int vector = 0; 2195 2196 free_irq(adapter->msix_entries[vector].vector, netdev); 2197 vector++; 2198 2199 free_irq(adapter->msix_entries[vector].vector, netdev); 2200 vector++; 2201 2202 /* Other Causes interrupt vector */ 2203 free_irq(adapter->msix_entries[vector].vector, netdev); 2204 return; 2205 } 2206 2207 free_irq(adapter->pdev->irq, netdev); 2208 } 2209 2210 /** 2211 * e1000_irq_disable - Mask off interrupt generation on the NIC 2212 * @adapter: board private structure 2213 **/ 2214 static void e1000_irq_disable(struct e1000_adapter *adapter) 2215 { 2216 struct e1000_hw *hw = &adapter->hw; 2217 2218 ew32(IMC, ~0); 2219 if (adapter->msix_entries) 2220 ew32(EIAC_82574, 0); 2221 e1e_flush(); 2222 2223 if (adapter->msix_entries) { 2224 int i; 2225 2226 for (i = 0; i < adapter->num_vectors; i++) 2227 synchronize_irq(adapter->msix_entries[i].vector); 2228 } else { 2229 synchronize_irq(adapter->pdev->irq); 2230 } 2231 } 2232 2233 /** 2234 * e1000_irq_enable - Enable default interrupt generation settings 2235 * @adapter: board private structure 2236 **/ 2237 static void e1000_irq_enable(struct e1000_adapter *adapter) 2238 { 2239 struct e1000_hw *hw = &adapter->hw; 2240 2241 if (adapter->msix_entries) { 2242 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2243 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2244 IMS_OTHER_MASK); 2245 } else if (hw->mac.type >= e1000_pch_lpt) { 2246 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2247 } else { 2248 ew32(IMS, IMS_ENABLE_MASK); 2249 } 2250 e1e_flush(); 2251 } 2252 2253 /** 2254 * e1000e_get_hw_control - get control of the h/w from f/w 2255 * @adapter: address of board private structure 2256 * 2257 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2258 * For ASF and Pass Through versions of f/w this means that 2259 * the driver is loaded. For AMT version (only with 82573) 2260 * of the f/w this means that the network i/f is open. 2261 **/ 2262 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2263 { 2264 struct e1000_hw *hw = &adapter->hw; 2265 u32 ctrl_ext; 2266 u32 swsm; 2267 2268 /* Let firmware know the driver has taken over */ 2269 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2270 swsm = er32(SWSM); 2271 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2272 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2273 ctrl_ext = er32(CTRL_EXT); 2274 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2275 } 2276 } 2277 2278 /** 2279 * e1000e_release_hw_control - release control of the h/w to f/w 2280 * @adapter: address of board private structure 2281 * 2282 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2283 * For ASF and Pass Through versions of f/w this means that the 2284 * driver is no longer loaded. For AMT version (only with 82573) i 2285 * of the f/w this means that the network i/f is closed. 2286 * 2287 **/ 2288 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2289 { 2290 struct e1000_hw *hw = &adapter->hw; 2291 u32 ctrl_ext; 2292 u32 swsm; 2293 2294 /* Let firmware taken over control of h/w */ 2295 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2296 swsm = er32(SWSM); 2297 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2298 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2299 ctrl_ext = er32(CTRL_EXT); 2300 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2301 } 2302 } 2303 2304 /** 2305 * e1000_alloc_ring_dma - allocate memory for a ring structure 2306 * @adapter: board private structure 2307 * @ring: ring struct for which to allocate dma 2308 **/ 2309 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2310 struct e1000_ring *ring) 2311 { 2312 struct pci_dev *pdev = adapter->pdev; 2313 2314 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2315 GFP_KERNEL); 2316 if (!ring->desc) 2317 return -ENOMEM; 2318 2319 return 0; 2320 } 2321 2322 /** 2323 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2324 * @tx_ring: Tx descriptor ring 2325 * 2326 * Return 0 on success, negative on failure 2327 **/ 2328 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2329 { 2330 struct e1000_adapter *adapter = tx_ring->adapter; 2331 int err = -ENOMEM, size; 2332 2333 size = sizeof(struct e1000_buffer) * tx_ring->count; 2334 tx_ring->buffer_info = vzalloc(size); 2335 if (!tx_ring->buffer_info) 2336 goto err; 2337 2338 /* round up to nearest 4K */ 2339 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2340 tx_ring->size = ALIGN(tx_ring->size, 4096); 2341 2342 err = e1000_alloc_ring_dma(adapter, tx_ring); 2343 if (err) 2344 goto err; 2345 2346 tx_ring->next_to_use = 0; 2347 tx_ring->next_to_clean = 0; 2348 2349 return 0; 2350 err: 2351 vfree(tx_ring->buffer_info); 2352 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2353 return err; 2354 } 2355 2356 /** 2357 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2358 * @rx_ring: Rx descriptor ring 2359 * 2360 * Returns 0 on success, negative on failure 2361 **/ 2362 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2363 { 2364 struct e1000_adapter *adapter = rx_ring->adapter; 2365 struct e1000_buffer *buffer_info; 2366 int i, size, desc_len, err = -ENOMEM; 2367 2368 size = sizeof(struct e1000_buffer) * rx_ring->count; 2369 rx_ring->buffer_info = vzalloc(size); 2370 if (!rx_ring->buffer_info) 2371 goto err; 2372 2373 for (i = 0; i < rx_ring->count; i++) { 2374 buffer_info = &rx_ring->buffer_info[i]; 2375 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2376 sizeof(struct e1000_ps_page), 2377 GFP_KERNEL); 2378 if (!buffer_info->ps_pages) 2379 goto err_pages; 2380 } 2381 2382 desc_len = sizeof(union e1000_rx_desc_packet_split); 2383 2384 /* Round up to nearest 4K */ 2385 rx_ring->size = rx_ring->count * desc_len; 2386 rx_ring->size = ALIGN(rx_ring->size, 4096); 2387 2388 err = e1000_alloc_ring_dma(adapter, rx_ring); 2389 if (err) 2390 goto err_pages; 2391 2392 rx_ring->next_to_clean = 0; 2393 rx_ring->next_to_use = 0; 2394 rx_ring->rx_skb_top = NULL; 2395 2396 return 0; 2397 2398 err_pages: 2399 for (i = 0; i < rx_ring->count; i++) { 2400 buffer_info = &rx_ring->buffer_info[i]; 2401 kfree(buffer_info->ps_pages); 2402 } 2403 err: 2404 vfree(rx_ring->buffer_info); 2405 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2406 return err; 2407 } 2408 2409 /** 2410 * e1000_clean_tx_ring - Free Tx Buffers 2411 * @tx_ring: Tx descriptor ring 2412 **/ 2413 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2414 { 2415 struct e1000_adapter *adapter = tx_ring->adapter; 2416 struct e1000_buffer *buffer_info; 2417 unsigned long size; 2418 unsigned int i; 2419 2420 for (i = 0; i < tx_ring->count; i++) { 2421 buffer_info = &tx_ring->buffer_info[i]; 2422 e1000_put_txbuf(tx_ring, buffer_info, false); 2423 } 2424 2425 netdev_reset_queue(adapter->netdev); 2426 size = sizeof(struct e1000_buffer) * tx_ring->count; 2427 memset(tx_ring->buffer_info, 0, size); 2428 2429 memset(tx_ring->desc, 0, tx_ring->size); 2430 2431 tx_ring->next_to_use = 0; 2432 tx_ring->next_to_clean = 0; 2433 } 2434 2435 /** 2436 * e1000e_free_tx_resources - Free Tx Resources per Queue 2437 * @tx_ring: Tx descriptor ring 2438 * 2439 * Free all transmit software resources 2440 **/ 2441 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2442 { 2443 struct e1000_adapter *adapter = tx_ring->adapter; 2444 struct pci_dev *pdev = adapter->pdev; 2445 2446 e1000_clean_tx_ring(tx_ring); 2447 2448 vfree(tx_ring->buffer_info); 2449 tx_ring->buffer_info = NULL; 2450 2451 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2452 tx_ring->dma); 2453 tx_ring->desc = NULL; 2454 } 2455 2456 /** 2457 * e1000e_free_rx_resources - Free Rx Resources 2458 * @rx_ring: Rx descriptor ring 2459 * 2460 * Free all receive software resources 2461 **/ 2462 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2463 { 2464 struct e1000_adapter *adapter = rx_ring->adapter; 2465 struct pci_dev *pdev = adapter->pdev; 2466 int i; 2467 2468 e1000_clean_rx_ring(rx_ring); 2469 2470 for (i = 0; i < rx_ring->count; i++) 2471 kfree(rx_ring->buffer_info[i].ps_pages); 2472 2473 vfree(rx_ring->buffer_info); 2474 rx_ring->buffer_info = NULL; 2475 2476 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2477 rx_ring->dma); 2478 rx_ring->desc = NULL; 2479 } 2480 2481 /** 2482 * e1000_update_itr - update the dynamic ITR value based on statistics 2483 * @itr_setting: current adapter->itr 2484 * @packets: the number of packets during this measurement interval 2485 * @bytes: the number of bytes during this measurement interval 2486 * 2487 * Stores a new ITR value based on packets and byte 2488 * counts during the last interrupt. The advantage of per interrupt 2489 * computation is faster updates and more accurate ITR for the current 2490 * traffic pattern. Constants in this function were computed 2491 * based on theoretical maximum wire speed and thresholds were set based 2492 * on testing data as well as attempting to minimize response time 2493 * while increasing bulk throughput. This functionality is controlled 2494 * by the InterruptThrottleRate module parameter. 2495 **/ 2496 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2497 { 2498 unsigned int retval = itr_setting; 2499 2500 if (packets == 0) 2501 return itr_setting; 2502 2503 switch (itr_setting) { 2504 case lowest_latency: 2505 /* handle TSO and jumbo frames */ 2506 if (bytes / packets > 8000) 2507 retval = bulk_latency; 2508 else if ((packets < 5) && (bytes > 512)) 2509 retval = low_latency; 2510 break; 2511 case low_latency: /* 50 usec aka 20000 ints/s */ 2512 if (bytes > 10000) { 2513 /* this if handles the TSO accounting */ 2514 if (bytes / packets > 8000) 2515 retval = bulk_latency; 2516 else if ((packets < 10) || ((bytes / packets) > 1200)) 2517 retval = bulk_latency; 2518 else if ((packets > 35)) 2519 retval = lowest_latency; 2520 } else if (bytes / packets > 2000) { 2521 retval = bulk_latency; 2522 } else if (packets <= 2 && bytes < 512) { 2523 retval = lowest_latency; 2524 } 2525 break; 2526 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2527 if (bytes > 25000) { 2528 if (packets > 35) 2529 retval = low_latency; 2530 } else if (bytes < 6000) { 2531 retval = low_latency; 2532 } 2533 break; 2534 } 2535 2536 return retval; 2537 } 2538 2539 static void e1000_set_itr(struct e1000_adapter *adapter) 2540 { 2541 u16 current_itr; 2542 u32 new_itr = adapter->itr; 2543 2544 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2545 if (adapter->link_speed != SPEED_1000) { 2546 new_itr = 4000; 2547 goto set_itr_now; 2548 } 2549 2550 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2551 new_itr = 0; 2552 goto set_itr_now; 2553 } 2554 2555 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2556 adapter->total_tx_packets, 2557 adapter->total_tx_bytes); 2558 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2559 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2560 adapter->tx_itr = low_latency; 2561 2562 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2563 adapter->total_rx_packets, 2564 adapter->total_rx_bytes); 2565 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2566 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2567 adapter->rx_itr = low_latency; 2568 2569 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2570 2571 /* counts and packets in update_itr are dependent on these numbers */ 2572 switch (current_itr) { 2573 case lowest_latency: 2574 new_itr = 70000; 2575 break; 2576 case low_latency: 2577 new_itr = 20000; /* aka hwitr = ~200 */ 2578 break; 2579 case bulk_latency: 2580 new_itr = 4000; 2581 break; 2582 default: 2583 break; 2584 } 2585 2586 set_itr_now: 2587 if (new_itr != adapter->itr) { 2588 /* this attempts to bias the interrupt rate towards Bulk 2589 * by adding intermediate steps when interrupt rate is 2590 * increasing 2591 */ 2592 new_itr = new_itr > adapter->itr ? 2593 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2594 adapter->itr = new_itr; 2595 adapter->rx_ring->itr_val = new_itr; 2596 if (adapter->msix_entries) 2597 adapter->rx_ring->set_itr = 1; 2598 else 2599 e1000e_write_itr(adapter, new_itr); 2600 } 2601 } 2602 2603 /** 2604 * e1000e_write_itr - write the ITR value to the appropriate registers 2605 * @adapter: address of board private structure 2606 * @itr: new ITR value to program 2607 * 2608 * e1000e_write_itr determines if the adapter is in MSI-X mode 2609 * and, if so, writes the EITR registers with the ITR value. 2610 * Otherwise, it writes the ITR value into the ITR register. 2611 **/ 2612 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2613 { 2614 struct e1000_hw *hw = &adapter->hw; 2615 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2616 2617 if (adapter->msix_entries) { 2618 int vector; 2619 2620 for (vector = 0; vector < adapter->num_vectors; vector++) 2621 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2622 } else { 2623 ew32(ITR, new_itr); 2624 } 2625 } 2626 2627 /** 2628 * e1000_alloc_queues - Allocate memory for all rings 2629 * @adapter: board private structure to initialize 2630 **/ 2631 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2632 { 2633 int size = sizeof(struct e1000_ring); 2634 2635 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2636 if (!adapter->tx_ring) 2637 goto err; 2638 adapter->tx_ring->count = adapter->tx_ring_count; 2639 adapter->tx_ring->adapter = adapter; 2640 2641 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2642 if (!adapter->rx_ring) 2643 goto err; 2644 adapter->rx_ring->count = adapter->rx_ring_count; 2645 adapter->rx_ring->adapter = adapter; 2646 2647 return 0; 2648 err: 2649 e_err("Unable to allocate memory for queues\n"); 2650 kfree(adapter->rx_ring); 2651 kfree(adapter->tx_ring); 2652 return -ENOMEM; 2653 } 2654 2655 /** 2656 * e1000e_poll - NAPI Rx polling callback 2657 * @napi: struct associated with this polling callback 2658 * @budget: number of packets driver is allowed to process this poll 2659 **/ 2660 static int e1000e_poll(struct napi_struct *napi, int budget) 2661 { 2662 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2663 napi); 2664 struct e1000_hw *hw = &adapter->hw; 2665 struct net_device *poll_dev = adapter->netdev; 2666 int tx_cleaned = 1, work_done = 0; 2667 2668 adapter = netdev_priv(poll_dev); 2669 2670 if (!adapter->msix_entries || 2671 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2672 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2673 2674 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2675 2676 if (!tx_cleaned || work_done == budget) 2677 return budget; 2678 2679 /* Exit the polling mode, but don't re-enable interrupts if stack might 2680 * poll us due to busy-polling 2681 */ 2682 if (likely(napi_complete_done(napi, work_done))) { 2683 if (adapter->itr_setting & 3) 2684 e1000_set_itr(adapter); 2685 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2686 if (adapter->msix_entries) 2687 ew32(IMS, adapter->rx_ring->ims_val); 2688 else 2689 e1000_irq_enable(adapter); 2690 } 2691 } 2692 2693 return work_done; 2694 } 2695 2696 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2697 __always_unused __be16 proto, u16 vid) 2698 { 2699 struct e1000_adapter *adapter = netdev_priv(netdev); 2700 struct e1000_hw *hw = &adapter->hw; 2701 u32 vfta, index; 2702 2703 /* don't update vlan cookie if already programmed */ 2704 if ((adapter->hw.mng_cookie.status & 2705 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2706 (vid == adapter->mng_vlan_id)) 2707 return 0; 2708 2709 /* add VID to filter table */ 2710 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2711 index = (vid >> 5) & 0x7F; 2712 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2713 vfta |= BIT((vid & 0x1F)); 2714 hw->mac.ops.write_vfta(hw, index, vfta); 2715 } 2716 2717 set_bit(vid, adapter->active_vlans); 2718 2719 return 0; 2720 } 2721 2722 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2723 __always_unused __be16 proto, u16 vid) 2724 { 2725 struct e1000_adapter *adapter = netdev_priv(netdev); 2726 struct e1000_hw *hw = &adapter->hw; 2727 u32 vfta, index; 2728 2729 if ((adapter->hw.mng_cookie.status & 2730 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2731 (vid == adapter->mng_vlan_id)) { 2732 /* release control to f/w */ 2733 e1000e_release_hw_control(adapter); 2734 return 0; 2735 } 2736 2737 /* remove VID from filter table */ 2738 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2739 index = (vid >> 5) & 0x7F; 2740 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2741 vfta &= ~BIT((vid & 0x1F)); 2742 hw->mac.ops.write_vfta(hw, index, vfta); 2743 } 2744 2745 clear_bit(vid, adapter->active_vlans); 2746 2747 return 0; 2748 } 2749 2750 /** 2751 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2752 * @adapter: board private structure to initialize 2753 **/ 2754 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2755 { 2756 struct net_device *netdev = adapter->netdev; 2757 struct e1000_hw *hw = &adapter->hw; 2758 u32 rctl; 2759 2760 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2761 /* disable VLAN receive filtering */ 2762 rctl = er32(RCTL); 2763 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2764 ew32(RCTL, rctl); 2765 2766 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2767 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2768 adapter->mng_vlan_id); 2769 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2770 } 2771 } 2772 } 2773 2774 /** 2775 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2776 * @adapter: board private structure to initialize 2777 **/ 2778 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2779 { 2780 struct e1000_hw *hw = &adapter->hw; 2781 u32 rctl; 2782 2783 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2784 /* enable VLAN receive filtering */ 2785 rctl = er32(RCTL); 2786 rctl |= E1000_RCTL_VFE; 2787 rctl &= ~E1000_RCTL_CFIEN; 2788 ew32(RCTL, rctl); 2789 } 2790 } 2791 2792 /** 2793 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2794 * @adapter: board private structure to initialize 2795 **/ 2796 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2797 { 2798 struct e1000_hw *hw = &adapter->hw; 2799 u32 ctrl; 2800 2801 /* disable VLAN tag insert/strip */ 2802 ctrl = er32(CTRL); 2803 ctrl &= ~E1000_CTRL_VME; 2804 ew32(CTRL, ctrl); 2805 } 2806 2807 /** 2808 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2809 * @adapter: board private structure to initialize 2810 **/ 2811 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2812 { 2813 struct e1000_hw *hw = &adapter->hw; 2814 u32 ctrl; 2815 2816 /* enable VLAN tag insert/strip */ 2817 ctrl = er32(CTRL); 2818 ctrl |= E1000_CTRL_VME; 2819 ew32(CTRL, ctrl); 2820 } 2821 2822 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2823 { 2824 struct net_device *netdev = adapter->netdev; 2825 u16 vid = adapter->hw.mng_cookie.vlan_id; 2826 u16 old_vid = adapter->mng_vlan_id; 2827 2828 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2829 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2830 adapter->mng_vlan_id = vid; 2831 } 2832 2833 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2834 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2835 } 2836 2837 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2838 { 2839 u16 vid; 2840 2841 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2842 2843 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2844 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2845 } 2846 2847 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2848 { 2849 struct e1000_hw *hw = &adapter->hw; 2850 u32 manc, manc2h, mdef, i, j; 2851 2852 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2853 return; 2854 2855 manc = er32(MANC); 2856 2857 /* enable receiving management packets to the host. this will probably 2858 * generate destination unreachable messages from the host OS, but 2859 * the packets will be handled on SMBUS 2860 */ 2861 manc |= E1000_MANC_EN_MNG2HOST; 2862 manc2h = er32(MANC2H); 2863 2864 switch (hw->mac.type) { 2865 default: 2866 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2867 break; 2868 case e1000_82574: 2869 case e1000_82583: 2870 /* Check if IPMI pass-through decision filter already exists; 2871 * if so, enable it. 2872 */ 2873 for (i = 0, j = 0; i < 8; i++) { 2874 mdef = er32(MDEF(i)); 2875 2876 /* Ignore filters with anything other than IPMI ports */ 2877 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2878 continue; 2879 2880 /* Enable this decision filter in MANC2H */ 2881 if (mdef) 2882 manc2h |= BIT(i); 2883 2884 j |= mdef; 2885 } 2886 2887 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2888 break; 2889 2890 /* Create new decision filter in an empty filter */ 2891 for (i = 0, j = 0; i < 8; i++) 2892 if (er32(MDEF(i)) == 0) { 2893 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2894 E1000_MDEF_PORT_664)); 2895 manc2h |= BIT(1); 2896 j++; 2897 break; 2898 } 2899 2900 if (!j) 2901 e_warn("Unable to create IPMI pass-through filter\n"); 2902 break; 2903 } 2904 2905 ew32(MANC2H, manc2h); 2906 ew32(MANC, manc); 2907 } 2908 2909 /** 2910 * e1000_configure_tx - Configure Transmit Unit after Reset 2911 * @adapter: board private structure 2912 * 2913 * Configure the Tx unit of the MAC after a reset. 2914 **/ 2915 static void e1000_configure_tx(struct e1000_adapter *adapter) 2916 { 2917 struct e1000_hw *hw = &adapter->hw; 2918 struct e1000_ring *tx_ring = adapter->tx_ring; 2919 u64 tdba; 2920 u32 tdlen, tctl, tarc; 2921 2922 /* Setup the HW Tx Head and Tail descriptor pointers */ 2923 tdba = tx_ring->dma; 2924 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2925 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2926 ew32(TDBAH(0), (tdba >> 32)); 2927 ew32(TDLEN(0), tdlen); 2928 ew32(TDH(0), 0); 2929 ew32(TDT(0), 0); 2930 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2931 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2932 2933 writel(0, tx_ring->head); 2934 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2935 e1000e_update_tdt_wa(tx_ring, 0); 2936 else 2937 writel(0, tx_ring->tail); 2938 2939 /* Set the Tx Interrupt Delay register */ 2940 ew32(TIDV, adapter->tx_int_delay); 2941 /* Tx irq moderation */ 2942 ew32(TADV, adapter->tx_abs_int_delay); 2943 2944 if (adapter->flags2 & FLAG2_DMA_BURST) { 2945 u32 txdctl = er32(TXDCTL(0)); 2946 2947 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2948 E1000_TXDCTL_WTHRESH); 2949 /* set up some performance related parameters to encourage the 2950 * hardware to use the bus more efficiently in bursts, depends 2951 * on the tx_int_delay to be enabled, 2952 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2953 * hthresh = 1 ==> prefetch when one or more available 2954 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2955 * BEWARE: this seems to work but should be considered first if 2956 * there are Tx hangs or other Tx related bugs 2957 */ 2958 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2959 ew32(TXDCTL(0), txdctl); 2960 } 2961 /* erratum work around: set txdctl the same for both queues */ 2962 ew32(TXDCTL(1), er32(TXDCTL(0))); 2963 2964 /* Program the Transmit Control Register */ 2965 tctl = er32(TCTL); 2966 tctl &= ~E1000_TCTL_CT; 2967 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2968 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2969 2970 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2971 tarc = er32(TARC(0)); 2972 /* set the speed mode bit, we'll clear it if we're not at 2973 * gigabit link later 2974 */ 2975 #define SPEED_MODE_BIT BIT(21) 2976 tarc |= SPEED_MODE_BIT; 2977 ew32(TARC(0), tarc); 2978 } 2979 2980 /* errata: program both queues to unweighted RR */ 2981 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2982 tarc = er32(TARC(0)); 2983 tarc |= 1; 2984 ew32(TARC(0), tarc); 2985 tarc = er32(TARC(1)); 2986 tarc |= 1; 2987 ew32(TARC(1), tarc); 2988 } 2989 2990 /* Setup Transmit Descriptor Settings for eop descriptor */ 2991 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 2992 2993 /* only set IDE if we are delaying interrupts using the timers */ 2994 if (adapter->tx_int_delay) 2995 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2996 2997 /* enable Report Status bit */ 2998 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2999 3000 ew32(TCTL, tctl); 3001 3002 hw->mac.ops.config_collision_dist(hw); 3003 3004 /* SPT and KBL Si errata workaround to avoid data corruption */ 3005 if (hw->mac.type == e1000_pch_spt) { 3006 u32 reg_val; 3007 3008 reg_val = er32(IOSFPC); 3009 reg_val |= E1000_RCTL_RDMTS_HEX; 3010 ew32(IOSFPC, reg_val); 3011 3012 reg_val = er32(TARC(0)); 3013 /* SPT and KBL Si errata workaround to avoid Tx hang. 3014 * Dropping the number of outstanding requests from 3015 * 3 to 2 in order to avoid a buffer overrun. 3016 */ 3017 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3018 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3019 ew32(TARC(0), reg_val); 3020 } 3021 } 3022 3023 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3024 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3025 3026 /** 3027 * e1000_setup_rctl - configure the receive control registers 3028 * @adapter: Board private structure 3029 **/ 3030 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3031 { 3032 struct e1000_hw *hw = &adapter->hw; 3033 u32 rctl, rfctl; 3034 u32 pages = 0; 3035 3036 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3037 * If jumbo frames not set, program related MAC/PHY registers 3038 * to h/w defaults 3039 */ 3040 if (hw->mac.type >= e1000_pch2lan) { 3041 s32 ret_val; 3042 3043 if (adapter->netdev->mtu > ETH_DATA_LEN) 3044 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3045 else 3046 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3047 3048 if (ret_val) 3049 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3050 } 3051 3052 /* Program MC offset vector base */ 3053 rctl = er32(RCTL); 3054 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3055 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3056 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3057 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3058 3059 /* Do not Store bad packets */ 3060 rctl &= ~E1000_RCTL_SBP; 3061 3062 /* Enable Long Packet receive */ 3063 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3064 rctl &= ~E1000_RCTL_LPE; 3065 else 3066 rctl |= E1000_RCTL_LPE; 3067 3068 /* Some systems expect that the CRC is included in SMBUS traffic. The 3069 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3070 * host memory when this is enabled 3071 */ 3072 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3073 rctl |= E1000_RCTL_SECRC; 3074 3075 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3076 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3077 u16 phy_data; 3078 3079 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3080 phy_data &= 0xfff8; 3081 phy_data |= BIT(2); 3082 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3083 3084 e1e_rphy(hw, 22, &phy_data); 3085 phy_data &= 0x0fff; 3086 phy_data |= BIT(14); 3087 e1e_wphy(hw, 0x10, 0x2823); 3088 e1e_wphy(hw, 0x11, 0x0003); 3089 e1e_wphy(hw, 22, phy_data); 3090 } 3091 3092 /* Setup buffer sizes */ 3093 rctl &= ~E1000_RCTL_SZ_4096; 3094 rctl |= E1000_RCTL_BSEX; 3095 switch (adapter->rx_buffer_len) { 3096 case 2048: 3097 default: 3098 rctl |= E1000_RCTL_SZ_2048; 3099 rctl &= ~E1000_RCTL_BSEX; 3100 break; 3101 case 4096: 3102 rctl |= E1000_RCTL_SZ_4096; 3103 break; 3104 case 8192: 3105 rctl |= E1000_RCTL_SZ_8192; 3106 break; 3107 case 16384: 3108 rctl |= E1000_RCTL_SZ_16384; 3109 break; 3110 } 3111 3112 /* Enable Extended Status in all Receive Descriptors */ 3113 rfctl = er32(RFCTL); 3114 rfctl |= E1000_RFCTL_EXTEN; 3115 ew32(RFCTL, rfctl); 3116 3117 /* 82571 and greater support packet-split where the protocol 3118 * header is placed in skb->data and the packet data is 3119 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3120 * In the case of a non-split, skb->data is linearly filled, 3121 * followed by the page buffers. Therefore, skb->data is 3122 * sized to hold the largest protocol header. 3123 * 3124 * allocations using alloc_page take too long for regular MTU 3125 * so only enable packet split for jumbo frames 3126 * 3127 * Using pages when the page size is greater than 16k wastes 3128 * a lot of memory, since we allocate 3 pages at all times 3129 * per packet. 3130 */ 3131 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3132 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3133 adapter->rx_ps_pages = pages; 3134 else 3135 adapter->rx_ps_pages = 0; 3136 3137 if (adapter->rx_ps_pages) { 3138 u32 psrctl = 0; 3139 3140 /* Enable Packet split descriptors */ 3141 rctl |= E1000_RCTL_DTYP_PS; 3142 3143 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3144 3145 switch (adapter->rx_ps_pages) { 3146 case 3: 3147 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3148 fallthrough; 3149 case 2: 3150 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3151 fallthrough; 3152 case 1: 3153 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3154 break; 3155 } 3156 3157 ew32(PSRCTL, psrctl); 3158 } 3159 3160 /* This is useful for sniffing bad packets. */ 3161 if (adapter->netdev->features & NETIF_F_RXALL) { 3162 /* UPE and MPE will be handled by normal PROMISC logic 3163 * in e1000e_set_rx_mode 3164 */ 3165 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3166 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3167 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3168 3169 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3170 E1000_RCTL_DPF | /* Allow filtered pause */ 3171 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3172 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3173 * and that breaks VLANs. 3174 */ 3175 } 3176 3177 ew32(RCTL, rctl); 3178 /* just started the receive unit, no need to restart */ 3179 adapter->flags &= ~FLAG_RESTART_NOW; 3180 } 3181 3182 /** 3183 * e1000_configure_rx - Configure Receive Unit after Reset 3184 * @adapter: board private structure 3185 * 3186 * Configure the Rx unit of the MAC after a reset. 3187 **/ 3188 static void e1000_configure_rx(struct e1000_adapter *adapter) 3189 { 3190 struct e1000_hw *hw = &adapter->hw; 3191 struct e1000_ring *rx_ring = adapter->rx_ring; 3192 u64 rdba; 3193 u32 rdlen, rctl, rxcsum, ctrl_ext; 3194 3195 if (adapter->rx_ps_pages) { 3196 /* this is a 32 byte descriptor */ 3197 rdlen = rx_ring->count * 3198 sizeof(union e1000_rx_desc_packet_split); 3199 adapter->clean_rx = e1000_clean_rx_irq_ps; 3200 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3201 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3202 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3203 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3204 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3205 } else { 3206 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3207 adapter->clean_rx = e1000_clean_rx_irq; 3208 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3209 } 3210 3211 /* disable receives while setting up the descriptors */ 3212 rctl = er32(RCTL); 3213 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3214 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3215 e1e_flush(); 3216 usleep_range(10000, 11000); 3217 3218 if (adapter->flags2 & FLAG2_DMA_BURST) { 3219 /* set the writeback threshold (only takes effect if the RDTR 3220 * is set). set GRAN=1 and write back up to 0x4 worth, and 3221 * enable prefetching of 0x20 Rx descriptors 3222 * granularity = 01 3223 * wthresh = 04, 3224 * hthresh = 04, 3225 * pthresh = 0x20 3226 */ 3227 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3228 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3229 } 3230 3231 /* set the Receive Delay Timer Register */ 3232 ew32(RDTR, adapter->rx_int_delay); 3233 3234 /* irq moderation */ 3235 ew32(RADV, adapter->rx_abs_int_delay); 3236 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3237 e1000e_write_itr(adapter, adapter->itr); 3238 3239 ctrl_ext = er32(CTRL_EXT); 3240 /* Auto-Mask interrupts upon ICR access */ 3241 ctrl_ext |= E1000_CTRL_EXT_IAME; 3242 ew32(IAM, 0xffffffff); 3243 ew32(CTRL_EXT, ctrl_ext); 3244 e1e_flush(); 3245 3246 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3247 * the Base and Length of the Rx Descriptor Ring 3248 */ 3249 rdba = rx_ring->dma; 3250 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3251 ew32(RDBAH(0), (rdba >> 32)); 3252 ew32(RDLEN(0), rdlen); 3253 ew32(RDH(0), 0); 3254 ew32(RDT(0), 0); 3255 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3256 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3257 3258 writel(0, rx_ring->head); 3259 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3260 e1000e_update_rdt_wa(rx_ring, 0); 3261 else 3262 writel(0, rx_ring->tail); 3263 3264 /* Enable Receive Checksum Offload for TCP and UDP */ 3265 rxcsum = er32(RXCSUM); 3266 if (adapter->netdev->features & NETIF_F_RXCSUM) 3267 rxcsum |= E1000_RXCSUM_TUOFL; 3268 else 3269 rxcsum &= ~E1000_RXCSUM_TUOFL; 3270 ew32(RXCSUM, rxcsum); 3271 3272 /* With jumbo frames, excessive C-state transition latencies result 3273 * in dropped transactions. 3274 */ 3275 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3276 u32 lat = 3277 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3278 adapter->max_frame_size) * 8 / 1000; 3279 3280 if (adapter->flags & FLAG_IS_ICH) { 3281 u32 rxdctl = er32(RXDCTL(0)); 3282 3283 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3284 } 3285 3286 dev_info(&adapter->pdev->dev, 3287 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3288 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat); 3289 } else { 3290 cpu_latency_qos_update_request(&adapter->pm_qos_req, 3291 PM_QOS_DEFAULT_VALUE); 3292 } 3293 3294 /* Enable Receives */ 3295 ew32(RCTL, rctl); 3296 } 3297 3298 /** 3299 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3300 * @netdev: network interface device structure 3301 * 3302 * Writes multicast address list to the MTA hash table. 3303 * Returns: -ENOMEM on failure 3304 * 0 on no addresses written 3305 * X on writing X addresses to MTA 3306 */ 3307 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3308 { 3309 struct e1000_adapter *adapter = netdev_priv(netdev); 3310 struct e1000_hw *hw = &adapter->hw; 3311 struct netdev_hw_addr *ha; 3312 u8 *mta_list; 3313 int i; 3314 3315 if (netdev_mc_empty(netdev)) { 3316 /* nothing to program, so clear mc list */ 3317 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3318 return 0; 3319 } 3320 3321 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3322 if (!mta_list) 3323 return -ENOMEM; 3324 3325 /* update_mc_addr_list expects a packed array of only addresses. */ 3326 i = 0; 3327 netdev_for_each_mc_addr(ha, netdev) 3328 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3329 3330 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3331 kfree(mta_list); 3332 3333 return netdev_mc_count(netdev); 3334 } 3335 3336 /** 3337 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3338 * @netdev: network interface device structure 3339 * 3340 * Writes unicast address list to the RAR table. 3341 * Returns: -ENOMEM on failure/insufficient address space 3342 * 0 on no addresses written 3343 * X on writing X addresses to the RAR table 3344 **/ 3345 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3346 { 3347 struct e1000_adapter *adapter = netdev_priv(netdev); 3348 struct e1000_hw *hw = &adapter->hw; 3349 unsigned int rar_entries; 3350 int count = 0; 3351 3352 rar_entries = hw->mac.ops.rar_get_count(hw); 3353 3354 /* save a rar entry for our hardware address */ 3355 rar_entries--; 3356 3357 /* save a rar entry for the LAA workaround */ 3358 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3359 rar_entries--; 3360 3361 /* return ENOMEM indicating insufficient memory for addresses */ 3362 if (netdev_uc_count(netdev) > rar_entries) 3363 return -ENOMEM; 3364 3365 if (!netdev_uc_empty(netdev) && rar_entries) { 3366 struct netdev_hw_addr *ha; 3367 3368 /* write the addresses in reverse order to avoid write 3369 * combining 3370 */ 3371 netdev_for_each_uc_addr(ha, netdev) { 3372 int ret_val; 3373 3374 if (!rar_entries) 3375 break; 3376 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3377 if (ret_val < 0) 3378 return -ENOMEM; 3379 count++; 3380 } 3381 } 3382 3383 /* zero out the remaining RAR entries not used above */ 3384 for (; rar_entries > 0; rar_entries--) { 3385 ew32(RAH(rar_entries), 0); 3386 ew32(RAL(rar_entries), 0); 3387 } 3388 e1e_flush(); 3389 3390 return count; 3391 } 3392 3393 /** 3394 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3395 * @netdev: network interface device structure 3396 * 3397 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3398 * address list or the network interface flags are updated. This routine is 3399 * responsible for configuring the hardware for proper unicast, multicast, 3400 * promiscuous mode, and all-multi behavior. 3401 **/ 3402 static void e1000e_set_rx_mode(struct net_device *netdev) 3403 { 3404 struct e1000_adapter *adapter = netdev_priv(netdev); 3405 struct e1000_hw *hw = &adapter->hw; 3406 u32 rctl; 3407 3408 if (pm_runtime_suspended(netdev->dev.parent)) 3409 return; 3410 3411 /* Check for Promiscuous and All Multicast modes */ 3412 rctl = er32(RCTL); 3413 3414 /* clear the affected bits */ 3415 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3416 3417 if (netdev->flags & IFF_PROMISC) { 3418 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3419 /* Do not hardware filter VLANs in promisc mode */ 3420 e1000e_vlan_filter_disable(adapter); 3421 } else { 3422 int count; 3423 3424 if (netdev->flags & IFF_ALLMULTI) { 3425 rctl |= E1000_RCTL_MPE; 3426 } else { 3427 /* Write addresses to the MTA, if the attempt fails 3428 * then we should just turn on promiscuous mode so 3429 * that we can at least receive multicast traffic 3430 */ 3431 count = e1000e_write_mc_addr_list(netdev); 3432 if (count < 0) 3433 rctl |= E1000_RCTL_MPE; 3434 } 3435 e1000e_vlan_filter_enable(adapter); 3436 /* Write addresses to available RAR registers, if there is not 3437 * sufficient space to store all the addresses then enable 3438 * unicast promiscuous mode 3439 */ 3440 count = e1000e_write_uc_addr_list(netdev); 3441 if (count < 0) 3442 rctl |= E1000_RCTL_UPE; 3443 } 3444 3445 ew32(RCTL, rctl); 3446 3447 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3448 e1000e_vlan_strip_enable(adapter); 3449 else 3450 e1000e_vlan_strip_disable(adapter); 3451 } 3452 3453 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3454 { 3455 struct e1000_hw *hw = &adapter->hw; 3456 u32 mrqc, rxcsum; 3457 u32 rss_key[10]; 3458 int i; 3459 3460 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3461 for (i = 0; i < 10; i++) 3462 ew32(RSSRK(i), rss_key[i]); 3463 3464 /* Direct all traffic to queue 0 */ 3465 for (i = 0; i < 32; i++) 3466 ew32(RETA(i), 0); 3467 3468 /* Disable raw packet checksumming so that RSS hash is placed in 3469 * descriptor on writeback. 3470 */ 3471 rxcsum = er32(RXCSUM); 3472 rxcsum |= E1000_RXCSUM_PCSD; 3473 3474 ew32(RXCSUM, rxcsum); 3475 3476 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3477 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3478 E1000_MRQC_RSS_FIELD_IPV6 | 3479 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3480 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3481 3482 ew32(MRQC, mrqc); 3483 } 3484 3485 /** 3486 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3487 * @adapter: board private structure 3488 * @timinca: pointer to returned time increment attributes 3489 * 3490 * Get attributes for incrementing the System Time Register SYSTIML/H at 3491 * the default base frequency, and set the cyclecounter shift value. 3492 **/ 3493 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3494 { 3495 struct e1000_hw *hw = &adapter->hw; 3496 u32 incvalue, incperiod, shift; 3497 3498 /* Make sure clock is enabled on I217/I218/I219 before checking 3499 * the frequency 3500 */ 3501 if ((hw->mac.type >= e1000_pch_lpt) && 3502 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3503 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3504 u32 fextnvm7 = er32(FEXTNVM7); 3505 3506 if (!(fextnvm7 & BIT(0))) { 3507 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3508 e1e_flush(); 3509 } 3510 } 3511 3512 switch (hw->mac.type) { 3513 case e1000_pch2lan: 3514 /* Stable 96MHz frequency */ 3515 incperiod = INCPERIOD_96MHZ; 3516 incvalue = INCVALUE_96MHZ; 3517 shift = INCVALUE_SHIFT_96MHZ; 3518 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3519 break; 3520 case e1000_pch_lpt: 3521 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3522 /* Stable 96MHz frequency */ 3523 incperiod = INCPERIOD_96MHZ; 3524 incvalue = INCVALUE_96MHZ; 3525 shift = INCVALUE_SHIFT_96MHZ; 3526 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3527 } else { 3528 /* Stable 25MHz frequency */ 3529 incperiod = INCPERIOD_25MHZ; 3530 incvalue = INCVALUE_25MHZ; 3531 shift = INCVALUE_SHIFT_25MHZ; 3532 adapter->cc.shift = shift; 3533 } 3534 break; 3535 case e1000_pch_spt: 3536 /* Stable 24MHz frequency */ 3537 incperiod = INCPERIOD_24MHZ; 3538 incvalue = INCVALUE_24MHZ; 3539 shift = INCVALUE_SHIFT_24MHZ; 3540 adapter->cc.shift = shift; 3541 break; 3542 case e1000_pch_cnp: 3543 case e1000_pch_tgp: 3544 case e1000_pch_adp: 3545 case e1000_pch_mtp: 3546 case e1000_pch_lnp: 3547 case e1000_pch_ptp: 3548 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3549 /* Stable 24MHz frequency */ 3550 incperiod = INCPERIOD_24MHZ; 3551 incvalue = INCVALUE_24MHZ; 3552 shift = INCVALUE_SHIFT_24MHZ; 3553 adapter->cc.shift = shift; 3554 } else { 3555 /* Stable 38400KHz frequency */ 3556 incperiod = INCPERIOD_38400KHZ; 3557 incvalue = INCVALUE_38400KHZ; 3558 shift = INCVALUE_SHIFT_38400KHZ; 3559 adapter->cc.shift = shift; 3560 } 3561 break; 3562 case e1000_82574: 3563 case e1000_82583: 3564 /* Stable 25MHz frequency */ 3565 incperiod = INCPERIOD_25MHZ; 3566 incvalue = INCVALUE_25MHZ; 3567 shift = INCVALUE_SHIFT_25MHZ; 3568 adapter->cc.shift = shift; 3569 break; 3570 default: 3571 return -EINVAL; 3572 } 3573 3574 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3575 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3576 3577 return 0; 3578 } 3579 3580 /** 3581 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3582 * @adapter: board private structure 3583 * @config: timestamp configuration 3584 * 3585 * Outgoing time stamping can be enabled and disabled. Play nice and 3586 * disable it when requested, although it shouldn't cause any overhead 3587 * when no packet needs it. At most one packet in the queue may be 3588 * marked for time stamping, otherwise it would be impossible to tell 3589 * for sure to which packet the hardware time stamp belongs. 3590 * 3591 * Incoming time stamping has to be configured via the hardware filters. 3592 * Not all combinations are supported, in particular event type has to be 3593 * specified. Matching the kind of event packet is not supported, with the 3594 * exception of "all V2 events regardless of level 2 or 4". 3595 **/ 3596 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3597 struct hwtstamp_config *config) 3598 { 3599 struct e1000_hw *hw = &adapter->hw; 3600 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3601 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3602 u32 rxmtrl = 0; 3603 u16 rxudp = 0; 3604 bool is_l4 = false; 3605 bool is_l2 = false; 3606 u32 regval; 3607 3608 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3609 return -EINVAL; 3610 3611 switch (config->tx_type) { 3612 case HWTSTAMP_TX_OFF: 3613 tsync_tx_ctl = 0; 3614 break; 3615 case HWTSTAMP_TX_ON: 3616 break; 3617 default: 3618 return -ERANGE; 3619 } 3620 3621 switch (config->rx_filter) { 3622 case HWTSTAMP_FILTER_NONE: 3623 tsync_rx_ctl = 0; 3624 break; 3625 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3626 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3627 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3628 is_l4 = true; 3629 break; 3630 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3631 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3632 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3633 is_l4 = true; 3634 break; 3635 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3636 /* Also time stamps V2 L2 Path Delay Request/Response */ 3637 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3638 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3639 is_l2 = true; 3640 break; 3641 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3642 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3643 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3644 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3645 is_l2 = true; 3646 break; 3647 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3648 /* Hardware cannot filter just V2 L4 Sync messages */ 3649 fallthrough; 3650 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3651 /* Also time stamps V2 Path Delay Request/Response. */ 3652 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3653 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3654 is_l2 = true; 3655 is_l4 = true; 3656 break; 3657 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3658 /* Hardware cannot filter just V2 L4 Delay Request messages */ 3659 fallthrough; 3660 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3661 /* Also time stamps V2 Path Delay Request/Response. */ 3662 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3663 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3664 is_l2 = true; 3665 is_l4 = true; 3666 break; 3667 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3668 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3669 /* Hardware cannot filter just V2 L4 or L2 Event messages */ 3670 fallthrough; 3671 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3672 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3673 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3674 is_l2 = true; 3675 is_l4 = true; 3676 break; 3677 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3678 /* For V1, the hardware can only filter Sync messages or 3679 * Delay Request messages but not both so fall-through to 3680 * time stamp all packets. 3681 */ 3682 fallthrough; 3683 case HWTSTAMP_FILTER_NTP_ALL: 3684 case HWTSTAMP_FILTER_ALL: 3685 is_l2 = true; 3686 is_l4 = true; 3687 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3688 config->rx_filter = HWTSTAMP_FILTER_ALL; 3689 break; 3690 default: 3691 return -ERANGE; 3692 } 3693 3694 adapter->hwtstamp_config = *config; 3695 3696 /* enable/disable Tx h/w time stamping */ 3697 regval = er32(TSYNCTXCTL); 3698 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3699 regval |= tsync_tx_ctl; 3700 ew32(TSYNCTXCTL, regval); 3701 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3702 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3703 e_err("Timesync Tx Control register not set as expected\n"); 3704 return -EAGAIN; 3705 } 3706 3707 /* enable/disable Rx h/w time stamping */ 3708 regval = er32(TSYNCRXCTL); 3709 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3710 regval |= tsync_rx_ctl; 3711 ew32(TSYNCRXCTL, regval); 3712 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3713 E1000_TSYNCRXCTL_TYPE_MASK)) != 3714 (regval & (E1000_TSYNCRXCTL_ENABLED | 3715 E1000_TSYNCRXCTL_TYPE_MASK))) { 3716 e_err("Timesync Rx Control register not set as expected\n"); 3717 return -EAGAIN; 3718 } 3719 3720 /* L2: define ethertype filter for time stamped packets */ 3721 if (is_l2) 3722 rxmtrl |= ETH_P_1588; 3723 3724 /* define which PTP packets get time stamped */ 3725 ew32(RXMTRL, rxmtrl); 3726 3727 /* Filter by destination port */ 3728 if (is_l4) { 3729 rxudp = PTP_EV_PORT; 3730 cpu_to_be16s(&rxudp); 3731 } 3732 ew32(RXUDP, rxudp); 3733 3734 e1e_flush(); 3735 3736 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3737 er32(RXSTMPH); 3738 er32(TXSTMPH); 3739 3740 return 0; 3741 } 3742 3743 /** 3744 * e1000_configure - configure the hardware for Rx and Tx 3745 * @adapter: private board structure 3746 **/ 3747 static void e1000_configure(struct e1000_adapter *adapter) 3748 { 3749 struct e1000_ring *rx_ring = adapter->rx_ring; 3750 3751 e1000e_set_rx_mode(adapter->netdev); 3752 3753 e1000_restore_vlan(adapter); 3754 e1000_init_manageability_pt(adapter); 3755 3756 e1000_configure_tx(adapter); 3757 3758 if (adapter->netdev->features & NETIF_F_RXHASH) 3759 e1000e_setup_rss_hash(adapter); 3760 e1000_setup_rctl(adapter); 3761 e1000_configure_rx(adapter); 3762 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3763 } 3764 3765 /** 3766 * e1000e_power_up_phy - restore link in case the phy was powered down 3767 * @adapter: address of board private structure 3768 * 3769 * The phy may be powered down to save power and turn off link when the 3770 * driver is unloaded and wake on lan is not enabled (among others) 3771 * *** this routine MUST be followed by a call to e1000e_reset *** 3772 **/ 3773 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3774 { 3775 if (adapter->hw.phy.ops.power_up) 3776 adapter->hw.phy.ops.power_up(&adapter->hw); 3777 3778 adapter->hw.mac.ops.setup_link(&adapter->hw); 3779 } 3780 3781 /** 3782 * e1000_power_down_phy - Power down the PHY 3783 * @adapter: board private structure 3784 * 3785 * Power down the PHY so no link is implied when interface is down. 3786 * The PHY cannot be powered down if management or WoL is active. 3787 */ 3788 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3789 { 3790 if (adapter->hw.phy.ops.power_down) 3791 adapter->hw.phy.ops.power_down(&adapter->hw); 3792 } 3793 3794 /** 3795 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3796 * @adapter: board private structure 3797 * 3798 * We want to clear all pending descriptors from the TX ring. 3799 * zeroing happens when the HW reads the regs. We assign the ring itself as 3800 * the data of the next descriptor. We don't care about the data we are about 3801 * to reset the HW. 3802 */ 3803 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3804 { 3805 struct e1000_hw *hw = &adapter->hw; 3806 struct e1000_ring *tx_ring = adapter->tx_ring; 3807 struct e1000_tx_desc *tx_desc = NULL; 3808 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3809 u16 size = 512; 3810 3811 tctl = er32(TCTL); 3812 ew32(TCTL, tctl | E1000_TCTL_EN); 3813 tdt = er32(TDT(0)); 3814 BUG_ON(tdt != tx_ring->next_to_use); 3815 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3816 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma); 3817 3818 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3819 tx_desc->upper.data = 0; 3820 /* flush descriptors to memory before notifying the HW */ 3821 wmb(); 3822 tx_ring->next_to_use++; 3823 if (tx_ring->next_to_use == tx_ring->count) 3824 tx_ring->next_to_use = 0; 3825 ew32(TDT(0), tx_ring->next_to_use); 3826 usleep_range(200, 250); 3827 } 3828 3829 /** 3830 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3831 * @adapter: board private structure 3832 * 3833 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3834 */ 3835 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3836 { 3837 u32 rctl, rxdctl; 3838 struct e1000_hw *hw = &adapter->hw; 3839 3840 rctl = er32(RCTL); 3841 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3842 e1e_flush(); 3843 usleep_range(100, 150); 3844 3845 rxdctl = er32(RXDCTL(0)); 3846 /* zero the lower 14 bits (prefetch and host thresholds) */ 3847 rxdctl &= 0xffffc000; 3848 3849 /* update thresholds: prefetch threshold to 31, host threshold to 1 3850 * and make sure the granularity is "descriptors" and not "cache lines" 3851 */ 3852 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3853 3854 ew32(RXDCTL(0), rxdctl); 3855 /* momentarily enable the RX ring for the changes to take effect */ 3856 ew32(RCTL, rctl | E1000_RCTL_EN); 3857 e1e_flush(); 3858 usleep_range(100, 150); 3859 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3860 } 3861 3862 /** 3863 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3864 * @adapter: board private structure 3865 * 3866 * In i219, the descriptor rings must be emptied before resetting the HW 3867 * or before changing the device state to D3 during runtime (runtime PM). 3868 * 3869 * Failure to do this will cause the HW to enter a unit hang state which can 3870 * only be released by PCI reset on the device 3871 * 3872 */ 3873 3874 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3875 { 3876 u16 hang_state; 3877 u32 fext_nvm11, tdlen; 3878 struct e1000_hw *hw = &adapter->hw; 3879 3880 /* First, disable MULR fix in FEXTNVM11 */ 3881 fext_nvm11 = er32(FEXTNVM11); 3882 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3883 ew32(FEXTNVM11, fext_nvm11); 3884 /* do nothing if we're not in faulty state, or if the queue is empty */ 3885 tdlen = er32(TDLEN(0)); 3886 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3887 &hang_state); 3888 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3889 return; 3890 e1000_flush_tx_ring(adapter); 3891 /* recheck, maybe the fault is caused by the rx ring */ 3892 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3893 &hang_state); 3894 if (hang_state & FLUSH_DESC_REQUIRED) 3895 e1000_flush_rx_ring(adapter); 3896 } 3897 3898 /** 3899 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3900 * @adapter: board private structure 3901 * 3902 * When the MAC is reset, all hardware bits for timesync will be reset to the 3903 * default values. This function will restore the settings last in place. 3904 * Since the clock SYSTIME registers are reset, we will simply restore the 3905 * cyclecounter to the kernel real clock time. 3906 **/ 3907 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3908 { 3909 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3910 struct e1000_hw *hw = &adapter->hw; 3911 unsigned long flags; 3912 u32 timinca; 3913 s32 ret_val; 3914 3915 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3916 return; 3917 3918 if (info->adjfine) { 3919 /* restore the previous ptp frequency delta */ 3920 ret_val = info->adjfine(info, adapter->ptp_delta); 3921 } else { 3922 /* set the default base frequency if no adjustment possible */ 3923 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3924 if (!ret_val) 3925 ew32(TIMINCA, timinca); 3926 } 3927 3928 if (ret_val) { 3929 dev_warn(&adapter->pdev->dev, 3930 "Failed to restore TIMINCA clock rate delta: %d\n", 3931 ret_val); 3932 return; 3933 } 3934 3935 /* reset the systim ns time counter */ 3936 spin_lock_irqsave(&adapter->systim_lock, flags); 3937 timecounter_init(&adapter->tc, &adapter->cc, 3938 ktime_to_ns(ktime_get_real())); 3939 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3940 3941 /* restore the previous hwtstamp configuration settings */ 3942 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3943 } 3944 3945 /** 3946 * e1000e_reset - bring the hardware into a known good state 3947 * @adapter: board private structure 3948 * 3949 * This function boots the hardware and enables some settings that 3950 * require a configuration cycle of the hardware - those cannot be 3951 * set/changed during runtime. After reset the device needs to be 3952 * properly configured for Rx, Tx etc. 3953 */ 3954 void e1000e_reset(struct e1000_adapter *adapter) 3955 { 3956 struct e1000_mac_info *mac = &adapter->hw.mac; 3957 struct e1000_fc_info *fc = &adapter->hw.fc; 3958 struct e1000_hw *hw = &adapter->hw; 3959 u32 tx_space, min_tx_space, min_rx_space; 3960 u32 pba = adapter->pba; 3961 u16 hwm; 3962 3963 /* reset Packet Buffer Allocation to default */ 3964 ew32(PBA, pba); 3965 3966 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3967 /* To maintain wire speed transmits, the Tx FIFO should be 3968 * large enough to accommodate two full transmit packets, 3969 * rounded up to the next 1KB and expressed in KB. Likewise, 3970 * the Rx FIFO should be large enough to accommodate at least 3971 * one full receive packet and is similarly rounded up and 3972 * expressed in KB. 3973 */ 3974 pba = er32(PBA); 3975 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3976 tx_space = pba >> 16; 3977 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3978 pba &= 0xffff; 3979 /* the Tx fifo also stores 16 bytes of information about the Tx 3980 * but don't include ethernet FCS because hardware appends it 3981 */ 3982 min_tx_space = (adapter->max_frame_size + 3983 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 3984 min_tx_space = ALIGN(min_tx_space, 1024); 3985 min_tx_space >>= 10; 3986 /* software strips receive CRC, so leave room for it */ 3987 min_rx_space = adapter->max_frame_size; 3988 min_rx_space = ALIGN(min_rx_space, 1024); 3989 min_rx_space >>= 10; 3990 3991 /* If current Tx allocation is less than the min Tx FIFO size, 3992 * and the min Tx FIFO size is less than the current Rx FIFO 3993 * allocation, take space away from current Rx allocation 3994 */ 3995 if ((tx_space < min_tx_space) && 3996 ((min_tx_space - tx_space) < pba)) { 3997 pba -= min_tx_space - tx_space; 3998 3999 /* if short on Rx space, Rx wins and must trump Tx 4000 * adjustment 4001 */ 4002 if (pba < min_rx_space) 4003 pba = min_rx_space; 4004 } 4005 4006 ew32(PBA, pba); 4007 } 4008 4009 /* flow control settings 4010 * 4011 * The high water mark must be low enough to fit one full frame 4012 * (or the size used for early receive) above it in the Rx FIFO. 4013 * Set it to the lower of: 4014 * - 90% of the Rx FIFO size, and 4015 * - the full Rx FIFO size minus one full frame 4016 */ 4017 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4018 fc->pause_time = 0xFFFF; 4019 else 4020 fc->pause_time = E1000_FC_PAUSE_TIME; 4021 fc->send_xon = true; 4022 fc->current_mode = fc->requested_mode; 4023 4024 switch (hw->mac.type) { 4025 case e1000_ich9lan: 4026 case e1000_ich10lan: 4027 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4028 pba = 14; 4029 ew32(PBA, pba); 4030 fc->high_water = 0x2800; 4031 fc->low_water = fc->high_water - 8; 4032 break; 4033 } 4034 fallthrough; 4035 default: 4036 hwm = min(((pba << 10) * 9 / 10), 4037 ((pba << 10) - adapter->max_frame_size)); 4038 4039 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4040 fc->low_water = fc->high_water - 8; 4041 break; 4042 case e1000_pchlan: 4043 /* Workaround PCH LOM adapter hangs with certain network 4044 * loads. If hangs persist, try disabling Tx flow control. 4045 */ 4046 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4047 fc->high_water = 0x3500; 4048 fc->low_water = 0x1500; 4049 } else { 4050 fc->high_water = 0x5000; 4051 fc->low_water = 0x3000; 4052 } 4053 fc->refresh_time = 0x1000; 4054 break; 4055 case e1000_pch2lan: 4056 case e1000_pch_lpt: 4057 case e1000_pch_spt: 4058 case e1000_pch_cnp: 4059 case e1000_pch_tgp: 4060 case e1000_pch_adp: 4061 case e1000_pch_mtp: 4062 case e1000_pch_lnp: 4063 case e1000_pch_ptp: 4064 fc->refresh_time = 0xFFFF; 4065 fc->pause_time = 0xFFFF; 4066 4067 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4068 fc->high_water = 0x05C20; 4069 fc->low_water = 0x05048; 4070 break; 4071 } 4072 4073 pba = 14; 4074 ew32(PBA, pba); 4075 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4076 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4077 break; 4078 } 4079 4080 /* Alignment of Tx data is on an arbitrary byte boundary with the 4081 * maximum size per Tx descriptor limited only to the transmit 4082 * allocation of the packet buffer minus 96 bytes with an upper 4083 * limit of 24KB due to receive synchronization limitations. 4084 */ 4085 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4086 24 << 10); 4087 4088 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4089 * fit in receive buffer. 4090 */ 4091 if (adapter->itr_setting & 0x3) { 4092 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4093 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4094 dev_info(&adapter->pdev->dev, 4095 "Interrupt Throttle Rate off\n"); 4096 adapter->flags2 |= FLAG2_DISABLE_AIM; 4097 e1000e_write_itr(adapter, 0); 4098 } 4099 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4100 dev_info(&adapter->pdev->dev, 4101 "Interrupt Throttle Rate on\n"); 4102 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4103 adapter->itr = 20000; 4104 e1000e_write_itr(adapter, adapter->itr); 4105 } 4106 } 4107 4108 if (hw->mac.type >= e1000_pch_spt) 4109 e1000_flush_desc_rings(adapter); 4110 /* Allow time for pending master requests to run */ 4111 mac->ops.reset_hw(hw); 4112 4113 /* For parts with AMT enabled, let the firmware know 4114 * that the network interface is in control 4115 */ 4116 if (adapter->flags & FLAG_HAS_AMT) 4117 e1000e_get_hw_control(adapter); 4118 4119 ew32(WUC, 0); 4120 4121 if (mac->ops.init_hw(hw)) 4122 e_err("Hardware Error\n"); 4123 4124 e1000_update_mng_vlan(adapter); 4125 4126 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4127 ew32(VET, ETH_P_8021Q); 4128 4129 e1000e_reset_adaptive(hw); 4130 4131 /* restore systim and hwtstamp settings */ 4132 e1000e_systim_reset(adapter); 4133 4134 /* Set EEE advertisement as appropriate */ 4135 if (adapter->flags2 & FLAG2_HAS_EEE) { 4136 s32 ret_val; 4137 u16 adv_addr; 4138 4139 switch (hw->phy.type) { 4140 case e1000_phy_82579: 4141 adv_addr = I82579_EEE_ADVERTISEMENT; 4142 break; 4143 case e1000_phy_i217: 4144 adv_addr = I217_EEE_ADVERTISEMENT; 4145 break; 4146 default: 4147 dev_err(&adapter->pdev->dev, 4148 "Invalid PHY type setting EEE advertisement\n"); 4149 return; 4150 } 4151 4152 ret_val = hw->phy.ops.acquire(hw); 4153 if (ret_val) { 4154 dev_err(&adapter->pdev->dev, 4155 "EEE advertisement - unable to acquire PHY\n"); 4156 return; 4157 } 4158 4159 e1000_write_emi_reg_locked(hw, adv_addr, 4160 hw->dev_spec.ich8lan.eee_disable ? 4161 0 : adapter->eee_advert); 4162 4163 hw->phy.ops.release(hw); 4164 } 4165 4166 if (!netif_running(adapter->netdev) && 4167 !test_bit(__E1000_TESTING, &adapter->state)) 4168 e1000_power_down_phy(adapter); 4169 4170 e1000_get_phy_info(hw); 4171 4172 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4173 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4174 u16 phy_data = 0; 4175 /* speed up time to link by disabling smart power down, ignore 4176 * the return value of this function because there is nothing 4177 * different we would do if it failed 4178 */ 4179 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4180 phy_data &= ~IGP02E1000_PM_SPD; 4181 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4182 } 4183 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4184 u32 reg; 4185 4186 /* Fextnvm7 @ 0xe4[2] = 1 */ 4187 reg = er32(FEXTNVM7); 4188 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4189 ew32(FEXTNVM7, reg); 4190 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4191 reg = er32(FEXTNVM9); 4192 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4193 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4194 ew32(FEXTNVM9, reg); 4195 } 4196 4197 } 4198 4199 /** 4200 * e1000e_trigger_lsc - trigger an LSC interrupt 4201 * @adapter: 4202 * 4203 * Fire a link status change interrupt to start the watchdog. 4204 **/ 4205 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4206 { 4207 struct e1000_hw *hw = &adapter->hw; 4208 4209 if (adapter->msix_entries) 4210 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4211 else 4212 ew32(ICS, E1000_ICS_LSC); 4213 } 4214 4215 void e1000e_up(struct e1000_adapter *adapter) 4216 { 4217 /* hardware has been reset, we need to reload some things */ 4218 e1000_configure(adapter); 4219 4220 clear_bit(__E1000_DOWN, &adapter->state); 4221 4222 if (adapter->msix_entries) 4223 e1000_configure_msix(adapter); 4224 e1000_irq_enable(adapter); 4225 4226 /* Tx queue started by watchdog timer when link is up */ 4227 4228 e1000e_trigger_lsc(adapter); 4229 } 4230 4231 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4232 { 4233 struct e1000_hw *hw = &adapter->hw; 4234 4235 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4236 return; 4237 4238 /* flush pending descriptor writebacks to memory */ 4239 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4240 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4241 4242 /* execute the writes immediately */ 4243 e1e_flush(); 4244 4245 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4246 * write is successful 4247 */ 4248 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4249 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4250 4251 /* execute the writes immediately */ 4252 e1e_flush(); 4253 } 4254 4255 static void e1000e_update_stats(struct e1000_adapter *adapter); 4256 4257 /** 4258 * e1000e_down - quiesce the device and optionally reset the hardware 4259 * @adapter: board private structure 4260 * @reset: boolean flag to reset the hardware or not 4261 */ 4262 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4263 { 4264 struct net_device *netdev = adapter->netdev; 4265 struct e1000_hw *hw = &adapter->hw; 4266 u32 tctl, rctl; 4267 4268 /* signal that we're down so the interrupt handler does not 4269 * reschedule our watchdog timer 4270 */ 4271 set_bit(__E1000_DOWN, &adapter->state); 4272 4273 netif_carrier_off(netdev); 4274 4275 /* disable receives in the hardware */ 4276 rctl = er32(RCTL); 4277 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4278 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4279 /* flush and sleep below */ 4280 4281 netif_stop_queue(netdev); 4282 4283 /* disable transmits in the hardware */ 4284 tctl = er32(TCTL); 4285 tctl &= ~E1000_TCTL_EN; 4286 ew32(TCTL, tctl); 4287 4288 /* flush both disables and wait for them to finish */ 4289 e1e_flush(); 4290 usleep_range(10000, 11000); 4291 4292 e1000_irq_disable(adapter); 4293 4294 napi_synchronize(&adapter->napi); 4295 4296 del_timer_sync(&adapter->watchdog_timer); 4297 del_timer_sync(&adapter->phy_info_timer); 4298 4299 spin_lock(&adapter->stats64_lock); 4300 e1000e_update_stats(adapter); 4301 spin_unlock(&adapter->stats64_lock); 4302 4303 e1000e_flush_descriptors(adapter); 4304 4305 adapter->link_speed = 0; 4306 adapter->link_duplex = 0; 4307 4308 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4309 if ((hw->mac.type >= e1000_pch2lan) && 4310 (adapter->netdev->mtu > ETH_DATA_LEN) && 4311 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4312 e_dbg("failed to disable jumbo frame workaround mode\n"); 4313 4314 if (!pci_channel_offline(adapter->pdev)) { 4315 if (reset) 4316 e1000e_reset(adapter); 4317 else if (hw->mac.type >= e1000_pch_spt) 4318 e1000_flush_desc_rings(adapter); 4319 } 4320 e1000_clean_tx_ring(adapter->tx_ring); 4321 e1000_clean_rx_ring(adapter->rx_ring); 4322 } 4323 4324 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4325 { 4326 might_sleep(); 4327 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4328 usleep_range(1000, 1100); 4329 e1000e_down(adapter, true); 4330 e1000e_up(adapter); 4331 clear_bit(__E1000_RESETTING, &adapter->state); 4332 } 4333 4334 /** 4335 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4336 * @hw: pointer to the HW structure 4337 * @systim: PHC time value read, sanitized and returned 4338 * @sts: structure to hold system time before and after reading SYSTIML, 4339 * may be NULL 4340 * 4341 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4342 * check to see that the time is incrementing at a reasonable 4343 * rate and is a multiple of incvalue. 4344 **/ 4345 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4346 struct ptp_system_timestamp *sts) 4347 { 4348 u64 time_delta, rem, temp; 4349 u64 systim_next; 4350 u32 incvalue; 4351 int i; 4352 4353 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4354 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4355 /* latch SYSTIMH on read of SYSTIML */ 4356 ptp_read_system_prets(sts); 4357 systim_next = (u64)er32(SYSTIML); 4358 ptp_read_system_postts(sts); 4359 systim_next |= (u64)er32(SYSTIMH) << 32; 4360 4361 time_delta = systim_next - systim; 4362 temp = time_delta; 4363 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4364 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4365 4366 systim = systim_next; 4367 4368 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4369 break; 4370 } 4371 4372 return systim; 4373 } 4374 4375 /** 4376 * e1000e_read_systim - read SYSTIM register 4377 * @adapter: board private structure 4378 * @sts: structure which will contain system time before and after reading 4379 * SYSTIML, may be NULL 4380 **/ 4381 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4382 struct ptp_system_timestamp *sts) 4383 { 4384 struct e1000_hw *hw = &adapter->hw; 4385 u32 systimel, systimel_2, systimeh; 4386 u64 systim; 4387 /* SYSTIMH latching upon SYSTIML read does not work well. 4388 * This means that if SYSTIML overflows after we read it but before 4389 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4390 * will experience a huge non linear increment in the systime value 4391 * to fix that we test for overflow and if true, we re-read systime. 4392 */ 4393 ptp_read_system_prets(sts); 4394 systimel = er32(SYSTIML); 4395 ptp_read_system_postts(sts); 4396 systimeh = er32(SYSTIMH); 4397 /* Is systimel is so large that overflow is possible? */ 4398 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4399 ptp_read_system_prets(sts); 4400 systimel_2 = er32(SYSTIML); 4401 ptp_read_system_postts(sts); 4402 if (systimel > systimel_2) { 4403 /* There was an overflow, read again SYSTIMH, and use 4404 * systimel_2 4405 */ 4406 systimeh = er32(SYSTIMH); 4407 systimel = systimel_2; 4408 } 4409 } 4410 systim = (u64)systimel; 4411 systim |= (u64)systimeh << 32; 4412 4413 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4414 systim = e1000e_sanitize_systim(hw, systim, sts); 4415 4416 return systim; 4417 } 4418 4419 /** 4420 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4421 * @cc: cyclecounter structure 4422 **/ 4423 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4424 { 4425 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4426 cc); 4427 4428 return e1000e_read_systim(adapter, NULL); 4429 } 4430 4431 /** 4432 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4433 * @adapter: board private structure to initialize 4434 * 4435 * e1000_sw_init initializes the Adapter private data structure. 4436 * Fields are initialized based on PCI device information and 4437 * OS network device settings (MTU size). 4438 **/ 4439 static int e1000_sw_init(struct e1000_adapter *adapter) 4440 { 4441 struct net_device *netdev = adapter->netdev; 4442 4443 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4444 adapter->rx_ps_bsize0 = 128; 4445 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4446 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4447 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4448 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4449 4450 spin_lock_init(&adapter->stats64_lock); 4451 4452 e1000e_set_interrupt_capability(adapter); 4453 4454 if (e1000_alloc_queues(adapter)) 4455 return -ENOMEM; 4456 4457 /* Setup hardware time stamping cyclecounter */ 4458 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4459 adapter->cc.read = e1000e_cyclecounter_read; 4460 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4461 adapter->cc.mult = 1; 4462 /* cc.shift set in e1000e_get_base_tininca() */ 4463 4464 spin_lock_init(&adapter->systim_lock); 4465 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4466 } 4467 4468 /* Explicitly disable IRQ since the NIC can be in any state. */ 4469 e1000_irq_disable(adapter); 4470 4471 set_bit(__E1000_DOWN, &adapter->state); 4472 return 0; 4473 } 4474 4475 /** 4476 * e1000_intr_msi_test - Interrupt Handler 4477 * @irq: interrupt number 4478 * @data: pointer to a network interface device structure 4479 **/ 4480 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4481 { 4482 struct net_device *netdev = data; 4483 struct e1000_adapter *adapter = netdev_priv(netdev); 4484 struct e1000_hw *hw = &adapter->hw; 4485 u32 icr = er32(ICR); 4486 4487 e_dbg("icr is %08X\n", icr); 4488 if (icr & E1000_ICR_RXSEQ) { 4489 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4490 /* Force memory writes to complete before acknowledging the 4491 * interrupt is handled. 4492 */ 4493 wmb(); 4494 } 4495 4496 return IRQ_HANDLED; 4497 } 4498 4499 /** 4500 * e1000_test_msi_interrupt - Returns 0 for successful test 4501 * @adapter: board private struct 4502 * 4503 * code flow taken from tg3.c 4504 **/ 4505 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4506 { 4507 struct net_device *netdev = adapter->netdev; 4508 struct e1000_hw *hw = &adapter->hw; 4509 int err; 4510 4511 /* poll_enable hasn't been called yet, so don't need disable */ 4512 /* clear any pending events */ 4513 er32(ICR); 4514 4515 /* free the real vector and request a test handler */ 4516 e1000_free_irq(adapter); 4517 e1000e_reset_interrupt_capability(adapter); 4518 4519 /* Assume that the test fails, if it succeeds then the test 4520 * MSI irq handler will unset this flag 4521 */ 4522 adapter->flags |= FLAG_MSI_TEST_FAILED; 4523 4524 err = pci_enable_msi(adapter->pdev); 4525 if (err) 4526 goto msi_test_failed; 4527 4528 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4529 netdev->name, netdev); 4530 if (err) { 4531 pci_disable_msi(adapter->pdev); 4532 goto msi_test_failed; 4533 } 4534 4535 /* Force memory writes to complete before enabling and firing an 4536 * interrupt. 4537 */ 4538 wmb(); 4539 4540 e1000_irq_enable(adapter); 4541 4542 /* fire an unusual interrupt on the test handler */ 4543 ew32(ICS, E1000_ICS_RXSEQ); 4544 e1e_flush(); 4545 msleep(100); 4546 4547 e1000_irq_disable(adapter); 4548 4549 rmb(); /* read flags after interrupt has been fired */ 4550 4551 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4552 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4553 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4554 } else { 4555 e_dbg("MSI interrupt test succeeded!\n"); 4556 } 4557 4558 free_irq(adapter->pdev->irq, netdev); 4559 pci_disable_msi(adapter->pdev); 4560 4561 msi_test_failed: 4562 e1000e_set_interrupt_capability(adapter); 4563 return e1000_request_irq(adapter); 4564 } 4565 4566 /** 4567 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4568 * @adapter: board private struct 4569 * 4570 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4571 **/ 4572 static int e1000_test_msi(struct e1000_adapter *adapter) 4573 { 4574 int err; 4575 u16 pci_cmd; 4576 4577 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4578 return 0; 4579 4580 /* disable SERR in case the MSI write causes a master abort */ 4581 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4582 if (pci_cmd & PCI_COMMAND_SERR) 4583 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4584 pci_cmd & ~PCI_COMMAND_SERR); 4585 4586 err = e1000_test_msi_interrupt(adapter); 4587 4588 /* re-enable SERR */ 4589 if (pci_cmd & PCI_COMMAND_SERR) { 4590 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4591 pci_cmd |= PCI_COMMAND_SERR; 4592 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4593 } 4594 4595 return err; 4596 } 4597 4598 /** 4599 * e1000e_open - Called when a network interface is made active 4600 * @netdev: network interface device structure 4601 * 4602 * Returns 0 on success, negative value on failure 4603 * 4604 * The open entry point is called when a network interface is made 4605 * active by the system (IFF_UP). At this point all resources needed 4606 * for transmit and receive operations are allocated, the interrupt 4607 * handler is registered with the OS, the watchdog timer is started, 4608 * and the stack is notified that the interface is ready. 4609 **/ 4610 int e1000e_open(struct net_device *netdev) 4611 { 4612 struct e1000_adapter *adapter = netdev_priv(netdev); 4613 struct e1000_hw *hw = &adapter->hw; 4614 struct pci_dev *pdev = adapter->pdev; 4615 int err; 4616 4617 /* disallow open during test */ 4618 if (test_bit(__E1000_TESTING, &adapter->state)) 4619 return -EBUSY; 4620 4621 pm_runtime_get_sync(&pdev->dev); 4622 4623 netif_carrier_off(netdev); 4624 netif_stop_queue(netdev); 4625 4626 /* allocate transmit descriptors */ 4627 err = e1000e_setup_tx_resources(adapter->tx_ring); 4628 if (err) 4629 goto err_setup_tx; 4630 4631 /* allocate receive descriptors */ 4632 err = e1000e_setup_rx_resources(adapter->rx_ring); 4633 if (err) 4634 goto err_setup_rx; 4635 4636 /* If AMT is enabled, let the firmware know that the network 4637 * interface is now open and reset the part to a known state. 4638 */ 4639 if (adapter->flags & FLAG_HAS_AMT) { 4640 e1000e_get_hw_control(adapter); 4641 e1000e_reset(adapter); 4642 } 4643 4644 e1000e_power_up_phy(adapter); 4645 4646 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4647 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4648 e1000_update_mng_vlan(adapter); 4649 4650 /* DMA latency requirement to workaround jumbo issue */ 4651 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE); 4652 4653 /* before we allocate an interrupt, we must be ready to handle it. 4654 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4655 * as soon as we call pci_request_irq, so we have to setup our 4656 * clean_rx handler before we do so. 4657 */ 4658 e1000_configure(adapter); 4659 4660 err = e1000_request_irq(adapter); 4661 if (err) 4662 goto err_req_irq; 4663 4664 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4665 * ignore e1000e MSI messages, which means we need to test our MSI 4666 * interrupt now 4667 */ 4668 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4669 err = e1000_test_msi(adapter); 4670 if (err) { 4671 e_err("Interrupt allocation failed\n"); 4672 goto err_req_irq; 4673 } 4674 } 4675 4676 /* From here on the code is the same as e1000e_up() */ 4677 clear_bit(__E1000_DOWN, &adapter->state); 4678 4679 napi_enable(&adapter->napi); 4680 4681 e1000_irq_enable(adapter); 4682 4683 adapter->tx_hang_recheck = false; 4684 4685 hw->mac.get_link_status = true; 4686 pm_runtime_put(&pdev->dev); 4687 4688 e1000e_trigger_lsc(adapter); 4689 4690 return 0; 4691 4692 err_req_irq: 4693 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4694 e1000e_release_hw_control(adapter); 4695 e1000_power_down_phy(adapter); 4696 e1000e_free_rx_resources(adapter->rx_ring); 4697 err_setup_rx: 4698 e1000e_free_tx_resources(adapter->tx_ring); 4699 err_setup_tx: 4700 e1000e_reset(adapter); 4701 pm_runtime_put_sync(&pdev->dev); 4702 4703 return err; 4704 } 4705 4706 /** 4707 * e1000e_close - Disables a network interface 4708 * @netdev: network interface device structure 4709 * 4710 * Returns 0, this is not allowed to fail 4711 * 4712 * The close entry point is called when an interface is de-activated 4713 * by the OS. The hardware is still under the drivers control, but 4714 * needs to be disabled. A global MAC reset is issued to stop the 4715 * hardware, and all transmit and receive resources are freed. 4716 **/ 4717 int e1000e_close(struct net_device *netdev) 4718 { 4719 struct e1000_adapter *adapter = netdev_priv(netdev); 4720 struct pci_dev *pdev = adapter->pdev; 4721 int count = E1000_CHECK_RESET_COUNT; 4722 4723 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4724 usleep_range(10000, 11000); 4725 4726 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4727 4728 pm_runtime_get_sync(&pdev->dev); 4729 4730 if (netif_device_present(netdev)) { 4731 e1000e_down(adapter, true); 4732 e1000_free_irq(adapter); 4733 4734 /* Link status message must follow this format */ 4735 netdev_info(netdev, "NIC Link is Down\n"); 4736 } 4737 4738 napi_disable(&adapter->napi); 4739 4740 e1000e_free_tx_resources(adapter->tx_ring); 4741 e1000e_free_rx_resources(adapter->rx_ring); 4742 4743 /* kill manageability vlan ID if supported, but not if a vlan with 4744 * the same ID is registered on the host OS (let 8021q kill it) 4745 */ 4746 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4747 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4748 adapter->mng_vlan_id); 4749 4750 /* If AMT is enabled, let the firmware know that the network 4751 * interface is now closed 4752 */ 4753 if ((adapter->flags & FLAG_HAS_AMT) && 4754 !test_bit(__E1000_TESTING, &adapter->state)) 4755 e1000e_release_hw_control(adapter); 4756 4757 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4758 4759 pm_runtime_put_sync(&pdev->dev); 4760 4761 return 0; 4762 } 4763 4764 /** 4765 * e1000_set_mac - Change the Ethernet Address of the NIC 4766 * @netdev: network interface device structure 4767 * @p: pointer to an address structure 4768 * 4769 * Returns 0 on success, negative on failure 4770 **/ 4771 static int e1000_set_mac(struct net_device *netdev, void *p) 4772 { 4773 struct e1000_adapter *adapter = netdev_priv(netdev); 4774 struct e1000_hw *hw = &adapter->hw; 4775 struct sockaddr *addr = p; 4776 4777 if (!is_valid_ether_addr(addr->sa_data)) 4778 return -EADDRNOTAVAIL; 4779 4780 eth_hw_addr_set(netdev, addr->sa_data); 4781 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4782 4783 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4784 4785 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4786 /* activate the work around */ 4787 e1000e_set_laa_state_82571(&adapter->hw, 1); 4788 4789 /* Hold a copy of the LAA in RAR[14] This is done so that 4790 * between the time RAR[0] gets clobbered and the time it 4791 * gets fixed (in e1000_watchdog), the actual LAA is in one 4792 * of the RARs and no incoming packets directed to this port 4793 * are dropped. Eventually the LAA will be in RAR[0] and 4794 * RAR[14] 4795 */ 4796 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4797 adapter->hw.mac.rar_entry_count - 1); 4798 } 4799 4800 return 0; 4801 } 4802 4803 /** 4804 * e1000e_update_phy_task - work thread to update phy 4805 * @work: pointer to our work struct 4806 * 4807 * this worker thread exists because we must acquire a 4808 * semaphore to read the phy, which we could msleep while 4809 * waiting for it, and we can't msleep in a timer. 4810 **/ 4811 static void e1000e_update_phy_task(struct work_struct *work) 4812 { 4813 struct e1000_adapter *adapter = container_of(work, 4814 struct e1000_adapter, 4815 update_phy_task); 4816 struct e1000_hw *hw = &adapter->hw; 4817 4818 if (test_bit(__E1000_DOWN, &adapter->state)) 4819 return; 4820 4821 e1000_get_phy_info(hw); 4822 4823 /* Enable EEE on 82579 after link up */ 4824 if (hw->phy.type >= e1000_phy_82579) 4825 e1000_set_eee_pchlan(hw); 4826 } 4827 4828 /** 4829 * e1000_update_phy_info - timre call-back to update PHY info 4830 * @t: pointer to timer_list containing private info adapter 4831 * 4832 * Need to wait a few seconds after link up to get diagnostic information from 4833 * the phy 4834 **/ 4835 static void e1000_update_phy_info(struct timer_list *t) 4836 { 4837 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4838 4839 if (test_bit(__E1000_DOWN, &adapter->state)) 4840 return; 4841 4842 schedule_work(&adapter->update_phy_task); 4843 } 4844 4845 /** 4846 * e1000e_update_phy_stats - Update the PHY statistics counters 4847 * @adapter: board private structure 4848 * 4849 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4850 **/ 4851 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4852 { 4853 struct e1000_hw *hw = &adapter->hw; 4854 s32 ret_val; 4855 u16 phy_data; 4856 4857 ret_val = hw->phy.ops.acquire(hw); 4858 if (ret_val) 4859 return; 4860 4861 /* A page set is expensive so check if already on desired page. 4862 * If not, set to the page with the PHY status registers. 4863 */ 4864 hw->phy.addr = 1; 4865 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4866 &phy_data); 4867 if (ret_val) 4868 goto release; 4869 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4870 ret_val = hw->phy.ops.set_page(hw, 4871 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4872 if (ret_val) 4873 goto release; 4874 } 4875 4876 /* Single Collision Count */ 4877 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4878 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4879 if (!ret_val) 4880 adapter->stats.scc += phy_data; 4881 4882 /* Excessive Collision Count */ 4883 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4884 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4885 if (!ret_val) 4886 adapter->stats.ecol += phy_data; 4887 4888 /* Multiple Collision Count */ 4889 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4890 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4891 if (!ret_val) 4892 adapter->stats.mcc += phy_data; 4893 4894 /* Late Collision Count */ 4895 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4896 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4897 if (!ret_val) 4898 adapter->stats.latecol += phy_data; 4899 4900 /* Collision Count - also used for adaptive IFS */ 4901 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4902 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4903 if (!ret_val) 4904 hw->mac.collision_delta = phy_data; 4905 4906 /* Defer Count */ 4907 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4908 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4909 if (!ret_val) 4910 adapter->stats.dc += phy_data; 4911 4912 /* Transmit with no CRS */ 4913 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4914 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4915 if (!ret_val) 4916 adapter->stats.tncrs += phy_data; 4917 4918 release: 4919 hw->phy.ops.release(hw); 4920 } 4921 4922 /** 4923 * e1000e_update_stats - Update the board statistics counters 4924 * @adapter: board private structure 4925 **/ 4926 static void e1000e_update_stats(struct e1000_adapter *adapter) 4927 { 4928 struct net_device *netdev = adapter->netdev; 4929 struct e1000_hw *hw = &adapter->hw; 4930 struct pci_dev *pdev = adapter->pdev; 4931 4932 /* Prevent stats update while adapter is being reset, or if the pci 4933 * connection is down. 4934 */ 4935 if (adapter->link_speed == 0) 4936 return; 4937 if (pci_channel_offline(pdev)) 4938 return; 4939 4940 adapter->stats.crcerrs += er32(CRCERRS); 4941 adapter->stats.gprc += er32(GPRC); 4942 adapter->stats.gorc += er32(GORCL); 4943 er32(GORCH); /* Clear gorc */ 4944 adapter->stats.bprc += er32(BPRC); 4945 adapter->stats.mprc += er32(MPRC); 4946 adapter->stats.roc += er32(ROC); 4947 4948 adapter->stats.mpc += er32(MPC); 4949 4950 /* Half-duplex statistics */ 4951 if (adapter->link_duplex == HALF_DUPLEX) { 4952 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4953 e1000e_update_phy_stats(adapter); 4954 } else { 4955 adapter->stats.scc += er32(SCC); 4956 adapter->stats.ecol += er32(ECOL); 4957 adapter->stats.mcc += er32(MCC); 4958 adapter->stats.latecol += er32(LATECOL); 4959 adapter->stats.dc += er32(DC); 4960 4961 hw->mac.collision_delta = er32(COLC); 4962 4963 if ((hw->mac.type != e1000_82574) && 4964 (hw->mac.type != e1000_82583)) 4965 adapter->stats.tncrs += er32(TNCRS); 4966 } 4967 adapter->stats.colc += hw->mac.collision_delta; 4968 } 4969 4970 adapter->stats.xonrxc += er32(XONRXC); 4971 adapter->stats.xontxc += er32(XONTXC); 4972 adapter->stats.xoffrxc += er32(XOFFRXC); 4973 adapter->stats.xofftxc += er32(XOFFTXC); 4974 adapter->stats.gptc += er32(GPTC); 4975 adapter->stats.gotc += er32(GOTCL); 4976 er32(GOTCH); /* Clear gotc */ 4977 adapter->stats.rnbc += er32(RNBC); 4978 adapter->stats.ruc += er32(RUC); 4979 4980 adapter->stats.mptc += er32(MPTC); 4981 adapter->stats.bptc += er32(BPTC); 4982 4983 /* used for adaptive IFS */ 4984 4985 hw->mac.tx_packet_delta = er32(TPT); 4986 adapter->stats.tpt += hw->mac.tx_packet_delta; 4987 4988 adapter->stats.algnerrc += er32(ALGNERRC); 4989 adapter->stats.rxerrc += er32(RXERRC); 4990 adapter->stats.cexterr += er32(CEXTERR); 4991 adapter->stats.tsctc += er32(TSCTC); 4992 adapter->stats.tsctfc += er32(TSCTFC); 4993 4994 /* Fill out the OS statistics structure */ 4995 netdev->stats.multicast = adapter->stats.mprc; 4996 netdev->stats.collisions = adapter->stats.colc; 4997 4998 /* Rx Errors */ 4999 5000 /* RLEC on some newer hardware can be incorrect so build 5001 * our own version based on RUC and ROC 5002 */ 5003 netdev->stats.rx_errors = adapter->stats.rxerrc + 5004 adapter->stats.crcerrs + adapter->stats.algnerrc + 5005 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5006 netdev->stats.rx_length_errors = adapter->stats.ruc + 5007 adapter->stats.roc; 5008 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5009 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5010 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5011 5012 /* Tx Errors */ 5013 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5014 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5015 netdev->stats.tx_window_errors = adapter->stats.latecol; 5016 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5017 5018 /* Tx Dropped needs to be maintained elsewhere */ 5019 5020 /* Management Stats */ 5021 adapter->stats.mgptc += er32(MGTPTC); 5022 adapter->stats.mgprc += er32(MGTPRC); 5023 adapter->stats.mgpdc += er32(MGTPDC); 5024 5025 /* Correctable ECC Errors */ 5026 if (hw->mac.type >= e1000_pch_lpt) { 5027 u32 pbeccsts = er32(PBECCSTS); 5028 5029 adapter->corr_errors += 5030 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5031 adapter->uncorr_errors += 5032 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5033 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5034 } 5035 } 5036 5037 /** 5038 * e1000_phy_read_status - Update the PHY register status snapshot 5039 * @adapter: board private structure 5040 **/ 5041 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5042 { 5043 struct e1000_hw *hw = &adapter->hw; 5044 struct e1000_phy_regs *phy = &adapter->phy_regs; 5045 5046 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5047 (er32(STATUS) & E1000_STATUS_LU) && 5048 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5049 int ret_val; 5050 5051 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5052 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5053 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5054 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5055 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5056 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5057 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5058 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5059 if (ret_val) 5060 e_warn("Error reading PHY register\n"); 5061 } else { 5062 /* Do not read PHY registers if link is not up 5063 * Set values to typical power-on defaults 5064 */ 5065 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5066 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5067 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5068 BMSR_ERCAP); 5069 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5070 ADVERTISE_ALL | ADVERTISE_CSMA); 5071 phy->lpa = 0; 5072 phy->expansion = EXPANSION_ENABLENPAGE; 5073 phy->ctrl1000 = ADVERTISE_1000FULL; 5074 phy->stat1000 = 0; 5075 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5076 } 5077 } 5078 5079 static void e1000_print_link_info(struct e1000_adapter *adapter) 5080 { 5081 struct e1000_hw *hw = &adapter->hw; 5082 u32 ctrl = er32(CTRL); 5083 5084 /* Link status message must follow this format for user tools */ 5085 netdev_info(adapter->netdev, 5086 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5087 adapter->link_speed, 5088 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5089 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5090 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5091 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5092 } 5093 5094 static bool e1000e_has_link(struct e1000_adapter *adapter) 5095 { 5096 struct e1000_hw *hw = &adapter->hw; 5097 bool link_active = false; 5098 s32 ret_val = 0; 5099 5100 /* get_link_status is set on LSC (link status) interrupt or 5101 * Rx sequence error interrupt. get_link_status will stay 5102 * true until the check_for_link establishes link 5103 * for copper adapters ONLY 5104 */ 5105 switch (hw->phy.media_type) { 5106 case e1000_media_type_copper: 5107 if (hw->mac.get_link_status) { 5108 ret_val = hw->mac.ops.check_for_link(hw); 5109 link_active = !hw->mac.get_link_status; 5110 } else { 5111 link_active = true; 5112 } 5113 break; 5114 case e1000_media_type_fiber: 5115 ret_val = hw->mac.ops.check_for_link(hw); 5116 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5117 break; 5118 case e1000_media_type_internal_serdes: 5119 ret_val = hw->mac.ops.check_for_link(hw); 5120 link_active = hw->mac.serdes_has_link; 5121 break; 5122 default: 5123 case e1000_media_type_unknown: 5124 break; 5125 } 5126 5127 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5128 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5129 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5130 e_info("Gigabit has been disabled, downgrading speed\n"); 5131 } 5132 5133 return link_active; 5134 } 5135 5136 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5137 { 5138 /* make sure the receive unit is started */ 5139 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5140 (adapter->flags & FLAG_RESTART_NOW)) { 5141 struct e1000_hw *hw = &adapter->hw; 5142 u32 rctl = er32(RCTL); 5143 5144 ew32(RCTL, rctl | E1000_RCTL_EN); 5145 adapter->flags &= ~FLAG_RESTART_NOW; 5146 } 5147 } 5148 5149 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5150 { 5151 struct e1000_hw *hw = &adapter->hw; 5152 5153 /* With 82574 controllers, PHY needs to be checked periodically 5154 * for hung state and reset, if two calls return true 5155 */ 5156 if (e1000_check_phy_82574(hw)) 5157 adapter->phy_hang_count++; 5158 else 5159 adapter->phy_hang_count = 0; 5160 5161 if (adapter->phy_hang_count > 1) { 5162 adapter->phy_hang_count = 0; 5163 e_dbg("PHY appears hung - resetting\n"); 5164 schedule_work(&adapter->reset_task); 5165 } 5166 } 5167 5168 /** 5169 * e1000_watchdog - Timer Call-back 5170 * @t: pointer to timer_list containing private info adapter 5171 **/ 5172 static void e1000_watchdog(struct timer_list *t) 5173 { 5174 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5175 5176 /* Do the rest outside of interrupt context */ 5177 schedule_work(&adapter->watchdog_task); 5178 5179 /* TODO: make this use queue_delayed_work() */ 5180 } 5181 5182 static void e1000_watchdog_task(struct work_struct *work) 5183 { 5184 struct e1000_adapter *adapter = container_of(work, 5185 struct e1000_adapter, 5186 watchdog_task); 5187 struct net_device *netdev = adapter->netdev; 5188 struct e1000_mac_info *mac = &adapter->hw.mac; 5189 struct e1000_phy_info *phy = &adapter->hw.phy; 5190 struct e1000_ring *tx_ring = adapter->tx_ring; 5191 u32 dmoff_exit_timeout = 100, tries = 0; 5192 struct e1000_hw *hw = &adapter->hw; 5193 u32 link, tctl, pcim_state; 5194 5195 if (test_bit(__E1000_DOWN, &adapter->state)) 5196 return; 5197 5198 link = e1000e_has_link(adapter); 5199 if ((netif_carrier_ok(netdev)) && link) { 5200 /* Cancel scheduled suspend requests. */ 5201 pm_runtime_resume(netdev->dev.parent); 5202 5203 e1000e_enable_receives(adapter); 5204 goto link_up; 5205 } 5206 5207 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5208 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5209 e1000_update_mng_vlan(adapter); 5210 5211 if (link) { 5212 if (!netif_carrier_ok(netdev)) { 5213 bool txb2b = true; 5214 5215 /* Cancel scheduled suspend requests. */ 5216 pm_runtime_resume(netdev->dev.parent); 5217 5218 /* Checking if MAC is in DMoff state*/ 5219 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 5220 pcim_state = er32(STATUS); 5221 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5222 if (tries++ == dmoff_exit_timeout) { 5223 e_dbg("Error in exiting dmoff\n"); 5224 break; 5225 } 5226 usleep_range(10000, 20000); 5227 pcim_state = er32(STATUS); 5228 5229 /* Checking if MAC exited DMoff state */ 5230 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5231 e1000_phy_hw_reset(&adapter->hw); 5232 } 5233 } 5234 5235 /* update snapshot of PHY registers on LSC */ 5236 e1000_phy_read_status(adapter); 5237 mac->ops.get_link_up_info(&adapter->hw, 5238 &adapter->link_speed, 5239 &adapter->link_duplex); 5240 e1000_print_link_info(adapter); 5241 5242 /* check if SmartSpeed worked */ 5243 e1000e_check_downshift(hw); 5244 if (phy->speed_downgraded) 5245 netdev_warn(netdev, 5246 "Link Speed was downgraded by SmartSpeed\n"); 5247 5248 /* On supported PHYs, check for duplex mismatch only 5249 * if link has autonegotiated at 10/100 half 5250 */ 5251 if ((hw->phy.type == e1000_phy_igp_3 || 5252 hw->phy.type == e1000_phy_bm) && 5253 hw->mac.autoneg && 5254 (adapter->link_speed == SPEED_10 || 5255 adapter->link_speed == SPEED_100) && 5256 (adapter->link_duplex == HALF_DUPLEX)) { 5257 u16 autoneg_exp; 5258 5259 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5260 5261 if (!(autoneg_exp & EXPANSION_NWAY)) 5262 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5263 } 5264 5265 /* adjust timeout factor according to speed/duplex */ 5266 adapter->tx_timeout_factor = 1; 5267 switch (adapter->link_speed) { 5268 case SPEED_10: 5269 txb2b = false; 5270 adapter->tx_timeout_factor = 16; 5271 break; 5272 case SPEED_100: 5273 txb2b = false; 5274 adapter->tx_timeout_factor = 10; 5275 break; 5276 } 5277 5278 /* workaround: re-program speed mode bit after 5279 * link-up event 5280 */ 5281 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5282 !txb2b) { 5283 u32 tarc0; 5284 5285 tarc0 = er32(TARC(0)); 5286 tarc0 &= ~SPEED_MODE_BIT; 5287 ew32(TARC(0), tarc0); 5288 } 5289 5290 /* disable TSO for pcie and 10/100 speeds, to avoid 5291 * some hardware issues 5292 */ 5293 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5294 switch (adapter->link_speed) { 5295 case SPEED_10: 5296 case SPEED_100: 5297 e_info("10/100 speed: disabling TSO\n"); 5298 netdev->features &= ~NETIF_F_TSO; 5299 netdev->features &= ~NETIF_F_TSO6; 5300 break; 5301 case SPEED_1000: 5302 netdev->features |= NETIF_F_TSO; 5303 netdev->features |= NETIF_F_TSO6; 5304 break; 5305 default: 5306 /* oops */ 5307 break; 5308 } 5309 if (hw->mac.type == e1000_pch_spt) { 5310 netdev->features &= ~NETIF_F_TSO; 5311 netdev->features &= ~NETIF_F_TSO6; 5312 } 5313 } 5314 5315 /* enable transmits in the hardware, need to do this 5316 * after setting TARC(0) 5317 */ 5318 tctl = er32(TCTL); 5319 tctl |= E1000_TCTL_EN; 5320 ew32(TCTL, tctl); 5321 5322 /* Perform any post-link-up configuration before 5323 * reporting link up. 5324 */ 5325 if (phy->ops.cfg_on_link_up) 5326 phy->ops.cfg_on_link_up(hw); 5327 5328 netif_wake_queue(netdev); 5329 netif_carrier_on(netdev); 5330 5331 if (!test_bit(__E1000_DOWN, &adapter->state)) 5332 mod_timer(&adapter->phy_info_timer, 5333 round_jiffies(jiffies + 2 * HZ)); 5334 } 5335 } else { 5336 if (netif_carrier_ok(netdev)) { 5337 adapter->link_speed = 0; 5338 adapter->link_duplex = 0; 5339 /* Link status message must follow this format */ 5340 netdev_info(netdev, "NIC Link is Down\n"); 5341 netif_carrier_off(netdev); 5342 netif_stop_queue(netdev); 5343 if (!test_bit(__E1000_DOWN, &adapter->state)) 5344 mod_timer(&adapter->phy_info_timer, 5345 round_jiffies(jiffies + 2 * HZ)); 5346 5347 /* 8000ES2LAN requires a Rx packet buffer work-around 5348 * on link down event; reset the controller to flush 5349 * the Rx packet buffer. 5350 */ 5351 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5352 adapter->flags |= FLAG_RESTART_NOW; 5353 else 5354 pm_schedule_suspend(netdev->dev.parent, 5355 LINK_TIMEOUT); 5356 } 5357 } 5358 5359 link_up: 5360 spin_lock(&adapter->stats64_lock); 5361 e1000e_update_stats(adapter); 5362 5363 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5364 adapter->tpt_old = adapter->stats.tpt; 5365 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5366 adapter->colc_old = adapter->stats.colc; 5367 5368 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5369 adapter->gorc_old = adapter->stats.gorc; 5370 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5371 adapter->gotc_old = adapter->stats.gotc; 5372 spin_unlock(&adapter->stats64_lock); 5373 5374 /* If the link is lost the controller stops DMA, but 5375 * if there is queued Tx work it cannot be done. So 5376 * reset the controller to flush the Tx packet buffers. 5377 */ 5378 if (!netif_carrier_ok(netdev) && 5379 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5380 adapter->flags |= FLAG_RESTART_NOW; 5381 5382 /* If reset is necessary, do it outside of interrupt context. */ 5383 if (adapter->flags & FLAG_RESTART_NOW) { 5384 schedule_work(&adapter->reset_task); 5385 /* return immediately since reset is imminent */ 5386 return; 5387 } 5388 5389 e1000e_update_adaptive(&adapter->hw); 5390 5391 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5392 if (adapter->itr_setting == 4) { 5393 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5394 * Total asymmetrical Tx or Rx gets ITR=8000; 5395 * everyone else is between 2000-8000. 5396 */ 5397 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5398 u32 dif = (adapter->gotc > adapter->gorc ? 5399 adapter->gotc - adapter->gorc : 5400 adapter->gorc - adapter->gotc) / 10000; 5401 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5402 5403 e1000e_write_itr(adapter, itr); 5404 } 5405 5406 /* Cause software interrupt to ensure Rx ring is cleaned */ 5407 if (adapter->msix_entries) 5408 ew32(ICS, adapter->rx_ring->ims_val); 5409 else 5410 ew32(ICS, E1000_ICS_RXDMT0); 5411 5412 /* flush pending descriptors to memory before detecting Tx hang */ 5413 e1000e_flush_descriptors(adapter); 5414 5415 /* Force detection of hung controller every watchdog period */ 5416 adapter->detect_tx_hung = true; 5417 5418 /* With 82571 controllers, LAA may be overwritten due to controller 5419 * reset from the other port. Set the appropriate LAA in RAR[0] 5420 */ 5421 if (e1000e_get_laa_state_82571(hw)) 5422 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5423 5424 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5425 e1000e_check_82574_phy_workaround(adapter); 5426 5427 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5428 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5429 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5430 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5431 er32(RXSTMPH); 5432 adapter->rx_hwtstamp_cleared++; 5433 } else { 5434 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5435 } 5436 } 5437 5438 /* Reset the timer */ 5439 if (!test_bit(__E1000_DOWN, &adapter->state)) 5440 mod_timer(&adapter->watchdog_timer, 5441 round_jiffies(jiffies + 2 * HZ)); 5442 } 5443 5444 #define E1000_TX_FLAGS_CSUM 0x00000001 5445 #define E1000_TX_FLAGS_VLAN 0x00000002 5446 #define E1000_TX_FLAGS_TSO 0x00000004 5447 #define E1000_TX_FLAGS_IPV4 0x00000008 5448 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5449 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5450 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5451 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5452 5453 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5454 __be16 protocol) 5455 { 5456 struct e1000_context_desc *context_desc; 5457 struct e1000_buffer *buffer_info; 5458 unsigned int i; 5459 u32 cmd_length = 0; 5460 u16 ipcse = 0, mss; 5461 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5462 int err; 5463 5464 if (!skb_is_gso(skb)) 5465 return 0; 5466 5467 err = skb_cow_head(skb, 0); 5468 if (err < 0) 5469 return err; 5470 5471 hdr_len = skb_tcp_all_headers(skb); 5472 mss = skb_shinfo(skb)->gso_size; 5473 if (protocol == htons(ETH_P_IP)) { 5474 struct iphdr *iph = ip_hdr(skb); 5475 iph->tot_len = 0; 5476 iph->check = 0; 5477 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5478 0, IPPROTO_TCP, 0); 5479 cmd_length = E1000_TXD_CMD_IP; 5480 ipcse = skb_transport_offset(skb) - 1; 5481 } else if (skb_is_gso_v6(skb)) { 5482 tcp_v6_gso_csum_prep(skb); 5483 ipcse = 0; 5484 } 5485 ipcss = skb_network_offset(skb); 5486 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5487 tucss = skb_transport_offset(skb); 5488 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5489 5490 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5491 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5492 5493 i = tx_ring->next_to_use; 5494 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5495 buffer_info = &tx_ring->buffer_info[i]; 5496 5497 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5498 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5499 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5500 context_desc->upper_setup.tcp_fields.tucss = tucss; 5501 context_desc->upper_setup.tcp_fields.tucso = tucso; 5502 context_desc->upper_setup.tcp_fields.tucse = 0; 5503 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5504 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5505 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5506 5507 buffer_info->time_stamp = jiffies; 5508 buffer_info->next_to_watch = i; 5509 5510 i++; 5511 if (i == tx_ring->count) 5512 i = 0; 5513 tx_ring->next_to_use = i; 5514 5515 return 1; 5516 } 5517 5518 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5519 __be16 protocol) 5520 { 5521 struct e1000_adapter *adapter = tx_ring->adapter; 5522 struct e1000_context_desc *context_desc; 5523 struct e1000_buffer *buffer_info; 5524 unsigned int i; 5525 u8 css; 5526 u32 cmd_len = E1000_TXD_CMD_DEXT; 5527 5528 if (skb->ip_summed != CHECKSUM_PARTIAL) 5529 return false; 5530 5531 switch (protocol) { 5532 case cpu_to_be16(ETH_P_IP): 5533 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5534 cmd_len |= E1000_TXD_CMD_TCP; 5535 break; 5536 case cpu_to_be16(ETH_P_IPV6): 5537 /* XXX not handling all IPV6 headers */ 5538 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5539 cmd_len |= E1000_TXD_CMD_TCP; 5540 break; 5541 default: 5542 if (unlikely(net_ratelimit())) 5543 e_warn("checksum_partial proto=%x!\n", 5544 be16_to_cpu(protocol)); 5545 break; 5546 } 5547 5548 css = skb_checksum_start_offset(skb); 5549 5550 i = tx_ring->next_to_use; 5551 buffer_info = &tx_ring->buffer_info[i]; 5552 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5553 5554 context_desc->lower_setup.ip_config = 0; 5555 context_desc->upper_setup.tcp_fields.tucss = css; 5556 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5557 context_desc->upper_setup.tcp_fields.tucse = 0; 5558 context_desc->tcp_seg_setup.data = 0; 5559 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5560 5561 buffer_info->time_stamp = jiffies; 5562 buffer_info->next_to_watch = i; 5563 5564 i++; 5565 if (i == tx_ring->count) 5566 i = 0; 5567 tx_ring->next_to_use = i; 5568 5569 return true; 5570 } 5571 5572 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5573 unsigned int first, unsigned int max_per_txd, 5574 unsigned int nr_frags) 5575 { 5576 struct e1000_adapter *adapter = tx_ring->adapter; 5577 struct pci_dev *pdev = adapter->pdev; 5578 struct e1000_buffer *buffer_info; 5579 unsigned int len = skb_headlen(skb); 5580 unsigned int offset = 0, size, count = 0, i; 5581 unsigned int f, bytecount, segs; 5582 5583 i = tx_ring->next_to_use; 5584 5585 while (len) { 5586 buffer_info = &tx_ring->buffer_info[i]; 5587 size = min(len, max_per_txd); 5588 5589 buffer_info->length = size; 5590 buffer_info->time_stamp = jiffies; 5591 buffer_info->next_to_watch = i; 5592 buffer_info->dma = dma_map_single(&pdev->dev, 5593 skb->data + offset, 5594 size, DMA_TO_DEVICE); 5595 buffer_info->mapped_as_page = false; 5596 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5597 goto dma_error; 5598 5599 len -= size; 5600 offset += size; 5601 count++; 5602 5603 if (len) { 5604 i++; 5605 if (i == tx_ring->count) 5606 i = 0; 5607 } 5608 } 5609 5610 for (f = 0; f < nr_frags; f++) { 5611 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5612 5613 len = skb_frag_size(frag); 5614 offset = 0; 5615 5616 while (len) { 5617 i++; 5618 if (i == tx_ring->count) 5619 i = 0; 5620 5621 buffer_info = &tx_ring->buffer_info[i]; 5622 size = min(len, max_per_txd); 5623 5624 buffer_info->length = size; 5625 buffer_info->time_stamp = jiffies; 5626 buffer_info->next_to_watch = i; 5627 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5628 offset, size, 5629 DMA_TO_DEVICE); 5630 buffer_info->mapped_as_page = true; 5631 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5632 goto dma_error; 5633 5634 len -= size; 5635 offset += size; 5636 count++; 5637 } 5638 } 5639 5640 segs = skb_shinfo(skb)->gso_segs ? : 1; 5641 /* multiply data chunks by size of headers */ 5642 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5643 5644 tx_ring->buffer_info[i].skb = skb; 5645 tx_ring->buffer_info[i].segs = segs; 5646 tx_ring->buffer_info[i].bytecount = bytecount; 5647 tx_ring->buffer_info[first].next_to_watch = i; 5648 5649 return count; 5650 5651 dma_error: 5652 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5653 buffer_info->dma = 0; 5654 if (count) 5655 count--; 5656 5657 while (count--) { 5658 if (i == 0) 5659 i += tx_ring->count; 5660 i--; 5661 buffer_info = &tx_ring->buffer_info[i]; 5662 e1000_put_txbuf(tx_ring, buffer_info, true); 5663 } 5664 5665 return 0; 5666 } 5667 5668 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5669 { 5670 struct e1000_adapter *adapter = tx_ring->adapter; 5671 struct e1000_tx_desc *tx_desc = NULL; 5672 struct e1000_buffer *buffer_info; 5673 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5674 unsigned int i; 5675 5676 if (tx_flags & E1000_TX_FLAGS_TSO) { 5677 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5678 E1000_TXD_CMD_TSE; 5679 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5680 5681 if (tx_flags & E1000_TX_FLAGS_IPV4) 5682 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5683 } 5684 5685 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5686 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5687 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5688 } 5689 5690 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5691 txd_lower |= E1000_TXD_CMD_VLE; 5692 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5693 } 5694 5695 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5696 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5697 5698 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5699 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5700 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5701 } 5702 5703 i = tx_ring->next_to_use; 5704 5705 do { 5706 buffer_info = &tx_ring->buffer_info[i]; 5707 tx_desc = E1000_TX_DESC(*tx_ring, i); 5708 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5709 tx_desc->lower.data = cpu_to_le32(txd_lower | 5710 buffer_info->length); 5711 tx_desc->upper.data = cpu_to_le32(txd_upper); 5712 5713 i++; 5714 if (i == tx_ring->count) 5715 i = 0; 5716 } while (--count > 0); 5717 5718 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5719 5720 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5721 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5722 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5723 5724 /* Force memory writes to complete before letting h/w 5725 * know there are new descriptors to fetch. (Only 5726 * applicable for weak-ordered memory model archs, 5727 * such as IA-64). 5728 */ 5729 wmb(); 5730 5731 tx_ring->next_to_use = i; 5732 } 5733 5734 #define MINIMUM_DHCP_PACKET_SIZE 282 5735 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5736 struct sk_buff *skb) 5737 { 5738 struct e1000_hw *hw = &adapter->hw; 5739 u16 length, offset; 5740 5741 if (skb_vlan_tag_present(skb) && 5742 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5743 (adapter->hw.mng_cookie.status & 5744 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5745 return 0; 5746 5747 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5748 return 0; 5749 5750 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5751 return 0; 5752 5753 { 5754 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5755 struct udphdr *udp; 5756 5757 if (ip->protocol != IPPROTO_UDP) 5758 return 0; 5759 5760 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5761 if (ntohs(udp->dest) != 67) 5762 return 0; 5763 5764 offset = (u8 *)udp + 8 - skb->data; 5765 length = skb->len - offset; 5766 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5767 } 5768 5769 return 0; 5770 } 5771 5772 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5773 { 5774 struct e1000_adapter *adapter = tx_ring->adapter; 5775 5776 netif_stop_queue(adapter->netdev); 5777 /* Herbert's original patch had: 5778 * smp_mb__after_netif_stop_queue(); 5779 * but since that doesn't exist yet, just open code it. 5780 */ 5781 smp_mb(); 5782 5783 /* We need to check again in a case another CPU has just 5784 * made room available. 5785 */ 5786 if (e1000_desc_unused(tx_ring) < size) 5787 return -EBUSY; 5788 5789 /* A reprieve! */ 5790 netif_start_queue(adapter->netdev); 5791 ++adapter->restart_queue; 5792 return 0; 5793 } 5794 5795 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5796 { 5797 BUG_ON(size > tx_ring->count); 5798 5799 if (e1000_desc_unused(tx_ring) >= size) 5800 return 0; 5801 return __e1000_maybe_stop_tx(tx_ring, size); 5802 } 5803 5804 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5805 struct net_device *netdev) 5806 { 5807 struct e1000_adapter *adapter = netdev_priv(netdev); 5808 struct e1000_ring *tx_ring = adapter->tx_ring; 5809 unsigned int first; 5810 unsigned int tx_flags = 0; 5811 unsigned int len = skb_headlen(skb); 5812 unsigned int nr_frags; 5813 unsigned int mss; 5814 int count = 0; 5815 int tso; 5816 unsigned int f; 5817 __be16 protocol = vlan_get_protocol(skb); 5818 5819 if (test_bit(__E1000_DOWN, &adapter->state)) { 5820 dev_kfree_skb_any(skb); 5821 return NETDEV_TX_OK; 5822 } 5823 5824 if (skb->len <= 0) { 5825 dev_kfree_skb_any(skb); 5826 return NETDEV_TX_OK; 5827 } 5828 5829 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5830 * pad skb in order to meet this minimum size requirement 5831 */ 5832 if (skb_put_padto(skb, 17)) 5833 return NETDEV_TX_OK; 5834 5835 mss = skb_shinfo(skb)->gso_size; 5836 if (mss) { 5837 u8 hdr_len; 5838 5839 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5840 * points to just header, pull a few bytes of payload from 5841 * frags into skb->data 5842 */ 5843 hdr_len = skb_tcp_all_headers(skb); 5844 /* we do this workaround for ES2LAN, but it is un-necessary, 5845 * avoiding it could save a lot of cycles 5846 */ 5847 if (skb->data_len && (hdr_len == len)) { 5848 unsigned int pull_size; 5849 5850 pull_size = min_t(unsigned int, 4, skb->data_len); 5851 if (!__pskb_pull_tail(skb, pull_size)) { 5852 e_err("__pskb_pull_tail failed.\n"); 5853 dev_kfree_skb_any(skb); 5854 return NETDEV_TX_OK; 5855 } 5856 len = skb_headlen(skb); 5857 } 5858 } 5859 5860 /* reserve a descriptor for the offload context */ 5861 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5862 count++; 5863 count++; 5864 5865 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5866 5867 nr_frags = skb_shinfo(skb)->nr_frags; 5868 for (f = 0; f < nr_frags; f++) 5869 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5870 adapter->tx_fifo_limit); 5871 5872 if (adapter->hw.mac.tx_pkt_filtering) 5873 e1000_transfer_dhcp_info(adapter, skb); 5874 5875 /* need: count + 2 desc gap to keep tail from touching 5876 * head, otherwise try next time 5877 */ 5878 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5879 return NETDEV_TX_BUSY; 5880 5881 if (skb_vlan_tag_present(skb)) { 5882 tx_flags |= E1000_TX_FLAGS_VLAN; 5883 tx_flags |= (skb_vlan_tag_get(skb) << 5884 E1000_TX_FLAGS_VLAN_SHIFT); 5885 } 5886 5887 first = tx_ring->next_to_use; 5888 5889 tso = e1000_tso(tx_ring, skb, protocol); 5890 if (tso < 0) { 5891 dev_kfree_skb_any(skb); 5892 return NETDEV_TX_OK; 5893 } 5894 5895 if (tso) 5896 tx_flags |= E1000_TX_FLAGS_TSO; 5897 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5898 tx_flags |= E1000_TX_FLAGS_CSUM; 5899 5900 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5901 * 82571 hardware supports TSO capabilities for IPv6 as well... 5902 * no longer assume, we must. 5903 */ 5904 if (protocol == htons(ETH_P_IP)) 5905 tx_flags |= E1000_TX_FLAGS_IPV4; 5906 5907 if (unlikely(skb->no_fcs)) 5908 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5909 5910 /* if count is 0 then mapping error has occurred */ 5911 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5912 nr_frags); 5913 if (count) { 5914 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5915 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5916 if (!adapter->tx_hwtstamp_skb) { 5917 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5918 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5919 adapter->tx_hwtstamp_skb = skb_get(skb); 5920 adapter->tx_hwtstamp_start = jiffies; 5921 schedule_work(&adapter->tx_hwtstamp_work); 5922 } else { 5923 adapter->tx_hwtstamp_skipped++; 5924 } 5925 } 5926 5927 skb_tx_timestamp(skb); 5928 5929 netdev_sent_queue(netdev, skb->len); 5930 e1000_tx_queue(tx_ring, tx_flags, count); 5931 /* Make sure there is space in the ring for the next send. */ 5932 e1000_maybe_stop_tx(tx_ring, 5933 ((MAX_SKB_FRAGS + 1) * 5934 DIV_ROUND_UP(PAGE_SIZE, 5935 adapter->tx_fifo_limit) + 4)); 5936 5937 if (!netdev_xmit_more() || 5938 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5939 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5940 e1000e_update_tdt_wa(tx_ring, 5941 tx_ring->next_to_use); 5942 else 5943 writel(tx_ring->next_to_use, tx_ring->tail); 5944 } 5945 } else { 5946 dev_kfree_skb_any(skb); 5947 tx_ring->buffer_info[first].time_stamp = 0; 5948 tx_ring->next_to_use = first; 5949 } 5950 5951 return NETDEV_TX_OK; 5952 } 5953 5954 /** 5955 * e1000_tx_timeout - Respond to a Tx Hang 5956 * @netdev: network interface device structure 5957 * @txqueue: index of the hung queue (unused) 5958 **/ 5959 static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 5960 { 5961 struct e1000_adapter *adapter = netdev_priv(netdev); 5962 5963 /* Do the reset outside of interrupt context */ 5964 adapter->tx_timeout_count++; 5965 schedule_work(&adapter->reset_task); 5966 } 5967 5968 static void e1000_reset_task(struct work_struct *work) 5969 { 5970 struct e1000_adapter *adapter; 5971 adapter = container_of(work, struct e1000_adapter, reset_task); 5972 5973 rtnl_lock(); 5974 /* don't run the task if already down */ 5975 if (test_bit(__E1000_DOWN, &adapter->state)) { 5976 rtnl_unlock(); 5977 return; 5978 } 5979 5980 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5981 e1000e_dump(adapter); 5982 e_err("Reset adapter unexpectedly\n"); 5983 } 5984 e1000e_reinit_locked(adapter); 5985 rtnl_unlock(); 5986 } 5987 5988 /** 5989 * e1000e_get_stats64 - Get System Network Statistics 5990 * @netdev: network interface device structure 5991 * @stats: rtnl_link_stats64 pointer 5992 * 5993 * Returns the address of the device statistics structure. 5994 **/ 5995 void e1000e_get_stats64(struct net_device *netdev, 5996 struct rtnl_link_stats64 *stats) 5997 { 5998 struct e1000_adapter *adapter = netdev_priv(netdev); 5999 6000 spin_lock(&adapter->stats64_lock); 6001 e1000e_update_stats(adapter); 6002 /* Fill out the OS statistics structure */ 6003 stats->rx_bytes = adapter->stats.gorc; 6004 stats->rx_packets = adapter->stats.gprc; 6005 stats->tx_bytes = adapter->stats.gotc; 6006 stats->tx_packets = adapter->stats.gptc; 6007 stats->multicast = adapter->stats.mprc; 6008 stats->collisions = adapter->stats.colc; 6009 6010 /* Rx Errors */ 6011 6012 /* RLEC on some newer hardware can be incorrect so build 6013 * our own version based on RUC and ROC 6014 */ 6015 stats->rx_errors = adapter->stats.rxerrc + 6016 adapter->stats.crcerrs + adapter->stats.algnerrc + 6017 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 6018 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 6019 stats->rx_crc_errors = adapter->stats.crcerrs; 6020 stats->rx_frame_errors = adapter->stats.algnerrc; 6021 stats->rx_missed_errors = adapter->stats.mpc; 6022 6023 /* Tx Errors */ 6024 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6025 stats->tx_aborted_errors = adapter->stats.ecol; 6026 stats->tx_window_errors = adapter->stats.latecol; 6027 stats->tx_carrier_errors = adapter->stats.tncrs; 6028 6029 /* Tx Dropped needs to be maintained elsewhere */ 6030 6031 spin_unlock(&adapter->stats64_lock); 6032 } 6033 6034 /** 6035 * e1000_change_mtu - Change the Maximum Transfer Unit 6036 * @netdev: network interface device structure 6037 * @new_mtu: new value for maximum frame size 6038 * 6039 * Returns 0 on success, negative on failure 6040 **/ 6041 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6042 { 6043 struct e1000_adapter *adapter = netdev_priv(netdev); 6044 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6045 6046 /* Jumbo frame support */ 6047 if ((new_mtu > ETH_DATA_LEN) && 6048 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6049 e_err("Jumbo Frames not supported.\n"); 6050 return -EINVAL; 6051 } 6052 6053 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6054 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6055 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6056 (new_mtu > ETH_DATA_LEN)) { 6057 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6058 return -EINVAL; 6059 } 6060 6061 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6062 usleep_range(1000, 1100); 6063 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6064 adapter->max_frame_size = max_frame; 6065 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6066 netdev->mtu, new_mtu); 6067 netdev->mtu = new_mtu; 6068 6069 pm_runtime_get_sync(netdev->dev.parent); 6070 6071 if (netif_running(netdev)) 6072 e1000e_down(adapter, true); 6073 6074 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6075 * means we reserve 2 more, this pushes us to allocate from the next 6076 * larger slab size. 6077 * i.e. RXBUFFER_2048 --> size-4096 slab 6078 * However with the new *_jumbo_rx* routines, jumbo receives will use 6079 * fragmented skbs 6080 */ 6081 6082 if (max_frame <= 2048) 6083 adapter->rx_buffer_len = 2048; 6084 else 6085 adapter->rx_buffer_len = 4096; 6086 6087 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6088 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6089 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6090 6091 if (netif_running(netdev)) 6092 e1000e_up(adapter); 6093 else 6094 e1000e_reset(adapter); 6095 6096 pm_runtime_put_sync(netdev->dev.parent); 6097 6098 clear_bit(__E1000_RESETTING, &adapter->state); 6099 6100 return 0; 6101 } 6102 6103 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6104 int cmd) 6105 { 6106 struct e1000_adapter *adapter = netdev_priv(netdev); 6107 struct mii_ioctl_data *data = if_mii(ifr); 6108 6109 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6110 return -EOPNOTSUPP; 6111 6112 switch (cmd) { 6113 case SIOCGMIIPHY: 6114 data->phy_id = adapter->hw.phy.addr; 6115 break; 6116 case SIOCGMIIREG: 6117 e1000_phy_read_status(adapter); 6118 6119 switch (data->reg_num & 0x1F) { 6120 case MII_BMCR: 6121 data->val_out = adapter->phy_regs.bmcr; 6122 break; 6123 case MII_BMSR: 6124 data->val_out = adapter->phy_regs.bmsr; 6125 break; 6126 case MII_PHYSID1: 6127 data->val_out = (adapter->hw.phy.id >> 16); 6128 break; 6129 case MII_PHYSID2: 6130 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6131 break; 6132 case MII_ADVERTISE: 6133 data->val_out = adapter->phy_regs.advertise; 6134 break; 6135 case MII_LPA: 6136 data->val_out = adapter->phy_regs.lpa; 6137 break; 6138 case MII_EXPANSION: 6139 data->val_out = adapter->phy_regs.expansion; 6140 break; 6141 case MII_CTRL1000: 6142 data->val_out = adapter->phy_regs.ctrl1000; 6143 break; 6144 case MII_STAT1000: 6145 data->val_out = adapter->phy_regs.stat1000; 6146 break; 6147 case MII_ESTATUS: 6148 data->val_out = adapter->phy_regs.estatus; 6149 break; 6150 default: 6151 return -EIO; 6152 } 6153 break; 6154 case SIOCSMIIREG: 6155 default: 6156 return -EOPNOTSUPP; 6157 } 6158 return 0; 6159 } 6160 6161 /** 6162 * e1000e_hwtstamp_set - control hardware time stamping 6163 * @netdev: network interface device structure 6164 * @ifr: interface request 6165 * 6166 * Outgoing time stamping can be enabled and disabled. Play nice and 6167 * disable it when requested, although it shouldn't cause any overhead 6168 * when no packet needs it. At most one packet in the queue may be 6169 * marked for time stamping, otherwise it would be impossible to tell 6170 * for sure to which packet the hardware time stamp belongs. 6171 * 6172 * Incoming time stamping has to be configured via the hardware filters. 6173 * Not all combinations are supported, in particular event type has to be 6174 * specified. Matching the kind of event packet is not supported, with the 6175 * exception of "all V2 events regardless of level 2 or 4". 6176 **/ 6177 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6178 { 6179 struct e1000_adapter *adapter = netdev_priv(netdev); 6180 struct hwtstamp_config config; 6181 int ret_val; 6182 6183 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6184 return -EFAULT; 6185 6186 ret_val = e1000e_config_hwtstamp(adapter, &config); 6187 if (ret_val) 6188 return ret_val; 6189 6190 switch (config.rx_filter) { 6191 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6192 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6193 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6194 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6195 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6196 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6197 /* With V2 type filters which specify a Sync or Delay Request, 6198 * Path Delay Request/Response messages are also time stamped 6199 * by hardware so notify the caller the requested packets plus 6200 * some others are time stamped. 6201 */ 6202 config.rx_filter = HWTSTAMP_FILTER_SOME; 6203 break; 6204 default: 6205 break; 6206 } 6207 6208 return copy_to_user(ifr->ifr_data, &config, 6209 sizeof(config)) ? -EFAULT : 0; 6210 } 6211 6212 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6213 { 6214 struct e1000_adapter *adapter = netdev_priv(netdev); 6215 6216 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6217 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6218 } 6219 6220 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6221 { 6222 switch (cmd) { 6223 case SIOCGMIIPHY: 6224 case SIOCGMIIREG: 6225 case SIOCSMIIREG: 6226 return e1000_mii_ioctl(netdev, ifr, cmd); 6227 case SIOCSHWTSTAMP: 6228 return e1000e_hwtstamp_set(netdev, ifr); 6229 case SIOCGHWTSTAMP: 6230 return e1000e_hwtstamp_get(netdev, ifr); 6231 default: 6232 return -EOPNOTSUPP; 6233 } 6234 } 6235 6236 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6237 { 6238 struct e1000_hw *hw = &adapter->hw; 6239 u32 i, mac_reg, wuc; 6240 u16 phy_reg, wuc_enable; 6241 int retval; 6242 6243 /* copy MAC RARs to PHY RARs */ 6244 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6245 6246 retval = hw->phy.ops.acquire(hw); 6247 if (retval) { 6248 e_err("Could not acquire PHY\n"); 6249 return retval; 6250 } 6251 6252 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6253 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6254 if (retval) 6255 goto release; 6256 6257 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6258 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6259 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6260 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6261 (u16)(mac_reg & 0xFFFF)); 6262 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6263 (u16)((mac_reg >> 16) & 0xFFFF)); 6264 } 6265 6266 /* configure PHY Rx Control register */ 6267 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6268 mac_reg = er32(RCTL); 6269 if (mac_reg & E1000_RCTL_UPE) 6270 phy_reg |= BM_RCTL_UPE; 6271 if (mac_reg & E1000_RCTL_MPE) 6272 phy_reg |= BM_RCTL_MPE; 6273 phy_reg &= ~(BM_RCTL_MO_MASK); 6274 if (mac_reg & E1000_RCTL_MO_3) 6275 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6276 << BM_RCTL_MO_SHIFT); 6277 if (mac_reg & E1000_RCTL_BAM) 6278 phy_reg |= BM_RCTL_BAM; 6279 if (mac_reg & E1000_RCTL_PMCF) 6280 phy_reg |= BM_RCTL_PMCF; 6281 mac_reg = er32(CTRL); 6282 if (mac_reg & E1000_CTRL_RFCE) 6283 phy_reg |= BM_RCTL_RFCE; 6284 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6285 6286 wuc = E1000_WUC_PME_EN; 6287 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6288 wuc |= E1000_WUC_APME; 6289 6290 /* enable PHY wakeup in MAC register */ 6291 ew32(WUFC, wufc); 6292 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6293 E1000_WUC_PME_STATUS | wuc)); 6294 6295 /* configure and enable PHY wakeup in PHY registers */ 6296 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6297 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6298 6299 /* activate PHY wakeup */ 6300 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6301 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6302 if (retval) 6303 e_err("Could not set PHY Host Wakeup bit\n"); 6304 release: 6305 hw->phy.ops.release(hw); 6306 6307 return retval; 6308 } 6309 6310 static void e1000e_flush_lpic(struct pci_dev *pdev) 6311 { 6312 struct net_device *netdev = pci_get_drvdata(pdev); 6313 struct e1000_adapter *adapter = netdev_priv(netdev); 6314 struct e1000_hw *hw = &adapter->hw; 6315 u32 ret_val; 6316 6317 pm_runtime_get_sync(netdev->dev.parent); 6318 6319 ret_val = hw->phy.ops.acquire(hw); 6320 if (ret_val) 6321 goto fl_out; 6322 6323 pr_info("EEE TX LPI TIMER: %08X\n", 6324 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6325 6326 hw->phy.ops.release(hw); 6327 6328 fl_out: 6329 pm_runtime_put_sync(netdev->dev.parent); 6330 } 6331 6332 /* S0ix implementation */ 6333 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6334 { 6335 struct e1000_hw *hw = &adapter->hw; 6336 u32 mac_data; 6337 u16 phy_data; 6338 6339 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6340 hw->mac.type >= e1000_pch_adp) { 6341 /* Request ME configure the device for S0ix */ 6342 mac_data = er32(H2ME); 6343 mac_data |= E1000_H2ME_START_DPG; 6344 mac_data &= ~E1000_H2ME_EXIT_DPG; 6345 trace_e1000e_trace_mac_register(mac_data); 6346 ew32(H2ME, mac_data); 6347 } else { 6348 /* Request driver configure the device to S0ix */ 6349 /* Disable the periodic inband message, 6350 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6351 */ 6352 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6353 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6354 phy_data |= BIT(10); 6355 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6356 6357 /* Make sure we don't exit K1 every time a new packet arrives 6358 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6359 */ 6360 e1e_rphy(hw, I217_CGFREG, &phy_data); 6361 phy_data |= BIT(5); 6362 e1e_wphy(hw, I217_CGFREG, phy_data); 6363 6364 /* Change the MAC/PHY interface to SMBus 6365 * Force the SMBus in PHY page769_23[0] = 1 6366 * Force the SMBus in MAC CTRL_EXT[11] = 1 6367 */ 6368 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6369 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6370 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6371 mac_data = er32(CTRL_EXT); 6372 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6373 ew32(CTRL_EXT, mac_data); 6374 6375 /* DFT control: PHY bit: page769_20[0] = 1 6376 * page769_20[7] - PHY PLL stop 6377 * page769_20[8] - PHY go to the electrical idle 6378 * page769_20[9] - PHY serdes disable 6379 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6380 */ 6381 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6382 phy_data |= BIT(0); 6383 phy_data |= BIT(7); 6384 phy_data |= BIT(8); 6385 phy_data |= BIT(9); 6386 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6387 6388 mac_data = er32(EXTCNF_CTRL); 6389 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6390 ew32(EXTCNF_CTRL, mac_data); 6391 6392 /* Enable the Dynamic Power Gating in the MAC */ 6393 mac_data = er32(FEXTNVM7); 6394 mac_data |= BIT(22); 6395 ew32(FEXTNVM7, mac_data); 6396 6397 /* Disable disconnected cable conditioning for Power Gating */ 6398 mac_data = er32(DPGFR); 6399 mac_data |= BIT(2); 6400 ew32(DPGFR, mac_data); 6401 6402 /* Don't wake from dynamic Power Gating with clock request */ 6403 mac_data = er32(FEXTNVM12); 6404 mac_data |= BIT(12); 6405 ew32(FEXTNVM12, mac_data); 6406 6407 /* Ungate PGCB clock */ 6408 mac_data = er32(FEXTNVM9); 6409 mac_data &= ~BIT(28); 6410 ew32(FEXTNVM9, mac_data); 6411 6412 /* Enable K1 off to enable mPHY Power Gating */ 6413 mac_data = er32(FEXTNVM6); 6414 mac_data |= BIT(31); 6415 ew32(FEXTNVM6, mac_data); 6416 6417 /* Enable mPHY power gating for any link and speed */ 6418 mac_data = er32(FEXTNVM8); 6419 mac_data |= BIT(9); 6420 ew32(FEXTNVM8, mac_data); 6421 6422 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6423 mac_data = er32(CTRL_EXT); 6424 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6425 ew32(CTRL_EXT, mac_data); 6426 6427 /* No MAC DPG gating SLP_S0 in modern standby 6428 * Switch the logic of the lanphypc to use PMC counter 6429 */ 6430 mac_data = er32(FEXTNVM5); 6431 mac_data |= BIT(7); 6432 ew32(FEXTNVM5, mac_data); 6433 } 6434 6435 /* Disable the time synchronization clock */ 6436 mac_data = er32(FEXTNVM7); 6437 mac_data |= BIT(31); 6438 mac_data &= ~BIT(0); 6439 ew32(FEXTNVM7, mac_data); 6440 6441 /* Dynamic Power Gating Enable */ 6442 mac_data = er32(CTRL_EXT); 6443 mac_data |= BIT(3); 6444 ew32(CTRL_EXT, mac_data); 6445 6446 /* Check MAC Tx/Rx packet buffer pointers. 6447 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6448 * pending traffic indication that would prevent power gating. 6449 */ 6450 mac_data = er32(TDFH); 6451 if (mac_data) 6452 ew32(TDFH, 0); 6453 mac_data = er32(TDFT); 6454 if (mac_data) 6455 ew32(TDFT, 0); 6456 mac_data = er32(TDFHS); 6457 if (mac_data) 6458 ew32(TDFHS, 0); 6459 mac_data = er32(TDFTS); 6460 if (mac_data) 6461 ew32(TDFTS, 0); 6462 mac_data = er32(TDFPC); 6463 if (mac_data) 6464 ew32(TDFPC, 0); 6465 mac_data = er32(RDFH); 6466 if (mac_data) 6467 ew32(RDFH, 0); 6468 mac_data = er32(RDFT); 6469 if (mac_data) 6470 ew32(RDFT, 0); 6471 mac_data = er32(RDFHS); 6472 if (mac_data) 6473 ew32(RDFHS, 0); 6474 mac_data = er32(RDFTS); 6475 if (mac_data) 6476 ew32(RDFTS, 0); 6477 mac_data = er32(RDFPC); 6478 if (mac_data) 6479 ew32(RDFPC, 0); 6480 } 6481 6482 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6483 { 6484 struct e1000_hw *hw = &adapter->hw; 6485 bool firmware_bug = false; 6486 u32 mac_data; 6487 u16 phy_data; 6488 u32 i = 0; 6489 6490 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6491 hw->mac.type >= e1000_pch_adp) { 6492 /* Keep the GPT clock enabled for CSME */ 6493 mac_data = er32(FEXTNVM); 6494 mac_data |= BIT(3); 6495 ew32(FEXTNVM, mac_data); 6496 /* Request ME unconfigure the device from S0ix */ 6497 mac_data = er32(H2ME); 6498 mac_data &= ~E1000_H2ME_START_DPG; 6499 mac_data |= E1000_H2ME_EXIT_DPG; 6500 trace_e1000e_trace_mac_register(mac_data); 6501 ew32(H2ME, mac_data); 6502 6503 /* Poll up to 2.5 seconds for ME to unconfigure DPG. 6504 * If this takes more than 1 second, show a warning indicating a 6505 * firmware bug 6506 */ 6507 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) { 6508 if (i > 100 && !firmware_bug) 6509 firmware_bug = true; 6510 6511 if (i++ == 250) { 6512 e_dbg("Timeout (firmware bug): %d msec\n", 6513 i * 10); 6514 break; 6515 } 6516 6517 usleep_range(10000, 11000); 6518 } 6519 if (firmware_bug) 6520 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n", 6521 i * 10); 6522 else 6523 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10); 6524 } else { 6525 /* Request driver unconfigure the device from S0ix */ 6526 6527 /* Disable the Dynamic Power Gating in the MAC */ 6528 mac_data = er32(FEXTNVM7); 6529 mac_data &= 0xFFBFFFFF; 6530 ew32(FEXTNVM7, mac_data); 6531 6532 /* Disable mPHY power gating for any link and speed */ 6533 mac_data = er32(FEXTNVM8); 6534 mac_data &= ~BIT(9); 6535 ew32(FEXTNVM8, mac_data); 6536 6537 /* Disable K1 off */ 6538 mac_data = er32(FEXTNVM6); 6539 mac_data &= ~BIT(31); 6540 ew32(FEXTNVM6, mac_data); 6541 6542 /* Disable Ungate PGCB clock */ 6543 mac_data = er32(FEXTNVM9); 6544 mac_data |= BIT(28); 6545 ew32(FEXTNVM9, mac_data); 6546 6547 /* Cancel not waking from dynamic 6548 * Power Gating with clock request 6549 */ 6550 mac_data = er32(FEXTNVM12); 6551 mac_data &= ~BIT(12); 6552 ew32(FEXTNVM12, mac_data); 6553 6554 /* Cancel disable disconnected cable conditioning 6555 * for Power Gating 6556 */ 6557 mac_data = er32(DPGFR); 6558 mac_data &= ~BIT(2); 6559 ew32(DPGFR, mac_data); 6560 6561 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6562 mac_data = er32(CTRL_EXT); 6563 mac_data &= 0xFFF7FFFF; 6564 ew32(CTRL_EXT, mac_data); 6565 6566 /* Revert the lanphypc logic to use the internal Gbe counter 6567 * and not the PMC counter 6568 */ 6569 mac_data = er32(FEXTNVM5); 6570 mac_data &= 0xFFFFFF7F; 6571 ew32(FEXTNVM5, mac_data); 6572 6573 /* Enable the periodic inband message, 6574 * Request PCIe clock in K1 page770_17[10:9] =01b 6575 */ 6576 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6577 phy_data &= 0xFBFF; 6578 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6579 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6580 6581 /* Return back configuration 6582 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6583 */ 6584 e1e_rphy(hw, I217_CGFREG, &phy_data); 6585 phy_data &= 0xFFDF; 6586 e1e_wphy(hw, I217_CGFREG, phy_data); 6587 6588 /* Change the MAC/PHY interface to Kumeran 6589 * Unforce the SMBus in PHY page769_23[0] = 0 6590 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6591 */ 6592 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6593 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6594 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6595 mac_data = er32(CTRL_EXT); 6596 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6597 ew32(CTRL_EXT, mac_data); 6598 } 6599 6600 /* Disable Dynamic Power Gating */ 6601 mac_data = er32(CTRL_EXT); 6602 mac_data &= 0xFFFFFFF7; 6603 ew32(CTRL_EXT, mac_data); 6604 6605 /* Enable the time synchronization clock */ 6606 mac_data = er32(FEXTNVM7); 6607 mac_data &= ~BIT(31); 6608 mac_data |= BIT(0); 6609 ew32(FEXTNVM7, mac_data); 6610 } 6611 6612 static int e1000e_pm_freeze(struct device *dev) 6613 { 6614 struct net_device *netdev = dev_get_drvdata(dev); 6615 struct e1000_adapter *adapter = netdev_priv(netdev); 6616 bool present; 6617 6618 rtnl_lock(); 6619 6620 present = netif_device_present(netdev); 6621 netif_device_detach(netdev); 6622 6623 if (present && netif_running(netdev)) { 6624 int count = E1000_CHECK_RESET_COUNT; 6625 6626 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6627 usleep_range(10000, 11000); 6628 6629 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6630 6631 /* Quiesce the device without resetting the hardware */ 6632 e1000e_down(adapter, false); 6633 e1000_free_irq(adapter); 6634 } 6635 rtnl_unlock(); 6636 6637 e1000e_reset_interrupt_capability(adapter); 6638 6639 /* Allow time for pending master requests to run */ 6640 e1000e_disable_pcie_master(&adapter->hw); 6641 6642 return 0; 6643 } 6644 6645 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6646 { 6647 struct net_device *netdev = pci_get_drvdata(pdev); 6648 struct e1000_adapter *adapter = netdev_priv(netdev); 6649 struct e1000_hw *hw = &adapter->hw; 6650 u32 ctrl, ctrl_ext, rctl, status, wufc; 6651 int retval = 0; 6652 6653 /* Runtime suspend should only enable wakeup for link changes */ 6654 if (runtime) 6655 wufc = E1000_WUFC_LNKC; 6656 else if (device_may_wakeup(&pdev->dev)) 6657 wufc = adapter->wol; 6658 else 6659 wufc = 0; 6660 6661 status = er32(STATUS); 6662 if (status & E1000_STATUS_LU) 6663 wufc &= ~E1000_WUFC_LNKC; 6664 6665 if (wufc) { 6666 e1000_setup_rctl(adapter); 6667 e1000e_set_rx_mode(netdev); 6668 6669 /* turn on all-multi mode if wake on multicast is enabled */ 6670 if (wufc & E1000_WUFC_MC) { 6671 rctl = er32(RCTL); 6672 rctl |= E1000_RCTL_MPE; 6673 ew32(RCTL, rctl); 6674 } 6675 6676 ctrl = er32(CTRL); 6677 ctrl |= E1000_CTRL_ADVD3WUC; 6678 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6679 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6680 ew32(CTRL, ctrl); 6681 6682 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6683 adapter->hw.phy.media_type == 6684 e1000_media_type_internal_serdes) { 6685 /* keep the laser running in D3 */ 6686 ctrl_ext = er32(CTRL_EXT); 6687 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6688 ew32(CTRL_EXT, ctrl_ext); 6689 } 6690 6691 if (!runtime) 6692 e1000e_power_up_phy(adapter); 6693 6694 if (adapter->flags & FLAG_IS_ICH) 6695 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6696 6697 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6698 /* enable wakeup by the PHY */ 6699 retval = e1000_init_phy_wakeup(adapter, wufc); 6700 if (retval) 6701 return retval; 6702 } else { 6703 /* enable wakeup by the MAC */ 6704 ew32(WUFC, wufc); 6705 ew32(WUC, E1000_WUC_PME_EN); 6706 } 6707 } else { 6708 ew32(WUC, 0); 6709 ew32(WUFC, 0); 6710 6711 e1000_power_down_phy(adapter); 6712 } 6713 6714 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6715 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6716 } else if (hw->mac.type >= e1000_pch_lpt) { 6717 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6718 /* ULP does not support wake from unicast, multicast 6719 * or broadcast. 6720 */ 6721 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6722 6723 if (retval) 6724 return retval; 6725 } 6726 6727 /* Ensure that the appropriate bits are set in LPI_CTRL 6728 * for EEE in Sx 6729 */ 6730 if ((hw->phy.type >= e1000_phy_i217) && 6731 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6732 u16 lpi_ctrl = 0; 6733 6734 retval = hw->phy.ops.acquire(hw); 6735 if (!retval) { 6736 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6737 &lpi_ctrl); 6738 if (!retval) { 6739 if (adapter->eee_advert & 6740 hw->dev_spec.ich8lan.eee_lp_ability & 6741 I82579_EEE_100_SUPPORTED) 6742 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6743 if (adapter->eee_advert & 6744 hw->dev_spec.ich8lan.eee_lp_ability & 6745 I82579_EEE_1000_SUPPORTED) 6746 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6747 6748 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6749 lpi_ctrl); 6750 } 6751 } 6752 hw->phy.ops.release(hw); 6753 } 6754 6755 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6756 * would have already happened in close and is redundant. 6757 */ 6758 e1000e_release_hw_control(adapter); 6759 6760 pci_clear_master(pdev); 6761 6762 /* The pci-e switch on some quad port adapters will report a 6763 * correctable error when the MAC transitions from D0 to D3. To 6764 * prevent this we need to mask off the correctable errors on the 6765 * downstream port of the pci-e switch. 6766 * 6767 * We don't have the associated upstream bridge while assigning 6768 * the PCI device into guest. For example, the KVM on power is 6769 * one of the cases. 6770 */ 6771 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6772 struct pci_dev *us_dev = pdev->bus->self; 6773 u16 devctl; 6774 6775 if (!us_dev) 6776 return 0; 6777 6778 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6779 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6780 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6781 6782 pci_save_state(pdev); 6783 pci_prepare_to_sleep(pdev); 6784 6785 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6786 } 6787 6788 return 0; 6789 } 6790 6791 /** 6792 * __e1000e_disable_aspm - Disable ASPM states 6793 * @pdev: pointer to PCI device struct 6794 * @state: bit-mask of ASPM states to disable 6795 * @locked: indication if this context holds pci_bus_sem locked. 6796 * 6797 * Some devices *must* have certain ASPM states disabled per hardware errata. 6798 **/ 6799 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6800 { 6801 struct pci_dev *parent = pdev->bus->self; 6802 u16 aspm_dis_mask = 0; 6803 u16 pdev_aspmc, parent_aspmc; 6804 6805 switch (state) { 6806 case PCIE_LINK_STATE_L0S: 6807 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6808 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6809 fallthrough; /* can't have L1 without L0s */ 6810 case PCIE_LINK_STATE_L1: 6811 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6812 break; 6813 default: 6814 return; 6815 } 6816 6817 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6818 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6819 6820 if (parent) { 6821 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6822 &parent_aspmc); 6823 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6824 } 6825 6826 /* Nothing to do if the ASPM states to be disabled already are */ 6827 if (!(pdev_aspmc & aspm_dis_mask) && 6828 (!parent || !(parent_aspmc & aspm_dis_mask))) 6829 return; 6830 6831 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6832 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6833 "L0s" : "", 6834 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6835 "L1" : ""); 6836 6837 #ifdef CONFIG_PCIEASPM 6838 if (locked) 6839 pci_disable_link_state_locked(pdev, state); 6840 else 6841 pci_disable_link_state(pdev, state); 6842 6843 /* Double-check ASPM control. If not disabled by the above, the 6844 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6845 * not enabled); override by writing PCI config space directly. 6846 */ 6847 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6848 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6849 6850 if (!(aspm_dis_mask & pdev_aspmc)) 6851 return; 6852 #endif 6853 6854 /* Both device and parent should have the same ASPM setting. 6855 * Disable ASPM in downstream component first and then upstream. 6856 */ 6857 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6858 6859 if (parent) 6860 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6861 aspm_dis_mask); 6862 } 6863 6864 /** 6865 * e1000e_disable_aspm - Disable ASPM states. 6866 * @pdev: pointer to PCI device struct 6867 * @state: bit-mask of ASPM states to disable 6868 * 6869 * This function acquires the pci_bus_sem! 6870 * Some devices *must* have certain ASPM states disabled per hardware errata. 6871 **/ 6872 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6873 { 6874 __e1000e_disable_aspm(pdev, state, 0); 6875 } 6876 6877 /** 6878 * e1000e_disable_aspm_locked - Disable ASPM states. 6879 * @pdev: pointer to PCI device struct 6880 * @state: bit-mask of ASPM states to disable 6881 * 6882 * This function must be called with pci_bus_sem acquired! 6883 * Some devices *must* have certain ASPM states disabled per hardware errata. 6884 **/ 6885 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6886 { 6887 __e1000e_disable_aspm(pdev, state, 1); 6888 } 6889 6890 static int e1000e_pm_thaw(struct device *dev) 6891 { 6892 struct net_device *netdev = dev_get_drvdata(dev); 6893 struct e1000_adapter *adapter = netdev_priv(netdev); 6894 int rc = 0; 6895 6896 e1000e_set_interrupt_capability(adapter); 6897 6898 rtnl_lock(); 6899 if (netif_running(netdev)) { 6900 rc = e1000_request_irq(adapter); 6901 if (rc) 6902 goto err_irq; 6903 6904 e1000e_up(adapter); 6905 } 6906 6907 netif_device_attach(netdev); 6908 err_irq: 6909 rtnl_unlock(); 6910 6911 return rc; 6912 } 6913 6914 static int __e1000_resume(struct pci_dev *pdev) 6915 { 6916 struct net_device *netdev = pci_get_drvdata(pdev); 6917 struct e1000_adapter *adapter = netdev_priv(netdev); 6918 struct e1000_hw *hw = &adapter->hw; 6919 u16 aspm_disable_flag = 0; 6920 6921 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6922 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6923 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6924 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6925 if (aspm_disable_flag) 6926 e1000e_disable_aspm(pdev, aspm_disable_flag); 6927 6928 pci_set_master(pdev); 6929 6930 if (hw->mac.type >= e1000_pch2lan) 6931 e1000_resume_workarounds_pchlan(&adapter->hw); 6932 6933 e1000e_power_up_phy(adapter); 6934 6935 /* report the system wakeup cause from S3/S4 */ 6936 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6937 u16 phy_data; 6938 6939 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6940 if (phy_data) { 6941 e_info("PHY Wakeup cause - %s\n", 6942 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6943 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6944 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6945 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6946 phy_data & E1000_WUS_LNKC ? 6947 "Link Status Change" : "other"); 6948 } 6949 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6950 } else { 6951 u32 wus = er32(WUS); 6952 6953 if (wus) { 6954 e_info("MAC Wakeup cause - %s\n", 6955 wus & E1000_WUS_EX ? "Unicast Packet" : 6956 wus & E1000_WUS_MC ? "Multicast Packet" : 6957 wus & E1000_WUS_BC ? "Broadcast Packet" : 6958 wus & E1000_WUS_MAG ? "Magic Packet" : 6959 wus & E1000_WUS_LNKC ? "Link Status Change" : 6960 "other"); 6961 } 6962 ew32(WUS, ~0); 6963 } 6964 6965 e1000e_reset(adapter); 6966 6967 e1000_init_manageability_pt(adapter); 6968 6969 /* If the controller has AMT, do not set DRV_LOAD until the interface 6970 * is up. For all other cases, let the f/w know that the h/w is now 6971 * under the control of the driver. 6972 */ 6973 if (!(adapter->flags & FLAG_HAS_AMT)) 6974 e1000e_get_hw_control(adapter); 6975 6976 return 0; 6977 } 6978 6979 static __maybe_unused int e1000e_pm_prepare(struct device *dev) 6980 { 6981 return pm_runtime_suspended(dev) && 6982 pm_suspend_via_firmware(); 6983 } 6984 6985 static __maybe_unused int e1000e_pm_suspend(struct device *dev) 6986 { 6987 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6988 struct e1000_adapter *adapter = netdev_priv(netdev); 6989 struct pci_dev *pdev = to_pci_dev(dev); 6990 int rc; 6991 6992 e1000e_flush_lpic(pdev); 6993 6994 e1000e_pm_freeze(dev); 6995 6996 rc = __e1000_shutdown(pdev, false); 6997 if (rc) { 6998 e1000e_pm_thaw(dev); 6999 } else { 7000 /* Introduce S0ix implementation */ 7001 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 7002 e1000e_s0ix_entry_flow(adapter); 7003 } 7004 7005 return rc; 7006 } 7007 7008 static __maybe_unused int e1000e_pm_resume(struct device *dev) 7009 { 7010 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 7011 struct e1000_adapter *adapter = netdev_priv(netdev); 7012 struct pci_dev *pdev = to_pci_dev(dev); 7013 int rc; 7014 7015 /* Introduce S0ix implementation */ 7016 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 7017 e1000e_s0ix_exit_flow(adapter); 7018 7019 rc = __e1000_resume(pdev); 7020 if (rc) 7021 return rc; 7022 7023 return e1000e_pm_thaw(dev); 7024 } 7025 7026 static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev) 7027 { 7028 struct net_device *netdev = dev_get_drvdata(dev); 7029 struct e1000_adapter *adapter = netdev_priv(netdev); 7030 u16 eee_lp; 7031 7032 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 7033 7034 if (!e1000e_has_link(adapter)) { 7035 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 7036 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 7037 } 7038 7039 return -EBUSY; 7040 } 7041 7042 static __maybe_unused int e1000e_pm_runtime_resume(struct device *dev) 7043 { 7044 struct pci_dev *pdev = to_pci_dev(dev); 7045 struct net_device *netdev = pci_get_drvdata(pdev); 7046 struct e1000_adapter *adapter = netdev_priv(netdev); 7047 int rc; 7048 7049 rc = __e1000_resume(pdev); 7050 if (rc) 7051 return rc; 7052 7053 if (netdev->flags & IFF_UP) 7054 e1000e_up(adapter); 7055 7056 return rc; 7057 } 7058 7059 static __maybe_unused int e1000e_pm_runtime_suspend(struct device *dev) 7060 { 7061 struct pci_dev *pdev = to_pci_dev(dev); 7062 struct net_device *netdev = pci_get_drvdata(pdev); 7063 struct e1000_adapter *adapter = netdev_priv(netdev); 7064 7065 if (netdev->flags & IFF_UP) { 7066 int count = E1000_CHECK_RESET_COUNT; 7067 7068 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 7069 usleep_range(10000, 11000); 7070 7071 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 7072 7073 /* Down the device without resetting the hardware */ 7074 e1000e_down(adapter, false); 7075 } 7076 7077 if (__e1000_shutdown(pdev, true)) { 7078 e1000e_pm_runtime_resume(dev); 7079 return -EBUSY; 7080 } 7081 7082 return 0; 7083 } 7084 7085 static void e1000_shutdown(struct pci_dev *pdev) 7086 { 7087 e1000e_flush_lpic(pdev); 7088 7089 e1000e_pm_freeze(&pdev->dev); 7090 7091 __e1000_shutdown(pdev, false); 7092 } 7093 7094 #ifdef CONFIG_NET_POLL_CONTROLLER 7095 7096 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 7097 { 7098 struct net_device *netdev = data; 7099 struct e1000_adapter *adapter = netdev_priv(netdev); 7100 7101 if (adapter->msix_entries) { 7102 int vector, msix_irq; 7103 7104 vector = 0; 7105 msix_irq = adapter->msix_entries[vector].vector; 7106 if (disable_hardirq(msix_irq)) 7107 e1000_intr_msix_rx(msix_irq, netdev); 7108 enable_irq(msix_irq); 7109 7110 vector++; 7111 msix_irq = adapter->msix_entries[vector].vector; 7112 if (disable_hardirq(msix_irq)) 7113 e1000_intr_msix_tx(msix_irq, netdev); 7114 enable_irq(msix_irq); 7115 7116 vector++; 7117 msix_irq = adapter->msix_entries[vector].vector; 7118 if (disable_hardirq(msix_irq)) 7119 e1000_msix_other(msix_irq, netdev); 7120 enable_irq(msix_irq); 7121 } 7122 7123 return IRQ_HANDLED; 7124 } 7125 7126 /** 7127 * e1000_netpoll 7128 * @netdev: network interface device structure 7129 * 7130 * Polling 'interrupt' - used by things like netconsole to send skbs 7131 * without having to re-enable interrupts. It's not called while 7132 * the interrupt routine is executing. 7133 */ 7134 static void e1000_netpoll(struct net_device *netdev) 7135 { 7136 struct e1000_adapter *adapter = netdev_priv(netdev); 7137 7138 switch (adapter->int_mode) { 7139 case E1000E_INT_MODE_MSIX: 7140 e1000_intr_msix(adapter->pdev->irq, netdev); 7141 break; 7142 case E1000E_INT_MODE_MSI: 7143 if (disable_hardirq(adapter->pdev->irq)) 7144 e1000_intr_msi(adapter->pdev->irq, netdev); 7145 enable_irq(adapter->pdev->irq); 7146 break; 7147 default: /* E1000E_INT_MODE_LEGACY */ 7148 if (disable_hardirq(adapter->pdev->irq)) 7149 e1000_intr(adapter->pdev->irq, netdev); 7150 enable_irq(adapter->pdev->irq); 7151 break; 7152 } 7153 } 7154 #endif 7155 7156 /** 7157 * e1000_io_error_detected - called when PCI error is detected 7158 * @pdev: Pointer to PCI device 7159 * @state: The current pci connection state 7160 * 7161 * This function is called after a PCI bus error affecting 7162 * this device has been detected. 7163 */ 7164 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7165 pci_channel_state_t state) 7166 { 7167 e1000e_pm_freeze(&pdev->dev); 7168 7169 if (state == pci_channel_io_perm_failure) 7170 return PCI_ERS_RESULT_DISCONNECT; 7171 7172 pci_disable_device(pdev); 7173 7174 /* Request a slot reset. */ 7175 return PCI_ERS_RESULT_NEED_RESET; 7176 } 7177 7178 /** 7179 * e1000_io_slot_reset - called after the pci bus has been reset. 7180 * @pdev: Pointer to PCI device 7181 * 7182 * Restart the card from scratch, as if from a cold-boot. Implementation 7183 * resembles the first-half of the e1000e_pm_resume routine. 7184 */ 7185 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7186 { 7187 struct net_device *netdev = pci_get_drvdata(pdev); 7188 struct e1000_adapter *adapter = netdev_priv(netdev); 7189 struct e1000_hw *hw = &adapter->hw; 7190 u16 aspm_disable_flag = 0; 7191 int err; 7192 pci_ers_result_t result; 7193 7194 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7195 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7196 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7197 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7198 if (aspm_disable_flag) 7199 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7200 7201 err = pci_enable_device_mem(pdev); 7202 if (err) { 7203 dev_err(&pdev->dev, 7204 "Cannot re-enable PCI device after reset.\n"); 7205 result = PCI_ERS_RESULT_DISCONNECT; 7206 } else { 7207 pdev->state_saved = true; 7208 pci_restore_state(pdev); 7209 pci_set_master(pdev); 7210 7211 pci_enable_wake(pdev, PCI_D3hot, 0); 7212 pci_enable_wake(pdev, PCI_D3cold, 0); 7213 7214 e1000e_reset(adapter); 7215 ew32(WUS, ~0); 7216 result = PCI_ERS_RESULT_RECOVERED; 7217 } 7218 7219 return result; 7220 } 7221 7222 /** 7223 * e1000_io_resume - called when traffic can start flowing again. 7224 * @pdev: Pointer to PCI device 7225 * 7226 * This callback is called when the error recovery driver tells us that 7227 * its OK to resume normal operation. Implementation resembles the 7228 * second-half of the e1000e_pm_resume routine. 7229 */ 7230 static void e1000_io_resume(struct pci_dev *pdev) 7231 { 7232 struct net_device *netdev = pci_get_drvdata(pdev); 7233 struct e1000_adapter *adapter = netdev_priv(netdev); 7234 7235 e1000_init_manageability_pt(adapter); 7236 7237 e1000e_pm_thaw(&pdev->dev); 7238 7239 /* If the controller has AMT, do not set DRV_LOAD until the interface 7240 * is up. For all other cases, let the f/w know that the h/w is now 7241 * under the control of the driver. 7242 */ 7243 if (!(adapter->flags & FLAG_HAS_AMT)) 7244 e1000e_get_hw_control(adapter); 7245 } 7246 7247 static void e1000_print_device_info(struct e1000_adapter *adapter) 7248 { 7249 struct e1000_hw *hw = &adapter->hw; 7250 struct net_device *netdev = adapter->netdev; 7251 u32 ret_val; 7252 u8 pba_str[E1000_PBANUM_LENGTH]; 7253 7254 /* print bus type/speed/width info */ 7255 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7256 /* bus width */ 7257 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7258 "Width x1"), 7259 /* MAC address */ 7260 netdev->dev_addr); 7261 e_info("Intel(R) PRO/%s Network Connection\n", 7262 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7263 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7264 E1000_PBANUM_LENGTH); 7265 if (ret_val) 7266 strscpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7267 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7268 hw->mac.type, hw->phy.type, pba_str); 7269 } 7270 7271 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7272 { 7273 struct e1000_hw *hw = &adapter->hw; 7274 int ret_val; 7275 u16 buf = 0; 7276 7277 if (hw->mac.type != e1000_82573) 7278 return; 7279 7280 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7281 le16_to_cpus(&buf); 7282 if (!ret_val && (!(buf & BIT(0)))) { 7283 /* Deep Smart Power Down (DSPD) */ 7284 dev_warn(&adapter->pdev->dev, 7285 "Warning: detected DSPD enabled in EEPROM\n"); 7286 } 7287 } 7288 7289 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7290 netdev_features_t features) 7291 { 7292 struct e1000_adapter *adapter = netdev_priv(netdev); 7293 struct e1000_hw *hw = &adapter->hw; 7294 7295 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7296 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7297 features &= ~NETIF_F_RXFCS; 7298 7299 /* Since there is no support for separate Rx/Tx vlan accel 7300 * enable/disable make sure Tx flag is always in same state as Rx. 7301 */ 7302 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7303 features |= NETIF_F_HW_VLAN_CTAG_TX; 7304 else 7305 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7306 7307 return features; 7308 } 7309 7310 static int e1000_set_features(struct net_device *netdev, 7311 netdev_features_t features) 7312 { 7313 struct e1000_adapter *adapter = netdev_priv(netdev); 7314 netdev_features_t changed = features ^ netdev->features; 7315 7316 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7317 adapter->flags |= FLAG_TSO_FORCE; 7318 7319 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7320 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7321 NETIF_F_RXALL))) 7322 return 0; 7323 7324 if (changed & NETIF_F_RXFCS) { 7325 if (features & NETIF_F_RXFCS) { 7326 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7327 } else { 7328 /* We need to take it back to defaults, which might mean 7329 * stripping is still disabled at the adapter level. 7330 */ 7331 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7332 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7333 else 7334 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7335 } 7336 } 7337 7338 netdev->features = features; 7339 7340 if (netif_running(netdev)) 7341 e1000e_reinit_locked(adapter); 7342 else 7343 e1000e_reset(adapter); 7344 7345 return 1; 7346 } 7347 7348 static const struct net_device_ops e1000e_netdev_ops = { 7349 .ndo_open = e1000e_open, 7350 .ndo_stop = e1000e_close, 7351 .ndo_start_xmit = e1000_xmit_frame, 7352 .ndo_get_stats64 = e1000e_get_stats64, 7353 .ndo_set_rx_mode = e1000e_set_rx_mode, 7354 .ndo_set_mac_address = e1000_set_mac, 7355 .ndo_change_mtu = e1000_change_mtu, 7356 .ndo_eth_ioctl = e1000_ioctl, 7357 .ndo_tx_timeout = e1000_tx_timeout, 7358 .ndo_validate_addr = eth_validate_addr, 7359 7360 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7361 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7362 #ifdef CONFIG_NET_POLL_CONTROLLER 7363 .ndo_poll_controller = e1000_netpoll, 7364 #endif 7365 .ndo_set_features = e1000_set_features, 7366 .ndo_fix_features = e1000_fix_features, 7367 .ndo_features_check = passthru_features_check, 7368 }; 7369 7370 /** 7371 * e1000_probe - Device Initialization Routine 7372 * @pdev: PCI device information struct 7373 * @ent: entry in e1000_pci_tbl 7374 * 7375 * Returns 0 on success, negative on failure 7376 * 7377 * e1000_probe initializes an adapter identified by a pci_dev structure. 7378 * The OS initialization, configuring of the adapter private structure, 7379 * and a hardware reset occur. 7380 **/ 7381 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7382 { 7383 struct net_device *netdev; 7384 struct e1000_adapter *adapter; 7385 struct e1000_hw *hw; 7386 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7387 resource_size_t mmio_start, mmio_len; 7388 resource_size_t flash_start, flash_len; 7389 static int cards_found; 7390 u16 aspm_disable_flag = 0; 7391 u16 eeprom_data = 0; 7392 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7393 int bars, i, err; 7394 s32 ret_val = 0; 7395 7396 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7397 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7398 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7399 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7400 if (aspm_disable_flag) 7401 e1000e_disable_aspm(pdev, aspm_disable_flag); 7402 7403 err = pci_enable_device_mem(pdev); 7404 if (err) 7405 return err; 7406 7407 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7408 if (err) { 7409 dev_err(&pdev->dev, 7410 "No usable DMA configuration, aborting\n"); 7411 goto err_dma; 7412 } 7413 7414 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7415 err = pci_request_selected_regions_exclusive(pdev, bars, 7416 e1000e_driver_name); 7417 if (err) 7418 goto err_pci_reg; 7419 7420 pci_set_master(pdev); 7421 /* PCI config space info */ 7422 err = pci_save_state(pdev); 7423 if (err) 7424 goto err_alloc_etherdev; 7425 7426 err = -ENOMEM; 7427 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7428 if (!netdev) 7429 goto err_alloc_etherdev; 7430 7431 SET_NETDEV_DEV(netdev, &pdev->dev); 7432 7433 netdev->irq = pdev->irq; 7434 7435 pci_set_drvdata(pdev, netdev); 7436 adapter = netdev_priv(netdev); 7437 hw = &adapter->hw; 7438 adapter->netdev = netdev; 7439 adapter->pdev = pdev; 7440 adapter->ei = ei; 7441 adapter->pba = ei->pba; 7442 adapter->flags = ei->flags; 7443 adapter->flags2 = ei->flags2; 7444 adapter->hw.adapter = adapter; 7445 adapter->hw.mac.type = ei->mac; 7446 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7447 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7448 7449 mmio_start = pci_resource_start(pdev, 0); 7450 mmio_len = pci_resource_len(pdev, 0); 7451 7452 err = -EIO; 7453 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7454 if (!adapter->hw.hw_addr) 7455 goto err_ioremap; 7456 7457 if ((adapter->flags & FLAG_HAS_FLASH) && 7458 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7459 (hw->mac.type < e1000_pch_spt)) { 7460 flash_start = pci_resource_start(pdev, 1); 7461 flash_len = pci_resource_len(pdev, 1); 7462 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7463 if (!adapter->hw.flash_address) 7464 goto err_flashmap; 7465 } 7466 7467 /* Set default EEE advertisement */ 7468 if (adapter->flags2 & FLAG2_HAS_EEE) 7469 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7470 7471 /* construct the net_device struct */ 7472 netdev->netdev_ops = &e1000e_netdev_ops; 7473 e1000e_set_ethtool_ops(netdev); 7474 netdev->watchdog_timeo = 5 * HZ; 7475 netif_napi_add(netdev, &adapter->napi, e1000e_poll); 7476 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7477 7478 netdev->mem_start = mmio_start; 7479 netdev->mem_end = mmio_start + mmio_len; 7480 7481 adapter->bd_number = cards_found++; 7482 7483 e1000e_check_options(adapter); 7484 7485 /* setup adapter struct */ 7486 err = e1000_sw_init(adapter); 7487 if (err) 7488 goto err_sw_init; 7489 7490 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7491 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7492 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7493 7494 err = ei->get_variants(adapter); 7495 if (err) 7496 goto err_hw_init; 7497 7498 if ((adapter->flags & FLAG_IS_ICH) && 7499 (adapter->flags & FLAG_READ_ONLY_NVM) && 7500 (hw->mac.type < e1000_pch_spt)) 7501 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7502 7503 hw->mac.ops.get_bus_info(&adapter->hw); 7504 7505 adapter->hw.phy.autoneg_wait_to_complete = 0; 7506 7507 /* Copper options */ 7508 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7509 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7510 adapter->hw.phy.disable_polarity_correction = 0; 7511 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7512 } 7513 7514 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7515 dev_info(&pdev->dev, 7516 "PHY reset is blocked due to SOL/IDER session.\n"); 7517 7518 /* Set initial default active device features */ 7519 netdev->features = (NETIF_F_SG | 7520 NETIF_F_HW_VLAN_CTAG_RX | 7521 NETIF_F_HW_VLAN_CTAG_TX | 7522 NETIF_F_TSO | 7523 NETIF_F_TSO6 | 7524 NETIF_F_RXHASH | 7525 NETIF_F_RXCSUM | 7526 NETIF_F_HW_CSUM); 7527 7528 /* Set user-changeable features (subset of all device features) */ 7529 netdev->hw_features = netdev->features; 7530 netdev->hw_features |= NETIF_F_RXFCS; 7531 netdev->priv_flags |= IFF_SUPP_NOFCS; 7532 netdev->hw_features |= NETIF_F_RXALL; 7533 7534 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7535 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7536 7537 netdev->vlan_features |= (NETIF_F_SG | 7538 NETIF_F_TSO | 7539 NETIF_F_TSO6 | 7540 NETIF_F_HW_CSUM); 7541 7542 netdev->priv_flags |= IFF_UNICAST_FLT; 7543 7544 netdev->features |= NETIF_F_HIGHDMA; 7545 netdev->vlan_features |= NETIF_F_HIGHDMA; 7546 7547 /* MTU range: 68 - max_hw_frame_size */ 7548 netdev->min_mtu = ETH_MIN_MTU; 7549 netdev->max_mtu = adapter->max_hw_frame_size - 7550 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7551 7552 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7553 adapter->flags |= FLAG_MNG_PT_ENABLED; 7554 7555 /* before reading the NVM, reset the controller to 7556 * put the device in a known good starting state 7557 */ 7558 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7559 7560 /* systems with ASPM and others may see the checksum fail on the first 7561 * attempt. Let's give it a few tries 7562 */ 7563 for (i = 0;; i++) { 7564 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7565 break; 7566 if (i == 2) { 7567 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7568 err = -EIO; 7569 goto err_eeprom; 7570 } 7571 } 7572 7573 e1000_eeprom_checks(adapter); 7574 7575 /* copy the MAC address */ 7576 if (e1000e_read_mac_addr(&adapter->hw)) 7577 dev_err(&pdev->dev, 7578 "NVM Read Error while reading MAC address\n"); 7579 7580 eth_hw_addr_set(netdev, adapter->hw.mac.addr); 7581 7582 if (!is_valid_ether_addr(netdev->dev_addr)) { 7583 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7584 netdev->dev_addr); 7585 err = -EIO; 7586 goto err_eeprom; 7587 } 7588 7589 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7590 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7591 7592 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7593 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7594 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7595 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7596 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7597 7598 /* Initialize link parameters. User can change them with ethtool */ 7599 adapter->hw.mac.autoneg = 1; 7600 adapter->fc_autoneg = true; 7601 adapter->hw.fc.requested_mode = e1000_fc_default; 7602 adapter->hw.fc.current_mode = e1000_fc_default; 7603 adapter->hw.phy.autoneg_advertised = 0x2f; 7604 7605 /* Initial Wake on LAN setting - If APM wake is enabled in 7606 * the EEPROM, enable the ACPI Magic Packet filter 7607 */ 7608 if (adapter->flags & FLAG_APME_IN_WUC) { 7609 /* APME bit in EEPROM is mapped to WUC.APME */ 7610 eeprom_data = er32(WUC); 7611 eeprom_apme_mask = E1000_WUC_APME; 7612 if ((hw->mac.type > e1000_ich10lan) && 7613 (eeprom_data & E1000_WUC_PHY_WAKE)) 7614 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7615 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7616 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7617 (adapter->hw.bus.func == 1)) 7618 ret_val = e1000_read_nvm(&adapter->hw, 7619 NVM_INIT_CONTROL3_PORT_B, 7620 1, &eeprom_data); 7621 else 7622 ret_val = e1000_read_nvm(&adapter->hw, 7623 NVM_INIT_CONTROL3_PORT_A, 7624 1, &eeprom_data); 7625 } 7626 7627 /* fetch WoL from EEPROM */ 7628 if (ret_val) 7629 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7630 else if (eeprom_data & eeprom_apme_mask) 7631 adapter->eeprom_wol |= E1000_WUFC_MAG; 7632 7633 /* now that we have the eeprom settings, apply the special cases 7634 * where the eeprom may be wrong or the board simply won't support 7635 * wake on lan on a particular port 7636 */ 7637 if (!(adapter->flags & FLAG_HAS_WOL)) 7638 adapter->eeprom_wol = 0; 7639 7640 /* initialize the wol settings based on the eeprom settings */ 7641 adapter->wol = adapter->eeprom_wol; 7642 7643 /* make sure adapter isn't asleep if manageability is enabled */ 7644 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7645 (hw->mac.ops.check_mng_mode(hw))) 7646 device_wakeup_enable(&pdev->dev); 7647 7648 /* save off EEPROM version number */ 7649 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7650 7651 if (ret_val) { 7652 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7653 adapter->eeprom_vers = 0; 7654 } 7655 7656 /* init PTP hardware clock */ 7657 e1000e_ptp_init(adapter); 7658 7659 /* reset the hardware with the new settings */ 7660 e1000e_reset(adapter); 7661 7662 /* If the controller has AMT, do not set DRV_LOAD until the interface 7663 * is up. For all other cases, let the f/w know that the h/w is now 7664 * under the control of the driver. 7665 */ 7666 if (!(adapter->flags & FLAG_HAS_AMT)) 7667 e1000e_get_hw_control(adapter); 7668 7669 if (hw->mac.type >= e1000_pch_cnp) 7670 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS; 7671 7672 strscpy(netdev->name, "eth%d", sizeof(netdev->name)); 7673 err = register_netdev(netdev); 7674 if (err) 7675 goto err_register; 7676 7677 /* carrier off reporting is important to ethtool even BEFORE open */ 7678 netif_carrier_off(netdev); 7679 7680 e1000_print_device_info(adapter); 7681 7682 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE); 7683 7684 if (pci_dev_run_wake(pdev) && hw->mac.type != e1000_pch_cnp) 7685 pm_runtime_put_noidle(&pdev->dev); 7686 7687 return 0; 7688 7689 err_register: 7690 if (!(adapter->flags & FLAG_HAS_AMT)) 7691 e1000e_release_hw_control(adapter); 7692 err_eeprom: 7693 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7694 e1000_phy_hw_reset(&adapter->hw); 7695 err_hw_init: 7696 kfree(adapter->tx_ring); 7697 kfree(adapter->rx_ring); 7698 err_sw_init: 7699 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7700 iounmap(adapter->hw.flash_address); 7701 e1000e_reset_interrupt_capability(adapter); 7702 err_flashmap: 7703 iounmap(adapter->hw.hw_addr); 7704 err_ioremap: 7705 free_netdev(netdev); 7706 err_alloc_etherdev: 7707 pci_release_mem_regions(pdev); 7708 err_pci_reg: 7709 err_dma: 7710 pci_disable_device(pdev); 7711 return err; 7712 } 7713 7714 /** 7715 * e1000_remove - Device Removal Routine 7716 * @pdev: PCI device information struct 7717 * 7718 * e1000_remove is called by the PCI subsystem to alert the driver 7719 * that it should release a PCI device. This could be caused by a 7720 * Hot-Plug event, or because the driver is going to be removed from 7721 * memory. 7722 **/ 7723 static void e1000_remove(struct pci_dev *pdev) 7724 { 7725 struct net_device *netdev = pci_get_drvdata(pdev); 7726 struct e1000_adapter *adapter = netdev_priv(netdev); 7727 7728 e1000e_ptp_remove(adapter); 7729 7730 /* The timers may be rescheduled, so explicitly disable them 7731 * from being rescheduled. 7732 */ 7733 set_bit(__E1000_DOWN, &adapter->state); 7734 del_timer_sync(&adapter->watchdog_timer); 7735 del_timer_sync(&adapter->phy_info_timer); 7736 7737 cancel_work_sync(&adapter->reset_task); 7738 cancel_work_sync(&adapter->watchdog_task); 7739 cancel_work_sync(&adapter->downshift_task); 7740 cancel_work_sync(&adapter->update_phy_task); 7741 cancel_work_sync(&adapter->print_hang_task); 7742 7743 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7744 cancel_work_sync(&adapter->tx_hwtstamp_work); 7745 if (adapter->tx_hwtstamp_skb) { 7746 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7747 adapter->tx_hwtstamp_skb = NULL; 7748 } 7749 } 7750 7751 unregister_netdev(netdev); 7752 7753 if (pci_dev_run_wake(pdev)) 7754 pm_runtime_get_noresume(&pdev->dev); 7755 7756 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7757 * would have already happened in close and is redundant. 7758 */ 7759 e1000e_release_hw_control(adapter); 7760 7761 e1000e_reset_interrupt_capability(adapter); 7762 kfree(adapter->tx_ring); 7763 kfree(adapter->rx_ring); 7764 7765 iounmap(adapter->hw.hw_addr); 7766 if ((adapter->hw.flash_address) && 7767 (adapter->hw.mac.type < e1000_pch_spt)) 7768 iounmap(adapter->hw.flash_address); 7769 pci_release_mem_regions(pdev); 7770 7771 free_netdev(netdev); 7772 7773 pci_disable_device(pdev); 7774 } 7775 7776 /* PCI Error Recovery (ERS) */ 7777 static const struct pci_error_handlers e1000_err_handler = { 7778 .error_detected = e1000_io_error_detected, 7779 .slot_reset = e1000_io_slot_reset, 7780 .resume = e1000_io_resume, 7781 }; 7782 7783 static const struct pci_device_id e1000_pci_tbl[] = { 7784 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7785 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7786 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7787 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7788 board_82571 }, 7789 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7790 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7791 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7792 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7793 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7794 7795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7796 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7798 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7799 7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7803 7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7807 7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7809 board_80003es2lan }, 7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7811 board_80003es2lan }, 7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7813 board_80003es2lan }, 7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7815 board_80003es2lan }, 7816 7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7825 7826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7835 7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7839 7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7843 7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7848 7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7851 7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7868 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp }, 7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp }, 7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp }, 7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, 7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, 7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, 7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp }, 7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp }, 7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp }, 7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp }, 7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp }, 7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp }, 7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp }, 7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp }, 7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp }, 7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp }, 7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp }, 7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp }, 7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp }, 7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp }, 7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_mtp }, 7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_mtp }, 7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_mtp }, 7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_mtp }, 7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_mtp }, 7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp }, 7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp }, 7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp }, 7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp }, 7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp }, 7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp }, 7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp }, 7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp }, 7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp }, 7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp }, 7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp }, 7913 7914 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7915 }; 7916 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7917 7918 static const struct dev_pm_ops e1000_pm_ops = { 7919 #ifdef CONFIG_PM_SLEEP 7920 .prepare = e1000e_pm_prepare, 7921 .suspend = e1000e_pm_suspend, 7922 .resume = e1000e_pm_resume, 7923 .freeze = e1000e_pm_freeze, 7924 .thaw = e1000e_pm_thaw, 7925 .poweroff = e1000e_pm_suspend, 7926 .restore = e1000e_pm_resume, 7927 #endif 7928 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7929 e1000e_pm_runtime_idle) 7930 }; 7931 7932 /* PCI Device API Driver */ 7933 static struct pci_driver e1000_driver = { 7934 .name = e1000e_driver_name, 7935 .id_table = e1000_pci_tbl, 7936 .probe = e1000_probe, 7937 .remove = e1000_remove, 7938 .driver = { 7939 .pm = &e1000_pm_ops, 7940 }, 7941 .shutdown = e1000_shutdown, 7942 .err_handler = &e1000_err_handler 7943 }; 7944 7945 /** 7946 * e1000_init_module - Driver Registration Routine 7947 * 7948 * e1000_init_module is the first routine called when the driver is 7949 * loaded. All it does is register with the PCI subsystem. 7950 **/ 7951 static int __init e1000_init_module(void) 7952 { 7953 pr_info("Intel(R) PRO/1000 Network Driver\n"); 7954 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7955 7956 return pci_register_driver(&e1000_driver); 7957 } 7958 module_init(e1000_init_module); 7959 7960 /** 7961 * e1000_exit_module - Driver Exit Cleanup Routine 7962 * 7963 * e1000_exit_module is called just before the driver is removed 7964 * from memory. 7965 **/ 7966 static void __exit e1000_exit_module(void) 7967 { 7968 pci_unregister_driver(&e1000_driver); 7969 } 7970 module_exit(e1000_exit_module); 7971 7972 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7973 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7974 MODULE_LICENSE("GPL v2"); 7975 7976 /* netdev.c */ 7977