1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/prefetch.h> 27 #include <linux/suspend.h> 28 29 #include "e1000.h" 30 #define CREATE_TRACE_POINTS 31 #include "e1000e_trace.h" 32 33 char e1000e_driver_name[] = "e1000e"; 34 35 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 36 static int debug = -1; 37 module_param(debug, int, 0); 38 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 39 40 static const struct e1000_info *e1000_info_tbl[] = { 41 [board_82571] = &e1000_82571_info, 42 [board_82572] = &e1000_82572_info, 43 [board_82573] = &e1000_82573_info, 44 [board_82574] = &e1000_82574_info, 45 [board_82583] = &e1000_82583_info, 46 [board_80003es2lan] = &e1000_es2_info, 47 [board_ich8lan] = &e1000_ich8_info, 48 [board_ich9lan] = &e1000_ich9_info, 49 [board_ich10lan] = &e1000_ich10_info, 50 [board_pchlan] = &e1000_pch_info, 51 [board_pch2lan] = &e1000_pch2_info, 52 [board_pch_lpt] = &e1000_pch_lpt_info, 53 [board_pch_spt] = &e1000_pch_spt_info, 54 [board_pch_cnp] = &e1000_pch_cnp_info, 55 [board_pch_tgp] = &e1000_pch_tgp_info, 56 [board_pch_adp] = &e1000_pch_adp_info, 57 [board_pch_mtp] = &e1000_pch_mtp_info, 58 }; 59 60 struct e1000_reg_info { 61 u32 ofs; 62 char *name; 63 }; 64 65 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 66 /* General Registers */ 67 {E1000_CTRL, "CTRL"}, 68 {E1000_STATUS, "STATUS"}, 69 {E1000_CTRL_EXT, "CTRL_EXT"}, 70 71 /* Interrupt Registers */ 72 {E1000_ICR, "ICR"}, 73 74 /* Rx Registers */ 75 {E1000_RCTL, "RCTL"}, 76 {E1000_RDLEN(0), "RDLEN"}, 77 {E1000_RDH(0), "RDH"}, 78 {E1000_RDT(0), "RDT"}, 79 {E1000_RDTR, "RDTR"}, 80 {E1000_RXDCTL(0), "RXDCTL"}, 81 {E1000_ERT, "ERT"}, 82 {E1000_RDBAL(0), "RDBAL"}, 83 {E1000_RDBAH(0), "RDBAH"}, 84 {E1000_RDFH, "RDFH"}, 85 {E1000_RDFT, "RDFT"}, 86 {E1000_RDFHS, "RDFHS"}, 87 {E1000_RDFTS, "RDFTS"}, 88 {E1000_RDFPC, "RDFPC"}, 89 90 /* Tx Registers */ 91 {E1000_TCTL, "TCTL"}, 92 {E1000_TDBAL(0), "TDBAL"}, 93 {E1000_TDBAH(0), "TDBAH"}, 94 {E1000_TDLEN(0), "TDLEN"}, 95 {E1000_TDH(0), "TDH"}, 96 {E1000_TDT(0), "TDT"}, 97 {E1000_TIDV, "TIDV"}, 98 {E1000_TXDCTL(0), "TXDCTL"}, 99 {E1000_TADV, "TADV"}, 100 {E1000_TARC(0), "TARC"}, 101 {E1000_TDFH, "TDFH"}, 102 {E1000_TDFT, "TDFT"}, 103 {E1000_TDFHS, "TDFHS"}, 104 {E1000_TDFTS, "TDFTS"}, 105 {E1000_TDFPC, "TDFPC"}, 106 107 /* List Terminator */ 108 {0, NULL} 109 }; 110 111 /** 112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 113 * @hw: pointer to the HW structure 114 * 115 * When updating the MAC CSR registers, the Manageability Engine (ME) could 116 * be accessing the registers at the same time. Normally, this is handled in 117 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 118 * accesses later than it should which could result in the register to have 119 * an incorrect value. Workaround this by checking the FWSM register which 120 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 121 * and try again a number of times. 122 **/ 123 static void __ew32_prepare(struct e1000_hw *hw) 124 { 125 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 126 127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 128 udelay(50); 129 } 130 131 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 132 { 133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 134 __ew32_prepare(hw); 135 136 writel(val, hw->hw_addr + reg); 137 } 138 139 /** 140 * e1000_regdump - register printout routine 141 * @hw: pointer to the HW structure 142 * @reginfo: pointer to the register info table 143 **/ 144 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 145 { 146 int n = 0; 147 char rname[16]; 148 u32 regs[8]; 149 150 switch (reginfo->ofs) { 151 case E1000_RXDCTL(0): 152 for (n = 0; n < 2; n++) 153 regs[n] = __er32(hw, E1000_RXDCTL(n)); 154 break; 155 case E1000_TXDCTL(0): 156 for (n = 0; n < 2; n++) 157 regs[n] = __er32(hw, E1000_TXDCTL(n)); 158 break; 159 case E1000_TARC(0): 160 for (n = 0; n < 2; n++) 161 regs[n] = __er32(hw, E1000_TARC(n)); 162 break; 163 default: 164 pr_info("%-15s %08x\n", 165 reginfo->name, __er32(hw, reginfo->ofs)); 166 return; 167 } 168 169 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 170 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 171 } 172 173 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 174 struct e1000_buffer *bi) 175 { 176 int i; 177 struct e1000_ps_page *ps_page; 178 179 for (i = 0; i < adapter->rx_ps_pages; i++) { 180 ps_page = &bi->ps_pages[i]; 181 182 if (ps_page->page) { 183 pr_info("packet dump for ps_page %d:\n", i); 184 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 185 16, 1, page_address(ps_page->page), 186 PAGE_SIZE, true); 187 } 188 } 189 } 190 191 /** 192 * e1000e_dump - Print registers, Tx-ring and Rx-ring 193 * @adapter: board private structure 194 **/ 195 static void e1000e_dump(struct e1000_adapter *adapter) 196 { 197 struct net_device *netdev = adapter->netdev; 198 struct e1000_hw *hw = &adapter->hw; 199 struct e1000_reg_info *reginfo; 200 struct e1000_ring *tx_ring = adapter->tx_ring; 201 struct e1000_tx_desc *tx_desc; 202 struct my_u0 { 203 __le64 a; 204 __le64 b; 205 } *u0; 206 struct e1000_buffer *buffer_info; 207 struct e1000_ring *rx_ring = adapter->rx_ring; 208 union e1000_rx_desc_packet_split *rx_desc_ps; 209 union e1000_rx_desc_extended *rx_desc; 210 struct my_u1 { 211 __le64 a; 212 __le64 b; 213 __le64 c; 214 __le64 d; 215 } *u1; 216 u32 staterr; 217 int i = 0; 218 219 if (!netif_msg_hw(adapter)) 220 return; 221 222 /* Print netdevice Info */ 223 if (netdev) { 224 dev_info(&adapter->pdev->dev, "Net device Info\n"); 225 pr_info("Device Name state trans_start\n"); 226 pr_info("%-15s %016lX %016lX\n", netdev->name, 227 netdev->state, dev_trans_start(netdev)); 228 } 229 230 /* Print Registers */ 231 dev_info(&adapter->pdev->dev, "Register Dump\n"); 232 pr_info(" Register Name Value\n"); 233 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 234 reginfo->name; reginfo++) { 235 e1000_regdump(hw, reginfo); 236 } 237 238 /* Print Tx Ring Summary */ 239 if (!netdev || !netif_running(netdev)) 240 return; 241 242 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 243 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 244 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 245 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 246 0, tx_ring->next_to_use, tx_ring->next_to_clean, 247 (unsigned long long)buffer_info->dma, 248 buffer_info->length, 249 buffer_info->next_to_watch, 250 (unsigned long long)buffer_info->time_stamp); 251 252 /* Print Tx Ring */ 253 if (!netif_msg_tx_done(adapter)) 254 goto rx_ring_summary; 255 256 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 257 258 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 259 * 260 * Legacy Transmit Descriptor 261 * +--------------------------------------------------------------+ 262 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 263 * +--------------------------------------------------------------+ 264 * 8 | Special | CSS | Status | CMD | CSO | Length | 265 * +--------------------------------------------------------------+ 266 * 63 48 47 36 35 32 31 24 23 16 15 0 267 * 268 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 269 * 63 48 47 40 39 32 31 16 15 8 7 0 270 * +----------------------------------------------------------------+ 271 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 272 * +----------------------------------------------------------------+ 273 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 274 * +----------------------------------------------------------------+ 275 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 276 * 277 * Extended Data Descriptor (DTYP=0x1) 278 * +----------------------------------------------------------------+ 279 * 0 | Buffer Address [63:0] | 280 * +----------------------------------------------------------------+ 281 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 282 * +----------------------------------------------------------------+ 283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 284 */ 285 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 286 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 287 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 288 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 289 const char *next_desc; 290 tx_desc = E1000_TX_DESC(*tx_ring, i); 291 buffer_info = &tx_ring->buffer_info[i]; 292 u0 = (struct my_u0 *)tx_desc; 293 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 294 next_desc = " NTC/U"; 295 else if (i == tx_ring->next_to_use) 296 next_desc = " NTU"; 297 else if (i == tx_ring->next_to_clean) 298 next_desc = " NTC"; 299 else 300 next_desc = ""; 301 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 302 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 303 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 304 i, 305 (unsigned long long)le64_to_cpu(u0->a), 306 (unsigned long long)le64_to_cpu(u0->b), 307 (unsigned long long)buffer_info->dma, 308 buffer_info->length, buffer_info->next_to_watch, 309 (unsigned long long)buffer_info->time_stamp, 310 buffer_info->skb, next_desc); 311 312 if (netif_msg_pktdata(adapter) && buffer_info->skb) 313 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 314 16, 1, buffer_info->skb->data, 315 buffer_info->skb->len, true); 316 } 317 318 /* Print Rx Ring Summary */ 319 rx_ring_summary: 320 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 321 pr_info("Queue [NTU] [NTC]\n"); 322 pr_info(" %5d %5X %5X\n", 323 0, rx_ring->next_to_use, rx_ring->next_to_clean); 324 325 /* Print Rx Ring */ 326 if (!netif_msg_rx_status(adapter)) 327 return; 328 329 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 330 switch (adapter->rx_ps_pages) { 331 case 1: 332 case 2: 333 case 3: 334 /* [Extended] Packet Split Receive Descriptor Format 335 * 336 * +-----------------------------------------------------+ 337 * 0 | Buffer Address 0 [63:0] | 338 * +-----------------------------------------------------+ 339 * 8 | Buffer Address 1 [63:0] | 340 * +-----------------------------------------------------+ 341 * 16 | Buffer Address 2 [63:0] | 342 * +-----------------------------------------------------+ 343 * 24 | Buffer Address 3 [63:0] | 344 * +-----------------------------------------------------+ 345 */ 346 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 347 /* [Extended] Receive Descriptor (Write-Back) Format 348 * 349 * 63 48 47 32 31 13 12 8 7 4 3 0 350 * +------------------------------------------------------+ 351 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 352 * | Checksum | Ident | | Queue | | Type | 353 * +------------------------------------------------------+ 354 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 355 * +------------------------------------------------------+ 356 * 63 48 47 32 31 20 19 0 357 */ 358 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 359 for (i = 0; i < rx_ring->count; i++) { 360 const char *next_desc; 361 buffer_info = &rx_ring->buffer_info[i]; 362 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 363 u1 = (struct my_u1 *)rx_desc_ps; 364 staterr = 365 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 366 367 if (i == rx_ring->next_to_use) 368 next_desc = " NTU"; 369 else if (i == rx_ring->next_to_clean) 370 next_desc = " NTC"; 371 else 372 next_desc = ""; 373 374 if (staterr & E1000_RXD_STAT_DD) { 375 /* Descriptor Done */ 376 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 377 "RWB", i, 378 (unsigned long long)le64_to_cpu(u1->a), 379 (unsigned long long)le64_to_cpu(u1->b), 380 (unsigned long long)le64_to_cpu(u1->c), 381 (unsigned long long)le64_to_cpu(u1->d), 382 buffer_info->skb, next_desc); 383 } else { 384 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 385 "R ", i, 386 (unsigned long long)le64_to_cpu(u1->a), 387 (unsigned long long)le64_to_cpu(u1->b), 388 (unsigned long long)le64_to_cpu(u1->c), 389 (unsigned long long)le64_to_cpu(u1->d), 390 (unsigned long long)buffer_info->dma, 391 buffer_info->skb, next_desc); 392 393 if (netif_msg_pktdata(adapter)) 394 e1000e_dump_ps_pages(adapter, 395 buffer_info); 396 } 397 } 398 break; 399 default: 400 case 0: 401 /* Extended Receive Descriptor (Read) Format 402 * 403 * +-----------------------------------------------------+ 404 * 0 | Buffer Address [63:0] | 405 * +-----------------------------------------------------+ 406 * 8 | Reserved | 407 * +-----------------------------------------------------+ 408 */ 409 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 410 /* Extended Receive Descriptor (Write-Back) Format 411 * 412 * 63 48 47 32 31 24 23 4 3 0 413 * +------------------------------------------------------+ 414 * | RSS Hash | | | | 415 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 416 * | Packet | IP | | | Type | 417 * | Checksum | Ident | | | | 418 * +------------------------------------------------------+ 419 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 420 * +------------------------------------------------------+ 421 * 63 48 47 32 31 20 19 0 422 */ 423 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 424 425 for (i = 0; i < rx_ring->count; i++) { 426 const char *next_desc; 427 428 buffer_info = &rx_ring->buffer_info[i]; 429 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 430 u1 = (struct my_u1 *)rx_desc; 431 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 432 433 if (i == rx_ring->next_to_use) 434 next_desc = " NTU"; 435 else if (i == rx_ring->next_to_clean) 436 next_desc = " NTC"; 437 else 438 next_desc = ""; 439 440 if (staterr & E1000_RXD_STAT_DD) { 441 /* Descriptor Done */ 442 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 443 "RWB", i, 444 (unsigned long long)le64_to_cpu(u1->a), 445 (unsigned long long)le64_to_cpu(u1->b), 446 buffer_info->skb, next_desc); 447 } else { 448 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 449 "R ", i, 450 (unsigned long long)le64_to_cpu(u1->a), 451 (unsigned long long)le64_to_cpu(u1->b), 452 (unsigned long long)buffer_info->dma, 453 buffer_info->skb, next_desc); 454 455 if (netif_msg_pktdata(adapter) && 456 buffer_info->skb) 457 print_hex_dump(KERN_INFO, "", 458 DUMP_PREFIX_ADDRESS, 16, 459 1, 460 buffer_info->skb->data, 461 adapter->rx_buffer_len, 462 true); 463 } 464 } 465 } 466 } 467 468 /** 469 * e1000_desc_unused - calculate if we have unused descriptors 470 * @ring: pointer to ring struct to perform calculation on 471 **/ 472 static int e1000_desc_unused(struct e1000_ring *ring) 473 { 474 if (ring->next_to_clean > ring->next_to_use) 475 return ring->next_to_clean - ring->next_to_use - 1; 476 477 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 478 } 479 480 /** 481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 482 * @adapter: board private structure 483 * @hwtstamps: time stamp structure to update 484 * @systim: unsigned 64bit system time value. 485 * 486 * Convert the system time value stored in the RX/TXSTMP registers into a 487 * hwtstamp which can be used by the upper level time stamping functions. 488 * 489 * The 'systim_lock' spinlock is used to protect the consistency of the 490 * system time value. This is needed because reading the 64 bit time 491 * value involves reading two 32 bit registers. The first read latches the 492 * value. 493 **/ 494 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 495 struct skb_shared_hwtstamps *hwtstamps, 496 u64 systim) 497 { 498 u64 ns; 499 unsigned long flags; 500 501 spin_lock_irqsave(&adapter->systim_lock, flags); 502 ns = timecounter_cyc2time(&adapter->tc, systim); 503 spin_unlock_irqrestore(&adapter->systim_lock, flags); 504 505 memset(hwtstamps, 0, sizeof(*hwtstamps)); 506 hwtstamps->hwtstamp = ns_to_ktime(ns); 507 } 508 509 /** 510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 511 * @adapter: board private structure 512 * @status: descriptor extended error and status field 513 * @skb: particular skb to include time stamp 514 * 515 * If the time stamp is valid, convert it into the timecounter ns value 516 * and store that result into the shhwtstamps structure which is passed 517 * up the network stack. 518 **/ 519 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 520 struct sk_buff *skb) 521 { 522 struct e1000_hw *hw = &adapter->hw; 523 u64 rxstmp; 524 525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 526 !(status & E1000_RXDEXT_STATERR_TST) || 527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 528 return; 529 530 /* The Rx time stamp registers contain the time stamp. No other 531 * received packet will be time stamped until the Rx time stamp 532 * registers are read. Because only one packet can be time stamped 533 * at a time, the register values must belong to this packet and 534 * therefore none of the other additional attributes need to be 535 * compared. 536 */ 537 rxstmp = (u64)er32(RXSTMPL); 538 rxstmp |= (u64)er32(RXSTMPH) << 32; 539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 540 541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 542 } 543 544 /** 545 * e1000_receive_skb - helper function to handle Rx indications 546 * @adapter: board private structure 547 * @netdev: pointer to netdev struct 548 * @staterr: descriptor extended error and status field as written by hardware 549 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 550 * @skb: pointer to sk_buff to be indicated to stack 551 **/ 552 static void e1000_receive_skb(struct e1000_adapter *adapter, 553 struct net_device *netdev, struct sk_buff *skb, 554 u32 staterr, __le16 vlan) 555 { 556 u16 tag = le16_to_cpu(vlan); 557 558 e1000e_rx_hwtstamp(adapter, staterr, skb); 559 560 skb->protocol = eth_type_trans(skb, netdev); 561 562 if (staterr & E1000_RXD_STAT_VP) 563 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 564 565 napi_gro_receive(&adapter->napi, skb); 566 } 567 568 /** 569 * e1000_rx_checksum - Receive Checksum Offload 570 * @adapter: board private structure 571 * @status_err: receive descriptor status and error fields 572 * @skb: socket buffer with received data 573 **/ 574 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 575 struct sk_buff *skb) 576 { 577 u16 status = (u16)status_err; 578 u8 errors = (u8)(status_err >> 24); 579 580 skb_checksum_none_assert(skb); 581 582 /* Rx checksum disabled */ 583 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 584 return; 585 586 /* Ignore Checksum bit is set */ 587 if (status & E1000_RXD_STAT_IXSM) 588 return; 589 590 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 592 /* let the stack verify checksum errors */ 593 adapter->hw_csum_err++; 594 return; 595 } 596 597 /* TCP/UDP Checksum has not been calculated */ 598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 599 return; 600 601 /* It must be a TCP or UDP packet with a valid checksum */ 602 skb->ip_summed = CHECKSUM_UNNECESSARY; 603 adapter->hw_csum_good++; 604 } 605 606 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 607 { 608 struct e1000_adapter *adapter = rx_ring->adapter; 609 struct e1000_hw *hw = &adapter->hw; 610 611 __ew32_prepare(hw); 612 writel(i, rx_ring->tail); 613 614 if (unlikely(i != readl(rx_ring->tail))) { 615 u32 rctl = er32(RCTL); 616 617 ew32(RCTL, rctl & ~E1000_RCTL_EN); 618 e_err("ME firmware caused invalid RDT - resetting\n"); 619 schedule_work(&adapter->reset_task); 620 } 621 } 622 623 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 624 { 625 struct e1000_adapter *adapter = tx_ring->adapter; 626 struct e1000_hw *hw = &adapter->hw; 627 628 __ew32_prepare(hw); 629 writel(i, tx_ring->tail); 630 631 if (unlikely(i != readl(tx_ring->tail))) { 632 u32 tctl = er32(TCTL); 633 634 ew32(TCTL, tctl & ~E1000_TCTL_EN); 635 e_err("ME firmware caused invalid TDT - resetting\n"); 636 schedule_work(&adapter->reset_task); 637 } 638 } 639 640 /** 641 * e1000_alloc_rx_buffers - Replace used receive buffers 642 * @rx_ring: Rx descriptor ring 643 * @cleaned_count: number to reallocate 644 * @gfp: flags for allocation 645 **/ 646 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 647 int cleaned_count, gfp_t gfp) 648 { 649 struct e1000_adapter *adapter = rx_ring->adapter; 650 struct net_device *netdev = adapter->netdev; 651 struct pci_dev *pdev = adapter->pdev; 652 union e1000_rx_desc_extended *rx_desc; 653 struct e1000_buffer *buffer_info; 654 struct sk_buff *skb; 655 unsigned int i; 656 unsigned int bufsz = adapter->rx_buffer_len; 657 658 i = rx_ring->next_to_use; 659 buffer_info = &rx_ring->buffer_info[i]; 660 661 while (cleaned_count--) { 662 skb = buffer_info->skb; 663 if (skb) { 664 skb_trim(skb, 0); 665 goto map_skb; 666 } 667 668 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 669 if (!skb) { 670 /* Better luck next round */ 671 adapter->alloc_rx_buff_failed++; 672 break; 673 } 674 675 buffer_info->skb = skb; 676 map_skb: 677 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 678 adapter->rx_buffer_len, 679 DMA_FROM_DEVICE); 680 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 681 dev_err(&pdev->dev, "Rx DMA map failed\n"); 682 adapter->rx_dma_failed++; 683 break; 684 } 685 686 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 687 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 688 689 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 690 /* Force memory writes to complete before letting h/w 691 * know there are new descriptors to fetch. (Only 692 * applicable for weak-ordered memory model archs, 693 * such as IA-64). 694 */ 695 wmb(); 696 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 697 e1000e_update_rdt_wa(rx_ring, i); 698 else 699 writel(i, rx_ring->tail); 700 } 701 i++; 702 if (i == rx_ring->count) 703 i = 0; 704 buffer_info = &rx_ring->buffer_info[i]; 705 } 706 707 rx_ring->next_to_use = i; 708 } 709 710 /** 711 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 712 * @rx_ring: Rx descriptor ring 713 * @cleaned_count: number to reallocate 714 * @gfp: flags for allocation 715 **/ 716 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 717 int cleaned_count, gfp_t gfp) 718 { 719 struct e1000_adapter *adapter = rx_ring->adapter; 720 struct net_device *netdev = adapter->netdev; 721 struct pci_dev *pdev = adapter->pdev; 722 union e1000_rx_desc_packet_split *rx_desc; 723 struct e1000_buffer *buffer_info; 724 struct e1000_ps_page *ps_page; 725 struct sk_buff *skb; 726 unsigned int i, j; 727 728 i = rx_ring->next_to_use; 729 buffer_info = &rx_ring->buffer_info[i]; 730 731 while (cleaned_count--) { 732 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 733 734 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 735 ps_page = &buffer_info->ps_pages[j]; 736 if (j >= adapter->rx_ps_pages) { 737 /* all unused desc entries get hw null ptr */ 738 rx_desc->read.buffer_addr[j + 1] = 739 ~cpu_to_le64(0); 740 continue; 741 } 742 if (!ps_page->page) { 743 ps_page->page = alloc_page(gfp); 744 if (!ps_page->page) { 745 adapter->alloc_rx_buff_failed++; 746 goto no_buffers; 747 } 748 ps_page->dma = dma_map_page(&pdev->dev, 749 ps_page->page, 750 0, PAGE_SIZE, 751 DMA_FROM_DEVICE); 752 if (dma_mapping_error(&pdev->dev, 753 ps_page->dma)) { 754 dev_err(&adapter->pdev->dev, 755 "Rx DMA page map failed\n"); 756 adapter->rx_dma_failed++; 757 goto no_buffers; 758 } 759 } 760 /* Refresh the desc even if buffer_addrs 761 * didn't change because each write-back 762 * erases this info. 763 */ 764 rx_desc->read.buffer_addr[j + 1] = 765 cpu_to_le64(ps_page->dma); 766 } 767 768 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 769 gfp); 770 771 if (!skb) { 772 adapter->alloc_rx_buff_failed++; 773 break; 774 } 775 776 buffer_info->skb = skb; 777 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 778 adapter->rx_ps_bsize0, 779 DMA_FROM_DEVICE); 780 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 781 dev_err(&pdev->dev, "Rx DMA map failed\n"); 782 adapter->rx_dma_failed++; 783 /* cleanup skb */ 784 dev_kfree_skb_any(skb); 785 buffer_info->skb = NULL; 786 break; 787 } 788 789 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 790 791 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 792 /* Force memory writes to complete before letting h/w 793 * know there are new descriptors to fetch. (Only 794 * applicable for weak-ordered memory model archs, 795 * such as IA-64). 796 */ 797 wmb(); 798 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 799 e1000e_update_rdt_wa(rx_ring, i << 1); 800 else 801 writel(i << 1, rx_ring->tail); 802 } 803 804 i++; 805 if (i == rx_ring->count) 806 i = 0; 807 buffer_info = &rx_ring->buffer_info[i]; 808 } 809 810 no_buffers: 811 rx_ring->next_to_use = i; 812 } 813 814 /** 815 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 816 * @rx_ring: Rx descriptor ring 817 * @cleaned_count: number of buffers to allocate this pass 818 * @gfp: flags for allocation 819 **/ 820 821 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 822 int cleaned_count, gfp_t gfp) 823 { 824 struct e1000_adapter *adapter = rx_ring->adapter; 825 struct net_device *netdev = adapter->netdev; 826 struct pci_dev *pdev = adapter->pdev; 827 union e1000_rx_desc_extended *rx_desc; 828 struct e1000_buffer *buffer_info; 829 struct sk_buff *skb; 830 unsigned int i; 831 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 832 833 i = rx_ring->next_to_use; 834 buffer_info = &rx_ring->buffer_info[i]; 835 836 while (cleaned_count--) { 837 skb = buffer_info->skb; 838 if (skb) { 839 skb_trim(skb, 0); 840 goto check_page; 841 } 842 843 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 844 if (unlikely(!skb)) { 845 /* Better luck next round */ 846 adapter->alloc_rx_buff_failed++; 847 break; 848 } 849 850 buffer_info->skb = skb; 851 check_page: 852 /* allocate a new page if necessary */ 853 if (!buffer_info->page) { 854 buffer_info->page = alloc_page(gfp); 855 if (unlikely(!buffer_info->page)) { 856 adapter->alloc_rx_buff_failed++; 857 break; 858 } 859 } 860 861 if (!buffer_info->dma) { 862 buffer_info->dma = dma_map_page(&pdev->dev, 863 buffer_info->page, 0, 864 PAGE_SIZE, 865 DMA_FROM_DEVICE); 866 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 867 adapter->alloc_rx_buff_failed++; 868 break; 869 } 870 } 871 872 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 873 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 874 875 if (unlikely(++i == rx_ring->count)) 876 i = 0; 877 buffer_info = &rx_ring->buffer_info[i]; 878 } 879 880 if (likely(rx_ring->next_to_use != i)) { 881 rx_ring->next_to_use = i; 882 if (unlikely(i-- == 0)) 883 i = (rx_ring->count - 1); 884 885 /* Force memory writes to complete before letting h/w 886 * know there are new descriptors to fetch. (Only 887 * applicable for weak-ordered memory model archs, 888 * such as IA-64). 889 */ 890 wmb(); 891 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 892 e1000e_update_rdt_wa(rx_ring, i); 893 else 894 writel(i, rx_ring->tail); 895 } 896 } 897 898 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 899 struct sk_buff *skb) 900 { 901 if (netdev->features & NETIF_F_RXHASH) 902 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 903 } 904 905 /** 906 * e1000_clean_rx_irq - Send received data up the network stack 907 * @rx_ring: Rx descriptor ring 908 * @work_done: output parameter for indicating completed work 909 * @work_to_do: how many packets we can clean 910 * 911 * the return value indicates whether actual cleaning was done, there 912 * is no guarantee that everything was cleaned 913 **/ 914 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 915 int work_to_do) 916 { 917 struct e1000_adapter *adapter = rx_ring->adapter; 918 struct net_device *netdev = adapter->netdev; 919 struct pci_dev *pdev = adapter->pdev; 920 struct e1000_hw *hw = &adapter->hw; 921 union e1000_rx_desc_extended *rx_desc, *next_rxd; 922 struct e1000_buffer *buffer_info, *next_buffer; 923 u32 length, staterr; 924 unsigned int i; 925 int cleaned_count = 0; 926 bool cleaned = false; 927 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 928 929 i = rx_ring->next_to_clean; 930 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 931 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 932 buffer_info = &rx_ring->buffer_info[i]; 933 934 while (staterr & E1000_RXD_STAT_DD) { 935 struct sk_buff *skb; 936 937 if (*work_done >= work_to_do) 938 break; 939 (*work_done)++; 940 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 941 942 skb = buffer_info->skb; 943 buffer_info->skb = NULL; 944 945 prefetch(skb->data - NET_IP_ALIGN); 946 947 i++; 948 if (i == rx_ring->count) 949 i = 0; 950 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 951 prefetch(next_rxd); 952 953 next_buffer = &rx_ring->buffer_info[i]; 954 955 cleaned = true; 956 cleaned_count++; 957 dma_unmap_single(&pdev->dev, buffer_info->dma, 958 adapter->rx_buffer_len, DMA_FROM_DEVICE); 959 buffer_info->dma = 0; 960 961 length = le16_to_cpu(rx_desc->wb.upper.length); 962 963 /* !EOP means multiple descriptors were used to store a single 964 * packet, if that's the case we need to toss it. In fact, we 965 * need to toss every packet with the EOP bit clear and the 966 * next frame that _does_ have the EOP bit set, as it is by 967 * definition only a frame fragment 968 */ 969 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 970 adapter->flags2 |= FLAG2_IS_DISCARDING; 971 972 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 973 /* All receives must fit into a single buffer */ 974 e_dbg("Receive packet consumed multiple buffers\n"); 975 /* recycle */ 976 buffer_info->skb = skb; 977 if (staterr & E1000_RXD_STAT_EOP) 978 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 979 goto next_desc; 980 } 981 982 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 983 !(netdev->features & NETIF_F_RXALL))) { 984 /* recycle */ 985 buffer_info->skb = skb; 986 goto next_desc; 987 } 988 989 /* adjust length to remove Ethernet CRC */ 990 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 991 /* If configured to store CRC, don't subtract FCS, 992 * but keep the FCS bytes out of the total_rx_bytes 993 * counter 994 */ 995 if (netdev->features & NETIF_F_RXFCS) 996 total_rx_bytes -= 4; 997 else 998 length -= 4; 999 } 1000 1001 total_rx_bytes += length; 1002 total_rx_packets++; 1003 1004 /* code added for copybreak, this should improve 1005 * performance for small packets with large amounts 1006 * of reassembly being done in the stack 1007 */ 1008 if (length < copybreak) { 1009 struct sk_buff *new_skb = 1010 napi_alloc_skb(&adapter->napi, length); 1011 if (new_skb) { 1012 skb_copy_to_linear_data_offset(new_skb, 1013 -NET_IP_ALIGN, 1014 (skb->data - 1015 NET_IP_ALIGN), 1016 (length + 1017 NET_IP_ALIGN)); 1018 /* save the skb in buffer_info as good */ 1019 buffer_info->skb = skb; 1020 skb = new_skb; 1021 } 1022 /* else just continue with the old one */ 1023 } 1024 /* end copybreak code */ 1025 skb_put(skb, length); 1026 1027 /* Receive Checksum Offload */ 1028 e1000_rx_checksum(adapter, staterr, skb); 1029 1030 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1031 1032 e1000_receive_skb(adapter, netdev, skb, staterr, 1033 rx_desc->wb.upper.vlan); 1034 1035 next_desc: 1036 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1037 1038 /* return some buffers to hardware, one at a time is too slow */ 1039 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1040 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1041 GFP_ATOMIC); 1042 cleaned_count = 0; 1043 } 1044 1045 /* use prefetched values */ 1046 rx_desc = next_rxd; 1047 buffer_info = next_buffer; 1048 1049 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1050 } 1051 rx_ring->next_to_clean = i; 1052 1053 cleaned_count = e1000_desc_unused(rx_ring); 1054 if (cleaned_count) 1055 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1056 1057 adapter->total_rx_bytes += total_rx_bytes; 1058 adapter->total_rx_packets += total_rx_packets; 1059 return cleaned; 1060 } 1061 1062 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1063 struct e1000_buffer *buffer_info, 1064 bool drop) 1065 { 1066 struct e1000_adapter *adapter = tx_ring->adapter; 1067 1068 if (buffer_info->dma) { 1069 if (buffer_info->mapped_as_page) 1070 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1071 buffer_info->length, DMA_TO_DEVICE); 1072 else 1073 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1074 buffer_info->length, DMA_TO_DEVICE); 1075 buffer_info->dma = 0; 1076 } 1077 if (buffer_info->skb) { 1078 if (drop) 1079 dev_kfree_skb_any(buffer_info->skb); 1080 else 1081 dev_consume_skb_any(buffer_info->skb); 1082 buffer_info->skb = NULL; 1083 } 1084 buffer_info->time_stamp = 0; 1085 } 1086 1087 static void e1000_print_hw_hang(struct work_struct *work) 1088 { 1089 struct e1000_adapter *adapter = container_of(work, 1090 struct e1000_adapter, 1091 print_hang_task); 1092 struct net_device *netdev = adapter->netdev; 1093 struct e1000_ring *tx_ring = adapter->tx_ring; 1094 unsigned int i = tx_ring->next_to_clean; 1095 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1096 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1097 struct e1000_hw *hw = &adapter->hw; 1098 u16 phy_status, phy_1000t_status, phy_ext_status; 1099 u16 pci_status; 1100 1101 if (test_bit(__E1000_DOWN, &adapter->state)) 1102 return; 1103 1104 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1105 /* May be block on write-back, flush and detect again 1106 * flush pending descriptor writebacks to memory 1107 */ 1108 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1109 /* execute the writes immediately */ 1110 e1e_flush(); 1111 /* Due to rare timing issues, write to TIDV again to ensure 1112 * the write is successful 1113 */ 1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1115 /* execute the writes immediately */ 1116 e1e_flush(); 1117 adapter->tx_hang_recheck = true; 1118 return; 1119 } 1120 adapter->tx_hang_recheck = false; 1121 1122 if (er32(TDH(0)) == er32(TDT(0))) { 1123 e_dbg("false hang detected, ignoring\n"); 1124 return; 1125 } 1126 1127 /* Real hang detected */ 1128 netif_stop_queue(netdev); 1129 1130 e1e_rphy(hw, MII_BMSR, &phy_status); 1131 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1132 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1133 1134 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1135 1136 /* detected Hardware unit hang */ 1137 e_err("Detected Hardware Unit Hang:\n" 1138 " TDH <%x>\n" 1139 " TDT <%x>\n" 1140 " next_to_use <%x>\n" 1141 " next_to_clean <%x>\n" 1142 "buffer_info[next_to_clean]:\n" 1143 " time_stamp <%lx>\n" 1144 " next_to_watch <%x>\n" 1145 " jiffies <%lx>\n" 1146 " next_to_watch.status <%x>\n" 1147 "MAC Status <%x>\n" 1148 "PHY Status <%x>\n" 1149 "PHY 1000BASE-T Status <%x>\n" 1150 "PHY Extended Status <%x>\n" 1151 "PCI Status <%x>\n", 1152 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1153 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1154 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1155 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1156 1157 e1000e_dump(adapter); 1158 1159 /* Suggest workaround for known h/w issue */ 1160 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1161 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1162 } 1163 1164 /** 1165 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1166 * @work: pointer to work struct 1167 * 1168 * This work function polls the TSYNCTXCTL valid bit to determine when a 1169 * timestamp has been taken for the current stored skb. The timestamp must 1170 * be for this skb because only one such packet is allowed in the queue. 1171 */ 1172 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1173 { 1174 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1175 tx_hwtstamp_work); 1176 struct e1000_hw *hw = &adapter->hw; 1177 1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1179 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1180 struct skb_shared_hwtstamps shhwtstamps; 1181 u64 txstmp; 1182 1183 txstmp = er32(TXSTMPL); 1184 txstmp |= (u64)er32(TXSTMPH) << 32; 1185 1186 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1187 1188 /* Clear the global tx_hwtstamp_skb pointer and force writes 1189 * prior to notifying the stack of a Tx timestamp. 1190 */ 1191 adapter->tx_hwtstamp_skb = NULL; 1192 wmb(); /* force write prior to skb_tstamp_tx */ 1193 1194 skb_tstamp_tx(skb, &shhwtstamps); 1195 dev_consume_skb_any(skb); 1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1197 + adapter->tx_timeout_factor * HZ)) { 1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1199 adapter->tx_hwtstamp_skb = NULL; 1200 adapter->tx_hwtstamp_timeouts++; 1201 e_warn("clearing Tx timestamp hang\n"); 1202 } else { 1203 /* reschedule to check later */ 1204 schedule_work(&adapter->tx_hwtstamp_work); 1205 } 1206 } 1207 1208 /** 1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1210 * @tx_ring: Tx descriptor ring 1211 * 1212 * the return value indicates whether actual cleaning was done, there 1213 * is no guarantee that everything was cleaned 1214 **/ 1215 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1216 { 1217 struct e1000_adapter *adapter = tx_ring->adapter; 1218 struct net_device *netdev = adapter->netdev; 1219 struct e1000_hw *hw = &adapter->hw; 1220 struct e1000_tx_desc *tx_desc, *eop_desc; 1221 struct e1000_buffer *buffer_info; 1222 unsigned int i, eop; 1223 unsigned int count = 0; 1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1225 unsigned int bytes_compl = 0, pkts_compl = 0; 1226 1227 i = tx_ring->next_to_clean; 1228 eop = tx_ring->buffer_info[i].next_to_watch; 1229 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1230 1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1232 (count < tx_ring->count)) { 1233 bool cleaned = false; 1234 1235 dma_rmb(); /* read buffer_info after eop_desc */ 1236 for (; !cleaned; count++) { 1237 tx_desc = E1000_TX_DESC(*tx_ring, i); 1238 buffer_info = &tx_ring->buffer_info[i]; 1239 cleaned = (i == eop); 1240 1241 if (cleaned) { 1242 total_tx_packets += buffer_info->segs; 1243 total_tx_bytes += buffer_info->bytecount; 1244 if (buffer_info->skb) { 1245 bytes_compl += buffer_info->skb->len; 1246 pkts_compl++; 1247 } 1248 } 1249 1250 e1000_put_txbuf(tx_ring, buffer_info, false); 1251 tx_desc->upper.data = 0; 1252 1253 i++; 1254 if (i == tx_ring->count) 1255 i = 0; 1256 } 1257 1258 if (i == tx_ring->next_to_use) 1259 break; 1260 eop = tx_ring->buffer_info[i].next_to_watch; 1261 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1262 } 1263 1264 tx_ring->next_to_clean = i; 1265 1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1267 1268 #define TX_WAKE_THRESHOLD 32 1269 if (count && netif_carrier_ok(netdev) && 1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1271 /* Make sure that anybody stopping the queue after this 1272 * sees the new next_to_clean. 1273 */ 1274 smp_mb(); 1275 1276 if (netif_queue_stopped(netdev) && 1277 !(test_bit(__E1000_DOWN, &adapter->state))) { 1278 netif_wake_queue(netdev); 1279 ++adapter->restart_queue; 1280 } 1281 } 1282 1283 if (adapter->detect_tx_hung) { 1284 /* Detect a transmit hang in hardware, this serializes the 1285 * check with the clearing of time_stamp and movement of i 1286 */ 1287 adapter->detect_tx_hung = false; 1288 if (tx_ring->buffer_info[i].time_stamp && 1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1290 + (adapter->tx_timeout_factor * HZ)) && 1291 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1292 schedule_work(&adapter->print_hang_task); 1293 else 1294 adapter->tx_hang_recheck = false; 1295 } 1296 adapter->total_tx_bytes += total_tx_bytes; 1297 adapter->total_tx_packets += total_tx_packets; 1298 return count < tx_ring->count; 1299 } 1300 1301 /** 1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1303 * @rx_ring: Rx descriptor ring 1304 * @work_done: output parameter for indicating completed work 1305 * @work_to_do: how many packets we can clean 1306 * 1307 * the return value indicates whether actual cleaning was done, there 1308 * is no guarantee that everything was cleaned 1309 **/ 1310 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1311 int work_to_do) 1312 { 1313 struct e1000_adapter *adapter = rx_ring->adapter; 1314 struct e1000_hw *hw = &adapter->hw; 1315 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1316 struct net_device *netdev = adapter->netdev; 1317 struct pci_dev *pdev = adapter->pdev; 1318 struct e1000_buffer *buffer_info, *next_buffer; 1319 struct e1000_ps_page *ps_page; 1320 struct sk_buff *skb; 1321 unsigned int i, j; 1322 u32 length, staterr; 1323 int cleaned_count = 0; 1324 bool cleaned = false; 1325 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1326 1327 i = rx_ring->next_to_clean; 1328 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1329 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1330 buffer_info = &rx_ring->buffer_info[i]; 1331 1332 while (staterr & E1000_RXD_STAT_DD) { 1333 if (*work_done >= work_to_do) 1334 break; 1335 (*work_done)++; 1336 skb = buffer_info->skb; 1337 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1338 1339 /* in the packet split case this is header only */ 1340 prefetch(skb->data - NET_IP_ALIGN); 1341 1342 i++; 1343 if (i == rx_ring->count) 1344 i = 0; 1345 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1346 prefetch(next_rxd); 1347 1348 next_buffer = &rx_ring->buffer_info[i]; 1349 1350 cleaned = true; 1351 cleaned_count++; 1352 dma_unmap_single(&pdev->dev, buffer_info->dma, 1353 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1354 buffer_info->dma = 0; 1355 1356 /* see !EOP comment in other Rx routine */ 1357 if (!(staterr & E1000_RXD_STAT_EOP)) 1358 adapter->flags2 |= FLAG2_IS_DISCARDING; 1359 1360 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1361 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1362 dev_kfree_skb_irq(skb); 1363 if (staterr & E1000_RXD_STAT_EOP) 1364 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1365 goto next_desc; 1366 } 1367 1368 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1369 !(netdev->features & NETIF_F_RXALL))) { 1370 dev_kfree_skb_irq(skb); 1371 goto next_desc; 1372 } 1373 1374 length = le16_to_cpu(rx_desc->wb.middle.length0); 1375 1376 if (!length) { 1377 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1378 dev_kfree_skb_irq(skb); 1379 goto next_desc; 1380 } 1381 1382 /* Good Receive */ 1383 skb_put(skb, length); 1384 1385 { 1386 /* this looks ugly, but it seems compiler issues make 1387 * it more efficient than reusing j 1388 */ 1389 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1390 1391 /* page alloc/put takes too long and effects small 1392 * packet throughput, so unsplit small packets and 1393 * save the alloc/put 1394 */ 1395 if (l1 && (l1 <= copybreak) && 1396 ((length + l1) <= adapter->rx_ps_bsize0)) { 1397 ps_page = &buffer_info->ps_pages[0]; 1398 1399 dma_sync_single_for_cpu(&pdev->dev, 1400 ps_page->dma, 1401 PAGE_SIZE, 1402 DMA_FROM_DEVICE); 1403 memcpy(skb_tail_pointer(skb), 1404 page_address(ps_page->page), l1); 1405 dma_sync_single_for_device(&pdev->dev, 1406 ps_page->dma, 1407 PAGE_SIZE, 1408 DMA_FROM_DEVICE); 1409 1410 /* remove the CRC */ 1411 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1412 if (!(netdev->features & NETIF_F_RXFCS)) 1413 l1 -= 4; 1414 } 1415 1416 skb_put(skb, l1); 1417 goto copydone; 1418 } /* if */ 1419 } 1420 1421 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1422 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1423 if (!length) 1424 break; 1425 1426 ps_page = &buffer_info->ps_pages[j]; 1427 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1428 DMA_FROM_DEVICE); 1429 ps_page->dma = 0; 1430 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1431 ps_page->page = NULL; 1432 skb->len += length; 1433 skb->data_len += length; 1434 skb->truesize += PAGE_SIZE; 1435 } 1436 1437 /* strip the ethernet crc, problem is we're using pages now so 1438 * this whole operation can get a little cpu intensive 1439 */ 1440 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1441 if (!(netdev->features & NETIF_F_RXFCS)) 1442 pskb_trim(skb, skb->len - 4); 1443 } 1444 1445 copydone: 1446 total_rx_bytes += skb->len; 1447 total_rx_packets++; 1448 1449 e1000_rx_checksum(adapter, staterr, skb); 1450 1451 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1452 1453 if (rx_desc->wb.upper.header_status & 1454 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1455 adapter->rx_hdr_split++; 1456 1457 e1000_receive_skb(adapter, netdev, skb, staterr, 1458 rx_desc->wb.middle.vlan); 1459 1460 next_desc: 1461 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1462 buffer_info->skb = NULL; 1463 1464 /* return some buffers to hardware, one at a time is too slow */ 1465 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1466 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1467 GFP_ATOMIC); 1468 cleaned_count = 0; 1469 } 1470 1471 /* use prefetched values */ 1472 rx_desc = next_rxd; 1473 buffer_info = next_buffer; 1474 1475 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1476 } 1477 rx_ring->next_to_clean = i; 1478 1479 cleaned_count = e1000_desc_unused(rx_ring); 1480 if (cleaned_count) 1481 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1482 1483 adapter->total_rx_bytes += total_rx_bytes; 1484 adapter->total_rx_packets += total_rx_packets; 1485 return cleaned; 1486 } 1487 1488 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1489 u16 length) 1490 { 1491 bi->page = NULL; 1492 skb->len += length; 1493 skb->data_len += length; 1494 skb->truesize += PAGE_SIZE; 1495 } 1496 1497 /** 1498 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1499 * @rx_ring: Rx descriptor ring 1500 * @work_done: output parameter for indicating completed work 1501 * @work_to_do: how many packets we can clean 1502 * 1503 * the return value indicates whether actual cleaning was done, there 1504 * is no guarantee that everything was cleaned 1505 **/ 1506 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1507 int work_to_do) 1508 { 1509 struct e1000_adapter *adapter = rx_ring->adapter; 1510 struct net_device *netdev = adapter->netdev; 1511 struct pci_dev *pdev = adapter->pdev; 1512 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1513 struct e1000_buffer *buffer_info, *next_buffer; 1514 u32 length, staterr; 1515 unsigned int i; 1516 int cleaned_count = 0; 1517 bool cleaned = false; 1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1519 struct skb_shared_info *shinfo; 1520 1521 i = rx_ring->next_to_clean; 1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1524 buffer_info = &rx_ring->buffer_info[i]; 1525 1526 while (staterr & E1000_RXD_STAT_DD) { 1527 struct sk_buff *skb; 1528 1529 if (*work_done >= work_to_do) 1530 break; 1531 (*work_done)++; 1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1533 1534 skb = buffer_info->skb; 1535 buffer_info->skb = NULL; 1536 1537 ++i; 1538 if (i == rx_ring->count) 1539 i = 0; 1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1541 prefetch(next_rxd); 1542 1543 next_buffer = &rx_ring->buffer_info[i]; 1544 1545 cleaned = true; 1546 cleaned_count++; 1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1548 DMA_FROM_DEVICE); 1549 buffer_info->dma = 0; 1550 1551 length = le16_to_cpu(rx_desc->wb.upper.length); 1552 1553 /* errors is only valid for DD + EOP descriptors */ 1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1556 !(netdev->features & NETIF_F_RXALL)))) { 1557 /* recycle both page and skb */ 1558 buffer_info->skb = skb; 1559 /* an error means any chain goes out the window too */ 1560 if (rx_ring->rx_skb_top) 1561 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1562 rx_ring->rx_skb_top = NULL; 1563 goto next_desc; 1564 } 1565 #define rxtop (rx_ring->rx_skb_top) 1566 if (!(staterr & E1000_RXD_STAT_EOP)) { 1567 /* this descriptor is only the beginning (or middle) */ 1568 if (!rxtop) { 1569 /* this is the beginning of a chain */ 1570 rxtop = skb; 1571 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1572 0, length); 1573 } else { 1574 /* this is the middle of a chain */ 1575 shinfo = skb_shinfo(rxtop); 1576 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1577 buffer_info->page, 0, 1578 length); 1579 /* re-use the skb, only consumed the page */ 1580 buffer_info->skb = skb; 1581 } 1582 e1000_consume_page(buffer_info, rxtop, length); 1583 goto next_desc; 1584 } else { 1585 if (rxtop) { 1586 /* end of the chain */ 1587 shinfo = skb_shinfo(rxtop); 1588 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1589 buffer_info->page, 0, 1590 length); 1591 /* re-use the current skb, we only consumed the 1592 * page 1593 */ 1594 buffer_info->skb = skb; 1595 skb = rxtop; 1596 rxtop = NULL; 1597 e1000_consume_page(buffer_info, skb, length); 1598 } else { 1599 /* no chain, got EOP, this buf is the packet 1600 * copybreak to save the put_page/alloc_page 1601 */ 1602 if (length <= copybreak && 1603 skb_tailroom(skb) >= length) { 1604 memcpy(skb_tail_pointer(skb), 1605 page_address(buffer_info->page), 1606 length); 1607 /* re-use the page, so don't erase 1608 * buffer_info->page 1609 */ 1610 skb_put(skb, length); 1611 } else { 1612 skb_fill_page_desc(skb, 0, 1613 buffer_info->page, 0, 1614 length); 1615 e1000_consume_page(buffer_info, skb, 1616 length); 1617 } 1618 } 1619 } 1620 1621 /* Receive Checksum Offload */ 1622 e1000_rx_checksum(adapter, staterr, skb); 1623 1624 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1625 1626 /* probably a little skewed due to removing CRC */ 1627 total_rx_bytes += skb->len; 1628 total_rx_packets++; 1629 1630 /* eth type trans needs skb->data to point to something */ 1631 if (!pskb_may_pull(skb, ETH_HLEN)) { 1632 e_err("pskb_may_pull failed.\n"); 1633 dev_kfree_skb_irq(skb); 1634 goto next_desc; 1635 } 1636 1637 e1000_receive_skb(adapter, netdev, skb, staterr, 1638 rx_desc->wb.upper.vlan); 1639 1640 next_desc: 1641 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1642 1643 /* return some buffers to hardware, one at a time is too slow */ 1644 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1645 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1646 GFP_ATOMIC); 1647 cleaned_count = 0; 1648 } 1649 1650 /* use prefetched values */ 1651 rx_desc = next_rxd; 1652 buffer_info = next_buffer; 1653 1654 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1655 } 1656 rx_ring->next_to_clean = i; 1657 1658 cleaned_count = e1000_desc_unused(rx_ring); 1659 if (cleaned_count) 1660 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1661 1662 adapter->total_rx_bytes += total_rx_bytes; 1663 adapter->total_rx_packets += total_rx_packets; 1664 return cleaned; 1665 } 1666 1667 /** 1668 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1669 * @rx_ring: Rx descriptor ring 1670 **/ 1671 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1672 { 1673 struct e1000_adapter *adapter = rx_ring->adapter; 1674 struct e1000_buffer *buffer_info; 1675 struct e1000_ps_page *ps_page; 1676 struct pci_dev *pdev = adapter->pdev; 1677 unsigned int i, j; 1678 1679 /* Free all the Rx ring sk_buffs */ 1680 for (i = 0; i < rx_ring->count; i++) { 1681 buffer_info = &rx_ring->buffer_info[i]; 1682 if (buffer_info->dma) { 1683 if (adapter->clean_rx == e1000_clean_rx_irq) 1684 dma_unmap_single(&pdev->dev, buffer_info->dma, 1685 adapter->rx_buffer_len, 1686 DMA_FROM_DEVICE); 1687 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1688 dma_unmap_page(&pdev->dev, buffer_info->dma, 1689 PAGE_SIZE, DMA_FROM_DEVICE); 1690 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1691 dma_unmap_single(&pdev->dev, buffer_info->dma, 1692 adapter->rx_ps_bsize0, 1693 DMA_FROM_DEVICE); 1694 buffer_info->dma = 0; 1695 } 1696 1697 if (buffer_info->page) { 1698 put_page(buffer_info->page); 1699 buffer_info->page = NULL; 1700 } 1701 1702 if (buffer_info->skb) { 1703 dev_kfree_skb(buffer_info->skb); 1704 buffer_info->skb = NULL; 1705 } 1706 1707 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1708 ps_page = &buffer_info->ps_pages[j]; 1709 if (!ps_page->page) 1710 break; 1711 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1712 DMA_FROM_DEVICE); 1713 ps_page->dma = 0; 1714 put_page(ps_page->page); 1715 ps_page->page = NULL; 1716 } 1717 } 1718 1719 /* there also may be some cached data from a chained receive */ 1720 if (rx_ring->rx_skb_top) { 1721 dev_kfree_skb(rx_ring->rx_skb_top); 1722 rx_ring->rx_skb_top = NULL; 1723 } 1724 1725 /* Zero out the descriptor ring */ 1726 memset(rx_ring->desc, 0, rx_ring->size); 1727 1728 rx_ring->next_to_clean = 0; 1729 rx_ring->next_to_use = 0; 1730 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1731 } 1732 1733 static void e1000e_downshift_workaround(struct work_struct *work) 1734 { 1735 struct e1000_adapter *adapter = container_of(work, 1736 struct e1000_adapter, 1737 downshift_task); 1738 1739 if (test_bit(__E1000_DOWN, &adapter->state)) 1740 return; 1741 1742 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1743 } 1744 1745 /** 1746 * e1000_intr_msi - Interrupt Handler 1747 * @irq: interrupt number 1748 * @data: pointer to a network interface device structure 1749 **/ 1750 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1751 { 1752 struct net_device *netdev = data; 1753 struct e1000_adapter *adapter = netdev_priv(netdev); 1754 struct e1000_hw *hw = &adapter->hw; 1755 u32 icr = er32(ICR); 1756 1757 /* read ICR disables interrupts using IAM */ 1758 if (icr & E1000_ICR_LSC) { 1759 hw->mac.get_link_status = true; 1760 /* ICH8 workaround-- Call gig speed drop workaround on cable 1761 * disconnect (LSC) before accessing any PHY registers 1762 */ 1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1764 (!(er32(STATUS) & E1000_STATUS_LU))) 1765 schedule_work(&adapter->downshift_task); 1766 1767 /* 80003ES2LAN workaround-- For packet buffer work-around on 1768 * link down event; disable receives here in the ISR and reset 1769 * adapter in watchdog 1770 */ 1771 if (netif_carrier_ok(netdev) && 1772 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1773 /* disable receives */ 1774 u32 rctl = er32(RCTL); 1775 1776 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1777 adapter->flags |= FLAG_RESTART_NOW; 1778 } 1779 /* guard against interrupt when we're going down */ 1780 if (!test_bit(__E1000_DOWN, &adapter->state)) 1781 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1782 } 1783 1784 /* Reset on uncorrectable ECC error */ 1785 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1786 u32 pbeccsts = er32(PBECCSTS); 1787 1788 adapter->corr_errors += 1789 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1790 adapter->uncorr_errors += 1791 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 1792 1793 /* Do the reset outside of interrupt context */ 1794 schedule_work(&adapter->reset_task); 1795 1796 /* return immediately since reset is imminent */ 1797 return IRQ_HANDLED; 1798 } 1799 1800 if (napi_schedule_prep(&adapter->napi)) { 1801 adapter->total_tx_bytes = 0; 1802 adapter->total_tx_packets = 0; 1803 adapter->total_rx_bytes = 0; 1804 adapter->total_rx_packets = 0; 1805 __napi_schedule(&adapter->napi); 1806 } 1807 1808 return IRQ_HANDLED; 1809 } 1810 1811 /** 1812 * e1000_intr - Interrupt Handler 1813 * @irq: interrupt number 1814 * @data: pointer to a network interface device structure 1815 **/ 1816 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1817 { 1818 struct net_device *netdev = data; 1819 struct e1000_adapter *adapter = netdev_priv(netdev); 1820 struct e1000_hw *hw = &adapter->hw; 1821 u32 rctl, icr = er32(ICR); 1822 1823 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1824 return IRQ_NONE; /* Not our interrupt */ 1825 1826 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1827 * not set, then the adapter didn't send an interrupt 1828 */ 1829 if (!(icr & E1000_ICR_INT_ASSERTED)) 1830 return IRQ_NONE; 1831 1832 /* Interrupt Auto-Mask...upon reading ICR, 1833 * interrupts are masked. No need for the 1834 * IMC write 1835 */ 1836 1837 if (icr & E1000_ICR_LSC) { 1838 hw->mac.get_link_status = true; 1839 /* ICH8 workaround-- Call gig speed drop workaround on cable 1840 * disconnect (LSC) before accessing any PHY registers 1841 */ 1842 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1843 (!(er32(STATUS) & E1000_STATUS_LU))) 1844 schedule_work(&adapter->downshift_task); 1845 1846 /* 80003ES2LAN workaround-- 1847 * For packet buffer work-around on link down event; 1848 * disable receives here in the ISR and 1849 * reset adapter in watchdog 1850 */ 1851 if (netif_carrier_ok(netdev) && 1852 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1853 /* disable receives */ 1854 rctl = er32(RCTL); 1855 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1856 adapter->flags |= FLAG_RESTART_NOW; 1857 } 1858 /* guard against interrupt when we're going down */ 1859 if (!test_bit(__E1000_DOWN, &adapter->state)) 1860 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1861 } 1862 1863 /* Reset on uncorrectable ECC error */ 1864 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1865 u32 pbeccsts = er32(PBECCSTS); 1866 1867 adapter->corr_errors += 1868 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1869 adapter->uncorr_errors += 1870 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 1871 1872 /* Do the reset outside of interrupt context */ 1873 schedule_work(&adapter->reset_task); 1874 1875 /* return immediately since reset is imminent */ 1876 return IRQ_HANDLED; 1877 } 1878 1879 if (napi_schedule_prep(&adapter->napi)) { 1880 adapter->total_tx_bytes = 0; 1881 adapter->total_tx_packets = 0; 1882 adapter->total_rx_bytes = 0; 1883 adapter->total_rx_packets = 0; 1884 __napi_schedule(&adapter->napi); 1885 } 1886 1887 return IRQ_HANDLED; 1888 } 1889 1890 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1891 { 1892 struct net_device *netdev = data; 1893 struct e1000_adapter *adapter = netdev_priv(netdev); 1894 struct e1000_hw *hw = &adapter->hw; 1895 u32 icr = er32(ICR); 1896 1897 if (icr & adapter->eiac_mask) 1898 ew32(ICS, (icr & adapter->eiac_mask)); 1899 1900 if (icr & E1000_ICR_LSC) { 1901 hw->mac.get_link_status = true; 1902 /* guard against interrupt when we're going down */ 1903 if (!test_bit(__E1000_DOWN, &adapter->state)) 1904 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1905 } 1906 1907 if (!test_bit(__E1000_DOWN, &adapter->state)) 1908 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1909 1910 return IRQ_HANDLED; 1911 } 1912 1913 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1914 { 1915 struct net_device *netdev = data; 1916 struct e1000_adapter *adapter = netdev_priv(netdev); 1917 struct e1000_hw *hw = &adapter->hw; 1918 struct e1000_ring *tx_ring = adapter->tx_ring; 1919 1920 adapter->total_tx_bytes = 0; 1921 adapter->total_tx_packets = 0; 1922 1923 if (!e1000_clean_tx_irq(tx_ring)) 1924 /* Ring was not completely cleaned, so fire another interrupt */ 1925 ew32(ICS, tx_ring->ims_val); 1926 1927 if (!test_bit(__E1000_DOWN, &adapter->state)) 1928 ew32(IMS, adapter->tx_ring->ims_val); 1929 1930 return IRQ_HANDLED; 1931 } 1932 1933 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1934 { 1935 struct net_device *netdev = data; 1936 struct e1000_adapter *adapter = netdev_priv(netdev); 1937 struct e1000_ring *rx_ring = adapter->rx_ring; 1938 1939 /* Write the ITR value calculated at the end of the 1940 * previous interrupt. 1941 */ 1942 if (rx_ring->set_itr) { 1943 u32 itr = rx_ring->itr_val ? 1944 1000000000 / (rx_ring->itr_val * 256) : 0; 1945 1946 writel(itr, rx_ring->itr_register); 1947 rx_ring->set_itr = 0; 1948 } 1949 1950 if (napi_schedule_prep(&adapter->napi)) { 1951 adapter->total_rx_bytes = 0; 1952 adapter->total_rx_packets = 0; 1953 __napi_schedule(&adapter->napi); 1954 } 1955 return IRQ_HANDLED; 1956 } 1957 1958 /** 1959 * e1000_configure_msix - Configure MSI-X hardware 1960 * @adapter: board private structure 1961 * 1962 * e1000_configure_msix sets up the hardware to properly 1963 * generate MSI-X interrupts. 1964 **/ 1965 static void e1000_configure_msix(struct e1000_adapter *adapter) 1966 { 1967 struct e1000_hw *hw = &adapter->hw; 1968 struct e1000_ring *rx_ring = adapter->rx_ring; 1969 struct e1000_ring *tx_ring = adapter->tx_ring; 1970 int vector = 0; 1971 u32 ctrl_ext, ivar = 0; 1972 1973 adapter->eiac_mask = 0; 1974 1975 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1976 if (hw->mac.type == e1000_82574) { 1977 u32 rfctl = er32(RFCTL); 1978 1979 rfctl |= E1000_RFCTL_ACK_DIS; 1980 ew32(RFCTL, rfctl); 1981 } 1982 1983 /* Configure Rx vector */ 1984 rx_ring->ims_val = E1000_IMS_RXQ0; 1985 adapter->eiac_mask |= rx_ring->ims_val; 1986 if (rx_ring->itr_val) 1987 writel(1000000000 / (rx_ring->itr_val * 256), 1988 rx_ring->itr_register); 1989 else 1990 writel(1, rx_ring->itr_register); 1991 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 1992 1993 /* Configure Tx vector */ 1994 tx_ring->ims_val = E1000_IMS_TXQ0; 1995 vector++; 1996 if (tx_ring->itr_val) 1997 writel(1000000000 / (tx_ring->itr_val * 256), 1998 tx_ring->itr_register); 1999 else 2000 writel(1, tx_ring->itr_register); 2001 adapter->eiac_mask |= tx_ring->ims_val; 2002 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2003 2004 /* set vector for Other Causes, e.g. link changes */ 2005 vector++; 2006 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2007 if (rx_ring->itr_val) 2008 writel(1000000000 / (rx_ring->itr_val * 256), 2009 hw->hw_addr + E1000_EITR_82574(vector)); 2010 else 2011 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2012 2013 /* Cause Tx interrupts on every write back */ 2014 ivar |= BIT(31); 2015 2016 ew32(IVAR, ivar); 2017 2018 /* enable MSI-X PBA support */ 2019 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2020 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2021 ew32(CTRL_EXT, ctrl_ext); 2022 e1e_flush(); 2023 } 2024 2025 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2026 { 2027 if (adapter->msix_entries) { 2028 pci_disable_msix(adapter->pdev); 2029 kfree(adapter->msix_entries); 2030 adapter->msix_entries = NULL; 2031 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2032 pci_disable_msi(adapter->pdev); 2033 adapter->flags &= ~FLAG_MSI_ENABLED; 2034 } 2035 } 2036 2037 /** 2038 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2039 * @adapter: board private structure 2040 * 2041 * Attempt to configure interrupts using the best available 2042 * capabilities of the hardware and kernel. 2043 **/ 2044 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2045 { 2046 int err; 2047 int i; 2048 2049 switch (adapter->int_mode) { 2050 case E1000E_INT_MODE_MSIX: 2051 if (adapter->flags & FLAG_HAS_MSIX) { 2052 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2053 adapter->msix_entries = kcalloc(adapter->num_vectors, 2054 sizeof(struct 2055 msix_entry), 2056 GFP_KERNEL); 2057 if (adapter->msix_entries) { 2058 struct e1000_adapter *a = adapter; 2059 2060 for (i = 0; i < adapter->num_vectors; i++) 2061 adapter->msix_entries[i].entry = i; 2062 2063 err = pci_enable_msix_range(a->pdev, 2064 a->msix_entries, 2065 a->num_vectors, 2066 a->num_vectors); 2067 if (err > 0) 2068 return; 2069 } 2070 /* MSI-X failed, so fall through and try MSI */ 2071 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2072 e1000e_reset_interrupt_capability(adapter); 2073 } 2074 adapter->int_mode = E1000E_INT_MODE_MSI; 2075 fallthrough; 2076 case E1000E_INT_MODE_MSI: 2077 if (!pci_enable_msi(adapter->pdev)) { 2078 adapter->flags |= FLAG_MSI_ENABLED; 2079 } else { 2080 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2081 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2082 } 2083 fallthrough; 2084 case E1000E_INT_MODE_LEGACY: 2085 /* Don't do anything; this is the system default */ 2086 break; 2087 } 2088 2089 /* store the number of vectors being used */ 2090 adapter->num_vectors = 1; 2091 } 2092 2093 /** 2094 * e1000_request_msix - Initialize MSI-X interrupts 2095 * @adapter: board private structure 2096 * 2097 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2098 * kernel. 2099 **/ 2100 static int e1000_request_msix(struct e1000_adapter *adapter) 2101 { 2102 struct net_device *netdev = adapter->netdev; 2103 int err = 0, vector = 0; 2104 2105 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2106 snprintf(adapter->rx_ring->name, 2107 sizeof(adapter->rx_ring->name) - 1, 2108 "%.14s-rx-0", netdev->name); 2109 else 2110 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2111 err = request_irq(adapter->msix_entries[vector].vector, 2112 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2113 netdev); 2114 if (err) 2115 return err; 2116 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2117 E1000_EITR_82574(vector); 2118 adapter->rx_ring->itr_val = adapter->itr; 2119 vector++; 2120 2121 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2122 snprintf(adapter->tx_ring->name, 2123 sizeof(adapter->tx_ring->name) - 1, 2124 "%.14s-tx-0", netdev->name); 2125 else 2126 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2127 err = request_irq(adapter->msix_entries[vector].vector, 2128 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2129 netdev); 2130 if (err) 2131 return err; 2132 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2133 E1000_EITR_82574(vector); 2134 adapter->tx_ring->itr_val = adapter->itr; 2135 vector++; 2136 2137 err = request_irq(adapter->msix_entries[vector].vector, 2138 e1000_msix_other, 0, netdev->name, netdev); 2139 if (err) 2140 return err; 2141 2142 e1000_configure_msix(adapter); 2143 2144 return 0; 2145 } 2146 2147 /** 2148 * e1000_request_irq - initialize interrupts 2149 * @adapter: board private structure 2150 * 2151 * Attempts to configure interrupts using the best available 2152 * capabilities of the hardware and kernel. 2153 **/ 2154 static int e1000_request_irq(struct e1000_adapter *adapter) 2155 { 2156 struct net_device *netdev = adapter->netdev; 2157 int err; 2158 2159 if (adapter->msix_entries) { 2160 err = e1000_request_msix(adapter); 2161 if (!err) 2162 return err; 2163 /* fall back to MSI */ 2164 e1000e_reset_interrupt_capability(adapter); 2165 adapter->int_mode = E1000E_INT_MODE_MSI; 2166 e1000e_set_interrupt_capability(adapter); 2167 } 2168 if (adapter->flags & FLAG_MSI_ENABLED) { 2169 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2170 netdev->name, netdev); 2171 if (!err) 2172 return err; 2173 2174 /* fall back to legacy interrupt */ 2175 e1000e_reset_interrupt_capability(adapter); 2176 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2177 } 2178 2179 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2180 netdev->name, netdev); 2181 if (err) 2182 e_err("Unable to allocate interrupt, Error: %d\n", err); 2183 2184 return err; 2185 } 2186 2187 static void e1000_free_irq(struct e1000_adapter *adapter) 2188 { 2189 struct net_device *netdev = adapter->netdev; 2190 2191 if (adapter->msix_entries) { 2192 int vector = 0; 2193 2194 free_irq(adapter->msix_entries[vector].vector, netdev); 2195 vector++; 2196 2197 free_irq(adapter->msix_entries[vector].vector, netdev); 2198 vector++; 2199 2200 /* Other Causes interrupt vector */ 2201 free_irq(adapter->msix_entries[vector].vector, netdev); 2202 return; 2203 } 2204 2205 free_irq(adapter->pdev->irq, netdev); 2206 } 2207 2208 /** 2209 * e1000_irq_disable - Mask off interrupt generation on the NIC 2210 * @adapter: board private structure 2211 **/ 2212 static void e1000_irq_disable(struct e1000_adapter *adapter) 2213 { 2214 struct e1000_hw *hw = &adapter->hw; 2215 2216 ew32(IMC, ~0); 2217 if (adapter->msix_entries) 2218 ew32(EIAC_82574, 0); 2219 e1e_flush(); 2220 2221 if (adapter->msix_entries) { 2222 int i; 2223 2224 for (i = 0; i < adapter->num_vectors; i++) 2225 synchronize_irq(adapter->msix_entries[i].vector); 2226 } else { 2227 synchronize_irq(adapter->pdev->irq); 2228 } 2229 } 2230 2231 /** 2232 * e1000_irq_enable - Enable default interrupt generation settings 2233 * @adapter: board private structure 2234 **/ 2235 static void e1000_irq_enable(struct e1000_adapter *adapter) 2236 { 2237 struct e1000_hw *hw = &adapter->hw; 2238 2239 if (adapter->msix_entries) { 2240 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2241 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2242 IMS_OTHER_MASK); 2243 } else if (hw->mac.type >= e1000_pch_lpt) { 2244 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2245 } else { 2246 ew32(IMS, IMS_ENABLE_MASK); 2247 } 2248 e1e_flush(); 2249 } 2250 2251 /** 2252 * e1000e_get_hw_control - get control of the h/w from f/w 2253 * @adapter: address of board private structure 2254 * 2255 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2256 * For ASF and Pass Through versions of f/w this means that 2257 * the driver is loaded. For AMT version (only with 82573) 2258 * of the f/w this means that the network i/f is open. 2259 **/ 2260 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2261 { 2262 struct e1000_hw *hw = &adapter->hw; 2263 u32 ctrl_ext; 2264 u32 swsm; 2265 2266 /* Let firmware know the driver has taken over */ 2267 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2268 swsm = er32(SWSM); 2269 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2270 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2271 ctrl_ext = er32(CTRL_EXT); 2272 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2273 } 2274 } 2275 2276 /** 2277 * e1000e_release_hw_control - release control of the h/w to f/w 2278 * @adapter: address of board private structure 2279 * 2280 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2281 * For ASF and Pass Through versions of f/w this means that the 2282 * driver is no longer loaded. For AMT version (only with 82573) i 2283 * of the f/w this means that the network i/f is closed. 2284 * 2285 **/ 2286 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2287 { 2288 struct e1000_hw *hw = &adapter->hw; 2289 u32 ctrl_ext; 2290 u32 swsm; 2291 2292 /* Let firmware taken over control of h/w */ 2293 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2294 swsm = er32(SWSM); 2295 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2296 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2297 ctrl_ext = er32(CTRL_EXT); 2298 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2299 } 2300 } 2301 2302 /** 2303 * e1000_alloc_ring_dma - allocate memory for a ring structure 2304 * @adapter: board private structure 2305 * @ring: ring struct for which to allocate dma 2306 **/ 2307 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2308 struct e1000_ring *ring) 2309 { 2310 struct pci_dev *pdev = adapter->pdev; 2311 2312 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2313 GFP_KERNEL); 2314 if (!ring->desc) 2315 return -ENOMEM; 2316 2317 return 0; 2318 } 2319 2320 /** 2321 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2322 * @tx_ring: Tx descriptor ring 2323 * 2324 * Return 0 on success, negative on failure 2325 **/ 2326 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2327 { 2328 struct e1000_adapter *adapter = tx_ring->adapter; 2329 int err = -ENOMEM, size; 2330 2331 size = sizeof(struct e1000_buffer) * tx_ring->count; 2332 tx_ring->buffer_info = vzalloc(size); 2333 if (!tx_ring->buffer_info) 2334 goto err; 2335 2336 /* round up to nearest 4K */ 2337 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2338 tx_ring->size = ALIGN(tx_ring->size, 4096); 2339 2340 err = e1000_alloc_ring_dma(adapter, tx_ring); 2341 if (err) 2342 goto err; 2343 2344 tx_ring->next_to_use = 0; 2345 tx_ring->next_to_clean = 0; 2346 2347 return 0; 2348 err: 2349 vfree(tx_ring->buffer_info); 2350 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2351 return err; 2352 } 2353 2354 /** 2355 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2356 * @rx_ring: Rx descriptor ring 2357 * 2358 * Returns 0 on success, negative on failure 2359 **/ 2360 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2361 { 2362 struct e1000_adapter *adapter = rx_ring->adapter; 2363 struct e1000_buffer *buffer_info; 2364 int i, size, desc_len, err = -ENOMEM; 2365 2366 size = sizeof(struct e1000_buffer) * rx_ring->count; 2367 rx_ring->buffer_info = vzalloc(size); 2368 if (!rx_ring->buffer_info) 2369 goto err; 2370 2371 for (i = 0; i < rx_ring->count; i++) { 2372 buffer_info = &rx_ring->buffer_info[i]; 2373 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2374 sizeof(struct e1000_ps_page), 2375 GFP_KERNEL); 2376 if (!buffer_info->ps_pages) 2377 goto err_pages; 2378 } 2379 2380 desc_len = sizeof(union e1000_rx_desc_packet_split); 2381 2382 /* Round up to nearest 4K */ 2383 rx_ring->size = rx_ring->count * desc_len; 2384 rx_ring->size = ALIGN(rx_ring->size, 4096); 2385 2386 err = e1000_alloc_ring_dma(adapter, rx_ring); 2387 if (err) 2388 goto err_pages; 2389 2390 rx_ring->next_to_clean = 0; 2391 rx_ring->next_to_use = 0; 2392 rx_ring->rx_skb_top = NULL; 2393 2394 return 0; 2395 2396 err_pages: 2397 for (i = 0; i < rx_ring->count; i++) { 2398 buffer_info = &rx_ring->buffer_info[i]; 2399 kfree(buffer_info->ps_pages); 2400 } 2401 err: 2402 vfree(rx_ring->buffer_info); 2403 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2404 return err; 2405 } 2406 2407 /** 2408 * e1000_clean_tx_ring - Free Tx Buffers 2409 * @tx_ring: Tx descriptor ring 2410 **/ 2411 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2412 { 2413 struct e1000_adapter *adapter = tx_ring->adapter; 2414 struct e1000_buffer *buffer_info; 2415 unsigned long size; 2416 unsigned int i; 2417 2418 for (i = 0; i < tx_ring->count; i++) { 2419 buffer_info = &tx_ring->buffer_info[i]; 2420 e1000_put_txbuf(tx_ring, buffer_info, false); 2421 } 2422 2423 netdev_reset_queue(adapter->netdev); 2424 size = sizeof(struct e1000_buffer) * tx_ring->count; 2425 memset(tx_ring->buffer_info, 0, size); 2426 2427 memset(tx_ring->desc, 0, tx_ring->size); 2428 2429 tx_ring->next_to_use = 0; 2430 tx_ring->next_to_clean = 0; 2431 } 2432 2433 /** 2434 * e1000e_free_tx_resources - Free Tx Resources per Queue 2435 * @tx_ring: Tx descriptor ring 2436 * 2437 * Free all transmit software resources 2438 **/ 2439 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2440 { 2441 struct e1000_adapter *adapter = tx_ring->adapter; 2442 struct pci_dev *pdev = adapter->pdev; 2443 2444 e1000_clean_tx_ring(tx_ring); 2445 2446 vfree(tx_ring->buffer_info); 2447 tx_ring->buffer_info = NULL; 2448 2449 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2450 tx_ring->dma); 2451 tx_ring->desc = NULL; 2452 } 2453 2454 /** 2455 * e1000e_free_rx_resources - Free Rx Resources 2456 * @rx_ring: Rx descriptor ring 2457 * 2458 * Free all receive software resources 2459 **/ 2460 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2461 { 2462 struct e1000_adapter *adapter = rx_ring->adapter; 2463 struct pci_dev *pdev = adapter->pdev; 2464 int i; 2465 2466 e1000_clean_rx_ring(rx_ring); 2467 2468 for (i = 0; i < rx_ring->count; i++) 2469 kfree(rx_ring->buffer_info[i].ps_pages); 2470 2471 vfree(rx_ring->buffer_info); 2472 rx_ring->buffer_info = NULL; 2473 2474 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2475 rx_ring->dma); 2476 rx_ring->desc = NULL; 2477 } 2478 2479 /** 2480 * e1000_update_itr - update the dynamic ITR value based on statistics 2481 * @itr_setting: current adapter->itr 2482 * @packets: the number of packets during this measurement interval 2483 * @bytes: the number of bytes during this measurement interval 2484 * 2485 * Stores a new ITR value based on packets and byte 2486 * counts during the last interrupt. The advantage of per interrupt 2487 * computation is faster updates and more accurate ITR for the current 2488 * traffic pattern. Constants in this function were computed 2489 * based on theoretical maximum wire speed and thresholds were set based 2490 * on testing data as well as attempting to minimize response time 2491 * while increasing bulk throughput. This functionality is controlled 2492 * by the InterruptThrottleRate module parameter. 2493 **/ 2494 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2495 { 2496 unsigned int retval = itr_setting; 2497 2498 if (packets == 0) 2499 return itr_setting; 2500 2501 switch (itr_setting) { 2502 case lowest_latency: 2503 /* handle TSO and jumbo frames */ 2504 if (bytes / packets > 8000) 2505 retval = bulk_latency; 2506 else if ((packets < 5) && (bytes > 512)) 2507 retval = low_latency; 2508 break; 2509 case low_latency: /* 50 usec aka 20000 ints/s */ 2510 if (bytes > 10000) { 2511 /* this if handles the TSO accounting */ 2512 if (bytes / packets > 8000) 2513 retval = bulk_latency; 2514 else if ((packets < 10) || ((bytes / packets) > 1200)) 2515 retval = bulk_latency; 2516 else if ((packets > 35)) 2517 retval = lowest_latency; 2518 } else if (bytes / packets > 2000) { 2519 retval = bulk_latency; 2520 } else if (packets <= 2 && bytes < 512) { 2521 retval = lowest_latency; 2522 } 2523 break; 2524 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2525 if (bytes > 25000) { 2526 if (packets > 35) 2527 retval = low_latency; 2528 } else if (bytes < 6000) { 2529 retval = low_latency; 2530 } 2531 break; 2532 } 2533 2534 return retval; 2535 } 2536 2537 static void e1000_set_itr(struct e1000_adapter *adapter) 2538 { 2539 u16 current_itr; 2540 u32 new_itr = adapter->itr; 2541 2542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2543 if (adapter->link_speed != SPEED_1000) { 2544 new_itr = 4000; 2545 goto set_itr_now; 2546 } 2547 2548 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2549 new_itr = 0; 2550 goto set_itr_now; 2551 } 2552 2553 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2554 adapter->total_tx_packets, 2555 adapter->total_tx_bytes); 2556 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2557 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2558 adapter->tx_itr = low_latency; 2559 2560 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2561 adapter->total_rx_packets, 2562 adapter->total_rx_bytes); 2563 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2564 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2565 adapter->rx_itr = low_latency; 2566 2567 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2568 2569 /* counts and packets in update_itr are dependent on these numbers */ 2570 switch (current_itr) { 2571 case lowest_latency: 2572 new_itr = 70000; 2573 break; 2574 case low_latency: 2575 new_itr = 20000; /* aka hwitr = ~200 */ 2576 break; 2577 case bulk_latency: 2578 new_itr = 4000; 2579 break; 2580 default: 2581 break; 2582 } 2583 2584 set_itr_now: 2585 if (new_itr != adapter->itr) { 2586 /* this attempts to bias the interrupt rate towards Bulk 2587 * by adding intermediate steps when interrupt rate is 2588 * increasing 2589 */ 2590 new_itr = new_itr > adapter->itr ? 2591 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2592 adapter->itr = new_itr; 2593 adapter->rx_ring->itr_val = new_itr; 2594 if (adapter->msix_entries) 2595 adapter->rx_ring->set_itr = 1; 2596 else 2597 e1000e_write_itr(adapter, new_itr); 2598 } 2599 } 2600 2601 /** 2602 * e1000e_write_itr - write the ITR value to the appropriate registers 2603 * @adapter: address of board private structure 2604 * @itr: new ITR value to program 2605 * 2606 * e1000e_write_itr determines if the adapter is in MSI-X mode 2607 * and, if so, writes the EITR registers with the ITR value. 2608 * Otherwise, it writes the ITR value into the ITR register. 2609 **/ 2610 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2611 { 2612 struct e1000_hw *hw = &adapter->hw; 2613 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2614 2615 if (adapter->msix_entries) { 2616 int vector; 2617 2618 for (vector = 0; vector < adapter->num_vectors; vector++) 2619 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2620 } else { 2621 ew32(ITR, new_itr); 2622 } 2623 } 2624 2625 /** 2626 * e1000_alloc_queues - Allocate memory for all rings 2627 * @adapter: board private structure to initialize 2628 **/ 2629 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2630 { 2631 int size = sizeof(struct e1000_ring); 2632 2633 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2634 if (!adapter->tx_ring) 2635 goto err; 2636 adapter->tx_ring->count = adapter->tx_ring_count; 2637 adapter->tx_ring->adapter = adapter; 2638 2639 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2640 if (!adapter->rx_ring) 2641 goto err; 2642 adapter->rx_ring->count = adapter->rx_ring_count; 2643 adapter->rx_ring->adapter = adapter; 2644 2645 return 0; 2646 err: 2647 e_err("Unable to allocate memory for queues\n"); 2648 kfree(adapter->rx_ring); 2649 kfree(adapter->tx_ring); 2650 return -ENOMEM; 2651 } 2652 2653 /** 2654 * e1000e_poll - NAPI Rx polling callback 2655 * @napi: struct associated with this polling callback 2656 * @budget: number of packets driver is allowed to process this poll 2657 **/ 2658 static int e1000e_poll(struct napi_struct *napi, int budget) 2659 { 2660 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2661 napi); 2662 struct e1000_hw *hw = &adapter->hw; 2663 struct net_device *poll_dev = adapter->netdev; 2664 int tx_cleaned = 1, work_done = 0; 2665 2666 adapter = netdev_priv(poll_dev); 2667 2668 if (!adapter->msix_entries || 2669 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2670 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2671 2672 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2673 2674 if (!tx_cleaned || work_done == budget) 2675 return budget; 2676 2677 /* Exit the polling mode, but don't re-enable interrupts if stack might 2678 * poll us due to busy-polling 2679 */ 2680 if (likely(napi_complete_done(napi, work_done))) { 2681 if (adapter->itr_setting & 3) 2682 e1000_set_itr(adapter); 2683 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2684 if (adapter->msix_entries) 2685 ew32(IMS, adapter->rx_ring->ims_val); 2686 else 2687 e1000_irq_enable(adapter); 2688 } 2689 } 2690 2691 return work_done; 2692 } 2693 2694 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2695 __always_unused __be16 proto, u16 vid) 2696 { 2697 struct e1000_adapter *adapter = netdev_priv(netdev); 2698 struct e1000_hw *hw = &adapter->hw; 2699 u32 vfta, index; 2700 2701 /* don't update vlan cookie if already programmed */ 2702 if ((adapter->hw.mng_cookie.status & 2703 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2704 (vid == adapter->mng_vlan_id)) 2705 return 0; 2706 2707 /* add VID to filter table */ 2708 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2709 index = (vid >> 5) & 0x7F; 2710 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2711 vfta |= BIT((vid & 0x1F)); 2712 hw->mac.ops.write_vfta(hw, index, vfta); 2713 } 2714 2715 set_bit(vid, adapter->active_vlans); 2716 2717 return 0; 2718 } 2719 2720 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2721 __always_unused __be16 proto, u16 vid) 2722 { 2723 struct e1000_adapter *adapter = netdev_priv(netdev); 2724 struct e1000_hw *hw = &adapter->hw; 2725 u32 vfta, index; 2726 2727 if ((adapter->hw.mng_cookie.status & 2728 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2729 (vid == adapter->mng_vlan_id)) { 2730 /* release control to f/w */ 2731 e1000e_release_hw_control(adapter); 2732 return 0; 2733 } 2734 2735 /* remove VID from filter table */ 2736 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2737 index = (vid >> 5) & 0x7F; 2738 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2739 vfta &= ~BIT((vid & 0x1F)); 2740 hw->mac.ops.write_vfta(hw, index, vfta); 2741 } 2742 2743 clear_bit(vid, adapter->active_vlans); 2744 2745 return 0; 2746 } 2747 2748 /** 2749 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2750 * @adapter: board private structure to initialize 2751 **/ 2752 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2753 { 2754 struct net_device *netdev = adapter->netdev; 2755 struct e1000_hw *hw = &adapter->hw; 2756 u32 rctl; 2757 2758 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2759 /* disable VLAN receive filtering */ 2760 rctl = er32(RCTL); 2761 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2762 ew32(RCTL, rctl); 2763 2764 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2765 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2766 adapter->mng_vlan_id); 2767 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2768 } 2769 } 2770 } 2771 2772 /** 2773 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2774 * @adapter: board private structure to initialize 2775 **/ 2776 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2777 { 2778 struct e1000_hw *hw = &adapter->hw; 2779 u32 rctl; 2780 2781 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2782 /* enable VLAN receive filtering */ 2783 rctl = er32(RCTL); 2784 rctl |= E1000_RCTL_VFE; 2785 rctl &= ~E1000_RCTL_CFIEN; 2786 ew32(RCTL, rctl); 2787 } 2788 } 2789 2790 /** 2791 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2792 * @adapter: board private structure to initialize 2793 **/ 2794 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2795 { 2796 struct e1000_hw *hw = &adapter->hw; 2797 u32 ctrl; 2798 2799 /* disable VLAN tag insert/strip */ 2800 ctrl = er32(CTRL); 2801 ctrl &= ~E1000_CTRL_VME; 2802 ew32(CTRL, ctrl); 2803 } 2804 2805 /** 2806 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2807 * @adapter: board private structure to initialize 2808 **/ 2809 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2810 { 2811 struct e1000_hw *hw = &adapter->hw; 2812 u32 ctrl; 2813 2814 /* enable VLAN tag insert/strip */ 2815 ctrl = er32(CTRL); 2816 ctrl |= E1000_CTRL_VME; 2817 ew32(CTRL, ctrl); 2818 } 2819 2820 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2821 { 2822 struct net_device *netdev = adapter->netdev; 2823 u16 vid = adapter->hw.mng_cookie.vlan_id; 2824 u16 old_vid = adapter->mng_vlan_id; 2825 2826 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2827 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2828 adapter->mng_vlan_id = vid; 2829 } 2830 2831 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2832 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2833 } 2834 2835 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2836 { 2837 u16 vid; 2838 2839 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2840 2841 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2842 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2843 } 2844 2845 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2846 { 2847 struct e1000_hw *hw = &adapter->hw; 2848 u32 manc, manc2h, mdef, i, j; 2849 2850 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2851 return; 2852 2853 manc = er32(MANC); 2854 2855 /* enable receiving management packets to the host. this will probably 2856 * generate destination unreachable messages from the host OS, but 2857 * the packets will be handled on SMBUS 2858 */ 2859 manc |= E1000_MANC_EN_MNG2HOST; 2860 manc2h = er32(MANC2H); 2861 2862 switch (hw->mac.type) { 2863 default: 2864 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2865 break; 2866 case e1000_82574: 2867 case e1000_82583: 2868 /* Check if IPMI pass-through decision filter already exists; 2869 * if so, enable it. 2870 */ 2871 for (i = 0, j = 0; i < 8; i++) { 2872 mdef = er32(MDEF(i)); 2873 2874 /* Ignore filters with anything other than IPMI ports */ 2875 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2876 continue; 2877 2878 /* Enable this decision filter in MANC2H */ 2879 if (mdef) 2880 manc2h |= BIT(i); 2881 2882 j |= mdef; 2883 } 2884 2885 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2886 break; 2887 2888 /* Create new decision filter in an empty filter */ 2889 for (i = 0, j = 0; i < 8; i++) 2890 if (er32(MDEF(i)) == 0) { 2891 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2892 E1000_MDEF_PORT_664)); 2893 manc2h |= BIT(1); 2894 j++; 2895 break; 2896 } 2897 2898 if (!j) 2899 e_warn("Unable to create IPMI pass-through filter\n"); 2900 break; 2901 } 2902 2903 ew32(MANC2H, manc2h); 2904 ew32(MANC, manc); 2905 } 2906 2907 /** 2908 * e1000_configure_tx - Configure Transmit Unit after Reset 2909 * @adapter: board private structure 2910 * 2911 * Configure the Tx unit of the MAC after a reset. 2912 **/ 2913 static void e1000_configure_tx(struct e1000_adapter *adapter) 2914 { 2915 struct e1000_hw *hw = &adapter->hw; 2916 struct e1000_ring *tx_ring = adapter->tx_ring; 2917 u64 tdba; 2918 u32 tdlen, tctl, tarc; 2919 2920 /* Setup the HW Tx Head and Tail descriptor pointers */ 2921 tdba = tx_ring->dma; 2922 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2923 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2924 ew32(TDBAH(0), (tdba >> 32)); 2925 ew32(TDLEN(0), tdlen); 2926 ew32(TDH(0), 0); 2927 ew32(TDT(0), 0); 2928 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2929 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2930 2931 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2932 e1000e_update_tdt_wa(tx_ring, 0); 2933 2934 /* Set the Tx Interrupt Delay register */ 2935 ew32(TIDV, adapter->tx_int_delay); 2936 /* Tx irq moderation */ 2937 ew32(TADV, adapter->tx_abs_int_delay); 2938 2939 if (adapter->flags2 & FLAG2_DMA_BURST) { 2940 u32 txdctl = er32(TXDCTL(0)); 2941 2942 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2943 E1000_TXDCTL_WTHRESH); 2944 /* set up some performance related parameters to encourage the 2945 * hardware to use the bus more efficiently in bursts, depends 2946 * on the tx_int_delay to be enabled, 2947 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2948 * hthresh = 1 ==> prefetch when one or more available 2949 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2950 * BEWARE: this seems to work but should be considered first if 2951 * there are Tx hangs or other Tx related bugs 2952 */ 2953 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2954 ew32(TXDCTL(0), txdctl); 2955 } 2956 /* erratum work around: set txdctl the same for both queues */ 2957 ew32(TXDCTL(1), er32(TXDCTL(0))); 2958 2959 /* Program the Transmit Control Register */ 2960 tctl = er32(TCTL); 2961 tctl &= ~E1000_TCTL_CT; 2962 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2963 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2964 2965 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2966 tarc = er32(TARC(0)); 2967 /* set the speed mode bit, we'll clear it if we're not at 2968 * gigabit link later 2969 */ 2970 #define SPEED_MODE_BIT BIT(21) 2971 tarc |= SPEED_MODE_BIT; 2972 ew32(TARC(0), tarc); 2973 } 2974 2975 /* errata: program both queues to unweighted RR */ 2976 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2977 tarc = er32(TARC(0)); 2978 tarc |= 1; 2979 ew32(TARC(0), tarc); 2980 tarc = er32(TARC(1)); 2981 tarc |= 1; 2982 ew32(TARC(1), tarc); 2983 } 2984 2985 /* Setup Transmit Descriptor Settings for eop descriptor */ 2986 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 2987 2988 /* only set IDE if we are delaying interrupts using the timers */ 2989 if (adapter->tx_int_delay) 2990 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2991 2992 /* enable Report Status bit */ 2993 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2994 2995 ew32(TCTL, tctl); 2996 2997 hw->mac.ops.config_collision_dist(hw); 2998 2999 /* SPT and KBL Si errata workaround to avoid data corruption */ 3000 if (hw->mac.type == e1000_pch_spt) { 3001 u32 reg_val; 3002 3003 reg_val = er32(IOSFPC); 3004 reg_val |= E1000_RCTL_RDMTS_HEX; 3005 ew32(IOSFPC, reg_val); 3006 3007 reg_val = er32(TARC(0)); 3008 /* SPT and KBL Si errata workaround to avoid Tx hang. 3009 * Dropping the number of outstanding requests from 3010 * 3 to 2 in order to avoid a buffer overrun. 3011 */ 3012 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3013 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3014 ew32(TARC(0), reg_val); 3015 } 3016 } 3017 3018 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3019 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3020 3021 /** 3022 * e1000_setup_rctl - configure the receive control registers 3023 * @adapter: Board private structure 3024 **/ 3025 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3026 { 3027 struct e1000_hw *hw = &adapter->hw; 3028 u32 rctl, rfctl; 3029 u32 pages = 0; 3030 3031 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3032 * If jumbo frames not set, program related MAC/PHY registers 3033 * to h/w defaults 3034 */ 3035 if (hw->mac.type >= e1000_pch2lan) { 3036 s32 ret_val; 3037 3038 if (adapter->netdev->mtu > ETH_DATA_LEN) 3039 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3040 else 3041 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3042 3043 if (ret_val) 3044 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3045 } 3046 3047 /* Program MC offset vector base */ 3048 rctl = er32(RCTL); 3049 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3050 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3051 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3052 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3053 3054 /* Do not Store bad packets */ 3055 rctl &= ~E1000_RCTL_SBP; 3056 3057 /* Enable Long Packet receive */ 3058 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3059 rctl &= ~E1000_RCTL_LPE; 3060 else 3061 rctl |= E1000_RCTL_LPE; 3062 3063 /* Some systems expect that the CRC is included in SMBUS traffic. The 3064 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3065 * host memory when this is enabled 3066 */ 3067 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3068 rctl |= E1000_RCTL_SECRC; 3069 3070 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3071 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3072 u16 phy_data; 3073 3074 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3075 phy_data &= 0xfff8; 3076 phy_data |= BIT(2); 3077 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3078 3079 e1e_rphy(hw, 22, &phy_data); 3080 phy_data &= 0x0fff; 3081 phy_data |= BIT(14); 3082 e1e_wphy(hw, 0x10, 0x2823); 3083 e1e_wphy(hw, 0x11, 0x0003); 3084 e1e_wphy(hw, 22, phy_data); 3085 } 3086 3087 /* Setup buffer sizes */ 3088 rctl &= ~E1000_RCTL_SZ_4096; 3089 rctl |= E1000_RCTL_BSEX; 3090 switch (adapter->rx_buffer_len) { 3091 case 2048: 3092 default: 3093 rctl |= E1000_RCTL_SZ_2048; 3094 rctl &= ~E1000_RCTL_BSEX; 3095 break; 3096 case 4096: 3097 rctl |= E1000_RCTL_SZ_4096; 3098 break; 3099 case 8192: 3100 rctl |= E1000_RCTL_SZ_8192; 3101 break; 3102 case 16384: 3103 rctl |= E1000_RCTL_SZ_16384; 3104 break; 3105 } 3106 3107 /* Enable Extended Status in all Receive Descriptors */ 3108 rfctl = er32(RFCTL); 3109 rfctl |= E1000_RFCTL_EXTEN; 3110 ew32(RFCTL, rfctl); 3111 3112 /* 82571 and greater support packet-split where the protocol 3113 * header is placed in skb->data and the packet data is 3114 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3115 * In the case of a non-split, skb->data is linearly filled, 3116 * followed by the page buffers. Therefore, skb->data is 3117 * sized to hold the largest protocol header. 3118 * 3119 * allocations using alloc_page take too long for regular MTU 3120 * so only enable packet split for jumbo frames 3121 * 3122 * Using pages when the page size is greater than 16k wastes 3123 * a lot of memory, since we allocate 3 pages at all times 3124 * per packet. 3125 */ 3126 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3127 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3128 adapter->rx_ps_pages = pages; 3129 else 3130 adapter->rx_ps_pages = 0; 3131 3132 if (adapter->rx_ps_pages) { 3133 u32 psrctl = 0; 3134 3135 /* Enable Packet split descriptors */ 3136 rctl |= E1000_RCTL_DTYP_PS; 3137 3138 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3139 3140 switch (adapter->rx_ps_pages) { 3141 case 3: 3142 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3143 fallthrough; 3144 case 2: 3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3146 fallthrough; 3147 case 1: 3148 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3149 break; 3150 } 3151 3152 ew32(PSRCTL, psrctl); 3153 } 3154 3155 /* This is useful for sniffing bad packets. */ 3156 if (adapter->netdev->features & NETIF_F_RXALL) { 3157 /* UPE and MPE will be handled by normal PROMISC logic 3158 * in e1000e_set_rx_mode 3159 */ 3160 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3161 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3162 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3163 3164 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3165 E1000_RCTL_DPF | /* Allow filtered pause */ 3166 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3167 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3168 * and that breaks VLANs. 3169 */ 3170 } 3171 3172 ew32(RCTL, rctl); 3173 /* just started the receive unit, no need to restart */ 3174 adapter->flags &= ~FLAG_RESTART_NOW; 3175 } 3176 3177 /** 3178 * e1000_configure_rx - Configure Receive Unit after Reset 3179 * @adapter: board private structure 3180 * 3181 * Configure the Rx unit of the MAC after a reset. 3182 **/ 3183 static void e1000_configure_rx(struct e1000_adapter *adapter) 3184 { 3185 struct e1000_hw *hw = &adapter->hw; 3186 struct e1000_ring *rx_ring = adapter->rx_ring; 3187 u64 rdba; 3188 u32 rdlen, rctl, rxcsum, ctrl_ext; 3189 3190 if (adapter->rx_ps_pages) { 3191 /* this is a 32 byte descriptor */ 3192 rdlen = rx_ring->count * 3193 sizeof(union e1000_rx_desc_packet_split); 3194 adapter->clean_rx = e1000_clean_rx_irq_ps; 3195 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3196 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3197 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3198 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3199 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3200 } else { 3201 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3202 adapter->clean_rx = e1000_clean_rx_irq; 3203 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3204 } 3205 3206 /* disable receives while setting up the descriptors */ 3207 rctl = er32(RCTL); 3208 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3209 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3210 e1e_flush(); 3211 usleep_range(10000, 11000); 3212 3213 if (adapter->flags2 & FLAG2_DMA_BURST) { 3214 /* set the writeback threshold (only takes effect if the RDTR 3215 * is set). set GRAN=1 and write back up to 0x4 worth, and 3216 * enable prefetching of 0x20 Rx descriptors 3217 * granularity = 01 3218 * wthresh = 04, 3219 * hthresh = 04, 3220 * pthresh = 0x20 3221 */ 3222 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3223 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3224 } 3225 3226 /* set the Receive Delay Timer Register */ 3227 ew32(RDTR, adapter->rx_int_delay); 3228 3229 /* irq moderation */ 3230 ew32(RADV, adapter->rx_abs_int_delay); 3231 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3232 e1000e_write_itr(adapter, adapter->itr); 3233 3234 ctrl_ext = er32(CTRL_EXT); 3235 /* Auto-Mask interrupts upon ICR access */ 3236 ctrl_ext |= E1000_CTRL_EXT_IAME; 3237 ew32(IAM, 0xffffffff); 3238 ew32(CTRL_EXT, ctrl_ext); 3239 e1e_flush(); 3240 3241 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3242 * the Base and Length of the Rx Descriptor Ring 3243 */ 3244 rdba = rx_ring->dma; 3245 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3246 ew32(RDBAH(0), (rdba >> 32)); 3247 ew32(RDLEN(0), rdlen); 3248 ew32(RDH(0), 0); 3249 ew32(RDT(0), 0); 3250 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3251 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3252 3253 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3254 e1000e_update_rdt_wa(rx_ring, 0); 3255 3256 /* Enable Receive Checksum Offload for TCP and UDP */ 3257 rxcsum = er32(RXCSUM); 3258 if (adapter->netdev->features & NETIF_F_RXCSUM) 3259 rxcsum |= E1000_RXCSUM_TUOFL; 3260 else 3261 rxcsum &= ~E1000_RXCSUM_TUOFL; 3262 ew32(RXCSUM, rxcsum); 3263 3264 /* With jumbo frames, excessive C-state transition latencies result 3265 * in dropped transactions. 3266 */ 3267 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3268 u32 lat = 3269 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3270 adapter->max_frame_size) * 8 / 1000; 3271 3272 if (adapter->flags & FLAG_IS_ICH) { 3273 u32 rxdctl = er32(RXDCTL(0)); 3274 3275 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3276 } 3277 3278 dev_info(&adapter->pdev->dev, 3279 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3280 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat); 3281 } else { 3282 cpu_latency_qos_update_request(&adapter->pm_qos_req, 3283 PM_QOS_DEFAULT_VALUE); 3284 } 3285 3286 /* Enable Receives */ 3287 ew32(RCTL, rctl); 3288 } 3289 3290 /** 3291 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3292 * @netdev: network interface device structure 3293 * 3294 * Writes multicast address list to the MTA hash table. 3295 * Returns: -ENOMEM on failure 3296 * 0 on no addresses written 3297 * X on writing X addresses to MTA 3298 */ 3299 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3300 { 3301 struct e1000_adapter *adapter = netdev_priv(netdev); 3302 struct e1000_hw *hw = &adapter->hw; 3303 struct netdev_hw_addr *ha; 3304 u8 *mta_list; 3305 int i; 3306 3307 if (netdev_mc_empty(netdev)) { 3308 /* nothing to program, so clear mc list */ 3309 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3310 return 0; 3311 } 3312 3313 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3314 if (!mta_list) 3315 return -ENOMEM; 3316 3317 /* update_mc_addr_list expects a packed array of only addresses. */ 3318 i = 0; 3319 netdev_for_each_mc_addr(ha, netdev) 3320 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3321 3322 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3323 kfree(mta_list); 3324 3325 return netdev_mc_count(netdev); 3326 } 3327 3328 /** 3329 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3330 * @netdev: network interface device structure 3331 * 3332 * Writes unicast address list to the RAR table. 3333 * Returns: -ENOMEM on failure/insufficient address space 3334 * 0 on no addresses written 3335 * X on writing X addresses to the RAR table 3336 **/ 3337 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3338 { 3339 struct e1000_adapter *adapter = netdev_priv(netdev); 3340 struct e1000_hw *hw = &adapter->hw; 3341 unsigned int rar_entries; 3342 int count = 0; 3343 3344 rar_entries = hw->mac.ops.rar_get_count(hw); 3345 3346 /* save a rar entry for our hardware address */ 3347 rar_entries--; 3348 3349 /* save a rar entry for the LAA workaround */ 3350 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3351 rar_entries--; 3352 3353 /* return ENOMEM indicating insufficient memory for addresses */ 3354 if (netdev_uc_count(netdev) > rar_entries) 3355 return -ENOMEM; 3356 3357 if (!netdev_uc_empty(netdev) && rar_entries) { 3358 struct netdev_hw_addr *ha; 3359 3360 /* write the addresses in reverse order to avoid write 3361 * combining 3362 */ 3363 netdev_for_each_uc_addr(ha, netdev) { 3364 int ret_val; 3365 3366 if (!rar_entries) 3367 break; 3368 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3369 if (ret_val < 0) 3370 return -ENOMEM; 3371 count++; 3372 } 3373 } 3374 3375 /* zero out the remaining RAR entries not used above */ 3376 for (; rar_entries > 0; rar_entries--) { 3377 ew32(RAH(rar_entries), 0); 3378 ew32(RAL(rar_entries), 0); 3379 } 3380 e1e_flush(); 3381 3382 return count; 3383 } 3384 3385 /** 3386 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3387 * @netdev: network interface device structure 3388 * 3389 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3390 * address list or the network interface flags are updated. This routine is 3391 * responsible for configuring the hardware for proper unicast, multicast, 3392 * promiscuous mode, and all-multi behavior. 3393 **/ 3394 static void e1000e_set_rx_mode(struct net_device *netdev) 3395 { 3396 struct e1000_adapter *adapter = netdev_priv(netdev); 3397 struct e1000_hw *hw = &adapter->hw; 3398 u32 rctl; 3399 3400 if (pm_runtime_suspended(netdev->dev.parent)) 3401 return; 3402 3403 /* Check for Promiscuous and All Multicast modes */ 3404 rctl = er32(RCTL); 3405 3406 /* clear the affected bits */ 3407 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3408 3409 if (netdev->flags & IFF_PROMISC) { 3410 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3411 /* Do not hardware filter VLANs in promisc mode */ 3412 e1000e_vlan_filter_disable(adapter); 3413 } else { 3414 int count; 3415 3416 if (netdev->flags & IFF_ALLMULTI) { 3417 rctl |= E1000_RCTL_MPE; 3418 } else { 3419 /* Write addresses to the MTA, if the attempt fails 3420 * then we should just turn on promiscuous mode so 3421 * that we can at least receive multicast traffic 3422 */ 3423 count = e1000e_write_mc_addr_list(netdev); 3424 if (count < 0) 3425 rctl |= E1000_RCTL_MPE; 3426 } 3427 e1000e_vlan_filter_enable(adapter); 3428 /* Write addresses to available RAR registers, if there is not 3429 * sufficient space to store all the addresses then enable 3430 * unicast promiscuous mode 3431 */ 3432 count = e1000e_write_uc_addr_list(netdev); 3433 if (count < 0) 3434 rctl |= E1000_RCTL_UPE; 3435 } 3436 3437 ew32(RCTL, rctl); 3438 3439 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3440 e1000e_vlan_strip_enable(adapter); 3441 else 3442 e1000e_vlan_strip_disable(adapter); 3443 } 3444 3445 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3446 { 3447 struct e1000_hw *hw = &adapter->hw; 3448 u32 mrqc, rxcsum; 3449 u32 rss_key[10]; 3450 int i; 3451 3452 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3453 for (i = 0; i < 10; i++) 3454 ew32(RSSRK(i), rss_key[i]); 3455 3456 /* Direct all traffic to queue 0 */ 3457 for (i = 0; i < 32; i++) 3458 ew32(RETA(i), 0); 3459 3460 /* Disable raw packet checksumming so that RSS hash is placed in 3461 * descriptor on writeback. 3462 */ 3463 rxcsum = er32(RXCSUM); 3464 rxcsum |= E1000_RXCSUM_PCSD; 3465 3466 ew32(RXCSUM, rxcsum); 3467 3468 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3469 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3470 E1000_MRQC_RSS_FIELD_IPV6 | 3471 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3472 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3473 3474 ew32(MRQC, mrqc); 3475 } 3476 3477 /** 3478 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3479 * @adapter: board private structure 3480 * @timinca: pointer to returned time increment attributes 3481 * 3482 * Get attributes for incrementing the System Time Register SYSTIML/H at 3483 * the default base frequency, and set the cyclecounter shift value. 3484 **/ 3485 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3486 { 3487 struct e1000_hw *hw = &adapter->hw; 3488 u32 incvalue, incperiod, shift; 3489 3490 /* Make sure clock is enabled on I217/I218/I219 before checking 3491 * the frequency 3492 */ 3493 if ((hw->mac.type >= e1000_pch_lpt) && 3494 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3495 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3496 u32 fextnvm7 = er32(FEXTNVM7); 3497 3498 if (!(fextnvm7 & BIT(0))) { 3499 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3500 e1e_flush(); 3501 } 3502 } 3503 3504 switch (hw->mac.type) { 3505 case e1000_pch2lan: 3506 /* Stable 96MHz frequency */ 3507 incperiod = INCPERIOD_96MHZ; 3508 incvalue = INCVALUE_96MHZ; 3509 shift = INCVALUE_SHIFT_96MHZ; 3510 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3511 break; 3512 case e1000_pch_lpt: 3513 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3514 /* Stable 96MHz frequency */ 3515 incperiod = INCPERIOD_96MHZ; 3516 incvalue = INCVALUE_96MHZ; 3517 shift = INCVALUE_SHIFT_96MHZ; 3518 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3519 } else { 3520 /* Stable 25MHz frequency */ 3521 incperiod = INCPERIOD_25MHZ; 3522 incvalue = INCVALUE_25MHZ; 3523 shift = INCVALUE_SHIFT_25MHZ; 3524 adapter->cc.shift = shift; 3525 } 3526 break; 3527 case e1000_pch_spt: 3528 /* Stable 24MHz frequency */ 3529 incperiod = INCPERIOD_24MHZ; 3530 incvalue = INCVALUE_24MHZ; 3531 shift = INCVALUE_SHIFT_24MHZ; 3532 adapter->cc.shift = shift; 3533 break; 3534 case e1000_pch_cnp: 3535 case e1000_pch_tgp: 3536 case e1000_pch_adp: 3537 case e1000_pch_mtp: 3538 case e1000_pch_lnp: 3539 case e1000_pch_ptp: 3540 case e1000_pch_nvp: 3541 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3542 /* Stable 24MHz frequency */ 3543 incperiod = INCPERIOD_24MHZ; 3544 incvalue = INCVALUE_24MHZ; 3545 shift = INCVALUE_SHIFT_24MHZ; 3546 adapter->cc.shift = shift; 3547 } else { 3548 /* Stable 38400KHz frequency */ 3549 incperiod = INCPERIOD_38400KHZ; 3550 incvalue = INCVALUE_38400KHZ; 3551 shift = INCVALUE_SHIFT_38400KHZ; 3552 adapter->cc.shift = shift; 3553 } 3554 break; 3555 case e1000_82574: 3556 case e1000_82583: 3557 /* Stable 25MHz frequency */ 3558 incperiod = INCPERIOD_25MHZ; 3559 incvalue = INCVALUE_25MHZ; 3560 shift = INCVALUE_SHIFT_25MHZ; 3561 adapter->cc.shift = shift; 3562 break; 3563 default: 3564 return -EINVAL; 3565 } 3566 3567 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3568 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3569 3570 return 0; 3571 } 3572 3573 /** 3574 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3575 * @adapter: board private structure 3576 * @config: timestamp configuration 3577 * @extack: netlink extended ACK for error report 3578 * 3579 * Outgoing time stamping can be enabled and disabled. Play nice and 3580 * disable it when requested, although it shouldn't cause any overhead 3581 * when no packet needs it. At most one packet in the queue may be 3582 * marked for time stamping, otherwise it would be impossible to tell 3583 * for sure to which packet the hardware time stamp belongs. 3584 * 3585 * Incoming time stamping has to be configured via the hardware filters. 3586 * Not all combinations are supported, in particular event type has to be 3587 * specified. Matching the kind of event packet is not supported, with the 3588 * exception of "all V2 events regardless of level 2 or 4". 3589 **/ 3590 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3591 struct kernel_hwtstamp_config *config, 3592 struct netlink_ext_ack *extack) 3593 { 3594 struct e1000_hw *hw = &adapter->hw; 3595 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3596 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3597 u32 rxmtrl = 0; 3598 u16 rxudp = 0; 3599 bool is_l4 = false; 3600 bool is_l2 = false; 3601 u32 regval; 3602 3603 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 3604 NL_SET_ERR_MSG(extack, "No HW timestamp support"); 3605 return -EINVAL; 3606 } 3607 3608 switch (config->tx_type) { 3609 case HWTSTAMP_TX_OFF: 3610 tsync_tx_ctl = 0; 3611 break; 3612 case HWTSTAMP_TX_ON: 3613 break; 3614 default: 3615 NL_SET_ERR_MSG(extack, "Unsupported TX HW timestamp type"); 3616 return -ERANGE; 3617 } 3618 3619 switch (config->rx_filter) { 3620 case HWTSTAMP_FILTER_NONE: 3621 tsync_rx_ctl = 0; 3622 break; 3623 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3624 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3625 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3626 is_l4 = true; 3627 break; 3628 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3629 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3630 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3631 is_l4 = true; 3632 break; 3633 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3634 /* Also time stamps V2 L2 Path Delay Request/Response */ 3635 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3636 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3637 is_l2 = true; 3638 break; 3639 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3640 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3641 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3642 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3643 is_l2 = true; 3644 break; 3645 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3646 /* Hardware cannot filter just V2 L4 Sync messages */ 3647 fallthrough; 3648 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3649 /* Also time stamps V2 Path Delay Request/Response. */ 3650 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3651 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3652 is_l2 = true; 3653 is_l4 = true; 3654 break; 3655 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3656 /* Hardware cannot filter just V2 L4 Delay Request messages */ 3657 fallthrough; 3658 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3659 /* Also time stamps V2 Path Delay Request/Response. */ 3660 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3661 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3662 is_l2 = true; 3663 is_l4 = true; 3664 break; 3665 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3666 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3667 /* Hardware cannot filter just V2 L4 or L2 Event messages */ 3668 fallthrough; 3669 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3670 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3671 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3672 is_l2 = true; 3673 is_l4 = true; 3674 break; 3675 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3676 /* For V1, the hardware can only filter Sync messages or 3677 * Delay Request messages but not both so fall-through to 3678 * time stamp all packets. 3679 */ 3680 fallthrough; 3681 case HWTSTAMP_FILTER_NTP_ALL: 3682 case HWTSTAMP_FILTER_ALL: 3683 is_l2 = true; 3684 is_l4 = true; 3685 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3686 config->rx_filter = HWTSTAMP_FILTER_ALL; 3687 break; 3688 default: 3689 NL_SET_ERR_MSG(extack, "Unsupported RX HW timestamp filter"); 3690 return -ERANGE; 3691 } 3692 3693 adapter->hwtstamp_config = *config; 3694 3695 /* enable/disable Tx h/w time stamping */ 3696 regval = er32(TSYNCTXCTL); 3697 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3698 regval |= tsync_tx_ctl; 3699 ew32(TSYNCTXCTL, regval); 3700 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3701 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3702 NL_SET_ERR_MSG(extack, 3703 "Timesync Tx Control register not set as expected"); 3704 return -EAGAIN; 3705 } 3706 3707 /* enable/disable Rx h/w time stamping */ 3708 regval = er32(TSYNCRXCTL); 3709 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3710 regval |= tsync_rx_ctl; 3711 ew32(TSYNCRXCTL, regval); 3712 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3713 E1000_TSYNCRXCTL_TYPE_MASK)) != 3714 (regval & (E1000_TSYNCRXCTL_ENABLED | 3715 E1000_TSYNCRXCTL_TYPE_MASK))) { 3716 NL_SET_ERR_MSG(extack, 3717 "Timesync Rx Control register not set as expected"); 3718 return -EAGAIN; 3719 } 3720 3721 /* L2: define ethertype filter for time stamped packets */ 3722 if (is_l2) 3723 rxmtrl |= ETH_P_1588; 3724 3725 /* define which PTP packets get time stamped */ 3726 ew32(RXMTRL, rxmtrl); 3727 3728 /* Filter by destination port */ 3729 if (is_l4) { 3730 rxudp = PTP_EV_PORT; 3731 cpu_to_be16s(&rxudp); 3732 } 3733 ew32(RXUDP, rxudp); 3734 3735 e1e_flush(); 3736 3737 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3738 er32(RXSTMPH); 3739 er32(TXSTMPH); 3740 3741 return 0; 3742 } 3743 3744 /** 3745 * e1000_configure - configure the hardware for Rx and Tx 3746 * @adapter: private board structure 3747 **/ 3748 static void e1000_configure(struct e1000_adapter *adapter) 3749 { 3750 struct e1000_ring *rx_ring = adapter->rx_ring; 3751 3752 e1000e_set_rx_mode(adapter->netdev); 3753 3754 e1000_restore_vlan(adapter); 3755 e1000_init_manageability_pt(adapter); 3756 3757 e1000_configure_tx(adapter); 3758 3759 if (adapter->netdev->features & NETIF_F_RXHASH) 3760 e1000e_setup_rss_hash(adapter); 3761 e1000_setup_rctl(adapter); 3762 e1000_configure_rx(adapter); 3763 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3764 } 3765 3766 /** 3767 * e1000e_power_up_phy - restore link in case the phy was powered down 3768 * @adapter: address of board private structure 3769 * 3770 * The phy may be powered down to save power and turn off link when the 3771 * driver is unloaded and wake on lan is not enabled (among others) 3772 * *** this routine MUST be followed by a call to e1000e_reset *** 3773 **/ 3774 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3775 { 3776 if (adapter->hw.phy.ops.power_up) 3777 adapter->hw.phy.ops.power_up(&adapter->hw); 3778 3779 adapter->hw.mac.ops.setup_link(&adapter->hw); 3780 } 3781 3782 /** 3783 * e1000_power_down_phy - Power down the PHY 3784 * @adapter: board private structure 3785 * 3786 * Power down the PHY so no link is implied when interface is down. 3787 * The PHY cannot be powered down if management or WoL is active. 3788 */ 3789 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3790 { 3791 if (adapter->hw.phy.ops.power_down) 3792 adapter->hw.phy.ops.power_down(&adapter->hw); 3793 } 3794 3795 /** 3796 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3797 * @adapter: board private structure 3798 * 3799 * We want to clear all pending descriptors from the TX ring. 3800 * zeroing happens when the HW reads the regs. We assign the ring itself as 3801 * the data of the next descriptor. We don't care about the data we are about 3802 * to reset the HW. 3803 */ 3804 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3805 { 3806 struct e1000_hw *hw = &adapter->hw; 3807 struct e1000_ring *tx_ring = adapter->tx_ring; 3808 struct e1000_tx_desc *tx_desc = NULL; 3809 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3810 u16 size = 512; 3811 3812 tctl = er32(TCTL); 3813 ew32(TCTL, tctl | E1000_TCTL_EN); 3814 tdt = er32(TDT(0)); 3815 BUG_ON(tdt != tx_ring->next_to_use); 3816 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3817 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma); 3818 3819 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3820 tx_desc->upper.data = 0; 3821 /* flush descriptors to memory before notifying the HW */ 3822 wmb(); 3823 tx_ring->next_to_use++; 3824 if (tx_ring->next_to_use == tx_ring->count) 3825 tx_ring->next_to_use = 0; 3826 ew32(TDT(0), tx_ring->next_to_use); 3827 usleep_range(200, 250); 3828 } 3829 3830 /** 3831 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3832 * @adapter: board private structure 3833 * 3834 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3835 */ 3836 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3837 { 3838 u32 rctl, rxdctl; 3839 struct e1000_hw *hw = &adapter->hw; 3840 3841 rctl = er32(RCTL); 3842 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3843 e1e_flush(); 3844 usleep_range(100, 150); 3845 3846 rxdctl = er32(RXDCTL(0)); 3847 /* zero the lower 14 bits (prefetch and host thresholds) */ 3848 rxdctl &= 0xffffc000; 3849 3850 /* update thresholds: prefetch threshold to 31, host threshold to 1 3851 * and make sure the granularity is "descriptors" and not "cache lines" 3852 */ 3853 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3854 3855 ew32(RXDCTL(0), rxdctl); 3856 /* momentarily enable the RX ring for the changes to take effect */ 3857 ew32(RCTL, rctl | E1000_RCTL_EN); 3858 e1e_flush(); 3859 usleep_range(100, 150); 3860 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3861 } 3862 3863 /** 3864 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3865 * @adapter: board private structure 3866 * 3867 * In i219, the descriptor rings must be emptied before resetting the HW 3868 * or before changing the device state to D3 during runtime (runtime PM). 3869 * 3870 * Failure to do this will cause the HW to enter a unit hang state which can 3871 * only be released by PCI reset on the device 3872 * 3873 */ 3874 3875 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3876 { 3877 u16 hang_state; 3878 u32 fext_nvm11, tdlen; 3879 struct e1000_hw *hw = &adapter->hw; 3880 3881 /* First, disable MULR fix in FEXTNVM11 */ 3882 fext_nvm11 = er32(FEXTNVM11); 3883 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3884 ew32(FEXTNVM11, fext_nvm11); 3885 /* do nothing if we're not in faulty state, or if the queue is empty */ 3886 tdlen = er32(TDLEN(0)); 3887 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3888 &hang_state); 3889 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3890 return; 3891 e1000_flush_tx_ring(adapter); 3892 /* recheck, maybe the fault is caused by the rx ring */ 3893 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3894 &hang_state); 3895 if (hang_state & FLUSH_DESC_REQUIRED) 3896 e1000_flush_rx_ring(adapter); 3897 } 3898 3899 /** 3900 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3901 * @adapter: board private structure 3902 * 3903 * When the MAC is reset, all hardware bits for timesync will be reset to the 3904 * default values. This function will restore the settings last in place. 3905 * Since the clock SYSTIME registers are reset, we will simply restore the 3906 * cyclecounter to the kernel real clock time. 3907 **/ 3908 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3909 { 3910 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3911 struct e1000_hw *hw = &adapter->hw; 3912 struct netlink_ext_ack extack = {}; 3913 unsigned long flags; 3914 u32 timinca; 3915 s32 ret_val; 3916 3917 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3918 return; 3919 3920 if (info->adjfine) { 3921 /* restore the previous ptp frequency delta */ 3922 ret_val = info->adjfine(info, adapter->ptp_delta); 3923 } else { 3924 /* set the default base frequency if no adjustment possible */ 3925 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3926 if (!ret_val) 3927 ew32(TIMINCA, timinca); 3928 } 3929 3930 if (ret_val) { 3931 dev_warn(&adapter->pdev->dev, 3932 "Failed to restore TIMINCA clock rate delta: %d\n", 3933 ret_val); 3934 return; 3935 } 3936 3937 /* reset the systim ns time counter */ 3938 spin_lock_irqsave(&adapter->systim_lock, flags); 3939 timecounter_init(&adapter->tc, &adapter->cc, 3940 ktime_to_ns(ktime_get_real())); 3941 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3942 3943 /* restore the previous hwtstamp configuration settings */ 3944 ret_val = e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config, 3945 &extack); 3946 if (ret_val) { 3947 if (extack._msg) 3948 e_err("%s\n", extack._msg); 3949 } 3950 } 3951 3952 /** 3953 * e1000e_reset - bring the hardware into a known good state 3954 * @adapter: board private structure 3955 * 3956 * This function boots the hardware and enables some settings that 3957 * require a configuration cycle of the hardware - those cannot be 3958 * set/changed during runtime. After reset the device needs to be 3959 * properly configured for Rx, Tx etc. 3960 */ 3961 void e1000e_reset(struct e1000_adapter *adapter) 3962 { 3963 struct e1000_mac_info *mac = &adapter->hw.mac; 3964 struct e1000_fc_info *fc = &adapter->hw.fc; 3965 struct e1000_hw *hw = &adapter->hw; 3966 u32 tx_space, min_tx_space, min_rx_space; 3967 u32 pba = adapter->pba; 3968 u16 hwm; 3969 3970 /* reset Packet Buffer Allocation to default */ 3971 ew32(PBA, pba); 3972 3973 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3974 /* To maintain wire speed transmits, the Tx FIFO should be 3975 * large enough to accommodate two full transmit packets, 3976 * rounded up to the next 1KB and expressed in KB. Likewise, 3977 * the Rx FIFO should be large enough to accommodate at least 3978 * one full receive packet and is similarly rounded up and 3979 * expressed in KB. 3980 */ 3981 pba = er32(PBA); 3982 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3983 tx_space = pba >> 16; 3984 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3985 pba &= 0xffff; 3986 /* the Tx fifo also stores 16 bytes of information about the Tx 3987 * but don't include ethernet FCS because hardware appends it 3988 */ 3989 min_tx_space = (adapter->max_frame_size + 3990 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 3991 min_tx_space = ALIGN(min_tx_space, 1024); 3992 min_tx_space >>= 10; 3993 /* software strips receive CRC, so leave room for it */ 3994 min_rx_space = adapter->max_frame_size; 3995 min_rx_space = ALIGN(min_rx_space, 1024); 3996 min_rx_space >>= 10; 3997 3998 /* If current Tx allocation is less than the min Tx FIFO size, 3999 * and the min Tx FIFO size is less than the current Rx FIFO 4000 * allocation, take space away from current Rx allocation 4001 */ 4002 if ((tx_space < min_tx_space) && 4003 ((min_tx_space - tx_space) < pba)) { 4004 pba -= min_tx_space - tx_space; 4005 4006 /* if short on Rx space, Rx wins and must trump Tx 4007 * adjustment 4008 */ 4009 if (pba < min_rx_space) 4010 pba = min_rx_space; 4011 } 4012 4013 ew32(PBA, pba); 4014 } 4015 4016 /* flow control settings 4017 * 4018 * The high water mark must be low enough to fit one full frame 4019 * (or the size used for early receive) above it in the Rx FIFO. 4020 * Set it to the lower of: 4021 * - 90% of the Rx FIFO size, and 4022 * - the full Rx FIFO size minus one full frame 4023 */ 4024 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4025 fc->pause_time = 0xFFFF; 4026 else 4027 fc->pause_time = E1000_FC_PAUSE_TIME; 4028 fc->send_xon = true; 4029 fc->current_mode = fc->requested_mode; 4030 4031 switch (hw->mac.type) { 4032 case e1000_ich9lan: 4033 case e1000_ich10lan: 4034 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4035 pba = 14; 4036 ew32(PBA, pba); 4037 fc->high_water = 0x2800; 4038 fc->low_water = fc->high_water - 8; 4039 break; 4040 } 4041 fallthrough; 4042 default: 4043 hwm = min(((pba << 10) * 9 / 10), 4044 ((pba << 10) - adapter->max_frame_size)); 4045 4046 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4047 fc->low_water = fc->high_water - 8; 4048 break; 4049 case e1000_pchlan: 4050 /* Workaround PCH LOM adapter hangs with certain network 4051 * loads. If hangs persist, try disabling Tx flow control. 4052 */ 4053 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4054 fc->high_water = 0x3500; 4055 fc->low_water = 0x1500; 4056 } else { 4057 fc->high_water = 0x5000; 4058 fc->low_water = 0x3000; 4059 } 4060 fc->refresh_time = 0x1000; 4061 break; 4062 case e1000_pch2lan: 4063 case e1000_pch_lpt: 4064 case e1000_pch_spt: 4065 case e1000_pch_cnp: 4066 case e1000_pch_tgp: 4067 case e1000_pch_adp: 4068 case e1000_pch_mtp: 4069 case e1000_pch_lnp: 4070 case e1000_pch_ptp: 4071 case e1000_pch_nvp: 4072 fc->refresh_time = 0xFFFF; 4073 fc->pause_time = 0xFFFF; 4074 4075 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4076 fc->high_water = 0x05C20; 4077 fc->low_water = 0x05048; 4078 break; 4079 } 4080 4081 pba = 14; 4082 ew32(PBA, pba); 4083 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4084 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4085 break; 4086 } 4087 4088 /* Alignment of Tx data is on an arbitrary byte boundary with the 4089 * maximum size per Tx descriptor limited only to the transmit 4090 * allocation of the packet buffer minus 96 bytes with an upper 4091 * limit of 24KB due to receive synchronization limitations. 4092 */ 4093 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4094 24 << 10); 4095 4096 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4097 * fit in receive buffer. 4098 */ 4099 if (adapter->itr_setting & 0x3) { 4100 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4101 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4102 dev_info(&adapter->pdev->dev, 4103 "Interrupt Throttle Rate off\n"); 4104 adapter->flags2 |= FLAG2_DISABLE_AIM; 4105 e1000e_write_itr(adapter, 0); 4106 } 4107 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4108 dev_info(&adapter->pdev->dev, 4109 "Interrupt Throttle Rate on\n"); 4110 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4111 adapter->itr = 20000; 4112 e1000e_write_itr(adapter, adapter->itr); 4113 } 4114 } 4115 4116 if (hw->mac.type >= e1000_pch_spt) 4117 e1000_flush_desc_rings(adapter); 4118 /* Allow time for pending master requests to run */ 4119 mac->ops.reset_hw(hw); 4120 4121 /* For parts with AMT enabled, let the firmware know 4122 * that the network interface is in control 4123 */ 4124 if (adapter->flags & FLAG_HAS_AMT) 4125 e1000e_get_hw_control(adapter); 4126 4127 ew32(WUC, 0); 4128 4129 if (mac->ops.init_hw(hw)) 4130 e_err("Hardware Error\n"); 4131 4132 e1000_update_mng_vlan(adapter); 4133 4134 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4135 ew32(VET, ETH_P_8021Q); 4136 4137 e1000e_reset_adaptive(hw); 4138 4139 /* restore systim and hwtstamp settings */ 4140 e1000e_systim_reset(adapter); 4141 4142 /* Set EEE advertisement as appropriate */ 4143 if (adapter->flags2 & FLAG2_HAS_EEE) { 4144 s32 ret_val; 4145 u16 adv_addr; 4146 4147 switch (hw->phy.type) { 4148 case e1000_phy_82579: 4149 adv_addr = I82579_EEE_ADVERTISEMENT; 4150 break; 4151 case e1000_phy_i217: 4152 adv_addr = I217_EEE_ADVERTISEMENT; 4153 break; 4154 default: 4155 dev_err(&adapter->pdev->dev, 4156 "Invalid PHY type setting EEE advertisement\n"); 4157 return; 4158 } 4159 4160 ret_val = hw->phy.ops.acquire(hw); 4161 if (ret_val) { 4162 dev_err(&adapter->pdev->dev, 4163 "EEE advertisement - unable to acquire PHY\n"); 4164 return; 4165 } 4166 4167 e1000_write_emi_reg_locked(hw, adv_addr, 4168 hw->dev_spec.ich8lan.eee_disable ? 4169 0 : adapter->eee_advert); 4170 4171 hw->phy.ops.release(hw); 4172 } 4173 4174 if (!netif_running(adapter->netdev) && 4175 !test_bit(__E1000_TESTING, &adapter->state)) 4176 e1000_power_down_phy(adapter); 4177 4178 e1000_get_phy_info(hw); 4179 4180 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4181 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4182 u16 phy_data = 0; 4183 /* speed up time to link by disabling smart power down, ignore 4184 * the return value of this function because there is nothing 4185 * different we would do if it failed 4186 */ 4187 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4188 phy_data &= ~IGP02E1000_PM_SPD; 4189 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4190 } 4191 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4192 u32 reg; 4193 4194 /* Fextnvm7 @ 0xe4[2] = 1 */ 4195 reg = er32(FEXTNVM7); 4196 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4197 ew32(FEXTNVM7, reg); 4198 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4199 reg = er32(FEXTNVM9); 4200 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4201 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4202 ew32(FEXTNVM9, reg); 4203 } 4204 4205 } 4206 4207 /** 4208 * e1000e_trigger_lsc - trigger an LSC interrupt 4209 * @adapter: board private structure 4210 * 4211 * Fire a link status change interrupt to start the watchdog. 4212 **/ 4213 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4214 { 4215 struct e1000_hw *hw = &adapter->hw; 4216 4217 if (adapter->msix_entries) 4218 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4219 else 4220 ew32(ICS, E1000_ICS_LSC); 4221 } 4222 4223 void e1000e_up(struct e1000_adapter *adapter) 4224 { 4225 /* hardware has been reset, we need to reload some things */ 4226 e1000_configure(adapter); 4227 4228 clear_bit(__E1000_DOWN, &adapter->state); 4229 4230 if (adapter->msix_entries) 4231 e1000_configure_msix(adapter); 4232 e1000_irq_enable(adapter); 4233 4234 /* Tx queue started by watchdog timer when link is up */ 4235 4236 e1000e_trigger_lsc(adapter); 4237 } 4238 4239 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4240 { 4241 struct e1000_hw *hw = &adapter->hw; 4242 4243 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4244 return; 4245 4246 /* flush pending descriptor writebacks to memory */ 4247 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4248 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4249 4250 /* execute the writes immediately */ 4251 e1e_flush(); 4252 4253 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4254 * write is successful 4255 */ 4256 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4257 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4258 4259 /* execute the writes immediately */ 4260 e1e_flush(); 4261 } 4262 4263 static void e1000e_update_stats(struct e1000_adapter *adapter); 4264 4265 /** 4266 * e1000e_down - quiesce the device and optionally reset the hardware 4267 * @adapter: board private structure 4268 * @reset: boolean flag to reset the hardware or not 4269 */ 4270 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4271 { 4272 struct net_device *netdev = adapter->netdev; 4273 struct e1000_hw *hw = &adapter->hw; 4274 u32 tctl, rctl; 4275 4276 /* signal that we're down so the interrupt handler does not 4277 * reschedule our watchdog timer 4278 */ 4279 set_bit(__E1000_DOWN, &adapter->state); 4280 4281 netif_carrier_off(netdev); 4282 4283 /* disable receives in the hardware */ 4284 rctl = er32(RCTL); 4285 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4286 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4287 /* flush and sleep below */ 4288 4289 netif_stop_queue(netdev); 4290 4291 /* disable transmits in the hardware */ 4292 tctl = er32(TCTL); 4293 tctl &= ~E1000_TCTL_EN; 4294 ew32(TCTL, tctl); 4295 4296 /* flush both disables and wait for them to finish */ 4297 e1e_flush(); 4298 usleep_range(10000, 11000); 4299 4300 e1000_irq_disable(adapter); 4301 4302 napi_synchronize(&adapter->napi); 4303 4304 timer_delete_sync(&adapter->watchdog_timer); 4305 timer_delete_sync(&adapter->phy_info_timer); 4306 4307 spin_lock(&adapter->stats64_lock); 4308 e1000e_update_stats(adapter); 4309 spin_unlock(&adapter->stats64_lock); 4310 4311 e1000e_flush_descriptors(adapter); 4312 4313 adapter->link_speed = 0; 4314 adapter->link_duplex = 0; 4315 4316 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4317 if ((hw->mac.type >= e1000_pch2lan) && 4318 (adapter->netdev->mtu > ETH_DATA_LEN) && 4319 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4320 e_dbg("failed to disable jumbo frame workaround mode\n"); 4321 4322 if (!pci_channel_offline(adapter->pdev)) { 4323 if (reset) 4324 e1000e_reset(adapter); 4325 else if (hw->mac.type >= e1000_pch_spt) 4326 e1000_flush_desc_rings(adapter); 4327 } 4328 e1000_clean_tx_ring(adapter->tx_ring); 4329 e1000_clean_rx_ring(adapter->rx_ring); 4330 } 4331 4332 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4333 { 4334 might_sleep(); 4335 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4336 usleep_range(1000, 1100); 4337 e1000e_down(adapter, true); 4338 e1000e_up(adapter); 4339 clear_bit(__E1000_RESETTING, &adapter->state); 4340 } 4341 4342 /** 4343 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4344 * @hw: pointer to the HW structure 4345 * @systim: PHC time value read, sanitized and returned 4346 * @sts: structure to hold system time before and after reading SYSTIML, 4347 * may be NULL 4348 * 4349 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4350 * check to see that the time is incrementing at a reasonable 4351 * rate and is a multiple of incvalue. 4352 **/ 4353 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4354 struct ptp_system_timestamp *sts) 4355 { 4356 u64 time_delta, rem, temp; 4357 u64 systim_next; 4358 u32 incvalue; 4359 int i; 4360 4361 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4362 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4363 /* latch SYSTIMH on read of SYSTIML */ 4364 ptp_read_system_prets(sts); 4365 systim_next = (u64)er32(SYSTIML); 4366 ptp_read_system_postts(sts); 4367 systim_next |= (u64)er32(SYSTIMH) << 32; 4368 4369 time_delta = systim_next - systim; 4370 temp = time_delta; 4371 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4372 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4373 4374 systim = systim_next; 4375 4376 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4377 break; 4378 } 4379 4380 return systim; 4381 } 4382 4383 /** 4384 * e1000e_read_systim - read SYSTIM register 4385 * @adapter: board private structure 4386 * @sts: structure which will contain system time before and after reading 4387 * SYSTIML, may be NULL 4388 **/ 4389 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4390 struct ptp_system_timestamp *sts) 4391 { 4392 struct e1000_hw *hw = &adapter->hw; 4393 u32 systimel, systimel_2, systimeh; 4394 u64 systim; 4395 /* SYSTIMH latching upon SYSTIML read does not work well. 4396 * This means that if SYSTIML overflows after we read it but before 4397 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4398 * will experience a huge non linear increment in the systime value 4399 * to fix that we test for overflow and if true, we re-read systime. 4400 */ 4401 ptp_read_system_prets(sts); 4402 systimel = er32(SYSTIML); 4403 ptp_read_system_postts(sts); 4404 systimeh = er32(SYSTIMH); 4405 /* Is systimel is so large that overflow is possible? */ 4406 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4407 ptp_read_system_prets(sts); 4408 systimel_2 = er32(SYSTIML); 4409 ptp_read_system_postts(sts); 4410 if (systimel > systimel_2) { 4411 /* There was an overflow, read again SYSTIMH, and use 4412 * systimel_2 4413 */ 4414 systimeh = er32(SYSTIMH); 4415 systimel = systimel_2; 4416 } 4417 } 4418 systim = (u64)systimel; 4419 systim |= (u64)systimeh << 32; 4420 4421 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4422 systim = e1000e_sanitize_systim(hw, systim, sts); 4423 4424 return systim; 4425 } 4426 4427 /** 4428 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4429 * @cc: cyclecounter structure 4430 **/ 4431 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4432 { 4433 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4434 cc); 4435 4436 return e1000e_read_systim(adapter, NULL); 4437 } 4438 4439 /** 4440 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4441 * @adapter: board private structure to initialize 4442 * 4443 * e1000_sw_init initializes the Adapter private data structure. 4444 * Fields are initialized based on PCI device information and 4445 * OS network device settings (MTU size). 4446 **/ 4447 static int e1000_sw_init(struct e1000_adapter *adapter) 4448 { 4449 struct net_device *netdev = adapter->netdev; 4450 4451 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4452 adapter->rx_ps_bsize0 = 128; 4453 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4454 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4455 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4456 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4457 4458 spin_lock_init(&adapter->stats64_lock); 4459 4460 e1000e_set_interrupt_capability(adapter); 4461 4462 if (e1000_alloc_queues(adapter)) 4463 return -ENOMEM; 4464 4465 /* Setup hardware time stamping cyclecounter */ 4466 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4467 adapter->cc.read = e1000e_cyclecounter_read; 4468 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4469 adapter->cc.mult = 1; 4470 /* cc.shift set in e1000e_get_base_tininca() */ 4471 4472 spin_lock_init(&adapter->systim_lock); 4473 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4474 } 4475 4476 /* Explicitly disable IRQ since the NIC can be in any state. */ 4477 e1000_irq_disable(adapter); 4478 4479 set_bit(__E1000_DOWN, &adapter->state); 4480 return 0; 4481 } 4482 4483 /** 4484 * e1000_intr_msi_test - Interrupt Handler 4485 * @irq: interrupt number 4486 * @data: pointer to a network interface device structure 4487 **/ 4488 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4489 { 4490 struct net_device *netdev = data; 4491 struct e1000_adapter *adapter = netdev_priv(netdev); 4492 struct e1000_hw *hw = &adapter->hw; 4493 u32 icr = er32(ICR); 4494 4495 e_dbg("icr is %08X\n", icr); 4496 if (icr & E1000_ICR_RXSEQ) { 4497 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4498 /* Force memory writes to complete before acknowledging the 4499 * interrupt is handled. 4500 */ 4501 wmb(); 4502 } 4503 4504 return IRQ_HANDLED; 4505 } 4506 4507 /** 4508 * e1000_test_msi_interrupt - Returns 0 for successful test 4509 * @adapter: board private struct 4510 * 4511 * code flow taken from tg3.c 4512 **/ 4513 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4514 { 4515 struct net_device *netdev = adapter->netdev; 4516 struct e1000_hw *hw = &adapter->hw; 4517 int err; 4518 4519 /* poll_enable hasn't been called yet, so don't need disable */ 4520 /* clear any pending events */ 4521 er32(ICR); 4522 4523 /* free the real vector and request a test handler */ 4524 e1000_free_irq(adapter); 4525 e1000e_reset_interrupt_capability(adapter); 4526 4527 /* Assume that the test fails, if it succeeds then the test 4528 * MSI irq handler will unset this flag 4529 */ 4530 adapter->flags |= FLAG_MSI_TEST_FAILED; 4531 4532 err = pci_enable_msi(adapter->pdev); 4533 if (err) 4534 goto msi_test_failed; 4535 4536 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4537 netdev->name, netdev); 4538 if (err) { 4539 pci_disable_msi(adapter->pdev); 4540 goto msi_test_failed; 4541 } 4542 4543 /* Force memory writes to complete before enabling and firing an 4544 * interrupt. 4545 */ 4546 wmb(); 4547 4548 e1000_irq_enable(adapter); 4549 4550 /* fire an unusual interrupt on the test handler */ 4551 ew32(ICS, E1000_ICS_RXSEQ); 4552 e1e_flush(); 4553 msleep(100); 4554 4555 e1000_irq_disable(adapter); 4556 4557 rmb(); /* read flags after interrupt has been fired */ 4558 4559 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4560 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4561 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4562 } else { 4563 e_dbg("MSI interrupt test succeeded!\n"); 4564 } 4565 4566 free_irq(adapter->pdev->irq, netdev); 4567 pci_disable_msi(adapter->pdev); 4568 4569 msi_test_failed: 4570 e1000e_set_interrupt_capability(adapter); 4571 return e1000_request_irq(adapter); 4572 } 4573 4574 /** 4575 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4576 * @adapter: board private struct 4577 * 4578 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4579 **/ 4580 static int e1000_test_msi(struct e1000_adapter *adapter) 4581 { 4582 int err; 4583 u16 pci_cmd; 4584 4585 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4586 return 0; 4587 4588 /* disable SERR in case the MSI write causes a master abort */ 4589 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4590 if (pci_cmd & PCI_COMMAND_SERR) 4591 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4592 pci_cmd & ~PCI_COMMAND_SERR); 4593 4594 err = e1000_test_msi_interrupt(adapter); 4595 4596 /* re-enable SERR */ 4597 if (pci_cmd & PCI_COMMAND_SERR) { 4598 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4599 pci_cmd |= PCI_COMMAND_SERR; 4600 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4601 } 4602 4603 return err; 4604 } 4605 4606 /** 4607 * e1000e_open - Called when a network interface is made active 4608 * @netdev: network interface device structure 4609 * 4610 * Returns 0 on success, negative value on failure 4611 * 4612 * The open entry point is called when a network interface is made 4613 * active by the system (IFF_UP). At this point all resources needed 4614 * for transmit and receive operations are allocated, the interrupt 4615 * handler is registered with the OS, the watchdog timer is started, 4616 * and the stack is notified that the interface is ready. 4617 **/ 4618 int e1000e_open(struct net_device *netdev) 4619 { 4620 struct e1000_adapter *adapter = netdev_priv(netdev); 4621 struct e1000_hw *hw = &adapter->hw; 4622 struct pci_dev *pdev = adapter->pdev; 4623 int err; 4624 int irq; 4625 4626 /* disallow open during test */ 4627 if (test_bit(__E1000_TESTING, &adapter->state)) 4628 return -EBUSY; 4629 4630 pm_runtime_get_sync(&pdev->dev); 4631 4632 netif_carrier_off(netdev); 4633 netif_stop_queue(netdev); 4634 4635 /* allocate transmit descriptors */ 4636 err = e1000e_setup_tx_resources(adapter->tx_ring); 4637 if (err) 4638 goto err_setup_tx; 4639 4640 /* allocate receive descriptors */ 4641 err = e1000e_setup_rx_resources(adapter->rx_ring); 4642 if (err) 4643 goto err_setup_rx; 4644 4645 /* If AMT is enabled, let the firmware know that the network 4646 * interface is now open and reset the part to a known state. 4647 */ 4648 if (adapter->flags & FLAG_HAS_AMT) { 4649 e1000e_get_hw_control(adapter); 4650 e1000e_reset(adapter); 4651 } 4652 4653 e1000e_power_up_phy(adapter); 4654 4655 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4656 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4657 e1000_update_mng_vlan(adapter); 4658 4659 /* DMA latency requirement to workaround jumbo issue */ 4660 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE); 4661 4662 /* before we allocate an interrupt, we must be ready to handle it. 4663 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4664 * as soon as we call pci_request_irq, so we have to setup our 4665 * clean_rx handler before we do so. 4666 */ 4667 e1000_configure(adapter); 4668 4669 err = e1000_request_irq(adapter); 4670 if (err) 4671 goto err_req_irq; 4672 4673 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4674 * ignore e1000e MSI messages, which means we need to test our MSI 4675 * interrupt now 4676 */ 4677 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4678 err = e1000_test_msi(adapter); 4679 if (err) { 4680 e_err("Interrupt allocation failed\n"); 4681 goto err_req_irq; 4682 } 4683 } 4684 4685 /* From here on the code is the same as e1000e_up() */ 4686 clear_bit(__E1000_DOWN, &adapter->state); 4687 4688 if (adapter->int_mode == E1000E_INT_MODE_MSIX) 4689 irq = adapter->msix_entries[0].vector; 4690 else 4691 irq = adapter->pdev->irq; 4692 4693 netif_napi_set_irq(&adapter->napi, irq); 4694 napi_enable(&adapter->napi); 4695 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, &adapter->napi); 4696 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, &adapter->napi); 4697 4698 e1000_irq_enable(adapter); 4699 4700 adapter->tx_hang_recheck = false; 4701 4702 hw->mac.get_link_status = true; 4703 pm_runtime_put(&pdev->dev); 4704 4705 e1000e_trigger_lsc(adapter); 4706 4707 return 0; 4708 4709 err_req_irq: 4710 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4711 e1000e_release_hw_control(adapter); 4712 e1000_power_down_phy(adapter); 4713 e1000e_free_rx_resources(adapter->rx_ring); 4714 err_setup_rx: 4715 e1000e_free_tx_resources(adapter->tx_ring); 4716 err_setup_tx: 4717 e1000e_reset(adapter); 4718 pm_runtime_put_sync(&pdev->dev); 4719 4720 return err; 4721 } 4722 4723 /** 4724 * e1000e_close - Disables a network interface 4725 * @netdev: network interface device structure 4726 * 4727 * Returns 0, this is not allowed to fail 4728 * 4729 * The close entry point is called when an interface is de-activated 4730 * by the OS. The hardware is still under the drivers control, but 4731 * needs to be disabled. A global MAC reset is issued to stop the 4732 * hardware, and all transmit and receive resources are freed. 4733 **/ 4734 int e1000e_close(struct net_device *netdev) 4735 { 4736 struct e1000_adapter *adapter = netdev_priv(netdev); 4737 struct pci_dev *pdev = adapter->pdev; 4738 int count = E1000_CHECK_RESET_COUNT; 4739 4740 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4741 usleep_range(10000, 11000); 4742 4743 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4744 4745 pm_runtime_get_sync(&pdev->dev); 4746 4747 if (netif_device_present(netdev)) { 4748 e1000e_down(adapter, true); 4749 e1000_free_irq(adapter); 4750 4751 /* Link status message must follow this format */ 4752 netdev_info(netdev, "NIC Link is Down\n"); 4753 } 4754 4755 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, NULL); 4756 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, NULL); 4757 napi_disable(&adapter->napi); 4758 4759 e1000e_free_tx_resources(adapter->tx_ring); 4760 e1000e_free_rx_resources(adapter->rx_ring); 4761 4762 /* kill manageability vlan ID if supported, but not if a vlan with 4763 * the same ID is registered on the host OS (let 8021q kill it) 4764 */ 4765 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4766 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4767 adapter->mng_vlan_id); 4768 4769 /* If AMT is enabled, let the firmware know that the network 4770 * interface is now closed 4771 */ 4772 if ((adapter->flags & FLAG_HAS_AMT) && 4773 !test_bit(__E1000_TESTING, &adapter->state)) 4774 e1000e_release_hw_control(adapter); 4775 4776 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4777 4778 pm_runtime_put_sync(&pdev->dev); 4779 4780 return 0; 4781 } 4782 4783 /** 4784 * e1000_set_mac - Change the Ethernet Address of the NIC 4785 * @netdev: network interface device structure 4786 * @p: pointer to an address structure 4787 * 4788 * Returns 0 on success, negative on failure 4789 **/ 4790 static int e1000_set_mac(struct net_device *netdev, void *p) 4791 { 4792 struct e1000_adapter *adapter = netdev_priv(netdev); 4793 struct e1000_hw *hw = &adapter->hw; 4794 struct sockaddr *addr = p; 4795 4796 if (!is_valid_ether_addr(addr->sa_data)) 4797 return -EADDRNOTAVAIL; 4798 4799 eth_hw_addr_set(netdev, addr->sa_data); 4800 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4801 4802 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4803 4804 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4805 /* activate the work around */ 4806 e1000e_set_laa_state_82571(&adapter->hw, 1); 4807 4808 /* Hold a copy of the LAA in RAR[14] This is done so that 4809 * between the time RAR[0] gets clobbered and the time it 4810 * gets fixed (in e1000_watchdog), the actual LAA is in one 4811 * of the RARs and no incoming packets directed to this port 4812 * are dropped. Eventually the LAA will be in RAR[0] and 4813 * RAR[14] 4814 */ 4815 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4816 adapter->hw.mac.rar_entry_count - 1); 4817 } 4818 4819 return 0; 4820 } 4821 4822 /** 4823 * e1000e_update_phy_task - work thread to update phy 4824 * @work: pointer to our work struct 4825 * 4826 * this worker thread exists because we must acquire a 4827 * semaphore to read the phy, which we could msleep while 4828 * waiting for it, and we can't msleep in a timer. 4829 **/ 4830 static void e1000e_update_phy_task(struct work_struct *work) 4831 { 4832 struct e1000_adapter *adapter = container_of(work, 4833 struct e1000_adapter, 4834 update_phy_task); 4835 struct e1000_hw *hw = &adapter->hw; 4836 4837 if (test_bit(__E1000_DOWN, &adapter->state)) 4838 return; 4839 4840 e1000_get_phy_info(hw); 4841 4842 /* Enable EEE on 82579 after link up */ 4843 if (hw->phy.type >= e1000_phy_82579) 4844 e1000_set_eee_pchlan(hw); 4845 } 4846 4847 /** 4848 * e1000_update_phy_info - timre call-back to update PHY info 4849 * @t: pointer to timer_list containing private info adapter 4850 * 4851 * Need to wait a few seconds after link up to get diagnostic information from 4852 * the phy 4853 **/ 4854 static void e1000_update_phy_info(struct timer_list *t) 4855 { 4856 struct e1000_adapter *adapter = timer_container_of(adapter, t, 4857 phy_info_timer); 4858 4859 if (test_bit(__E1000_DOWN, &adapter->state)) 4860 return; 4861 4862 schedule_work(&adapter->update_phy_task); 4863 } 4864 4865 /** 4866 * e1000e_update_phy_stats - Update the PHY statistics counters 4867 * @adapter: board private structure 4868 * 4869 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4870 **/ 4871 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4872 { 4873 struct e1000_hw *hw = &adapter->hw; 4874 s32 ret_val; 4875 u16 phy_data; 4876 4877 ret_val = hw->phy.ops.acquire(hw); 4878 if (ret_val) 4879 return; 4880 4881 /* A page set is expensive so check if already on desired page. 4882 * If not, set to the page with the PHY status registers. 4883 */ 4884 hw->phy.addr = 1; 4885 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4886 &phy_data); 4887 if (ret_val) 4888 goto release; 4889 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4890 ret_val = hw->phy.ops.set_page(hw, 4891 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4892 if (ret_val) 4893 goto release; 4894 } 4895 4896 /* Single Collision Count */ 4897 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4898 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4899 if (!ret_val) 4900 adapter->stats.scc += phy_data; 4901 4902 /* Excessive Collision Count */ 4903 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4904 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4905 if (!ret_val) 4906 adapter->stats.ecol += phy_data; 4907 4908 /* Multiple Collision Count */ 4909 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4910 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4911 if (!ret_val) 4912 adapter->stats.mcc += phy_data; 4913 4914 /* Late Collision Count */ 4915 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4916 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4917 if (!ret_val) 4918 adapter->stats.latecol += phy_data; 4919 4920 /* Collision Count - also used for adaptive IFS */ 4921 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4922 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4923 if (!ret_val) 4924 hw->mac.collision_delta = phy_data; 4925 4926 /* Defer Count */ 4927 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4928 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4929 if (!ret_val) 4930 adapter->stats.dc += phy_data; 4931 4932 /* Transmit with no CRS */ 4933 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4934 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4935 if (!ret_val) 4936 adapter->stats.tncrs += phy_data; 4937 4938 release: 4939 hw->phy.ops.release(hw); 4940 } 4941 4942 /** 4943 * e1000e_update_stats - Update the board statistics counters 4944 * @adapter: board private structure 4945 **/ 4946 static void e1000e_update_stats(struct e1000_adapter *adapter) 4947 { 4948 struct net_device *netdev = adapter->netdev; 4949 struct e1000_hw *hw = &adapter->hw; 4950 struct pci_dev *pdev = adapter->pdev; 4951 4952 /* Prevent stats update while adapter is being reset, or if the pci 4953 * connection is down. 4954 */ 4955 if (adapter->link_speed == 0) 4956 return; 4957 if (pci_channel_offline(pdev)) 4958 return; 4959 4960 adapter->stats.crcerrs += er32(CRCERRS); 4961 adapter->stats.gprc += er32(GPRC); 4962 adapter->stats.gorc += er32(GORCL); 4963 er32(GORCH); /* Clear gorc */ 4964 adapter->stats.bprc += er32(BPRC); 4965 adapter->stats.mprc += er32(MPRC); 4966 adapter->stats.roc += er32(ROC); 4967 4968 adapter->stats.mpc += er32(MPC); 4969 4970 /* Half-duplex statistics */ 4971 if (adapter->link_duplex == HALF_DUPLEX) { 4972 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4973 e1000e_update_phy_stats(adapter); 4974 } else { 4975 adapter->stats.scc += er32(SCC); 4976 adapter->stats.ecol += er32(ECOL); 4977 adapter->stats.mcc += er32(MCC); 4978 adapter->stats.latecol += er32(LATECOL); 4979 adapter->stats.dc += er32(DC); 4980 4981 hw->mac.collision_delta = er32(COLC); 4982 4983 if ((hw->mac.type != e1000_82574) && 4984 (hw->mac.type != e1000_82583)) 4985 adapter->stats.tncrs += er32(TNCRS); 4986 } 4987 adapter->stats.colc += hw->mac.collision_delta; 4988 } 4989 4990 adapter->stats.xonrxc += er32(XONRXC); 4991 adapter->stats.xontxc += er32(XONTXC); 4992 adapter->stats.xoffrxc += er32(XOFFRXC); 4993 adapter->stats.xofftxc += er32(XOFFTXC); 4994 adapter->stats.gptc += er32(GPTC); 4995 adapter->stats.gotc += er32(GOTCL); 4996 er32(GOTCH); /* Clear gotc */ 4997 adapter->stats.rnbc += er32(RNBC); 4998 adapter->stats.ruc += er32(RUC); 4999 5000 adapter->stats.mptc += er32(MPTC); 5001 adapter->stats.bptc += er32(BPTC); 5002 5003 /* used for adaptive IFS */ 5004 5005 hw->mac.tx_packet_delta = er32(TPT); 5006 adapter->stats.tpt += hw->mac.tx_packet_delta; 5007 5008 adapter->stats.algnerrc += er32(ALGNERRC); 5009 adapter->stats.rxerrc += er32(RXERRC); 5010 adapter->stats.cexterr += er32(CEXTERR); 5011 adapter->stats.tsctc += er32(TSCTC); 5012 adapter->stats.tsctfc += er32(TSCTFC); 5013 5014 /* Fill out the OS statistics structure */ 5015 netdev->stats.multicast = adapter->stats.mprc; 5016 netdev->stats.collisions = adapter->stats.colc; 5017 5018 /* Rx Errors */ 5019 5020 /* RLEC on some newer hardware can be incorrect so build 5021 * our own version based on RUC and ROC 5022 */ 5023 netdev->stats.rx_errors = adapter->stats.rxerrc + 5024 adapter->stats.crcerrs + adapter->stats.algnerrc + 5025 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5026 netdev->stats.rx_length_errors = adapter->stats.ruc + 5027 adapter->stats.roc; 5028 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5029 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5030 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5031 5032 /* Tx Errors */ 5033 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5034 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5035 netdev->stats.tx_window_errors = adapter->stats.latecol; 5036 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5037 5038 /* Tx Dropped needs to be maintained elsewhere */ 5039 5040 /* Management Stats */ 5041 adapter->stats.mgptc += er32(MGTPTC); 5042 adapter->stats.mgprc += er32(MGTPRC); 5043 adapter->stats.mgpdc += er32(MGTPDC); 5044 5045 /* Correctable ECC Errors */ 5046 if (hw->mac.type >= e1000_pch_lpt) { 5047 u32 pbeccsts = er32(PBECCSTS); 5048 5049 adapter->corr_errors += 5050 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5051 adapter->uncorr_errors += 5052 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 5053 } 5054 } 5055 5056 /** 5057 * e1000_phy_read_status - Update the PHY register status snapshot 5058 * @adapter: board private structure 5059 **/ 5060 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5061 { 5062 struct e1000_hw *hw = &adapter->hw; 5063 struct e1000_phy_regs *phy = &adapter->phy_regs; 5064 5065 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5066 (er32(STATUS) & E1000_STATUS_LU) && 5067 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5068 int ret_val; 5069 5070 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5071 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5072 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5073 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5074 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5075 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5076 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5077 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5078 if (ret_val) 5079 e_warn("Error reading PHY register\n"); 5080 } else { 5081 /* Do not read PHY registers if link is not up 5082 * Set values to typical power-on defaults 5083 */ 5084 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5085 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5086 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5087 BMSR_ERCAP); 5088 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5089 ADVERTISE_ALL | ADVERTISE_CSMA); 5090 phy->lpa = 0; 5091 phy->expansion = EXPANSION_ENABLENPAGE; 5092 phy->ctrl1000 = ADVERTISE_1000FULL; 5093 phy->stat1000 = 0; 5094 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5095 } 5096 } 5097 5098 static void e1000_print_link_info(struct e1000_adapter *adapter) 5099 { 5100 struct e1000_hw *hw = &adapter->hw; 5101 u32 ctrl = er32(CTRL); 5102 5103 /* Link status message must follow this format for user tools */ 5104 netdev_info(adapter->netdev, 5105 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5106 adapter->link_speed, 5107 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5108 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5109 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5110 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5111 } 5112 5113 static bool e1000e_has_link(struct e1000_adapter *adapter) 5114 { 5115 struct e1000_hw *hw = &adapter->hw; 5116 bool link_active = false; 5117 s32 ret_val = 0; 5118 5119 /* get_link_status is set on LSC (link status) interrupt or 5120 * Rx sequence error interrupt. get_link_status will stay 5121 * true until the check_for_link establishes link 5122 * for copper adapters ONLY 5123 */ 5124 switch (hw->phy.media_type) { 5125 case e1000_media_type_copper: 5126 if (hw->mac.get_link_status) { 5127 ret_val = hw->mac.ops.check_for_link(hw); 5128 link_active = !hw->mac.get_link_status; 5129 } else { 5130 link_active = true; 5131 } 5132 break; 5133 case e1000_media_type_fiber: 5134 ret_val = hw->mac.ops.check_for_link(hw); 5135 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5136 break; 5137 case e1000_media_type_internal_serdes: 5138 ret_val = hw->mac.ops.check_for_link(hw); 5139 link_active = hw->mac.serdes_has_link; 5140 break; 5141 default: 5142 case e1000_media_type_unknown: 5143 break; 5144 } 5145 5146 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5147 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5148 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5149 e_info("Gigabit has been disabled, downgrading speed\n"); 5150 } 5151 5152 return link_active; 5153 } 5154 5155 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5156 { 5157 /* make sure the receive unit is started */ 5158 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5159 (adapter->flags & FLAG_RESTART_NOW)) { 5160 struct e1000_hw *hw = &adapter->hw; 5161 u32 rctl = er32(RCTL); 5162 5163 ew32(RCTL, rctl | E1000_RCTL_EN); 5164 adapter->flags &= ~FLAG_RESTART_NOW; 5165 } 5166 } 5167 5168 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5169 { 5170 struct e1000_hw *hw = &adapter->hw; 5171 5172 /* With 82574 controllers, PHY needs to be checked periodically 5173 * for hung state and reset, if two calls return true 5174 */ 5175 if (e1000_check_phy_82574(hw)) 5176 adapter->phy_hang_count++; 5177 else 5178 adapter->phy_hang_count = 0; 5179 5180 if (adapter->phy_hang_count > 1) { 5181 adapter->phy_hang_count = 0; 5182 e_dbg("PHY appears hung - resetting\n"); 5183 schedule_work(&adapter->reset_task); 5184 } 5185 } 5186 5187 /** 5188 * e1000_watchdog - Timer Call-back 5189 * @t: pointer to timer_list containing private info adapter 5190 **/ 5191 static void e1000_watchdog(struct timer_list *t) 5192 { 5193 struct e1000_adapter *adapter = timer_container_of(adapter, t, 5194 watchdog_timer); 5195 5196 /* Do the rest outside of interrupt context */ 5197 schedule_work(&adapter->watchdog_task); 5198 5199 /* TODO: make this use queue_delayed_work() */ 5200 } 5201 5202 static void e1000_watchdog_task(struct work_struct *work) 5203 { 5204 struct e1000_adapter *adapter = container_of(work, 5205 struct e1000_adapter, 5206 watchdog_task); 5207 struct net_device *netdev = adapter->netdev; 5208 struct e1000_mac_info *mac = &adapter->hw.mac; 5209 struct e1000_phy_info *phy = &adapter->hw.phy; 5210 struct e1000_ring *tx_ring = adapter->tx_ring; 5211 u32 dmoff_exit_timeout = 100, tries = 0; 5212 struct e1000_hw *hw = &adapter->hw; 5213 u32 link, tctl, pcim_state; 5214 5215 if (test_bit(__E1000_DOWN, &adapter->state)) 5216 return; 5217 5218 link = e1000e_has_link(adapter); 5219 if ((netif_carrier_ok(netdev)) && link) { 5220 /* Cancel scheduled suspend requests. */ 5221 pm_runtime_resume(netdev->dev.parent); 5222 5223 e1000e_enable_receives(adapter); 5224 goto link_up; 5225 } 5226 5227 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5228 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5229 e1000_update_mng_vlan(adapter); 5230 5231 if (link) { 5232 if (!netif_carrier_ok(netdev)) { 5233 bool txb2b = true; 5234 5235 /* Cancel scheduled suspend requests. */ 5236 pm_runtime_resume(netdev->dev.parent); 5237 5238 /* Checking if MAC is in DMoff state*/ 5239 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 5240 pcim_state = er32(STATUS); 5241 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5242 if (tries++ == dmoff_exit_timeout) { 5243 e_dbg("Error in exiting dmoff\n"); 5244 break; 5245 } 5246 usleep_range(10000, 20000); 5247 pcim_state = er32(STATUS); 5248 5249 /* Checking if MAC exited DMoff state */ 5250 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5251 e1000_phy_hw_reset(&adapter->hw); 5252 } 5253 } 5254 5255 /* update snapshot of PHY registers on LSC */ 5256 e1000_phy_read_status(adapter); 5257 mac->ops.get_link_up_info(&adapter->hw, 5258 &adapter->link_speed, 5259 &adapter->link_duplex); 5260 e1000_print_link_info(adapter); 5261 5262 /* check if SmartSpeed worked */ 5263 e1000e_check_downshift(hw); 5264 if (phy->speed_downgraded) 5265 netdev_warn(netdev, 5266 "Link Speed was downgraded by SmartSpeed\n"); 5267 5268 /* On supported PHYs, check for duplex mismatch only 5269 * if link has autonegotiated at 10/100 half 5270 */ 5271 if ((hw->phy.type == e1000_phy_igp_3 || 5272 hw->phy.type == e1000_phy_bm) && 5273 hw->mac.autoneg && 5274 (adapter->link_speed == SPEED_10 || 5275 adapter->link_speed == SPEED_100) && 5276 (adapter->link_duplex == HALF_DUPLEX)) { 5277 u16 autoneg_exp; 5278 5279 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5280 5281 if (!(autoneg_exp & EXPANSION_NWAY)) 5282 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5283 } 5284 5285 /* adjust timeout factor according to speed/duplex */ 5286 adapter->tx_timeout_factor = 1; 5287 switch (adapter->link_speed) { 5288 case SPEED_10: 5289 txb2b = false; 5290 adapter->tx_timeout_factor = 16; 5291 break; 5292 case SPEED_100: 5293 txb2b = false; 5294 adapter->tx_timeout_factor = 10; 5295 break; 5296 } 5297 5298 /* workaround: re-program speed mode bit after 5299 * link-up event 5300 */ 5301 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5302 !txb2b) { 5303 u32 tarc0; 5304 5305 tarc0 = er32(TARC(0)); 5306 tarc0 &= ~SPEED_MODE_BIT; 5307 ew32(TARC(0), tarc0); 5308 } 5309 5310 /* enable transmits in the hardware, need to do this 5311 * after setting TARC(0) 5312 */ 5313 tctl = er32(TCTL); 5314 tctl |= E1000_TCTL_EN; 5315 ew32(TCTL, tctl); 5316 5317 /* Perform any post-link-up configuration before 5318 * reporting link up. 5319 */ 5320 if (phy->ops.cfg_on_link_up) 5321 phy->ops.cfg_on_link_up(hw); 5322 5323 netif_wake_queue(netdev); 5324 netif_carrier_on(netdev); 5325 5326 if (!test_bit(__E1000_DOWN, &adapter->state)) 5327 mod_timer(&adapter->phy_info_timer, 5328 round_jiffies(jiffies + 2 * HZ)); 5329 } 5330 } else { 5331 if (netif_carrier_ok(netdev)) { 5332 adapter->link_speed = 0; 5333 adapter->link_duplex = 0; 5334 /* Link status message must follow this format */ 5335 netdev_info(netdev, "NIC Link is Down\n"); 5336 netif_carrier_off(netdev); 5337 netif_stop_queue(netdev); 5338 if (!test_bit(__E1000_DOWN, &adapter->state)) 5339 mod_timer(&adapter->phy_info_timer, 5340 round_jiffies(jiffies + 2 * HZ)); 5341 5342 /* 8000ES2LAN requires a Rx packet buffer work-around 5343 * on link down event; reset the controller to flush 5344 * the Rx packet buffer. 5345 */ 5346 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5347 adapter->flags |= FLAG_RESTART_NOW; 5348 else 5349 pm_schedule_suspend(netdev->dev.parent, 5350 LINK_TIMEOUT); 5351 } 5352 } 5353 5354 link_up: 5355 spin_lock(&adapter->stats64_lock); 5356 e1000e_update_stats(adapter); 5357 5358 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5359 adapter->tpt_old = adapter->stats.tpt; 5360 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5361 adapter->colc_old = adapter->stats.colc; 5362 5363 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5364 adapter->gorc_old = adapter->stats.gorc; 5365 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5366 adapter->gotc_old = adapter->stats.gotc; 5367 spin_unlock(&adapter->stats64_lock); 5368 5369 /* If the link is lost the controller stops DMA, but 5370 * if there is queued Tx work it cannot be done. So 5371 * reset the controller to flush the Tx packet buffers. 5372 */ 5373 if (!netif_carrier_ok(netdev) && 5374 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5375 adapter->flags |= FLAG_RESTART_NOW; 5376 5377 /* If reset is necessary, do it outside of interrupt context. */ 5378 if (adapter->flags & FLAG_RESTART_NOW) { 5379 schedule_work(&adapter->reset_task); 5380 /* return immediately since reset is imminent */ 5381 return; 5382 } 5383 5384 e1000e_update_adaptive(&adapter->hw); 5385 5386 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5387 if (adapter->itr_setting == 4) { 5388 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5389 * Total asymmetrical Tx or Rx gets ITR=8000; 5390 * everyone else is between 2000-8000. 5391 */ 5392 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5393 u32 dif = (adapter->gotc > adapter->gorc ? 5394 adapter->gotc - adapter->gorc : 5395 adapter->gorc - adapter->gotc) / 10000; 5396 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5397 5398 e1000e_write_itr(adapter, itr); 5399 } 5400 5401 /* Cause software interrupt to ensure Rx ring is cleaned */ 5402 if (adapter->msix_entries) 5403 ew32(ICS, adapter->rx_ring->ims_val); 5404 else 5405 ew32(ICS, E1000_ICS_RXDMT0); 5406 5407 /* flush pending descriptors to memory before detecting Tx hang */ 5408 e1000e_flush_descriptors(adapter); 5409 5410 /* Force detection of hung controller every watchdog period */ 5411 adapter->detect_tx_hung = true; 5412 5413 /* With 82571 controllers, LAA may be overwritten due to controller 5414 * reset from the other port. Set the appropriate LAA in RAR[0] 5415 */ 5416 if (e1000e_get_laa_state_82571(hw)) 5417 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5418 5419 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5420 e1000e_check_82574_phy_workaround(adapter); 5421 5422 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5423 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5424 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5425 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5426 er32(RXSTMPH); 5427 adapter->rx_hwtstamp_cleared++; 5428 } else { 5429 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5430 } 5431 } 5432 5433 /* Reset the timer */ 5434 if (!test_bit(__E1000_DOWN, &adapter->state)) 5435 mod_timer(&adapter->watchdog_timer, 5436 round_jiffies(jiffies + 2 * HZ)); 5437 } 5438 5439 #define E1000_TX_FLAGS_CSUM 0x00000001 5440 #define E1000_TX_FLAGS_VLAN 0x00000002 5441 #define E1000_TX_FLAGS_TSO 0x00000004 5442 #define E1000_TX_FLAGS_IPV4 0x00000008 5443 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5444 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5445 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5446 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5447 5448 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5449 __be16 protocol) 5450 { 5451 struct e1000_context_desc *context_desc; 5452 struct e1000_buffer *buffer_info; 5453 unsigned int i; 5454 u32 cmd_length = 0; 5455 u16 ipcse = 0, mss; 5456 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5457 int err; 5458 5459 if (!skb_is_gso(skb)) 5460 return 0; 5461 5462 err = skb_cow_head(skb, 0); 5463 if (err < 0) 5464 return err; 5465 5466 hdr_len = skb_tcp_all_headers(skb); 5467 mss = skb_shinfo(skb)->gso_size; 5468 if (protocol == htons(ETH_P_IP)) { 5469 struct iphdr *iph = ip_hdr(skb); 5470 iph->tot_len = 0; 5471 iph->check = 0; 5472 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5473 0, IPPROTO_TCP, 0); 5474 cmd_length = E1000_TXD_CMD_IP; 5475 ipcse = skb_transport_offset(skb) - 1; 5476 } else if (skb_is_gso_v6(skb)) { 5477 tcp_v6_gso_csum_prep(skb); 5478 ipcse = 0; 5479 } 5480 ipcss = skb_network_offset(skb); 5481 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5482 tucss = skb_transport_offset(skb); 5483 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5484 5485 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5486 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5487 5488 i = tx_ring->next_to_use; 5489 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5490 buffer_info = &tx_ring->buffer_info[i]; 5491 5492 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5493 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5494 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5495 context_desc->upper_setup.tcp_fields.tucss = tucss; 5496 context_desc->upper_setup.tcp_fields.tucso = tucso; 5497 context_desc->upper_setup.tcp_fields.tucse = 0; 5498 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5499 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5500 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5501 5502 buffer_info->time_stamp = jiffies; 5503 buffer_info->next_to_watch = i; 5504 5505 i++; 5506 if (i == tx_ring->count) 5507 i = 0; 5508 tx_ring->next_to_use = i; 5509 5510 return 1; 5511 } 5512 5513 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5514 __be16 protocol) 5515 { 5516 struct e1000_adapter *adapter = tx_ring->adapter; 5517 struct e1000_context_desc *context_desc; 5518 struct e1000_buffer *buffer_info; 5519 unsigned int i; 5520 u8 css; 5521 u32 cmd_len = E1000_TXD_CMD_DEXT; 5522 5523 if (skb->ip_summed != CHECKSUM_PARTIAL) 5524 return false; 5525 5526 switch (protocol) { 5527 case cpu_to_be16(ETH_P_IP): 5528 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5529 cmd_len |= E1000_TXD_CMD_TCP; 5530 break; 5531 case cpu_to_be16(ETH_P_IPV6): 5532 /* XXX not handling all IPV6 headers */ 5533 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5534 cmd_len |= E1000_TXD_CMD_TCP; 5535 break; 5536 default: 5537 if (unlikely(net_ratelimit())) 5538 e_warn("checksum_partial proto=%x!\n", 5539 be16_to_cpu(protocol)); 5540 break; 5541 } 5542 5543 css = skb_checksum_start_offset(skb); 5544 5545 i = tx_ring->next_to_use; 5546 buffer_info = &tx_ring->buffer_info[i]; 5547 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5548 5549 context_desc->lower_setup.ip_config = 0; 5550 context_desc->upper_setup.tcp_fields.tucss = css; 5551 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5552 context_desc->upper_setup.tcp_fields.tucse = 0; 5553 context_desc->tcp_seg_setup.data = 0; 5554 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5555 5556 buffer_info->time_stamp = jiffies; 5557 buffer_info->next_to_watch = i; 5558 5559 i++; 5560 if (i == tx_ring->count) 5561 i = 0; 5562 tx_ring->next_to_use = i; 5563 5564 return true; 5565 } 5566 5567 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5568 unsigned int first, unsigned int max_per_txd, 5569 unsigned int nr_frags) 5570 { 5571 struct e1000_adapter *adapter = tx_ring->adapter; 5572 struct pci_dev *pdev = adapter->pdev; 5573 struct e1000_buffer *buffer_info; 5574 unsigned int len = skb_headlen(skb); 5575 unsigned int offset = 0, size, count = 0, i; 5576 unsigned int f, bytecount, segs; 5577 5578 i = tx_ring->next_to_use; 5579 5580 while (len) { 5581 buffer_info = &tx_ring->buffer_info[i]; 5582 size = min(len, max_per_txd); 5583 5584 buffer_info->length = size; 5585 buffer_info->time_stamp = jiffies; 5586 buffer_info->next_to_watch = i; 5587 buffer_info->dma = dma_map_single(&pdev->dev, 5588 skb->data + offset, 5589 size, DMA_TO_DEVICE); 5590 buffer_info->mapped_as_page = false; 5591 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5592 goto dma_error; 5593 5594 len -= size; 5595 offset += size; 5596 count++; 5597 5598 if (len) { 5599 i++; 5600 if (i == tx_ring->count) 5601 i = 0; 5602 } 5603 } 5604 5605 for (f = 0; f < nr_frags; f++) { 5606 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5607 5608 len = skb_frag_size(frag); 5609 offset = 0; 5610 5611 while (len) { 5612 i++; 5613 if (i == tx_ring->count) 5614 i = 0; 5615 5616 buffer_info = &tx_ring->buffer_info[i]; 5617 size = min(len, max_per_txd); 5618 5619 buffer_info->length = size; 5620 buffer_info->time_stamp = jiffies; 5621 buffer_info->next_to_watch = i; 5622 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5623 offset, size, 5624 DMA_TO_DEVICE); 5625 buffer_info->mapped_as_page = true; 5626 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5627 goto dma_error; 5628 5629 len -= size; 5630 offset += size; 5631 count++; 5632 } 5633 } 5634 5635 segs = skb_shinfo(skb)->gso_segs ? : 1; 5636 /* multiply data chunks by size of headers */ 5637 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5638 5639 tx_ring->buffer_info[i].skb = skb; 5640 tx_ring->buffer_info[i].segs = segs; 5641 tx_ring->buffer_info[i].bytecount = bytecount; 5642 tx_ring->buffer_info[first].next_to_watch = i; 5643 5644 return count; 5645 5646 dma_error: 5647 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5648 buffer_info->dma = 0; 5649 if (count) 5650 count--; 5651 5652 while (count--) { 5653 if (i == 0) 5654 i += tx_ring->count; 5655 i--; 5656 buffer_info = &tx_ring->buffer_info[i]; 5657 e1000_put_txbuf(tx_ring, buffer_info, true); 5658 } 5659 5660 return 0; 5661 } 5662 5663 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5664 { 5665 struct e1000_adapter *adapter = tx_ring->adapter; 5666 struct e1000_tx_desc *tx_desc = NULL; 5667 struct e1000_buffer *buffer_info; 5668 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5669 unsigned int i; 5670 5671 if (tx_flags & E1000_TX_FLAGS_TSO) { 5672 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5673 E1000_TXD_CMD_TSE; 5674 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5675 5676 if (tx_flags & E1000_TX_FLAGS_IPV4) 5677 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5678 } 5679 5680 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5681 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5682 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5683 } 5684 5685 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5686 txd_lower |= E1000_TXD_CMD_VLE; 5687 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5688 } 5689 5690 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5691 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5692 5693 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5694 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5695 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5696 } 5697 5698 i = tx_ring->next_to_use; 5699 5700 do { 5701 buffer_info = &tx_ring->buffer_info[i]; 5702 tx_desc = E1000_TX_DESC(*tx_ring, i); 5703 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5704 tx_desc->lower.data = cpu_to_le32(txd_lower | 5705 buffer_info->length); 5706 tx_desc->upper.data = cpu_to_le32(txd_upper); 5707 5708 i++; 5709 if (i == tx_ring->count) 5710 i = 0; 5711 } while (--count > 0); 5712 5713 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5714 5715 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5716 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5717 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5718 5719 /* Force memory writes to complete before letting h/w 5720 * know there are new descriptors to fetch. (Only 5721 * applicable for weak-ordered memory model archs, 5722 * such as IA-64). 5723 */ 5724 wmb(); 5725 5726 tx_ring->next_to_use = i; 5727 } 5728 5729 #define MINIMUM_DHCP_PACKET_SIZE 282 5730 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5731 struct sk_buff *skb) 5732 { 5733 struct e1000_hw *hw = &adapter->hw; 5734 u16 length, offset; 5735 5736 if (skb_vlan_tag_present(skb) && 5737 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5738 (adapter->hw.mng_cookie.status & 5739 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5740 return 0; 5741 5742 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5743 return 0; 5744 5745 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5746 return 0; 5747 5748 { 5749 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5750 struct udphdr *udp; 5751 5752 if (ip->protocol != IPPROTO_UDP) 5753 return 0; 5754 5755 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5756 if (ntohs(udp->dest) != 67) 5757 return 0; 5758 5759 offset = (u8 *)udp + 8 - skb->data; 5760 length = skb->len - offset; 5761 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5762 } 5763 5764 return 0; 5765 } 5766 5767 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5768 { 5769 struct e1000_adapter *adapter = tx_ring->adapter; 5770 5771 netif_stop_queue(adapter->netdev); 5772 /* Herbert's original patch had: 5773 * smp_mb__after_netif_stop_queue(); 5774 * but since that doesn't exist yet, just open code it. 5775 */ 5776 smp_mb(); 5777 5778 /* We need to check again in a case another CPU has just 5779 * made room available. 5780 */ 5781 if (e1000_desc_unused(tx_ring) < size) 5782 return -EBUSY; 5783 5784 /* A reprieve! */ 5785 netif_start_queue(adapter->netdev); 5786 ++adapter->restart_queue; 5787 return 0; 5788 } 5789 5790 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5791 { 5792 BUG_ON(size > tx_ring->count); 5793 5794 if (e1000_desc_unused(tx_ring) >= size) 5795 return 0; 5796 return __e1000_maybe_stop_tx(tx_ring, size); 5797 } 5798 5799 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5800 struct net_device *netdev) 5801 { 5802 struct e1000_adapter *adapter = netdev_priv(netdev); 5803 struct e1000_ring *tx_ring = adapter->tx_ring; 5804 unsigned int first; 5805 unsigned int tx_flags = 0; 5806 unsigned int len = skb_headlen(skb); 5807 unsigned int nr_frags; 5808 unsigned int mss; 5809 int count = 0; 5810 int tso; 5811 unsigned int f; 5812 __be16 protocol = vlan_get_protocol(skb); 5813 5814 if (test_bit(__E1000_DOWN, &adapter->state)) { 5815 dev_kfree_skb_any(skb); 5816 return NETDEV_TX_OK; 5817 } 5818 5819 if (skb->len <= 0) { 5820 dev_kfree_skb_any(skb); 5821 return NETDEV_TX_OK; 5822 } 5823 5824 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5825 * pad skb in order to meet this minimum size requirement 5826 */ 5827 if (skb_put_padto(skb, 17)) 5828 return NETDEV_TX_OK; 5829 5830 mss = skb_shinfo(skb)->gso_size; 5831 if (mss) { 5832 u8 hdr_len; 5833 5834 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5835 * points to just header, pull a few bytes of payload from 5836 * frags into skb->data 5837 */ 5838 hdr_len = skb_tcp_all_headers(skb); 5839 /* we do this workaround for ES2LAN, but it is un-necessary, 5840 * avoiding it could save a lot of cycles 5841 */ 5842 if (skb->data_len && (hdr_len == len)) { 5843 unsigned int pull_size; 5844 5845 pull_size = min_t(unsigned int, 4, skb->data_len); 5846 if (!__pskb_pull_tail(skb, pull_size)) { 5847 e_err("__pskb_pull_tail failed.\n"); 5848 dev_kfree_skb_any(skb); 5849 return NETDEV_TX_OK; 5850 } 5851 len = skb_headlen(skb); 5852 } 5853 } 5854 5855 /* reserve a descriptor for the offload context */ 5856 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5857 count++; 5858 count++; 5859 5860 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5861 5862 nr_frags = skb_shinfo(skb)->nr_frags; 5863 for (f = 0; f < nr_frags; f++) 5864 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5865 adapter->tx_fifo_limit); 5866 5867 if (adapter->hw.mac.tx_pkt_filtering) 5868 e1000_transfer_dhcp_info(adapter, skb); 5869 5870 /* need: count + 2 desc gap to keep tail from touching 5871 * head, otherwise try next time 5872 */ 5873 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5874 return NETDEV_TX_BUSY; 5875 5876 if (skb_vlan_tag_present(skb)) { 5877 tx_flags |= E1000_TX_FLAGS_VLAN; 5878 tx_flags |= (skb_vlan_tag_get(skb) << 5879 E1000_TX_FLAGS_VLAN_SHIFT); 5880 } 5881 5882 first = tx_ring->next_to_use; 5883 5884 tso = e1000_tso(tx_ring, skb, protocol); 5885 if (tso < 0) { 5886 dev_kfree_skb_any(skb); 5887 return NETDEV_TX_OK; 5888 } 5889 5890 if (tso) 5891 tx_flags |= E1000_TX_FLAGS_TSO; 5892 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5893 tx_flags |= E1000_TX_FLAGS_CSUM; 5894 5895 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5896 * 82571 hardware supports TSO capabilities for IPv6 as well... 5897 * no longer assume, we must. 5898 */ 5899 if (protocol == htons(ETH_P_IP)) 5900 tx_flags |= E1000_TX_FLAGS_IPV4; 5901 5902 if (unlikely(skb->no_fcs)) 5903 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5904 5905 /* if count is 0 then mapping error has occurred */ 5906 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5907 nr_frags); 5908 if (count) { 5909 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5910 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5911 if (!adapter->tx_hwtstamp_skb) { 5912 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5913 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5914 adapter->tx_hwtstamp_skb = skb_get(skb); 5915 adapter->tx_hwtstamp_start = jiffies; 5916 schedule_work(&adapter->tx_hwtstamp_work); 5917 } else { 5918 adapter->tx_hwtstamp_skipped++; 5919 } 5920 } 5921 5922 skb_tx_timestamp(skb); 5923 5924 netdev_sent_queue(netdev, skb->len); 5925 e1000_tx_queue(tx_ring, tx_flags, count); 5926 /* Make sure there is space in the ring for the next send. */ 5927 e1000_maybe_stop_tx(tx_ring, 5928 ((MAX_SKB_FRAGS + 1) * 5929 DIV_ROUND_UP(PAGE_SIZE, 5930 adapter->tx_fifo_limit) + 4)); 5931 5932 if (!netdev_xmit_more() || 5933 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5934 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5935 e1000e_update_tdt_wa(tx_ring, 5936 tx_ring->next_to_use); 5937 else 5938 writel(tx_ring->next_to_use, tx_ring->tail); 5939 } 5940 } else { 5941 dev_kfree_skb_any(skb); 5942 tx_ring->buffer_info[first].time_stamp = 0; 5943 tx_ring->next_to_use = first; 5944 } 5945 5946 return NETDEV_TX_OK; 5947 } 5948 5949 /** 5950 * e1000_tx_timeout - Respond to a Tx Hang 5951 * @netdev: network interface device structure 5952 * @txqueue: index of the hung queue (unused) 5953 **/ 5954 static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 5955 { 5956 struct e1000_adapter *adapter = netdev_priv(netdev); 5957 5958 /* Do the reset outside of interrupt context */ 5959 adapter->tx_timeout_count++; 5960 schedule_work(&adapter->reset_task); 5961 } 5962 5963 static void e1000_reset_task(struct work_struct *work) 5964 { 5965 struct e1000_adapter *adapter; 5966 adapter = container_of(work, struct e1000_adapter, reset_task); 5967 5968 rtnl_lock(); 5969 /* don't run the task if already down */ 5970 if (test_bit(__E1000_DOWN, &adapter->state)) { 5971 rtnl_unlock(); 5972 return; 5973 } 5974 5975 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5976 e1000e_dump(adapter); 5977 e_err("Reset adapter unexpectedly\n"); 5978 } 5979 e1000e_reinit_locked(adapter); 5980 rtnl_unlock(); 5981 } 5982 5983 /** 5984 * e1000e_get_stats64 - Get System Network Statistics 5985 * @netdev: network interface device structure 5986 * @stats: rtnl_link_stats64 pointer 5987 * 5988 * Returns the address of the device statistics structure. 5989 **/ 5990 void e1000e_get_stats64(struct net_device *netdev, 5991 struct rtnl_link_stats64 *stats) 5992 { 5993 struct e1000_adapter *adapter = netdev_priv(netdev); 5994 5995 spin_lock(&adapter->stats64_lock); 5996 e1000e_update_stats(adapter); 5997 /* Fill out the OS statistics structure */ 5998 stats->rx_bytes = adapter->stats.gorc; 5999 stats->rx_packets = adapter->stats.gprc; 6000 stats->tx_bytes = adapter->stats.gotc; 6001 stats->tx_packets = adapter->stats.gptc; 6002 stats->multicast = adapter->stats.mprc; 6003 stats->collisions = adapter->stats.colc; 6004 6005 /* Rx Errors */ 6006 6007 /* RLEC on some newer hardware can be incorrect so build 6008 * our own version based on RUC and ROC 6009 */ 6010 stats->rx_errors = adapter->stats.rxerrc + 6011 adapter->stats.crcerrs + adapter->stats.algnerrc + 6012 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 6013 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 6014 stats->rx_crc_errors = adapter->stats.crcerrs; 6015 stats->rx_frame_errors = adapter->stats.algnerrc; 6016 stats->rx_missed_errors = adapter->stats.mpc; 6017 6018 /* Tx Errors */ 6019 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6020 stats->tx_aborted_errors = adapter->stats.ecol; 6021 stats->tx_window_errors = adapter->stats.latecol; 6022 stats->tx_carrier_errors = adapter->stats.tncrs; 6023 6024 /* Tx Dropped needs to be maintained elsewhere */ 6025 6026 spin_unlock(&adapter->stats64_lock); 6027 } 6028 6029 /** 6030 * e1000_change_mtu - Change the Maximum Transfer Unit 6031 * @netdev: network interface device structure 6032 * @new_mtu: new value for maximum frame size 6033 * 6034 * Returns 0 on success, negative on failure 6035 **/ 6036 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6037 { 6038 struct e1000_adapter *adapter = netdev_priv(netdev); 6039 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6040 6041 /* Jumbo frame support */ 6042 if ((new_mtu > ETH_DATA_LEN) && 6043 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6044 e_err("Jumbo Frames not supported.\n"); 6045 return -EINVAL; 6046 } 6047 6048 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6049 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6050 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6051 (new_mtu > ETH_DATA_LEN)) { 6052 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6053 return -EINVAL; 6054 } 6055 6056 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6057 usleep_range(1000, 1100); 6058 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6059 adapter->max_frame_size = max_frame; 6060 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6061 netdev->mtu, new_mtu); 6062 WRITE_ONCE(netdev->mtu, new_mtu); 6063 6064 pm_runtime_get_sync(netdev->dev.parent); 6065 6066 if (netif_running(netdev)) 6067 e1000e_down(adapter, true); 6068 6069 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6070 * means we reserve 2 more, this pushes us to allocate from the next 6071 * larger slab size. 6072 * i.e. RXBUFFER_2048 --> size-4096 slab 6073 * However with the new *_jumbo_rx* routines, jumbo receives will use 6074 * fragmented skbs 6075 */ 6076 6077 if (max_frame <= 2048) 6078 adapter->rx_buffer_len = 2048; 6079 else 6080 adapter->rx_buffer_len = 4096; 6081 6082 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6083 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6084 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6085 6086 if (netif_running(netdev)) 6087 e1000e_up(adapter); 6088 else 6089 e1000e_reset(adapter); 6090 6091 pm_runtime_put_sync(netdev->dev.parent); 6092 6093 clear_bit(__E1000_RESETTING, &adapter->state); 6094 6095 return 0; 6096 } 6097 6098 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6099 { 6100 struct e1000_adapter *adapter = netdev_priv(netdev); 6101 struct mii_ioctl_data *data = if_mii(ifr); 6102 6103 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6104 return -EOPNOTSUPP; 6105 6106 switch (cmd) { 6107 case SIOCGMIIPHY: 6108 data->phy_id = adapter->hw.phy.addr; 6109 break; 6110 case SIOCGMIIREG: 6111 e1000_phy_read_status(adapter); 6112 6113 switch (data->reg_num & 0x1F) { 6114 case MII_BMCR: 6115 data->val_out = adapter->phy_regs.bmcr; 6116 break; 6117 case MII_BMSR: 6118 data->val_out = adapter->phy_regs.bmsr; 6119 break; 6120 case MII_PHYSID1: 6121 data->val_out = (adapter->hw.phy.id >> 16); 6122 break; 6123 case MII_PHYSID2: 6124 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6125 break; 6126 case MII_ADVERTISE: 6127 data->val_out = adapter->phy_regs.advertise; 6128 break; 6129 case MII_LPA: 6130 data->val_out = adapter->phy_regs.lpa; 6131 break; 6132 case MII_EXPANSION: 6133 data->val_out = adapter->phy_regs.expansion; 6134 break; 6135 case MII_CTRL1000: 6136 data->val_out = adapter->phy_regs.ctrl1000; 6137 break; 6138 case MII_STAT1000: 6139 data->val_out = adapter->phy_regs.stat1000; 6140 break; 6141 case MII_ESTATUS: 6142 data->val_out = adapter->phy_regs.estatus; 6143 break; 6144 default: 6145 return -EIO; 6146 } 6147 break; 6148 case SIOCSMIIREG: 6149 default: 6150 return -EOPNOTSUPP; 6151 } 6152 return 0; 6153 } 6154 6155 /** 6156 * e1000e_hwtstamp_set - control hardware time stamping 6157 * @netdev: network interface device structure 6158 * @config: timestamp configuration 6159 * @extack: netlink extended ACK report 6160 * 6161 * Outgoing time stamping can be enabled and disabled. Play nice and 6162 * disable it when requested, although it shouldn't cause any overhead 6163 * when no packet needs it. At most one packet in the queue may be 6164 * marked for time stamping, otherwise it would be impossible to tell 6165 * for sure to which packet the hardware time stamp belongs. 6166 * 6167 * Incoming time stamping has to be configured via the hardware filters. 6168 * Not all combinations are supported, in particular event type has to be 6169 * specified. Matching the kind of event packet is not supported, with the 6170 * exception of "all V2 events regardless of level 2 or 4". 6171 **/ 6172 static int e1000e_hwtstamp_set(struct net_device *netdev, 6173 struct kernel_hwtstamp_config *config, 6174 struct netlink_ext_ack *extack) 6175 { 6176 struct e1000_adapter *adapter = netdev_priv(netdev); 6177 int ret_val; 6178 6179 ret_val = e1000e_config_hwtstamp(adapter, config, extack); 6180 if (ret_val) 6181 return ret_val; 6182 6183 switch (config->rx_filter) { 6184 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6185 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6186 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6187 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6188 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6189 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6190 /* With V2 type filters which specify a Sync or Delay Request, 6191 * Path Delay Request/Response messages are also time stamped 6192 * by hardware so notify the caller the requested packets plus 6193 * some others are time stamped. 6194 */ 6195 config->rx_filter = HWTSTAMP_FILTER_SOME; 6196 break; 6197 default: 6198 break; 6199 } 6200 6201 return 0; 6202 } 6203 6204 static int e1000e_hwtstamp_get(struct net_device *netdev, 6205 struct kernel_hwtstamp_config *kernel_config) 6206 { 6207 struct e1000_adapter *adapter = netdev_priv(netdev); 6208 6209 *kernel_config = adapter->hwtstamp_config; 6210 6211 return 0; 6212 } 6213 6214 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6215 { 6216 struct e1000_hw *hw = &adapter->hw; 6217 u32 i, mac_reg, wuc; 6218 u16 phy_reg, wuc_enable; 6219 int retval; 6220 6221 /* copy MAC RARs to PHY RARs */ 6222 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6223 6224 retval = hw->phy.ops.acquire(hw); 6225 if (retval) { 6226 e_err("Could not acquire PHY\n"); 6227 return retval; 6228 } 6229 6230 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6231 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6232 if (retval) 6233 goto release; 6234 6235 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6236 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6237 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6238 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6239 (u16)(mac_reg & 0xFFFF)); 6240 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6241 (u16)((mac_reg >> 16) & 0xFFFF)); 6242 } 6243 6244 /* configure PHY Rx Control register */ 6245 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6246 mac_reg = er32(RCTL); 6247 if (mac_reg & E1000_RCTL_UPE) 6248 phy_reg |= BM_RCTL_UPE; 6249 if (mac_reg & E1000_RCTL_MPE) 6250 phy_reg |= BM_RCTL_MPE; 6251 phy_reg &= ~(BM_RCTL_MO_MASK); 6252 if (mac_reg & E1000_RCTL_MO_3) 6253 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg) 6254 << BM_RCTL_MO_SHIFT); 6255 if (mac_reg & E1000_RCTL_BAM) 6256 phy_reg |= BM_RCTL_BAM; 6257 if (mac_reg & E1000_RCTL_PMCF) 6258 phy_reg |= BM_RCTL_PMCF; 6259 mac_reg = er32(CTRL); 6260 if (mac_reg & E1000_CTRL_RFCE) 6261 phy_reg |= BM_RCTL_RFCE; 6262 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6263 6264 wuc = E1000_WUC_PME_EN; 6265 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6266 wuc |= E1000_WUC_APME; 6267 6268 /* enable PHY wakeup in MAC register */ 6269 ew32(WUFC, wufc); 6270 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6271 E1000_WUC_PME_STATUS | wuc)); 6272 6273 /* configure and enable PHY wakeup in PHY registers */ 6274 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6275 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6276 6277 /* activate PHY wakeup */ 6278 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6279 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6280 if (retval) 6281 e_err("Could not set PHY Host Wakeup bit\n"); 6282 release: 6283 hw->phy.ops.release(hw); 6284 6285 return retval; 6286 } 6287 6288 static void e1000e_flush_lpic(struct pci_dev *pdev) 6289 { 6290 struct net_device *netdev = pci_get_drvdata(pdev); 6291 struct e1000_adapter *adapter = netdev_priv(netdev); 6292 struct e1000_hw *hw = &adapter->hw; 6293 u32 ret_val; 6294 6295 pm_runtime_get_sync(netdev->dev.parent); 6296 6297 ret_val = hw->phy.ops.acquire(hw); 6298 if (ret_val) 6299 goto fl_out; 6300 6301 pr_info("EEE TX LPI TIMER: %08X\n", 6302 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6303 6304 hw->phy.ops.release(hw); 6305 6306 fl_out: 6307 pm_runtime_put_sync(netdev->dev.parent); 6308 } 6309 6310 /* S0ix implementation */ 6311 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6312 { 6313 struct e1000_hw *hw = &adapter->hw; 6314 u32 mac_data; 6315 u16 phy_data; 6316 6317 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6318 hw->mac.type >= e1000_pch_adp) { 6319 /* Request ME configure the device for S0ix */ 6320 mac_data = er32(H2ME); 6321 mac_data |= E1000_H2ME_START_DPG; 6322 mac_data &= ~E1000_H2ME_EXIT_DPG; 6323 trace_e1000e_trace_mac_register(mac_data); 6324 ew32(H2ME, mac_data); 6325 } else { 6326 /* Request driver configure the device to S0ix */ 6327 /* Disable the periodic inband message, 6328 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6329 */ 6330 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6331 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6332 phy_data |= BIT(10); 6333 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6334 6335 /* Make sure we don't exit K1 every time a new packet arrives 6336 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6337 */ 6338 e1e_rphy(hw, I217_CGFREG, &phy_data); 6339 phy_data |= BIT(5); 6340 e1e_wphy(hw, I217_CGFREG, phy_data); 6341 6342 /* Change the MAC/PHY interface to SMBus 6343 * Force the SMBus in PHY page769_23[0] = 1 6344 * Force the SMBus in MAC CTRL_EXT[11] = 1 6345 */ 6346 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6347 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6348 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6349 mac_data = er32(CTRL_EXT); 6350 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6351 ew32(CTRL_EXT, mac_data); 6352 6353 /* DFT control: PHY bit: page769_20[0] = 1 6354 * page769_20[7] - PHY PLL stop 6355 * page769_20[8] - PHY go to the electrical idle 6356 * page769_20[9] - PHY serdes disable 6357 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6358 */ 6359 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6360 phy_data |= BIT(0); 6361 phy_data |= BIT(7); 6362 phy_data |= BIT(8); 6363 phy_data |= BIT(9); 6364 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6365 6366 mac_data = er32(EXTCNF_CTRL); 6367 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6368 ew32(EXTCNF_CTRL, mac_data); 6369 6370 /* Disable disconnected cable conditioning for Power Gating */ 6371 mac_data = er32(DPGFR); 6372 mac_data |= BIT(2); 6373 ew32(DPGFR, mac_data); 6374 6375 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6376 mac_data = er32(CTRL_EXT); 6377 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6378 ew32(CTRL_EXT, mac_data); 6379 } 6380 6381 /* Enable the Dynamic Power Gating in the MAC */ 6382 mac_data = er32(FEXTNVM7); 6383 mac_data |= BIT(22); 6384 ew32(FEXTNVM7, mac_data); 6385 6386 /* Don't wake from dynamic Power Gating with clock request */ 6387 mac_data = er32(FEXTNVM12); 6388 mac_data |= BIT(12); 6389 ew32(FEXTNVM12, mac_data); 6390 6391 /* Ungate PGCB clock */ 6392 mac_data = er32(FEXTNVM9); 6393 mac_data &= ~BIT(28); 6394 ew32(FEXTNVM9, mac_data); 6395 6396 /* Enable K1 off to enable mPHY Power Gating */ 6397 mac_data = er32(FEXTNVM6); 6398 mac_data |= BIT(31); 6399 ew32(FEXTNVM6, mac_data); 6400 6401 /* Enable mPHY power gating for any link and speed */ 6402 mac_data = er32(FEXTNVM8); 6403 mac_data |= BIT(9); 6404 ew32(FEXTNVM8, mac_data); 6405 6406 /* No MAC DPG gating SLP_S0 in modern standby 6407 * Switch the logic of the lanphypc to use PMC counter 6408 */ 6409 mac_data = er32(FEXTNVM5); 6410 mac_data |= BIT(7); 6411 ew32(FEXTNVM5, mac_data); 6412 6413 /* Disable the time synchronization clock */ 6414 mac_data = er32(FEXTNVM7); 6415 mac_data |= BIT(31); 6416 mac_data &= ~BIT(0); 6417 ew32(FEXTNVM7, mac_data); 6418 6419 /* Dynamic Power Gating Enable */ 6420 mac_data = er32(CTRL_EXT); 6421 mac_data |= BIT(3); 6422 ew32(CTRL_EXT, mac_data); 6423 6424 /* Check MAC Tx/Rx packet buffer pointers. 6425 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6426 * pending traffic indication that would prevent power gating. 6427 */ 6428 mac_data = er32(TDFH); 6429 if (mac_data) 6430 ew32(TDFH, 0); 6431 mac_data = er32(TDFT); 6432 if (mac_data) 6433 ew32(TDFT, 0); 6434 mac_data = er32(TDFHS); 6435 if (mac_data) 6436 ew32(TDFHS, 0); 6437 mac_data = er32(TDFTS); 6438 if (mac_data) 6439 ew32(TDFTS, 0); 6440 mac_data = er32(TDFPC); 6441 if (mac_data) 6442 ew32(TDFPC, 0); 6443 mac_data = er32(RDFH); 6444 if (mac_data) 6445 ew32(RDFH, 0); 6446 mac_data = er32(RDFT); 6447 if (mac_data) 6448 ew32(RDFT, 0); 6449 mac_data = er32(RDFHS); 6450 if (mac_data) 6451 ew32(RDFHS, 0); 6452 mac_data = er32(RDFTS); 6453 if (mac_data) 6454 ew32(RDFTS, 0); 6455 mac_data = er32(RDFPC); 6456 if (mac_data) 6457 ew32(RDFPC, 0); 6458 } 6459 6460 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6461 { 6462 struct e1000_hw *hw = &adapter->hw; 6463 bool firmware_bug = false; 6464 u32 mac_data; 6465 u16 phy_data; 6466 u32 i = 0; 6467 6468 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6469 hw->mac.type >= e1000_pch_adp) { 6470 /* Keep the GPT clock enabled for CSME */ 6471 mac_data = er32(FEXTNVM); 6472 mac_data |= BIT(3); 6473 ew32(FEXTNVM, mac_data); 6474 /* Request ME unconfigure the device from S0ix */ 6475 mac_data = er32(H2ME); 6476 mac_data &= ~E1000_H2ME_START_DPG; 6477 mac_data |= E1000_H2ME_EXIT_DPG; 6478 trace_e1000e_trace_mac_register(mac_data); 6479 ew32(H2ME, mac_data); 6480 6481 /* Poll up to 2.5 seconds for ME to unconfigure DPG. 6482 * If this takes more than 1 second, show a warning indicating a 6483 * firmware bug 6484 */ 6485 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) { 6486 if (i > 100 && !firmware_bug) 6487 firmware_bug = true; 6488 6489 if (i++ == 250) { 6490 e_dbg("Timeout (firmware bug): %d msec\n", 6491 i * 10); 6492 break; 6493 } 6494 6495 usleep_range(10000, 11000); 6496 } 6497 if (firmware_bug) 6498 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n", 6499 i * 10); 6500 else 6501 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10); 6502 } else { 6503 /* Request driver unconfigure the device from S0ix */ 6504 6505 /* Cancel disable disconnected cable conditioning 6506 * for Power Gating 6507 */ 6508 mac_data = er32(DPGFR); 6509 mac_data &= ~BIT(2); 6510 ew32(DPGFR, mac_data); 6511 6512 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6513 mac_data = er32(CTRL_EXT); 6514 mac_data &= 0xFFF7FFFF; 6515 ew32(CTRL_EXT, mac_data); 6516 6517 /* Enable the periodic inband message, 6518 * Request PCIe clock in K1 page770_17[10:9] =01b 6519 */ 6520 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6521 phy_data &= 0xFBFF; 6522 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6523 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6524 6525 /* Return back configuration 6526 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6527 */ 6528 e1e_rphy(hw, I217_CGFREG, &phy_data); 6529 phy_data &= 0xFFDF; 6530 e1e_wphy(hw, I217_CGFREG, phy_data); 6531 6532 /* Change the MAC/PHY interface to Kumeran 6533 * Unforce the SMBus in PHY page769_23[0] = 0 6534 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6535 */ 6536 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6537 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6538 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6539 mac_data = er32(CTRL_EXT); 6540 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6541 ew32(CTRL_EXT, mac_data); 6542 } 6543 6544 /* Disable Dynamic Power Gating */ 6545 mac_data = er32(CTRL_EXT); 6546 mac_data &= 0xFFFFFFF7; 6547 ew32(CTRL_EXT, mac_data); 6548 6549 /* Enable the time synchronization clock */ 6550 mac_data = er32(FEXTNVM7); 6551 mac_data &= ~BIT(31); 6552 mac_data |= BIT(0); 6553 ew32(FEXTNVM7, mac_data); 6554 6555 /* Disable the Dynamic Power Gating in the MAC */ 6556 mac_data = er32(FEXTNVM7); 6557 mac_data &= 0xFFBFFFFF; 6558 ew32(FEXTNVM7, mac_data); 6559 6560 /* Disable mPHY power gating for any link and speed */ 6561 mac_data = er32(FEXTNVM8); 6562 mac_data &= ~BIT(9); 6563 ew32(FEXTNVM8, mac_data); 6564 6565 /* Disable K1 off */ 6566 mac_data = er32(FEXTNVM6); 6567 mac_data &= ~BIT(31); 6568 ew32(FEXTNVM6, mac_data); 6569 6570 /* Disable Ungate PGCB clock */ 6571 mac_data = er32(FEXTNVM9); 6572 mac_data |= BIT(28); 6573 ew32(FEXTNVM9, mac_data); 6574 6575 /* Cancel not waking from dynamic 6576 * Power Gating with clock request 6577 */ 6578 mac_data = er32(FEXTNVM12); 6579 mac_data &= ~BIT(12); 6580 ew32(FEXTNVM12, mac_data); 6581 6582 /* Revert the lanphypc logic to use the internal Gbe counter 6583 * and not the PMC counter 6584 */ 6585 mac_data = er32(FEXTNVM5); 6586 mac_data &= 0xFFFFFF7F; 6587 ew32(FEXTNVM5, mac_data); 6588 } 6589 6590 static int e1000e_pm_freeze(struct device *dev) 6591 { 6592 struct net_device *netdev = dev_get_drvdata(dev); 6593 struct e1000_adapter *adapter = netdev_priv(netdev); 6594 bool present; 6595 6596 rtnl_lock(); 6597 6598 present = netif_device_present(netdev); 6599 netif_device_detach(netdev); 6600 6601 if (present && netif_running(netdev)) { 6602 int count = E1000_CHECK_RESET_COUNT; 6603 6604 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6605 usleep_range(10000, 11000); 6606 6607 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6608 6609 /* Quiesce the device without resetting the hardware */ 6610 e1000e_down(adapter, false); 6611 e1000_free_irq(adapter); 6612 } 6613 rtnl_unlock(); 6614 6615 e1000e_reset_interrupt_capability(adapter); 6616 6617 /* Allow time for pending master requests to run */ 6618 e1000e_disable_pcie_master(&adapter->hw); 6619 6620 return 0; 6621 } 6622 6623 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6624 { 6625 struct net_device *netdev = pci_get_drvdata(pdev); 6626 struct e1000_adapter *adapter = netdev_priv(netdev); 6627 struct e1000_hw *hw = &adapter->hw; 6628 u32 ctrl, ctrl_ext, rctl, status, wufc; 6629 int retval = 0; 6630 6631 /* Runtime suspend should only enable wakeup for link changes */ 6632 if (runtime) 6633 wufc = E1000_WUFC_LNKC; 6634 else if (device_may_wakeup(&pdev->dev)) 6635 wufc = adapter->wol; 6636 else 6637 wufc = 0; 6638 6639 status = er32(STATUS); 6640 if (status & E1000_STATUS_LU) 6641 wufc &= ~E1000_WUFC_LNKC; 6642 6643 if (wufc) { 6644 e1000_setup_rctl(adapter); 6645 e1000e_set_rx_mode(netdev); 6646 6647 /* turn on all-multi mode if wake on multicast is enabled */ 6648 if (wufc & E1000_WUFC_MC) { 6649 rctl = er32(RCTL); 6650 rctl |= E1000_RCTL_MPE; 6651 ew32(RCTL, rctl); 6652 } 6653 6654 ctrl = er32(CTRL); 6655 ctrl |= E1000_CTRL_ADVD3WUC; 6656 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6657 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6658 ew32(CTRL, ctrl); 6659 6660 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6661 adapter->hw.phy.media_type == 6662 e1000_media_type_internal_serdes) { 6663 /* keep the laser running in D3 */ 6664 ctrl_ext = er32(CTRL_EXT); 6665 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6666 ew32(CTRL_EXT, ctrl_ext); 6667 } 6668 6669 if (!runtime) 6670 e1000e_power_up_phy(adapter); 6671 6672 if (adapter->flags & FLAG_IS_ICH) 6673 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6674 6675 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6676 /* enable wakeup by the PHY */ 6677 retval = e1000_init_phy_wakeup(adapter, wufc); 6678 if (retval) { 6679 e_err("Failed to enable wakeup\n"); 6680 goto skip_phy_configurations; 6681 } 6682 } else { 6683 /* enable wakeup by the MAC */ 6684 ew32(WUFC, wufc); 6685 ew32(WUC, E1000_WUC_PME_EN); 6686 } 6687 } else { 6688 ew32(WUC, 0); 6689 ew32(WUFC, 0); 6690 6691 e1000_power_down_phy(adapter); 6692 } 6693 6694 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6695 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6696 } else if (hw->mac.type >= e1000_pch_lpt) { 6697 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) { 6698 /* ULP does not support wake from unicast, multicast 6699 * or broadcast. 6700 */ 6701 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6702 if (retval) { 6703 e_err("Failed to enable ULP\n"); 6704 goto skip_phy_configurations; 6705 } 6706 } 6707 } 6708 6709 /* Ensure that the appropriate bits are set in LPI_CTRL 6710 * for EEE in Sx 6711 */ 6712 if ((hw->phy.type >= e1000_phy_i217) && 6713 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6714 u16 lpi_ctrl = 0; 6715 6716 retval = hw->phy.ops.acquire(hw); 6717 if (!retval) { 6718 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6719 &lpi_ctrl); 6720 if (!retval) { 6721 if (adapter->eee_advert & 6722 hw->dev_spec.ich8lan.eee_lp_ability & 6723 I82579_EEE_100_SUPPORTED) 6724 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6725 if (adapter->eee_advert & 6726 hw->dev_spec.ich8lan.eee_lp_ability & 6727 I82579_EEE_1000_SUPPORTED) 6728 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6729 6730 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6731 lpi_ctrl); 6732 } 6733 } 6734 hw->phy.ops.release(hw); 6735 } 6736 6737 skip_phy_configurations: 6738 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6739 * would have already happened in close and is redundant. 6740 */ 6741 e1000e_release_hw_control(adapter); 6742 6743 pci_clear_master(pdev); 6744 6745 /* The pci-e switch on some quad port adapters will report a 6746 * correctable error when the MAC transitions from D0 to D3. To 6747 * prevent this we need to mask off the correctable errors on the 6748 * downstream port of the pci-e switch. 6749 * 6750 * We don't have the associated upstream bridge while assigning 6751 * the PCI device into guest. For example, the KVM on power is 6752 * one of the cases. 6753 */ 6754 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6755 struct pci_dev *us_dev = pdev->bus->self; 6756 u16 devctl; 6757 6758 if (!us_dev) 6759 return 0; 6760 6761 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6762 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6763 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6764 6765 pci_save_state(pdev); 6766 pci_prepare_to_sleep(pdev); 6767 6768 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6769 } 6770 6771 return 0; 6772 } 6773 6774 /** 6775 * __e1000e_disable_aspm - Disable ASPM states 6776 * @pdev: pointer to PCI device struct 6777 * @state: bit-mask of ASPM states to disable 6778 * @locked: indication if this context holds pci_bus_sem locked. 6779 * 6780 * Some devices *must* have certain ASPM states disabled per hardware errata. 6781 **/ 6782 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6783 { 6784 struct pci_dev *parent = pdev->bus->self; 6785 u16 aspm_dis_mask = 0; 6786 u16 pdev_aspmc, parent_aspmc; 6787 6788 switch (state) { 6789 case PCIE_LINK_STATE_L0S: 6790 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6791 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6792 fallthrough; /* can't have L1 without L0s */ 6793 case PCIE_LINK_STATE_L1: 6794 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6795 break; 6796 default: 6797 return; 6798 } 6799 6800 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6801 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6802 6803 if (parent) { 6804 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6805 &parent_aspmc); 6806 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6807 } 6808 6809 /* Nothing to do if the ASPM states to be disabled already are */ 6810 if (!(pdev_aspmc & aspm_dis_mask) && 6811 (!parent || !(parent_aspmc & aspm_dis_mask))) 6812 return; 6813 6814 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6815 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6816 "L0s" : "", 6817 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6818 "L1" : ""); 6819 6820 #ifdef CONFIG_PCIEASPM 6821 if (locked) 6822 pci_disable_link_state_locked(pdev, state); 6823 else 6824 pci_disable_link_state(pdev, state); 6825 6826 /* Double-check ASPM control. If not disabled by the above, the 6827 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6828 * not enabled); override by writing PCI config space directly. 6829 */ 6830 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6831 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6832 6833 if (!(aspm_dis_mask & pdev_aspmc)) 6834 return; 6835 #endif 6836 6837 /* Both device and parent should have the same ASPM setting. 6838 * Disable ASPM in downstream component first and then upstream. 6839 */ 6840 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6841 6842 if (parent) 6843 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6844 aspm_dis_mask); 6845 } 6846 6847 /** 6848 * e1000e_disable_aspm - Disable ASPM states. 6849 * @pdev: pointer to PCI device struct 6850 * @state: bit-mask of ASPM states to disable 6851 * 6852 * This function acquires the pci_bus_sem! 6853 * Some devices *must* have certain ASPM states disabled per hardware errata. 6854 **/ 6855 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6856 { 6857 __e1000e_disable_aspm(pdev, state, 0); 6858 } 6859 6860 /** 6861 * e1000e_disable_aspm_locked - Disable ASPM states. 6862 * @pdev: pointer to PCI device struct 6863 * @state: bit-mask of ASPM states to disable 6864 * 6865 * This function must be called with pci_bus_sem acquired! 6866 * Some devices *must* have certain ASPM states disabled per hardware errata. 6867 **/ 6868 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6869 { 6870 __e1000e_disable_aspm(pdev, state, 1); 6871 } 6872 6873 static int e1000e_pm_thaw(struct device *dev) 6874 { 6875 struct net_device *netdev = dev_get_drvdata(dev); 6876 struct e1000_adapter *adapter = netdev_priv(netdev); 6877 int rc = 0; 6878 6879 e1000e_set_interrupt_capability(adapter); 6880 6881 rtnl_lock(); 6882 if (netif_running(netdev)) { 6883 rc = e1000_request_irq(adapter); 6884 if (rc) 6885 goto err_irq; 6886 6887 e1000e_up(adapter); 6888 } 6889 6890 netif_device_attach(netdev); 6891 err_irq: 6892 rtnl_unlock(); 6893 6894 return rc; 6895 } 6896 6897 static int __e1000_resume(struct pci_dev *pdev) 6898 { 6899 struct net_device *netdev = pci_get_drvdata(pdev); 6900 struct e1000_adapter *adapter = netdev_priv(netdev); 6901 struct e1000_hw *hw = &adapter->hw; 6902 u16 aspm_disable_flag = 0; 6903 6904 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6905 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6906 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6907 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6908 if (aspm_disable_flag) 6909 e1000e_disable_aspm(pdev, aspm_disable_flag); 6910 6911 pci_set_master(pdev); 6912 6913 if (hw->mac.type >= e1000_pch2lan) 6914 e1000_resume_workarounds_pchlan(&adapter->hw); 6915 6916 e1000e_power_up_phy(adapter); 6917 6918 /* report the system wakeup cause from S3/S4 */ 6919 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6920 u16 phy_data; 6921 6922 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6923 if (phy_data) { 6924 e_info("PHY Wakeup cause - %s\n", 6925 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6926 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6927 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6928 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6929 phy_data & E1000_WUS_LNKC ? 6930 "Link Status Change" : "other"); 6931 } 6932 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6933 } else { 6934 u32 wus = er32(WUS); 6935 6936 if (wus) { 6937 e_info("MAC Wakeup cause - %s\n", 6938 wus & E1000_WUS_EX ? "Unicast Packet" : 6939 wus & E1000_WUS_MC ? "Multicast Packet" : 6940 wus & E1000_WUS_BC ? "Broadcast Packet" : 6941 wus & E1000_WUS_MAG ? "Magic Packet" : 6942 wus & E1000_WUS_LNKC ? "Link Status Change" : 6943 "other"); 6944 } 6945 ew32(WUS, ~0); 6946 } 6947 6948 e1000e_reset(adapter); 6949 6950 e1000_init_manageability_pt(adapter); 6951 6952 /* If the controller has AMT, do not set DRV_LOAD until the interface 6953 * is up. For all other cases, let the f/w know that the h/w is now 6954 * under the control of the driver. 6955 */ 6956 if (!(adapter->flags & FLAG_HAS_AMT)) 6957 e1000e_get_hw_control(adapter); 6958 6959 return 0; 6960 } 6961 6962 static int e1000e_pm_prepare(struct device *dev) 6963 { 6964 return pm_runtime_suspended(dev) && 6965 pm_suspend_via_firmware(); 6966 } 6967 6968 static int e1000e_pm_suspend(struct device *dev) 6969 { 6970 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6971 struct e1000_adapter *adapter = netdev_priv(netdev); 6972 struct pci_dev *pdev = to_pci_dev(dev); 6973 int rc; 6974 6975 e1000e_flush_lpic(pdev); 6976 6977 e1000e_pm_freeze(dev); 6978 6979 rc = __e1000_shutdown(pdev, false); 6980 if (!rc) { 6981 /* Introduce S0ix implementation */ 6982 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 6983 e1000e_s0ix_entry_flow(adapter); 6984 } 6985 6986 return 0; 6987 } 6988 6989 static int e1000e_pm_resume(struct device *dev) 6990 { 6991 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6992 struct e1000_adapter *adapter = netdev_priv(netdev); 6993 struct pci_dev *pdev = to_pci_dev(dev); 6994 int rc; 6995 6996 /* Introduce S0ix implementation */ 6997 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 6998 e1000e_s0ix_exit_flow(adapter); 6999 7000 rc = __e1000_resume(pdev); 7001 if (rc) 7002 return rc; 7003 7004 return e1000e_pm_thaw(dev); 7005 } 7006 7007 static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev) 7008 { 7009 struct net_device *netdev = dev_get_drvdata(dev); 7010 struct e1000_adapter *adapter = netdev_priv(netdev); 7011 u16 eee_lp; 7012 7013 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 7014 7015 if (!e1000e_has_link(adapter)) { 7016 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 7017 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 7018 } 7019 7020 return -EBUSY; 7021 } 7022 7023 static int e1000e_pm_runtime_resume(struct device *dev) 7024 { 7025 struct pci_dev *pdev = to_pci_dev(dev); 7026 struct net_device *netdev = pci_get_drvdata(pdev); 7027 struct e1000_adapter *adapter = netdev_priv(netdev); 7028 int rc; 7029 7030 pdev->pme_poll = true; 7031 7032 rc = __e1000_resume(pdev); 7033 if (rc) 7034 return rc; 7035 7036 if (netdev->flags & IFF_UP) 7037 e1000e_up(adapter); 7038 7039 return rc; 7040 } 7041 7042 static int e1000e_pm_runtime_suspend(struct device *dev) 7043 { 7044 struct pci_dev *pdev = to_pci_dev(dev); 7045 struct net_device *netdev = pci_get_drvdata(pdev); 7046 struct e1000_adapter *adapter = netdev_priv(netdev); 7047 7048 if (netdev->flags & IFF_UP) { 7049 int count = E1000_CHECK_RESET_COUNT; 7050 7051 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 7052 usleep_range(10000, 11000); 7053 7054 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 7055 7056 /* Down the device without resetting the hardware */ 7057 e1000e_down(adapter, false); 7058 } 7059 7060 if (__e1000_shutdown(pdev, true)) { 7061 e1000e_pm_runtime_resume(dev); 7062 return -EBUSY; 7063 } 7064 7065 return 0; 7066 } 7067 7068 static void e1000_shutdown(struct pci_dev *pdev) 7069 { 7070 e1000e_flush_lpic(pdev); 7071 7072 e1000e_pm_freeze(&pdev->dev); 7073 7074 __e1000_shutdown(pdev, false); 7075 } 7076 7077 #ifdef CONFIG_NET_POLL_CONTROLLER 7078 7079 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 7080 { 7081 struct net_device *netdev = data; 7082 struct e1000_adapter *adapter = netdev_priv(netdev); 7083 7084 if (adapter->msix_entries) { 7085 int vector, msix_irq; 7086 7087 vector = 0; 7088 msix_irq = adapter->msix_entries[vector].vector; 7089 if (disable_hardirq(msix_irq)) 7090 e1000_intr_msix_rx(msix_irq, netdev); 7091 enable_irq(msix_irq); 7092 7093 vector++; 7094 msix_irq = adapter->msix_entries[vector].vector; 7095 if (disable_hardirq(msix_irq)) 7096 e1000_intr_msix_tx(msix_irq, netdev); 7097 enable_irq(msix_irq); 7098 7099 vector++; 7100 msix_irq = adapter->msix_entries[vector].vector; 7101 if (disable_hardirq(msix_irq)) 7102 e1000_msix_other(msix_irq, netdev); 7103 enable_irq(msix_irq); 7104 } 7105 7106 return IRQ_HANDLED; 7107 } 7108 7109 /** 7110 * e1000_netpoll 7111 * @netdev: network interface device structure 7112 * 7113 * Polling 'interrupt' - used by things like netconsole to send skbs 7114 * without having to re-enable interrupts. It's not called while 7115 * the interrupt routine is executing. 7116 */ 7117 static void e1000_netpoll(struct net_device *netdev) 7118 { 7119 struct e1000_adapter *adapter = netdev_priv(netdev); 7120 7121 switch (adapter->int_mode) { 7122 case E1000E_INT_MODE_MSIX: 7123 e1000_intr_msix(adapter->pdev->irq, netdev); 7124 break; 7125 case E1000E_INT_MODE_MSI: 7126 if (disable_hardirq(adapter->pdev->irq)) 7127 e1000_intr_msi(adapter->pdev->irq, netdev); 7128 enable_irq(adapter->pdev->irq); 7129 break; 7130 default: /* E1000E_INT_MODE_LEGACY */ 7131 if (disable_hardirq(adapter->pdev->irq)) 7132 e1000_intr(adapter->pdev->irq, netdev); 7133 enable_irq(adapter->pdev->irq); 7134 break; 7135 } 7136 } 7137 #endif 7138 7139 /** 7140 * e1000_io_error_detected - called when PCI error is detected 7141 * @pdev: Pointer to PCI device 7142 * @state: The current pci connection state 7143 * 7144 * This function is called after a PCI bus error affecting 7145 * this device has been detected. 7146 */ 7147 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7148 pci_channel_state_t state) 7149 { 7150 e1000e_pm_freeze(&pdev->dev); 7151 7152 if (state == pci_channel_io_perm_failure) 7153 return PCI_ERS_RESULT_DISCONNECT; 7154 7155 pci_disable_device(pdev); 7156 7157 /* Request a slot reset. */ 7158 return PCI_ERS_RESULT_NEED_RESET; 7159 } 7160 7161 /** 7162 * e1000_io_slot_reset - called after the pci bus has been reset. 7163 * @pdev: Pointer to PCI device 7164 * 7165 * Restart the card from scratch, as if from a cold-boot. Implementation 7166 * resembles the first-half of the e1000e_pm_resume routine. 7167 */ 7168 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7169 { 7170 struct net_device *netdev = pci_get_drvdata(pdev); 7171 struct e1000_adapter *adapter = netdev_priv(netdev); 7172 struct e1000_hw *hw = &adapter->hw; 7173 u16 aspm_disable_flag = 0; 7174 int err; 7175 pci_ers_result_t result; 7176 7177 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7178 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7179 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7180 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7181 if (aspm_disable_flag) 7182 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7183 7184 err = pci_enable_device_mem(pdev); 7185 if (err) { 7186 dev_err(&pdev->dev, 7187 "Cannot re-enable PCI device after reset.\n"); 7188 result = PCI_ERS_RESULT_DISCONNECT; 7189 } else { 7190 pdev->state_saved = true; 7191 pci_restore_state(pdev); 7192 pci_set_master(pdev); 7193 7194 pci_enable_wake(pdev, PCI_D3hot, 0); 7195 pci_enable_wake(pdev, PCI_D3cold, 0); 7196 7197 e1000e_reset(adapter); 7198 ew32(WUS, ~0); 7199 result = PCI_ERS_RESULT_RECOVERED; 7200 } 7201 7202 return result; 7203 } 7204 7205 /** 7206 * e1000_io_resume - called when traffic can start flowing again. 7207 * @pdev: Pointer to PCI device 7208 * 7209 * This callback is called when the error recovery driver tells us that 7210 * its OK to resume normal operation. Implementation resembles the 7211 * second-half of the e1000e_pm_resume routine. 7212 */ 7213 static void e1000_io_resume(struct pci_dev *pdev) 7214 { 7215 struct net_device *netdev = pci_get_drvdata(pdev); 7216 struct e1000_adapter *adapter = netdev_priv(netdev); 7217 7218 e1000_init_manageability_pt(adapter); 7219 7220 e1000e_pm_thaw(&pdev->dev); 7221 7222 /* If the controller has AMT, do not set DRV_LOAD until the interface 7223 * is up. For all other cases, let the f/w know that the h/w is now 7224 * under the control of the driver. 7225 */ 7226 if (!(adapter->flags & FLAG_HAS_AMT)) 7227 e1000e_get_hw_control(adapter); 7228 } 7229 7230 static void e1000_print_device_info(struct e1000_adapter *adapter) 7231 { 7232 struct e1000_hw *hw = &adapter->hw; 7233 struct net_device *netdev = adapter->netdev; 7234 u32 ret_val; 7235 u8 pba_str[E1000_PBANUM_LENGTH]; 7236 7237 /* print bus type/speed/width info */ 7238 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7239 /* bus width */ 7240 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7241 "Width x1"), 7242 /* MAC address */ 7243 netdev->dev_addr); 7244 e_info("Intel(R) PRO/%s Network Connection\n", 7245 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7246 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7247 E1000_PBANUM_LENGTH); 7248 if (ret_val) 7249 strscpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7250 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7251 hw->mac.type, hw->phy.type, pba_str); 7252 } 7253 7254 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7255 { 7256 struct e1000_hw *hw = &adapter->hw; 7257 int ret_val; 7258 u16 buf = 0; 7259 7260 if (hw->mac.type != e1000_82573) 7261 return; 7262 7263 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7264 le16_to_cpus(&buf); 7265 if (!ret_val && (!(buf & BIT(0)))) { 7266 /* Deep Smart Power Down (DSPD) */ 7267 dev_warn(&adapter->pdev->dev, 7268 "Warning: detected DSPD enabled in EEPROM\n"); 7269 } 7270 } 7271 7272 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7273 netdev_features_t features) 7274 { 7275 struct e1000_adapter *adapter = netdev_priv(netdev); 7276 struct e1000_hw *hw = &adapter->hw; 7277 7278 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7279 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7280 features &= ~NETIF_F_RXFCS; 7281 7282 /* Since there is no support for separate Rx/Tx vlan accel 7283 * enable/disable make sure Tx flag is always in same state as Rx. 7284 */ 7285 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7286 features |= NETIF_F_HW_VLAN_CTAG_TX; 7287 else 7288 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7289 7290 return features; 7291 } 7292 7293 static int e1000_set_features(struct net_device *netdev, 7294 netdev_features_t features) 7295 { 7296 struct e1000_adapter *adapter = netdev_priv(netdev); 7297 netdev_features_t changed = features ^ netdev->features; 7298 7299 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7300 adapter->flags |= FLAG_TSO_FORCE; 7301 7302 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7303 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7304 NETIF_F_RXALL))) 7305 return 0; 7306 7307 if (changed & NETIF_F_RXFCS) { 7308 if (features & NETIF_F_RXFCS) { 7309 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7310 } else { 7311 /* We need to take it back to defaults, which might mean 7312 * stripping is still disabled at the adapter level. 7313 */ 7314 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7315 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7316 else 7317 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7318 } 7319 } 7320 7321 netdev->features = features; 7322 7323 if (netif_running(netdev)) 7324 e1000e_reinit_locked(adapter); 7325 else 7326 e1000e_reset(adapter); 7327 7328 return 1; 7329 } 7330 7331 static const struct net_device_ops e1000e_netdev_ops = { 7332 .ndo_open = e1000e_open, 7333 .ndo_stop = e1000e_close, 7334 .ndo_start_xmit = e1000_xmit_frame, 7335 .ndo_get_stats64 = e1000e_get_stats64, 7336 .ndo_set_rx_mode = e1000e_set_rx_mode, 7337 .ndo_set_mac_address = e1000_set_mac, 7338 .ndo_change_mtu = e1000_change_mtu, 7339 .ndo_eth_ioctl = e1000_ioctl, 7340 .ndo_tx_timeout = e1000_tx_timeout, 7341 .ndo_validate_addr = eth_validate_addr, 7342 7343 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7344 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7345 #ifdef CONFIG_NET_POLL_CONTROLLER 7346 .ndo_poll_controller = e1000_netpoll, 7347 #endif 7348 .ndo_set_features = e1000_set_features, 7349 .ndo_fix_features = e1000_fix_features, 7350 .ndo_features_check = passthru_features_check, 7351 .ndo_hwtstamp_get = e1000e_hwtstamp_get, 7352 .ndo_hwtstamp_set = e1000e_hwtstamp_set, 7353 }; 7354 7355 /** 7356 * e1000_probe - Device Initialization Routine 7357 * @pdev: PCI device information struct 7358 * @ent: entry in e1000_pci_tbl 7359 * 7360 * Returns 0 on success, negative on failure 7361 * 7362 * e1000_probe initializes an adapter identified by a pci_dev structure. 7363 * The OS initialization, configuring of the adapter private structure, 7364 * and a hardware reset occur. 7365 **/ 7366 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7367 { 7368 struct net_device *netdev; 7369 struct e1000_adapter *adapter; 7370 struct e1000_hw *hw; 7371 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7372 resource_size_t mmio_start, mmio_len; 7373 resource_size_t flash_start, flash_len; 7374 static int cards_found; 7375 u16 aspm_disable_flag = 0; 7376 u16 eeprom_data = 0; 7377 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7378 int bars, i, err; 7379 s32 ret_val = 0; 7380 7381 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7382 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7383 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7384 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7385 if (aspm_disable_flag) 7386 e1000e_disable_aspm(pdev, aspm_disable_flag); 7387 7388 err = pci_enable_device_mem(pdev); 7389 if (err) 7390 return err; 7391 7392 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7393 if (err) { 7394 dev_err(&pdev->dev, 7395 "No usable DMA configuration, aborting\n"); 7396 goto err_dma; 7397 } 7398 7399 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7400 err = pci_request_selected_regions_exclusive(pdev, bars, 7401 e1000e_driver_name); 7402 if (err) 7403 goto err_pci_reg; 7404 7405 pci_set_master(pdev); 7406 /* PCI config space info */ 7407 err = pci_save_state(pdev); 7408 if (err) 7409 goto err_alloc_etherdev; 7410 7411 err = -ENOMEM; 7412 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7413 if (!netdev) 7414 goto err_alloc_etherdev; 7415 7416 SET_NETDEV_DEV(netdev, &pdev->dev); 7417 7418 netdev->irq = pdev->irq; 7419 7420 pci_set_drvdata(pdev, netdev); 7421 adapter = netdev_priv(netdev); 7422 hw = &adapter->hw; 7423 adapter->netdev = netdev; 7424 adapter->pdev = pdev; 7425 adapter->ei = ei; 7426 adapter->pba = ei->pba; 7427 adapter->flags = ei->flags; 7428 adapter->flags2 = ei->flags2; 7429 adapter->hw.adapter = adapter; 7430 adapter->hw.mac.type = ei->mac; 7431 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7432 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7433 7434 mmio_start = pci_resource_start(pdev, 0); 7435 mmio_len = pci_resource_len(pdev, 0); 7436 7437 err = -EIO; 7438 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7439 if (!adapter->hw.hw_addr) 7440 goto err_ioremap; 7441 7442 if ((adapter->flags & FLAG_HAS_FLASH) && 7443 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7444 (hw->mac.type < e1000_pch_spt)) { 7445 flash_start = pci_resource_start(pdev, 1); 7446 flash_len = pci_resource_len(pdev, 1); 7447 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7448 if (!adapter->hw.flash_address) 7449 goto err_flashmap; 7450 } 7451 7452 /* Set default EEE advertisement */ 7453 if (adapter->flags2 & FLAG2_HAS_EEE) 7454 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7455 7456 /* construct the net_device struct */ 7457 netdev->netdev_ops = &e1000e_netdev_ops; 7458 e1000e_set_ethtool_ops(netdev); 7459 netdev->watchdog_timeo = 5 * HZ; 7460 netif_napi_add(netdev, &adapter->napi, e1000e_poll); 7461 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7462 7463 netdev->mem_start = mmio_start; 7464 netdev->mem_end = mmio_start + mmio_len; 7465 7466 adapter->bd_number = cards_found++; 7467 7468 e1000e_check_options(adapter); 7469 7470 /* setup adapter struct */ 7471 err = e1000_sw_init(adapter); 7472 if (err) 7473 goto err_sw_init; 7474 7475 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7476 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7477 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7478 7479 err = ei->get_variants(adapter); 7480 if (err) 7481 goto err_hw_init; 7482 7483 if ((adapter->flags & FLAG_IS_ICH) && 7484 (adapter->flags & FLAG_READ_ONLY_NVM) && 7485 (hw->mac.type < e1000_pch_spt)) 7486 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7487 7488 hw->mac.ops.get_bus_info(&adapter->hw); 7489 7490 adapter->hw.phy.autoneg_wait_to_complete = 0; 7491 7492 /* Copper options */ 7493 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7494 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7495 adapter->hw.phy.disable_polarity_correction = 0; 7496 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7497 } 7498 7499 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7500 dev_info(&pdev->dev, 7501 "PHY reset is blocked due to SOL/IDER session.\n"); 7502 7503 /* Set initial default active device features */ 7504 netdev->features = (NETIF_F_SG | 7505 NETIF_F_HW_VLAN_CTAG_RX | 7506 NETIF_F_HW_VLAN_CTAG_TX | 7507 NETIF_F_TSO | 7508 NETIF_F_TSO6 | 7509 NETIF_F_RXHASH | 7510 NETIF_F_RXCSUM | 7511 NETIF_F_HW_CSUM); 7512 7513 /* disable TSO for pcie and 10/100 speeds to avoid 7514 * some hardware issues and for i219 to fix transfer 7515 * speed being capped at 60% 7516 */ 7517 if (!(adapter->flags & FLAG_TSO_FORCE)) { 7518 switch (adapter->link_speed) { 7519 case SPEED_10: 7520 case SPEED_100: 7521 e_info("10/100 speed: disabling TSO\n"); 7522 netdev->features &= ~NETIF_F_TSO; 7523 netdev->features &= ~NETIF_F_TSO6; 7524 break; 7525 case SPEED_1000: 7526 netdev->features |= NETIF_F_TSO; 7527 netdev->features |= NETIF_F_TSO6; 7528 break; 7529 default: 7530 /* oops */ 7531 break; 7532 } 7533 if (hw->mac.type == e1000_pch_spt) { 7534 netdev->features &= ~NETIF_F_TSO; 7535 netdev->features &= ~NETIF_F_TSO6; 7536 } 7537 } 7538 7539 /* Set user-changeable features (subset of all device features) */ 7540 netdev->hw_features = netdev->features; 7541 netdev->hw_features |= NETIF_F_RXFCS; 7542 netdev->priv_flags |= IFF_SUPP_NOFCS; 7543 netdev->hw_features |= NETIF_F_RXALL; 7544 7545 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7546 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7547 7548 netdev->vlan_features |= (NETIF_F_SG | 7549 NETIF_F_TSO | 7550 NETIF_F_TSO6 | 7551 NETIF_F_HW_CSUM); 7552 7553 netdev->priv_flags |= IFF_UNICAST_FLT; 7554 7555 netdev->features |= NETIF_F_HIGHDMA; 7556 netdev->vlan_features |= NETIF_F_HIGHDMA; 7557 7558 /* MTU range: 68 - max_hw_frame_size */ 7559 netdev->min_mtu = ETH_MIN_MTU; 7560 netdev->max_mtu = adapter->max_hw_frame_size - 7561 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7562 7563 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7564 adapter->flags |= FLAG_MNG_PT_ENABLED; 7565 7566 /* before reading the NVM, reset the controller to 7567 * put the device in a known good starting state 7568 */ 7569 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7570 7571 /* systems with ASPM and others may see the checksum fail on the first 7572 * attempt. Let's give it a few tries 7573 */ 7574 for (i = 0;; i++) { 7575 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7576 break; 7577 if (i == 2) { 7578 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7579 err = -EIO; 7580 goto err_eeprom; 7581 } 7582 } 7583 7584 e1000_eeprom_checks(adapter); 7585 7586 /* copy the MAC address */ 7587 if (e1000e_read_mac_addr(&adapter->hw)) 7588 dev_err(&pdev->dev, 7589 "NVM Read Error while reading MAC address\n"); 7590 7591 eth_hw_addr_set(netdev, adapter->hw.mac.addr); 7592 7593 if (!is_valid_ether_addr(netdev->dev_addr)) { 7594 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7595 netdev->dev_addr); 7596 err = -EIO; 7597 goto err_eeprom; 7598 } 7599 7600 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7601 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7602 7603 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7604 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7605 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7606 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7607 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7608 7609 /* Initialize link parameters. User can change them with ethtool */ 7610 adapter->hw.mac.autoneg = 1; 7611 adapter->fc_autoneg = true; 7612 adapter->hw.fc.requested_mode = e1000_fc_default; 7613 adapter->hw.fc.current_mode = e1000_fc_default; 7614 adapter->hw.phy.autoneg_advertised = 0x2f; 7615 7616 /* Initial Wake on LAN setting - If APM wake is enabled in 7617 * the EEPROM, enable the ACPI Magic Packet filter 7618 */ 7619 if (adapter->flags & FLAG_APME_IN_WUC) { 7620 /* APME bit in EEPROM is mapped to WUC.APME */ 7621 eeprom_data = er32(WUC); 7622 eeprom_apme_mask = E1000_WUC_APME; 7623 if ((hw->mac.type > e1000_ich10lan) && 7624 (eeprom_data & E1000_WUC_PHY_WAKE)) 7625 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7626 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7627 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7628 (adapter->hw.bus.func == 1)) 7629 ret_val = e1000_read_nvm(&adapter->hw, 7630 NVM_INIT_CONTROL3_PORT_B, 7631 1, &eeprom_data); 7632 else 7633 ret_val = e1000_read_nvm(&adapter->hw, 7634 NVM_INIT_CONTROL3_PORT_A, 7635 1, &eeprom_data); 7636 } 7637 7638 /* fetch WoL from EEPROM */ 7639 if (ret_val) 7640 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7641 else if (eeprom_data & eeprom_apme_mask) 7642 adapter->eeprom_wol |= E1000_WUFC_MAG; 7643 7644 /* now that we have the eeprom settings, apply the special cases 7645 * where the eeprom may be wrong or the board simply won't support 7646 * wake on lan on a particular port 7647 */ 7648 if (!(adapter->flags & FLAG_HAS_WOL)) 7649 adapter->eeprom_wol = 0; 7650 7651 /* initialize the wol settings based on the eeprom settings */ 7652 adapter->wol = adapter->eeprom_wol; 7653 7654 /* make sure adapter isn't asleep if manageability is enabled */ 7655 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7656 (hw->mac.ops.check_mng_mode(hw))) 7657 device_wakeup_enable(&pdev->dev); 7658 7659 /* save off EEPROM version number */ 7660 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7661 7662 if (ret_val) { 7663 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7664 adapter->eeprom_vers = 0; 7665 } 7666 7667 /* init PTP hardware clock */ 7668 e1000e_ptp_init(adapter); 7669 7670 /* reset the hardware with the new settings */ 7671 e1000e_reset(adapter); 7672 7673 /* If the controller has AMT, do not set DRV_LOAD until the interface 7674 * is up. For all other cases, let the f/w know that the h/w is now 7675 * under the control of the driver. 7676 */ 7677 if (!(adapter->flags & FLAG_HAS_AMT)) 7678 e1000e_get_hw_control(adapter); 7679 7680 if (hw->mac.type >= e1000_pch_cnp) 7681 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS; 7682 7683 strscpy(netdev->name, "eth%d", sizeof(netdev->name)); 7684 err = register_netdev(netdev); 7685 if (err) 7686 goto err_register; 7687 7688 /* carrier off reporting is important to ethtool even BEFORE open */ 7689 netif_carrier_off(netdev); 7690 7691 e1000_print_device_info(adapter); 7692 7693 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE); 7694 7695 if (pci_dev_run_wake(pdev)) 7696 pm_runtime_put_noidle(&pdev->dev); 7697 7698 return 0; 7699 7700 err_register: 7701 if (!(adapter->flags & FLAG_HAS_AMT)) 7702 e1000e_release_hw_control(adapter); 7703 err_eeprom: 7704 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7705 e1000_phy_hw_reset(&adapter->hw); 7706 err_hw_init: 7707 kfree(adapter->tx_ring); 7708 kfree(adapter->rx_ring); 7709 err_sw_init: 7710 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7711 iounmap(adapter->hw.flash_address); 7712 e1000e_reset_interrupt_capability(adapter); 7713 err_flashmap: 7714 iounmap(adapter->hw.hw_addr); 7715 err_ioremap: 7716 free_netdev(netdev); 7717 err_alloc_etherdev: 7718 pci_release_mem_regions(pdev); 7719 err_pci_reg: 7720 err_dma: 7721 pci_disable_device(pdev); 7722 return err; 7723 } 7724 7725 /** 7726 * e1000_remove - Device Removal Routine 7727 * @pdev: PCI device information struct 7728 * 7729 * e1000_remove is called by the PCI subsystem to alert the driver 7730 * that it should release a PCI device. This could be caused by a 7731 * Hot-Plug event, or because the driver is going to be removed from 7732 * memory. 7733 **/ 7734 static void e1000_remove(struct pci_dev *pdev) 7735 { 7736 struct net_device *netdev = pci_get_drvdata(pdev); 7737 struct e1000_adapter *adapter = netdev_priv(netdev); 7738 7739 e1000e_ptp_remove(adapter); 7740 7741 /* The timers may be rescheduled, so explicitly disable them 7742 * from being rescheduled. 7743 */ 7744 set_bit(__E1000_DOWN, &adapter->state); 7745 timer_delete_sync(&adapter->watchdog_timer); 7746 timer_delete_sync(&adapter->phy_info_timer); 7747 7748 cancel_work_sync(&adapter->reset_task); 7749 cancel_work_sync(&adapter->watchdog_task); 7750 cancel_work_sync(&adapter->downshift_task); 7751 cancel_work_sync(&adapter->update_phy_task); 7752 cancel_work_sync(&adapter->print_hang_task); 7753 7754 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7755 cancel_work_sync(&adapter->tx_hwtstamp_work); 7756 if (adapter->tx_hwtstamp_skb) { 7757 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7758 adapter->tx_hwtstamp_skb = NULL; 7759 } 7760 } 7761 7762 unregister_netdev(netdev); 7763 7764 if (pci_dev_run_wake(pdev)) 7765 pm_runtime_get_noresume(&pdev->dev); 7766 7767 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7768 * would have already happened in close and is redundant. 7769 */ 7770 e1000e_release_hw_control(adapter); 7771 7772 e1000e_reset_interrupt_capability(adapter); 7773 kfree(adapter->tx_ring); 7774 kfree(adapter->rx_ring); 7775 7776 iounmap(adapter->hw.hw_addr); 7777 if ((adapter->hw.flash_address) && 7778 (adapter->hw.mac.type < e1000_pch_spt)) 7779 iounmap(adapter->hw.flash_address); 7780 pci_release_mem_regions(pdev); 7781 7782 free_netdev(netdev); 7783 7784 pci_disable_device(pdev); 7785 } 7786 7787 /* PCI Error Recovery (ERS) */ 7788 static const struct pci_error_handlers e1000_err_handler = { 7789 .error_detected = e1000_io_error_detected, 7790 .slot_reset = e1000_io_slot_reset, 7791 .resume = e1000_io_resume, 7792 }; 7793 7794 static const struct pci_device_id e1000_pci_tbl[] = { 7795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7796 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7798 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7799 board_82571 }, 7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7805 7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7810 7811 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7813 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7814 7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7818 7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7820 board_80003es2lan }, 7821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7822 board_80003es2lan }, 7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7824 board_80003es2lan }, 7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7826 board_80003es2lan }, 7827 7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7836 7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7846 7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7850 7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7854 7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7859 7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7862 7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7868 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp }, 7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp }, 7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp }, 7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, 7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, 7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, 7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp }, 7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp }, 7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp }, 7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp }, 7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp }, 7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp }, 7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp }, 7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp }, 7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp }, 7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp }, 7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp }, 7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp }, 7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp }, 7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp }, 7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM19), board_pch_adp }, 7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V19), board_pch_adp }, 7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_mtp }, 7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_mtp }, 7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_mtp }, 7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp }, 7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp }, 7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp }, 7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp }, 7917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp }, 7918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp }, 7919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp }, 7920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp }, 7921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp }, 7922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp }, 7923 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp }, 7924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29), board_pch_mtp }, 7925 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29), board_pch_mtp }, 7926 7927 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7928 }; 7929 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7930 7931 static const struct dev_pm_ops e1000e_pm_ops = { 7932 .prepare = e1000e_pm_prepare, 7933 .suspend = e1000e_pm_suspend, 7934 .resume = e1000e_pm_resume, 7935 .freeze = e1000e_pm_freeze, 7936 .thaw = e1000e_pm_thaw, 7937 .poweroff = e1000e_pm_suspend, 7938 .restore = e1000e_pm_resume, 7939 RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7940 e1000e_pm_runtime_idle) 7941 }; 7942 7943 /* PCI Device API Driver */ 7944 static struct pci_driver e1000_driver = { 7945 .name = e1000e_driver_name, 7946 .id_table = e1000_pci_tbl, 7947 .probe = e1000_probe, 7948 .remove = e1000_remove, 7949 .driver.pm = pm_ptr(&e1000e_pm_ops), 7950 .shutdown = e1000_shutdown, 7951 .err_handler = &e1000_err_handler 7952 }; 7953 7954 /** 7955 * e1000_init_module - Driver Registration Routine 7956 * 7957 * e1000_init_module is the first routine called when the driver is 7958 * loaded. All it does is register with the PCI subsystem. 7959 **/ 7960 static int __init e1000_init_module(void) 7961 { 7962 pr_info("Intel(R) PRO/1000 Network Driver\n"); 7963 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7964 7965 return pci_register_driver(&e1000_driver); 7966 } 7967 module_init(e1000_init_module); 7968 7969 /** 7970 * e1000_exit_module - Driver Exit Cleanup Routine 7971 * 7972 * e1000_exit_module is called just before the driver is removed 7973 * from memory. 7974 **/ 7975 static void __exit e1000_exit_module(void) 7976 { 7977 pci_unregister_driver(&e1000_driver); 7978 } 7979 module_exit(e1000_exit_module); 7980 7981 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7982 MODULE_LICENSE("GPL v2"); 7983 7984 /* netdev.c */ 7985