1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/module.h> 25 #include <linux/types.h> 26 #include <linux/init.h> 27 #include <linux/pci.h> 28 #include <linux/vmalloc.h> 29 #include <linux/pagemap.h> 30 #include <linux/delay.h> 31 #include <linux/netdevice.h> 32 #include <linux/interrupt.h> 33 #include <linux/tcp.h> 34 #include <linux/ipv6.h> 35 #include <linux/slab.h> 36 #include <net/checksum.h> 37 #include <net/ip6_checksum.h> 38 #include <linux/ethtool.h> 39 #include <linux/if_vlan.h> 40 #include <linux/cpu.h> 41 #include <linux/smp.h> 42 #include <linux/pm_qos.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/aer.h> 45 #include <linux/prefetch.h> 46 47 #include "e1000.h" 48 49 #define DRV_EXTRAVERSION "-k" 50 51 #define DRV_VERSION "2.3.2" DRV_EXTRAVERSION 52 char e1000e_driver_name[] = "e1000e"; 53 const char e1000e_driver_version[] = DRV_VERSION; 54 55 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 56 static int debug = -1; 57 module_param(debug, int, 0); 58 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 59 60 static const struct e1000_info *e1000_info_tbl[] = { 61 [board_82571] = &e1000_82571_info, 62 [board_82572] = &e1000_82572_info, 63 [board_82573] = &e1000_82573_info, 64 [board_82574] = &e1000_82574_info, 65 [board_82583] = &e1000_82583_info, 66 [board_80003es2lan] = &e1000_es2_info, 67 [board_ich8lan] = &e1000_ich8_info, 68 [board_ich9lan] = &e1000_ich9_info, 69 [board_ich10lan] = &e1000_ich10_info, 70 [board_pchlan] = &e1000_pch_info, 71 [board_pch2lan] = &e1000_pch2_info, 72 [board_pch_lpt] = &e1000_pch_lpt_info, 73 }; 74 75 struct e1000_reg_info { 76 u32 ofs; 77 char *name; 78 }; 79 80 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 81 /* General Registers */ 82 {E1000_CTRL, "CTRL"}, 83 {E1000_STATUS, "STATUS"}, 84 {E1000_CTRL_EXT, "CTRL_EXT"}, 85 86 /* Interrupt Registers */ 87 {E1000_ICR, "ICR"}, 88 89 /* Rx Registers */ 90 {E1000_RCTL, "RCTL"}, 91 {E1000_RDLEN(0), "RDLEN"}, 92 {E1000_RDH(0), "RDH"}, 93 {E1000_RDT(0), "RDT"}, 94 {E1000_RDTR, "RDTR"}, 95 {E1000_RXDCTL(0), "RXDCTL"}, 96 {E1000_ERT, "ERT"}, 97 {E1000_RDBAL(0), "RDBAL"}, 98 {E1000_RDBAH(0), "RDBAH"}, 99 {E1000_RDFH, "RDFH"}, 100 {E1000_RDFT, "RDFT"}, 101 {E1000_RDFHS, "RDFHS"}, 102 {E1000_RDFTS, "RDFTS"}, 103 {E1000_RDFPC, "RDFPC"}, 104 105 /* Tx Registers */ 106 {E1000_TCTL, "TCTL"}, 107 {E1000_TDBAL(0), "TDBAL"}, 108 {E1000_TDBAH(0), "TDBAH"}, 109 {E1000_TDLEN(0), "TDLEN"}, 110 {E1000_TDH(0), "TDH"}, 111 {E1000_TDT(0), "TDT"}, 112 {E1000_TIDV, "TIDV"}, 113 {E1000_TXDCTL(0), "TXDCTL"}, 114 {E1000_TADV, "TADV"}, 115 {E1000_TARC(0), "TARC"}, 116 {E1000_TDFH, "TDFH"}, 117 {E1000_TDFT, "TDFT"}, 118 {E1000_TDFHS, "TDFHS"}, 119 {E1000_TDFTS, "TDFTS"}, 120 {E1000_TDFPC, "TDFPC"}, 121 122 /* List Terminator */ 123 {0, NULL} 124 }; 125 126 /** 127 * e1000_regdump - register printout routine 128 * @hw: pointer to the HW structure 129 * @reginfo: pointer to the register info table 130 **/ 131 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 132 { 133 int n = 0; 134 char rname[16]; 135 u32 regs[8]; 136 137 switch (reginfo->ofs) { 138 case E1000_RXDCTL(0): 139 for (n = 0; n < 2; n++) 140 regs[n] = __er32(hw, E1000_RXDCTL(n)); 141 break; 142 case E1000_TXDCTL(0): 143 for (n = 0; n < 2; n++) 144 regs[n] = __er32(hw, E1000_TXDCTL(n)); 145 break; 146 case E1000_TARC(0): 147 for (n = 0; n < 2; n++) 148 regs[n] = __er32(hw, E1000_TARC(n)); 149 break; 150 default: 151 pr_info("%-15s %08x\n", 152 reginfo->name, __er32(hw, reginfo->ofs)); 153 return; 154 } 155 156 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 157 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 158 } 159 160 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 161 struct e1000_buffer *bi) 162 { 163 int i; 164 struct e1000_ps_page *ps_page; 165 166 for (i = 0; i < adapter->rx_ps_pages; i++) { 167 ps_page = &bi->ps_pages[i]; 168 169 if (ps_page->page) { 170 pr_info("packet dump for ps_page %d:\n", i); 171 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 172 16, 1, page_address(ps_page->page), 173 PAGE_SIZE, true); 174 } 175 } 176 } 177 178 /** 179 * e1000e_dump - Print registers, Tx-ring and Rx-ring 180 * @adapter: board private structure 181 **/ 182 static void e1000e_dump(struct e1000_adapter *adapter) 183 { 184 struct net_device *netdev = adapter->netdev; 185 struct e1000_hw *hw = &adapter->hw; 186 struct e1000_reg_info *reginfo; 187 struct e1000_ring *tx_ring = adapter->tx_ring; 188 struct e1000_tx_desc *tx_desc; 189 struct my_u0 { 190 __le64 a; 191 __le64 b; 192 } *u0; 193 struct e1000_buffer *buffer_info; 194 struct e1000_ring *rx_ring = adapter->rx_ring; 195 union e1000_rx_desc_packet_split *rx_desc_ps; 196 union e1000_rx_desc_extended *rx_desc; 197 struct my_u1 { 198 __le64 a; 199 __le64 b; 200 __le64 c; 201 __le64 d; 202 } *u1; 203 u32 staterr; 204 int i = 0; 205 206 if (!netif_msg_hw(adapter)) 207 return; 208 209 /* Print netdevice Info */ 210 if (netdev) { 211 dev_info(&adapter->pdev->dev, "Net device Info\n"); 212 pr_info("Device Name state trans_start last_rx\n"); 213 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 214 netdev->state, netdev->trans_start, netdev->last_rx); 215 } 216 217 /* Print Registers */ 218 dev_info(&adapter->pdev->dev, "Register Dump\n"); 219 pr_info(" Register Name Value\n"); 220 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 221 reginfo->name; reginfo++) { 222 e1000_regdump(hw, reginfo); 223 } 224 225 /* Print Tx Ring Summary */ 226 if (!netdev || !netif_running(netdev)) 227 return; 228 229 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 230 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 231 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 232 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 233 0, tx_ring->next_to_use, tx_ring->next_to_clean, 234 (unsigned long long)buffer_info->dma, 235 buffer_info->length, 236 buffer_info->next_to_watch, 237 (unsigned long long)buffer_info->time_stamp); 238 239 /* Print Tx Ring */ 240 if (!netif_msg_tx_done(adapter)) 241 goto rx_ring_summary; 242 243 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 244 245 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 246 * 247 * Legacy Transmit Descriptor 248 * +--------------------------------------------------------------+ 249 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 250 * +--------------------------------------------------------------+ 251 * 8 | Special | CSS | Status | CMD | CSO | Length | 252 * +--------------------------------------------------------------+ 253 * 63 48 47 36 35 32 31 24 23 16 15 0 254 * 255 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 256 * 63 48 47 40 39 32 31 16 15 8 7 0 257 * +----------------------------------------------------------------+ 258 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 259 * +----------------------------------------------------------------+ 260 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 261 * +----------------------------------------------------------------+ 262 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 263 * 264 * Extended Data Descriptor (DTYP=0x1) 265 * +----------------------------------------------------------------+ 266 * 0 | Buffer Address [63:0] | 267 * +----------------------------------------------------------------+ 268 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 269 * +----------------------------------------------------------------+ 270 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 271 */ 272 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 273 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 274 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 275 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 276 const char *next_desc; 277 tx_desc = E1000_TX_DESC(*tx_ring, i); 278 buffer_info = &tx_ring->buffer_info[i]; 279 u0 = (struct my_u0 *)tx_desc; 280 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 281 next_desc = " NTC/U"; 282 else if (i == tx_ring->next_to_use) 283 next_desc = " NTU"; 284 else if (i == tx_ring->next_to_clean) 285 next_desc = " NTC"; 286 else 287 next_desc = ""; 288 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 289 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' : 290 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')), 291 i, 292 (unsigned long long)le64_to_cpu(u0->a), 293 (unsigned long long)le64_to_cpu(u0->b), 294 (unsigned long long)buffer_info->dma, 295 buffer_info->length, buffer_info->next_to_watch, 296 (unsigned long long)buffer_info->time_stamp, 297 buffer_info->skb, next_desc); 298 299 if (netif_msg_pktdata(adapter) && buffer_info->skb) 300 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 301 16, 1, buffer_info->skb->data, 302 buffer_info->skb->len, true); 303 } 304 305 /* Print Rx Ring Summary */ 306 rx_ring_summary: 307 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 308 pr_info("Queue [NTU] [NTC]\n"); 309 pr_info(" %5d %5X %5X\n", 310 0, rx_ring->next_to_use, rx_ring->next_to_clean); 311 312 /* Print Rx Ring */ 313 if (!netif_msg_rx_status(adapter)) 314 return; 315 316 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 317 switch (adapter->rx_ps_pages) { 318 case 1: 319 case 2: 320 case 3: 321 /* [Extended] Packet Split Receive Descriptor Format 322 * 323 * +-----------------------------------------------------+ 324 * 0 | Buffer Address 0 [63:0] | 325 * +-----------------------------------------------------+ 326 * 8 | Buffer Address 1 [63:0] | 327 * +-----------------------------------------------------+ 328 * 16 | Buffer Address 2 [63:0] | 329 * +-----------------------------------------------------+ 330 * 24 | Buffer Address 3 [63:0] | 331 * +-----------------------------------------------------+ 332 */ 333 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 334 /* [Extended] Receive Descriptor (Write-Back) Format 335 * 336 * 63 48 47 32 31 13 12 8 7 4 3 0 337 * +------------------------------------------------------+ 338 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 339 * | Checksum | Ident | | Queue | | Type | 340 * +------------------------------------------------------+ 341 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 342 * +------------------------------------------------------+ 343 * 63 48 47 32 31 20 19 0 344 */ 345 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 346 for (i = 0; i < rx_ring->count; i++) { 347 const char *next_desc; 348 buffer_info = &rx_ring->buffer_info[i]; 349 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 350 u1 = (struct my_u1 *)rx_desc_ps; 351 staterr = 352 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 353 354 if (i == rx_ring->next_to_use) 355 next_desc = " NTU"; 356 else if (i == rx_ring->next_to_clean) 357 next_desc = " NTC"; 358 else 359 next_desc = ""; 360 361 if (staterr & E1000_RXD_STAT_DD) { 362 /* Descriptor Done */ 363 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 364 "RWB", i, 365 (unsigned long long)le64_to_cpu(u1->a), 366 (unsigned long long)le64_to_cpu(u1->b), 367 (unsigned long long)le64_to_cpu(u1->c), 368 (unsigned long long)le64_to_cpu(u1->d), 369 buffer_info->skb, next_desc); 370 } else { 371 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 372 "R ", i, 373 (unsigned long long)le64_to_cpu(u1->a), 374 (unsigned long long)le64_to_cpu(u1->b), 375 (unsigned long long)le64_to_cpu(u1->c), 376 (unsigned long long)le64_to_cpu(u1->d), 377 (unsigned long long)buffer_info->dma, 378 buffer_info->skb, next_desc); 379 380 if (netif_msg_pktdata(adapter)) 381 e1000e_dump_ps_pages(adapter, 382 buffer_info); 383 } 384 } 385 break; 386 default: 387 case 0: 388 /* Extended Receive Descriptor (Read) Format 389 * 390 * +-----------------------------------------------------+ 391 * 0 | Buffer Address [63:0] | 392 * +-----------------------------------------------------+ 393 * 8 | Reserved | 394 * +-----------------------------------------------------+ 395 */ 396 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 397 /* Extended Receive Descriptor (Write-Back) Format 398 * 399 * 63 48 47 32 31 24 23 4 3 0 400 * +------------------------------------------------------+ 401 * | RSS Hash | | | | 402 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 403 * | Packet | IP | | | Type | 404 * | Checksum | Ident | | | | 405 * +------------------------------------------------------+ 406 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 407 * +------------------------------------------------------+ 408 * 63 48 47 32 31 20 19 0 409 */ 410 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 411 412 for (i = 0; i < rx_ring->count; i++) { 413 const char *next_desc; 414 415 buffer_info = &rx_ring->buffer_info[i]; 416 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 417 u1 = (struct my_u1 *)rx_desc; 418 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 419 420 if (i == rx_ring->next_to_use) 421 next_desc = " NTU"; 422 else if (i == rx_ring->next_to_clean) 423 next_desc = " NTC"; 424 else 425 next_desc = ""; 426 427 if (staterr & E1000_RXD_STAT_DD) { 428 /* Descriptor Done */ 429 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 430 "RWB", i, 431 (unsigned long long)le64_to_cpu(u1->a), 432 (unsigned long long)le64_to_cpu(u1->b), 433 buffer_info->skb, next_desc); 434 } else { 435 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 436 "R ", i, 437 (unsigned long long)le64_to_cpu(u1->a), 438 (unsigned long long)le64_to_cpu(u1->b), 439 (unsigned long long)buffer_info->dma, 440 buffer_info->skb, next_desc); 441 442 if (netif_msg_pktdata(adapter) && 443 buffer_info->skb) 444 print_hex_dump(KERN_INFO, "", 445 DUMP_PREFIX_ADDRESS, 16, 446 1, 447 buffer_info->skb->data, 448 adapter->rx_buffer_len, 449 true); 450 } 451 } 452 } 453 } 454 455 /** 456 * e1000_desc_unused - calculate if we have unused descriptors 457 **/ 458 static int e1000_desc_unused(struct e1000_ring *ring) 459 { 460 if (ring->next_to_clean > ring->next_to_use) 461 return ring->next_to_clean - ring->next_to_use - 1; 462 463 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 464 } 465 466 /** 467 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 468 * @adapter: board private structure 469 * @hwtstamps: time stamp structure to update 470 * @systim: unsigned 64bit system time value. 471 * 472 * Convert the system time value stored in the RX/TXSTMP registers into a 473 * hwtstamp which can be used by the upper level time stamping functions. 474 * 475 * The 'systim_lock' spinlock is used to protect the consistency of the 476 * system time value. This is needed because reading the 64 bit time 477 * value involves reading two 32 bit registers. The first read latches the 478 * value. 479 **/ 480 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 481 struct skb_shared_hwtstamps *hwtstamps, 482 u64 systim) 483 { 484 u64 ns; 485 unsigned long flags; 486 487 spin_lock_irqsave(&adapter->systim_lock, flags); 488 ns = timecounter_cyc2time(&adapter->tc, systim); 489 spin_unlock_irqrestore(&adapter->systim_lock, flags); 490 491 memset(hwtstamps, 0, sizeof(*hwtstamps)); 492 hwtstamps->hwtstamp = ns_to_ktime(ns); 493 } 494 495 /** 496 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 497 * @adapter: board private structure 498 * @status: descriptor extended error and status field 499 * @skb: particular skb to include time stamp 500 * 501 * If the time stamp is valid, convert it into the timecounter ns value 502 * and store that result into the shhwtstamps structure which is passed 503 * up the network stack. 504 **/ 505 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 506 struct sk_buff *skb) 507 { 508 struct e1000_hw *hw = &adapter->hw; 509 u64 rxstmp; 510 511 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 512 !(status & E1000_RXDEXT_STATERR_TST) || 513 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 514 return; 515 516 /* The Rx time stamp registers contain the time stamp. No other 517 * received packet will be time stamped until the Rx time stamp 518 * registers are read. Because only one packet can be time stamped 519 * at a time, the register values must belong to this packet and 520 * therefore none of the other additional attributes need to be 521 * compared. 522 */ 523 rxstmp = (u64)er32(RXSTMPL); 524 rxstmp |= (u64)er32(RXSTMPH) << 32; 525 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 526 527 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 528 } 529 530 /** 531 * e1000_receive_skb - helper function to handle Rx indications 532 * @adapter: board private structure 533 * @staterr: descriptor extended error and status field as written by hardware 534 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 535 * @skb: pointer to sk_buff to be indicated to stack 536 **/ 537 static void e1000_receive_skb(struct e1000_adapter *adapter, 538 struct net_device *netdev, struct sk_buff *skb, 539 u32 staterr, __le16 vlan) 540 { 541 u16 tag = le16_to_cpu(vlan); 542 543 e1000e_rx_hwtstamp(adapter, staterr, skb); 544 545 skb->protocol = eth_type_trans(skb, netdev); 546 547 if (staterr & E1000_RXD_STAT_VP) 548 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 549 550 napi_gro_receive(&adapter->napi, skb); 551 } 552 553 /** 554 * e1000_rx_checksum - Receive Checksum Offload 555 * @adapter: board private structure 556 * @status_err: receive descriptor status and error fields 557 * @csum: receive descriptor csum field 558 * @sk_buff: socket buffer with received data 559 **/ 560 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 561 struct sk_buff *skb) 562 { 563 u16 status = (u16)status_err; 564 u8 errors = (u8)(status_err >> 24); 565 566 skb_checksum_none_assert(skb); 567 568 /* Rx checksum disabled */ 569 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 570 return; 571 572 /* Ignore Checksum bit is set */ 573 if (status & E1000_RXD_STAT_IXSM) 574 return; 575 576 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 577 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 578 /* let the stack verify checksum errors */ 579 adapter->hw_csum_err++; 580 return; 581 } 582 583 /* TCP/UDP Checksum has not been calculated */ 584 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 585 return; 586 587 /* It must be a TCP or UDP packet with a valid checksum */ 588 skb->ip_summed = CHECKSUM_UNNECESSARY; 589 adapter->hw_csum_good++; 590 } 591 592 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 593 { 594 struct e1000_adapter *adapter = rx_ring->adapter; 595 struct e1000_hw *hw = &adapter->hw; 596 s32 ret_val = __ew32_prepare(hw); 597 598 writel(i, rx_ring->tail); 599 600 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { 601 u32 rctl = er32(RCTL); 602 603 ew32(RCTL, rctl & ~E1000_RCTL_EN); 604 e_err("ME firmware caused invalid RDT - resetting\n"); 605 schedule_work(&adapter->reset_task); 606 } 607 } 608 609 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 610 { 611 struct e1000_adapter *adapter = tx_ring->adapter; 612 struct e1000_hw *hw = &adapter->hw; 613 s32 ret_val = __ew32_prepare(hw); 614 615 writel(i, tx_ring->tail); 616 617 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { 618 u32 tctl = er32(TCTL); 619 620 ew32(TCTL, tctl & ~E1000_TCTL_EN); 621 e_err("ME firmware caused invalid TDT - resetting\n"); 622 schedule_work(&adapter->reset_task); 623 } 624 } 625 626 /** 627 * e1000_alloc_rx_buffers - Replace used receive buffers 628 * @rx_ring: Rx descriptor ring 629 **/ 630 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 631 int cleaned_count, gfp_t gfp) 632 { 633 struct e1000_adapter *adapter = rx_ring->adapter; 634 struct net_device *netdev = adapter->netdev; 635 struct pci_dev *pdev = adapter->pdev; 636 union e1000_rx_desc_extended *rx_desc; 637 struct e1000_buffer *buffer_info; 638 struct sk_buff *skb; 639 unsigned int i; 640 unsigned int bufsz = adapter->rx_buffer_len; 641 642 i = rx_ring->next_to_use; 643 buffer_info = &rx_ring->buffer_info[i]; 644 645 while (cleaned_count--) { 646 skb = buffer_info->skb; 647 if (skb) { 648 skb_trim(skb, 0); 649 goto map_skb; 650 } 651 652 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 653 if (!skb) { 654 /* Better luck next round */ 655 adapter->alloc_rx_buff_failed++; 656 break; 657 } 658 659 buffer_info->skb = skb; 660 map_skb: 661 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 662 adapter->rx_buffer_len, 663 DMA_FROM_DEVICE); 664 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 665 dev_err(&pdev->dev, "Rx DMA map failed\n"); 666 adapter->rx_dma_failed++; 667 break; 668 } 669 670 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 671 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 672 673 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 674 /* Force memory writes to complete before letting h/w 675 * know there are new descriptors to fetch. (Only 676 * applicable for weak-ordered memory model archs, 677 * such as IA-64). 678 */ 679 wmb(); 680 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 681 e1000e_update_rdt_wa(rx_ring, i); 682 else 683 writel(i, rx_ring->tail); 684 } 685 i++; 686 if (i == rx_ring->count) 687 i = 0; 688 buffer_info = &rx_ring->buffer_info[i]; 689 } 690 691 rx_ring->next_to_use = i; 692 } 693 694 /** 695 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 696 * @rx_ring: Rx descriptor ring 697 **/ 698 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 699 int cleaned_count, gfp_t gfp) 700 { 701 struct e1000_adapter *adapter = rx_ring->adapter; 702 struct net_device *netdev = adapter->netdev; 703 struct pci_dev *pdev = adapter->pdev; 704 union e1000_rx_desc_packet_split *rx_desc; 705 struct e1000_buffer *buffer_info; 706 struct e1000_ps_page *ps_page; 707 struct sk_buff *skb; 708 unsigned int i, j; 709 710 i = rx_ring->next_to_use; 711 buffer_info = &rx_ring->buffer_info[i]; 712 713 while (cleaned_count--) { 714 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 715 716 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 717 ps_page = &buffer_info->ps_pages[j]; 718 if (j >= adapter->rx_ps_pages) { 719 /* all unused desc entries get hw null ptr */ 720 rx_desc->read.buffer_addr[j + 1] = 721 ~cpu_to_le64(0); 722 continue; 723 } 724 if (!ps_page->page) { 725 ps_page->page = alloc_page(gfp); 726 if (!ps_page->page) { 727 adapter->alloc_rx_buff_failed++; 728 goto no_buffers; 729 } 730 ps_page->dma = dma_map_page(&pdev->dev, 731 ps_page->page, 732 0, PAGE_SIZE, 733 DMA_FROM_DEVICE); 734 if (dma_mapping_error(&pdev->dev, 735 ps_page->dma)) { 736 dev_err(&adapter->pdev->dev, 737 "Rx DMA page map failed\n"); 738 adapter->rx_dma_failed++; 739 goto no_buffers; 740 } 741 } 742 /* Refresh the desc even if buffer_addrs 743 * didn't change because each write-back 744 * erases this info. 745 */ 746 rx_desc->read.buffer_addr[j + 1] = 747 cpu_to_le64(ps_page->dma); 748 } 749 750 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 751 gfp); 752 753 if (!skb) { 754 adapter->alloc_rx_buff_failed++; 755 break; 756 } 757 758 buffer_info->skb = skb; 759 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 760 adapter->rx_ps_bsize0, 761 DMA_FROM_DEVICE); 762 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 763 dev_err(&pdev->dev, "Rx DMA map failed\n"); 764 adapter->rx_dma_failed++; 765 /* cleanup skb */ 766 dev_kfree_skb_any(skb); 767 buffer_info->skb = NULL; 768 break; 769 } 770 771 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 772 773 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 774 /* Force memory writes to complete before letting h/w 775 * know there are new descriptors to fetch. (Only 776 * applicable for weak-ordered memory model archs, 777 * such as IA-64). 778 */ 779 wmb(); 780 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 781 e1000e_update_rdt_wa(rx_ring, i << 1); 782 else 783 writel(i << 1, rx_ring->tail); 784 } 785 786 i++; 787 if (i == rx_ring->count) 788 i = 0; 789 buffer_info = &rx_ring->buffer_info[i]; 790 } 791 792 no_buffers: 793 rx_ring->next_to_use = i; 794 } 795 796 /** 797 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 798 * @rx_ring: Rx descriptor ring 799 * @cleaned_count: number of buffers to allocate this pass 800 **/ 801 802 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 803 int cleaned_count, gfp_t gfp) 804 { 805 struct e1000_adapter *adapter = rx_ring->adapter; 806 struct net_device *netdev = adapter->netdev; 807 struct pci_dev *pdev = adapter->pdev; 808 union e1000_rx_desc_extended *rx_desc; 809 struct e1000_buffer *buffer_info; 810 struct sk_buff *skb; 811 unsigned int i; 812 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 813 814 i = rx_ring->next_to_use; 815 buffer_info = &rx_ring->buffer_info[i]; 816 817 while (cleaned_count--) { 818 skb = buffer_info->skb; 819 if (skb) { 820 skb_trim(skb, 0); 821 goto check_page; 822 } 823 824 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 825 if (unlikely(!skb)) { 826 /* Better luck next round */ 827 adapter->alloc_rx_buff_failed++; 828 break; 829 } 830 831 buffer_info->skb = skb; 832 check_page: 833 /* allocate a new page if necessary */ 834 if (!buffer_info->page) { 835 buffer_info->page = alloc_page(gfp); 836 if (unlikely(!buffer_info->page)) { 837 adapter->alloc_rx_buff_failed++; 838 break; 839 } 840 } 841 842 if (!buffer_info->dma) { 843 buffer_info->dma = dma_map_page(&pdev->dev, 844 buffer_info->page, 0, 845 PAGE_SIZE, 846 DMA_FROM_DEVICE); 847 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 848 adapter->alloc_rx_buff_failed++; 849 break; 850 } 851 } 852 853 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 854 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 855 856 if (unlikely(++i == rx_ring->count)) 857 i = 0; 858 buffer_info = &rx_ring->buffer_info[i]; 859 } 860 861 if (likely(rx_ring->next_to_use != i)) { 862 rx_ring->next_to_use = i; 863 if (unlikely(i-- == 0)) 864 i = (rx_ring->count - 1); 865 866 /* Force memory writes to complete before letting h/w 867 * know there are new descriptors to fetch. (Only 868 * applicable for weak-ordered memory model archs, 869 * such as IA-64). 870 */ 871 wmb(); 872 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 873 e1000e_update_rdt_wa(rx_ring, i); 874 else 875 writel(i, rx_ring->tail); 876 } 877 } 878 879 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 880 struct sk_buff *skb) 881 { 882 if (netdev->features & NETIF_F_RXHASH) 883 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 884 } 885 886 /** 887 * e1000_clean_rx_irq - Send received data up the network stack 888 * @rx_ring: Rx descriptor ring 889 * 890 * the return value indicates whether actual cleaning was done, there 891 * is no guarantee that everything was cleaned 892 **/ 893 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 894 int work_to_do) 895 { 896 struct e1000_adapter *adapter = rx_ring->adapter; 897 struct net_device *netdev = adapter->netdev; 898 struct pci_dev *pdev = adapter->pdev; 899 struct e1000_hw *hw = &adapter->hw; 900 union e1000_rx_desc_extended *rx_desc, *next_rxd; 901 struct e1000_buffer *buffer_info, *next_buffer; 902 u32 length, staterr; 903 unsigned int i; 904 int cleaned_count = 0; 905 bool cleaned = false; 906 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 907 908 i = rx_ring->next_to_clean; 909 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 910 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 911 buffer_info = &rx_ring->buffer_info[i]; 912 913 while (staterr & E1000_RXD_STAT_DD) { 914 struct sk_buff *skb; 915 916 if (*work_done >= work_to_do) 917 break; 918 (*work_done)++; 919 rmb(); /* read descriptor and rx_buffer_info after status DD */ 920 921 skb = buffer_info->skb; 922 buffer_info->skb = NULL; 923 924 prefetch(skb->data - NET_IP_ALIGN); 925 926 i++; 927 if (i == rx_ring->count) 928 i = 0; 929 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 930 prefetch(next_rxd); 931 932 next_buffer = &rx_ring->buffer_info[i]; 933 934 cleaned = true; 935 cleaned_count++; 936 dma_unmap_single(&pdev->dev, buffer_info->dma, 937 adapter->rx_buffer_len, DMA_FROM_DEVICE); 938 buffer_info->dma = 0; 939 940 length = le16_to_cpu(rx_desc->wb.upper.length); 941 942 /* !EOP means multiple descriptors were used to store a single 943 * packet, if that's the case we need to toss it. In fact, we 944 * need to toss every packet with the EOP bit clear and the 945 * next frame that _does_ have the EOP bit set, as it is by 946 * definition only a frame fragment 947 */ 948 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 949 adapter->flags2 |= FLAG2_IS_DISCARDING; 950 951 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 952 /* All receives must fit into a single buffer */ 953 e_dbg("Receive packet consumed multiple buffers\n"); 954 /* recycle */ 955 buffer_info->skb = skb; 956 if (staterr & E1000_RXD_STAT_EOP) 957 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 958 goto next_desc; 959 } 960 961 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 962 !(netdev->features & NETIF_F_RXALL))) { 963 /* recycle */ 964 buffer_info->skb = skb; 965 goto next_desc; 966 } 967 968 /* adjust length to remove Ethernet CRC */ 969 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 970 /* If configured to store CRC, don't subtract FCS, 971 * but keep the FCS bytes out of the total_rx_bytes 972 * counter 973 */ 974 if (netdev->features & NETIF_F_RXFCS) 975 total_rx_bytes -= 4; 976 else 977 length -= 4; 978 } 979 980 total_rx_bytes += length; 981 total_rx_packets++; 982 983 /* code added for copybreak, this should improve 984 * performance for small packets with large amounts 985 * of reassembly being done in the stack 986 */ 987 if (length < copybreak) { 988 struct sk_buff *new_skb = 989 netdev_alloc_skb_ip_align(netdev, length); 990 if (new_skb) { 991 skb_copy_to_linear_data_offset(new_skb, 992 -NET_IP_ALIGN, 993 (skb->data - 994 NET_IP_ALIGN), 995 (length + 996 NET_IP_ALIGN)); 997 /* save the skb in buffer_info as good */ 998 buffer_info->skb = skb; 999 skb = new_skb; 1000 } 1001 /* else just continue with the old one */ 1002 } 1003 /* end copybreak code */ 1004 skb_put(skb, length); 1005 1006 /* Receive Checksum Offload */ 1007 e1000_rx_checksum(adapter, staterr, skb); 1008 1009 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1010 1011 e1000_receive_skb(adapter, netdev, skb, staterr, 1012 rx_desc->wb.upper.vlan); 1013 1014 next_desc: 1015 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1016 1017 /* return some buffers to hardware, one at a time is too slow */ 1018 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1019 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1020 GFP_ATOMIC); 1021 cleaned_count = 0; 1022 } 1023 1024 /* use prefetched values */ 1025 rx_desc = next_rxd; 1026 buffer_info = next_buffer; 1027 1028 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1029 } 1030 rx_ring->next_to_clean = i; 1031 1032 cleaned_count = e1000_desc_unused(rx_ring); 1033 if (cleaned_count) 1034 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1035 1036 adapter->total_rx_bytes += total_rx_bytes; 1037 adapter->total_rx_packets += total_rx_packets; 1038 return cleaned; 1039 } 1040 1041 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1042 struct e1000_buffer *buffer_info) 1043 { 1044 struct e1000_adapter *adapter = tx_ring->adapter; 1045 1046 if (buffer_info->dma) { 1047 if (buffer_info->mapped_as_page) 1048 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1049 buffer_info->length, DMA_TO_DEVICE); 1050 else 1051 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1052 buffer_info->length, DMA_TO_DEVICE); 1053 buffer_info->dma = 0; 1054 } 1055 if (buffer_info->skb) { 1056 dev_kfree_skb_any(buffer_info->skb); 1057 buffer_info->skb = NULL; 1058 } 1059 buffer_info->time_stamp = 0; 1060 } 1061 1062 static void e1000_print_hw_hang(struct work_struct *work) 1063 { 1064 struct e1000_adapter *adapter = container_of(work, 1065 struct e1000_adapter, 1066 print_hang_task); 1067 struct net_device *netdev = adapter->netdev; 1068 struct e1000_ring *tx_ring = adapter->tx_ring; 1069 unsigned int i = tx_ring->next_to_clean; 1070 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1071 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1072 struct e1000_hw *hw = &adapter->hw; 1073 u16 phy_status, phy_1000t_status, phy_ext_status; 1074 u16 pci_status; 1075 1076 if (test_bit(__E1000_DOWN, &adapter->state)) 1077 return; 1078 1079 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1080 /* May be block on write-back, flush and detect again 1081 * flush pending descriptor writebacks to memory 1082 */ 1083 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1084 /* execute the writes immediately */ 1085 e1e_flush(); 1086 /* Due to rare timing issues, write to TIDV again to ensure 1087 * the write is successful 1088 */ 1089 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1090 /* execute the writes immediately */ 1091 e1e_flush(); 1092 adapter->tx_hang_recheck = true; 1093 return; 1094 } 1095 adapter->tx_hang_recheck = false; 1096 1097 if (er32(TDH(0)) == er32(TDT(0))) { 1098 e_dbg("false hang detected, ignoring\n"); 1099 return; 1100 } 1101 1102 /* Real hang detected */ 1103 netif_stop_queue(netdev); 1104 1105 e1e_rphy(hw, MII_BMSR, &phy_status); 1106 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1107 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1108 1109 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1110 1111 /* detected Hardware unit hang */ 1112 e_err("Detected Hardware Unit Hang:\n" 1113 " TDH <%x>\n" 1114 " TDT <%x>\n" 1115 " next_to_use <%x>\n" 1116 " next_to_clean <%x>\n" 1117 "buffer_info[next_to_clean]:\n" 1118 " time_stamp <%lx>\n" 1119 " next_to_watch <%x>\n" 1120 " jiffies <%lx>\n" 1121 " next_to_watch.status <%x>\n" 1122 "MAC Status <%x>\n" 1123 "PHY Status <%x>\n" 1124 "PHY 1000BASE-T Status <%x>\n" 1125 "PHY Extended Status <%x>\n" 1126 "PCI Status <%x>\n", 1127 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1128 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1129 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1130 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1131 1132 e1000e_dump(adapter); 1133 1134 /* Suggest workaround for known h/w issue */ 1135 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1136 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1137 } 1138 1139 /** 1140 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1141 * @work: pointer to work struct 1142 * 1143 * This work function polls the TSYNCTXCTL valid bit to determine when a 1144 * timestamp has been taken for the current stored skb. The timestamp must 1145 * be for this skb because only one such packet is allowed in the queue. 1146 */ 1147 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1148 { 1149 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1150 tx_hwtstamp_work); 1151 struct e1000_hw *hw = &adapter->hw; 1152 1153 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1154 struct skb_shared_hwtstamps shhwtstamps; 1155 u64 txstmp; 1156 1157 txstmp = er32(TXSTMPL); 1158 txstmp |= (u64)er32(TXSTMPH) << 32; 1159 1160 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1161 1162 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps); 1163 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1164 adapter->tx_hwtstamp_skb = NULL; 1165 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1166 + adapter->tx_timeout_factor * HZ)) { 1167 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1168 adapter->tx_hwtstamp_skb = NULL; 1169 adapter->tx_hwtstamp_timeouts++; 1170 e_warn("clearing Tx timestamp hang\n"); 1171 } else { 1172 /* reschedule to check later */ 1173 schedule_work(&adapter->tx_hwtstamp_work); 1174 } 1175 } 1176 1177 /** 1178 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1179 * @tx_ring: Tx descriptor ring 1180 * 1181 * the return value indicates whether actual cleaning was done, there 1182 * is no guarantee that everything was cleaned 1183 **/ 1184 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1185 { 1186 struct e1000_adapter *adapter = tx_ring->adapter; 1187 struct net_device *netdev = adapter->netdev; 1188 struct e1000_hw *hw = &adapter->hw; 1189 struct e1000_tx_desc *tx_desc, *eop_desc; 1190 struct e1000_buffer *buffer_info; 1191 unsigned int i, eop; 1192 unsigned int count = 0; 1193 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1194 unsigned int bytes_compl = 0, pkts_compl = 0; 1195 1196 i = tx_ring->next_to_clean; 1197 eop = tx_ring->buffer_info[i].next_to_watch; 1198 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1199 1200 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1201 (count < tx_ring->count)) { 1202 bool cleaned = false; 1203 1204 rmb(); /* read buffer_info after eop_desc */ 1205 for (; !cleaned; count++) { 1206 tx_desc = E1000_TX_DESC(*tx_ring, i); 1207 buffer_info = &tx_ring->buffer_info[i]; 1208 cleaned = (i == eop); 1209 1210 if (cleaned) { 1211 total_tx_packets += buffer_info->segs; 1212 total_tx_bytes += buffer_info->bytecount; 1213 if (buffer_info->skb) { 1214 bytes_compl += buffer_info->skb->len; 1215 pkts_compl++; 1216 } 1217 } 1218 1219 e1000_put_txbuf(tx_ring, buffer_info); 1220 tx_desc->upper.data = 0; 1221 1222 i++; 1223 if (i == tx_ring->count) 1224 i = 0; 1225 } 1226 1227 if (i == tx_ring->next_to_use) 1228 break; 1229 eop = tx_ring->buffer_info[i].next_to_watch; 1230 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1231 } 1232 1233 tx_ring->next_to_clean = i; 1234 1235 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1236 1237 #define TX_WAKE_THRESHOLD 32 1238 if (count && netif_carrier_ok(netdev) && 1239 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1240 /* Make sure that anybody stopping the queue after this 1241 * sees the new next_to_clean. 1242 */ 1243 smp_mb(); 1244 1245 if (netif_queue_stopped(netdev) && 1246 !(test_bit(__E1000_DOWN, &adapter->state))) { 1247 netif_wake_queue(netdev); 1248 ++adapter->restart_queue; 1249 } 1250 } 1251 1252 if (adapter->detect_tx_hung) { 1253 /* Detect a transmit hang in hardware, this serializes the 1254 * check with the clearing of time_stamp and movement of i 1255 */ 1256 adapter->detect_tx_hung = false; 1257 if (tx_ring->buffer_info[i].time_stamp && 1258 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1259 + (adapter->tx_timeout_factor * HZ)) && 1260 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1261 schedule_work(&adapter->print_hang_task); 1262 else 1263 adapter->tx_hang_recheck = false; 1264 } 1265 adapter->total_tx_bytes += total_tx_bytes; 1266 adapter->total_tx_packets += total_tx_packets; 1267 return count < tx_ring->count; 1268 } 1269 1270 /** 1271 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1272 * @rx_ring: Rx descriptor ring 1273 * 1274 * the return value indicates whether actual cleaning was done, there 1275 * is no guarantee that everything was cleaned 1276 **/ 1277 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1278 int work_to_do) 1279 { 1280 struct e1000_adapter *adapter = rx_ring->adapter; 1281 struct e1000_hw *hw = &adapter->hw; 1282 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1283 struct net_device *netdev = adapter->netdev; 1284 struct pci_dev *pdev = adapter->pdev; 1285 struct e1000_buffer *buffer_info, *next_buffer; 1286 struct e1000_ps_page *ps_page; 1287 struct sk_buff *skb; 1288 unsigned int i, j; 1289 u32 length, staterr; 1290 int cleaned_count = 0; 1291 bool cleaned = false; 1292 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1293 1294 i = rx_ring->next_to_clean; 1295 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1296 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1297 buffer_info = &rx_ring->buffer_info[i]; 1298 1299 while (staterr & E1000_RXD_STAT_DD) { 1300 if (*work_done >= work_to_do) 1301 break; 1302 (*work_done)++; 1303 skb = buffer_info->skb; 1304 rmb(); /* read descriptor and rx_buffer_info after status DD */ 1305 1306 /* in the packet split case this is header only */ 1307 prefetch(skb->data - NET_IP_ALIGN); 1308 1309 i++; 1310 if (i == rx_ring->count) 1311 i = 0; 1312 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1313 prefetch(next_rxd); 1314 1315 next_buffer = &rx_ring->buffer_info[i]; 1316 1317 cleaned = true; 1318 cleaned_count++; 1319 dma_unmap_single(&pdev->dev, buffer_info->dma, 1320 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1321 buffer_info->dma = 0; 1322 1323 /* see !EOP comment in other Rx routine */ 1324 if (!(staterr & E1000_RXD_STAT_EOP)) 1325 adapter->flags2 |= FLAG2_IS_DISCARDING; 1326 1327 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1328 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1329 dev_kfree_skb_irq(skb); 1330 if (staterr & E1000_RXD_STAT_EOP) 1331 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1332 goto next_desc; 1333 } 1334 1335 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1336 !(netdev->features & NETIF_F_RXALL))) { 1337 dev_kfree_skb_irq(skb); 1338 goto next_desc; 1339 } 1340 1341 length = le16_to_cpu(rx_desc->wb.middle.length0); 1342 1343 if (!length) { 1344 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1345 dev_kfree_skb_irq(skb); 1346 goto next_desc; 1347 } 1348 1349 /* Good Receive */ 1350 skb_put(skb, length); 1351 1352 { 1353 /* this looks ugly, but it seems compiler issues make 1354 * it more efficient than reusing j 1355 */ 1356 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1357 1358 /* page alloc/put takes too long and effects small 1359 * packet throughput, so unsplit small packets and 1360 * save the alloc/put only valid in softirq (napi) 1361 * context to call kmap_* 1362 */ 1363 if (l1 && (l1 <= copybreak) && 1364 ((length + l1) <= adapter->rx_ps_bsize0)) { 1365 u8 *vaddr; 1366 1367 ps_page = &buffer_info->ps_pages[0]; 1368 1369 /* there is no documentation about how to call 1370 * kmap_atomic, so we can't hold the mapping 1371 * very long 1372 */ 1373 dma_sync_single_for_cpu(&pdev->dev, 1374 ps_page->dma, 1375 PAGE_SIZE, 1376 DMA_FROM_DEVICE); 1377 vaddr = kmap_atomic(ps_page->page); 1378 memcpy(skb_tail_pointer(skb), vaddr, l1); 1379 kunmap_atomic(vaddr); 1380 dma_sync_single_for_device(&pdev->dev, 1381 ps_page->dma, 1382 PAGE_SIZE, 1383 DMA_FROM_DEVICE); 1384 1385 /* remove the CRC */ 1386 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1387 if (!(netdev->features & NETIF_F_RXFCS)) 1388 l1 -= 4; 1389 } 1390 1391 skb_put(skb, l1); 1392 goto copydone; 1393 } /* if */ 1394 } 1395 1396 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1397 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1398 if (!length) 1399 break; 1400 1401 ps_page = &buffer_info->ps_pages[j]; 1402 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1403 DMA_FROM_DEVICE); 1404 ps_page->dma = 0; 1405 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1406 ps_page->page = NULL; 1407 skb->len += length; 1408 skb->data_len += length; 1409 skb->truesize += PAGE_SIZE; 1410 } 1411 1412 /* strip the ethernet crc, problem is we're using pages now so 1413 * this whole operation can get a little cpu intensive 1414 */ 1415 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1416 if (!(netdev->features & NETIF_F_RXFCS)) 1417 pskb_trim(skb, skb->len - 4); 1418 } 1419 1420 copydone: 1421 total_rx_bytes += skb->len; 1422 total_rx_packets++; 1423 1424 e1000_rx_checksum(adapter, staterr, skb); 1425 1426 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1427 1428 if (rx_desc->wb.upper.header_status & 1429 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1430 adapter->rx_hdr_split++; 1431 1432 e1000_receive_skb(adapter, netdev, skb, staterr, 1433 rx_desc->wb.middle.vlan); 1434 1435 next_desc: 1436 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1437 buffer_info->skb = NULL; 1438 1439 /* return some buffers to hardware, one at a time is too slow */ 1440 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1441 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1442 GFP_ATOMIC); 1443 cleaned_count = 0; 1444 } 1445 1446 /* use prefetched values */ 1447 rx_desc = next_rxd; 1448 buffer_info = next_buffer; 1449 1450 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1451 } 1452 rx_ring->next_to_clean = i; 1453 1454 cleaned_count = e1000_desc_unused(rx_ring); 1455 if (cleaned_count) 1456 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1457 1458 adapter->total_rx_bytes += total_rx_bytes; 1459 adapter->total_rx_packets += total_rx_packets; 1460 return cleaned; 1461 } 1462 1463 /** 1464 * e1000_consume_page - helper function 1465 **/ 1466 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1467 u16 length) 1468 { 1469 bi->page = NULL; 1470 skb->len += length; 1471 skb->data_len += length; 1472 skb->truesize += PAGE_SIZE; 1473 } 1474 1475 /** 1476 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1477 * @adapter: board private structure 1478 * 1479 * the return value indicates whether actual cleaning was done, there 1480 * is no guarantee that everything was cleaned 1481 **/ 1482 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1483 int work_to_do) 1484 { 1485 struct e1000_adapter *adapter = rx_ring->adapter; 1486 struct net_device *netdev = adapter->netdev; 1487 struct pci_dev *pdev = adapter->pdev; 1488 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1489 struct e1000_buffer *buffer_info, *next_buffer; 1490 u32 length, staterr; 1491 unsigned int i; 1492 int cleaned_count = 0; 1493 bool cleaned = false; 1494 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1495 struct skb_shared_info *shinfo; 1496 1497 i = rx_ring->next_to_clean; 1498 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1499 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1500 buffer_info = &rx_ring->buffer_info[i]; 1501 1502 while (staterr & E1000_RXD_STAT_DD) { 1503 struct sk_buff *skb; 1504 1505 if (*work_done >= work_to_do) 1506 break; 1507 (*work_done)++; 1508 rmb(); /* read descriptor and rx_buffer_info after status DD */ 1509 1510 skb = buffer_info->skb; 1511 buffer_info->skb = NULL; 1512 1513 ++i; 1514 if (i == rx_ring->count) 1515 i = 0; 1516 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1517 prefetch(next_rxd); 1518 1519 next_buffer = &rx_ring->buffer_info[i]; 1520 1521 cleaned = true; 1522 cleaned_count++; 1523 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1524 DMA_FROM_DEVICE); 1525 buffer_info->dma = 0; 1526 1527 length = le16_to_cpu(rx_desc->wb.upper.length); 1528 1529 /* errors is only valid for DD + EOP descriptors */ 1530 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1531 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1532 !(netdev->features & NETIF_F_RXALL)))) { 1533 /* recycle both page and skb */ 1534 buffer_info->skb = skb; 1535 /* an error means any chain goes out the window too */ 1536 if (rx_ring->rx_skb_top) 1537 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1538 rx_ring->rx_skb_top = NULL; 1539 goto next_desc; 1540 } 1541 #define rxtop (rx_ring->rx_skb_top) 1542 if (!(staterr & E1000_RXD_STAT_EOP)) { 1543 /* this descriptor is only the beginning (or middle) */ 1544 if (!rxtop) { 1545 /* this is the beginning of a chain */ 1546 rxtop = skb; 1547 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1548 0, length); 1549 } else { 1550 /* this is the middle of a chain */ 1551 shinfo = skb_shinfo(rxtop); 1552 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1553 buffer_info->page, 0, 1554 length); 1555 /* re-use the skb, only consumed the page */ 1556 buffer_info->skb = skb; 1557 } 1558 e1000_consume_page(buffer_info, rxtop, length); 1559 goto next_desc; 1560 } else { 1561 if (rxtop) { 1562 /* end of the chain */ 1563 shinfo = skb_shinfo(rxtop); 1564 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1565 buffer_info->page, 0, 1566 length); 1567 /* re-use the current skb, we only consumed the 1568 * page 1569 */ 1570 buffer_info->skb = skb; 1571 skb = rxtop; 1572 rxtop = NULL; 1573 e1000_consume_page(buffer_info, skb, length); 1574 } else { 1575 /* no chain, got EOP, this buf is the packet 1576 * copybreak to save the put_page/alloc_page 1577 */ 1578 if (length <= copybreak && 1579 skb_tailroom(skb) >= length) { 1580 u8 *vaddr; 1581 vaddr = kmap_atomic(buffer_info->page); 1582 memcpy(skb_tail_pointer(skb), vaddr, 1583 length); 1584 kunmap_atomic(vaddr); 1585 /* re-use the page, so don't erase 1586 * buffer_info->page 1587 */ 1588 skb_put(skb, length); 1589 } else { 1590 skb_fill_page_desc(skb, 0, 1591 buffer_info->page, 0, 1592 length); 1593 e1000_consume_page(buffer_info, skb, 1594 length); 1595 } 1596 } 1597 } 1598 1599 /* Receive Checksum Offload */ 1600 e1000_rx_checksum(adapter, staterr, skb); 1601 1602 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1603 1604 /* probably a little skewed due to removing CRC */ 1605 total_rx_bytes += skb->len; 1606 total_rx_packets++; 1607 1608 /* eth type trans needs skb->data to point to something */ 1609 if (!pskb_may_pull(skb, ETH_HLEN)) { 1610 e_err("pskb_may_pull failed.\n"); 1611 dev_kfree_skb_irq(skb); 1612 goto next_desc; 1613 } 1614 1615 e1000_receive_skb(adapter, netdev, skb, staterr, 1616 rx_desc->wb.upper.vlan); 1617 1618 next_desc: 1619 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1620 1621 /* return some buffers to hardware, one at a time is too slow */ 1622 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1623 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1624 GFP_ATOMIC); 1625 cleaned_count = 0; 1626 } 1627 1628 /* use prefetched values */ 1629 rx_desc = next_rxd; 1630 buffer_info = next_buffer; 1631 1632 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1633 } 1634 rx_ring->next_to_clean = i; 1635 1636 cleaned_count = e1000_desc_unused(rx_ring); 1637 if (cleaned_count) 1638 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1639 1640 adapter->total_rx_bytes += total_rx_bytes; 1641 adapter->total_rx_packets += total_rx_packets; 1642 return cleaned; 1643 } 1644 1645 /** 1646 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1647 * @rx_ring: Rx descriptor ring 1648 **/ 1649 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1650 { 1651 struct e1000_adapter *adapter = rx_ring->adapter; 1652 struct e1000_buffer *buffer_info; 1653 struct e1000_ps_page *ps_page; 1654 struct pci_dev *pdev = adapter->pdev; 1655 unsigned int i, j; 1656 1657 /* Free all the Rx ring sk_buffs */ 1658 for (i = 0; i < rx_ring->count; i++) { 1659 buffer_info = &rx_ring->buffer_info[i]; 1660 if (buffer_info->dma) { 1661 if (adapter->clean_rx == e1000_clean_rx_irq) 1662 dma_unmap_single(&pdev->dev, buffer_info->dma, 1663 adapter->rx_buffer_len, 1664 DMA_FROM_DEVICE); 1665 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1666 dma_unmap_page(&pdev->dev, buffer_info->dma, 1667 PAGE_SIZE, DMA_FROM_DEVICE); 1668 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1669 dma_unmap_single(&pdev->dev, buffer_info->dma, 1670 adapter->rx_ps_bsize0, 1671 DMA_FROM_DEVICE); 1672 buffer_info->dma = 0; 1673 } 1674 1675 if (buffer_info->page) { 1676 put_page(buffer_info->page); 1677 buffer_info->page = NULL; 1678 } 1679 1680 if (buffer_info->skb) { 1681 dev_kfree_skb(buffer_info->skb); 1682 buffer_info->skb = NULL; 1683 } 1684 1685 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1686 ps_page = &buffer_info->ps_pages[j]; 1687 if (!ps_page->page) 1688 break; 1689 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1690 DMA_FROM_DEVICE); 1691 ps_page->dma = 0; 1692 put_page(ps_page->page); 1693 ps_page->page = NULL; 1694 } 1695 } 1696 1697 /* there also may be some cached data from a chained receive */ 1698 if (rx_ring->rx_skb_top) { 1699 dev_kfree_skb(rx_ring->rx_skb_top); 1700 rx_ring->rx_skb_top = NULL; 1701 } 1702 1703 /* Zero out the descriptor ring */ 1704 memset(rx_ring->desc, 0, rx_ring->size); 1705 1706 rx_ring->next_to_clean = 0; 1707 rx_ring->next_to_use = 0; 1708 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1709 1710 writel(0, rx_ring->head); 1711 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 1712 e1000e_update_rdt_wa(rx_ring, 0); 1713 else 1714 writel(0, rx_ring->tail); 1715 } 1716 1717 static void e1000e_downshift_workaround(struct work_struct *work) 1718 { 1719 struct e1000_adapter *adapter = container_of(work, 1720 struct e1000_adapter, 1721 downshift_task); 1722 1723 if (test_bit(__E1000_DOWN, &adapter->state)) 1724 return; 1725 1726 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1727 } 1728 1729 /** 1730 * e1000_intr_msi - Interrupt Handler 1731 * @irq: interrupt number 1732 * @data: pointer to a network interface device structure 1733 **/ 1734 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1735 { 1736 struct net_device *netdev = data; 1737 struct e1000_adapter *adapter = netdev_priv(netdev); 1738 struct e1000_hw *hw = &adapter->hw; 1739 u32 icr = er32(ICR); 1740 1741 /* read ICR disables interrupts using IAM */ 1742 if (icr & E1000_ICR_LSC) { 1743 hw->mac.get_link_status = true; 1744 /* ICH8 workaround-- Call gig speed drop workaround on cable 1745 * disconnect (LSC) before accessing any PHY registers 1746 */ 1747 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1748 (!(er32(STATUS) & E1000_STATUS_LU))) 1749 schedule_work(&adapter->downshift_task); 1750 1751 /* 80003ES2LAN workaround-- For packet buffer work-around on 1752 * link down event; disable receives here in the ISR and reset 1753 * adapter in watchdog 1754 */ 1755 if (netif_carrier_ok(netdev) && 1756 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1757 /* disable receives */ 1758 u32 rctl = er32(RCTL); 1759 1760 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1761 adapter->flags |= FLAG_RESTART_NOW; 1762 } 1763 /* guard against interrupt when we're going down */ 1764 if (!test_bit(__E1000_DOWN, &adapter->state)) 1765 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1766 } 1767 1768 /* Reset on uncorrectable ECC error */ 1769 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) { 1770 u32 pbeccsts = er32(PBECCSTS); 1771 1772 adapter->corr_errors += 1773 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1774 adapter->uncorr_errors += 1775 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1776 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1777 1778 /* Do the reset outside of interrupt context */ 1779 schedule_work(&adapter->reset_task); 1780 1781 /* return immediately since reset is imminent */ 1782 return IRQ_HANDLED; 1783 } 1784 1785 if (napi_schedule_prep(&adapter->napi)) { 1786 adapter->total_tx_bytes = 0; 1787 adapter->total_tx_packets = 0; 1788 adapter->total_rx_bytes = 0; 1789 adapter->total_rx_packets = 0; 1790 __napi_schedule(&adapter->napi); 1791 } 1792 1793 return IRQ_HANDLED; 1794 } 1795 1796 /** 1797 * e1000_intr - Interrupt Handler 1798 * @irq: interrupt number 1799 * @data: pointer to a network interface device structure 1800 **/ 1801 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1802 { 1803 struct net_device *netdev = data; 1804 struct e1000_adapter *adapter = netdev_priv(netdev); 1805 struct e1000_hw *hw = &adapter->hw; 1806 u32 rctl, icr = er32(ICR); 1807 1808 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1809 return IRQ_NONE; /* Not our interrupt */ 1810 1811 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1812 * not set, then the adapter didn't send an interrupt 1813 */ 1814 if (!(icr & E1000_ICR_INT_ASSERTED)) 1815 return IRQ_NONE; 1816 1817 /* Interrupt Auto-Mask...upon reading ICR, 1818 * interrupts are masked. No need for the 1819 * IMC write 1820 */ 1821 1822 if (icr & E1000_ICR_LSC) { 1823 hw->mac.get_link_status = true; 1824 /* ICH8 workaround-- Call gig speed drop workaround on cable 1825 * disconnect (LSC) before accessing any PHY registers 1826 */ 1827 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1828 (!(er32(STATUS) & E1000_STATUS_LU))) 1829 schedule_work(&adapter->downshift_task); 1830 1831 /* 80003ES2LAN workaround-- 1832 * For packet buffer work-around on link down event; 1833 * disable receives here in the ISR and 1834 * reset adapter in watchdog 1835 */ 1836 if (netif_carrier_ok(netdev) && 1837 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1838 /* disable receives */ 1839 rctl = er32(RCTL); 1840 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1841 adapter->flags |= FLAG_RESTART_NOW; 1842 } 1843 /* guard against interrupt when we're going down */ 1844 if (!test_bit(__E1000_DOWN, &adapter->state)) 1845 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1846 } 1847 1848 /* Reset on uncorrectable ECC error */ 1849 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) { 1850 u32 pbeccsts = er32(PBECCSTS); 1851 1852 adapter->corr_errors += 1853 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1854 adapter->uncorr_errors += 1855 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1856 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1857 1858 /* Do the reset outside of interrupt context */ 1859 schedule_work(&adapter->reset_task); 1860 1861 /* return immediately since reset is imminent */ 1862 return IRQ_HANDLED; 1863 } 1864 1865 if (napi_schedule_prep(&adapter->napi)) { 1866 adapter->total_tx_bytes = 0; 1867 adapter->total_tx_packets = 0; 1868 adapter->total_rx_bytes = 0; 1869 adapter->total_rx_packets = 0; 1870 __napi_schedule(&adapter->napi); 1871 } 1872 1873 return IRQ_HANDLED; 1874 } 1875 1876 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1877 { 1878 struct net_device *netdev = data; 1879 struct e1000_adapter *adapter = netdev_priv(netdev); 1880 struct e1000_hw *hw = &adapter->hw; 1881 u32 icr = er32(ICR); 1882 1883 if (!(icr & E1000_ICR_INT_ASSERTED)) { 1884 if (!test_bit(__E1000_DOWN, &adapter->state)) 1885 ew32(IMS, E1000_IMS_OTHER); 1886 return IRQ_NONE; 1887 } 1888 1889 if (icr & adapter->eiac_mask) 1890 ew32(ICS, (icr & adapter->eiac_mask)); 1891 1892 if (icr & E1000_ICR_OTHER) { 1893 if (!(icr & E1000_ICR_LSC)) 1894 goto no_link_interrupt; 1895 hw->mac.get_link_status = true; 1896 /* guard against interrupt when we're going down */ 1897 if (!test_bit(__E1000_DOWN, &adapter->state)) 1898 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1899 } 1900 1901 no_link_interrupt: 1902 if (!test_bit(__E1000_DOWN, &adapter->state)) 1903 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER); 1904 1905 return IRQ_HANDLED; 1906 } 1907 1908 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1909 { 1910 struct net_device *netdev = data; 1911 struct e1000_adapter *adapter = netdev_priv(netdev); 1912 struct e1000_hw *hw = &adapter->hw; 1913 struct e1000_ring *tx_ring = adapter->tx_ring; 1914 1915 adapter->total_tx_bytes = 0; 1916 adapter->total_tx_packets = 0; 1917 1918 if (!e1000_clean_tx_irq(tx_ring)) 1919 /* Ring was not completely cleaned, so fire another interrupt */ 1920 ew32(ICS, tx_ring->ims_val); 1921 1922 return IRQ_HANDLED; 1923 } 1924 1925 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1926 { 1927 struct net_device *netdev = data; 1928 struct e1000_adapter *adapter = netdev_priv(netdev); 1929 struct e1000_ring *rx_ring = adapter->rx_ring; 1930 1931 /* Write the ITR value calculated at the end of the 1932 * previous interrupt. 1933 */ 1934 if (rx_ring->set_itr) { 1935 writel(1000000000 / (rx_ring->itr_val * 256), 1936 rx_ring->itr_register); 1937 rx_ring->set_itr = 0; 1938 } 1939 1940 if (napi_schedule_prep(&adapter->napi)) { 1941 adapter->total_rx_bytes = 0; 1942 adapter->total_rx_packets = 0; 1943 __napi_schedule(&adapter->napi); 1944 } 1945 return IRQ_HANDLED; 1946 } 1947 1948 /** 1949 * e1000_configure_msix - Configure MSI-X hardware 1950 * 1951 * e1000_configure_msix sets up the hardware to properly 1952 * generate MSI-X interrupts. 1953 **/ 1954 static void e1000_configure_msix(struct e1000_adapter *adapter) 1955 { 1956 struct e1000_hw *hw = &adapter->hw; 1957 struct e1000_ring *rx_ring = adapter->rx_ring; 1958 struct e1000_ring *tx_ring = adapter->tx_ring; 1959 int vector = 0; 1960 u32 ctrl_ext, ivar = 0; 1961 1962 adapter->eiac_mask = 0; 1963 1964 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1965 if (hw->mac.type == e1000_82574) { 1966 u32 rfctl = er32(RFCTL); 1967 1968 rfctl |= E1000_RFCTL_ACK_DIS; 1969 ew32(RFCTL, rfctl); 1970 } 1971 1972 /* Configure Rx vector */ 1973 rx_ring->ims_val = E1000_IMS_RXQ0; 1974 adapter->eiac_mask |= rx_ring->ims_val; 1975 if (rx_ring->itr_val) 1976 writel(1000000000 / (rx_ring->itr_val * 256), 1977 rx_ring->itr_register); 1978 else 1979 writel(1, rx_ring->itr_register); 1980 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 1981 1982 /* Configure Tx vector */ 1983 tx_ring->ims_val = E1000_IMS_TXQ0; 1984 vector++; 1985 if (tx_ring->itr_val) 1986 writel(1000000000 / (tx_ring->itr_val * 256), 1987 tx_ring->itr_register); 1988 else 1989 writel(1, tx_ring->itr_register); 1990 adapter->eiac_mask |= tx_ring->ims_val; 1991 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 1992 1993 /* set vector for Other Causes, e.g. link changes */ 1994 vector++; 1995 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 1996 if (rx_ring->itr_val) 1997 writel(1000000000 / (rx_ring->itr_val * 256), 1998 hw->hw_addr + E1000_EITR_82574(vector)); 1999 else 2000 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2001 2002 /* Cause Tx interrupts on every write back */ 2003 ivar |= (1 << 31); 2004 2005 ew32(IVAR, ivar); 2006 2007 /* enable MSI-X PBA support */ 2008 ctrl_ext = er32(CTRL_EXT); 2009 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR; 2010 2011 /* Auto-Mask Other interrupts upon ICR read */ 2012 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER); 2013 ctrl_ext |= E1000_CTRL_EXT_EIAME; 2014 ew32(CTRL_EXT, ctrl_ext); 2015 e1e_flush(); 2016 } 2017 2018 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2019 { 2020 if (adapter->msix_entries) { 2021 pci_disable_msix(adapter->pdev); 2022 kfree(adapter->msix_entries); 2023 adapter->msix_entries = NULL; 2024 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2025 pci_disable_msi(adapter->pdev); 2026 adapter->flags &= ~FLAG_MSI_ENABLED; 2027 } 2028 } 2029 2030 /** 2031 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2032 * 2033 * Attempt to configure interrupts using the best available 2034 * capabilities of the hardware and kernel. 2035 **/ 2036 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2037 { 2038 int err; 2039 int i; 2040 2041 switch (adapter->int_mode) { 2042 case E1000E_INT_MODE_MSIX: 2043 if (adapter->flags & FLAG_HAS_MSIX) { 2044 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2045 adapter->msix_entries = kcalloc(adapter->num_vectors, 2046 sizeof(struct 2047 msix_entry), 2048 GFP_KERNEL); 2049 if (adapter->msix_entries) { 2050 struct e1000_adapter *a = adapter; 2051 2052 for (i = 0; i < adapter->num_vectors; i++) 2053 adapter->msix_entries[i].entry = i; 2054 2055 err = pci_enable_msix_range(a->pdev, 2056 a->msix_entries, 2057 a->num_vectors, 2058 a->num_vectors); 2059 if (err > 0) 2060 return; 2061 } 2062 /* MSI-X failed, so fall through and try MSI */ 2063 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2064 e1000e_reset_interrupt_capability(adapter); 2065 } 2066 adapter->int_mode = E1000E_INT_MODE_MSI; 2067 /* Fall through */ 2068 case E1000E_INT_MODE_MSI: 2069 if (!pci_enable_msi(adapter->pdev)) { 2070 adapter->flags |= FLAG_MSI_ENABLED; 2071 } else { 2072 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2073 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2074 } 2075 /* Fall through */ 2076 case E1000E_INT_MODE_LEGACY: 2077 /* Don't do anything; this is the system default */ 2078 break; 2079 } 2080 2081 /* store the number of vectors being used */ 2082 adapter->num_vectors = 1; 2083 } 2084 2085 /** 2086 * e1000_request_msix - Initialize MSI-X interrupts 2087 * 2088 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2089 * kernel. 2090 **/ 2091 static int e1000_request_msix(struct e1000_adapter *adapter) 2092 { 2093 struct net_device *netdev = adapter->netdev; 2094 int err = 0, vector = 0; 2095 2096 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2097 snprintf(adapter->rx_ring->name, 2098 sizeof(adapter->rx_ring->name) - 1, 2099 "%s-rx-0", netdev->name); 2100 else 2101 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2102 err = request_irq(adapter->msix_entries[vector].vector, 2103 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2104 netdev); 2105 if (err) 2106 return err; 2107 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2108 E1000_EITR_82574(vector); 2109 adapter->rx_ring->itr_val = adapter->itr; 2110 vector++; 2111 2112 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2113 snprintf(adapter->tx_ring->name, 2114 sizeof(adapter->tx_ring->name) - 1, 2115 "%s-tx-0", netdev->name); 2116 else 2117 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2118 err = request_irq(adapter->msix_entries[vector].vector, 2119 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2120 netdev); 2121 if (err) 2122 return err; 2123 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2124 E1000_EITR_82574(vector); 2125 adapter->tx_ring->itr_val = adapter->itr; 2126 vector++; 2127 2128 err = request_irq(adapter->msix_entries[vector].vector, 2129 e1000_msix_other, 0, netdev->name, netdev); 2130 if (err) 2131 return err; 2132 2133 e1000_configure_msix(adapter); 2134 2135 return 0; 2136 } 2137 2138 /** 2139 * e1000_request_irq - initialize interrupts 2140 * 2141 * Attempts to configure interrupts using the best available 2142 * capabilities of the hardware and kernel. 2143 **/ 2144 static int e1000_request_irq(struct e1000_adapter *adapter) 2145 { 2146 struct net_device *netdev = adapter->netdev; 2147 int err; 2148 2149 if (adapter->msix_entries) { 2150 err = e1000_request_msix(adapter); 2151 if (!err) 2152 return err; 2153 /* fall back to MSI */ 2154 e1000e_reset_interrupt_capability(adapter); 2155 adapter->int_mode = E1000E_INT_MODE_MSI; 2156 e1000e_set_interrupt_capability(adapter); 2157 } 2158 if (adapter->flags & FLAG_MSI_ENABLED) { 2159 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2160 netdev->name, netdev); 2161 if (!err) 2162 return err; 2163 2164 /* fall back to legacy interrupt */ 2165 e1000e_reset_interrupt_capability(adapter); 2166 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2167 } 2168 2169 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2170 netdev->name, netdev); 2171 if (err) 2172 e_err("Unable to allocate interrupt, Error: %d\n", err); 2173 2174 return err; 2175 } 2176 2177 static void e1000_free_irq(struct e1000_adapter *adapter) 2178 { 2179 struct net_device *netdev = adapter->netdev; 2180 2181 if (adapter->msix_entries) { 2182 int vector = 0; 2183 2184 free_irq(adapter->msix_entries[vector].vector, netdev); 2185 vector++; 2186 2187 free_irq(adapter->msix_entries[vector].vector, netdev); 2188 vector++; 2189 2190 /* Other Causes interrupt vector */ 2191 free_irq(adapter->msix_entries[vector].vector, netdev); 2192 return; 2193 } 2194 2195 free_irq(adapter->pdev->irq, netdev); 2196 } 2197 2198 /** 2199 * e1000_irq_disable - Mask off interrupt generation on the NIC 2200 **/ 2201 static void e1000_irq_disable(struct e1000_adapter *adapter) 2202 { 2203 struct e1000_hw *hw = &adapter->hw; 2204 2205 ew32(IMC, ~0); 2206 if (adapter->msix_entries) 2207 ew32(EIAC_82574, 0); 2208 e1e_flush(); 2209 2210 if (adapter->msix_entries) { 2211 int i; 2212 2213 for (i = 0; i < adapter->num_vectors; i++) 2214 synchronize_irq(adapter->msix_entries[i].vector); 2215 } else { 2216 synchronize_irq(adapter->pdev->irq); 2217 } 2218 } 2219 2220 /** 2221 * e1000_irq_enable - Enable default interrupt generation settings 2222 **/ 2223 static void e1000_irq_enable(struct e1000_adapter *adapter) 2224 { 2225 struct e1000_hw *hw = &adapter->hw; 2226 2227 if (adapter->msix_entries) { 2228 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2229 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC); 2230 } else if (hw->mac.type == e1000_pch_lpt) { 2231 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2232 } else { 2233 ew32(IMS, IMS_ENABLE_MASK); 2234 } 2235 e1e_flush(); 2236 } 2237 2238 /** 2239 * e1000e_get_hw_control - get control of the h/w from f/w 2240 * @adapter: address of board private structure 2241 * 2242 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2243 * For ASF and Pass Through versions of f/w this means that 2244 * the driver is loaded. For AMT version (only with 82573) 2245 * of the f/w this means that the network i/f is open. 2246 **/ 2247 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2248 { 2249 struct e1000_hw *hw = &adapter->hw; 2250 u32 ctrl_ext; 2251 u32 swsm; 2252 2253 /* Let firmware know the driver has taken over */ 2254 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2255 swsm = er32(SWSM); 2256 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2257 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2258 ctrl_ext = er32(CTRL_EXT); 2259 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2260 } 2261 } 2262 2263 /** 2264 * e1000e_release_hw_control - release control of the h/w to f/w 2265 * @adapter: address of board private structure 2266 * 2267 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2268 * For ASF and Pass Through versions of f/w this means that the 2269 * driver is no longer loaded. For AMT version (only with 82573) i 2270 * of the f/w this means that the network i/f is closed. 2271 * 2272 **/ 2273 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2274 { 2275 struct e1000_hw *hw = &adapter->hw; 2276 u32 ctrl_ext; 2277 u32 swsm; 2278 2279 /* Let firmware taken over control of h/w */ 2280 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2281 swsm = er32(SWSM); 2282 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2283 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2284 ctrl_ext = er32(CTRL_EXT); 2285 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2286 } 2287 } 2288 2289 /** 2290 * e1000_alloc_ring_dma - allocate memory for a ring structure 2291 **/ 2292 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2293 struct e1000_ring *ring) 2294 { 2295 struct pci_dev *pdev = adapter->pdev; 2296 2297 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2298 GFP_KERNEL); 2299 if (!ring->desc) 2300 return -ENOMEM; 2301 2302 return 0; 2303 } 2304 2305 /** 2306 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2307 * @tx_ring: Tx descriptor ring 2308 * 2309 * Return 0 on success, negative on failure 2310 **/ 2311 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2312 { 2313 struct e1000_adapter *adapter = tx_ring->adapter; 2314 int err = -ENOMEM, size; 2315 2316 size = sizeof(struct e1000_buffer) * tx_ring->count; 2317 tx_ring->buffer_info = vzalloc(size); 2318 if (!tx_ring->buffer_info) 2319 goto err; 2320 2321 /* round up to nearest 4K */ 2322 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2323 tx_ring->size = ALIGN(tx_ring->size, 4096); 2324 2325 err = e1000_alloc_ring_dma(adapter, tx_ring); 2326 if (err) 2327 goto err; 2328 2329 tx_ring->next_to_use = 0; 2330 tx_ring->next_to_clean = 0; 2331 2332 return 0; 2333 err: 2334 vfree(tx_ring->buffer_info); 2335 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2336 return err; 2337 } 2338 2339 /** 2340 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2341 * @rx_ring: Rx descriptor ring 2342 * 2343 * Returns 0 on success, negative on failure 2344 **/ 2345 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2346 { 2347 struct e1000_adapter *adapter = rx_ring->adapter; 2348 struct e1000_buffer *buffer_info; 2349 int i, size, desc_len, err = -ENOMEM; 2350 2351 size = sizeof(struct e1000_buffer) * rx_ring->count; 2352 rx_ring->buffer_info = vzalloc(size); 2353 if (!rx_ring->buffer_info) 2354 goto err; 2355 2356 for (i = 0; i < rx_ring->count; i++) { 2357 buffer_info = &rx_ring->buffer_info[i]; 2358 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2359 sizeof(struct e1000_ps_page), 2360 GFP_KERNEL); 2361 if (!buffer_info->ps_pages) 2362 goto err_pages; 2363 } 2364 2365 desc_len = sizeof(union e1000_rx_desc_packet_split); 2366 2367 /* Round up to nearest 4K */ 2368 rx_ring->size = rx_ring->count * desc_len; 2369 rx_ring->size = ALIGN(rx_ring->size, 4096); 2370 2371 err = e1000_alloc_ring_dma(adapter, rx_ring); 2372 if (err) 2373 goto err_pages; 2374 2375 rx_ring->next_to_clean = 0; 2376 rx_ring->next_to_use = 0; 2377 rx_ring->rx_skb_top = NULL; 2378 2379 return 0; 2380 2381 err_pages: 2382 for (i = 0; i < rx_ring->count; i++) { 2383 buffer_info = &rx_ring->buffer_info[i]; 2384 kfree(buffer_info->ps_pages); 2385 } 2386 err: 2387 vfree(rx_ring->buffer_info); 2388 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2389 return err; 2390 } 2391 2392 /** 2393 * e1000_clean_tx_ring - Free Tx Buffers 2394 * @tx_ring: Tx descriptor ring 2395 **/ 2396 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2397 { 2398 struct e1000_adapter *adapter = tx_ring->adapter; 2399 struct e1000_buffer *buffer_info; 2400 unsigned long size; 2401 unsigned int i; 2402 2403 for (i = 0; i < tx_ring->count; i++) { 2404 buffer_info = &tx_ring->buffer_info[i]; 2405 e1000_put_txbuf(tx_ring, buffer_info); 2406 } 2407 2408 netdev_reset_queue(adapter->netdev); 2409 size = sizeof(struct e1000_buffer) * tx_ring->count; 2410 memset(tx_ring->buffer_info, 0, size); 2411 2412 memset(tx_ring->desc, 0, tx_ring->size); 2413 2414 tx_ring->next_to_use = 0; 2415 tx_ring->next_to_clean = 0; 2416 2417 writel(0, tx_ring->head); 2418 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2419 e1000e_update_tdt_wa(tx_ring, 0); 2420 else 2421 writel(0, tx_ring->tail); 2422 } 2423 2424 /** 2425 * e1000e_free_tx_resources - Free Tx Resources per Queue 2426 * @tx_ring: Tx descriptor ring 2427 * 2428 * Free all transmit software resources 2429 **/ 2430 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2431 { 2432 struct e1000_adapter *adapter = tx_ring->adapter; 2433 struct pci_dev *pdev = adapter->pdev; 2434 2435 e1000_clean_tx_ring(tx_ring); 2436 2437 vfree(tx_ring->buffer_info); 2438 tx_ring->buffer_info = NULL; 2439 2440 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2441 tx_ring->dma); 2442 tx_ring->desc = NULL; 2443 } 2444 2445 /** 2446 * e1000e_free_rx_resources - Free Rx Resources 2447 * @rx_ring: Rx descriptor ring 2448 * 2449 * Free all receive software resources 2450 **/ 2451 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2452 { 2453 struct e1000_adapter *adapter = rx_ring->adapter; 2454 struct pci_dev *pdev = adapter->pdev; 2455 int i; 2456 2457 e1000_clean_rx_ring(rx_ring); 2458 2459 for (i = 0; i < rx_ring->count; i++) 2460 kfree(rx_ring->buffer_info[i].ps_pages); 2461 2462 vfree(rx_ring->buffer_info); 2463 rx_ring->buffer_info = NULL; 2464 2465 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2466 rx_ring->dma); 2467 rx_ring->desc = NULL; 2468 } 2469 2470 /** 2471 * e1000_update_itr - update the dynamic ITR value based on statistics 2472 * @adapter: pointer to adapter 2473 * @itr_setting: current adapter->itr 2474 * @packets: the number of packets during this measurement interval 2475 * @bytes: the number of bytes during this measurement interval 2476 * 2477 * Stores a new ITR value based on packets and byte 2478 * counts during the last interrupt. The advantage of per interrupt 2479 * computation is faster updates and more accurate ITR for the current 2480 * traffic pattern. Constants in this function were computed 2481 * based on theoretical maximum wire speed and thresholds were set based 2482 * on testing data as well as attempting to minimize response time 2483 * while increasing bulk throughput. This functionality is controlled 2484 * by the InterruptThrottleRate module parameter. 2485 **/ 2486 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2487 { 2488 unsigned int retval = itr_setting; 2489 2490 if (packets == 0) 2491 return itr_setting; 2492 2493 switch (itr_setting) { 2494 case lowest_latency: 2495 /* handle TSO and jumbo frames */ 2496 if (bytes / packets > 8000) 2497 retval = bulk_latency; 2498 else if ((packets < 5) && (bytes > 512)) 2499 retval = low_latency; 2500 break; 2501 case low_latency: /* 50 usec aka 20000 ints/s */ 2502 if (bytes > 10000) { 2503 /* this if handles the TSO accounting */ 2504 if (bytes / packets > 8000) 2505 retval = bulk_latency; 2506 else if ((packets < 10) || ((bytes / packets) > 1200)) 2507 retval = bulk_latency; 2508 else if ((packets > 35)) 2509 retval = lowest_latency; 2510 } else if (bytes / packets > 2000) { 2511 retval = bulk_latency; 2512 } else if (packets <= 2 && bytes < 512) { 2513 retval = lowest_latency; 2514 } 2515 break; 2516 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2517 if (bytes > 25000) { 2518 if (packets > 35) 2519 retval = low_latency; 2520 } else if (bytes < 6000) { 2521 retval = low_latency; 2522 } 2523 break; 2524 } 2525 2526 return retval; 2527 } 2528 2529 static void e1000_set_itr(struct e1000_adapter *adapter) 2530 { 2531 u16 current_itr; 2532 u32 new_itr = adapter->itr; 2533 2534 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2535 if (adapter->link_speed != SPEED_1000) { 2536 current_itr = 0; 2537 new_itr = 4000; 2538 goto set_itr_now; 2539 } 2540 2541 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2542 new_itr = 0; 2543 goto set_itr_now; 2544 } 2545 2546 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2547 adapter->total_tx_packets, 2548 adapter->total_tx_bytes); 2549 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2550 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2551 adapter->tx_itr = low_latency; 2552 2553 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2554 adapter->total_rx_packets, 2555 adapter->total_rx_bytes); 2556 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2557 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2558 adapter->rx_itr = low_latency; 2559 2560 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2561 2562 /* counts and packets in update_itr are dependent on these numbers */ 2563 switch (current_itr) { 2564 case lowest_latency: 2565 new_itr = 70000; 2566 break; 2567 case low_latency: 2568 new_itr = 20000; /* aka hwitr = ~200 */ 2569 break; 2570 case bulk_latency: 2571 new_itr = 4000; 2572 break; 2573 default: 2574 break; 2575 } 2576 2577 set_itr_now: 2578 if (new_itr != adapter->itr) { 2579 /* this attempts to bias the interrupt rate towards Bulk 2580 * by adding intermediate steps when interrupt rate is 2581 * increasing 2582 */ 2583 new_itr = new_itr > adapter->itr ? 2584 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2585 adapter->itr = new_itr; 2586 adapter->rx_ring->itr_val = new_itr; 2587 if (adapter->msix_entries) 2588 adapter->rx_ring->set_itr = 1; 2589 else 2590 e1000e_write_itr(adapter, new_itr); 2591 } 2592 } 2593 2594 /** 2595 * e1000e_write_itr - write the ITR value to the appropriate registers 2596 * @adapter: address of board private structure 2597 * @itr: new ITR value to program 2598 * 2599 * e1000e_write_itr determines if the adapter is in MSI-X mode 2600 * and, if so, writes the EITR registers with the ITR value. 2601 * Otherwise, it writes the ITR value into the ITR register. 2602 **/ 2603 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2604 { 2605 struct e1000_hw *hw = &adapter->hw; 2606 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2607 2608 if (adapter->msix_entries) { 2609 int vector; 2610 2611 for (vector = 0; vector < adapter->num_vectors; vector++) 2612 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2613 } else { 2614 ew32(ITR, new_itr); 2615 } 2616 } 2617 2618 /** 2619 * e1000_alloc_queues - Allocate memory for all rings 2620 * @adapter: board private structure to initialize 2621 **/ 2622 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2623 { 2624 int size = sizeof(struct e1000_ring); 2625 2626 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2627 if (!adapter->tx_ring) 2628 goto err; 2629 adapter->tx_ring->count = adapter->tx_ring_count; 2630 adapter->tx_ring->adapter = adapter; 2631 2632 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2633 if (!adapter->rx_ring) 2634 goto err; 2635 adapter->rx_ring->count = adapter->rx_ring_count; 2636 adapter->rx_ring->adapter = adapter; 2637 2638 return 0; 2639 err: 2640 e_err("Unable to allocate memory for queues\n"); 2641 kfree(adapter->rx_ring); 2642 kfree(adapter->tx_ring); 2643 return -ENOMEM; 2644 } 2645 2646 /** 2647 * e1000e_poll - NAPI Rx polling callback 2648 * @napi: struct associated with this polling callback 2649 * @weight: number of packets driver is allowed to process this poll 2650 **/ 2651 static int e1000e_poll(struct napi_struct *napi, int weight) 2652 { 2653 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2654 napi); 2655 struct e1000_hw *hw = &adapter->hw; 2656 struct net_device *poll_dev = adapter->netdev; 2657 int tx_cleaned = 1, work_done = 0; 2658 2659 adapter = netdev_priv(poll_dev); 2660 2661 if (!adapter->msix_entries || 2662 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2663 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2664 2665 adapter->clean_rx(adapter->rx_ring, &work_done, weight); 2666 2667 if (!tx_cleaned) 2668 work_done = weight; 2669 2670 /* If weight not fully consumed, exit the polling mode */ 2671 if (work_done < weight) { 2672 if (adapter->itr_setting & 3) 2673 e1000_set_itr(adapter); 2674 napi_complete(napi); 2675 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2676 if (adapter->msix_entries) 2677 ew32(IMS, adapter->rx_ring->ims_val); 2678 else 2679 e1000_irq_enable(adapter); 2680 } 2681 } 2682 2683 return work_done; 2684 } 2685 2686 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2687 __always_unused __be16 proto, u16 vid) 2688 { 2689 struct e1000_adapter *adapter = netdev_priv(netdev); 2690 struct e1000_hw *hw = &adapter->hw; 2691 u32 vfta, index; 2692 2693 /* don't update vlan cookie if already programmed */ 2694 if ((adapter->hw.mng_cookie.status & 2695 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2696 (vid == adapter->mng_vlan_id)) 2697 return 0; 2698 2699 /* add VID to filter table */ 2700 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2701 index = (vid >> 5) & 0x7F; 2702 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2703 vfta |= (1 << (vid & 0x1F)); 2704 hw->mac.ops.write_vfta(hw, index, vfta); 2705 } 2706 2707 set_bit(vid, adapter->active_vlans); 2708 2709 return 0; 2710 } 2711 2712 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2713 __always_unused __be16 proto, u16 vid) 2714 { 2715 struct e1000_adapter *adapter = netdev_priv(netdev); 2716 struct e1000_hw *hw = &adapter->hw; 2717 u32 vfta, index; 2718 2719 if ((adapter->hw.mng_cookie.status & 2720 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2721 (vid == adapter->mng_vlan_id)) { 2722 /* release control to f/w */ 2723 e1000e_release_hw_control(adapter); 2724 return 0; 2725 } 2726 2727 /* remove VID from filter table */ 2728 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2729 index = (vid >> 5) & 0x7F; 2730 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2731 vfta &= ~(1 << (vid & 0x1F)); 2732 hw->mac.ops.write_vfta(hw, index, vfta); 2733 } 2734 2735 clear_bit(vid, adapter->active_vlans); 2736 2737 return 0; 2738 } 2739 2740 /** 2741 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2742 * @adapter: board private structure to initialize 2743 **/ 2744 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2745 { 2746 struct net_device *netdev = adapter->netdev; 2747 struct e1000_hw *hw = &adapter->hw; 2748 u32 rctl; 2749 2750 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2751 /* disable VLAN receive filtering */ 2752 rctl = er32(RCTL); 2753 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2754 ew32(RCTL, rctl); 2755 2756 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2757 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2758 adapter->mng_vlan_id); 2759 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2760 } 2761 } 2762 } 2763 2764 /** 2765 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2766 * @adapter: board private structure to initialize 2767 **/ 2768 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2769 { 2770 struct e1000_hw *hw = &adapter->hw; 2771 u32 rctl; 2772 2773 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2774 /* enable VLAN receive filtering */ 2775 rctl = er32(RCTL); 2776 rctl |= E1000_RCTL_VFE; 2777 rctl &= ~E1000_RCTL_CFIEN; 2778 ew32(RCTL, rctl); 2779 } 2780 } 2781 2782 /** 2783 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping 2784 * @adapter: board private structure to initialize 2785 **/ 2786 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2787 { 2788 struct e1000_hw *hw = &adapter->hw; 2789 u32 ctrl; 2790 2791 /* disable VLAN tag insert/strip */ 2792 ctrl = er32(CTRL); 2793 ctrl &= ~E1000_CTRL_VME; 2794 ew32(CTRL, ctrl); 2795 } 2796 2797 /** 2798 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2799 * @adapter: board private structure to initialize 2800 **/ 2801 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2802 { 2803 struct e1000_hw *hw = &adapter->hw; 2804 u32 ctrl; 2805 2806 /* enable VLAN tag insert/strip */ 2807 ctrl = er32(CTRL); 2808 ctrl |= E1000_CTRL_VME; 2809 ew32(CTRL, ctrl); 2810 } 2811 2812 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2813 { 2814 struct net_device *netdev = adapter->netdev; 2815 u16 vid = adapter->hw.mng_cookie.vlan_id; 2816 u16 old_vid = adapter->mng_vlan_id; 2817 2818 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2819 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2820 adapter->mng_vlan_id = vid; 2821 } 2822 2823 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2824 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2825 } 2826 2827 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2828 { 2829 u16 vid; 2830 2831 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2832 2833 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2834 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2835 } 2836 2837 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2838 { 2839 struct e1000_hw *hw = &adapter->hw; 2840 u32 manc, manc2h, mdef, i, j; 2841 2842 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2843 return; 2844 2845 manc = er32(MANC); 2846 2847 /* enable receiving management packets to the host. this will probably 2848 * generate destination unreachable messages from the host OS, but 2849 * the packets will be handled on SMBUS 2850 */ 2851 manc |= E1000_MANC_EN_MNG2HOST; 2852 manc2h = er32(MANC2H); 2853 2854 switch (hw->mac.type) { 2855 default: 2856 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2857 break; 2858 case e1000_82574: 2859 case e1000_82583: 2860 /* Check if IPMI pass-through decision filter already exists; 2861 * if so, enable it. 2862 */ 2863 for (i = 0, j = 0; i < 8; i++) { 2864 mdef = er32(MDEF(i)); 2865 2866 /* Ignore filters with anything other than IPMI ports */ 2867 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2868 continue; 2869 2870 /* Enable this decision filter in MANC2H */ 2871 if (mdef) 2872 manc2h |= (1 << i); 2873 2874 j |= mdef; 2875 } 2876 2877 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2878 break; 2879 2880 /* Create new decision filter in an empty filter */ 2881 for (i = 0, j = 0; i < 8; i++) 2882 if (er32(MDEF(i)) == 0) { 2883 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2884 E1000_MDEF_PORT_664)); 2885 manc2h |= (1 << 1); 2886 j++; 2887 break; 2888 } 2889 2890 if (!j) 2891 e_warn("Unable to create IPMI pass-through filter\n"); 2892 break; 2893 } 2894 2895 ew32(MANC2H, manc2h); 2896 ew32(MANC, manc); 2897 } 2898 2899 /** 2900 * e1000_configure_tx - Configure Transmit Unit after Reset 2901 * @adapter: board private structure 2902 * 2903 * Configure the Tx unit of the MAC after a reset. 2904 **/ 2905 static void e1000_configure_tx(struct e1000_adapter *adapter) 2906 { 2907 struct e1000_hw *hw = &adapter->hw; 2908 struct e1000_ring *tx_ring = adapter->tx_ring; 2909 u64 tdba; 2910 u32 tdlen, tctl, tarc; 2911 2912 /* Setup the HW Tx Head and Tail descriptor pointers */ 2913 tdba = tx_ring->dma; 2914 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2915 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2916 ew32(TDBAH(0), (tdba >> 32)); 2917 ew32(TDLEN(0), tdlen); 2918 ew32(TDH(0), 0); 2919 ew32(TDT(0), 0); 2920 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2921 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2922 2923 /* Set the Tx Interrupt Delay register */ 2924 ew32(TIDV, adapter->tx_int_delay); 2925 /* Tx irq moderation */ 2926 ew32(TADV, adapter->tx_abs_int_delay); 2927 2928 if (adapter->flags2 & FLAG2_DMA_BURST) { 2929 u32 txdctl = er32(TXDCTL(0)); 2930 2931 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2932 E1000_TXDCTL_WTHRESH); 2933 /* set up some performance related parameters to encourage the 2934 * hardware to use the bus more efficiently in bursts, depends 2935 * on the tx_int_delay to be enabled, 2936 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2937 * hthresh = 1 ==> prefetch when one or more available 2938 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2939 * BEWARE: this seems to work but should be considered first if 2940 * there are Tx hangs or other Tx related bugs 2941 */ 2942 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2943 ew32(TXDCTL(0), txdctl); 2944 } 2945 /* erratum work around: set txdctl the same for both queues */ 2946 ew32(TXDCTL(1), er32(TXDCTL(0))); 2947 2948 /* Program the Transmit Control Register */ 2949 tctl = er32(TCTL); 2950 tctl &= ~E1000_TCTL_CT; 2951 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2952 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2953 2954 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2955 tarc = er32(TARC(0)); 2956 /* set the speed mode bit, we'll clear it if we're not at 2957 * gigabit link later 2958 */ 2959 #define SPEED_MODE_BIT (1 << 21) 2960 tarc |= SPEED_MODE_BIT; 2961 ew32(TARC(0), tarc); 2962 } 2963 2964 /* errata: program both queues to unweighted RR */ 2965 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2966 tarc = er32(TARC(0)); 2967 tarc |= 1; 2968 ew32(TARC(0), tarc); 2969 tarc = er32(TARC(1)); 2970 tarc |= 1; 2971 ew32(TARC(1), tarc); 2972 } 2973 2974 /* Setup Transmit Descriptor Settings for eop descriptor */ 2975 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 2976 2977 /* only set IDE if we are delaying interrupts using the timers */ 2978 if (adapter->tx_int_delay) 2979 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2980 2981 /* enable Report Status bit */ 2982 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2983 2984 ew32(TCTL, tctl); 2985 2986 hw->mac.ops.config_collision_dist(hw); 2987 } 2988 2989 /** 2990 * e1000_setup_rctl - configure the receive control registers 2991 * @adapter: Board private structure 2992 **/ 2993 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 2994 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 2995 static void e1000_setup_rctl(struct e1000_adapter *adapter) 2996 { 2997 struct e1000_hw *hw = &adapter->hw; 2998 u32 rctl, rfctl; 2999 u32 pages = 0; 3000 3001 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3002 * If jumbo frames not set, program related MAC/PHY registers 3003 * to h/w defaults 3004 */ 3005 if (hw->mac.type >= e1000_pch2lan) { 3006 s32 ret_val; 3007 3008 if (adapter->netdev->mtu > ETH_DATA_LEN) 3009 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3010 else 3011 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3012 3013 if (ret_val) 3014 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3015 } 3016 3017 /* Program MC offset vector base */ 3018 rctl = er32(RCTL); 3019 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3020 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3021 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3022 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3023 3024 /* Do not Store bad packets */ 3025 rctl &= ~E1000_RCTL_SBP; 3026 3027 /* Enable Long Packet receive */ 3028 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3029 rctl &= ~E1000_RCTL_LPE; 3030 else 3031 rctl |= E1000_RCTL_LPE; 3032 3033 /* Some systems expect that the CRC is included in SMBUS traffic. The 3034 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3035 * host memory when this is enabled 3036 */ 3037 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3038 rctl |= E1000_RCTL_SECRC; 3039 3040 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3041 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3042 u16 phy_data; 3043 3044 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3045 phy_data &= 0xfff8; 3046 phy_data |= (1 << 2); 3047 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3048 3049 e1e_rphy(hw, 22, &phy_data); 3050 phy_data &= 0x0fff; 3051 phy_data |= (1 << 14); 3052 e1e_wphy(hw, 0x10, 0x2823); 3053 e1e_wphy(hw, 0x11, 0x0003); 3054 e1e_wphy(hw, 22, phy_data); 3055 } 3056 3057 /* Setup buffer sizes */ 3058 rctl &= ~E1000_RCTL_SZ_4096; 3059 rctl |= E1000_RCTL_BSEX; 3060 switch (adapter->rx_buffer_len) { 3061 case 2048: 3062 default: 3063 rctl |= E1000_RCTL_SZ_2048; 3064 rctl &= ~E1000_RCTL_BSEX; 3065 break; 3066 case 4096: 3067 rctl |= E1000_RCTL_SZ_4096; 3068 break; 3069 case 8192: 3070 rctl |= E1000_RCTL_SZ_8192; 3071 break; 3072 case 16384: 3073 rctl |= E1000_RCTL_SZ_16384; 3074 break; 3075 } 3076 3077 /* Enable Extended Status in all Receive Descriptors */ 3078 rfctl = er32(RFCTL); 3079 rfctl |= E1000_RFCTL_EXTEN; 3080 ew32(RFCTL, rfctl); 3081 3082 /* 82571 and greater support packet-split where the protocol 3083 * header is placed in skb->data and the packet data is 3084 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3085 * In the case of a non-split, skb->data is linearly filled, 3086 * followed by the page buffers. Therefore, skb->data is 3087 * sized to hold the largest protocol header. 3088 * 3089 * allocations using alloc_page take too long for regular MTU 3090 * so only enable packet split for jumbo frames 3091 * 3092 * Using pages when the page size is greater than 16k wastes 3093 * a lot of memory, since we allocate 3 pages at all times 3094 * per packet. 3095 */ 3096 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3097 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3098 adapter->rx_ps_pages = pages; 3099 else 3100 adapter->rx_ps_pages = 0; 3101 3102 if (adapter->rx_ps_pages) { 3103 u32 psrctl = 0; 3104 3105 /* Enable Packet split descriptors */ 3106 rctl |= E1000_RCTL_DTYP_PS; 3107 3108 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3109 3110 switch (adapter->rx_ps_pages) { 3111 case 3: 3112 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3113 /* fall-through */ 3114 case 2: 3115 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3116 /* fall-through */ 3117 case 1: 3118 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3119 break; 3120 } 3121 3122 ew32(PSRCTL, psrctl); 3123 } 3124 3125 /* This is useful for sniffing bad packets. */ 3126 if (adapter->netdev->features & NETIF_F_RXALL) { 3127 /* UPE and MPE will be handled by normal PROMISC logic 3128 * in e1000e_set_rx_mode 3129 */ 3130 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3131 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3132 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3133 3134 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3135 E1000_RCTL_DPF | /* Allow filtered pause */ 3136 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3137 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3138 * and that breaks VLANs. 3139 */ 3140 } 3141 3142 ew32(RCTL, rctl); 3143 /* just started the receive unit, no need to restart */ 3144 adapter->flags &= ~FLAG_RESTART_NOW; 3145 } 3146 3147 /** 3148 * e1000_configure_rx - Configure Receive Unit after Reset 3149 * @adapter: board private structure 3150 * 3151 * Configure the Rx unit of the MAC after a reset. 3152 **/ 3153 static void e1000_configure_rx(struct e1000_adapter *adapter) 3154 { 3155 struct e1000_hw *hw = &adapter->hw; 3156 struct e1000_ring *rx_ring = adapter->rx_ring; 3157 u64 rdba; 3158 u32 rdlen, rctl, rxcsum, ctrl_ext; 3159 3160 if (adapter->rx_ps_pages) { 3161 /* this is a 32 byte descriptor */ 3162 rdlen = rx_ring->count * 3163 sizeof(union e1000_rx_desc_packet_split); 3164 adapter->clean_rx = e1000_clean_rx_irq_ps; 3165 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3166 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3167 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3168 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3169 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3170 } else { 3171 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3172 adapter->clean_rx = e1000_clean_rx_irq; 3173 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3174 } 3175 3176 /* disable receives while setting up the descriptors */ 3177 rctl = er32(RCTL); 3178 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3179 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3180 e1e_flush(); 3181 usleep_range(10000, 20000); 3182 3183 if (adapter->flags2 & FLAG2_DMA_BURST) { 3184 /* set the writeback threshold (only takes effect if the RDTR 3185 * is set). set GRAN=1 and write back up to 0x4 worth, and 3186 * enable prefetching of 0x20 Rx descriptors 3187 * granularity = 01 3188 * wthresh = 04, 3189 * hthresh = 04, 3190 * pthresh = 0x20 3191 */ 3192 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3193 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3194 3195 /* override the delay timers for enabling bursting, only if 3196 * the value was not set by the user via module options 3197 */ 3198 if (adapter->rx_int_delay == DEFAULT_RDTR) 3199 adapter->rx_int_delay = BURST_RDTR; 3200 if (adapter->rx_abs_int_delay == DEFAULT_RADV) 3201 adapter->rx_abs_int_delay = BURST_RADV; 3202 } 3203 3204 /* set the Receive Delay Timer Register */ 3205 ew32(RDTR, adapter->rx_int_delay); 3206 3207 /* irq moderation */ 3208 ew32(RADV, adapter->rx_abs_int_delay); 3209 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3210 e1000e_write_itr(adapter, adapter->itr); 3211 3212 ctrl_ext = er32(CTRL_EXT); 3213 /* Auto-Mask interrupts upon ICR access */ 3214 ctrl_ext |= E1000_CTRL_EXT_IAME; 3215 ew32(IAM, 0xffffffff); 3216 ew32(CTRL_EXT, ctrl_ext); 3217 e1e_flush(); 3218 3219 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3220 * the Base and Length of the Rx Descriptor Ring 3221 */ 3222 rdba = rx_ring->dma; 3223 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3224 ew32(RDBAH(0), (rdba >> 32)); 3225 ew32(RDLEN(0), rdlen); 3226 ew32(RDH(0), 0); 3227 ew32(RDT(0), 0); 3228 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3229 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3230 3231 /* Enable Receive Checksum Offload for TCP and UDP */ 3232 rxcsum = er32(RXCSUM); 3233 if (adapter->netdev->features & NETIF_F_RXCSUM) 3234 rxcsum |= E1000_RXCSUM_TUOFL; 3235 else 3236 rxcsum &= ~E1000_RXCSUM_TUOFL; 3237 ew32(RXCSUM, rxcsum); 3238 3239 /* With jumbo frames, excessive C-state transition latencies result 3240 * in dropped transactions. 3241 */ 3242 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3243 u32 lat = 3244 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3245 adapter->max_frame_size) * 8 / 1000; 3246 3247 if (adapter->flags & FLAG_IS_ICH) { 3248 u32 rxdctl = er32(RXDCTL(0)); 3249 3250 ew32(RXDCTL(0), rxdctl | 0x3); 3251 } 3252 3253 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat); 3254 } else { 3255 pm_qos_update_request(&adapter->netdev->pm_qos_req, 3256 PM_QOS_DEFAULT_VALUE); 3257 } 3258 3259 /* Enable Receives */ 3260 ew32(RCTL, rctl); 3261 } 3262 3263 /** 3264 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3265 * @netdev: network interface device structure 3266 * 3267 * Writes multicast address list to the MTA hash table. 3268 * Returns: -ENOMEM on failure 3269 * 0 on no addresses written 3270 * X on writing X addresses to MTA 3271 */ 3272 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3273 { 3274 struct e1000_adapter *adapter = netdev_priv(netdev); 3275 struct e1000_hw *hw = &adapter->hw; 3276 struct netdev_hw_addr *ha; 3277 u8 *mta_list; 3278 int i; 3279 3280 if (netdev_mc_empty(netdev)) { 3281 /* nothing to program, so clear mc list */ 3282 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3283 return 0; 3284 } 3285 3286 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC); 3287 if (!mta_list) 3288 return -ENOMEM; 3289 3290 /* update_mc_addr_list expects a packed array of only addresses. */ 3291 i = 0; 3292 netdev_for_each_mc_addr(ha, netdev) 3293 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3294 3295 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3296 kfree(mta_list); 3297 3298 return netdev_mc_count(netdev); 3299 } 3300 3301 /** 3302 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3303 * @netdev: network interface device structure 3304 * 3305 * Writes unicast address list to the RAR table. 3306 * Returns: -ENOMEM on failure/insufficient address space 3307 * 0 on no addresses written 3308 * X on writing X addresses to the RAR table 3309 **/ 3310 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3311 { 3312 struct e1000_adapter *adapter = netdev_priv(netdev); 3313 struct e1000_hw *hw = &adapter->hw; 3314 unsigned int rar_entries = hw->mac.rar_entry_count; 3315 int count = 0; 3316 3317 /* save a rar entry for our hardware address */ 3318 rar_entries--; 3319 3320 /* save a rar entry for the LAA workaround */ 3321 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3322 rar_entries--; 3323 3324 /* return ENOMEM indicating insufficient memory for addresses */ 3325 if (netdev_uc_count(netdev) > rar_entries) 3326 return -ENOMEM; 3327 3328 if (!netdev_uc_empty(netdev) && rar_entries) { 3329 struct netdev_hw_addr *ha; 3330 3331 /* write the addresses in reverse order to avoid write 3332 * combining 3333 */ 3334 netdev_for_each_uc_addr(ha, netdev) { 3335 if (!rar_entries) 3336 break; 3337 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3338 count++; 3339 } 3340 } 3341 3342 /* zero out the remaining RAR entries not used above */ 3343 for (; rar_entries > 0; rar_entries--) { 3344 ew32(RAH(rar_entries), 0); 3345 ew32(RAL(rar_entries), 0); 3346 } 3347 e1e_flush(); 3348 3349 return count; 3350 } 3351 3352 /** 3353 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3354 * @netdev: network interface device structure 3355 * 3356 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3357 * address list or the network interface flags are updated. This routine is 3358 * responsible for configuring the hardware for proper unicast, multicast, 3359 * promiscuous mode, and all-multi behavior. 3360 **/ 3361 static void e1000e_set_rx_mode(struct net_device *netdev) 3362 { 3363 struct e1000_adapter *adapter = netdev_priv(netdev); 3364 struct e1000_hw *hw = &adapter->hw; 3365 u32 rctl; 3366 3367 if (pm_runtime_suspended(netdev->dev.parent)) 3368 return; 3369 3370 /* Check for Promiscuous and All Multicast modes */ 3371 rctl = er32(RCTL); 3372 3373 /* clear the affected bits */ 3374 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3375 3376 if (netdev->flags & IFF_PROMISC) { 3377 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3378 /* Do not hardware filter VLANs in promisc mode */ 3379 e1000e_vlan_filter_disable(adapter); 3380 } else { 3381 int count; 3382 3383 if (netdev->flags & IFF_ALLMULTI) { 3384 rctl |= E1000_RCTL_MPE; 3385 } else { 3386 /* Write addresses to the MTA, if the attempt fails 3387 * then we should just turn on promiscuous mode so 3388 * that we can at least receive multicast traffic 3389 */ 3390 count = e1000e_write_mc_addr_list(netdev); 3391 if (count < 0) 3392 rctl |= E1000_RCTL_MPE; 3393 } 3394 e1000e_vlan_filter_enable(adapter); 3395 /* Write addresses to available RAR registers, if there is not 3396 * sufficient space to store all the addresses then enable 3397 * unicast promiscuous mode 3398 */ 3399 count = e1000e_write_uc_addr_list(netdev); 3400 if (count < 0) 3401 rctl |= E1000_RCTL_UPE; 3402 } 3403 3404 ew32(RCTL, rctl); 3405 3406 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3407 e1000e_vlan_strip_enable(adapter); 3408 else 3409 e1000e_vlan_strip_disable(adapter); 3410 } 3411 3412 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3413 { 3414 struct e1000_hw *hw = &adapter->hw; 3415 u32 mrqc, rxcsum; 3416 int i; 3417 static const u32 rsskey[10] = { 3418 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0, 3419 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe 3420 }; 3421 3422 /* Fill out hash function seed */ 3423 for (i = 0; i < 10; i++) 3424 ew32(RSSRK(i), rsskey[i]); 3425 3426 /* Direct all traffic to queue 0 */ 3427 for (i = 0; i < 32; i++) 3428 ew32(RETA(i), 0); 3429 3430 /* Disable raw packet checksumming so that RSS hash is placed in 3431 * descriptor on writeback. 3432 */ 3433 rxcsum = er32(RXCSUM); 3434 rxcsum |= E1000_RXCSUM_PCSD; 3435 3436 ew32(RXCSUM, rxcsum); 3437 3438 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3439 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3440 E1000_MRQC_RSS_FIELD_IPV6 | 3441 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3442 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3443 3444 ew32(MRQC, mrqc); 3445 } 3446 3447 /** 3448 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3449 * @adapter: board private structure 3450 * @timinca: pointer to returned time increment attributes 3451 * 3452 * Get attributes for incrementing the System Time Register SYSTIML/H at 3453 * the default base frequency, and set the cyclecounter shift value. 3454 **/ 3455 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3456 { 3457 struct e1000_hw *hw = &adapter->hw; 3458 u32 incvalue, incperiod, shift; 3459 3460 /* Make sure clock is enabled on I217 before checking the frequency */ 3461 if ((hw->mac.type == e1000_pch_lpt) && 3462 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3463 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3464 u32 fextnvm7 = er32(FEXTNVM7); 3465 3466 if (!(fextnvm7 & (1 << 0))) { 3467 ew32(FEXTNVM7, fextnvm7 | (1 << 0)); 3468 e1e_flush(); 3469 } 3470 } 3471 3472 switch (hw->mac.type) { 3473 case e1000_pch2lan: 3474 case e1000_pch_lpt: 3475 /* On I217, the clock frequency is 25MHz or 96MHz as 3476 * indicated by the System Clock Frequency Indication 3477 */ 3478 if ((hw->mac.type != e1000_pch_lpt) || 3479 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) { 3480 /* Stable 96MHz frequency */ 3481 incperiod = INCPERIOD_96MHz; 3482 incvalue = INCVALUE_96MHz; 3483 shift = INCVALUE_SHIFT_96MHz; 3484 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz; 3485 break; 3486 } 3487 /* fall-through */ 3488 case e1000_82574: 3489 case e1000_82583: 3490 /* Stable 25MHz frequency */ 3491 incperiod = INCPERIOD_25MHz; 3492 incvalue = INCVALUE_25MHz; 3493 shift = INCVALUE_SHIFT_25MHz; 3494 adapter->cc.shift = shift; 3495 break; 3496 default: 3497 return -EINVAL; 3498 } 3499 3500 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3501 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3502 3503 return 0; 3504 } 3505 3506 /** 3507 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3508 * @adapter: board private structure 3509 * 3510 * Outgoing time stamping can be enabled and disabled. Play nice and 3511 * disable it when requested, although it shouldn't cause any overhead 3512 * when no packet needs it. At most one packet in the queue may be 3513 * marked for time stamping, otherwise it would be impossible to tell 3514 * for sure to which packet the hardware time stamp belongs. 3515 * 3516 * Incoming time stamping has to be configured via the hardware filters. 3517 * Not all combinations are supported, in particular event type has to be 3518 * specified. Matching the kind of event packet is not supported, with the 3519 * exception of "all V2 events regardless of level 2 or 4". 3520 **/ 3521 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3522 struct hwtstamp_config *config) 3523 { 3524 struct e1000_hw *hw = &adapter->hw; 3525 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3526 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3527 u32 rxmtrl = 0; 3528 u16 rxudp = 0; 3529 bool is_l4 = false; 3530 bool is_l2 = false; 3531 u32 regval; 3532 s32 ret_val; 3533 3534 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3535 return -EINVAL; 3536 3537 /* flags reserved for future extensions - must be zero */ 3538 if (config->flags) 3539 return -EINVAL; 3540 3541 switch (config->tx_type) { 3542 case HWTSTAMP_TX_OFF: 3543 tsync_tx_ctl = 0; 3544 break; 3545 case HWTSTAMP_TX_ON: 3546 break; 3547 default: 3548 return -ERANGE; 3549 } 3550 3551 switch (config->rx_filter) { 3552 case HWTSTAMP_FILTER_NONE: 3553 tsync_rx_ctl = 0; 3554 break; 3555 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3556 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3557 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3558 is_l4 = true; 3559 break; 3560 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3561 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3562 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3563 is_l4 = true; 3564 break; 3565 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3566 /* Also time stamps V2 L2 Path Delay Request/Response */ 3567 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3568 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3569 is_l2 = true; 3570 break; 3571 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3572 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3573 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3574 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3575 is_l2 = true; 3576 break; 3577 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3578 /* Hardware cannot filter just V2 L4 Sync messages; 3579 * fall-through to V2 (both L2 and L4) Sync. 3580 */ 3581 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3582 /* Also time stamps V2 Path Delay Request/Response. */ 3583 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3584 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3585 is_l2 = true; 3586 is_l4 = true; 3587 break; 3588 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3589 /* Hardware cannot filter just V2 L4 Delay Request messages; 3590 * fall-through to V2 (both L2 and L4) Delay Request. 3591 */ 3592 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3593 /* Also time stamps V2 Path Delay Request/Response. */ 3594 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3595 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3596 is_l2 = true; 3597 is_l4 = true; 3598 break; 3599 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3600 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3601 /* Hardware cannot filter just V2 L4 or L2 Event messages; 3602 * fall-through to all V2 (both L2 and L4) Events. 3603 */ 3604 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3605 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3606 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3607 is_l2 = true; 3608 is_l4 = true; 3609 break; 3610 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3611 /* For V1, the hardware can only filter Sync messages or 3612 * Delay Request messages but not both so fall-through to 3613 * time stamp all packets. 3614 */ 3615 case HWTSTAMP_FILTER_ALL: 3616 is_l2 = true; 3617 is_l4 = true; 3618 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3619 config->rx_filter = HWTSTAMP_FILTER_ALL; 3620 break; 3621 default: 3622 return -ERANGE; 3623 } 3624 3625 adapter->hwtstamp_config = *config; 3626 3627 /* enable/disable Tx h/w time stamping */ 3628 regval = er32(TSYNCTXCTL); 3629 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3630 regval |= tsync_tx_ctl; 3631 ew32(TSYNCTXCTL, regval); 3632 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3633 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3634 e_err("Timesync Tx Control register not set as expected\n"); 3635 return -EAGAIN; 3636 } 3637 3638 /* enable/disable Rx h/w time stamping */ 3639 regval = er32(TSYNCRXCTL); 3640 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3641 regval |= tsync_rx_ctl; 3642 ew32(TSYNCRXCTL, regval); 3643 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3644 E1000_TSYNCRXCTL_TYPE_MASK)) != 3645 (regval & (E1000_TSYNCRXCTL_ENABLED | 3646 E1000_TSYNCRXCTL_TYPE_MASK))) { 3647 e_err("Timesync Rx Control register not set as expected\n"); 3648 return -EAGAIN; 3649 } 3650 3651 /* L2: define ethertype filter for time stamped packets */ 3652 if (is_l2) 3653 rxmtrl |= ETH_P_1588; 3654 3655 /* define which PTP packets get time stamped */ 3656 ew32(RXMTRL, rxmtrl); 3657 3658 /* Filter by destination port */ 3659 if (is_l4) { 3660 rxudp = PTP_EV_PORT; 3661 cpu_to_be16s(&rxudp); 3662 } 3663 ew32(RXUDP, rxudp); 3664 3665 e1e_flush(); 3666 3667 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3668 er32(RXSTMPH); 3669 er32(TXSTMPH); 3670 3671 /* Get and set the System Time Register SYSTIM base frequency */ 3672 ret_val = e1000e_get_base_timinca(adapter, ®val); 3673 if (ret_val) 3674 return ret_val; 3675 ew32(TIMINCA, regval); 3676 3677 /* reset the ns time counter */ 3678 timecounter_init(&adapter->tc, &adapter->cc, 3679 ktime_to_ns(ktime_get_real())); 3680 3681 return 0; 3682 } 3683 3684 /** 3685 * e1000_configure - configure the hardware for Rx and Tx 3686 * @adapter: private board structure 3687 **/ 3688 static void e1000_configure(struct e1000_adapter *adapter) 3689 { 3690 struct e1000_ring *rx_ring = adapter->rx_ring; 3691 3692 e1000e_set_rx_mode(adapter->netdev); 3693 3694 e1000_restore_vlan(adapter); 3695 e1000_init_manageability_pt(adapter); 3696 3697 e1000_configure_tx(adapter); 3698 3699 if (adapter->netdev->features & NETIF_F_RXHASH) 3700 e1000e_setup_rss_hash(adapter); 3701 e1000_setup_rctl(adapter); 3702 e1000_configure_rx(adapter); 3703 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3704 } 3705 3706 /** 3707 * e1000e_power_up_phy - restore link in case the phy was powered down 3708 * @adapter: address of board private structure 3709 * 3710 * The phy may be powered down to save power and turn off link when the 3711 * driver is unloaded and wake on lan is not enabled (among others) 3712 * *** this routine MUST be followed by a call to e1000e_reset *** 3713 **/ 3714 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3715 { 3716 if (adapter->hw.phy.ops.power_up) 3717 adapter->hw.phy.ops.power_up(&adapter->hw); 3718 3719 adapter->hw.mac.ops.setup_link(&adapter->hw); 3720 } 3721 3722 /** 3723 * e1000_power_down_phy - Power down the PHY 3724 * 3725 * Power down the PHY so no link is implied when interface is down. 3726 * The PHY cannot be powered down if management or WoL is active. 3727 */ 3728 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3729 { 3730 if (adapter->hw.phy.ops.power_down) 3731 adapter->hw.phy.ops.power_down(&adapter->hw); 3732 } 3733 3734 /** 3735 * e1000e_reset - bring the hardware into a known good state 3736 * 3737 * This function boots the hardware and enables some settings that 3738 * require a configuration cycle of the hardware - those cannot be 3739 * set/changed during runtime. After reset the device needs to be 3740 * properly configured for Rx, Tx etc. 3741 */ 3742 void e1000e_reset(struct e1000_adapter *adapter) 3743 { 3744 struct e1000_mac_info *mac = &adapter->hw.mac; 3745 struct e1000_fc_info *fc = &adapter->hw.fc; 3746 struct e1000_hw *hw = &adapter->hw; 3747 u32 tx_space, min_tx_space, min_rx_space; 3748 u32 pba = adapter->pba; 3749 u16 hwm; 3750 3751 /* reset Packet Buffer Allocation to default */ 3752 ew32(PBA, pba); 3753 3754 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) { 3755 /* To maintain wire speed transmits, the Tx FIFO should be 3756 * large enough to accommodate two full transmit packets, 3757 * rounded up to the next 1KB and expressed in KB. Likewise, 3758 * the Rx FIFO should be large enough to accommodate at least 3759 * one full receive packet and is similarly rounded up and 3760 * expressed in KB. 3761 */ 3762 pba = er32(PBA); 3763 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3764 tx_space = pba >> 16; 3765 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3766 pba &= 0xffff; 3767 /* the Tx fifo also stores 16 bytes of information about the Tx 3768 * but don't include ethernet FCS because hardware appends it 3769 */ 3770 min_tx_space = (adapter->max_frame_size + 3771 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 3772 min_tx_space = ALIGN(min_tx_space, 1024); 3773 min_tx_space >>= 10; 3774 /* software strips receive CRC, so leave room for it */ 3775 min_rx_space = adapter->max_frame_size; 3776 min_rx_space = ALIGN(min_rx_space, 1024); 3777 min_rx_space >>= 10; 3778 3779 /* If current Tx allocation is less than the min Tx FIFO size, 3780 * and the min Tx FIFO size is less than the current Rx FIFO 3781 * allocation, take space away from current Rx allocation 3782 */ 3783 if ((tx_space < min_tx_space) && 3784 ((min_tx_space - tx_space) < pba)) { 3785 pba -= min_tx_space - tx_space; 3786 3787 /* if short on Rx space, Rx wins and must trump Tx 3788 * adjustment 3789 */ 3790 if (pba < min_rx_space) 3791 pba = min_rx_space; 3792 } 3793 3794 ew32(PBA, pba); 3795 } 3796 3797 /* flow control settings 3798 * 3799 * The high water mark must be low enough to fit one full frame 3800 * (or the size used for early receive) above it in the Rx FIFO. 3801 * Set it to the lower of: 3802 * - 90% of the Rx FIFO size, and 3803 * - the full Rx FIFO size minus one full frame 3804 */ 3805 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 3806 fc->pause_time = 0xFFFF; 3807 else 3808 fc->pause_time = E1000_FC_PAUSE_TIME; 3809 fc->send_xon = true; 3810 fc->current_mode = fc->requested_mode; 3811 3812 switch (hw->mac.type) { 3813 case e1000_ich9lan: 3814 case e1000_ich10lan: 3815 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3816 pba = 14; 3817 ew32(PBA, pba); 3818 fc->high_water = 0x2800; 3819 fc->low_water = fc->high_water - 8; 3820 break; 3821 } 3822 /* fall-through */ 3823 default: 3824 hwm = min(((pba << 10) * 9 / 10), 3825 ((pba << 10) - adapter->max_frame_size)); 3826 3827 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 3828 fc->low_water = fc->high_water - 8; 3829 break; 3830 case e1000_pchlan: 3831 /* Workaround PCH LOM adapter hangs with certain network 3832 * loads. If hangs persist, try disabling Tx flow control. 3833 */ 3834 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3835 fc->high_water = 0x3500; 3836 fc->low_water = 0x1500; 3837 } else { 3838 fc->high_water = 0x5000; 3839 fc->low_water = 0x3000; 3840 } 3841 fc->refresh_time = 0x1000; 3842 break; 3843 case e1000_pch2lan: 3844 case e1000_pch_lpt: 3845 fc->refresh_time = 0x0400; 3846 3847 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 3848 fc->high_water = 0x05C20; 3849 fc->low_water = 0x05048; 3850 fc->pause_time = 0x0650; 3851 break; 3852 } 3853 3854 pba = 14; 3855 ew32(PBA, pba); 3856 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 3857 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 3858 break; 3859 } 3860 3861 /* Alignment of Tx data is on an arbitrary byte boundary with the 3862 * maximum size per Tx descriptor limited only to the transmit 3863 * allocation of the packet buffer minus 96 bytes with an upper 3864 * limit of 24KB due to receive synchronization limitations. 3865 */ 3866 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 3867 24 << 10); 3868 3869 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 3870 * fit in receive buffer. 3871 */ 3872 if (adapter->itr_setting & 0x3) { 3873 if ((adapter->max_frame_size * 2) > (pba << 10)) { 3874 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 3875 dev_info(&adapter->pdev->dev, 3876 "Interrupt Throttle Rate off\n"); 3877 adapter->flags2 |= FLAG2_DISABLE_AIM; 3878 e1000e_write_itr(adapter, 0); 3879 } 3880 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 3881 dev_info(&adapter->pdev->dev, 3882 "Interrupt Throttle Rate on\n"); 3883 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 3884 adapter->itr = 20000; 3885 e1000e_write_itr(adapter, adapter->itr); 3886 } 3887 } 3888 3889 /* Allow time for pending master requests to run */ 3890 mac->ops.reset_hw(hw); 3891 3892 /* For parts with AMT enabled, let the firmware know 3893 * that the network interface is in control 3894 */ 3895 if (adapter->flags & FLAG_HAS_AMT) 3896 e1000e_get_hw_control(adapter); 3897 3898 ew32(WUC, 0); 3899 3900 if (mac->ops.init_hw(hw)) 3901 e_err("Hardware Error\n"); 3902 3903 e1000_update_mng_vlan(adapter); 3904 3905 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 3906 ew32(VET, ETH_P_8021Q); 3907 3908 e1000e_reset_adaptive(hw); 3909 3910 /* initialize systim and reset the ns time counter */ 3911 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3912 3913 /* Set EEE advertisement as appropriate */ 3914 if (adapter->flags2 & FLAG2_HAS_EEE) { 3915 s32 ret_val; 3916 u16 adv_addr; 3917 3918 switch (hw->phy.type) { 3919 case e1000_phy_82579: 3920 adv_addr = I82579_EEE_ADVERTISEMENT; 3921 break; 3922 case e1000_phy_i217: 3923 adv_addr = I217_EEE_ADVERTISEMENT; 3924 break; 3925 default: 3926 dev_err(&adapter->pdev->dev, 3927 "Invalid PHY type setting EEE advertisement\n"); 3928 return; 3929 } 3930 3931 ret_val = hw->phy.ops.acquire(hw); 3932 if (ret_val) { 3933 dev_err(&adapter->pdev->dev, 3934 "EEE advertisement - unable to acquire PHY\n"); 3935 return; 3936 } 3937 3938 e1000_write_emi_reg_locked(hw, adv_addr, 3939 hw->dev_spec.ich8lan.eee_disable ? 3940 0 : adapter->eee_advert); 3941 3942 hw->phy.ops.release(hw); 3943 } 3944 3945 if (!netif_running(adapter->netdev) && 3946 !test_bit(__E1000_TESTING, &adapter->state)) 3947 e1000_power_down_phy(adapter); 3948 3949 e1000_get_phy_info(hw); 3950 3951 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 3952 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 3953 u16 phy_data = 0; 3954 /* speed up time to link by disabling smart power down, ignore 3955 * the return value of this function because there is nothing 3956 * different we would do if it failed 3957 */ 3958 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 3959 phy_data &= ~IGP02E1000_PM_SPD; 3960 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 3961 } 3962 } 3963 3964 int e1000e_up(struct e1000_adapter *adapter) 3965 { 3966 struct e1000_hw *hw = &adapter->hw; 3967 3968 /* hardware has been reset, we need to reload some things */ 3969 e1000_configure(adapter); 3970 3971 clear_bit(__E1000_DOWN, &adapter->state); 3972 3973 if (adapter->msix_entries) 3974 e1000_configure_msix(adapter); 3975 e1000_irq_enable(adapter); 3976 3977 netif_start_queue(adapter->netdev); 3978 3979 /* fire a link change interrupt to start the watchdog */ 3980 if (adapter->msix_entries) 3981 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER); 3982 else 3983 ew32(ICS, E1000_ICS_LSC); 3984 3985 return 0; 3986 } 3987 3988 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 3989 { 3990 struct e1000_hw *hw = &adapter->hw; 3991 3992 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 3993 return; 3994 3995 /* flush pending descriptor writebacks to memory */ 3996 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 3997 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 3998 3999 /* execute the writes immediately */ 4000 e1e_flush(); 4001 4002 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4003 * write is successful 4004 */ 4005 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4006 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4007 4008 /* execute the writes immediately */ 4009 e1e_flush(); 4010 } 4011 4012 static void e1000e_update_stats(struct e1000_adapter *adapter); 4013 4014 /** 4015 * e1000e_down - quiesce the device and optionally reset the hardware 4016 * @adapter: board private structure 4017 * @reset: boolean flag to reset the hardware or not 4018 */ 4019 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4020 { 4021 struct net_device *netdev = adapter->netdev; 4022 struct e1000_hw *hw = &adapter->hw; 4023 u32 tctl, rctl; 4024 4025 /* signal that we're down so the interrupt handler does not 4026 * reschedule our watchdog timer 4027 */ 4028 set_bit(__E1000_DOWN, &adapter->state); 4029 4030 /* disable receives in the hardware */ 4031 rctl = er32(RCTL); 4032 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4033 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4034 /* flush and sleep below */ 4035 4036 netif_stop_queue(netdev); 4037 4038 /* disable transmits in the hardware */ 4039 tctl = er32(TCTL); 4040 tctl &= ~E1000_TCTL_EN; 4041 ew32(TCTL, tctl); 4042 4043 /* flush both disables and wait for them to finish */ 4044 e1e_flush(); 4045 usleep_range(10000, 20000); 4046 4047 e1000_irq_disable(adapter); 4048 4049 napi_synchronize(&adapter->napi); 4050 4051 del_timer_sync(&adapter->watchdog_timer); 4052 del_timer_sync(&adapter->phy_info_timer); 4053 4054 netif_carrier_off(netdev); 4055 4056 spin_lock(&adapter->stats64_lock); 4057 e1000e_update_stats(adapter); 4058 spin_unlock(&adapter->stats64_lock); 4059 4060 e1000e_flush_descriptors(adapter); 4061 e1000_clean_tx_ring(adapter->tx_ring); 4062 e1000_clean_rx_ring(adapter->rx_ring); 4063 4064 adapter->link_speed = 0; 4065 adapter->link_duplex = 0; 4066 4067 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4068 if ((hw->mac.type >= e1000_pch2lan) && 4069 (adapter->netdev->mtu > ETH_DATA_LEN) && 4070 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4071 e_dbg("failed to disable jumbo frame workaround mode\n"); 4072 4073 if (reset && !pci_channel_offline(adapter->pdev)) 4074 e1000e_reset(adapter); 4075 } 4076 4077 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4078 { 4079 might_sleep(); 4080 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4081 usleep_range(1000, 2000); 4082 e1000e_down(adapter, true); 4083 e1000e_up(adapter); 4084 clear_bit(__E1000_RESETTING, &adapter->state); 4085 } 4086 4087 /** 4088 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4089 * @cc: cyclecounter structure 4090 **/ 4091 static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc) 4092 { 4093 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4094 cc); 4095 struct e1000_hw *hw = &adapter->hw; 4096 cycle_t systim; 4097 4098 /* latch SYSTIMH on read of SYSTIML */ 4099 systim = (cycle_t)er32(SYSTIML); 4100 systim |= (cycle_t)er32(SYSTIMH) << 32; 4101 4102 return systim; 4103 } 4104 4105 /** 4106 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4107 * @adapter: board private structure to initialize 4108 * 4109 * e1000_sw_init initializes the Adapter private data structure. 4110 * Fields are initialized based on PCI device information and 4111 * OS network device settings (MTU size). 4112 **/ 4113 static int e1000_sw_init(struct e1000_adapter *adapter) 4114 { 4115 struct net_device *netdev = adapter->netdev; 4116 4117 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN; 4118 adapter->rx_ps_bsize0 = 128; 4119 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4120 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4121 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4122 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4123 4124 spin_lock_init(&adapter->stats64_lock); 4125 4126 e1000e_set_interrupt_capability(adapter); 4127 4128 if (e1000_alloc_queues(adapter)) 4129 return -ENOMEM; 4130 4131 /* Setup hardware time stamping cyclecounter */ 4132 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4133 adapter->cc.read = e1000e_cyclecounter_read; 4134 adapter->cc.mask = CLOCKSOURCE_MASK(64); 4135 adapter->cc.mult = 1; 4136 /* cc.shift set in e1000e_get_base_tininca() */ 4137 4138 spin_lock_init(&adapter->systim_lock); 4139 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4140 } 4141 4142 /* Explicitly disable IRQ since the NIC can be in any state. */ 4143 e1000_irq_disable(adapter); 4144 4145 set_bit(__E1000_DOWN, &adapter->state); 4146 return 0; 4147 } 4148 4149 /** 4150 * e1000_intr_msi_test - Interrupt Handler 4151 * @irq: interrupt number 4152 * @data: pointer to a network interface device structure 4153 **/ 4154 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4155 { 4156 struct net_device *netdev = data; 4157 struct e1000_adapter *adapter = netdev_priv(netdev); 4158 struct e1000_hw *hw = &adapter->hw; 4159 u32 icr = er32(ICR); 4160 4161 e_dbg("icr is %08X\n", icr); 4162 if (icr & E1000_ICR_RXSEQ) { 4163 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4164 /* Force memory writes to complete before acknowledging the 4165 * interrupt is handled. 4166 */ 4167 wmb(); 4168 } 4169 4170 return IRQ_HANDLED; 4171 } 4172 4173 /** 4174 * e1000_test_msi_interrupt - Returns 0 for successful test 4175 * @adapter: board private struct 4176 * 4177 * code flow taken from tg3.c 4178 **/ 4179 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4180 { 4181 struct net_device *netdev = adapter->netdev; 4182 struct e1000_hw *hw = &adapter->hw; 4183 int err; 4184 4185 /* poll_enable hasn't been called yet, so don't need disable */ 4186 /* clear any pending events */ 4187 er32(ICR); 4188 4189 /* free the real vector and request a test handler */ 4190 e1000_free_irq(adapter); 4191 e1000e_reset_interrupt_capability(adapter); 4192 4193 /* Assume that the test fails, if it succeeds then the test 4194 * MSI irq handler will unset this flag 4195 */ 4196 adapter->flags |= FLAG_MSI_TEST_FAILED; 4197 4198 err = pci_enable_msi(adapter->pdev); 4199 if (err) 4200 goto msi_test_failed; 4201 4202 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4203 netdev->name, netdev); 4204 if (err) { 4205 pci_disable_msi(adapter->pdev); 4206 goto msi_test_failed; 4207 } 4208 4209 /* Force memory writes to complete before enabling and firing an 4210 * interrupt. 4211 */ 4212 wmb(); 4213 4214 e1000_irq_enable(adapter); 4215 4216 /* fire an unusual interrupt on the test handler */ 4217 ew32(ICS, E1000_ICS_RXSEQ); 4218 e1e_flush(); 4219 msleep(100); 4220 4221 e1000_irq_disable(adapter); 4222 4223 rmb(); /* read flags after interrupt has been fired */ 4224 4225 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4226 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4227 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4228 } else { 4229 e_dbg("MSI interrupt test succeeded!\n"); 4230 } 4231 4232 free_irq(adapter->pdev->irq, netdev); 4233 pci_disable_msi(adapter->pdev); 4234 4235 msi_test_failed: 4236 e1000e_set_interrupt_capability(adapter); 4237 return e1000_request_irq(adapter); 4238 } 4239 4240 /** 4241 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4242 * @adapter: board private struct 4243 * 4244 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4245 **/ 4246 static int e1000_test_msi(struct e1000_adapter *adapter) 4247 { 4248 int err; 4249 u16 pci_cmd; 4250 4251 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4252 return 0; 4253 4254 /* disable SERR in case the MSI write causes a master abort */ 4255 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4256 if (pci_cmd & PCI_COMMAND_SERR) 4257 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4258 pci_cmd & ~PCI_COMMAND_SERR); 4259 4260 err = e1000_test_msi_interrupt(adapter); 4261 4262 /* re-enable SERR */ 4263 if (pci_cmd & PCI_COMMAND_SERR) { 4264 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4265 pci_cmd |= PCI_COMMAND_SERR; 4266 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4267 } 4268 4269 return err; 4270 } 4271 4272 /** 4273 * e1000_open - Called when a network interface is made active 4274 * @netdev: network interface device structure 4275 * 4276 * Returns 0 on success, negative value on failure 4277 * 4278 * The open entry point is called when a network interface is made 4279 * active by the system (IFF_UP). At this point all resources needed 4280 * for transmit and receive operations are allocated, the interrupt 4281 * handler is registered with the OS, the watchdog timer is started, 4282 * and the stack is notified that the interface is ready. 4283 **/ 4284 static int e1000_open(struct net_device *netdev) 4285 { 4286 struct e1000_adapter *adapter = netdev_priv(netdev); 4287 struct e1000_hw *hw = &adapter->hw; 4288 struct pci_dev *pdev = adapter->pdev; 4289 int err; 4290 4291 /* disallow open during test */ 4292 if (test_bit(__E1000_TESTING, &adapter->state)) 4293 return -EBUSY; 4294 4295 pm_runtime_get_sync(&pdev->dev); 4296 4297 netif_carrier_off(netdev); 4298 4299 /* allocate transmit descriptors */ 4300 err = e1000e_setup_tx_resources(adapter->tx_ring); 4301 if (err) 4302 goto err_setup_tx; 4303 4304 /* allocate receive descriptors */ 4305 err = e1000e_setup_rx_resources(adapter->rx_ring); 4306 if (err) 4307 goto err_setup_rx; 4308 4309 /* If AMT is enabled, let the firmware know that the network 4310 * interface is now open and reset the part to a known state. 4311 */ 4312 if (adapter->flags & FLAG_HAS_AMT) { 4313 e1000e_get_hw_control(adapter); 4314 e1000e_reset(adapter); 4315 } 4316 4317 e1000e_power_up_phy(adapter); 4318 4319 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4320 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4321 e1000_update_mng_vlan(adapter); 4322 4323 /* DMA latency requirement to workaround jumbo issue */ 4324 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 4325 PM_QOS_DEFAULT_VALUE); 4326 4327 /* before we allocate an interrupt, we must be ready to handle it. 4328 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4329 * as soon as we call pci_request_irq, so we have to setup our 4330 * clean_rx handler before we do so. 4331 */ 4332 e1000_configure(adapter); 4333 4334 err = e1000_request_irq(adapter); 4335 if (err) 4336 goto err_req_irq; 4337 4338 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4339 * ignore e1000e MSI messages, which means we need to test our MSI 4340 * interrupt now 4341 */ 4342 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4343 err = e1000_test_msi(adapter); 4344 if (err) { 4345 e_err("Interrupt allocation failed\n"); 4346 goto err_req_irq; 4347 } 4348 } 4349 4350 /* From here on the code is the same as e1000e_up() */ 4351 clear_bit(__E1000_DOWN, &adapter->state); 4352 4353 napi_enable(&adapter->napi); 4354 4355 e1000_irq_enable(adapter); 4356 4357 adapter->tx_hang_recheck = false; 4358 netif_start_queue(netdev); 4359 4360 hw->mac.get_link_status = true; 4361 pm_runtime_put(&pdev->dev); 4362 4363 /* fire a link status change interrupt to start the watchdog */ 4364 if (adapter->msix_entries) 4365 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER); 4366 else 4367 ew32(ICS, E1000_ICS_LSC); 4368 4369 return 0; 4370 4371 err_req_irq: 4372 e1000e_release_hw_control(adapter); 4373 e1000_power_down_phy(adapter); 4374 e1000e_free_rx_resources(adapter->rx_ring); 4375 err_setup_rx: 4376 e1000e_free_tx_resources(adapter->tx_ring); 4377 err_setup_tx: 4378 e1000e_reset(adapter); 4379 pm_runtime_put_sync(&pdev->dev); 4380 4381 return err; 4382 } 4383 4384 /** 4385 * e1000_close - Disables a network interface 4386 * @netdev: network interface device structure 4387 * 4388 * Returns 0, this is not allowed to fail 4389 * 4390 * The close entry point is called when an interface is de-activated 4391 * by the OS. The hardware is still under the drivers control, but 4392 * needs to be disabled. A global MAC reset is issued to stop the 4393 * hardware, and all transmit and receive resources are freed. 4394 **/ 4395 static int e1000_close(struct net_device *netdev) 4396 { 4397 struct e1000_adapter *adapter = netdev_priv(netdev); 4398 struct pci_dev *pdev = adapter->pdev; 4399 int count = E1000_CHECK_RESET_COUNT; 4400 4401 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4402 usleep_range(10000, 20000); 4403 4404 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4405 4406 pm_runtime_get_sync(&pdev->dev); 4407 4408 if (!test_bit(__E1000_DOWN, &adapter->state)) { 4409 e1000e_down(adapter, true); 4410 e1000_free_irq(adapter); 4411 4412 /* Link status message must follow this format */ 4413 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 4414 } 4415 4416 napi_disable(&adapter->napi); 4417 4418 e1000e_free_tx_resources(adapter->tx_ring); 4419 e1000e_free_rx_resources(adapter->rx_ring); 4420 4421 /* kill manageability vlan ID if supported, but not if a vlan with 4422 * the same ID is registered on the host OS (let 8021q kill it) 4423 */ 4424 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4425 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4426 adapter->mng_vlan_id); 4427 4428 /* If AMT is enabled, let the firmware know that the network 4429 * interface is now closed 4430 */ 4431 if ((adapter->flags & FLAG_HAS_AMT) && 4432 !test_bit(__E1000_TESTING, &adapter->state)) 4433 e1000e_release_hw_control(adapter); 4434 4435 pm_qos_remove_request(&adapter->netdev->pm_qos_req); 4436 4437 pm_runtime_put_sync(&pdev->dev); 4438 4439 return 0; 4440 } 4441 4442 /** 4443 * e1000_set_mac - Change the Ethernet Address of the NIC 4444 * @netdev: network interface device structure 4445 * @p: pointer to an address structure 4446 * 4447 * Returns 0 on success, negative on failure 4448 **/ 4449 static int e1000_set_mac(struct net_device *netdev, void *p) 4450 { 4451 struct e1000_adapter *adapter = netdev_priv(netdev); 4452 struct e1000_hw *hw = &adapter->hw; 4453 struct sockaddr *addr = p; 4454 4455 if (!is_valid_ether_addr(addr->sa_data)) 4456 return -EADDRNOTAVAIL; 4457 4458 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4459 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4460 4461 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4462 4463 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4464 /* activate the work around */ 4465 e1000e_set_laa_state_82571(&adapter->hw, 1); 4466 4467 /* Hold a copy of the LAA in RAR[14] This is done so that 4468 * between the time RAR[0] gets clobbered and the time it 4469 * gets fixed (in e1000_watchdog), the actual LAA is in one 4470 * of the RARs and no incoming packets directed to this port 4471 * are dropped. Eventually the LAA will be in RAR[0] and 4472 * RAR[14] 4473 */ 4474 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4475 adapter->hw.mac.rar_entry_count - 1); 4476 } 4477 4478 return 0; 4479 } 4480 4481 /** 4482 * e1000e_update_phy_task - work thread to update phy 4483 * @work: pointer to our work struct 4484 * 4485 * this worker thread exists because we must acquire a 4486 * semaphore to read the phy, which we could msleep while 4487 * waiting for it, and we can't msleep in a timer. 4488 **/ 4489 static void e1000e_update_phy_task(struct work_struct *work) 4490 { 4491 struct e1000_adapter *adapter = container_of(work, 4492 struct e1000_adapter, 4493 update_phy_task); 4494 struct e1000_hw *hw = &adapter->hw; 4495 4496 if (test_bit(__E1000_DOWN, &adapter->state)) 4497 return; 4498 4499 e1000_get_phy_info(hw); 4500 4501 /* Enable EEE on 82579 after link up */ 4502 if (hw->phy.type == e1000_phy_82579) 4503 e1000_set_eee_pchlan(hw); 4504 } 4505 4506 /** 4507 * e1000_update_phy_info - timre call-back to update PHY info 4508 * @data: pointer to adapter cast into an unsigned long 4509 * 4510 * Need to wait a few seconds after link up to get diagnostic information from 4511 * the phy 4512 **/ 4513 static void e1000_update_phy_info(unsigned long data) 4514 { 4515 struct e1000_adapter *adapter = (struct e1000_adapter *)data; 4516 4517 if (test_bit(__E1000_DOWN, &adapter->state)) 4518 return; 4519 4520 schedule_work(&adapter->update_phy_task); 4521 } 4522 4523 /** 4524 * e1000e_update_phy_stats - Update the PHY statistics counters 4525 * @adapter: board private structure 4526 * 4527 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4528 **/ 4529 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4530 { 4531 struct e1000_hw *hw = &adapter->hw; 4532 s32 ret_val; 4533 u16 phy_data; 4534 4535 ret_val = hw->phy.ops.acquire(hw); 4536 if (ret_val) 4537 return; 4538 4539 /* A page set is expensive so check if already on desired page. 4540 * If not, set to the page with the PHY status registers. 4541 */ 4542 hw->phy.addr = 1; 4543 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4544 &phy_data); 4545 if (ret_val) 4546 goto release; 4547 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4548 ret_val = hw->phy.ops.set_page(hw, 4549 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4550 if (ret_val) 4551 goto release; 4552 } 4553 4554 /* Single Collision Count */ 4555 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4556 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4557 if (!ret_val) 4558 adapter->stats.scc += phy_data; 4559 4560 /* Excessive Collision Count */ 4561 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4562 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4563 if (!ret_val) 4564 adapter->stats.ecol += phy_data; 4565 4566 /* Multiple Collision Count */ 4567 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4568 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4569 if (!ret_val) 4570 adapter->stats.mcc += phy_data; 4571 4572 /* Late Collision Count */ 4573 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4574 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4575 if (!ret_val) 4576 adapter->stats.latecol += phy_data; 4577 4578 /* Collision Count - also used for adaptive IFS */ 4579 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4580 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4581 if (!ret_val) 4582 hw->mac.collision_delta = phy_data; 4583 4584 /* Defer Count */ 4585 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4586 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4587 if (!ret_val) 4588 adapter->stats.dc += phy_data; 4589 4590 /* Transmit with no CRS */ 4591 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4592 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4593 if (!ret_val) 4594 adapter->stats.tncrs += phy_data; 4595 4596 release: 4597 hw->phy.ops.release(hw); 4598 } 4599 4600 /** 4601 * e1000e_update_stats - Update the board statistics counters 4602 * @adapter: board private structure 4603 **/ 4604 static void e1000e_update_stats(struct e1000_adapter *adapter) 4605 { 4606 struct net_device *netdev = adapter->netdev; 4607 struct e1000_hw *hw = &adapter->hw; 4608 struct pci_dev *pdev = adapter->pdev; 4609 4610 /* Prevent stats update while adapter is being reset, or if the pci 4611 * connection is down. 4612 */ 4613 if (adapter->link_speed == 0) 4614 return; 4615 if (pci_channel_offline(pdev)) 4616 return; 4617 4618 adapter->stats.crcerrs += er32(CRCERRS); 4619 adapter->stats.gprc += er32(GPRC); 4620 adapter->stats.gorc += er32(GORCL); 4621 er32(GORCH); /* Clear gorc */ 4622 adapter->stats.bprc += er32(BPRC); 4623 adapter->stats.mprc += er32(MPRC); 4624 adapter->stats.roc += er32(ROC); 4625 4626 adapter->stats.mpc += er32(MPC); 4627 4628 /* Half-duplex statistics */ 4629 if (adapter->link_duplex == HALF_DUPLEX) { 4630 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4631 e1000e_update_phy_stats(adapter); 4632 } else { 4633 adapter->stats.scc += er32(SCC); 4634 adapter->stats.ecol += er32(ECOL); 4635 adapter->stats.mcc += er32(MCC); 4636 adapter->stats.latecol += er32(LATECOL); 4637 adapter->stats.dc += er32(DC); 4638 4639 hw->mac.collision_delta = er32(COLC); 4640 4641 if ((hw->mac.type != e1000_82574) && 4642 (hw->mac.type != e1000_82583)) 4643 adapter->stats.tncrs += er32(TNCRS); 4644 } 4645 adapter->stats.colc += hw->mac.collision_delta; 4646 } 4647 4648 adapter->stats.xonrxc += er32(XONRXC); 4649 adapter->stats.xontxc += er32(XONTXC); 4650 adapter->stats.xoffrxc += er32(XOFFRXC); 4651 adapter->stats.xofftxc += er32(XOFFTXC); 4652 adapter->stats.gptc += er32(GPTC); 4653 adapter->stats.gotc += er32(GOTCL); 4654 er32(GOTCH); /* Clear gotc */ 4655 adapter->stats.rnbc += er32(RNBC); 4656 adapter->stats.ruc += er32(RUC); 4657 4658 adapter->stats.mptc += er32(MPTC); 4659 adapter->stats.bptc += er32(BPTC); 4660 4661 /* used for adaptive IFS */ 4662 4663 hw->mac.tx_packet_delta = er32(TPT); 4664 adapter->stats.tpt += hw->mac.tx_packet_delta; 4665 4666 adapter->stats.algnerrc += er32(ALGNERRC); 4667 adapter->stats.rxerrc += er32(RXERRC); 4668 adapter->stats.cexterr += er32(CEXTERR); 4669 adapter->stats.tsctc += er32(TSCTC); 4670 adapter->stats.tsctfc += er32(TSCTFC); 4671 4672 /* Fill out the OS statistics structure */ 4673 netdev->stats.multicast = adapter->stats.mprc; 4674 netdev->stats.collisions = adapter->stats.colc; 4675 4676 /* Rx Errors */ 4677 4678 /* RLEC on some newer hardware can be incorrect so build 4679 * our own version based on RUC and ROC 4680 */ 4681 netdev->stats.rx_errors = adapter->stats.rxerrc + 4682 adapter->stats.crcerrs + adapter->stats.algnerrc + 4683 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 4684 netdev->stats.rx_length_errors = adapter->stats.ruc + 4685 adapter->stats.roc; 4686 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 4687 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 4688 netdev->stats.rx_missed_errors = adapter->stats.mpc; 4689 4690 /* Tx Errors */ 4691 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 4692 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 4693 netdev->stats.tx_window_errors = adapter->stats.latecol; 4694 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 4695 4696 /* Tx Dropped needs to be maintained elsewhere */ 4697 4698 /* Management Stats */ 4699 adapter->stats.mgptc += er32(MGTPTC); 4700 adapter->stats.mgprc += er32(MGTPRC); 4701 adapter->stats.mgpdc += er32(MGTPDC); 4702 4703 /* Correctable ECC Errors */ 4704 if (hw->mac.type == e1000_pch_lpt) { 4705 u32 pbeccsts = er32(PBECCSTS); 4706 4707 adapter->corr_errors += 4708 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 4709 adapter->uncorr_errors += 4710 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 4711 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 4712 } 4713 } 4714 4715 /** 4716 * e1000_phy_read_status - Update the PHY register status snapshot 4717 * @adapter: board private structure 4718 **/ 4719 static void e1000_phy_read_status(struct e1000_adapter *adapter) 4720 { 4721 struct e1000_hw *hw = &adapter->hw; 4722 struct e1000_phy_regs *phy = &adapter->phy_regs; 4723 4724 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 4725 (er32(STATUS) & E1000_STATUS_LU) && 4726 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 4727 int ret_val; 4728 4729 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 4730 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 4731 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 4732 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 4733 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 4734 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 4735 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 4736 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 4737 if (ret_val) 4738 e_warn("Error reading PHY register\n"); 4739 } else { 4740 /* Do not read PHY registers if link is not up 4741 * Set values to typical power-on defaults 4742 */ 4743 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 4744 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 4745 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 4746 BMSR_ERCAP); 4747 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 4748 ADVERTISE_ALL | ADVERTISE_CSMA); 4749 phy->lpa = 0; 4750 phy->expansion = EXPANSION_ENABLENPAGE; 4751 phy->ctrl1000 = ADVERTISE_1000FULL; 4752 phy->stat1000 = 0; 4753 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 4754 } 4755 } 4756 4757 static void e1000_print_link_info(struct e1000_adapter *adapter) 4758 { 4759 struct e1000_hw *hw = &adapter->hw; 4760 u32 ctrl = er32(CTRL); 4761 4762 /* Link status message must follow this format for user tools */ 4763 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4764 adapter->netdev->name, adapter->link_speed, 4765 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 4766 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 4767 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 4768 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 4769 } 4770 4771 static bool e1000e_has_link(struct e1000_adapter *adapter) 4772 { 4773 struct e1000_hw *hw = &adapter->hw; 4774 bool link_active = false; 4775 s32 ret_val = 0; 4776 4777 /* get_link_status is set on LSC (link status) interrupt or 4778 * Rx sequence error interrupt. get_link_status will stay 4779 * false until the check_for_link establishes link 4780 * for copper adapters ONLY 4781 */ 4782 switch (hw->phy.media_type) { 4783 case e1000_media_type_copper: 4784 if (hw->mac.get_link_status) { 4785 ret_val = hw->mac.ops.check_for_link(hw); 4786 link_active = !hw->mac.get_link_status; 4787 } else { 4788 link_active = true; 4789 } 4790 break; 4791 case e1000_media_type_fiber: 4792 ret_val = hw->mac.ops.check_for_link(hw); 4793 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 4794 break; 4795 case e1000_media_type_internal_serdes: 4796 ret_val = hw->mac.ops.check_for_link(hw); 4797 link_active = adapter->hw.mac.serdes_has_link; 4798 break; 4799 default: 4800 case e1000_media_type_unknown: 4801 break; 4802 } 4803 4804 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 4805 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 4806 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 4807 e_info("Gigabit has been disabled, downgrading speed\n"); 4808 } 4809 4810 return link_active; 4811 } 4812 4813 static void e1000e_enable_receives(struct e1000_adapter *adapter) 4814 { 4815 /* make sure the receive unit is started */ 4816 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 4817 (adapter->flags & FLAG_RESTART_NOW)) { 4818 struct e1000_hw *hw = &adapter->hw; 4819 u32 rctl = er32(RCTL); 4820 4821 ew32(RCTL, rctl | E1000_RCTL_EN); 4822 adapter->flags &= ~FLAG_RESTART_NOW; 4823 } 4824 } 4825 4826 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 4827 { 4828 struct e1000_hw *hw = &adapter->hw; 4829 4830 /* With 82574 controllers, PHY needs to be checked periodically 4831 * for hung state and reset, if two calls return true 4832 */ 4833 if (e1000_check_phy_82574(hw)) 4834 adapter->phy_hang_count++; 4835 else 4836 adapter->phy_hang_count = 0; 4837 4838 if (adapter->phy_hang_count > 1) { 4839 adapter->phy_hang_count = 0; 4840 e_dbg("PHY appears hung - resetting\n"); 4841 schedule_work(&adapter->reset_task); 4842 } 4843 } 4844 4845 /** 4846 * e1000_watchdog - Timer Call-back 4847 * @data: pointer to adapter cast into an unsigned long 4848 **/ 4849 static void e1000_watchdog(unsigned long data) 4850 { 4851 struct e1000_adapter *adapter = (struct e1000_adapter *)data; 4852 4853 /* Do the rest outside of interrupt context */ 4854 schedule_work(&adapter->watchdog_task); 4855 4856 /* TODO: make this use queue_delayed_work() */ 4857 } 4858 4859 static void e1000_watchdog_task(struct work_struct *work) 4860 { 4861 struct e1000_adapter *adapter = container_of(work, 4862 struct e1000_adapter, 4863 watchdog_task); 4864 struct net_device *netdev = adapter->netdev; 4865 struct e1000_mac_info *mac = &adapter->hw.mac; 4866 struct e1000_phy_info *phy = &adapter->hw.phy; 4867 struct e1000_ring *tx_ring = adapter->tx_ring; 4868 struct e1000_hw *hw = &adapter->hw; 4869 u32 link, tctl; 4870 4871 if (test_bit(__E1000_DOWN, &adapter->state)) 4872 return; 4873 4874 link = e1000e_has_link(adapter); 4875 if ((netif_carrier_ok(netdev)) && link) { 4876 /* Cancel scheduled suspend requests. */ 4877 pm_runtime_resume(netdev->dev.parent); 4878 4879 e1000e_enable_receives(adapter); 4880 goto link_up; 4881 } 4882 4883 if ((e1000e_enable_tx_pkt_filtering(hw)) && 4884 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 4885 e1000_update_mng_vlan(adapter); 4886 4887 if (link) { 4888 if (!netif_carrier_ok(netdev)) { 4889 bool txb2b = true; 4890 4891 /* Cancel scheduled suspend requests. */ 4892 pm_runtime_resume(netdev->dev.parent); 4893 4894 /* update snapshot of PHY registers on LSC */ 4895 e1000_phy_read_status(adapter); 4896 mac->ops.get_link_up_info(&adapter->hw, 4897 &adapter->link_speed, 4898 &adapter->link_duplex); 4899 e1000_print_link_info(adapter); 4900 4901 /* check if SmartSpeed worked */ 4902 e1000e_check_downshift(hw); 4903 if (phy->speed_downgraded) 4904 netdev_warn(netdev, 4905 "Link Speed was downgraded by SmartSpeed\n"); 4906 4907 /* On supported PHYs, check for duplex mismatch only 4908 * if link has autonegotiated at 10/100 half 4909 */ 4910 if ((hw->phy.type == e1000_phy_igp_3 || 4911 hw->phy.type == e1000_phy_bm) && 4912 hw->mac.autoneg && 4913 (adapter->link_speed == SPEED_10 || 4914 adapter->link_speed == SPEED_100) && 4915 (adapter->link_duplex == HALF_DUPLEX)) { 4916 u16 autoneg_exp; 4917 4918 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 4919 4920 if (!(autoneg_exp & EXPANSION_NWAY)) 4921 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 4922 } 4923 4924 /* adjust timeout factor according to speed/duplex */ 4925 adapter->tx_timeout_factor = 1; 4926 switch (adapter->link_speed) { 4927 case SPEED_10: 4928 txb2b = false; 4929 adapter->tx_timeout_factor = 16; 4930 break; 4931 case SPEED_100: 4932 txb2b = false; 4933 adapter->tx_timeout_factor = 10; 4934 break; 4935 } 4936 4937 /* workaround: re-program speed mode bit after 4938 * link-up event 4939 */ 4940 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 4941 !txb2b) { 4942 u32 tarc0; 4943 4944 tarc0 = er32(TARC(0)); 4945 tarc0 &= ~SPEED_MODE_BIT; 4946 ew32(TARC(0), tarc0); 4947 } 4948 4949 /* disable TSO for pcie and 10/100 speeds, to avoid 4950 * some hardware issues 4951 */ 4952 if (!(adapter->flags & FLAG_TSO_FORCE)) { 4953 switch (adapter->link_speed) { 4954 case SPEED_10: 4955 case SPEED_100: 4956 e_info("10/100 speed: disabling TSO\n"); 4957 netdev->features &= ~NETIF_F_TSO; 4958 netdev->features &= ~NETIF_F_TSO6; 4959 break; 4960 case SPEED_1000: 4961 netdev->features |= NETIF_F_TSO; 4962 netdev->features |= NETIF_F_TSO6; 4963 break; 4964 default: 4965 /* oops */ 4966 break; 4967 } 4968 } 4969 4970 /* enable transmits in the hardware, need to do this 4971 * after setting TARC(0) 4972 */ 4973 tctl = er32(TCTL); 4974 tctl |= E1000_TCTL_EN; 4975 ew32(TCTL, tctl); 4976 4977 /* Perform any post-link-up configuration before 4978 * reporting link up. 4979 */ 4980 if (phy->ops.cfg_on_link_up) 4981 phy->ops.cfg_on_link_up(hw); 4982 4983 netif_carrier_on(netdev); 4984 4985 if (!test_bit(__E1000_DOWN, &adapter->state)) 4986 mod_timer(&adapter->phy_info_timer, 4987 round_jiffies(jiffies + 2 * HZ)); 4988 } 4989 } else { 4990 if (netif_carrier_ok(netdev)) { 4991 adapter->link_speed = 0; 4992 adapter->link_duplex = 0; 4993 /* Link status message must follow this format */ 4994 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 4995 netif_carrier_off(netdev); 4996 if (!test_bit(__E1000_DOWN, &adapter->state)) 4997 mod_timer(&adapter->phy_info_timer, 4998 round_jiffies(jiffies + 2 * HZ)); 4999 5000 /* 8000ES2LAN requires a Rx packet buffer work-around 5001 * on link down event; reset the controller to flush 5002 * the Rx packet buffer. 5003 */ 5004 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5005 adapter->flags |= FLAG_RESTART_NOW; 5006 else 5007 pm_schedule_suspend(netdev->dev.parent, 5008 LINK_TIMEOUT); 5009 } 5010 } 5011 5012 link_up: 5013 spin_lock(&adapter->stats64_lock); 5014 e1000e_update_stats(adapter); 5015 5016 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5017 adapter->tpt_old = adapter->stats.tpt; 5018 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5019 adapter->colc_old = adapter->stats.colc; 5020 5021 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5022 adapter->gorc_old = adapter->stats.gorc; 5023 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5024 adapter->gotc_old = adapter->stats.gotc; 5025 spin_unlock(&adapter->stats64_lock); 5026 5027 /* If the link is lost the controller stops DMA, but 5028 * if there is queued Tx work it cannot be done. So 5029 * reset the controller to flush the Tx packet buffers. 5030 */ 5031 if (!netif_carrier_ok(netdev) && 5032 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5033 adapter->flags |= FLAG_RESTART_NOW; 5034 5035 /* If reset is necessary, do it outside of interrupt context. */ 5036 if (adapter->flags & FLAG_RESTART_NOW) { 5037 schedule_work(&adapter->reset_task); 5038 /* return immediately since reset is imminent */ 5039 return; 5040 } 5041 5042 e1000e_update_adaptive(&adapter->hw); 5043 5044 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5045 if (adapter->itr_setting == 4) { 5046 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5047 * Total asymmetrical Tx or Rx gets ITR=8000; 5048 * everyone else is between 2000-8000. 5049 */ 5050 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5051 u32 dif = (adapter->gotc > adapter->gorc ? 5052 adapter->gotc - adapter->gorc : 5053 adapter->gorc - adapter->gotc) / 10000; 5054 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5055 5056 e1000e_write_itr(adapter, itr); 5057 } 5058 5059 /* Cause software interrupt to ensure Rx ring is cleaned */ 5060 if (adapter->msix_entries) 5061 ew32(ICS, adapter->rx_ring->ims_val); 5062 else 5063 ew32(ICS, E1000_ICS_RXDMT0); 5064 5065 /* flush pending descriptors to memory before detecting Tx hang */ 5066 e1000e_flush_descriptors(adapter); 5067 5068 /* Force detection of hung controller every watchdog period */ 5069 adapter->detect_tx_hung = true; 5070 5071 /* With 82571 controllers, LAA may be overwritten due to controller 5072 * reset from the other port. Set the appropriate LAA in RAR[0] 5073 */ 5074 if (e1000e_get_laa_state_82571(hw)) 5075 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5076 5077 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5078 e1000e_check_82574_phy_workaround(adapter); 5079 5080 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5081 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5082 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5083 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5084 er32(RXSTMPH); 5085 adapter->rx_hwtstamp_cleared++; 5086 } else { 5087 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5088 } 5089 } 5090 5091 /* Reset the timer */ 5092 if (!test_bit(__E1000_DOWN, &adapter->state)) 5093 mod_timer(&adapter->watchdog_timer, 5094 round_jiffies(jiffies + 2 * HZ)); 5095 } 5096 5097 #define E1000_TX_FLAGS_CSUM 0x00000001 5098 #define E1000_TX_FLAGS_VLAN 0x00000002 5099 #define E1000_TX_FLAGS_TSO 0x00000004 5100 #define E1000_TX_FLAGS_IPV4 0x00000008 5101 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5102 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5103 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5104 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5105 5106 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb) 5107 { 5108 struct e1000_context_desc *context_desc; 5109 struct e1000_buffer *buffer_info; 5110 unsigned int i; 5111 u32 cmd_length = 0; 5112 u16 ipcse = 0, mss; 5113 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5114 int err; 5115 5116 if (!skb_is_gso(skb)) 5117 return 0; 5118 5119 err = skb_cow_head(skb, 0); 5120 if (err < 0) 5121 return err; 5122 5123 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5124 mss = skb_shinfo(skb)->gso_size; 5125 if (skb->protocol == htons(ETH_P_IP)) { 5126 struct iphdr *iph = ip_hdr(skb); 5127 iph->tot_len = 0; 5128 iph->check = 0; 5129 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5130 0, IPPROTO_TCP, 0); 5131 cmd_length = E1000_TXD_CMD_IP; 5132 ipcse = skb_transport_offset(skb) - 1; 5133 } else if (skb_is_gso_v6(skb)) { 5134 ipv6_hdr(skb)->payload_len = 0; 5135 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 5136 &ipv6_hdr(skb)->daddr, 5137 0, IPPROTO_TCP, 0); 5138 ipcse = 0; 5139 } 5140 ipcss = skb_network_offset(skb); 5141 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5142 tucss = skb_transport_offset(skb); 5143 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5144 5145 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5146 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5147 5148 i = tx_ring->next_to_use; 5149 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5150 buffer_info = &tx_ring->buffer_info[i]; 5151 5152 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5153 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5154 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5155 context_desc->upper_setup.tcp_fields.tucss = tucss; 5156 context_desc->upper_setup.tcp_fields.tucso = tucso; 5157 context_desc->upper_setup.tcp_fields.tucse = 0; 5158 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5159 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5160 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5161 5162 buffer_info->time_stamp = jiffies; 5163 buffer_info->next_to_watch = i; 5164 5165 i++; 5166 if (i == tx_ring->count) 5167 i = 0; 5168 tx_ring->next_to_use = i; 5169 5170 return 1; 5171 } 5172 5173 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb) 5174 { 5175 struct e1000_adapter *adapter = tx_ring->adapter; 5176 struct e1000_context_desc *context_desc; 5177 struct e1000_buffer *buffer_info; 5178 unsigned int i; 5179 u8 css; 5180 u32 cmd_len = E1000_TXD_CMD_DEXT; 5181 __be16 protocol; 5182 5183 if (skb->ip_summed != CHECKSUM_PARTIAL) 5184 return false; 5185 5186 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) 5187 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; 5188 else 5189 protocol = skb->protocol; 5190 5191 switch (protocol) { 5192 case cpu_to_be16(ETH_P_IP): 5193 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5194 cmd_len |= E1000_TXD_CMD_TCP; 5195 break; 5196 case cpu_to_be16(ETH_P_IPV6): 5197 /* XXX not handling all IPV6 headers */ 5198 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5199 cmd_len |= E1000_TXD_CMD_TCP; 5200 break; 5201 default: 5202 if (unlikely(net_ratelimit())) 5203 e_warn("checksum_partial proto=%x!\n", 5204 be16_to_cpu(protocol)); 5205 break; 5206 } 5207 5208 css = skb_checksum_start_offset(skb); 5209 5210 i = tx_ring->next_to_use; 5211 buffer_info = &tx_ring->buffer_info[i]; 5212 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5213 5214 context_desc->lower_setup.ip_config = 0; 5215 context_desc->upper_setup.tcp_fields.tucss = css; 5216 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5217 context_desc->upper_setup.tcp_fields.tucse = 0; 5218 context_desc->tcp_seg_setup.data = 0; 5219 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5220 5221 buffer_info->time_stamp = jiffies; 5222 buffer_info->next_to_watch = i; 5223 5224 i++; 5225 if (i == tx_ring->count) 5226 i = 0; 5227 tx_ring->next_to_use = i; 5228 5229 return true; 5230 } 5231 5232 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5233 unsigned int first, unsigned int max_per_txd, 5234 unsigned int nr_frags) 5235 { 5236 struct e1000_adapter *adapter = tx_ring->adapter; 5237 struct pci_dev *pdev = adapter->pdev; 5238 struct e1000_buffer *buffer_info; 5239 unsigned int len = skb_headlen(skb); 5240 unsigned int offset = 0, size, count = 0, i; 5241 unsigned int f, bytecount, segs; 5242 5243 i = tx_ring->next_to_use; 5244 5245 while (len) { 5246 buffer_info = &tx_ring->buffer_info[i]; 5247 size = min(len, max_per_txd); 5248 5249 buffer_info->length = size; 5250 buffer_info->time_stamp = jiffies; 5251 buffer_info->next_to_watch = i; 5252 buffer_info->dma = dma_map_single(&pdev->dev, 5253 skb->data + offset, 5254 size, DMA_TO_DEVICE); 5255 buffer_info->mapped_as_page = false; 5256 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5257 goto dma_error; 5258 5259 len -= size; 5260 offset += size; 5261 count++; 5262 5263 if (len) { 5264 i++; 5265 if (i == tx_ring->count) 5266 i = 0; 5267 } 5268 } 5269 5270 for (f = 0; f < nr_frags; f++) { 5271 const struct skb_frag_struct *frag; 5272 5273 frag = &skb_shinfo(skb)->frags[f]; 5274 len = skb_frag_size(frag); 5275 offset = 0; 5276 5277 while (len) { 5278 i++; 5279 if (i == tx_ring->count) 5280 i = 0; 5281 5282 buffer_info = &tx_ring->buffer_info[i]; 5283 size = min(len, max_per_txd); 5284 5285 buffer_info->length = size; 5286 buffer_info->time_stamp = jiffies; 5287 buffer_info->next_to_watch = i; 5288 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5289 offset, size, 5290 DMA_TO_DEVICE); 5291 buffer_info->mapped_as_page = true; 5292 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5293 goto dma_error; 5294 5295 len -= size; 5296 offset += size; 5297 count++; 5298 } 5299 } 5300 5301 segs = skb_shinfo(skb)->gso_segs ? : 1; 5302 /* multiply data chunks by size of headers */ 5303 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5304 5305 tx_ring->buffer_info[i].skb = skb; 5306 tx_ring->buffer_info[i].segs = segs; 5307 tx_ring->buffer_info[i].bytecount = bytecount; 5308 tx_ring->buffer_info[first].next_to_watch = i; 5309 5310 return count; 5311 5312 dma_error: 5313 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5314 buffer_info->dma = 0; 5315 if (count) 5316 count--; 5317 5318 while (count--) { 5319 if (i == 0) 5320 i += tx_ring->count; 5321 i--; 5322 buffer_info = &tx_ring->buffer_info[i]; 5323 e1000_put_txbuf(tx_ring, buffer_info); 5324 } 5325 5326 return 0; 5327 } 5328 5329 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5330 { 5331 struct e1000_adapter *adapter = tx_ring->adapter; 5332 struct e1000_tx_desc *tx_desc = NULL; 5333 struct e1000_buffer *buffer_info; 5334 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5335 unsigned int i; 5336 5337 if (tx_flags & E1000_TX_FLAGS_TSO) { 5338 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5339 E1000_TXD_CMD_TSE; 5340 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5341 5342 if (tx_flags & E1000_TX_FLAGS_IPV4) 5343 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5344 } 5345 5346 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5347 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5348 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5349 } 5350 5351 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5352 txd_lower |= E1000_TXD_CMD_VLE; 5353 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5354 } 5355 5356 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5357 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5358 5359 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5360 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5361 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5362 } 5363 5364 i = tx_ring->next_to_use; 5365 5366 do { 5367 buffer_info = &tx_ring->buffer_info[i]; 5368 tx_desc = E1000_TX_DESC(*tx_ring, i); 5369 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5370 tx_desc->lower.data = cpu_to_le32(txd_lower | 5371 buffer_info->length); 5372 tx_desc->upper.data = cpu_to_le32(txd_upper); 5373 5374 i++; 5375 if (i == tx_ring->count) 5376 i = 0; 5377 } while (--count > 0); 5378 5379 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5380 5381 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5382 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5383 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5384 5385 /* Force memory writes to complete before letting h/w 5386 * know there are new descriptors to fetch. (Only 5387 * applicable for weak-ordered memory model archs, 5388 * such as IA-64). 5389 */ 5390 wmb(); 5391 5392 tx_ring->next_to_use = i; 5393 5394 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5395 e1000e_update_tdt_wa(tx_ring, i); 5396 else 5397 writel(i, tx_ring->tail); 5398 5399 /* we need this if more than one processor can write to our tail 5400 * at a time, it synchronizes IO on IA64/Altix systems 5401 */ 5402 mmiowb(); 5403 } 5404 5405 #define MINIMUM_DHCP_PACKET_SIZE 282 5406 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5407 struct sk_buff *skb) 5408 { 5409 struct e1000_hw *hw = &adapter->hw; 5410 u16 length, offset; 5411 5412 if (vlan_tx_tag_present(skb) && 5413 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5414 (adapter->hw.mng_cookie.status & 5415 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5416 return 0; 5417 5418 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5419 return 0; 5420 5421 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5422 return 0; 5423 5424 { 5425 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5426 struct udphdr *udp; 5427 5428 if (ip->protocol != IPPROTO_UDP) 5429 return 0; 5430 5431 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5432 if (ntohs(udp->dest) != 67) 5433 return 0; 5434 5435 offset = (u8 *)udp + 8 - skb->data; 5436 length = skb->len - offset; 5437 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5438 } 5439 5440 return 0; 5441 } 5442 5443 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5444 { 5445 struct e1000_adapter *adapter = tx_ring->adapter; 5446 5447 netif_stop_queue(adapter->netdev); 5448 /* Herbert's original patch had: 5449 * smp_mb__after_netif_stop_queue(); 5450 * but since that doesn't exist yet, just open code it. 5451 */ 5452 smp_mb(); 5453 5454 /* We need to check again in a case another CPU has just 5455 * made room available. 5456 */ 5457 if (e1000_desc_unused(tx_ring) < size) 5458 return -EBUSY; 5459 5460 /* A reprieve! */ 5461 netif_start_queue(adapter->netdev); 5462 ++adapter->restart_queue; 5463 return 0; 5464 } 5465 5466 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5467 { 5468 BUG_ON(size > tx_ring->count); 5469 5470 if (e1000_desc_unused(tx_ring) >= size) 5471 return 0; 5472 return __e1000_maybe_stop_tx(tx_ring, size); 5473 } 5474 5475 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5476 struct net_device *netdev) 5477 { 5478 struct e1000_adapter *adapter = netdev_priv(netdev); 5479 struct e1000_ring *tx_ring = adapter->tx_ring; 5480 unsigned int first; 5481 unsigned int tx_flags = 0; 5482 unsigned int len = skb_headlen(skb); 5483 unsigned int nr_frags; 5484 unsigned int mss; 5485 int count = 0; 5486 int tso; 5487 unsigned int f; 5488 5489 if (test_bit(__E1000_DOWN, &adapter->state)) { 5490 dev_kfree_skb_any(skb); 5491 return NETDEV_TX_OK; 5492 } 5493 5494 if (skb->len <= 0) { 5495 dev_kfree_skb_any(skb); 5496 return NETDEV_TX_OK; 5497 } 5498 5499 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5500 * pad skb in order to meet this minimum size requirement 5501 */ 5502 if (unlikely(skb->len < 17)) { 5503 if (skb_pad(skb, 17 - skb->len)) 5504 return NETDEV_TX_OK; 5505 skb->len = 17; 5506 skb_set_tail_pointer(skb, 17); 5507 } 5508 5509 mss = skb_shinfo(skb)->gso_size; 5510 if (mss) { 5511 u8 hdr_len; 5512 5513 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5514 * points to just header, pull a few bytes of payload from 5515 * frags into skb->data 5516 */ 5517 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5518 /* we do this workaround for ES2LAN, but it is un-necessary, 5519 * avoiding it could save a lot of cycles 5520 */ 5521 if (skb->data_len && (hdr_len == len)) { 5522 unsigned int pull_size; 5523 5524 pull_size = min_t(unsigned int, 4, skb->data_len); 5525 if (!__pskb_pull_tail(skb, pull_size)) { 5526 e_err("__pskb_pull_tail failed.\n"); 5527 dev_kfree_skb_any(skb); 5528 return NETDEV_TX_OK; 5529 } 5530 len = skb_headlen(skb); 5531 } 5532 } 5533 5534 /* reserve a descriptor for the offload context */ 5535 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5536 count++; 5537 count++; 5538 5539 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5540 5541 nr_frags = skb_shinfo(skb)->nr_frags; 5542 for (f = 0; f < nr_frags; f++) 5543 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5544 adapter->tx_fifo_limit); 5545 5546 if (adapter->hw.mac.tx_pkt_filtering) 5547 e1000_transfer_dhcp_info(adapter, skb); 5548 5549 /* need: count + 2 desc gap to keep tail from touching 5550 * head, otherwise try next time 5551 */ 5552 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5553 return NETDEV_TX_BUSY; 5554 5555 if (vlan_tx_tag_present(skb)) { 5556 tx_flags |= E1000_TX_FLAGS_VLAN; 5557 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT); 5558 } 5559 5560 first = tx_ring->next_to_use; 5561 5562 tso = e1000_tso(tx_ring, skb); 5563 if (tso < 0) { 5564 dev_kfree_skb_any(skb); 5565 return NETDEV_TX_OK; 5566 } 5567 5568 if (tso) 5569 tx_flags |= E1000_TX_FLAGS_TSO; 5570 else if (e1000_tx_csum(tx_ring, skb)) 5571 tx_flags |= E1000_TX_FLAGS_CSUM; 5572 5573 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5574 * 82571 hardware supports TSO capabilities for IPv6 as well... 5575 * no longer assume, we must. 5576 */ 5577 if (skb->protocol == htons(ETH_P_IP)) 5578 tx_flags |= E1000_TX_FLAGS_IPV4; 5579 5580 if (unlikely(skb->no_fcs)) 5581 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5582 5583 /* if count is 0 then mapping error has occurred */ 5584 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5585 nr_frags); 5586 if (count) { 5587 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5588 !adapter->tx_hwtstamp_skb)) { 5589 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5590 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5591 adapter->tx_hwtstamp_skb = skb_get(skb); 5592 adapter->tx_hwtstamp_start = jiffies; 5593 schedule_work(&adapter->tx_hwtstamp_work); 5594 } else { 5595 skb_tx_timestamp(skb); 5596 } 5597 5598 netdev_sent_queue(netdev, skb->len); 5599 e1000_tx_queue(tx_ring, tx_flags, count); 5600 /* Make sure there is space in the ring for the next send. */ 5601 e1000_maybe_stop_tx(tx_ring, 5602 (MAX_SKB_FRAGS * 5603 DIV_ROUND_UP(PAGE_SIZE, 5604 adapter->tx_fifo_limit) + 2)); 5605 } else { 5606 dev_kfree_skb_any(skb); 5607 tx_ring->buffer_info[first].time_stamp = 0; 5608 tx_ring->next_to_use = first; 5609 } 5610 5611 return NETDEV_TX_OK; 5612 } 5613 5614 /** 5615 * e1000_tx_timeout - Respond to a Tx Hang 5616 * @netdev: network interface device structure 5617 **/ 5618 static void e1000_tx_timeout(struct net_device *netdev) 5619 { 5620 struct e1000_adapter *adapter = netdev_priv(netdev); 5621 5622 /* Do the reset outside of interrupt context */ 5623 adapter->tx_timeout_count++; 5624 schedule_work(&adapter->reset_task); 5625 } 5626 5627 static void e1000_reset_task(struct work_struct *work) 5628 { 5629 struct e1000_adapter *adapter; 5630 adapter = container_of(work, struct e1000_adapter, reset_task); 5631 5632 /* don't run the task if already down */ 5633 if (test_bit(__E1000_DOWN, &adapter->state)) 5634 return; 5635 5636 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5637 e1000e_dump(adapter); 5638 e_err("Reset adapter unexpectedly\n"); 5639 } 5640 e1000e_reinit_locked(adapter); 5641 } 5642 5643 /** 5644 * e1000_get_stats64 - Get System Network Statistics 5645 * @netdev: network interface device structure 5646 * @stats: rtnl_link_stats64 pointer 5647 * 5648 * Returns the address of the device statistics structure. 5649 **/ 5650 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, 5651 struct rtnl_link_stats64 *stats) 5652 { 5653 struct e1000_adapter *adapter = netdev_priv(netdev); 5654 5655 memset(stats, 0, sizeof(struct rtnl_link_stats64)); 5656 spin_lock(&adapter->stats64_lock); 5657 e1000e_update_stats(adapter); 5658 /* Fill out the OS statistics structure */ 5659 stats->rx_bytes = adapter->stats.gorc; 5660 stats->rx_packets = adapter->stats.gprc; 5661 stats->tx_bytes = adapter->stats.gotc; 5662 stats->tx_packets = adapter->stats.gptc; 5663 stats->multicast = adapter->stats.mprc; 5664 stats->collisions = adapter->stats.colc; 5665 5666 /* Rx Errors */ 5667 5668 /* RLEC on some newer hardware can be incorrect so build 5669 * our own version based on RUC and ROC 5670 */ 5671 stats->rx_errors = adapter->stats.rxerrc + 5672 adapter->stats.crcerrs + adapter->stats.algnerrc + 5673 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5674 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 5675 stats->rx_crc_errors = adapter->stats.crcerrs; 5676 stats->rx_frame_errors = adapter->stats.algnerrc; 5677 stats->rx_missed_errors = adapter->stats.mpc; 5678 5679 /* Tx Errors */ 5680 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5681 stats->tx_aborted_errors = adapter->stats.ecol; 5682 stats->tx_window_errors = adapter->stats.latecol; 5683 stats->tx_carrier_errors = adapter->stats.tncrs; 5684 5685 /* Tx Dropped needs to be maintained elsewhere */ 5686 5687 spin_unlock(&adapter->stats64_lock); 5688 return stats; 5689 } 5690 5691 /** 5692 * e1000_change_mtu - Change the Maximum Transfer Unit 5693 * @netdev: network interface device structure 5694 * @new_mtu: new value for maximum frame size 5695 * 5696 * Returns 0 on success, negative on failure 5697 **/ 5698 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 5699 { 5700 struct e1000_adapter *adapter = netdev_priv(netdev); 5701 int max_frame = new_mtu + VLAN_HLEN + ETH_HLEN + ETH_FCS_LEN; 5702 5703 /* Jumbo frame support */ 5704 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) && 5705 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 5706 e_err("Jumbo Frames not supported.\n"); 5707 return -EINVAL; 5708 } 5709 5710 /* Supported frame sizes */ 5711 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) || 5712 (max_frame > adapter->max_hw_frame_size)) { 5713 e_err("Unsupported MTU setting\n"); 5714 return -EINVAL; 5715 } 5716 5717 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 5718 if ((adapter->hw.mac.type >= e1000_pch2lan) && 5719 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 5720 (new_mtu > ETH_DATA_LEN)) { 5721 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 5722 return -EINVAL; 5723 } 5724 5725 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 5726 usleep_range(1000, 2000); 5727 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 5728 adapter->max_frame_size = max_frame; 5729 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5730 netdev->mtu = new_mtu; 5731 5732 pm_runtime_get_sync(netdev->dev.parent); 5733 5734 if (netif_running(netdev)) 5735 e1000e_down(adapter, true); 5736 5737 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 5738 * means we reserve 2 more, this pushes us to allocate from the next 5739 * larger slab size. 5740 * i.e. RXBUFFER_2048 --> size-4096 slab 5741 * However with the new *_jumbo_rx* routines, jumbo receives will use 5742 * fragmented skbs 5743 */ 5744 5745 if (max_frame <= 2048) 5746 adapter->rx_buffer_len = 2048; 5747 else 5748 adapter->rx_buffer_len = 4096; 5749 5750 /* adjust allocation if LPE protects us, and we aren't using SBP */ 5751 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || 5752 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)) 5753 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN 5754 + ETH_FCS_LEN; 5755 5756 if (netif_running(netdev)) 5757 e1000e_up(adapter); 5758 else 5759 e1000e_reset(adapter); 5760 5761 pm_runtime_put_sync(netdev->dev.parent); 5762 5763 clear_bit(__E1000_RESETTING, &adapter->state); 5764 5765 return 0; 5766 } 5767 5768 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 5769 int cmd) 5770 { 5771 struct e1000_adapter *adapter = netdev_priv(netdev); 5772 struct mii_ioctl_data *data = if_mii(ifr); 5773 5774 if (adapter->hw.phy.media_type != e1000_media_type_copper) 5775 return -EOPNOTSUPP; 5776 5777 switch (cmd) { 5778 case SIOCGMIIPHY: 5779 data->phy_id = adapter->hw.phy.addr; 5780 break; 5781 case SIOCGMIIREG: 5782 e1000_phy_read_status(adapter); 5783 5784 switch (data->reg_num & 0x1F) { 5785 case MII_BMCR: 5786 data->val_out = adapter->phy_regs.bmcr; 5787 break; 5788 case MII_BMSR: 5789 data->val_out = adapter->phy_regs.bmsr; 5790 break; 5791 case MII_PHYSID1: 5792 data->val_out = (adapter->hw.phy.id >> 16); 5793 break; 5794 case MII_PHYSID2: 5795 data->val_out = (adapter->hw.phy.id & 0xFFFF); 5796 break; 5797 case MII_ADVERTISE: 5798 data->val_out = adapter->phy_regs.advertise; 5799 break; 5800 case MII_LPA: 5801 data->val_out = adapter->phy_regs.lpa; 5802 break; 5803 case MII_EXPANSION: 5804 data->val_out = adapter->phy_regs.expansion; 5805 break; 5806 case MII_CTRL1000: 5807 data->val_out = adapter->phy_regs.ctrl1000; 5808 break; 5809 case MII_STAT1000: 5810 data->val_out = adapter->phy_regs.stat1000; 5811 break; 5812 case MII_ESTATUS: 5813 data->val_out = adapter->phy_regs.estatus; 5814 break; 5815 default: 5816 return -EIO; 5817 } 5818 break; 5819 case SIOCSMIIREG: 5820 default: 5821 return -EOPNOTSUPP; 5822 } 5823 return 0; 5824 } 5825 5826 /** 5827 * e1000e_hwtstamp_ioctl - control hardware time stamping 5828 * @netdev: network interface device structure 5829 * @ifreq: interface request 5830 * 5831 * Outgoing time stamping can be enabled and disabled. Play nice and 5832 * disable it when requested, although it shouldn't cause any overhead 5833 * when no packet needs it. At most one packet in the queue may be 5834 * marked for time stamping, otherwise it would be impossible to tell 5835 * for sure to which packet the hardware time stamp belongs. 5836 * 5837 * Incoming time stamping has to be configured via the hardware filters. 5838 * Not all combinations are supported, in particular event type has to be 5839 * specified. Matching the kind of event packet is not supported, with the 5840 * exception of "all V2 events regardless of level 2 or 4". 5841 **/ 5842 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 5843 { 5844 struct e1000_adapter *adapter = netdev_priv(netdev); 5845 struct hwtstamp_config config; 5846 int ret_val; 5847 5848 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 5849 return -EFAULT; 5850 5851 ret_val = e1000e_config_hwtstamp(adapter, &config); 5852 if (ret_val) 5853 return ret_val; 5854 5855 switch (config.rx_filter) { 5856 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 5857 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 5858 case HWTSTAMP_FILTER_PTP_V2_SYNC: 5859 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 5860 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 5861 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 5862 /* With V2 type filters which specify a Sync or Delay Request, 5863 * Path Delay Request/Response messages are also time stamped 5864 * by hardware so notify the caller the requested packets plus 5865 * some others are time stamped. 5866 */ 5867 config.rx_filter = HWTSTAMP_FILTER_SOME; 5868 break; 5869 default: 5870 break; 5871 } 5872 5873 return copy_to_user(ifr->ifr_data, &config, 5874 sizeof(config)) ? -EFAULT : 0; 5875 } 5876 5877 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 5878 { 5879 struct e1000_adapter *adapter = netdev_priv(netdev); 5880 5881 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 5882 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 5883 } 5884 5885 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 5886 { 5887 switch (cmd) { 5888 case SIOCGMIIPHY: 5889 case SIOCGMIIREG: 5890 case SIOCSMIIREG: 5891 return e1000_mii_ioctl(netdev, ifr, cmd); 5892 case SIOCSHWTSTAMP: 5893 return e1000e_hwtstamp_set(netdev, ifr); 5894 case SIOCGHWTSTAMP: 5895 return e1000e_hwtstamp_get(netdev, ifr); 5896 default: 5897 return -EOPNOTSUPP; 5898 } 5899 } 5900 5901 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 5902 { 5903 struct e1000_hw *hw = &adapter->hw; 5904 u32 i, mac_reg, wuc; 5905 u16 phy_reg, wuc_enable; 5906 int retval; 5907 5908 /* copy MAC RARs to PHY RARs */ 5909 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 5910 5911 retval = hw->phy.ops.acquire(hw); 5912 if (retval) { 5913 e_err("Could not acquire PHY\n"); 5914 return retval; 5915 } 5916 5917 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 5918 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 5919 if (retval) 5920 goto release; 5921 5922 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 5923 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 5924 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 5925 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 5926 (u16)(mac_reg & 0xFFFF)); 5927 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 5928 (u16)((mac_reg >> 16) & 0xFFFF)); 5929 } 5930 5931 /* configure PHY Rx Control register */ 5932 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 5933 mac_reg = er32(RCTL); 5934 if (mac_reg & E1000_RCTL_UPE) 5935 phy_reg |= BM_RCTL_UPE; 5936 if (mac_reg & E1000_RCTL_MPE) 5937 phy_reg |= BM_RCTL_MPE; 5938 phy_reg &= ~(BM_RCTL_MO_MASK); 5939 if (mac_reg & E1000_RCTL_MO_3) 5940 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 5941 << BM_RCTL_MO_SHIFT); 5942 if (mac_reg & E1000_RCTL_BAM) 5943 phy_reg |= BM_RCTL_BAM; 5944 if (mac_reg & E1000_RCTL_PMCF) 5945 phy_reg |= BM_RCTL_PMCF; 5946 mac_reg = er32(CTRL); 5947 if (mac_reg & E1000_CTRL_RFCE) 5948 phy_reg |= BM_RCTL_RFCE; 5949 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 5950 5951 wuc = E1000_WUC_PME_EN; 5952 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 5953 wuc |= E1000_WUC_APME; 5954 5955 /* enable PHY wakeup in MAC register */ 5956 ew32(WUFC, wufc); 5957 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 5958 E1000_WUC_PME_STATUS | wuc)); 5959 5960 /* configure and enable PHY wakeup in PHY registers */ 5961 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 5962 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 5963 5964 /* activate PHY wakeup */ 5965 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 5966 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 5967 if (retval) 5968 e_err("Could not set PHY Host Wakeup bit\n"); 5969 release: 5970 hw->phy.ops.release(hw); 5971 5972 return retval; 5973 } 5974 5975 static int e1000e_pm_freeze(struct device *dev) 5976 { 5977 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 5978 struct e1000_adapter *adapter = netdev_priv(netdev); 5979 5980 netif_device_detach(netdev); 5981 5982 if (netif_running(netdev)) { 5983 int count = E1000_CHECK_RESET_COUNT; 5984 5985 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 5986 usleep_range(10000, 20000); 5987 5988 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 5989 5990 /* Quiesce the device without resetting the hardware */ 5991 e1000e_down(adapter, false); 5992 e1000_free_irq(adapter); 5993 } 5994 e1000e_reset_interrupt_capability(adapter); 5995 5996 /* Allow time for pending master requests to run */ 5997 e1000e_disable_pcie_master(&adapter->hw); 5998 5999 return 0; 6000 } 6001 6002 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6003 { 6004 struct net_device *netdev = pci_get_drvdata(pdev); 6005 struct e1000_adapter *adapter = netdev_priv(netdev); 6006 struct e1000_hw *hw = &adapter->hw; 6007 u32 ctrl, ctrl_ext, rctl, status; 6008 /* Runtime suspend should only enable wakeup for link changes */ 6009 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6010 int retval = 0; 6011 6012 status = er32(STATUS); 6013 if (status & E1000_STATUS_LU) 6014 wufc &= ~E1000_WUFC_LNKC; 6015 6016 if (wufc) { 6017 e1000_setup_rctl(adapter); 6018 e1000e_set_rx_mode(netdev); 6019 6020 /* turn on all-multi mode if wake on multicast is enabled */ 6021 if (wufc & E1000_WUFC_MC) { 6022 rctl = er32(RCTL); 6023 rctl |= E1000_RCTL_MPE; 6024 ew32(RCTL, rctl); 6025 } 6026 6027 ctrl = er32(CTRL); 6028 ctrl |= E1000_CTRL_ADVD3WUC; 6029 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6030 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6031 ew32(CTRL, ctrl); 6032 6033 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6034 adapter->hw.phy.media_type == 6035 e1000_media_type_internal_serdes) { 6036 /* keep the laser running in D3 */ 6037 ctrl_ext = er32(CTRL_EXT); 6038 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6039 ew32(CTRL_EXT, ctrl_ext); 6040 } 6041 6042 if (!runtime) 6043 e1000e_power_up_phy(adapter); 6044 6045 if (adapter->flags & FLAG_IS_ICH) 6046 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6047 6048 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6049 /* enable wakeup by the PHY */ 6050 retval = e1000_init_phy_wakeup(adapter, wufc); 6051 if (retval) 6052 return retval; 6053 } else { 6054 /* enable wakeup by the MAC */ 6055 ew32(WUFC, wufc); 6056 ew32(WUC, E1000_WUC_PME_EN); 6057 } 6058 } else { 6059 ew32(WUC, 0); 6060 ew32(WUFC, 0); 6061 6062 e1000_power_down_phy(adapter); 6063 } 6064 6065 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6066 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6067 } else if (hw->mac.type == e1000_pch_lpt) { 6068 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6069 /* ULP does not support wake from unicast, multicast 6070 * or broadcast. 6071 */ 6072 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6073 6074 if (retval) 6075 return retval; 6076 } 6077 6078 6079 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6080 * would have already happened in close and is redundant. 6081 */ 6082 e1000e_release_hw_control(adapter); 6083 6084 pci_clear_master(pdev); 6085 6086 /* The pci-e switch on some quad port adapters will report a 6087 * correctable error when the MAC transitions from D0 to D3. To 6088 * prevent this we need to mask off the correctable errors on the 6089 * downstream port of the pci-e switch. 6090 * 6091 * We don't have the associated upstream bridge while assigning 6092 * the PCI device into guest. For example, the KVM on power is 6093 * one of the cases. 6094 */ 6095 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6096 struct pci_dev *us_dev = pdev->bus->self; 6097 u16 devctl; 6098 6099 if (!us_dev) 6100 return 0; 6101 6102 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6103 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6104 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6105 6106 pci_save_state(pdev); 6107 pci_prepare_to_sleep(pdev); 6108 6109 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6110 } 6111 6112 return 0; 6113 } 6114 6115 /** 6116 * e1000e_disable_aspm - Disable ASPM states 6117 * @pdev: pointer to PCI device struct 6118 * @state: bit-mask of ASPM states to disable 6119 * 6120 * Some devices *must* have certain ASPM states disabled per hardware errata. 6121 **/ 6122 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6123 { 6124 struct pci_dev *parent = pdev->bus->self; 6125 u16 aspm_dis_mask = 0; 6126 u16 pdev_aspmc, parent_aspmc; 6127 6128 switch (state) { 6129 case PCIE_LINK_STATE_L0S: 6130 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6131 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6132 /* fall-through - can't have L1 without L0s */ 6133 case PCIE_LINK_STATE_L1: 6134 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6135 break; 6136 default: 6137 return; 6138 } 6139 6140 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6141 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6142 6143 if (parent) { 6144 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6145 &parent_aspmc); 6146 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6147 } 6148 6149 /* Nothing to do if the ASPM states to be disabled already are */ 6150 if (!(pdev_aspmc & aspm_dis_mask) && 6151 (!parent || !(parent_aspmc & aspm_dis_mask))) 6152 return; 6153 6154 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6155 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6156 "L0s" : "", 6157 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6158 "L1" : ""); 6159 6160 #ifdef CONFIG_PCIEASPM 6161 pci_disable_link_state_locked(pdev, state); 6162 6163 /* Double-check ASPM control. If not disabled by the above, the 6164 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6165 * not enabled); override by writing PCI config space directly. 6166 */ 6167 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6168 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6169 6170 if (!(aspm_dis_mask & pdev_aspmc)) 6171 return; 6172 #endif 6173 6174 /* Both device and parent should have the same ASPM setting. 6175 * Disable ASPM in downstream component first and then upstream. 6176 */ 6177 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6178 6179 if (parent) 6180 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6181 aspm_dis_mask); 6182 } 6183 6184 #ifdef CONFIG_PM 6185 static int __e1000_resume(struct pci_dev *pdev) 6186 { 6187 struct net_device *netdev = pci_get_drvdata(pdev); 6188 struct e1000_adapter *adapter = netdev_priv(netdev); 6189 struct e1000_hw *hw = &adapter->hw; 6190 u16 aspm_disable_flag = 0; 6191 6192 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6193 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6194 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6195 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6196 if (aspm_disable_flag) 6197 e1000e_disable_aspm(pdev, aspm_disable_flag); 6198 6199 pci_set_master(pdev); 6200 6201 if (hw->mac.type >= e1000_pch2lan) 6202 e1000_resume_workarounds_pchlan(&adapter->hw); 6203 6204 e1000e_power_up_phy(adapter); 6205 6206 /* report the system wakeup cause from S3/S4 */ 6207 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6208 u16 phy_data; 6209 6210 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6211 if (phy_data) { 6212 e_info("PHY Wakeup cause - %s\n", 6213 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6214 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6215 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6216 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6217 phy_data & E1000_WUS_LNKC ? 6218 "Link Status Change" : "other"); 6219 } 6220 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6221 } else { 6222 u32 wus = er32(WUS); 6223 6224 if (wus) { 6225 e_info("MAC Wakeup cause - %s\n", 6226 wus & E1000_WUS_EX ? "Unicast Packet" : 6227 wus & E1000_WUS_MC ? "Multicast Packet" : 6228 wus & E1000_WUS_BC ? "Broadcast Packet" : 6229 wus & E1000_WUS_MAG ? "Magic Packet" : 6230 wus & E1000_WUS_LNKC ? "Link Status Change" : 6231 "other"); 6232 } 6233 ew32(WUS, ~0); 6234 } 6235 6236 e1000e_reset(adapter); 6237 6238 e1000_init_manageability_pt(adapter); 6239 6240 /* If the controller has AMT, do not set DRV_LOAD until the interface 6241 * is up. For all other cases, let the f/w know that the h/w is now 6242 * under the control of the driver. 6243 */ 6244 if (!(adapter->flags & FLAG_HAS_AMT)) 6245 e1000e_get_hw_control(adapter); 6246 6247 return 0; 6248 } 6249 6250 #ifdef CONFIG_PM_SLEEP 6251 static int e1000e_pm_thaw(struct device *dev) 6252 { 6253 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6254 struct e1000_adapter *adapter = netdev_priv(netdev); 6255 6256 e1000e_set_interrupt_capability(adapter); 6257 if (netif_running(netdev)) { 6258 u32 err = e1000_request_irq(adapter); 6259 6260 if (err) 6261 return err; 6262 6263 e1000e_up(adapter); 6264 } 6265 6266 netif_device_attach(netdev); 6267 6268 return 0; 6269 } 6270 6271 static int e1000e_pm_suspend(struct device *dev) 6272 { 6273 struct pci_dev *pdev = to_pci_dev(dev); 6274 6275 e1000e_pm_freeze(dev); 6276 6277 return __e1000_shutdown(pdev, false); 6278 } 6279 6280 static int e1000e_pm_resume(struct device *dev) 6281 { 6282 struct pci_dev *pdev = to_pci_dev(dev); 6283 int rc; 6284 6285 rc = __e1000_resume(pdev); 6286 if (rc) 6287 return rc; 6288 6289 return e1000e_pm_thaw(dev); 6290 } 6291 #endif /* CONFIG_PM_SLEEP */ 6292 6293 #ifdef CONFIG_PM_RUNTIME 6294 static int e1000e_pm_runtime_idle(struct device *dev) 6295 { 6296 struct pci_dev *pdev = to_pci_dev(dev); 6297 struct net_device *netdev = pci_get_drvdata(pdev); 6298 struct e1000_adapter *adapter = netdev_priv(netdev); 6299 6300 if (!e1000e_has_link(adapter)) 6301 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 6302 6303 return -EBUSY; 6304 } 6305 6306 static int e1000e_pm_runtime_resume(struct device *dev) 6307 { 6308 struct pci_dev *pdev = to_pci_dev(dev); 6309 struct net_device *netdev = pci_get_drvdata(pdev); 6310 struct e1000_adapter *adapter = netdev_priv(netdev); 6311 int rc; 6312 6313 rc = __e1000_resume(pdev); 6314 if (rc) 6315 return rc; 6316 6317 if (netdev->flags & IFF_UP) 6318 rc = e1000e_up(adapter); 6319 6320 return rc; 6321 } 6322 6323 static int e1000e_pm_runtime_suspend(struct device *dev) 6324 { 6325 struct pci_dev *pdev = to_pci_dev(dev); 6326 struct net_device *netdev = pci_get_drvdata(pdev); 6327 struct e1000_adapter *adapter = netdev_priv(netdev); 6328 6329 if (netdev->flags & IFF_UP) { 6330 int count = E1000_CHECK_RESET_COUNT; 6331 6332 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6333 usleep_range(10000, 20000); 6334 6335 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6336 6337 /* Down the device without resetting the hardware */ 6338 e1000e_down(adapter, false); 6339 } 6340 6341 if (__e1000_shutdown(pdev, true)) { 6342 e1000e_pm_runtime_resume(dev); 6343 return -EBUSY; 6344 } 6345 6346 return 0; 6347 } 6348 #endif /* CONFIG_PM_RUNTIME */ 6349 #endif /* CONFIG_PM */ 6350 6351 static void e1000_shutdown(struct pci_dev *pdev) 6352 { 6353 e1000e_pm_freeze(&pdev->dev); 6354 6355 __e1000_shutdown(pdev, false); 6356 } 6357 6358 #ifdef CONFIG_NET_POLL_CONTROLLER 6359 6360 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 6361 { 6362 struct net_device *netdev = data; 6363 struct e1000_adapter *adapter = netdev_priv(netdev); 6364 6365 if (adapter->msix_entries) { 6366 int vector, msix_irq; 6367 6368 vector = 0; 6369 msix_irq = adapter->msix_entries[vector].vector; 6370 disable_irq(msix_irq); 6371 e1000_intr_msix_rx(msix_irq, netdev); 6372 enable_irq(msix_irq); 6373 6374 vector++; 6375 msix_irq = adapter->msix_entries[vector].vector; 6376 disable_irq(msix_irq); 6377 e1000_intr_msix_tx(msix_irq, netdev); 6378 enable_irq(msix_irq); 6379 6380 vector++; 6381 msix_irq = adapter->msix_entries[vector].vector; 6382 disable_irq(msix_irq); 6383 e1000_msix_other(msix_irq, netdev); 6384 enable_irq(msix_irq); 6385 } 6386 6387 return IRQ_HANDLED; 6388 } 6389 6390 /** 6391 * e1000_netpoll 6392 * @netdev: network interface device structure 6393 * 6394 * Polling 'interrupt' - used by things like netconsole to send skbs 6395 * without having to re-enable interrupts. It's not called while 6396 * the interrupt routine is executing. 6397 */ 6398 static void e1000_netpoll(struct net_device *netdev) 6399 { 6400 struct e1000_adapter *adapter = netdev_priv(netdev); 6401 6402 switch (adapter->int_mode) { 6403 case E1000E_INT_MODE_MSIX: 6404 e1000_intr_msix(adapter->pdev->irq, netdev); 6405 break; 6406 case E1000E_INT_MODE_MSI: 6407 disable_irq(adapter->pdev->irq); 6408 e1000_intr_msi(adapter->pdev->irq, netdev); 6409 enable_irq(adapter->pdev->irq); 6410 break; 6411 default: /* E1000E_INT_MODE_LEGACY */ 6412 disable_irq(adapter->pdev->irq); 6413 e1000_intr(adapter->pdev->irq, netdev); 6414 enable_irq(adapter->pdev->irq); 6415 break; 6416 } 6417 } 6418 #endif 6419 6420 /** 6421 * e1000_io_error_detected - called when PCI error is detected 6422 * @pdev: Pointer to PCI device 6423 * @state: The current pci connection state 6424 * 6425 * This function is called after a PCI bus error affecting 6426 * this device has been detected. 6427 */ 6428 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 6429 pci_channel_state_t state) 6430 { 6431 struct net_device *netdev = pci_get_drvdata(pdev); 6432 struct e1000_adapter *adapter = netdev_priv(netdev); 6433 6434 netif_device_detach(netdev); 6435 6436 if (state == pci_channel_io_perm_failure) 6437 return PCI_ERS_RESULT_DISCONNECT; 6438 6439 if (netif_running(netdev)) 6440 e1000e_down(adapter, true); 6441 pci_disable_device(pdev); 6442 6443 /* Request a slot slot reset. */ 6444 return PCI_ERS_RESULT_NEED_RESET; 6445 } 6446 6447 /** 6448 * e1000_io_slot_reset - called after the pci bus has been reset. 6449 * @pdev: Pointer to PCI device 6450 * 6451 * Restart the card from scratch, as if from a cold-boot. Implementation 6452 * resembles the first-half of the e1000e_pm_resume routine. 6453 */ 6454 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 6455 { 6456 struct net_device *netdev = pci_get_drvdata(pdev); 6457 struct e1000_adapter *adapter = netdev_priv(netdev); 6458 struct e1000_hw *hw = &adapter->hw; 6459 u16 aspm_disable_flag = 0; 6460 int err; 6461 pci_ers_result_t result; 6462 6463 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6464 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6465 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6466 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6467 if (aspm_disable_flag) 6468 e1000e_disable_aspm(pdev, aspm_disable_flag); 6469 6470 err = pci_enable_device_mem(pdev); 6471 if (err) { 6472 dev_err(&pdev->dev, 6473 "Cannot re-enable PCI device after reset.\n"); 6474 result = PCI_ERS_RESULT_DISCONNECT; 6475 } else { 6476 pdev->state_saved = true; 6477 pci_restore_state(pdev); 6478 pci_set_master(pdev); 6479 6480 pci_enable_wake(pdev, PCI_D3hot, 0); 6481 pci_enable_wake(pdev, PCI_D3cold, 0); 6482 6483 e1000e_reset(adapter); 6484 ew32(WUS, ~0); 6485 result = PCI_ERS_RESULT_RECOVERED; 6486 } 6487 6488 pci_cleanup_aer_uncorrect_error_status(pdev); 6489 6490 return result; 6491 } 6492 6493 /** 6494 * e1000_io_resume - called when traffic can start flowing again. 6495 * @pdev: Pointer to PCI device 6496 * 6497 * This callback is called when the error recovery driver tells us that 6498 * its OK to resume normal operation. Implementation resembles the 6499 * second-half of the e1000e_pm_resume routine. 6500 */ 6501 static void e1000_io_resume(struct pci_dev *pdev) 6502 { 6503 struct net_device *netdev = pci_get_drvdata(pdev); 6504 struct e1000_adapter *adapter = netdev_priv(netdev); 6505 6506 e1000_init_manageability_pt(adapter); 6507 6508 if (netif_running(netdev)) { 6509 if (e1000e_up(adapter)) { 6510 dev_err(&pdev->dev, 6511 "can't bring device back up after reset\n"); 6512 return; 6513 } 6514 } 6515 6516 netif_device_attach(netdev); 6517 6518 /* If the controller has AMT, do not set DRV_LOAD until the interface 6519 * is up. For all other cases, let the f/w know that the h/w is now 6520 * under the control of the driver. 6521 */ 6522 if (!(adapter->flags & FLAG_HAS_AMT)) 6523 e1000e_get_hw_control(adapter); 6524 } 6525 6526 static void e1000_print_device_info(struct e1000_adapter *adapter) 6527 { 6528 struct e1000_hw *hw = &adapter->hw; 6529 struct net_device *netdev = adapter->netdev; 6530 u32 ret_val; 6531 u8 pba_str[E1000_PBANUM_LENGTH]; 6532 6533 /* print bus type/speed/width info */ 6534 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 6535 /* bus width */ 6536 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 6537 "Width x1"), 6538 /* MAC address */ 6539 netdev->dev_addr); 6540 e_info("Intel(R) PRO/%s Network Connection\n", 6541 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 6542 ret_val = e1000_read_pba_string_generic(hw, pba_str, 6543 E1000_PBANUM_LENGTH); 6544 if (ret_val) 6545 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 6546 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 6547 hw->mac.type, hw->phy.type, pba_str); 6548 } 6549 6550 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 6551 { 6552 struct e1000_hw *hw = &adapter->hw; 6553 int ret_val; 6554 u16 buf = 0; 6555 6556 if (hw->mac.type != e1000_82573) 6557 return; 6558 6559 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 6560 le16_to_cpus(&buf); 6561 if (!ret_val && (!(buf & (1 << 0)))) { 6562 /* Deep Smart Power Down (DSPD) */ 6563 dev_warn(&adapter->pdev->dev, 6564 "Warning: detected DSPD enabled in EEPROM\n"); 6565 } 6566 } 6567 6568 static int e1000_set_features(struct net_device *netdev, 6569 netdev_features_t features) 6570 { 6571 struct e1000_adapter *adapter = netdev_priv(netdev); 6572 netdev_features_t changed = features ^ netdev->features; 6573 6574 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 6575 adapter->flags |= FLAG_TSO_FORCE; 6576 6577 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 6578 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 6579 NETIF_F_RXALL))) 6580 return 0; 6581 6582 if (changed & NETIF_F_RXFCS) { 6583 if (features & NETIF_F_RXFCS) { 6584 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 6585 } else { 6586 /* We need to take it back to defaults, which might mean 6587 * stripping is still disabled at the adapter level. 6588 */ 6589 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 6590 adapter->flags2 |= FLAG2_CRC_STRIPPING; 6591 else 6592 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 6593 } 6594 } 6595 6596 netdev->features = features; 6597 6598 if (netif_running(netdev)) 6599 e1000e_reinit_locked(adapter); 6600 else 6601 e1000e_reset(adapter); 6602 6603 return 0; 6604 } 6605 6606 static const struct net_device_ops e1000e_netdev_ops = { 6607 .ndo_open = e1000_open, 6608 .ndo_stop = e1000_close, 6609 .ndo_start_xmit = e1000_xmit_frame, 6610 .ndo_get_stats64 = e1000e_get_stats64, 6611 .ndo_set_rx_mode = e1000e_set_rx_mode, 6612 .ndo_set_mac_address = e1000_set_mac, 6613 .ndo_change_mtu = e1000_change_mtu, 6614 .ndo_do_ioctl = e1000_ioctl, 6615 .ndo_tx_timeout = e1000_tx_timeout, 6616 .ndo_validate_addr = eth_validate_addr, 6617 6618 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 6619 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 6620 #ifdef CONFIG_NET_POLL_CONTROLLER 6621 .ndo_poll_controller = e1000_netpoll, 6622 #endif 6623 .ndo_set_features = e1000_set_features, 6624 }; 6625 6626 /** 6627 * e1000_probe - Device Initialization Routine 6628 * @pdev: PCI device information struct 6629 * @ent: entry in e1000_pci_tbl 6630 * 6631 * Returns 0 on success, negative on failure 6632 * 6633 * e1000_probe initializes an adapter identified by a pci_dev structure. 6634 * The OS initialization, configuring of the adapter private structure, 6635 * and a hardware reset occur. 6636 **/ 6637 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 6638 { 6639 struct net_device *netdev; 6640 struct e1000_adapter *adapter; 6641 struct e1000_hw *hw; 6642 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 6643 resource_size_t mmio_start, mmio_len; 6644 resource_size_t flash_start, flash_len; 6645 static int cards_found; 6646 u16 aspm_disable_flag = 0; 6647 int bars, i, err, pci_using_dac; 6648 u16 eeprom_data = 0; 6649 u16 eeprom_apme_mask = E1000_EEPROM_APME; 6650 6651 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 6652 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6653 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 6654 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6655 if (aspm_disable_flag) 6656 e1000e_disable_aspm(pdev, aspm_disable_flag); 6657 6658 err = pci_enable_device_mem(pdev); 6659 if (err) 6660 return err; 6661 6662 pci_using_dac = 0; 6663 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 6664 if (!err) { 6665 pci_using_dac = 1; 6666 } else { 6667 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 6668 if (err) { 6669 dev_err(&pdev->dev, 6670 "No usable DMA configuration, aborting\n"); 6671 goto err_dma; 6672 } 6673 } 6674 6675 bars = pci_select_bars(pdev, IORESOURCE_MEM); 6676 err = pci_request_selected_regions_exclusive(pdev, bars, 6677 e1000e_driver_name); 6678 if (err) 6679 goto err_pci_reg; 6680 6681 /* AER (Advanced Error Reporting) hooks */ 6682 pci_enable_pcie_error_reporting(pdev); 6683 6684 pci_set_master(pdev); 6685 /* PCI config space info */ 6686 err = pci_save_state(pdev); 6687 if (err) 6688 goto err_alloc_etherdev; 6689 6690 err = -ENOMEM; 6691 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 6692 if (!netdev) 6693 goto err_alloc_etherdev; 6694 6695 SET_NETDEV_DEV(netdev, &pdev->dev); 6696 6697 netdev->irq = pdev->irq; 6698 6699 pci_set_drvdata(pdev, netdev); 6700 adapter = netdev_priv(netdev); 6701 hw = &adapter->hw; 6702 adapter->netdev = netdev; 6703 adapter->pdev = pdev; 6704 adapter->ei = ei; 6705 adapter->pba = ei->pba; 6706 adapter->flags = ei->flags; 6707 adapter->flags2 = ei->flags2; 6708 adapter->hw.adapter = adapter; 6709 adapter->hw.mac.type = ei->mac; 6710 adapter->max_hw_frame_size = ei->max_hw_frame_size; 6711 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 6712 6713 mmio_start = pci_resource_start(pdev, 0); 6714 mmio_len = pci_resource_len(pdev, 0); 6715 6716 err = -EIO; 6717 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 6718 if (!adapter->hw.hw_addr) 6719 goto err_ioremap; 6720 6721 if ((adapter->flags & FLAG_HAS_FLASH) && 6722 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { 6723 flash_start = pci_resource_start(pdev, 1); 6724 flash_len = pci_resource_len(pdev, 1); 6725 adapter->hw.flash_address = ioremap(flash_start, flash_len); 6726 if (!adapter->hw.flash_address) 6727 goto err_flashmap; 6728 } 6729 6730 /* Set default EEE advertisement */ 6731 if (adapter->flags2 & FLAG2_HAS_EEE) 6732 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 6733 6734 /* construct the net_device struct */ 6735 netdev->netdev_ops = &e1000e_netdev_ops; 6736 e1000e_set_ethtool_ops(netdev); 6737 netdev->watchdog_timeo = 5 * HZ; 6738 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 6739 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 6740 6741 netdev->mem_start = mmio_start; 6742 netdev->mem_end = mmio_start + mmio_len; 6743 6744 adapter->bd_number = cards_found++; 6745 6746 e1000e_check_options(adapter); 6747 6748 /* setup adapter struct */ 6749 err = e1000_sw_init(adapter); 6750 if (err) 6751 goto err_sw_init; 6752 6753 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 6754 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 6755 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 6756 6757 err = ei->get_variants(adapter); 6758 if (err) 6759 goto err_hw_init; 6760 6761 if ((adapter->flags & FLAG_IS_ICH) && 6762 (adapter->flags & FLAG_READ_ONLY_NVM)) 6763 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 6764 6765 hw->mac.ops.get_bus_info(&adapter->hw); 6766 6767 adapter->hw.phy.autoneg_wait_to_complete = 0; 6768 6769 /* Copper options */ 6770 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 6771 adapter->hw.phy.mdix = AUTO_ALL_MODES; 6772 adapter->hw.phy.disable_polarity_correction = 0; 6773 adapter->hw.phy.ms_type = e1000_ms_hw_default; 6774 } 6775 6776 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 6777 dev_info(&pdev->dev, 6778 "PHY reset is blocked due to SOL/IDER session.\n"); 6779 6780 /* Set initial default active device features */ 6781 netdev->features = (NETIF_F_SG | 6782 NETIF_F_HW_VLAN_CTAG_RX | 6783 NETIF_F_HW_VLAN_CTAG_TX | 6784 NETIF_F_TSO | 6785 NETIF_F_TSO6 | 6786 NETIF_F_RXHASH | 6787 NETIF_F_RXCSUM | 6788 NETIF_F_HW_CSUM); 6789 6790 /* Set user-changeable features (subset of all device features) */ 6791 netdev->hw_features = netdev->features; 6792 netdev->hw_features |= NETIF_F_RXFCS; 6793 netdev->priv_flags |= IFF_SUPP_NOFCS; 6794 netdev->hw_features |= NETIF_F_RXALL; 6795 6796 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 6797 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 6798 6799 netdev->vlan_features |= (NETIF_F_SG | 6800 NETIF_F_TSO | 6801 NETIF_F_TSO6 | 6802 NETIF_F_HW_CSUM); 6803 6804 netdev->priv_flags |= IFF_UNICAST_FLT; 6805 6806 if (pci_using_dac) { 6807 netdev->features |= NETIF_F_HIGHDMA; 6808 netdev->vlan_features |= NETIF_F_HIGHDMA; 6809 } 6810 6811 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 6812 adapter->flags |= FLAG_MNG_PT_ENABLED; 6813 6814 /* before reading the NVM, reset the controller to 6815 * put the device in a known good starting state 6816 */ 6817 adapter->hw.mac.ops.reset_hw(&adapter->hw); 6818 6819 /* systems with ASPM and others may see the checksum fail on the first 6820 * attempt. Let's give it a few tries 6821 */ 6822 for (i = 0;; i++) { 6823 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 6824 break; 6825 if (i == 2) { 6826 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 6827 err = -EIO; 6828 goto err_eeprom; 6829 } 6830 } 6831 6832 e1000_eeprom_checks(adapter); 6833 6834 /* copy the MAC address */ 6835 if (e1000e_read_mac_addr(&adapter->hw)) 6836 dev_err(&pdev->dev, 6837 "NVM Read Error while reading MAC address\n"); 6838 6839 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 6840 6841 if (!is_valid_ether_addr(netdev->dev_addr)) { 6842 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 6843 netdev->dev_addr); 6844 err = -EIO; 6845 goto err_eeprom; 6846 } 6847 6848 init_timer(&adapter->watchdog_timer); 6849 adapter->watchdog_timer.function = e1000_watchdog; 6850 adapter->watchdog_timer.data = (unsigned long)adapter; 6851 6852 init_timer(&adapter->phy_info_timer); 6853 adapter->phy_info_timer.function = e1000_update_phy_info; 6854 adapter->phy_info_timer.data = (unsigned long)adapter; 6855 6856 INIT_WORK(&adapter->reset_task, e1000_reset_task); 6857 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 6858 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 6859 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 6860 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 6861 6862 /* Initialize link parameters. User can change them with ethtool */ 6863 adapter->hw.mac.autoneg = 1; 6864 adapter->fc_autoneg = true; 6865 adapter->hw.fc.requested_mode = e1000_fc_default; 6866 adapter->hw.fc.current_mode = e1000_fc_default; 6867 adapter->hw.phy.autoneg_advertised = 0x2f; 6868 6869 /* Initial Wake on LAN setting - If APM wake is enabled in 6870 * the EEPROM, enable the ACPI Magic Packet filter 6871 */ 6872 if (adapter->flags & FLAG_APME_IN_WUC) { 6873 /* APME bit in EEPROM is mapped to WUC.APME */ 6874 eeprom_data = er32(WUC); 6875 eeprom_apme_mask = E1000_WUC_APME; 6876 if ((hw->mac.type > e1000_ich10lan) && 6877 (eeprom_data & E1000_WUC_PHY_WAKE)) 6878 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 6879 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 6880 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 6881 (adapter->hw.bus.func == 1)) 6882 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B, 6883 1, &eeprom_data); 6884 else 6885 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A, 6886 1, &eeprom_data); 6887 } 6888 6889 /* fetch WoL from EEPROM */ 6890 if (eeprom_data & eeprom_apme_mask) 6891 adapter->eeprom_wol |= E1000_WUFC_MAG; 6892 6893 /* now that we have the eeprom settings, apply the special cases 6894 * where the eeprom may be wrong or the board simply won't support 6895 * wake on lan on a particular port 6896 */ 6897 if (!(adapter->flags & FLAG_HAS_WOL)) 6898 adapter->eeprom_wol = 0; 6899 6900 /* initialize the wol settings based on the eeprom settings */ 6901 adapter->wol = adapter->eeprom_wol; 6902 6903 /* make sure adapter isn't asleep if manageability is enabled */ 6904 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 6905 (hw->mac.ops.check_mng_mode(hw))) 6906 device_wakeup_enable(&pdev->dev); 6907 6908 /* save off EEPROM version number */ 6909 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 6910 6911 /* reset the hardware with the new settings */ 6912 e1000e_reset(adapter); 6913 6914 /* If the controller has AMT, do not set DRV_LOAD until the interface 6915 * is up. For all other cases, let the f/w know that the h/w is now 6916 * under the control of the driver. 6917 */ 6918 if (!(adapter->flags & FLAG_HAS_AMT)) 6919 e1000e_get_hw_control(adapter); 6920 6921 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 6922 err = register_netdev(netdev); 6923 if (err) 6924 goto err_register; 6925 6926 /* carrier off reporting is important to ethtool even BEFORE open */ 6927 netif_carrier_off(netdev); 6928 6929 /* init PTP hardware clock */ 6930 e1000e_ptp_init(adapter); 6931 6932 e1000_print_device_info(adapter); 6933 6934 if (pci_dev_run_wake(pdev)) 6935 pm_runtime_put_noidle(&pdev->dev); 6936 6937 return 0; 6938 6939 err_register: 6940 if (!(adapter->flags & FLAG_HAS_AMT)) 6941 e1000e_release_hw_control(adapter); 6942 err_eeprom: 6943 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 6944 e1000_phy_hw_reset(&adapter->hw); 6945 err_hw_init: 6946 kfree(adapter->tx_ring); 6947 kfree(adapter->rx_ring); 6948 err_sw_init: 6949 if (adapter->hw.flash_address) 6950 iounmap(adapter->hw.flash_address); 6951 e1000e_reset_interrupt_capability(adapter); 6952 err_flashmap: 6953 iounmap(adapter->hw.hw_addr); 6954 err_ioremap: 6955 free_netdev(netdev); 6956 err_alloc_etherdev: 6957 pci_release_selected_regions(pdev, 6958 pci_select_bars(pdev, IORESOURCE_MEM)); 6959 err_pci_reg: 6960 err_dma: 6961 pci_disable_device(pdev); 6962 return err; 6963 } 6964 6965 /** 6966 * e1000_remove - Device Removal Routine 6967 * @pdev: PCI device information struct 6968 * 6969 * e1000_remove is called by the PCI subsystem to alert the driver 6970 * that it should release a PCI device. The could be caused by a 6971 * Hot-Plug event, or because the driver is going to be removed from 6972 * memory. 6973 **/ 6974 static void e1000_remove(struct pci_dev *pdev) 6975 { 6976 struct net_device *netdev = pci_get_drvdata(pdev); 6977 struct e1000_adapter *adapter = netdev_priv(netdev); 6978 bool down = test_bit(__E1000_DOWN, &adapter->state); 6979 6980 e1000e_ptp_remove(adapter); 6981 6982 /* The timers may be rescheduled, so explicitly disable them 6983 * from being rescheduled. 6984 */ 6985 if (!down) 6986 set_bit(__E1000_DOWN, &adapter->state); 6987 del_timer_sync(&adapter->watchdog_timer); 6988 del_timer_sync(&adapter->phy_info_timer); 6989 6990 cancel_work_sync(&adapter->reset_task); 6991 cancel_work_sync(&adapter->watchdog_task); 6992 cancel_work_sync(&adapter->downshift_task); 6993 cancel_work_sync(&adapter->update_phy_task); 6994 cancel_work_sync(&adapter->print_hang_task); 6995 6996 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 6997 cancel_work_sync(&adapter->tx_hwtstamp_work); 6998 if (adapter->tx_hwtstamp_skb) { 6999 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 7000 adapter->tx_hwtstamp_skb = NULL; 7001 } 7002 } 7003 7004 /* Don't lie to e1000_close() down the road. */ 7005 if (!down) 7006 clear_bit(__E1000_DOWN, &adapter->state); 7007 unregister_netdev(netdev); 7008 7009 if (pci_dev_run_wake(pdev)) 7010 pm_runtime_get_noresume(&pdev->dev); 7011 7012 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7013 * would have already happened in close and is redundant. 7014 */ 7015 e1000e_release_hw_control(adapter); 7016 7017 e1000e_reset_interrupt_capability(adapter); 7018 kfree(adapter->tx_ring); 7019 kfree(adapter->rx_ring); 7020 7021 iounmap(adapter->hw.hw_addr); 7022 if (adapter->hw.flash_address) 7023 iounmap(adapter->hw.flash_address); 7024 pci_release_selected_regions(pdev, 7025 pci_select_bars(pdev, IORESOURCE_MEM)); 7026 7027 free_netdev(netdev); 7028 7029 /* AER disable */ 7030 pci_disable_pcie_error_reporting(pdev); 7031 7032 pci_disable_device(pdev); 7033 } 7034 7035 /* PCI Error Recovery (ERS) */ 7036 static const struct pci_error_handlers e1000_err_handler = { 7037 .error_detected = e1000_io_error_detected, 7038 .slot_reset = e1000_io_slot_reset, 7039 .resume = e1000_io_resume, 7040 }; 7041 7042 static const struct pci_device_id e1000_pci_tbl[] = { 7043 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7044 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7045 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7046 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7047 board_82571 }, 7048 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7049 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7050 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7051 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7052 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7053 7054 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7055 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7056 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7057 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7058 7059 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7060 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7061 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7062 7063 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7064 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7065 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7066 7067 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7068 board_80003es2lan }, 7069 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7070 board_80003es2lan }, 7071 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7072 board_80003es2lan }, 7073 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7074 board_80003es2lan }, 7075 7076 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7077 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7078 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7079 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7080 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7081 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7082 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7083 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7084 7085 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7086 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7087 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7088 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7089 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7090 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7091 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7092 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7093 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7094 7095 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7096 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7097 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7098 7099 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7102 7103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7107 7108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7110 7111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7115 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7116 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7117 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7118 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7119 7120 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7121 }; 7122 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7123 7124 static const struct dev_pm_ops e1000_pm_ops = { 7125 #ifdef CONFIG_PM_SLEEP 7126 .suspend = e1000e_pm_suspend, 7127 .resume = e1000e_pm_resume, 7128 .freeze = e1000e_pm_freeze, 7129 .thaw = e1000e_pm_thaw, 7130 .poweroff = e1000e_pm_suspend, 7131 .restore = e1000e_pm_resume, 7132 #endif 7133 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7134 e1000e_pm_runtime_idle) 7135 }; 7136 7137 /* PCI Device API Driver */ 7138 static struct pci_driver e1000_driver = { 7139 .name = e1000e_driver_name, 7140 .id_table = e1000_pci_tbl, 7141 .probe = e1000_probe, 7142 .remove = e1000_remove, 7143 .driver = { 7144 .pm = &e1000_pm_ops, 7145 }, 7146 .shutdown = e1000_shutdown, 7147 .err_handler = &e1000_err_handler 7148 }; 7149 7150 /** 7151 * e1000_init_module - Driver Registration Routine 7152 * 7153 * e1000_init_module is the first routine called when the driver is 7154 * loaded. All it does is register with the PCI subsystem. 7155 **/ 7156 static int __init e1000_init_module(void) 7157 { 7158 int ret; 7159 7160 pr_info("Intel(R) PRO/1000 Network Driver - %s\n", 7161 e1000e_driver_version); 7162 pr_info("Copyright(c) 1999 - 2014 Intel Corporation.\n"); 7163 ret = pci_register_driver(&e1000_driver); 7164 7165 return ret; 7166 } 7167 module_init(e1000_init_module); 7168 7169 /** 7170 * e1000_exit_module - Driver Exit Cleanup Routine 7171 * 7172 * e1000_exit_module is called just before the driver is removed 7173 * from memory. 7174 **/ 7175 static void __exit e1000_exit_module(void) 7176 { 7177 pci_unregister_driver(&e1000_driver); 7178 } 7179 module_exit(e1000_exit_module); 7180 7181 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7182 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7183 MODULE_LICENSE("GPL"); 7184 MODULE_VERSION(DRV_VERSION); 7185 7186 /* netdev.c */ 7187