1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/aer.h> 27 #include <linux/prefetch.h> 28 29 #include "e1000.h" 30 31 #define DRV_EXTRAVERSION "-k" 32 33 #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION 34 char e1000e_driver_name[] = "e1000e"; 35 const char e1000e_driver_version[] = DRV_VERSION; 36 37 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 38 static int debug = -1; 39 module_param(debug, int, 0); 40 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 41 42 static const struct e1000_info *e1000_info_tbl[] = { 43 [board_82571] = &e1000_82571_info, 44 [board_82572] = &e1000_82572_info, 45 [board_82573] = &e1000_82573_info, 46 [board_82574] = &e1000_82574_info, 47 [board_82583] = &e1000_82583_info, 48 [board_80003es2lan] = &e1000_es2_info, 49 [board_ich8lan] = &e1000_ich8_info, 50 [board_ich9lan] = &e1000_ich9_info, 51 [board_ich10lan] = &e1000_ich10_info, 52 [board_pchlan] = &e1000_pch_info, 53 [board_pch2lan] = &e1000_pch2_info, 54 [board_pch_lpt] = &e1000_pch_lpt_info, 55 [board_pch_spt] = &e1000_pch_spt_info, 56 [board_pch_cnp] = &e1000_pch_cnp_info, 57 }; 58 59 struct e1000_reg_info { 60 u32 ofs; 61 char *name; 62 }; 63 64 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 65 /* General Registers */ 66 {E1000_CTRL, "CTRL"}, 67 {E1000_STATUS, "STATUS"}, 68 {E1000_CTRL_EXT, "CTRL_EXT"}, 69 70 /* Interrupt Registers */ 71 {E1000_ICR, "ICR"}, 72 73 /* Rx Registers */ 74 {E1000_RCTL, "RCTL"}, 75 {E1000_RDLEN(0), "RDLEN"}, 76 {E1000_RDH(0), "RDH"}, 77 {E1000_RDT(0), "RDT"}, 78 {E1000_RDTR, "RDTR"}, 79 {E1000_RXDCTL(0), "RXDCTL"}, 80 {E1000_ERT, "ERT"}, 81 {E1000_RDBAL(0), "RDBAL"}, 82 {E1000_RDBAH(0), "RDBAH"}, 83 {E1000_RDFH, "RDFH"}, 84 {E1000_RDFT, "RDFT"}, 85 {E1000_RDFHS, "RDFHS"}, 86 {E1000_RDFTS, "RDFTS"}, 87 {E1000_RDFPC, "RDFPC"}, 88 89 /* Tx Registers */ 90 {E1000_TCTL, "TCTL"}, 91 {E1000_TDBAL(0), "TDBAL"}, 92 {E1000_TDBAH(0), "TDBAH"}, 93 {E1000_TDLEN(0), "TDLEN"}, 94 {E1000_TDH(0), "TDH"}, 95 {E1000_TDT(0), "TDT"}, 96 {E1000_TIDV, "TIDV"}, 97 {E1000_TXDCTL(0), "TXDCTL"}, 98 {E1000_TADV, "TADV"}, 99 {E1000_TARC(0), "TARC"}, 100 {E1000_TDFH, "TDFH"}, 101 {E1000_TDFT, "TDFT"}, 102 {E1000_TDFHS, "TDFHS"}, 103 {E1000_TDFTS, "TDFTS"}, 104 {E1000_TDFPC, "TDFPC"}, 105 106 /* List Terminator */ 107 {0, NULL} 108 }; 109 110 /** 111 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 112 * @hw: pointer to the HW structure 113 * 114 * When updating the MAC CSR registers, the Manageability Engine (ME) could 115 * be accessing the registers at the same time. Normally, this is handled in 116 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 117 * accesses later than it should which could result in the register to have 118 * an incorrect value. Workaround this by checking the FWSM register which 119 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 120 * and try again a number of times. 121 **/ 122 s32 __ew32_prepare(struct e1000_hw *hw) 123 { 124 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 125 126 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 127 udelay(50); 128 129 return i; 130 } 131 132 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 133 { 134 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 135 __ew32_prepare(hw); 136 137 writel(val, hw->hw_addr + reg); 138 } 139 140 /** 141 * e1000_regdump - register printout routine 142 * @hw: pointer to the HW structure 143 * @reginfo: pointer to the register info table 144 **/ 145 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 146 { 147 int n = 0; 148 char rname[16]; 149 u32 regs[8]; 150 151 switch (reginfo->ofs) { 152 case E1000_RXDCTL(0): 153 for (n = 0; n < 2; n++) 154 regs[n] = __er32(hw, E1000_RXDCTL(n)); 155 break; 156 case E1000_TXDCTL(0): 157 for (n = 0; n < 2; n++) 158 regs[n] = __er32(hw, E1000_TXDCTL(n)); 159 break; 160 case E1000_TARC(0): 161 for (n = 0; n < 2; n++) 162 regs[n] = __er32(hw, E1000_TARC(n)); 163 break; 164 default: 165 pr_info("%-15s %08x\n", 166 reginfo->name, __er32(hw, reginfo->ofs)); 167 return; 168 } 169 170 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 171 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 172 } 173 174 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 175 struct e1000_buffer *bi) 176 { 177 int i; 178 struct e1000_ps_page *ps_page; 179 180 for (i = 0; i < adapter->rx_ps_pages; i++) { 181 ps_page = &bi->ps_pages[i]; 182 183 if (ps_page->page) { 184 pr_info("packet dump for ps_page %d:\n", i); 185 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 186 16, 1, page_address(ps_page->page), 187 PAGE_SIZE, true); 188 } 189 } 190 } 191 192 /** 193 * e1000e_dump - Print registers, Tx-ring and Rx-ring 194 * @adapter: board private structure 195 **/ 196 static void e1000e_dump(struct e1000_adapter *adapter) 197 { 198 struct net_device *netdev = adapter->netdev; 199 struct e1000_hw *hw = &adapter->hw; 200 struct e1000_reg_info *reginfo; 201 struct e1000_ring *tx_ring = adapter->tx_ring; 202 struct e1000_tx_desc *tx_desc; 203 struct my_u0 { 204 __le64 a; 205 __le64 b; 206 } *u0; 207 struct e1000_buffer *buffer_info; 208 struct e1000_ring *rx_ring = adapter->rx_ring; 209 union e1000_rx_desc_packet_split *rx_desc_ps; 210 union e1000_rx_desc_extended *rx_desc; 211 struct my_u1 { 212 __le64 a; 213 __le64 b; 214 __le64 c; 215 __le64 d; 216 } *u1; 217 u32 staterr; 218 int i = 0; 219 220 if (!netif_msg_hw(adapter)) 221 return; 222 223 /* Print netdevice Info */ 224 if (netdev) { 225 dev_info(&adapter->pdev->dev, "Net device Info\n"); 226 pr_info("Device Name state trans_start\n"); 227 pr_info("%-15s %016lX %016lX\n", netdev->name, 228 netdev->state, dev_trans_start(netdev)); 229 } 230 231 /* Print Registers */ 232 dev_info(&adapter->pdev->dev, "Register Dump\n"); 233 pr_info(" Register Name Value\n"); 234 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 235 reginfo->name; reginfo++) { 236 e1000_regdump(hw, reginfo); 237 } 238 239 /* Print Tx Ring Summary */ 240 if (!netdev || !netif_running(netdev)) 241 return; 242 243 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 244 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 245 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 246 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 247 0, tx_ring->next_to_use, tx_ring->next_to_clean, 248 (unsigned long long)buffer_info->dma, 249 buffer_info->length, 250 buffer_info->next_to_watch, 251 (unsigned long long)buffer_info->time_stamp); 252 253 /* Print Tx Ring */ 254 if (!netif_msg_tx_done(adapter)) 255 goto rx_ring_summary; 256 257 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 258 259 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 260 * 261 * Legacy Transmit Descriptor 262 * +--------------------------------------------------------------+ 263 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 264 * +--------------------------------------------------------------+ 265 * 8 | Special | CSS | Status | CMD | CSO | Length | 266 * +--------------------------------------------------------------+ 267 * 63 48 47 36 35 32 31 24 23 16 15 0 268 * 269 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 270 * 63 48 47 40 39 32 31 16 15 8 7 0 271 * +----------------------------------------------------------------+ 272 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 273 * +----------------------------------------------------------------+ 274 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 275 * +----------------------------------------------------------------+ 276 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 277 * 278 * Extended Data Descriptor (DTYP=0x1) 279 * +----------------------------------------------------------------+ 280 * 0 | Buffer Address [63:0] | 281 * +----------------------------------------------------------------+ 282 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 283 * +----------------------------------------------------------------+ 284 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 285 */ 286 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 287 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 288 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 289 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 290 const char *next_desc; 291 tx_desc = E1000_TX_DESC(*tx_ring, i); 292 buffer_info = &tx_ring->buffer_info[i]; 293 u0 = (struct my_u0 *)tx_desc; 294 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 295 next_desc = " NTC/U"; 296 else if (i == tx_ring->next_to_use) 297 next_desc = " NTU"; 298 else if (i == tx_ring->next_to_clean) 299 next_desc = " NTC"; 300 else 301 next_desc = ""; 302 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 303 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 304 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 305 i, 306 (unsigned long long)le64_to_cpu(u0->a), 307 (unsigned long long)le64_to_cpu(u0->b), 308 (unsigned long long)buffer_info->dma, 309 buffer_info->length, buffer_info->next_to_watch, 310 (unsigned long long)buffer_info->time_stamp, 311 buffer_info->skb, next_desc); 312 313 if (netif_msg_pktdata(adapter) && buffer_info->skb) 314 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 315 16, 1, buffer_info->skb->data, 316 buffer_info->skb->len, true); 317 } 318 319 /* Print Rx Ring Summary */ 320 rx_ring_summary: 321 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 322 pr_info("Queue [NTU] [NTC]\n"); 323 pr_info(" %5d %5X %5X\n", 324 0, rx_ring->next_to_use, rx_ring->next_to_clean); 325 326 /* Print Rx Ring */ 327 if (!netif_msg_rx_status(adapter)) 328 return; 329 330 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 331 switch (adapter->rx_ps_pages) { 332 case 1: 333 case 2: 334 case 3: 335 /* [Extended] Packet Split Receive Descriptor Format 336 * 337 * +-----------------------------------------------------+ 338 * 0 | Buffer Address 0 [63:0] | 339 * +-----------------------------------------------------+ 340 * 8 | Buffer Address 1 [63:0] | 341 * +-----------------------------------------------------+ 342 * 16 | Buffer Address 2 [63:0] | 343 * +-----------------------------------------------------+ 344 * 24 | Buffer Address 3 [63:0] | 345 * +-----------------------------------------------------+ 346 */ 347 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 348 /* [Extended] Receive Descriptor (Write-Back) Format 349 * 350 * 63 48 47 32 31 13 12 8 7 4 3 0 351 * +------------------------------------------------------+ 352 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 353 * | Checksum | Ident | | Queue | | Type | 354 * +------------------------------------------------------+ 355 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 356 * +------------------------------------------------------+ 357 * 63 48 47 32 31 20 19 0 358 */ 359 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 360 for (i = 0; i < rx_ring->count; i++) { 361 const char *next_desc; 362 buffer_info = &rx_ring->buffer_info[i]; 363 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 364 u1 = (struct my_u1 *)rx_desc_ps; 365 staterr = 366 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 367 368 if (i == rx_ring->next_to_use) 369 next_desc = " NTU"; 370 else if (i == rx_ring->next_to_clean) 371 next_desc = " NTC"; 372 else 373 next_desc = ""; 374 375 if (staterr & E1000_RXD_STAT_DD) { 376 /* Descriptor Done */ 377 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 378 "RWB", i, 379 (unsigned long long)le64_to_cpu(u1->a), 380 (unsigned long long)le64_to_cpu(u1->b), 381 (unsigned long long)le64_to_cpu(u1->c), 382 (unsigned long long)le64_to_cpu(u1->d), 383 buffer_info->skb, next_desc); 384 } else { 385 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 386 "R ", i, 387 (unsigned long long)le64_to_cpu(u1->a), 388 (unsigned long long)le64_to_cpu(u1->b), 389 (unsigned long long)le64_to_cpu(u1->c), 390 (unsigned long long)le64_to_cpu(u1->d), 391 (unsigned long long)buffer_info->dma, 392 buffer_info->skb, next_desc); 393 394 if (netif_msg_pktdata(adapter)) 395 e1000e_dump_ps_pages(adapter, 396 buffer_info); 397 } 398 } 399 break; 400 default: 401 case 0: 402 /* Extended Receive Descriptor (Read) Format 403 * 404 * +-----------------------------------------------------+ 405 * 0 | Buffer Address [63:0] | 406 * +-----------------------------------------------------+ 407 * 8 | Reserved | 408 * +-----------------------------------------------------+ 409 */ 410 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 411 /* Extended Receive Descriptor (Write-Back) Format 412 * 413 * 63 48 47 32 31 24 23 4 3 0 414 * +------------------------------------------------------+ 415 * | RSS Hash | | | | 416 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 417 * | Packet | IP | | | Type | 418 * | Checksum | Ident | | | | 419 * +------------------------------------------------------+ 420 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 421 * +------------------------------------------------------+ 422 * 63 48 47 32 31 20 19 0 423 */ 424 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 425 426 for (i = 0; i < rx_ring->count; i++) { 427 const char *next_desc; 428 429 buffer_info = &rx_ring->buffer_info[i]; 430 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 431 u1 = (struct my_u1 *)rx_desc; 432 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 433 434 if (i == rx_ring->next_to_use) 435 next_desc = " NTU"; 436 else if (i == rx_ring->next_to_clean) 437 next_desc = " NTC"; 438 else 439 next_desc = ""; 440 441 if (staterr & E1000_RXD_STAT_DD) { 442 /* Descriptor Done */ 443 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 444 "RWB", i, 445 (unsigned long long)le64_to_cpu(u1->a), 446 (unsigned long long)le64_to_cpu(u1->b), 447 buffer_info->skb, next_desc); 448 } else { 449 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 450 "R ", i, 451 (unsigned long long)le64_to_cpu(u1->a), 452 (unsigned long long)le64_to_cpu(u1->b), 453 (unsigned long long)buffer_info->dma, 454 buffer_info->skb, next_desc); 455 456 if (netif_msg_pktdata(adapter) && 457 buffer_info->skb) 458 print_hex_dump(KERN_INFO, "", 459 DUMP_PREFIX_ADDRESS, 16, 460 1, 461 buffer_info->skb->data, 462 adapter->rx_buffer_len, 463 true); 464 } 465 } 466 } 467 } 468 469 /** 470 * e1000_desc_unused - calculate if we have unused descriptors 471 **/ 472 static int e1000_desc_unused(struct e1000_ring *ring) 473 { 474 if (ring->next_to_clean > ring->next_to_use) 475 return ring->next_to_clean - ring->next_to_use - 1; 476 477 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 478 } 479 480 /** 481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 482 * @adapter: board private structure 483 * @hwtstamps: time stamp structure to update 484 * @systim: unsigned 64bit system time value. 485 * 486 * Convert the system time value stored in the RX/TXSTMP registers into a 487 * hwtstamp which can be used by the upper level time stamping functions. 488 * 489 * The 'systim_lock' spinlock is used to protect the consistency of the 490 * system time value. This is needed because reading the 64 bit time 491 * value involves reading two 32 bit registers. The first read latches the 492 * value. 493 **/ 494 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 495 struct skb_shared_hwtstamps *hwtstamps, 496 u64 systim) 497 { 498 u64 ns; 499 unsigned long flags; 500 501 spin_lock_irqsave(&adapter->systim_lock, flags); 502 ns = timecounter_cyc2time(&adapter->tc, systim); 503 spin_unlock_irqrestore(&adapter->systim_lock, flags); 504 505 memset(hwtstamps, 0, sizeof(*hwtstamps)); 506 hwtstamps->hwtstamp = ns_to_ktime(ns); 507 } 508 509 /** 510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 511 * @adapter: board private structure 512 * @status: descriptor extended error and status field 513 * @skb: particular skb to include time stamp 514 * 515 * If the time stamp is valid, convert it into the timecounter ns value 516 * and store that result into the shhwtstamps structure which is passed 517 * up the network stack. 518 **/ 519 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 520 struct sk_buff *skb) 521 { 522 struct e1000_hw *hw = &adapter->hw; 523 u64 rxstmp; 524 525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 526 !(status & E1000_RXDEXT_STATERR_TST) || 527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 528 return; 529 530 /* The Rx time stamp registers contain the time stamp. No other 531 * received packet will be time stamped until the Rx time stamp 532 * registers are read. Because only one packet can be time stamped 533 * at a time, the register values must belong to this packet and 534 * therefore none of the other additional attributes need to be 535 * compared. 536 */ 537 rxstmp = (u64)er32(RXSTMPL); 538 rxstmp |= (u64)er32(RXSTMPH) << 32; 539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 540 541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 542 } 543 544 /** 545 * e1000_receive_skb - helper function to handle Rx indications 546 * @adapter: board private structure 547 * @staterr: descriptor extended error and status field as written by hardware 548 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 549 * @skb: pointer to sk_buff to be indicated to stack 550 **/ 551 static void e1000_receive_skb(struct e1000_adapter *adapter, 552 struct net_device *netdev, struct sk_buff *skb, 553 u32 staterr, __le16 vlan) 554 { 555 u16 tag = le16_to_cpu(vlan); 556 557 e1000e_rx_hwtstamp(adapter, staterr, skb); 558 559 skb->protocol = eth_type_trans(skb, netdev); 560 561 if (staterr & E1000_RXD_STAT_VP) 562 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 563 564 napi_gro_receive(&adapter->napi, skb); 565 } 566 567 /** 568 * e1000_rx_checksum - Receive Checksum Offload 569 * @adapter: board private structure 570 * @status_err: receive descriptor status and error fields 571 * @csum: receive descriptor csum field 572 * @sk_buff: socket buffer with received data 573 **/ 574 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 575 struct sk_buff *skb) 576 { 577 u16 status = (u16)status_err; 578 u8 errors = (u8)(status_err >> 24); 579 580 skb_checksum_none_assert(skb); 581 582 /* Rx checksum disabled */ 583 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 584 return; 585 586 /* Ignore Checksum bit is set */ 587 if (status & E1000_RXD_STAT_IXSM) 588 return; 589 590 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 592 /* let the stack verify checksum errors */ 593 adapter->hw_csum_err++; 594 return; 595 } 596 597 /* TCP/UDP Checksum has not been calculated */ 598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 599 return; 600 601 /* It must be a TCP or UDP packet with a valid checksum */ 602 skb->ip_summed = CHECKSUM_UNNECESSARY; 603 adapter->hw_csum_good++; 604 } 605 606 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 607 { 608 struct e1000_adapter *adapter = rx_ring->adapter; 609 struct e1000_hw *hw = &adapter->hw; 610 s32 ret_val = __ew32_prepare(hw); 611 612 writel(i, rx_ring->tail); 613 614 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { 615 u32 rctl = er32(RCTL); 616 617 ew32(RCTL, rctl & ~E1000_RCTL_EN); 618 e_err("ME firmware caused invalid RDT - resetting\n"); 619 schedule_work(&adapter->reset_task); 620 } 621 } 622 623 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 624 { 625 struct e1000_adapter *adapter = tx_ring->adapter; 626 struct e1000_hw *hw = &adapter->hw; 627 s32 ret_val = __ew32_prepare(hw); 628 629 writel(i, tx_ring->tail); 630 631 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { 632 u32 tctl = er32(TCTL); 633 634 ew32(TCTL, tctl & ~E1000_TCTL_EN); 635 e_err("ME firmware caused invalid TDT - resetting\n"); 636 schedule_work(&adapter->reset_task); 637 } 638 } 639 640 /** 641 * e1000_alloc_rx_buffers - Replace used receive buffers 642 * @rx_ring: Rx descriptor ring 643 **/ 644 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 645 int cleaned_count, gfp_t gfp) 646 { 647 struct e1000_adapter *adapter = rx_ring->adapter; 648 struct net_device *netdev = adapter->netdev; 649 struct pci_dev *pdev = adapter->pdev; 650 union e1000_rx_desc_extended *rx_desc; 651 struct e1000_buffer *buffer_info; 652 struct sk_buff *skb; 653 unsigned int i; 654 unsigned int bufsz = adapter->rx_buffer_len; 655 656 i = rx_ring->next_to_use; 657 buffer_info = &rx_ring->buffer_info[i]; 658 659 while (cleaned_count--) { 660 skb = buffer_info->skb; 661 if (skb) { 662 skb_trim(skb, 0); 663 goto map_skb; 664 } 665 666 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 667 if (!skb) { 668 /* Better luck next round */ 669 adapter->alloc_rx_buff_failed++; 670 break; 671 } 672 673 buffer_info->skb = skb; 674 map_skb: 675 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 676 adapter->rx_buffer_len, 677 DMA_FROM_DEVICE); 678 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 679 dev_err(&pdev->dev, "Rx DMA map failed\n"); 680 adapter->rx_dma_failed++; 681 break; 682 } 683 684 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 685 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 686 687 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 688 /* Force memory writes to complete before letting h/w 689 * know there are new descriptors to fetch. (Only 690 * applicable for weak-ordered memory model archs, 691 * such as IA-64). 692 */ 693 wmb(); 694 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 695 e1000e_update_rdt_wa(rx_ring, i); 696 else 697 writel(i, rx_ring->tail); 698 } 699 i++; 700 if (i == rx_ring->count) 701 i = 0; 702 buffer_info = &rx_ring->buffer_info[i]; 703 } 704 705 rx_ring->next_to_use = i; 706 } 707 708 /** 709 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 710 * @rx_ring: Rx descriptor ring 711 **/ 712 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 713 int cleaned_count, gfp_t gfp) 714 { 715 struct e1000_adapter *adapter = rx_ring->adapter; 716 struct net_device *netdev = adapter->netdev; 717 struct pci_dev *pdev = adapter->pdev; 718 union e1000_rx_desc_packet_split *rx_desc; 719 struct e1000_buffer *buffer_info; 720 struct e1000_ps_page *ps_page; 721 struct sk_buff *skb; 722 unsigned int i, j; 723 724 i = rx_ring->next_to_use; 725 buffer_info = &rx_ring->buffer_info[i]; 726 727 while (cleaned_count--) { 728 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 729 730 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 731 ps_page = &buffer_info->ps_pages[j]; 732 if (j >= adapter->rx_ps_pages) { 733 /* all unused desc entries get hw null ptr */ 734 rx_desc->read.buffer_addr[j + 1] = 735 ~cpu_to_le64(0); 736 continue; 737 } 738 if (!ps_page->page) { 739 ps_page->page = alloc_page(gfp); 740 if (!ps_page->page) { 741 adapter->alloc_rx_buff_failed++; 742 goto no_buffers; 743 } 744 ps_page->dma = dma_map_page(&pdev->dev, 745 ps_page->page, 746 0, PAGE_SIZE, 747 DMA_FROM_DEVICE); 748 if (dma_mapping_error(&pdev->dev, 749 ps_page->dma)) { 750 dev_err(&adapter->pdev->dev, 751 "Rx DMA page map failed\n"); 752 adapter->rx_dma_failed++; 753 goto no_buffers; 754 } 755 } 756 /* Refresh the desc even if buffer_addrs 757 * didn't change because each write-back 758 * erases this info. 759 */ 760 rx_desc->read.buffer_addr[j + 1] = 761 cpu_to_le64(ps_page->dma); 762 } 763 764 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 765 gfp); 766 767 if (!skb) { 768 adapter->alloc_rx_buff_failed++; 769 break; 770 } 771 772 buffer_info->skb = skb; 773 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 774 adapter->rx_ps_bsize0, 775 DMA_FROM_DEVICE); 776 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 777 dev_err(&pdev->dev, "Rx DMA map failed\n"); 778 adapter->rx_dma_failed++; 779 /* cleanup skb */ 780 dev_kfree_skb_any(skb); 781 buffer_info->skb = NULL; 782 break; 783 } 784 785 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 786 787 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 788 /* Force memory writes to complete before letting h/w 789 * know there are new descriptors to fetch. (Only 790 * applicable for weak-ordered memory model archs, 791 * such as IA-64). 792 */ 793 wmb(); 794 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 795 e1000e_update_rdt_wa(rx_ring, i << 1); 796 else 797 writel(i << 1, rx_ring->tail); 798 } 799 800 i++; 801 if (i == rx_ring->count) 802 i = 0; 803 buffer_info = &rx_ring->buffer_info[i]; 804 } 805 806 no_buffers: 807 rx_ring->next_to_use = i; 808 } 809 810 /** 811 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 812 * @rx_ring: Rx descriptor ring 813 * @cleaned_count: number of buffers to allocate this pass 814 **/ 815 816 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 817 int cleaned_count, gfp_t gfp) 818 { 819 struct e1000_adapter *adapter = rx_ring->adapter; 820 struct net_device *netdev = adapter->netdev; 821 struct pci_dev *pdev = adapter->pdev; 822 union e1000_rx_desc_extended *rx_desc; 823 struct e1000_buffer *buffer_info; 824 struct sk_buff *skb; 825 unsigned int i; 826 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 827 828 i = rx_ring->next_to_use; 829 buffer_info = &rx_ring->buffer_info[i]; 830 831 while (cleaned_count--) { 832 skb = buffer_info->skb; 833 if (skb) { 834 skb_trim(skb, 0); 835 goto check_page; 836 } 837 838 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 839 if (unlikely(!skb)) { 840 /* Better luck next round */ 841 adapter->alloc_rx_buff_failed++; 842 break; 843 } 844 845 buffer_info->skb = skb; 846 check_page: 847 /* allocate a new page if necessary */ 848 if (!buffer_info->page) { 849 buffer_info->page = alloc_page(gfp); 850 if (unlikely(!buffer_info->page)) { 851 adapter->alloc_rx_buff_failed++; 852 break; 853 } 854 } 855 856 if (!buffer_info->dma) { 857 buffer_info->dma = dma_map_page(&pdev->dev, 858 buffer_info->page, 0, 859 PAGE_SIZE, 860 DMA_FROM_DEVICE); 861 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 862 adapter->alloc_rx_buff_failed++; 863 break; 864 } 865 } 866 867 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 868 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 869 870 if (unlikely(++i == rx_ring->count)) 871 i = 0; 872 buffer_info = &rx_ring->buffer_info[i]; 873 } 874 875 if (likely(rx_ring->next_to_use != i)) { 876 rx_ring->next_to_use = i; 877 if (unlikely(i-- == 0)) 878 i = (rx_ring->count - 1); 879 880 /* Force memory writes to complete before letting h/w 881 * know there are new descriptors to fetch. (Only 882 * applicable for weak-ordered memory model archs, 883 * such as IA-64). 884 */ 885 wmb(); 886 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 887 e1000e_update_rdt_wa(rx_ring, i); 888 else 889 writel(i, rx_ring->tail); 890 } 891 } 892 893 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 894 struct sk_buff *skb) 895 { 896 if (netdev->features & NETIF_F_RXHASH) 897 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 898 } 899 900 /** 901 * e1000_clean_rx_irq - Send received data up the network stack 902 * @rx_ring: Rx descriptor ring 903 * 904 * the return value indicates whether actual cleaning was done, there 905 * is no guarantee that everything was cleaned 906 **/ 907 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 908 int work_to_do) 909 { 910 struct e1000_adapter *adapter = rx_ring->adapter; 911 struct net_device *netdev = adapter->netdev; 912 struct pci_dev *pdev = adapter->pdev; 913 struct e1000_hw *hw = &adapter->hw; 914 union e1000_rx_desc_extended *rx_desc, *next_rxd; 915 struct e1000_buffer *buffer_info, *next_buffer; 916 u32 length, staterr; 917 unsigned int i; 918 int cleaned_count = 0; 919 bool cleaned = false; 920 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 921 922 i = rx_ring->next_to_clean; 923 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 924 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 925 buffer_info = &rx_ring->buffer_info[i]; 926 927 while (staterr & E1000_RXD_STAT_DD) { 928 struct sk_buff *skb; 929 930 if (*work_done >= work_to_do) 931 break; 932 (*work_done)++; 933 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 934 935 skb = buffer_info->skb; 936 buffer_info->skb = NULL; 937 938 prefetch(skb->data - NET_IP_ALIGN); 939 940 i++; 941 if (i == rx_ring->count) 942 i = 0; 943 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 944 prefetch(next_rxd); 945 946 next_buffer = &rx_ring->buffer_info[i]; 947 948 cleaned = true; 949 cleaned_count++; 950 dma_unmap_single(&pdev->dev, buffer_info->dma, 951 adapter->rx_buffer_len, DMA_FROM_DEVICE); 952 buffer_info->dma = 0; 953 954 length = le16_to_cpu(rx_desc->wb.upper.length); 955 956 /* !EOP means multiple descriptors were used to store a single 957 * packet, if that's the case we need to toss it. In fact, we 958 * need to toss every packet with the EOP bit clear and the 959 * next frame that _does_ have the EOP bit set, as it is by 960 * definition only a frame fragment 961 */ 962 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 963 adapter->flags2 |= FLAG2_IS_DISCARDING; 964 965 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 966 /* All receives must fit into a single buffer */ 967 e_dbg("Receive packet consumed multiple buffers\n"); 968 /* recycle */ 969 buffer_info->skb = skb; 970 if (staterr & E1000_RXD_STAT_EOP) 971 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 972 goto next_desc; 973 } 974 975 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 976 !(netdev->features & NETIF_F_RXALL))) { 977 /* recycle */ 978 buffer_info->skb = skb; 979 goto next_desc; 980 } 981 982 /* adjust length to remove Ethernet CRC */ 983 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 984 /* If configured to store CRC, don't subtract FCS, 985 * but keep the FCS bytes out of the total_rx_bytes 986 * counter 987 */ 988 if (netdev->features & NETIF_F_RXFCS) 989 total_rx_bytes -= 4; 990 else 991 length -= 4; 992 } 993 994 total_rx_bytes += length; 995 total_rx_packets++; 996 997 /* code added for copybreak, this should improve 998 * performance for small packets with large amounts 999 * of reassembly being done in the stack 1000 */ 1001 if (length < copybreak) { 1002 struct sk_buff *new_skb = 1003 napi_alloc_skb(&adapter->napi, length); 1004 if (new_skb) { 1005 skb_copy_to_linear_data_offset(new_skb, 1006 -NET_IP_ALIGN, 1007 (skb->data - 1008 NET_IP_ALIGN), 1009 (length + 1010 NET_IP_ALIGN)); 1011 /* save the skb in buffer_info as good */ 1012 buffer_info->skb = skb; 1013 skb = new_skb; 1014 } 1015 /* else just continue with the old one */ 1016 } 1017 /* end copybreak code */ 1018 skb_put(skb, length); 1019 1020 /* Receive Checksum Offload */ 1021 e1000_rx_checksum(adapter, staterr, skb); 1022 1023 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1024 1025 e1000_receive_skb(adapter, netdev, skb, staterr, 1026 rx_desc->wb.upper.vlan); 1027 1028 next_desc: 1029 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1030 1031 /* return some buffers to hardware, one at a time is too slow */ 1032 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1033 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1034 GFP_ATOMIC); 1035 cleaned_count = 0; 1036 } 1037 1038 /* use prefetched values */ 1039 rx_desc = next_rxd; 1040 buffer_info = next_buffer; 1041 1042 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1043 } 1044 rx_ring->next_to_clean = i; 1045 1046 cleaned_count = e1000_desc_unused(rx_ring); 1047 if (cleaned_count) 1048 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1049 1050 adapter->total_rx_bytes += total_rx_bytes; 1051 adapter->total_rx_packets += total_rx_packets; 1052 return cleaned; 1053 } 1054 1055 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1056 struct e1000_buffer *buffer_info, 1057 bool drop) 1058 { 1059 struct e1000_adapter *adapter = tx_ring->adapter; 1060 1061 if (buffer_info->dma) { 1062 if (buffer_info->mapped_as_page) 1063 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1064 buffer_info->length, DMA_TO_DEVICE); 1065 else 1066 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1067 buffer_info->length, DMA_TO_DEVICE); 1068 buffer_info->dma = 0; 1069 } 1070 if (buffer_info->skb) { 1071 if (drop) 1072 dev_kfree_skb_any(buffer_info->skb); 1073 else 1074 dev_consume_skb_any(buffer_info->skb); 1075 buffer_info->skb = NULL; 1076 } 1077 buffer_info->time_stamp = 0; 1078 } 1079 1080 static void e1000_print_hw_hang(struct work_struct *work) 1081 { 1082 struct e1000_adapter *adapter = container_of(work, 1083 struct e1000_adapter, 1084 print_hang_task); 1085 struct net_device *netdev = adapter->netdev; 1086 struct e1000_ring *tx_ring = adapter->tx_ring; 1087 unsigned int i = tx_ring->next_to_clean; 1088 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1089 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1090 struct e1000_hw *hw = &adapter->hw; 1091 u16 phy_status, phy_1000t_status, phy_ext_status; 1092 u16 pci_status; 1093 1094 if (test_bit(__E1000_DOWN, &adapter->state)) 1095 return; 1096 1097 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1098 /* May be block on write-back, flush and detect again 1099 * flush pending descriptor writebacks to memory 1100 */ 1101 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1102 /* execute the writes immediately */ 1103 e1e_flush(); 1104 /* Due to rare timing issues, write to TIDV again to ensure 1105 * the write is successful 1106 */ 1107 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1108 /* execute the writes immediately */ 1109 e1e_flush(); 1110 adapter->tx_hang_recheck = true; 1111 return; 1112 } 1113 adapter->tx_hang_recheck = false; 1114 1115 if (er32(TDH(0)) == er32(TDT(0))) { 1116 e_dbg("false hang detected, ignoring\n"); 1117 return; 1118 } 1119 1120 /* Real hang detected */ 1121 netif_stop_queue(netdev); 1122 1123 e1e_rphy(hw, MII_BMSR, &phy_status); 1124 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1125 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1126 1127 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1128 1129 /* detected Hardware unit hang */ 1130 e_err("Detected Hardware Unit Hang:\n" 1131 " TDH <%x>\n" 1132 " TDT <%x>\n" 1133 " next_to_use <%x>\n" 1134 " next_to_clean <%x>\n" 1135 "buffer_info[next_to_clean]:\n" 1136 " time_stamp <%lx>\n" 1137 " next_to_watch <%x>\n" 1138 " jiffies <%lx>\n" 1139 " next_to_watch.status <%x>\n" 1140 "MAC Status <%x>\n" 1141 "PHY Status <%x>\n" 1142 "PHY 1000BASE-T Status <%x>\n" 1143 "PHY Extended Status <%x>\n" 1144 "PCI Status <%x>\n", 1145 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1146 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1147 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1148 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1149 1150 e1000e_dump(adapter); 1151 1152 /* Suggest workaround for known h/w issue */ 1153 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1154 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1155 } 1156 1157 /** 1158 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1159 * @work: pointer to work struct 1160 * 1161 * This work function polls the TSYNCTXCTL valid bit to determine when a 1162 * timestamp has been taken for the current stored skb. The timestamp must 1163 * be for this skb because only one such packet is allowed in the queue. 1164 */ 1165 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1166 { 1167 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1168 tx_hwtstamp_work); 1169 struct e1000_hw *hw = &adapter->hw; 1170 1171 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1172 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1173 struct skb_shared_hwtstamps shhwtstamps; 1174 u64 txstmp; 1175 1176 txstmp = er32(TXSTMPL); 1177 txstmp |= (u64)er32(TXSTMPH) << 32; 1178 1179 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1180 1181 /* Clear the global tx_hwtstamp_skb pointer and force writes 1182 * prior to notifying the stack of a Tx timestamp. 1183 */ 1184 adapter->tx_hwtstamp_skb = NULL; 1185 wmb(); /* force write prior to skb_tstamp_tx */ 1186 1187 skb_tstamp_tx(skb, &shhwtstamps); 1188 dev_consume_skb_any(skb); 1189 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1190 + adapter->tx_timeout_factor * HZ)) { 1191 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1192 adapter->tx_hwtstamp_skb = NULL; 1193 adapter->tx_hwtstamp_timeouts++; 1194 e_warn("clearing Tx timestamp hang\n"); 1195 } else { 1196 /* reschedule to check later */ 1197 schedule_work(&adapter->tx_hwtstamp_work); 1198 } 1199 } 1200 1201 /** 1202 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1203 * @tx_ring: Tx descriptor ring 1204 * 1205 * the return value indicates whether actual cleaning was done, there 1206 * is no guarantee that everything was cleaned 1207 **/ 1208 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1209 { 1210 struct e1000_adapter *adapter = tx_ring->adapter; 1211 struct net_device *netdev = adapter->netdev; 1212 struct e1000_hw *hw = &adapter->hw; 1213 struct e1000_tx_desc *tx_desc, *eop_desc; 1214 struct e1000_buffer *buffer_info; 1215 unsigned int i, eop; 1216 unsigned int count = 0; 1217 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1218 unsigned int bytes_compl = 0, pkts_compl = 0; 1219 1220 i = tx_ring->next_to_clean; 1221 eop = tx_ring->buffer_info[i].next_to_watch; 1222 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1223 1224 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1225 (count < tx_ring->count)) { 1226 bool cleaned = false; 1227 1228 dma_rmb(); /* read buffer_info after eop_desc */ 1229 for (; !cleaned; count++) { 1230 tx_desc = E1000_TX_DESC(*tx_ring, i); 1231 buffer_info = &tx_ring->buffer_info[i]; 1232 cleaned = (i == eop); 1233 1234 if (cleaned) { 1235 total_tx_packets += buffer_info->segs; 1236 total_tx_bytes += buffer_info->bytecount; 1237 if (buffer_info->skb) { 1238 bytes_compl += buffer_info->skb->len; 1239 pkts_compl++; 1240 } 1241 } 1242 1243 e1000_put_txbuf(tx_ring, buffer_info, false); 1244 tx_desc->upper.data = 0; 1245 1246 i++; 1247 if (i == tx_ring->count) 1248 i = 0; 1249 } 1250 1251 if (i == tx_ring->next_to_use) 1252 break; 1253 eop = tx_ring->buffer_info[i].next_to_watch; 1254 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1255 } 1256 1257 tx_ring->next_to_clean = i; 1258 1259 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1260 1261 #define TX_WAKE_THRESHOLD 32 1262 if (count && netif_carrier_ok(netdev) && 1263 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1264 /* Make sure that anybody stopping the queue after this 1265 * sees the new next_to_clean. 1266 */ 1267 smp_mb(); 1268 1269 if (netif_queue_stopped(netdev) && 1270 !(test_bit(__E1000_DOWN, &adapter->state))) { 1271 netif_wake_queue(netdev); 1272 ++adapter->restart_queue; 1273 } 1274 } 1275 1276 if (adapter->detect_tx_hung) { 1277 /* Detect a transmit hang in hardware, this serializes the 1278 * check with the clearing of time_stamp and movement of i 1279 */ 1280 adapter->detect_tx_hung = false; 1281 if (tx_ring->buffer_info[i].time_stamp && 1282 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1283 + (adapter->tx_timeout_factor * HZ)) && 1284 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1285 schedule_work(&adapter->print_hang_task); 1286 else 1287 adapter->tx_hang_recheck = false; 1288 } 1289 adapter->total_tx_bytes += total_tx_bytes; 1290 adapter->total_tx_packets += total_tx_packets; 1291 return count < tx_ring->count; 1292 } 1293 1294 /** 1295 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1296 * @rx_ring: Rx descriptor ring 1297 * 1298 * the return value indicates whether actual cleaning was done, there 1299 * is no guarantee that everything was cleaned 1300 **/ 1301 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1302 int work_to_do) 1303 { 1304 struct e1000_adapter *adapter = rx_ring->adapter; 1305 struct e1000_hw *hw = &adapter->hw; 1306 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1307 struct net_device *netdev = adapter->netdev; 1308 struct pci_dev *pdev = adapter->pdev; 1309 struct e1000_buffer *buffer_info, *next_buffer; 1310 struct e1000_ps_page *ps_page; 1311 struct sk_buff *skb; 1312 unsigned int i, j; 1313 u32 length, staterr; 1314 int cleaned_count = 0; 1315 bool cleaned = false; 1316 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1317 1318 i = rx_ring->next_to_clean; 1319 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1320 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1321 buffer_info = &rx_ring->buffer_info[i]; 1322 1323 while (staterr & E1000_RXD_STAT_DD) { 1324 if (*work_done >= work_to_do) 1325 break; 1326 (*work_done)++; 1327 skb = buffer_info->skb; 1328 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1329 1330 /* in the packet split case this is header only */ 1331 prefetch(skb->data - NET_IP_ALIGN); 1332 1333 i++; 1334 if (i == rx_ring->count) 1335 i = 0; 1336 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1337 prefetch(next_rxd); 1338 1339 next_buffer = &rx_ring->buffer_info[i]; 1340 1341 cleaned = true; 1342 cleaned_count++; 1343 dma_unmap_single(&pdev->dev, buffer_info->dma, 1344 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1345 buffer_info->dma = 0; 1346 1347 /* see !EOP comment in other Rx routine */ 1348 if (!(staterr & E1000_RXD_STAT_EOP)) 1349 adapter->flags2 |= FLAG2_IS_DISCARDING; 1350 1351 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1352 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1353 dev_kfree_skb_irq(skb); 1354 if (staterr & E1000_RXD_STAT_EOP) 1355 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1356 goto next_desc; 1357 } 1358 1359 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1360 !(netdev->features & NETIF_F_RXALL))) { 1361 dev_kfree_skb_irq(skb); 1362 goto next_desc; 1363 } 1364 1365 length = le16_to_cpu(rx_desc->wb.middle.length0); 1366 1367 if (!length) { 1368 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1369 dev_kfree_skb_irq(skb); 1370 goto next_desc; 1371 } 1372 1373 /* Good Receive */ 1374 skb_put(skb, length); 1375 1376 { 1377 /* this looks ugly, but it seems compiler issues make 1378 * it more efficient than reusing j 1379 */ 1380 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1381 1382 /* page alloc/put takes too long and effects small 1383 * packet throughput, so unsplit small packets and 1384 * save the alloc/put only valid in softirq (napi) 1385 * context to call kmap_* 1386 */ 1387 if (l1 && (l1 <= copybreak) && 1388 ((length + l1) <= adapter->rx_ps_bsize0)) { 1389 u8 *vaddr; 1390 1391 ps_page = &buffer_info->ps_pages[0]; 1392 1393 /* there is no documentation about how to call 1394 * kmap_atomic, so we can't hold the mapping 1395 * very long 1396 */ 1397 dma_sync_single_for_cpu(&pdev->dev, 1398 ps_page->dma, 1399 PAGE_SIZE, 1400 DMA_FROM_DEVICE); 1401 vaddr = kmap_atomic(ps_page->page); 1402 memcpy(skb_tail_pointer(skb), vaddr, l1); 1403 kunmap_atomic(vaddr); 1404 dma_sync_single_for_device(&pdev->dev, 1405 ps_page->dma, 1406 PAGE_SIZE, 1407 DMA_FROM_DEVICE); 1408 1409 /* remove the CRC */ 1410 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1411 if (!(netdev->features & NETIF_F_RXFCS)) 1412 l1 -= 4; 1413 } 1414 1415 skb_put(skb, l1); 1416 goto copydone; 1417 } /* if */ 1418 } 1419 1420 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1421 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1422 if (!length) 1423 break; 1424 1425 ps_page = &buffer_info->ps_pages[j]; 1426 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1427 DMA_FROM_DEVICE); 1428 ps_page->dma = 0; 1429 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1430 ps_page->page = NULL; 1431 skb->len += length; 1432 skb->data_len += length; 1433 skb->truesize += PAGE_SIZE; 1434 } 1435 1436 /* strip the ethernet crc, problem is we're using pages now so 1437 * this whole operation can get a little cpu intensive 1438 */ 1439 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1440 if (!(netdev->features & NETIF_F_RXFCS)) 1441 pskb_trim(skb, skb->len - 4); 1442 } 1443 1444 copydone: 1445 total_rx_bytes += skb->len; 1446 total_rx_packets++; 1447 1448 e1000_rx_checksum(adapter, staterr, skb); 1449 1450 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1451 1452 if (rx_desc->wb.upper.header_status & 1453 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1454 adapter->rx_hdr_split++; 1455 1456 e1000_receive_skb(adapter, netdev, skb, staterr, 1457 rx_desc->wb.middle.vlan); 1458 1459 next_desc: 1460 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1461 buffer_info->skb = NULL; 1462 1463 /* return some buffers to hardware, one at a time is too slow */ 1464 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1465 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1466 GFP_ATOMIC); 1467 cleaned_count = 0; 1468 } 1469 1470 /* use prefetched values */ 1471 rx_desc = next_rxd; 1472 buffer_info = next_buffer; 1473 1474 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1475 } 1476 rx_ring->next_to_clean = i; 1477 1478 cleaned_count = e1000_desc_unused(rx_ring); 1479 if (cleaned_count) 1480 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1481 1482 adapter->total_rx_bytes += total_rx_bytes; 1483 adapter->total_rx_packets += total_rx_packets; 1484 return cleaned; 1485 } 1486 1487 /** 1488 * e1000_consume_page - helper function 1489 **/ 1490 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1491 u16 length) 1492 { 1493 bi->page = NULL; 1494 skb->len += length; 1495 skb->data_len += length; 1496 skb->truesize += PAGE_SIZE; 1497 } 1498 1499 /** 1500 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1501 * @adapter: board private structure 1502 * 1503 * the return value indicates whether actual cleaning was done, there 1504 * is no guarantee that everything was cleaned 1505 **/ 1506 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1507 int work_to_do) 1508 { 1509 struct e1000_adapter *adapter = rx_ring->adapter; 1510 struct net_device *netdev = adapter->netdev; 1511 struct pci_dev *pdev = adapter->pdev; 1512 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1513 struct e1000_buffer *buffer_info, *next_buffer; 1514 u32 length, staterr; 1515 unsigned int i; 1516 int cleaned_count = 0; 1517 bool cleaned = false; 1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1519 struct skb_shared_info *shinfo; 1520 1521 i = rx_ring->next_to_clean; 1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1524 buffer_info = &rx_ring->buffer_info[i]; 1525 1526 while (staterr & E1000_RXD_STAT_DD) { 1527 struct sk_buff *skb; 1528 1529 if (*work_done >= work_to_do) 1530 break; 1531 (*work_done)++; 1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1533 1534 skb = buffer_info->skb; 1535 buffer_info->skb = NULL; 1536 1537 ++i; 1538 if (i == rx_ring->count) 1539 i = 0; 1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1541 prefetch(next_rxd); 1542 1543 next_buffer = &rx_ring->buffer_info[i]; 1544 1545 cleaned = true; 1546 cleaned_count++; 1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1548 DMA_FROM_DEVICE); 1549 buffer_info->dma = 0; 1550 1551 length = le16_to_cpu(rx_desc->wb.upper.length); 1552 1553 /* errors is only valid for DD + EOP descriptors */ 1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1556 !(netdev->features & NETIF_F_RXALL)))) { 1557 /* recycle both page and skb */ 1558 buffer_info->skb = skb; 1559 /* an error means any chain goes out the window too */ 1560 if (rx_ring->rx_skb_top) 1561 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1562 rx_ring->rx_skb_top = NULL; 1563 goto next_desc; 1564 } 1565 #define rxtop (rx_ring->rx_skb_top) 1566 if (!(staterr & E1000_RXD_STAT_EOP)) { 1567 /* this descriptor is only the beginning (or middle) */ 1568 if (!rxtop) { 1569 /* this is the beginning of a chain */ 1570 rxtop = skb; 1571 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1572 0, length); 1573 } else { 1574 /* this is the middle of a chain */ 1575 shinfo = skb_shinfo(rxtop); 1576 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1577 buffer_info->page, 0, 1578 length); 1579 /* re-use the skb, only consumed the page */ 1580 buffer_info->skb = skb; 1581 } 1582 e1000_consume_page(buffer_info, rxtop, length); 1583 goto next_desc; 1584 } else { 1585 if (rxtop) { 1586 /* end of the chain */ 1587 shinfo = skb_shinfo(rxtop); 1588 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1589 buffer_info->page, 0, 1590 length); 1591 /* re-use the current skb, we only consumed the 1592 * page 1593 */ 1594 buffer_info->skb = skb; 1595 skb = rxtop; 1596 rxtop = NULL; 1597 e1000_consume_page(buffer_info, skb, length); 1598 } else { 1599 /* no chain, got EOP, this buf is the packet 1600 * copybreak to save the put_page/alloc_page 1601 */ 1602 if (length <= copybreak && 1603 skb_tailroom(skb) >= length) { 1604 u8 *vaddr; 1605 vaddr = kmap_atomic(buffer_info->page); 1606 memcpy(skb_tail_pointer(skb), vaddr, 1607 length); 1608 kunmap_atomic(vaddr); 1609 /* re-use the page, so don't erase 1610 * buffer_info->page 1611 */ 1612 skb_put(skb, length); 1613 } else { 1614 skb_fill_page_desc(skb, 0, 1615 buffer_info->page, 0, 1616 length); 1617 e1000_consume_page(buffer_info, skb, 1618 length); 1619 } 1620 } 1621 } 1622 1623 /* Receive Checksum Offload */ 1624 e1000_rx_checksum(adapter, staterr, skb); 1625 1626 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1627 1628 /* probably a little skewed due to removing CRC */ 1629 total_rx_bytes += skb->len; 1630 total_rx_packets++; 1631 1632 /* eth type trans needs skb->data to point to something */ 1633 if (!pskb_may_pull(skb, ETH_HLEN)) { 1634 e_err("pskb_may_pull failed.\n"); 1635 dev_kfree_skb_irq(skb); 1636 goto next_desc; 1637 } 1638 1639 e1000_receive_skb(adapter, netdev, skb, staterr, 1640 rx_desc->wb.upper.vlan); 1641 1642 next_desc: 1643 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1644 1645 /* return some buffers to hardware, one at a time is too slow */ 1646 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1647 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1648 GFP_ATOMIC); 1649 cleaned_count = 0; 1650 } 1651 1652 /* use prefetched values */ 1653 rx_desc = next_rxd; 1654 buffer_info = next_buffer; 1655 1656 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1657 } 1658 rx_ring->next_to_clean = i; 1659 1660 cleaned_count = e1000_desc_unused(rx_ring); 1661 if (cleaned_count) 1662 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1663 1664 adapter->total_rx_bytes += total_rx_bytes; 1665 adapter->total_rx_packets += total_rx_packets; 1666 return cleaned; 1667 } 1668 1669 /** 1670 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1671 * @rx_ring: Rx descriptor ring 1672 **/ 1673 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1674 { 1675 struct e1000_adapter *adapter = rx_ring->adapter; 1676 struct e1000_buffer *buffer_info; 1677 struct e1000_ps_page *ps_page; 1678 struct pci_dev *pdev = adapter->pdev; 1679 unsigned int i, j; 1680 1681 /* Free all the Rx ring sk_buffs */ 1682 for (i = 0; i < rx_ring->count; i++) { 1683 buffer_info = &rx_ring->buffer_info[i]; 1684 if (buffer_info->dma) { 1685 if (adapter->clean_rx == e1000_clean_rx_irq) 1686 dma_unmap_single(&pdev->dev, buffer_info->dma, 1687 adapter->rx_buffer_len, 1688 DMA_FROM_DEVICE); 1689 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1690 dma_unmap_page(&pdev->dev, buffer_info->dma, 1691 PAGE_SIZE, DMA_FROM_DEVICE); 1692 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1693 dma_unmap_single(&pdev->dev, buffer_info->dma, 1694 adapter->rx_ps_bsize0, 1695 DMA_FROM_DEVICE); 1696 buffer_info->dma = 0; 1697 } 1698 1699 if (buffer_info->page) { 1700 put_page(buffer_info->page); 1701 buffer_info->page = NULL; 1702 } 1703 1704 if (buffer_info->skb) { 1705 dev_kfree_skb(buffer_info->skb); 1706 buffer_info->skb = NULL; 1707 } 1708 1709 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1710 ps_page = &buffer_info->ps_pages[j]; 1711 if (!ps_page->page) 1712 break; 1713 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1714 DMA_FROM_DEVICE); 1715 ps_page->dma = 0; 1716 put_page(ps_page->page); 1717 ps_page->page = NULL; 1718 } 1719 } 1720 1721 /* there also may be some cached data from a chained receive */ 1722 if (rx_ring->rx_skb_top) { 1723 dev_kfree_skb(rx_ring->rx_skb_top); 1724 rx_ring->rx_skb_top = NULL; 1725 } 1726 1727 /* Zero out the descriptor ring */ 1728 memset(rx_ring->desc, 0, rx_ring->size); 1729 1730 rx_ring->next_to_clean = 0; 1731 rx_ring->next_to_use = 0; 1732 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1733 } 1734 1735 static void e1000e_downshift_workaround(struct work_struct *work) 1736 { 1737 struct e1000_adapter *adapter = container_of(work, 1738 struct e1000_adapter, 1739 downshift_task); 1740 1741 if (test_bit(__E1000_DOWN, &adapter->state)) 1742 return; 1743 1744 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1745 } 1746 1747 /** 1748 * e1000_intr_msi - Interrupt Handler 1749 * @irq: interrupt number 1750 * @data: pointer to a network interface device structure 1751 **/ 1752 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1753 { 1754 struct net_device *netdev = data; 1755 struct e1000_adapter *adapter = netdev_priv(netdev); 1756 struct e1000_hw *hw = &adapter->hw; 1757 u32 icr = er32(ICR); 1758 1759 /* read ICR disables interrupts using IAM */ 1760 if (icr & E1000_ICR_LSC) { 1761 hw->mac.get_link_status = true; 1762 /* ICH8 workaround-- Call gig speed drop workaround on cable 1763 * disconnect (LSC) before accessing any PHY registers 1764 */ 1765 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1766 (!(er32(STATUS) & E1000_STATUS_LU))) 1767 schedule_work(&adapter->downshift_task); 1768 1769 /* 80003ES2LAN workaround-- For packet buffer work-around on 1770 * link down event; disable receives here in the ISR and reset 1771 * adapter in watchdog 1772 */ 1773 if (netif_carrier_ok(netdev) && 1774 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1775 /* disable receives */ 1776 u32 rctl = er32(RCTL); 1777 1778 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1779 adapter->flags |= FLAG_RESTART_NOW; 1780 } 1781 /* guard against interrupt when we're going down */ 1782 if (!test_bit(__E1000_DOWN, &adapter->state)) 1783 mod_delayed_work(adapter->e1000_workqueue, 1784 &adapter->watchdog_task, HZ); 1785 } 1786 1787 /* Reset on uncorrectable ECC error */ 1788 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1789 u32 pbeccsts = er32(PBECCSTS); 1790 1791 adapter->corr_errors += 1792 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1793 adapter->uncorr_errors += 1794 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1795 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1796 1797 /* Do the reset outside of interrupt context */ 1798 schedule_work(&adapter->reset_task); 1799 1800 /* return immediately since reset is imminent */ 1801 return IRQ_HANDLED; 1802 } 1803 1804 if (napi_schedule_prep(&adapter->napi)) { 1805 adapter->total_tx_bytes = 0; 1806 adapter->total_tx_packets = 0; 1807 adapter->total_rx_bytes = 0; 1808 adapter->total_rx_packets = 0; 1809 __napi_schedule(&adapter->napi); 1810 } 1811 1812 return IRQ_HANDLED; 1813 } 1814 1815 /** 1816 * e1000_intr - Interrupt Handler 1817 * @irq: interrupt number 1818 * @data: pointer to a network interface device structure 1819 **/ 1820 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1821 { 1822 struct net_device *netdev = data; 1823 struct e1000_adapter *adapter = netdev_priv(netdev); 1824 struct e1000_hw *hw = &adapter->hw; 1825 u32 rctl, icr = er32(ICR); 1826 1827 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1828 return IRQ_NONE; /* Not our interrupt */ 1829 1830 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1831 * not set, then the adapter didn't send an interrupt 1832 */ 1833 if (!(icr & E1000_ICR_INT_ASSERTED)) 1834 return IRQ_NONE; 1835 1836 /* Interrupt Auto-Mask...upon reading ICR, 1837 * interrupts are masked. No need for the 1838 * IMC write 1839 */ 1840 1841 if (icr & E1000_ICR_LSC) { 1842 hw->mac.get_link_status = true; 1843 /* ICH8 workaround-- Call gig speed drop workaround on cable 1844 * disconnect (LSC) before accessing any PHY registers 1845 */ 1846 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1847 (!(er32(STATUS) & E1000_STATUS_LU))) 1848 schedule_work(&adapter->downshift_task); 1849 1850 /* 80003ES2LAN workaround-- 1851 * For packet buffer work-around on link down event; 1852 * disable receives here in the ISR and 1853 * reset adapter in watchdog 1854 */ 1855 if (netif_carrier_ok(netdev) && 1856 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1857 /* disable receives */ 1858 rctl = er32(RCTL); 1859 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1860 adapter->flags |= FLAG_RESTART_NOW; 1861 } 1862 /* guard against interrupt when we're going down */ 1863 if (!test_bit(__E1000_DOWN, &adapter->state)) 1864 mod_delayed_work(adapter->e1000_workqueue, 1865 &adapter->watchdog_task, HZ); 1866 } 1867 1868 /* Reset on uncorrectable ECC error */ 1869 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1870 u32 pbeccsts = er32(PBECCSTS); 1871 1872 adapter->corr_errors += 1873 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1874 adapter->uncorr_errors += 1875 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1876 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1877 1878 /* Do the reset outside of interrupt context */ 1879 schedule_work(&adapter->reset_task); 1880 1881 /* return immediately since reset is imminent */ 1882 return IRQ_HANDLED; 1883 } 1884 1885 if (napi_schedule_prep(&adapter->napi)) { 1886 adapter->total_tx_bytes = 0; 1887 adapter->total_tx_packets = 0; 1888 adapter->total_rx_bytes = 0; 1889 adapter->total_rx_packets = 0; 1890 __napi_schedule(&adapter->napi); 1891 } 1892 1893 return IRQ_HANDLED; 1894 } 1895 1896 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1897 { 1898 struct net_device *netdev = data; 1899 struct e1000_adapter *adapter = netdev_priv(netdev); 1900 struct e1000_hw *hw = &adapter->hw; 1901 u32 icr = er32(ICR); 1902 1903 if (icr & adapter->eiac_mask) 1904 ew32(ICS, (icr & adapter->eiac_mask)); 1905 1906 if (icr & E1000_ICR_LSC) { 1907 hw->mac.get_link_status = true; 1908 /* guard against interrupt when we're going down */ 1909 if (!test_bit(__E1000_DOWN, &adapter->state)) 1910 mod_delayed_work(adapter->e1000_workqueue, 1911 &adapter->watchdog_task, HZ); 1912 } 1913 1914 if (!test_bit(__E1000_DOWN, &adapter->state)) 1915 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1916 1917 return IRQ_HANDLED; 1918 } 1919 1920 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1921 { 1922 struct net_device *netdev = data; 1923 struct e1000_adapter *adapter = netdev_priv(netdev); 1924 struct e1000_hw *hw = &adapter->hw; 1925 struct e1000_ring *tx_ring = adapter->tx_ring; 1926 1927 adapter->total_tx_bytes = 0; 1928 adapter->total_tx_packets = 0; 1929 1930 if (!e1000_clean_tx_irq(tx_ring)) 1931 /* Ring was not completely cleaned, so fire another interrupt */ 1932 ew32(ICS, tx_ring->ims_val); 1933 1934 if (!test_bit(__E1000_DOWN, &adapter->state)) 1935 ew32(IMS, adapter->tx_ring->ims_val); 1936 1937 return IRQ_HANDLED; 1938 } 1939 1940 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1941 { 1942 struct net_device *netdev = data; 1943 struct e1000_adapter *adapter = netdev_priv(netdev); 1944 struct e1000_ring *rx_ring = adapter->rx_ring; 1945 1946 /* Write the ITR value calculated at the end of the 1947 * previous interrupt. 1948 */ 1949 if (rx_ring->set_itr) { 1950 u32 itr = rx_ring->itr_val ? 1951 1000000000 / (rx_ring->itr_val * 256) : 0; 1952 1953 writel(itr, rx_ring->itr_register); 1954 rx_ring->set_itr = 0; 1955 } 1956 1957 if (napi_schedule_prep(&adapter->napi)) { 1958 adapter->total_rx_bytes = 0; 1959 adapter->total_rx_packets = 0; 1960 __napi_schedule(&adapter->napi); 1961 } 1962 return IRQ_HANDLED; 1963 } 1964 1965 /** 1966 * e1000_configure_msix - Configure MSI-X hardware 1967 * 1968 * e1000_configure_msix sets up the hardware to properly 1969 * generate MSI-X interrupts. 1970 **/ 1971 static void e1000_configure_msix(struct e1000_adapter *adapter) 1972 { 1973 struct e1000_hw *hw = &adapter->hw; 1974 struct e1000_ring *rx_ring = adapter->rx_ring; 1975 struct e1000_ring *tx_ring = adapter->tx_ring; 1976 int vector = 0; 1977 u32 ctrl_ext, ivar = 0; 1978 1979 adapter->eiac_mask = 0; 1980 1981 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1982 if (hw->mac.type == e1000_82574) { 1983 u32 rfctl = er32(RFCTL); 1984 1985 rfctl |= E1000_RFCTL_ACK_DIS; 1986 ew32(RFCTL, rfctl); 1987 } 1988 1989 /* Configure Rx vector */ 1990 rx_ring->ims_val = E1000_IMS_RXQ0; 1991 adapter->eiac_mask |= rx_ring->ims_val; 1992 if (rx_ring->itr_val) 1993 writel(1000000000 / (rx_ring->itr_val * 256), 1994 rx_ring->itr_register); 1995 else 1996 writel(1, rx_ring->itr_register); 1997 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 1998 1999 /* Configure Tx vector */ 2000 tx_ring->ims_val = E1000_IMS_TXQ0; 2001 vector++; 2002 if (tx_ring->itr_val) 2003 writel(1000000000 / (tx_ring->itr_val * 256), 2004 tx_ring->itr_register); 2005 else 2006 writel(1, tx_ring->itr_register); 2007 adapter->eiac_mask |= tx_ring->ims_val; 2008 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2009 2010 /* set vector for Other Causes, e.g. link changes */ 2011 vector++; 2012 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2013 if (rx_ring->itr_val) 2014 writel(1000000000 / (rx_ring->itr_val * 256), 2015 hw->hw_addr + E1000_EITR_82574(vector)); 2016 else 2017 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2018 2019 /* Cause Tx interrupts on every write back */ 2020 ivar |= BIT(31); 2021 2022 ew32(IVAR, ivar); 2023 2024 /* enable MSI-X PBA support */ 2025 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2026 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2027 ew32(CTRL_EXT, ctrl_ext); 2028 e1e_flush(); 2029 } 2030 2031 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2032 { 2033 if (adapter->msix_entries) { 2034 pci_disable_msix(adapter->pdev); 2035 kfree(adapter->msix_entries); 2036 adapter->msix_entries = NULL; 2037 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2038 pci_disable_msi(adapter->pdev); 2039 adapter->flags &= ~FLAG_MSI_ENABLED; 2040 } 2041 } 2042 2043 /** 2044 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2045 * 2046 * Attempt to configure interrupts using the best available 2047 * capabilities of the hardware and kernel. 2048 **/ 2049 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2050 { 2051 int err; 2052 int i; 2053 2054 switch (adapter->int_mode) { 2055 case E1000E_INT_MODE_MSIX: 2056 if (adapter->flags & FLAG_HAS_MSIX) { 2057 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2058 adapter->msix_entries = kcalloc(adapter->num_vectors, 2059 sizeof(struct 2060 msix_entry), 2061 GFP_KERNEL); 2062 if (adapter->msix_entries) { 2063 struct e1000_adapter *a = adapter; 2064 2065 for (i = 0; i < adapter->num_vectors; i++) 2066 adapter->msix_entries[i].entry = i; 2067 2068 err = pci_enable_msix_range(a->pdev, 2069 a->msix_entries, 2070 a->num_vectors, 2071 a->num_vectors); 2072 if (err > 0) 2073 return; 2074 } 2075 /* MSI-X failed, so fall through and try MSI */ 2076 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2077 e1000e_reset_interrupt_capability(adapter); 2078 } 2079 adapter->int_mode = E1000E_INT_MODE_MSI; 2080 /* Fall through */ 2081 case E1000E_INT_MODE_MSI: 2082 if (!pci_enable_msi(adapter->pdev)) { 2083 adapter->flags |= FLAG_MSI_ENABLED; 2084 } else { 2085 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2086 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2087 } 2088 /* Fall through */ 2089 case E1000E_INT_MODE_LEGACY: 2090 /* Don't do anything; this is the system default */ 2091 break; 2092 } 2093 2094 /* store the number of vectors being used */ 2095 adapter->num_vectors = 1; 2096 } 2097 2098 /** 2099 * e1000_request_msix - Initialize MSI-X interrupts 2100 * 2101 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2102 * kernel. 2103 **/ 2104 static int e1000_request_msix(struct e1000_adapter *adapter) 2105 { 2106 struct net_device *netdev = adapter->netdev; 2107 int err = 0, vector = 0; 2108 2109 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2110 snprintf(adapter->rx_ring->name, 2111 sizeof(adapter->rx_ring->name) - 1, 2112 "%.14s-rx-0", netdev->name); 2113 else 2114 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2115 err = request_irq(adapter->msix_entries[vector].vector, 2116 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2117 netdev); 2118 if (err) 2119 return err; 2120 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2121 E1000_EITR_82574(vector); 2122 adapter->rx_ring->itr_val = adapter->itr; 2123 vector++; 2124 2125 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2126 snprintf(adapter->tx_ring->name, 2127 sizeof(adapter->tx_ring->name) - 1, 2128 "%.14s-tx-0", netdev->name); 2129 else 2130 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2131 err = request_irq(adapter->msix_entries[vector].vector, 2132 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2133 netdev); 2134 if (err) 2135 return err; 2136 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2137 E1000_EITR_82574(vector); 2138 adapter->tx_ring->itr_val = adapter->itr; 2139 vector++; 2140 2141 err = request_irq(adapter->msix_entries[vector].vector, 2142 e1000_msix_other, 0, netdev->name, netdev); 2143 if (err) 2144 return err; 2145 2146 e1000_configure_msix(adapter); 2147 2148 return 0; 2149 } 2150 2151 /** 2152 * e1000_request_irq - initialize interrupts 2153 * 2154 * Attempts to configure interrupts using the best available 2155 * capabilities of the hardware and kernel. 2156 **/ 2157 static int e1000_request_irq(struct e1000_adapter *adapter) 2158 { 2159 struct net_device *netdev = adapter->netdev; 2160 int err; 2161 2162 if (adapter->msix_entries) { 2163 err = e1000_request_msix(adapter); 2164 if (!err) 2165 return err; 2166 /* fall back to MSI */ 2167 e1000e_reset_interrupt_capability(adapter); 2168 adapter->int_mode = E1000E_INT_MODE_MSI; 2169 e1000e_set_interrupt_capability(adapter); 2170 } 2171 if (adapter->flags & FLAG_MSI_ENABLED) { 2172 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2173 netdev->name, netdev); 2174 if (!err) 2175 return err; 2176 2177 /* fall back to legacy interrupt */ 2178 e1000e_reset_interrupt_capability(adapter); 2179 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2180 } 2181 2182 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2183 netdev->name, netdev); 2184 if (err) 2185 e_err("Unable to allocate interrupt, Error: %d\n", err); 2186 2187 return err; 2188 } 2189 2190 static void e1000_free_irq(struct e1000_adapter *adapter) 2191 { 2192 struct net_device *netdev = adapter->netdev; 2193 2194 if (adapter->msix_entries) { 2195 int vector = 0; 2196 2197 free_irq(adapter->msix_entries[vector].vector, netdev); 2198 vector++; 2199 2200 free_irq(adapter->msix_entries[vector].vector, netdev); 2201 vector++; 2202 2203 /* Other Causes interrupt vector */ 2204 free_irq(adapter->msix_entries[vector].vector, netdev); 2205 return; 2206 } 2207 2208 free_irq(adapter->pdev->irq, netdev); 2209 } 2210 2211 /** 2212 * e1000_irq_disable - Mask off interrupt generation on the NIC 2213 **/ 2214 static void e1000_irq_disable(struct e1000_adapter *adapter) 2215 { 2216 struct e1000_hw *hw = &adapter->hw; 2217 2218 ew32(IMC, ~0); 2219 if (adapter->msix_entries) 2220 ew32(EIAC_82574, 0); 2221 e1e_flush(); 2222 2223 if (adapter->msix_entries) { 2224 int i; 2225 2226 for (i = 0; i < adapter->num_vectors; i++) 2227 synchronize_irq(adapter->msix_entries[i].vector); 2228 } else { 2229 synchronize_irq(adapter->pdev->irq); 2230 } 2231 } 2232 2233 /** 2234 * e1000_irq_enable - Enable default interrupt generation settings 2235 **/ 2236 static void e1000_irq_enable(struct e1000_adapter *adapter) 2237 { 2238 struct e1000_hw *hw = &adapter->hw; 2239 2240 if (adapter->msix_entries) { 2241 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2242 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2243 IMS_OTHER_MASK); 2244 } else if (hw->mac.type >= e1000_pch_lpt) { 2245 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2246 } else { 2247 ew32(IMS, IMS_ENABLE_MASK); 2248 } 2249 e1e_flush(); 2250 } 2251 2252 /** 2253 * e1000e_get_hw_control - get control of the h/w from f/w 2254 * @adapter: address of board private structure 2255 * 2256 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2257 * For ASF and Pass Through versions of f/w this means that 2258 * the driver is loaded. For AMT version (only with 82573) 2259 * of the f/w this means that the network i/f is open. 2260 **/ 2261 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2262 { 2263 struct e1000_hw *hw = &adapter->hw; 2264 u32 ctrl_ext; 2265 u32 swsm; 2266 2267 /* Let firmware know the driver has taken over */ 2268 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2269 swsm = er32(SWSM); 2270 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2271 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2272 ctrl_ext = er32(CTRL_EXT); 2273 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2274 } 2275 } 2276 2277 /** 2278 * e1000e_release_hw_control - release control of the h/w to f/w 2279 * @adapter: address of board private structure 2280 * 2281 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2282 * For ASF and Pass Through versions of f/w this means that the 2283 * driver is no longer loaded. For AMT version (only with 82573) i 2284 * of the f/w this means that the network i/f is closed. 2285 * 2286 **/ 2287 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2288 { 2289 struct e1000_hw *hw = &adapter->hw; 2290 u32 ctrl_ext; 2291 u32 swsm; 2292 2293 /* Let firmware taken over control of h/w */ 2294 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2295 swsm = er32(SWSM); 2296 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2297 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2298 ctrl_ext = er32(CTRL_EXT); 2299 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2300 } 2301 } 2302 2303 /** 2304 * e1000_alloc_ring_dma - allocate memory for a ring structure 2305 **/ 2306 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2307 struct e1000_ring *ring) 2308 { 2309 struct pci_dev *pdev = adapter->pdev; 2310 2311 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2312 GFP_KERNEL); 2313 if (!ring->desc) 2314 return -ENOMEM; 2315 2316 return 0; 2317 } 2318 2319 /** 2320 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2321 * @tx_ring: Tx descriptor ring 2322 * 2323 * Return 0 on success, negative on failure 2324 **/ 2325 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2326 { 2327 struct e1000_adapter *adapter = tx_ring->adapter; 2328 int err = -ENOMEM, size; 2329 2330 size = sizeof(struct e1000_buffer) * tx_ring->count; 2331 tx_ring->buffer_info = vzalloc(size); 2332 if (!tx_ring->buffer_info) 2333 goto err; 2334 2335 /* round up to nearest 4K */ 2336 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2337 tx_ring->size = ALIGN(tx_ring->size, 4096); 2338 2339 err = e1000_alloc_ring_dma(adapter, tx_ring); 2340 if (err) 2341 goto err; 2342 2343 tx_ring->next_to_use = 0; 2344 tx_ring->next_to_clean = 0; 2345 2346 return 0; 2347 err: 2348 vfree(tx_ring->buffer_info); 2349 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2350 return err; 2351 } 2352 2353 /** 2354 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2355 * @rx_ring: Rx descriptor ring 2356 * 2357 * Returns 0 on success, negative on failure 2358 **/ 2359 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2360 { 2361 struct e1000_adapter *adapter = rx_ring->adapter; 2362 struct e1000_buffer *buffer_info; 2363 int i, size, desc_len, err = -ENOMEM; 2364 2365 size = sizeof(struct e1000_buffer) * rx_ring->count; 2366 rx_ring->buffer_info = vzalloc(size); 2367 if (!rx_ring->buffer_info) 2368 goto err; 2369 2370 for (i = 0; i < rx_ring->count; i++) { 2371 buffer_info = &rx_ring->buffer_info[i]; 2372 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2373 sizeof(struct e1000_ps_page), 2374 GFP_KERNEL); 2375 if (!buffer_info->ps_pages) 2376 goto err_pages; 2377 } 2378 2379 desc_len = sizeof(union e1000_rx_desc_packet_split); 2380 2381 /* Round up to nearest 4K */ 2382 rx_ring->size = rx_ring->count * desc_len; 2383 rx_ring->size = ALIGN(rx_ring->size, 4096); 2384 2385 err = e1000_alloc_ring_dma(adapter, rx_ring); 2386 if (err) 2387 goto err_pages; 2388 2389 rx_ring->next_to_clean = 0; 2390 rx_ring->next_to_use = 0; 2391 rx_ring->rx_skb_top = NULL; 2392 2393 return 0; 2394 2395 err_pages: 2396 for (i = 0; i < rx_ring->count; i++) { 2397 buffer_info = &rx_ring->buffer_info[i]; 2398 kfree(buffer_info->ps_pages); 2399 } 2400 err: 2401 vfree(rx_ring->buffer_info); 2402 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2403 return err; 2404 } 2405 2406 /** 2407 * e1000_clean_tx_ring - Free Tx Buffers 2408 * @tx_ring: Tx descriptor ring 2409 **/ 2410 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2411 { 2412 struct e1000_adapter *adapter = tx_ring->adapter; 2413 struct e1000_buffer *buffer_info; 2414 unsigned long size; 2415 unsigned int i; 2416 2417 for (i = 0; i < tx_ring->count; i++) { 2418 buffer_info = &tx_ring->buffer_info[i]; 2419 e1000_put_txbuf(tx_ring, buffer_info, false); 2420 } 2421 2422 netdev_reset_queue(adapter->netdev); 2423 size = sizeof(struct e1000_buffer) * tx_ring->count; 2424 memset(tx_ring->buffer_info, 0, size); 2425 2426 memset(tx_ring->desc, 0, tx_ring->size); 2427 2428 tx_ring->next_to_use = 0; 2429 tx_ring->next_to_clean = 0; 2430 } 2431 2432 /** 2433 * e1000e_free_tx_resources - Free Tx Resources per Queue 2434 * @tx_ring: Tx descriptor ring 2435 * 2436 * Free all transmit software resources 2437 **/ 2438 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2439 { 2440 struct e1000_adapter *adapter = tx_ring->adapter; 2441 struct pci_dev *pdev = adapter->pdev; 2442 2443 e1000_clean_tx_ring(tx_ring); 2444 2445 vfree(tx_ring->buffer_info); 2446 tx_ring->buffer_info = NULL; 2447 2448 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2449 tx_ring->dma); 2450 tx_ring->desc = NULL; 2451 } 2452 2453 /** 2454 * e1000e_free_rx_resources - Free Rx Resources 2455 * @rx_ring: Rx descriptor ring 2456 * 2457 * Free all receive software resources 2458 **/ 2459 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2460 { 2461 struct e1000_adapter *adapter = rx_ring->adapter; 2462 struct pci_dev *pdev = adapter->pdev; 2463 int i; 2464 2465 e1000_clean_rx_ring(rx_ring); 2466 2467 for (i = 0; i < rx_ring->count; i++) 2468 kfree(rx_ring->buffer_info[i].ps_pages); 2469 2470 vfree(rx_ring->buffer_info); 2471 rx_ring->buffer_info = NULL; 2472 2473 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2474 rx_ring->dma); 2475 rx_ring->desc = NULL; 2476 } 2477 2478 /** 2479 * e1000_update_itr - update the dynamic ITR value based on statistics 2480 * @adapter: pointer to adapter 2481 * @itr_setting: current adapter->itr 2482 * @packets: the number of packets during this measurement interval 2483 * @bytes: the number of bytes during this measurement interval 2484 * 2485 * Stores a new ITR value based on packets and byte 2486 * counts during the last interrupt. The advantage of per interrupt 2487 * computation is faster updates and more accurate ITR for the current 2488 * traffic pattern. Constants in this function were computed 2489 * based on theoretical maximum wire speed and thresholds were set based 2490 * on testing data as well as attempting to minimize response time 2491 * while increasing bulk throughput. This functionality is controlled 2492 * by the InterruptThrottleRate module parameter. 2493 **/ 2494 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2495 { 2496 unsigned int retval = itr_setting; 2497 2498 if (packets == 0) 2499 return itr_setting; 2500 2501 switch (itr_setting) { 2502 case lowest_latency: 2503 /* handle TSO and jumbo frames */ 2504 if (bytes / packets > 8000) 2505 retval = bulk_latency; 2506 else if ((packets < 5) && (bytes > 512)) 2507 retval = low_latency; 2508 break; 2509 case low_latency: /* 50 usec aka 20000 ints/s */ 2510 if (bytes > 10000) { 2511 /* this if handles the TSO accounting */ 2512 if (bytes / packets > 8000) 2513 retval = bulk_latency; 2514 else if ((packets < 10) || ((bytes / packets) > 1200)) 2515 retval = bulk_latency; 2516 else if ((packets > 35)) 2517 retval = lowest_latency; 2518 } else if (bytes / packets > 2000) { 2519 retval = bulk_latency; 2520 } else if (packets <= 2 && bytes < 512) { 2521 retval = lowest_latency; 2522 } 2523 break; 2524 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2525 if (bytes > 25000) { 2526 if (packets > 35) 2527 retval = low_latency; 2528 } else if (bytes < 6000) { 2529 retval = low_latency; 2530 } 2531 break; 2532 } 2533 2534 return retval; 2535 } 2536 2537 static void e1000_set_itr(struct e1000_adapter *adapter) 2538 { 2539 u16 current_itr; 2540 u32 new_itr = adapter->itr; 2541 2542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2543 if (adapter->link_speed != SPEED_1000) { 2544 current_itr = 0; 2545 new_itr = 4000; 2546 goto set_itr_now; 2547 } 2548 2549 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2550 new_itr = 0; 2551 goto set_itr_now; 2552 } 2553 2554 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2555 adapter->total_tx_packets, 2556 adapter->total_tx_bytes); 2557 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2558 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2559 adapter->tx_itr = low_latency; 2560 2561 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2562 adapter->total_rx_packets, 2563 adapter->total_rx_bytes); 2564 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2565 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2566 adapter->rx_itr = low_latency; 2567 2568 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2569 2570 /* counts and packets in update_itr are dependent on these numbers */ 2571 switch (current_itr) { 2572 case lowest_latency: 2573 new_itr = 70000; 2574 break; 2575 case low_latency: 2576 new_itr = 20000; /* aka hwitr = ~200 */ 2577 break; 2578 case bulk_latency: 2579 new_itr = 4000; 2580 break; 2581 default: 2582 break; 2583 } 2584 2585 set_itr_now: 2586 if (new_itr != adapter->itr) { 2587 /* this attempts to bias the interrupt rate towards Bulk 2588 * by adding intermediate steps when interrupt rate is 2589 * increasing 2590 */ 2591 new_itr = new_itr > adapter->itr ? 2592 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2593 adapter->itr = new_itr; 2594 adapter->rx_ring->itr_val = new_itr; 2595 if (adapter->msix_entries) 2596 adapter->rx_ring->set_itr = 1; 2597 else 2598 e1000e_write_itr(adapter, new_itr); 2599 } 2600 } 2601 2602 /** 2603 * e1000e_write_itr - write the ITR value to the appropriate registers 2604 * @adapter: address of board private structure 2605 * @itr: new ITR value to program 2606 * 2607 * e1000e_write_itr determines if the adapter is in MSI-X mode 2608 * and, if so, writes the EITR registers with the ITR value. 2609 * Otherwise, it writes the ITR value into the ITR register. 2610 **/ 2611 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2612 { 2613 struct e1000_hw *hw = &adapter->hw; 2614 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2615 2616 if (adapter->msix_entries) { 2617 int vector; 2618 2619 for (vector = 0; vector < adapter->num_vectors; vector++) 2620 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2621 } else { 2622 ew32(ITR, new_itr); 2623 } 2624 } 2625 2626 /** 2627 * e1000_alloc_queues - Allocate memory for all rings 2628 * @adapter: board private structure to initialize 2629 **/ 2630 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2631 { 2632 int size = sizeof(struct e1000_ring); 2633 2634 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2635 if (!adapter->tx_ring) 2636 goto err; 2637 adapter->tx_ring->count = adapter->tx_ring_count; 2638 adapter->tx_ring->adapter = adapter; 2639 2640 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2641 if (!adapter->rx_ring) 2642 goto err; 2643 adapter->rx_ring->count = adapter->rx_ring_count; 2644 adapter->rx_ring->adapter = adapter; 2645 2646 return 0; 2647 err: 2648 e_err("Unable to allocate memory for queues\n"); 2649 kfree(adapter->rx_ring); 2650 kfree(adapter->tx_ring); 2651 return -ENOMEM; 2652 } 2653 2654 /** 2655 * e1000e_poll - NAPI Rx polling callback 2656 * @napi: struct associated with this polling callback 2657 * @budget: number of packets driver is allowed to process this poll 2658 **/ 2659 static int e1000e_poll(struct napi_struct *napi, int budget) 2660 { 2661 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2662 napi); 2663 struct e1000_hw *hw = &adapter->hw; 2664 struct net_device *poll_dev = adapter->netdev; 2665 int tx_cleaned = 1, work_done = 0; 2666 2667 adapter = netdev_priv(poll_dev); 2668 2669 if (!adapter->msix_entries || 2670 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2671 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2672 2673 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2674 2675 if (!tx_cleaned || work_done == budget) 2676 return budget; 2677 2678 /* Exit the polling mode, but don't re-enable interrupts if stack might 2679 * poll us due to busy-polling 2680 */ 2681 if (likely(napi_complete_done(napi, work_done))) { 2682 if (adapter->itr_setting & 3) 2683 e1000_set_itr(adapter); 2684 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2685 if (adapter->msix_entries) 2686 ew32(IMS, adapter->rx_ring->ims_val); 2687 else 2688 e1000_irq_enable(adapter); 2689 } 2690 } 2691 2692 return work_done; 2693 } 2694 2695 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2696 __always_unused __be16 proto, u16 vid) 2697 { 2698 struct e1000_adapter *adapter = netdev_priv(netdev); 2699 struct e1000_hw *hw = &adapter->hw; 2700 u32 vfta, index; 2701 2702 /* don't update vlan cookie if already programmed */ 2703 if ((adapter->hw.mng_cookie.status & 2704 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2705 (vid == adapter->mng_vlan_id)) 2706 return 0; 2707 2708 /* add VID to filter table */ 2709 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2710 index = (vid >> 5) & 0x7F; 2711 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2712 vfta |= BIT((vid & 0x1F)); 2713 hw->mac.ops.write_vfta(hw, index, vfta); 2714 } 2715 2716 set_bit(vid, adapter->active_vlans); 2717 2718 return 0; 2719 } 2720 2721 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2722 __always_unused __be16 proto, u16 vid) 2723 { 2724 struct e1000_adapter *adapter = netdev_priv(netdev); 2725 struct e1000_hw *hw = &adapter->hw; 2726 u32 vfta, index; 2727 2728 if ((adapter->hw.mng_cookie.status & 2729 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2730 (vid == adapter->mng_vlan_id)) { 2731 /* release control to f/w */ 2732 e1000e_release_hw_control(adapter); 2733 return 0; 2734 } 2735 2736 /* remove VID from filter table */ 2737 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2738 index = (vid >> 5) & 0x7F; 2739 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2740 vfta &= ~BIT((vid & 0x1F)); 2741 hw->mac.ops.write_vfta(hw, index, vfta); 2742 } 2743 2744 clear_bit(vid, adapter->active_vlans); 2745 2746 return 0; 2747 } 2748 2749 /** 2750 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2751 * @adapter: board private structure to initialize 2752 **/ 2753 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2754 { 2755 struct net_device *netdev = adapter->netdev; 2756 struct e1000_hw *hw = &adapter->hw; 2757 u32 rctl; 2758 2759 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2760 /* disable VLAN receive filtering */ 2761 rctl = er32(RCTL); 2762 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2763 ew32(RCTL, rctl); 2764 2765 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2766 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2767 adapter->mng_vlan_id); 2768 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2769 } 2770 } 2771 } 2772 2773 /** 2774 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2775 * @adapter: board private structure to initialize 2776 **/ 2777 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2778 { 2779 struct e1000_hw *hw = &adapter->hw; 2780 u32 rctl; 2781 2782 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2783 /* enable VLAN receive filtering */ 2784 rctl = er32(RCTL); 2785 rctl |= E1000_RCTL_VFE; 2786 rctl &= ~E1000_RCTL_CFIEN; 2787 ew32(RCTL, rctl); 2788 } 2789 } 2790 2791 /** 2792 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2793 * @adapter: board private structure to initialize 2794 **/ 2795 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2796 { 2797 struct e1000_hw *hw = &adapter->hw; 2798 u32 ctrl; 2799 2800 /* disable VLAN tag insert/strip */ 2801 ctrl = er32(CTRL); 2802 ctrl &= ~E1000_CTRL_VME; 2803 ew32(CTRL, ctrl); 2804 } 2805 2806 /** 2807 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2808 * @adapter: board private structure to initialize 2809 **/ 2810 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2811 { 2812 struct e1000_hw *hw = &adapter->hw; 2813 u32 ctrl; 2814 2815 /* enable VLAN tag insert/strip */ 2816 ctrl = er32(CTRL); 2817 ctrl |= E1000_CTRL_VME; 2818 ew32(CTRL, ctrl); 2819 } 2820 2821 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2822 { 2823 struct net_device *netdev = adapter->netdev; 2824 u16 vid = adapter->hw.mng_cookie.vlan_id; 2825 u16 old_vid = adapter->mng_vlan_id; 2826 2827 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2828 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2829 adapter->mng_vlan_id = vid; 2830 } 2831 2832 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2833 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2834 } 2835 2836 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2837 { 2838 u16 vid; 2839 2840 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2841 2842 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2843 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2844 } 2845 2846 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2847 { 2848 struct e1000_hw *hw = &adapter->hw; 2849 u32 manc, manc2h, mdef, i, j; 2850 2851 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2852 return; 2853 2854 manc = er32(MANC); 2855 2856 /* enable receiving management packets to the host. this will probably 2857 * generate destination unreachable messages from the host OS, but 2858 * the packets will be handled on SMBUS 2859 */ 2860 manc |= E1000_MANC_EN_MNG2HOST; 2861 manc2h = er32(MANC2H); 2862 2863 switch (hw->mac.type) { 2864 default: 2865 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2866 break; 2867 case e1000_82574: 2868 case e1000_82583: 2869 /* Check if IPMI pass-through decision filter already exists; 2870 * if so, enable it. 2871 */ 2872 for (i = 0, j = 0; i < 8; i++) { 2873 mdef = er32(MDEF(i)); 2874 2875 /* Ignore filters with anything other than IPMI ports */ 2876 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2877 continue; 2878 2879 /* Enable this decision filter in MANC2H */ 2880 if (mdef) 2881 manc2h |= BIT(i); 2882 2883 j |= mdef; 2884 } 2885 2886 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2887 break; 2888 2889 /* Create new decision filter in an empty filter */ 2890 for (i = 0, j = 0; i < 8; i++) 2891 if (er32(MDEF(i)) == 0) { 2892 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2893 E1000_MDEF_PORT_664)); 2894 manc2h |= BIT(1); 2895 j++; 2896 break; 2897 } 2898 2899 if (!j) 2900 e_warn("Unable to create IPMI pass-through filter\n"); 2901 break; 2902 } 2903 2904 ew32(MANC2H, manc2h); 2905 ew32(MANC, manc); 2906 } 2907 2908 /** 2909 * e1000_configure_tx - Configure Transmit Unit after Reset 2910 * @adapter: board private structure 2911 * 2912 * Configure the Tx unit of the MAC after a reset. 2913 **/ 2914 static void e1000_configure_tx(struct e1000_adapter *adapter) 2915 { 2916 struct e1000_hw *hw = &adapter->hw; 2917 struct e1000_ring *tx_ring = adapter->tx_ring; 2918 u64 tdba; 2919 u32 tdlen, tctl, tarc; 2920 2921 /* Setup the HW Tx Head and Tail descriptor pointers */ 2922 tdba = tx_ring->dma; 2923 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2924 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2925 ew32(TDBAH(0), (tdba >> 32)); 2926 ew32(TDLEN(0), tdlen); 2927 ew32(TDH(0), 0); 2928 ew32(TDT(0), 0); 2929 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2930 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2931 2932 writel(0, tx_ring->head); 2933 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2934 e1000e_update_tdt_wa(tx_ring, 0); 2935 else 2936 writel(0, tx_ring->tail); 2937 2938 /* Set the Tx Interrupt Delay register */ 2939 ew32(TIDV, adapter->tx_int_delay); 2940 /* Tx irq moderation */ 2941 ew32(TADV, adapter->tx_abs_int_delay); 2942 2943 if (adapter->flags2 & FLAG2_DMA_BURST) { 2944 u32 txdctl = er32(TXDCTL(0)); 2945 2946 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2947 E1000_TXDCTL_WTHRESH); 2948 /* set up some performance related parameters to encourage the 2949 * hardware to use the bus more efficiently in bursts, depends 2950 * on the tx_int_delay to be enabled, 2951 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2952 * hthresh = 1 ==> prefetch when one or more available 2953 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2954 * BEWARE: this seems to work but should be considered first if 2955 * there are Tx hangs or other Tx related bugs 2956 */ 2957 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2958 ew32(TXDCTL(0), txdctl); 2959 } 2960 /* erratum work around: set txdctl the same for both queues */ 2961 ew32(TXDCTL(1), er32(TXDCTL(0))); 2962 2963 /* Program the Transmit Control Register */ 2964 tctl = er32(TCTL); 2965 tctl &= ~E1000_TCTL_CT; 2966 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2967 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2968 2969 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2970 tarc = er32(TARC(0)); 2971 /* set the speed mode bit, we'll clear it if we're not at 2972 * gigabit link later 2973 */ 2974 #define SPEED_MODE_BIT BIT(21) 2975 tarc |= SPEED_MODE_BIT; 2976 ew32(TARC(0), tarc); 2977 } 2978 2979 /* errata: program both queues to unweighted RR */ 2980 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2981 tarc = er32(TARC(0)); 2982 tarc |= 1; 2983 ew32(TARC(0), tarc); 2984 tarc = er32(TARC(1)); 2985 tarc |= 1; 2986 ew32(TARC(1), tarc); 2987 } 2988 2989 /* Setup Transmit Descriptor Settings for eop descriptor */ 2990 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 2991 2992 /* only set IDE if we are delaying interrupts using the timers */ 2993 if (adapter->tx_int_delay) 2994 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2995 2996 /* enable Report Status bit */ 2997 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2998 2999 ew32(TCTL, tctl); 3000 3001 hw->mac.ops.config_collision_dist(hw); 3002 3003 /* SPT and KBL Si errata workaround to avoid data corruption */ 3004 if (hw->mac.type == e1000_pch_spt) { 3005 u32 reg_val; 3006 3007 reg_val = er32(IOSFPC); 3008 reg_val |= E1000_RCTL_RDMTS_HEX; 3009 ew32(IOSFPC, reg_val); 3010 3011 reg_val = er32(TARC(0)); 3012 /* SPT and KBL Si errata workaround to avoid Tx hang. 3013 * Dropping the number of outstanding requests from 3014 * 3 to 2 in order to avoid a buffer overrun. 3015 */ 3016 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3017 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3018 ew32(TARC(0), reg_val); 3019 } 3020 } 3021 3022 /** 3023 * e1000_setup_rctl - configure the receive control registers 3024 * @adapter: Board private structure 3025 **/ 3026 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3027 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3028 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3029 { 3030 struct e1000_hw *hw = &adapter->hw; 3031 u32 rctl, rfctl; 3032 u32 pages = 0; 3033 3034 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3035 * If jumbo frames not set, program related MAC/PHY registers 3036 * to h/w defaults 3037 */ 3038 if (hw->mac.type >= e1000_pch2lan) { 3039 s32 ret_val; 3040 3041 if (adapter->netdev->mtu > ETH_DATA_LEN) 3042 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3043 else 3044 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3045 3046 if (ret_val) 3047 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3048 } 3049 3050 /* Program MC offset vector base */ 3051 rctl = er32(RCTL); 3052 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3053 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3054 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3055 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3056 3057 /* Do not Store bad packets */ 3058 rctl &= ~E1000_RCTL_SBP; 3059 3060 /* Enable Long Packet receive */ 3061 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3062 rctl &= ~E1000_RCTL_LPE; 3063 else 3064 rctl |= E1000_RCTL_LPE; 3065 3066 /* Some systems expect that the CRC is included in SMBUS traffic. The 3067 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3068 * host memory when this is enabled 3069 */ 3070 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3071 rctl |= E1000_RCTL_SECRC; 3072 3073 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3074 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3075 u16 phy_data; 3076 3077 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3078 phy_data &= 0xfff8; 3079 phy_data |= BIT(2); 3080 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3081 3082 e1e_rphy(hw, 22, &phy_data); 3083 phy_data &= 0x0fff; 3084 phy_data |= BIT(14); 3085 e1e_wphy(hw, 0x10, 0x2823); 3086 e1e_wphy(hw, 0x11, 0x0003); 3087 e1e_wphy(hw, 22, phy_data); 3088 } 3089 3090 /* Setup buffer sizes */ 3091 rctl &= ~E1000_RCTL_SZ_4096; 3092 rctl |= E1000_RCTL_BSEX; 3093 switch (adapter->rx_buffer_len) { 3094 case 2048: 3095 default: 3096 rctl |= E1000_RCTL_SZ_2048; 3097 rctl &= ~E1000_RCTL_BSEX; 3098 break; 3099 case 4096: 3100 rctl |= E1000_RCTL_SZ_4096; 3101 break; 3102 case 8192: 3103 rctl |= E1000_RCTL_SZ_8192; 3104 break; 3105 case 16384: 3106 rctl |= E1000_RCTL_SZ_16384; 3107 break; 3108 } 3109 3110 /* Enable Extended Status in all Receive Descriptors */ 3111 rfctl = er32(RFCTL); 3112 rfctl |= E1000_RFCTL_EXTEN; 3113 ew32(RFCTL, rfctl); 3114 3115 /* 82571 and greater support packet-split where the protocol 3116 * header is placed in skb->data and the packet data is 3117 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3118 * In the case of a non-split, skb->data is linearly filled, 3119 * followed by the page buffers. Therefore, skb->data is 3120 * sized to hold the largest protocol header. 3121 * 3122 * allocations using alloc_page take too long for regular MTU 3123 * so only enable packet split for jumbo frames 3124 * 3125 * Using pages when the page size is greater than 16k wastes 3126 * a lot of memory, since we allocate 3 pages at all times 3127 * per packet. 3128 */ 3129 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3130 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3131 adapter->rx_ps_pages = pages; 3132 else 3133 adapter->rx_ps_pages = 0; 3134 3135 if (adapter->rx_ps_pages) { 3136 u32 psrctl = 0; 3137 3138 /* Enable Packet split descriptors */ 3139 rctl |= E1000_RCTL_DTYP_PS; 3140 3141 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3142 3143 switch (adapter->rx_ps_pages) { 3144 case 3: 3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3146 /* fall-through */ 3147 case 2: 3148 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3149 /* fall-through */ 3150 case 1: 3151 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3152 break; 3153 } 3154 3155 ew32(PSRCTL, psrctl); 3156 } 3157 3158 /* This is useful for sniffing bad packets. */ 3159 if (adapter->netdev->features & NETIF_F_RXALL) { 3160 /* UPE and MPE will be handled by normal PROMISC logic 3161 * in e1000e_set_rx_mode 3162 */ 3163 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3164 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3165 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3166 3167 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3168 E1000_RCTL_DPF | /* Allow filtered pause */ 3169 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3170 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3171 * and that breaks VLANs. 3172 */ 3173 } 3174 3175 ew32(RCTL, rctl); 3176 /* just started the receive unit, no need to restart */ 3177 adapter->flags &= ~FLAG_RESTART_NOW; 3178 } 3179 3180 /** 3181 * e1000_configure_rx - Configure Receive Unit after Reset 3182 * @adapter: board private structure 3183 * 3184 * Configure the Rx unit of the MAC after a reset. 3185 **/ 3186 static void e1000_configure_rx(struct e1000_adapter *adapter) 3187 { 3188 struct e1000_hw *hw = &adapter->hw; 3189 struct e1000_ring *rx_ring = adapter->rx_ring; 3190 u64 rdba; 3191 u32 rdlen, rctl, rxcsum, ctrl_ext; 3192 3193 if (adapter->rx_ps_pages) { 3194 /* this is a 32 byte descriptor */ 3195 rdlen = rx_ring->count * 3196 sizeof(union e1000_rx_desc_packet_split); 3197 adapter->clean_rx = e1000_clean_rx_irq_ps; 3198 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3199 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3200 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3201 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3202 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3203 } else { 3204 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3205 adapter->clean_rx = e1000_clean_rx_irq; 3206 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3207 } 3208 3209 /* disable receives while setting up the descriptors */ 3210 rctl = er32(RCTL); 3211 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3212 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3213 e1e_flush(); 3214 usleep_range(10000, 11000); 3215 3216 if (adapter->flags2 & FLAG2_DMA_BURST) { 3217 /* set the writeback threshold (only takes effect if the RDTR 3218 * is set). set GRAN=1 and write back up to 0x4 worth, and 3219 * enable prefetching of 0x20 Rx descriptors 3220 * granularity = 01 3221 * wthresh = 04, 3222 * hthresh = 04, 3223 * pthresh = 0x20 3224 */ 3225 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3226 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3227 } 3228 3229 /* set the Receive Delay Timer Register */ 3230 ew32(RDTR, adapter->rx_int_delay); 3231 3232 /* irq moderation */ 3233 ew32(RADV, adapter->rx_abs_int_delay); 3234 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3235 e1000e_write_itr(adapter, adapter->itr); 3236 3237 ctrl_ext = er32(CTRL_EXT); 3238 /* Auto-Mask interrupts upon ICR access */ 3239 ctrl_ext |= E1000_CTRL_EXT_IAME; 3240 ew32(IAM, 0xffffffff); 3241 ew32(CTRL_EXT, ctrl_ext); 3242 e1e_flush(); 3243 3244 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3245 * the Base and Length of the Rx Descriptor Ring 3246 */ 3247 rdba = rx_ring->dma; 3248 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3249 ew32(RDBAH(0), (rdba >> 32)); 3250 ew32(RDLEN(0), rdlen); 3251 ew32(RDH(0), 0); 3252 ew32(RDT(0), 0); 3253 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3254 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3255 3256 writel(0, rx_ring->head); 3257 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3258 e1000e_update_rdt_wa(rx_ring, 0); 3259 else 3260 writel(0, rx_ring->tail); 3261 3262 /* Enable Receive Checksum Offload for TCP and UDP */ 3263 rxcsum = er32(RXCSUM); 3264 if (adapter->netdev->features & NETIF_F_RXCSUM) 3265 rxcsum |= E1000_RXCSUM_TUOFL; 3266 else 3267 rxcsum &= ~E1000_RXCSUM_TUOFL; 3268 ew32(RXCSUM, rxcsum); 3269 3270 /* With jumbo frames, excessive C-state transition latencies result 3271 * in dropped transactions. 3272 */ 3273 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3274 u32 lat = 3275 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3276 adapter->max_frame_size) * 8 / 1000; 3277 3278 if (adapter->flags & FLAG_IS_ICH) { 3279 u32 rxdctl = er32(RXDCTL(0)); 3280 3281 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3282 } 3283 3284 dev_info(&adapter->pdev->dev, 3285 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3286 pm_qos_update_request(&adapter->pm_qos_req, lat); 3287 } else { 3288 pm_qos_update_request(&adapter->pm_qos_req, 3289 PM_QOS_DEFAULT_VALUE); 3290 } 3291 3292 /* Enable Receives */ 3293 ew32(RCTL, rctl); 3294 } 3295 3296 /** 3297 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3298 * @netdev: network interface device structure 3299 * 3300 * Writes multicast address list to the MTA hash table. 3301 * Returns: -ENOMEM on failure 3302 * 0 on no addresses written 3303 * X on writing X addresses to MTA 3304 */ 3305 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3306 { 3307 struct e1000_adapter *adapter = netdev_priv(netdev); 3308 struct e1000_hw *hw = &adapter->hw; 3309 struct netdev_hw_addr *ha; 3310 u8 *mta_list; 3311 int i; 3312 3313 if (netdev_mc_empty(netdev)) { 3314 /* nothing to program, so clear mc list */ 3315 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3316 return 0; 3317 } 3318 3319 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3320 if (!mta_list) 3321 return -ENOMEM; 3322 3323 /* update_mc_addr_list expects a packed array of only addresses. */ 3324 i = 0; 3325 netdev_for_each_mc_addr(ha, netdev) 3326 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3327 3328 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3329 kfree(mta_list); 3330 3331 return netdev_mc_count(netdev); 3332 } 3333 3334 /** 3335 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3336 * @netdev: network interface device structure 3337 * 3338 * Writes unicast address list to the RAR table. 3339 * Returns: -ENOMEM on failure/insufficient address space 3340 * 0 on no addresses written 3341 * X on writing X addresses to the RAR table 3342 **/ 3343 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3344 { 3345 struct e1000_adapter *adapter = netdev_priv(netdev); 3346 struct e1000_hw *hw = &adapter->hw; 3347 unsigned int rar_entries; 3348 int count = 0; 3349 3350 rar_entries = hw->mac.ops.rar_get_count(hw); 3351 3352 /* save a rar entry for our hardware address */ 3353 rar_entries--; 3354 3355 /* save a rar entry for the LAA workaround */ 3356 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3357 rar_entries--; 3358 3359 /* return ENOMEM indicating insufficient memory for addresses */ 3360 if (netdev_uc_count(netdev) > rar_entries) 3361 return -ENOMEM; 3362 3363 if (!netdev_uc_empty(netdev) && rar_entries) { 3364 struct netdev_hw_addr *ha; 3365 3366 /* write the addresses in reverse order to avoid write 3367 * combining 3368 */ 3369 netdev_for_each_uc_addr(ha, netdev) { 3370 int ret_val; 3371 3372 if (!rar_entries) 3373 break; 3374 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3375 if (ret_val < 0) 3376 return -ENOMEM; 3377 count++; 3378 } 3379 } 3380 3381 /* zero out the remaining RAR entries not used above */ 3382 for (; rar_entries > 0; rar_entries--) { 3383 ew32(RAH(rar_entries), 0); 3384 ew32(RAL(rar_entries), 0); 3385 } 3386 e1e_flush(); 3387 3388 return count; 3389 } 3390 3391 /** 3392 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3393 * @netdev: network interface device structure 3394 * 3395 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3396 * address list or the network interface flags are updated. This routine is 3397 * responsible for configuring the hardware for proper unicast, multicast, 3398 * promiscuous mode, and all-multi behavior. 3399 **/ 3400 static void e1000e_set_rx_mode(struct net_device *netdev) 3401 { 3402 struct e1000_adapter *adapter = netdev_priv(netdev); 3403 struct e1000_hw *hw = &adapter->hw; 3404 u32 rctl; 3405 3406 if (pm_runtime_suspended(netdev->dev.parent)) 3407 return; 3408 3409 /* Check for Promiscuous and All Multicast modes */ 3410 rctl = er32(RCTL); 3411 3412 /* clear the affected bits */ 3413 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3414 3415 if (netdev->flags & IFF_PROMISC) { 3416 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3417 /* Do not hardware filter VLANs in promisc mode */ 3418 e1000e_vlan_filter_disable(adapter); 3419 } else { 3420 int count; 3421 3422 if (netdev->flags & IFF_ALLMULTI) { 3423 rctl |= E1000_RCTL_MPE; 3424 } else { 3425 /* Write addresses to the MTA, if the attempt fails 3426 * then we should just turn on promiscuous mode so 3427 * that we can at least receive multicast traffic 3428 */ 3429 count = e1000e_write_mc_addr_list(netdev); 3430 if (count < 0) 3431 rctl |= E1000_RCTL_MPE; 3432 } 3433 e1000e_vlan_filter_enable(adapter); 3434 /* Write addresses to available RAR registers, if there is not 3435 * sufficient space to store all the addresses then enable 3436 * unicast promiscuous mode 3437 */ 3438 count = e1000e_write_uc_addr_list(netdev); 3439 if (count < 0) 3440 rctl |= E1000_RCTL_UPE; 3441 } 3442 3443 ew32(RCTL, rctl); 3444 3445 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3446 e1000e_vlan_strip_enable(adapter); 3447 else 3448 e1000e_vlan_strip_disable(adapter); 3449 } 3450 3451 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3452 { 3453 struct e1000_hw *hw = &adapter->hw; 3454 u32 mrqc, rxcsum; 3455 u32 rss_key[10]; 3456 int i; 3457 3458 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3459 for (i = 0; i < 10; i++) 3460 ew32(RSSRK(i), rss_key[i]); 3461 3462 /* Direct all traffic to queue 0 */ 3463 for (i = 0; i < 32; i++) 3464 ew32(RETA(i), 0); 3465 3466 /* Disable raw packet checksumming so that RSS hash is placed in 3467 * descriptor on writeback. 3468 */ 3469 rxcsum = er32(RXCSUM); 3470 rxcsum |= E1000_RXCSUM_PCSD; 3471 3472 ew32(RXCSUM, rxcsum); 3473 3474 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3475 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3476 E1000_MRQC_RSS_FIELD_IPV6 | 3477 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3478 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3479 3480 ew32(MRQC, mrqc); 3481 } 3482 3483 /** 3484 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3485 * @adapter: board private structure 3486 * @timinca: pointer to returned time increment attributes 3487 * 3488 * Get attributes for incrementing the System Time Register SYSTIML/H at 3489 * the default base frequency, and set the cyclecounter shift value. 3490 **/ 3491 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3492 { 3493 struct e1000_hw *hw = &adapter->hw; 3494 u32 incvalue, incperiod, shift; 3495 3496 /* Make sure clock is enabled on I217/I218/I219 before checking 3497 * the frequency 3498 */ 3499 if ((hw->mac.type >= e1000_pch_lpt) && 3500 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3501 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3502 u32 fextnvm7 = er32(FEXTNVM7); 3503 3504 if (!(fextnvm7 & BIT(0))) { 3505 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3506 e1e_flush(); 3507 } 3508 } 3509 3510 switch (hw->mac.type) { 3511 case e1000_pch2lan: 3512 /* Stable 96MHz frequency */ 3513 incperiod = INCPERIOD_96MHZ; 3514 incvalue = INCVALUE_96MHZ; 3515 shift = INCVALUE_SHIFT_96MHZ; 3516 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3517 break; 3518 case e1000_pch_lpt: 3519 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3520 /* Stable 96MHz frequency */ 3521 incperiod = INCPERIOD_96MHZ; 3522 incvalue = INCVALUE_96MHZ; 3523 shift = INCVALUE_SHIFT_96MHZ; 3524 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3525 } else { 3526 /* Stable 25MHz frequency */ 3527 incperiod = INCPERIOD_25MHZ; 3528 incvalue = INCVALUE_25MHZ; 3529 shift = INCVALUE_SHIFT_25MHZ; 3530 adapter->cc.shift = shift; 3531 } 3532 break; 3533 case e1000_pch_spt: 3534 /* Stable 24MHz frequency */ 3535 incperiod = INCPERIOD_24MHZ; 3536 incvalue = INCVALUE_24MHZ; 3537 shift = INCVALUE_SHIFT_24MHZ; 3538 adapter->cc.shift = shift; 3539 break; 3540 case e1000_pch_cnp: 3541 case e1000_pch_tgp: 3542 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3543 /* Stable 24MHz frequency */ 3544 incperiod = INCPERIOD_24MHZ; 3545 incvalue = INCVALUE_24MHZ; 3546 shift = INCVALUE_SHIFT_24MHZ; 3547 adapter->cc.shift = shift; 3548 } else { 3549 /* Stable 38400KHz frequency */ 3550 incperiod = INCPERIOD_38400KHZ; 3551 incvalue = INCVALUE_38400KHZ; 3552 shift = INCVALUE_SHIFT_38400KHZ; 3553 adapter->cc.shift = shift; 3554 } 3555 break; 3556 case e1000_82574: 3557 case e1000_82583: 3558 /* Stable 25MHz frequency */ 3559 incperiod = INCPERIOD_25MHZ; 3560 incvalue = INCVALUE_25MHZ; 3561 shift = INCVALUE_SHIFT_25MHZ; 3562 adapter->cc.shift = shift; 3563 break; 3564 default: 3565 return -EINVAL; 3566 } 3567 3568 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3569 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3570 3571 return 0; 3572 } 3573 3574 /** 3575 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3576 * @adapter: board private structure 3577 * 3578 * Outgoing time stamping can be enabled and disabled. Play nice and 3579 * disable it when requested, although it shouldn't cause any overhead 3580 * when no packet needs it. At most one packet in the queue may be 3581 * marked for time stamping, otherwise it would be impossible to tell 3582 * for sure to which packet the hardware time stamp belongs. 3583 * 3584 * Incoming time stamping has to be configured via the hardware filters. 3585 * Not all combinations are supported, in particular event type has to be 3586 * specified. Matching the kind of event packet is not supported, with the 3587 * exception of "all V2 events regardless of level 2 or 4". 3588 **/ 3589 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3590 struct hwtstamp_config *config) 3591 { 3592 struct e1000_hw *hw = &adapter->hw; 3593 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3594 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3595 u32 rxmtrl = 0; 3596 u16 rxudp = 0; 3597 bool is_l4 = false; 3598 bool is_l2 = false; 3599 u32 regval; 3600 3601 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3602 return -EINVAL; 3603 3604 /* flags reserved for future extensions - must be zero */ 3605 if (config->flags) 3606 return -EINVAL; 3607 3608 switch (config->tx_type) { 3609 case HWTSTAMP_TX_OFF: 3610 tsync_tx_ctl = 0; 3611 break; 3612 case HWTSTAMP_TX_ON: 3613 break; 3614 default: 3615 return -ERANGE; 3616 } 3617 3618 switch (config->rx_filter) { 3619 case HWTSTAMP_FILTER_NONE: 3620 tsync_rx_ctl = 0; 3621 break; 3622 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3623 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3624 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3625 is_l4 = true; 3626 break; 3627 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3628 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3629 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3630 is_l4 = true; 3631 break; 3632 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3633 /* Also time stamps V2 L2 Path Delay Request/Response */ 3634 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3635 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3636 is_l2 = true; 3637 break; 3638 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3639 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3640 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3641 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3642 is_l2 = true; 3643 break; 3644 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3645 /* Hardware cannot filter just V2 L4 Sync messages; 3646 * fall-through to V2 (both L2 and L4) Sync. 3647 */ 3648 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3649 /* Also time stamps V2 Path Delay Request/Response. */ 3650 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3651 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3652 is_l2 = true; 3653 is_l4 = true; 3654 break; 3655 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3656 /* Hardware cannot filter just V2 L4 Delay Request messages; 3657 * fall-through to V2 (both L2 and L4) Delay Request. 3658 */ 3659 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3660 /* Also time stamps V2 Path Delay Request/Response. */ 3661 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3662 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3663 is_l2 = true; 3664 is_l4 = true; 3665 break; 3666 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3667 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3668 /* Hardware cannot filter just V2 L4 or L2 Event messages; 3669 * fall-through to all V2 (both L2 and L4) Events. 3670 */ 3671 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3672 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3673 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3674 is_l2 = true; 3675 is_l4 = true; 3676 break; 3677 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3678 /* For V1, the hardware can only filter Sync messages or 3679 * Delay Request messages but not both so fall-through to 3680 * time stamp all packets. 3681 */ 3682 case HWTSTAMP_FILTER_NTP_ALL: 3683 case HWTSTAMP_FILTER_ALL: 3684 is_l2 = true; 3685 is_l4 = true; 3686 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3687 config->rx_filter = HWTSTAMP_FILTER_ALL; 3688 break; 3689 default: 3690 return -ERANGE; 3691 } 3692 3693 adapter->hwtstamp_config = *config; 3694 3695 /* enable/disable Tx h/w time stamping */ 3696 regval = er32(TSYNCTXCTL); 3697 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3698 regval |= tsync_tx_ctl; 3699 ew32(TSYNCTXCTL, regval); 3700 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3701 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3702 e_err("Timesync Tx Control register not set as expected\n"); 3703 return -EAGAIN; 3704 } 3705 3706 /* enable/disable Rx h/w time stamping */ 3707 regval = er32(TSYNCRXCTL); 3708 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3709 regval |= tsync_rx_ctl; 3710 ew32(TSYNCRXCTL, regval); 3711 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3712 E1000_TSYNCRXCTL_TYPE_MASK)) != 3713 (regval & (E1000_TSYNCRXCTL_ENABLED | 3714 E1000_TSYNCRXCTL_TYPE_MASK))) { 3715 e_err("Timesync Rx Control register not set as expected\n"); 3716 return -EAGAIN; 3717 } 3718 3719 /* L2: define ethertype filter for time stamped packets */ 3720 if (is_l2) 3721 rxmtrl |= ETH_P_1588; 3722 3723 /* define which PTP packets get time stamped */ 3724 ew32(RXMTRL, rxmtrl); 3725 3726 /* Filter by destination port */ 3727 if (is_l4) { 3728 rxudp = PTP_EV_PORT; 3729 cpu_to_be16s(&rxudp); 3730 } 3731 ew32(RXUDP, rxudp); 3732 3733 e1e_flush(); 3734 3735 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3736 er32(RXSTMPH); 3737 er32(TXSTMPH); 3738 3739 return 0; 3740 } 3741 3742 /** 3743 * e1000_configure - configure the hardware for Rx and Tx 3744 * @adapter: private board structure 3745 **/ 3746 static void e1000_configure(struct e1000_adapter *adapter) 3747 { 3748 struct e1000_ring *rx_ring = adapter->rx_ring; 3749 3750 e1000e_set_rx_mode(adapter->netdev); 3751 3752 e1000_restore_vlan(adapter); 3753 e1000_init_manageability_pt(adapter); 3754 3755 e1000_configure_tx(adapter); 3756 3757 if (adapter->netdev->features & NETIF_F_RXHASH) 3758 e1000e_setup_rss_hash(adapter); 3759 e1000_setup_rctl(adapter); 3760 e1000_configure_rx(adapter); 3761 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3762 } 3763 3764 /** 3765 * e1000e_power_up_phy - restore link in case the phy was powered down 3766 * @adapter: address of board private structure 3767 * 3768 * The phy may be powered down to save power and turn off link when the 3769 * driver is unloaded and wake on lan is not enabled (among others) 3770 * *** this routine MUST be followed by a call to e1000e_reset *** 3771 **/ 3772 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3773 { 3774 if (adapter->hw.phy.ops.power_up) 3775 adapter->hw.phy.ops.power_up(&adapter->hw); 3776 3777 adapter->hw.mac.ops.setup_link(&adapter->hw); 3778 } 3779 3780 /** 3781 * e1000_power_down_phy - Power down the PHY 3782 * 3783 * Power down the PHY so no link is implied when interface is down. 3784 * The PHY cannot be powered down if management or WoL is active. 3785 */ 3786 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3787 { 3788 if (adapter->hw.phy.ops.power_down) 3789 adapter->hw.phy.ops.power_down(&adapter->hw); 3790 } 3791 3792 /** 3793 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3794 * 3795 * We want to clear all pending descriptors from the TX ring. 3796 * zeroing happens when the HW reads the regs. We assign the ring itself as 3797 * the data of the next descriptor. We don't care about the data we are about 3798 * to reset the HW. 3799 */ 3800 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3801 { 3802 struct e1000_hw *hw = &adapter->hw; 3803 struct e1000_ring *tx_ring = adapter->tx_ring; 3804 struct e1000_tx_desc *tx_desc = NULL; 3805 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3806 u16 size = 512; 3807 3808 tctl = er32(TCTL); 3809 ew32(TCTL, tctl | E1000_TCTL_EN); 3810 tdt = er32(TDT(0)); 3811 BUG_ON(tdt != tx_ring->next_to_use); 3812 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3813 tx_desc->buffer_addr = tx_ring->dma; 3814 3815 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3816 tx_desc->upper.data = 0; 3817 /* flush descriptors to memory before notifying the HW */ 3818 wmb(); 3819 tx_ring->next_to_use++; 3820 if (tx_ring->next_to_use == tx_ring->count) 3821 tx_ring->next_to_use = 0; 3822 ew32(TDT(0), tx_ring->next_to_use); 3823 usleep_range(200, 250); 3824 } 3825 3826 /** 3827 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3828 * 3829 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3830 */ 3831 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3832 { 3833 u32 rctl, rxdctl; 3834 struct e1000_hw *hw = &adapter->hw; 3835 3836 rctl = er32(RCTL); 3837 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3838 e1e_flush(); 3839 usleep_range(100, 150); 3840 3841 rxdctl = er32(RXDCTL(0)); 3842 /* zero the lower 14 bits (prefetch and host thresholds) */ 3843 rxdctl &= 0xffffc000; 3844 3845 /* update thresholds: prefetch threshold to 31, host threshold to 1 3846 * and make sure the granularity is "descriptors" and not "cache lines" 3847 */ 3848 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3849 3850 ew32(RXDCTL(0), rxdctl); 3851 /* momentarily enable the RX ring for the changes to take effect */ 3852 ew32(RCTL, rctl | E1000_RCTL_EN); 3853 e1e_flush(); 3854 usleep_range(100, 150); 3855 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3856 } 3857 3858 /** 3859 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3860 * 3861 * In i219, the descriptor rings must be emptied before resetting the HW 3862 * or before changing the device state to D3 during runtime (runtime PM). 3863 * 3864 * Failure to do this will cause the HW to enter a unit hang state which can 3865 * only be released by PCI reset on the device 3866 * 3867 */ 3868 3869 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3870 { 3871 u16 hang_state; 3872 u32 fext_nvm11, tdlen; 3873 struct e1000_hw *hw = &adapter->hw; 3874 3875 /* First, disable MULR fix in FEXTNVM11 */ 3876 fext_nvm11 = er32(FEXTNVM11); 3877 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3878 ew32(FEXTNVM11, fext_nvm11); 3879 /* do nothing if we're not in faulty state, or if the queue is empty */ 3880 tdlen = er32(TDLEN(0)); 3881 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3882 &hang_state); 3883 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3884 return; 3885 e1000_flush_tx_ring(adapter); 3886 /* recheck, maybe the fault is caused by the rx ring */ 3887 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3888 &hang_state); 3889 if (hang_state & FLUSH_DESC_REQUIRED) 3890 e1000_flush_rx_ring(adapter); 3891 } 3892 3893 /** 3894 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3895 * @adapter: board private structure 3896 * 3897 * When the MAC is reset, all hardware bits for timesync will be reset to the 3898 * default values. This function will restore the settings last in place. 3899 * Since the clock SYSTIME registers are reset, we will simply restore the 3900 * cyclecounter to the kernel real clock time. 3901 **/ 3902 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3903 { 3904 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3905 struct e1000_hw *hw = &adapter->hw; 3906 unsigned long flags; 3907 u32 timinca; 3908 s32 ret_val; 3909 3910 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3911 return; 3912 3913 if (info->adjfreq) { 3914 /* restore the previous ptp frequency delta */ 3915 ret_val = info->adjfreq(info, adapter->ptp_delta); 3916 } else { 3917 /* set the default base frequency if no adjustment possible */ 3918 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3919 if (!ret_val) 3920 ew32(TIMINCA, timinca); 3921 } 3922 3923 if (ret_val) { 3924 dev_warn(&adapter->pdev->dev, 3925 "Failed to restore TIMINCA clock rate delta: %d\n", 3926 ret_val); 3927 return; 3928 } 3929 3930 /* reset the systim ns time counter */ 3931 spin_lock_irqsave(&adapter->systim_lock, flags); 3932 timecounter_init(&adapter->tc, &adapter->cc, 3933 ktime_to_ns(ktime_get_real())); 3934 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3935 3936 /* restore the previous hwtstamp configuration settings */ 3937 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3938 } 3939 3940 /** 3941 * e1000e_reset - bring the hardware into a known good state 3942 * 3943 * This function boots the hardware and enables some settings that 3944 * require a configuration cycle of the hardware - those cannot be 3945 * set/changed during runtime. After reset the device needs to be 3946 * properly configured for Rx, Tx etc. 3947 */ 3948 void e1000e_reset(struct e1000_adapter *adapter) 3949 { 3950 struct e1000_mac_info *mac = &adapter->hw.mac; 3951 struct e1000_fc_info *fc = &adapter->hw.fc; 3952 struct e1000_hw *hw = &adapter->hw; 3953 u32 tx_space, min_tx_space, min_rx_space; 3954 u32 pba = adapter->pba; 3955 u16 hwm; 3956 3957 /* reset Packet Buffer Allocation to default */ 3958 ew32(PBA, pba); 3959 3960 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3961 /* To maintain wire speed transmits, the Tx FIFO should be 3962 * large enough to accommodate two full transmit packets, 3963 * rounded up to the next 1KB and expressed in KB. Likewise, 3964 * the Rx FIFO should be large enough to accommodate at least 3965 * one full receive packet and is similarly rounded up and 3966 * expressed in KB. 3967 */ 3968 pba = er32(PBA); 3969 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3970 tx_space = pba >> 16; 3971 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3972 pba &= 0xffff; 3973 /* the Tx fifo also stores 16 bytes of information about the Tx 3974 * but don't include ethernet FCS because hardware appends it 3975 */ 3976 min_tx_space = (adapter->max_frame_size + 3977 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 3978 min_tx_space = ALIGN(min_tx_space, 1024); 3979 min_tx_space >>= 10; 3980 /* software strips receive CRC, so leave room for it */ 3981 min_rx_space = adapter->max_frame_size; 3982 min_rx_space = ALIGN(min_rx_space, 1024); 3983 min_rx_space >>= 10; 3984 3985 /* If current Tx allocation is less than the min Tx FIFO size, 3986 * and the min Tx FIFO size is less than the current Rx FIFO 3987 * allocation, take space away from current Rx allocation 3988 */ 3989 if ((tx_space < min_tx_space) && 3990 ((min_tx_space - tx_space) < pba)) { 3991 pba -= min_tx_space - tx_space; 3992 3993 /* if short on Rx space, Rx wins and must trump Tx 3994 * adjustment 3995 */ 3996 if (pba < min_rx_space) 3997 pba = min_rx_space; 3998 } 3999 4000 ew32(PBA, pba); 4001 } 4002 4003 /* flow control settings 4004 * 4005 * The high water mark must be low enough to fit one full frame 4006 * (or the size used for early receive) above it in the Rx FIFO. 4007 * Set it to the lower of: 4008 * - 90% of the Rx FIFO size, and 4009 * - the full Rx FIFO size minus one full frame 4010 */ 4011 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4012 fc->pause_time = 0xFFFF; 4013 else 4014 fc->pause_time = E1000_FC_PAUSE_TIME; 4015 fc->send_xon = true; 4016 fc->current_mode = fc->requested_mode; 4017 4018 switch (hw->mac.type) { 4019 case e1000_ich9lan: 4020 case e1000_ich10lan: 4021 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4022 pba = 14; 4023 ew32(PBA, pba); 4024 fc->high_water = 0x2800; 4025 fc->low_water = fc->high_water - 8; 4026 break; 4027 } 4028 /* fall-through */ 4029 default: 4030 hwm = min(((pba << 10) * 9 / 10), 4031 ((pba << 10) - adapter->max_frame_size)); 4032 4033 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4034 fc->low_water = fc->high_water - 8; 4035 break; 4036 case e1000_pchlan: 4037 /* Workaround PCH LOM adapter hangs with certain network 4038 * loads. If hangs persist, try disabling Tx flow control. 4039 */ 4040 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4041 fc->high_water = 0x3500; 4042 fc->low_water = 0x1500; 4043 } else { 4044 fc->high_water = 0x5000; 4045 fc->low_water = 0x3000; 4046 } 4047 fc->refresh_time = 0x1000; 4048 break; 4049 case e1000_pch2lan: 4050 case e1000_pch_lpt: 4051 case e1000_pch_spt: 4052 case e1000_pch_cnp: 4053 /* fall-through */ 4054 case e1000_pch_tgp: 4055 fc->refresh_time = 0xFFFF; 4056 fc->pause_time = 0xFFFF; 4057 4058 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4059 fc->high_water = 0x05C20; 4060 fc->low_water = 0x05048; 4061 break; 4062 } 4063 4064 pba = 14; 4065 ew32(PBA, pba); 4066 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4067 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4068 break; 4069 } 4070 4071 /* Alignment of Tx data is on an arbitrary byte boundary with the 4072 * maximum size per Tx descriptor limited only to the transmit 4073 * allocation of the packet buffer minus 96 bytes with an upper 4074 * limit of 24KB due to receive synchronization limitations. 4075 */ 4076 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4077 24 << 10); 4078 4079 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4080 * fit in receive buffer. 4081 */ 4082 if (adapter->itr_setting & 0x3) { 4083 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4084 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4085 dev_info(&adapter->pdev->dev, 4086 "Interrupt Throttle Rate off\n"); 4087 adapter->flags2 |= FLAG2_DISABLE_AIM; 4088 e1000e_write_itr(adapter, 0); 4089 } 4090 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4091 dev_info(&adapter->pdev->dev, 4092 "Interrupt Throttle Rate on\n"); 4093 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4094 adapter->itr = 20000; 4095 e1000e_write_itr(adapter, adapter->itr); 4096 } 4097 } 4098 4099 if (hw->mac.type >= e1000_pch_spt) 4100 e1000_flush_desc_rings(adapter); 4101 /* Allow time for pending master requests to run */ 4102 mac->ops.reset_hw(hw); 4103 4104 /* For parts with AMT enabled, let the firmware know 4105 * that the network interface is in control 4106 */ 4107 if (adapter->flags & FLAG_HAS_AMT) 4108 e1000e_get_hw_control(adapter); 4109 4110 ew32(WUC, 0); 4111 4112 if (mac->ops.init_hw(hw)) 4113 e_err("Hardware Error\n"); 4114 4115 e1000_update_mng_vlan(adapter); 4116 4117 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4118 ew32(VET, ETH_P_8021Q); 4119 4120 e1000e_reset_adaptive(hw); 4121 4122 /* restore systim and hwtstamp settings */ 4123 e1000e_systim_reset(adapter); 4124 4125 /* Set EEE advertisement as appropriate */ 4126 if (adapter->flags2 & FLAG2_HAS_EEE) { 4127 s32 ret_val; 4128 u16 adv_addr; 4129 4130 switch (hw->phy.type) { 4131 case e1000_phy_82579: 4132 adv_addr = I82579_EEE_ADVERTISEMENT; 4133 break; 4134 case e1000_phy_i217: 4135 adv_addr = I217_EEE_ADVERTISEMENT; 4136 break; 4137 default: 4138 dev_err(&adapter->pdev->dev, 4139 "Invalid PHY type setting EEE advertisement\n"); 4140 return; 4141 } 4142 4143 ret_val = hw->phy.ops.acquire(hw); 4144 if (ret_val) { 4145 dev_err(&adapter->pdev->dev, 4146 "EEE advertisement - unable to acquire PHY\n"); 4147 return; 4148 } 4149 4150 e1000_write_emi_reg_locked(hw, adv_addr, 4151 hw->dev_spec.ich8lan.eee_disable ? 4152 0 : adapter->eee_advert); 4153 4154 hw->phy.ops.release(hw); 4155 } 4156 4157 if (!netif_running(adapter->netdev) && 4158 !test_bit(__E1000_TESTING, &adapter->state)) 4159 e1000_power_down_phy(adapter); 4160 4161 e1000_get_phy_info(hw); 4162 4163 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4164 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4165 u16 phy_data = 0; 4166 /* speed up time to link by disabling smart power down, ignore 4167 * the return value of this function because there is nothing 4168 * different we would do if it failed 4169 */ 4170 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4171 phy_data &= ~IGP02E1000_PM_SPD; 4172 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4173 } 4174 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4175 u32 reg; 4176 4177 /* Fextnvm7 @ 0xe4[2] = 1 */ 4178 reg = er32(FEXTNVM7); 4179 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4180 ew32(FEXTNVM7, reg); 4181 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4182 reg = er32(FEXTNVM9); 4183 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4184 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4185 ew32(FEXTNVM9, reg); 4186 } 4187 4188 } 4189 4190 /** 4191 * e1000e_trigger_lsc - trigger an LSC interrupt 4192 * @adapter: 4193 * 4194 * Fire a link status change interrupt to start the watchdog. 4195 **/ 4196 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4197 { 4198 struct e1000_hw *hw = &adapter->hw; 4199 4200 if (adapter->msix_entries) 4201 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4202 else 4203 ew32(ICS, E1000_ICS_LSC); 4204 } 4205 4206 void e1000e_up(struct e1000_adapter *adapter) 4207 { 4208 /* hardware has been reset, we need to reload some things */ 4209 e1000_configure(adapter); 4210 4211 clear_bit(__E1000_DOWN, &adapter->state); 4212 4213 if (adapter->msix_entries) 4214 e1000_configure_msix(adapter); 4215 e1000_irq_enable(adapter); 4216 4217 /* Tx queue started by watchdog timer when link is up */ 4218 4219 e1000e_trigger_lsc(adapter); 4220 } 4221 4222 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4223 { 4224 struct e1000_hw *hw = &adapter->hw; 4225 4226 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4227 return; 4228 4229 /* flush pending descriptor writebacks to memory */ 4230 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4231 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4232 4233 /* execute the writes immediately */ 4234 e1e_flush(); 4235 4236 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4237 * write is successful 4238 */ 4239 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4240 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4241 4242 /* execute the writes immediately */ 4243 e1e_flush(); 4244 } 4245 4246 static void e1000e_update_stats(struct e1000_adapter *adapter); 4247 4248 /** 4249 * e1000e_down - quiesce the device and optionally reset the hardware 4250 * @adapter: board private structure 4251 * @reset: boolean flag to reset the hardware or not 4252 */ 4253 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4254 { 4255 struct net_device *netdev = adapter->netdev; 4256 struct e1000_hw *hw = &adapter->hw; 4257 u32 tctl, rctl; 4258 4259 /* signal that we're down so the interrupt handler does not 4260 * reschedule our watchdog timer 4261 */ 4262 set_bit(__E1000_DOWN, &adapter->state); 4263 4264 netif_carrier_off(netdev); 4265 4266 /* disable receives in the hardware */ 4267 rctl = er32(RCTL); 4268 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4269 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4270 /* flush and sleep below */ 4271 4272 netif_stop_queue(netdev); 4273 4274 /* disable transmits in the hardware */ 4275 tctl = er32(TCTL); 4276 tctl &= ~E1000_TCTL_EN; 4277 ew32(TCTL, tctl); 4278 4279 /* flush both disables and wait for them to finish */ 4280 e1e_flush(); 4281 usleep_range(10000, 11000); 4282 4283 e1000_irq_disable(adapter); 4284 4285 napi_synchronize(&adapter->napi); 4286 4287 del_timer_sync(&adapter->phy_info_timer); 4288 4289 spin_lock(&adapter->stats64_lock); 4290 e1000e_update_stats(adapter); 4291 spin_unlock(&adapter->stats64_lock); 4292 4293 e1000e_flush_descriptors(adapter); 4294 4295 adapter->link_speed = 0; 4296 adapter->link_duplex = 0; 4297 4298 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4299 if ((hw->mac.type >= e1000_pch2lan) && 4300 (adapter->netdev->mtu > ETH_DATA_LEN) && 4301 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4302 e_dbg("failed to disable jumbo frame workaround mode\n"); 4303 4304 if (!pci_channel_offline(adapter->pdev)) { 4305 if (reset) 4306 e1000e_reset(adapter); 4307 else if (hw->mac.type >= e1000_pch_spt) 4308 e1000_flush_desc_rings(adapter); 4309 } 4310 e1000_clean_tx_ring(adapter->tx_ring); 4311 e1000_clean_rx_ring(adapter->rx_ring); 4312 } 4313 4314 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4315 { 4316 might_sleep(); 4317 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4318 usleep_range(1000, 1100); 4319 e1000e_down(adapter, true); 4320 e1000e_up(adapter); 4321 clear_bit(__E1000_RESETTING, &adapter->state); 4322 } 4323 4324 /** 4325 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4326 * @hw: pointer to the HW structure 4327 * @systim: PHC time value read, sanitized and returned 4328 * @sts: structure to hold system time before and after reading SYSTIML, 4329 * may be NULL 4330 * 4331 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4332 * check to see that the time is incrementing at a reasonable 4333 * rate and is a multiple of incvalue. 4334 **/ 4335 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4336 struct ptp_system_timestamp *sts) 4337 { 4338 u64 time_delta, rem, temp; 4339 u64 systim_next; 4340 u32 incvalue; 4341 int i; 4342 4343 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4344 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4345 /* latch SYSTIMH on read of SYSTIML */ 4346 ptp_read_system_prets(sts); 4347 systim_next = (u64)er32(SYSTIML); 4348 ptp_read_system_postts(sts); 4349 systim_next |= (u64)er32(SYSTIMH) << 32; 4350 4351 time_delta = systim_next - systim; 4352 temp = time_delta; 4353 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4354 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4355 4356 systim = systim_next; 4357 4358 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4359 break; 4360 } 4361 4362 return systim; 4363 } 4364 4365 /** 4366 * e1000e_read_systim - read SYSTIM register 4367 * @adapter: board private structure 4368 * @sts: structure which will contain system time before and after reading 4369 * SYSTIML, may be NULL 4370 **/ 4371 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4372 struct ptp_system_timestamp *sts) 4373 { 4374 struct e1000_hw *hw = &adapter->hw; 4375 u32 systimel, systimel_2, systimeh; 4376 u64 systim; 4377 /* SYSTIMH latching upon SYSTIML read does not work well. 4378 * This means that if SYSTIML overflows after we read it but before 4379 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4380 * will experience a huge non linear increment in the systime value 4381 * to fix that we test for overflow and if true, we re-read systime. 4382 */ 4383 ptp_read_system_prets(sts); 4384 systimel = er32(SYSTIML); 4385 ptp_read_system_postts(sts); 4386 systimeh = er32(SYSTIMH); 4387 /* Is systimel is so large that overflow is possible? */ 4388 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4389 ptp_read_system_prets(sts); 4390 systimel_2 = er32(SYSTIML); 4391 ptp_read_system_postts(sts); 4392 if (systimel > systimel_2) { 4393 /* There was an overflow, read again SYSTIMH, and use 4394 * systimel_2 4395 */ 4396 systimeh = er32(SYSTIMH); 4397 systimel = systimel_2; 4398 } 4399 } 4400 systim = (u64)systimel; 4401 systim |= (u64)systimeh << 32; 4402 4403 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4404 systim = e1000e_sanitize_systim(hw, systim, sts); 4405 4406 return systim; 4407 } 4408 4409 /** 4410 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4411 * @cc: cyclecounter structure 4412 **/ 4413 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4414 { 4415 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4416 cc); 4417 4418 return e1000e_read_systim(adapter, NULL); 4419 } 4420 4421 /** 4422 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4423 * @adapter: board private structure to initialize 4424 * 4425 * e1000_sw_init initializes the Adapter private data structure. 4426 * Fields are initialized based on PCI device information and 4427 * OS network device settings (MTU size). 4428 **/ 4429 static int e1000_sw_init(struct e1000_adapter *adapter) 4430 { 4431 struct net_device *netdev = adapter->netdev; 4432 4433 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4434 adapter->rx_ps_bsize0 = 128; 4435 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4436 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4437 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4438 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4439 4440 spin_lock_init(&adapter->stats64_lock); 4441 4442 e1000e_set_interrupt_capability(adapter); 4443 4444 if (e1000_alloc_queues(adapter)) 4445 return -ENOMEM; 4446 4447 /* Setup hardware time stamping cyclecounter */ 4448 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4449 adapter->cc.read = e1000e_cyclecounter_read; 4450 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4451 adapter->cc.mult = 1; 4452 /* cc.shift set in e1000e_get_base_tininca() */ 4453 4454 spin_lock_init(&adapter->systim_lock); 4455 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4456 } 4457 4458 /* Explicitly disable IRQ since the NIC can be in any state. */ 4459 e1000_irq_disable(adapter); 4460 4461 set_bit(__E1000_DOWN, &adapter->state); 4462 return 0; 4463 } 4464 4465 /** 4466 * e1000_intr_msi_test - Interrupt Handler 4467 * @irq: interrupt number 4468 * @data: pointer to a network interface device structure 4469 **/ 4470 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4471 { 4472 struct net_device *netdev = data; 4473 struct e1000_adapter *adapter = netdev_priv(netdev); 4474 struct e1000_hw *hw = &adapter->hw; 4475 u32 icr = er32(ICR); 4476 4477 e_dbg("icr is %08X\n", icr); 4478 if (icr & E1000_ICR_RXSEQ) { 4479 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4480 /* Force memory writes to complete before acknowledging the 4481 * interrupt is handled. 4482 */ 4483 wmb(); 4484 } 4485 4486 return IRQ_HANDLED; 4487 } 4488 4489 /** 4490 * e1000_test_msi_interrupt - Returns 0 for successful test 4491 * @adapter: board private struct 4492 * 4493 * code flow taken from tg3.c 4494 **/ 4495 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4496 { 4497 struct net_device *netdev = adapter->netdev; 4498 struct e1000_hw *hw = &adapter->hw; 4499 int err; 4500 4501 /* poll_enable hasn't been called yet, so don't need disable */ 4502 /* clear any pending events */ 4503 er32(ICR); 4504 4505 /* free the real vector and request a test handler */ 4506 e1000_free_irq(adapter); 4507 e1000e_reset_interrupt_capability(adapter); 4508 4509 /* Assume that the test fails, if it succeeds then the test 4510 * MSI irq handler will unset this flag 4511 */ 4512 adapter->flags |= FLAG_MSI_TEST_FAILED; 4513 4514 err = pci_enable_msi(adapter->pdev); 4515 if (err) 4516 goto msi_test_failed; 4517 4518 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4519 netdev->name, netdev); 4520 if (err) { 4521 pci_disable_msi(adapter->pdev); 4522 goto msi_test_failed; 4523 } 4524 4525 /* Force memory writes to complete before enabling and firing an 4526 * interrupt. 4527 */ 4528 wmb(); 4529 4530 e1000_irq_enable(adapter); 4531 4532 /* fire an unusual interrupt on the test handler */ 4533 ew32(ICS, E1000_ICS_RXSEQ); 4534 e1e_flush(); 4535 msleep(100); 4536 4537 e1000_irq_disable(adapter); 4538 4539 rmb(); /* read flags after interrupt has been fired */ 4540 4541 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4542 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4543 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4544 } else { 4545 e_dbg("MSI interrupt test succeeded!\n"); 4546 } 4547 4548 free_irq(adapter->pdev->irq, netdev); 4549 pci_disable_msi(adapter->pdev); 4550 4551 msi_test_failed: 4552 e1000e_set_interrupt_capability(adapter); 4553 return e1000_request_irq(adapter); 4554 } 4555 4556 /** 4557 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4558 * @adapter: board private struct 4559 * 4560 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4561 **/ 4562 static int e1000_test_msi(struct e1000_adapter *adapter) 4563 { 4564 int err; 4565 u16 pci_cmd; 4566 4567 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4568 return 0; 4569 4570 /* disable SERR in case the MSI write causes a master abort */ 4571 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4572 if (pci_cmd & PCI_COMMAND_SERR) 4573 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4574 pci_cmd & ~PCI_COMMAND_SERR); 4575 4576 err = e1000_test_msi_interrupt(adapter); 4577 4578 /* re-enable SERR */ 4579 if (pci_cmd & PCI_COMMAND_SERR) { 4580 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4581 pci_cmd |= PCI_COMMAND_SERR; 4582 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4583 } 4584 4585 return err; 4586 } 4587 4588 /** 4589 * e1000e_open - Called when a network interface is made active 4590 * @netdev: network interface device structure 4591 * 4592 * Returns 0 on success, negative value on failure 4593 * 4594 * The open entry point is called when a network interface is made 4595 * active by the system (IFF_UP). At this point all resources needed 4596 * for transmit and receive operations are allocated, the interrupt 4597 * handler is registered with the OS, the watchdog timer is started, 4598 * and the stack is notified that the interface is ready. 4599 **/ 4600 int e1000e_open(struct net_device *netdev) 4601 { 4602 struct e1000_adapter *adapter = netdev_priv(netdev); 4603 struct e1000_hw *hw = &adapter->hw; 4604 struct pci_dev *pdev = adapter->pdev; 4605 int err; 4606 4607 /* disallow open during test */ 4608 if (test_bit(__E1000_TESTING, &adapter->state)) 4609 return -EBUSY; 4610 4611 pm_runtime_get_sync(&pdev->dev); 4612 4613 netif_carrier_off(netdev); 4614 netif_stop_queue(netdev); 4615 4616 /* allocate transmit descriptors */ 4617 err = e1000e_setup_tx_resources(adapter->tx_ring); 4618 if (err) 4619 goto err_setup_tx; 4620 4621 /* allocate receive descriptors */ 4622 err = e1000e_setup_rx_resources(adapter->rx_ring); 4623 if (err) 4624 goto err_setup_rx; 4625 4626 /* If AMT is enabled, let the firmware know that the network 4627 * interface is now open and reset the part to a known state. 4628 */ 4629 if (adapter->flags & FLAG_HAS_AMT) { 4630 e1000e_get_hw_control(adapter); 4631 e1000e_reset(adapter); 4632 } 4633 4634 e1000e_power_up_phy(adapter); 4635 4636 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4637 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4638 e1000_update_mng_vlan(adapter); 4639 4640 /* DMA latency requirement to workaround jumbo issue */ 4641 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 4642 PM_QOS_DEFAULT_VALUE); 4643 4644 /* before we allocate an interrupt, we must be ready to handle it. 4645 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4646 * as soon as we call pci_request_irq, so we have to setup our 4647 * clean_rx handler before we do so. 4648 */ 4649 e1000_configure(adapter); 4650 4651 err = e1000_request_irq(adapter); 4652 if (err) 4653 goto err_req_irq; 4654 4655 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4656 * ignore e1000e MSI messages, which means we need to test our MSI 4657 * interrupt now 4658 */ 4659 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4660 err = e1000_test_msi(adapter); 4661 if (err) { 4662 e_err("Interrupt allocation failed\n"); 4663 goto err_req_irq; 4664 } 4665 } 4666 4667 /* From here on the code is the same as e1000e_up() */ 4668 clear_bit(__E1000_DOWN, &adapter->state); 4669 4670 napi_enable(&adapter->napi); 4671 4672 e1000_irq_enable(adapter); 4673 4674 adapter->tx_hang_recheck = false; 4675 4676 hw->mac.get_link_status = true; 4677 pm_runtime_put(&pdev->dev); 4678 4679 e1000e_trigger_lsc(adapter); 4680 4681 return 0; 4682 4683 err_req_irq: 4684 pm_qos_remove_request(&adapter->pm_qos_req); 4685 e1000e_release_hw_control(adapter); 4686 e1000_power_down_phy(adapter); 4687 e1000e_free_rx_resources(adapter->rx_ring); 4688 err_setup_rx: 4689 e1000e_free_tx_resources(adapter->tx_ring); 4690 err_setup_tx: 4691 e1000e_reset(adapter); 4692 pm_runtime_put_sync(&pdev->dev); 4693 4694 return err; 4695 } 4696 4697 /** 4698 * e1000e_close - Disables a network interface 4699 * @netdev: network interface device structure 4700 * 4701 * Returns 0, this is not allowed to fail 4702 * 4703 * The close entry point is called when an interface is de-activated 4704 * by the OS. The hardware is still under the drivers control, but 4705 * needs to be disabled. A global MAC reset is issued to stop the 4706 * hardware, and all transmit and receive resources are freed. 4707 **/ 4708 int e1000e_close(struct net_device *netdev) 4709 { 4710 struct e1000_adapter *adapter = netdev_priv(netdev); 4711 struct pci_dev *pdev = adapter->pdev; 4712 int count = E1000_CHECK_RESET_COUNT; 4713 4714 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4715 usleep_range(10000, 11000); 4716 4717 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4718 4719 pm_runtime_get_sync(&pdev->dev); 4720 4721 if (netif_device_present(netdev)) { 4722 e1000e_down(adapter, true); 4723 e1000_free_irq(adapter); 4724 4725 /* Link status message must follow this format */ 4726 netdev_info(netdev, "NIC Link is Down\n"); 4727 } 4728 4729 napi_disable(&adapter->napi); 4730 4731 e1000e_free_tx_resources(adapter->tx_ring); 4732 e1000e_free_rx_resources(adapter->rx_ring); 4733 4734 /* kill manageability vlan ID if supported, but not if a vlan with 4735 * the same ID is registered on the host OS (let 8021q kill it) 4736 */ 4737 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4738 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4739 adapter->mng_vlan_id); 4740 4741 /* If AMT is enabled, let the firmware know that the network 4742 * interface is now closed 4743 */ 4744 if ((adapter->flags & FLAG_HAS_AMT) && 4745 !test_bit(__E1000_TESTING, &adapter->state)) 4746 e1000e_release_hw_control(adapter); 4747 4748 pm_qos_remove_request(&adapter->pm_qos_req); 4749 4750 pm_runtime_put_sync(&pdev->dev); 4751 4752 return 0; 4753 } 4754 4755 /** 4756 * e1000_set_mac - Change the Ethernet Address of the NIC 4757 * @netdev: network interface device structure 4758 * @p: pointer to an address structure 4759 * 4760 * Returns 0 on success, negative on failure 4761 **/ 4762 static int e1000_set_mac(struct net_device *netdev, void *p) 4763 { 4764 struct e1000_adapter *adapter = netdev_priv(netdev); 4765 struct e1000_hw *hw = &adapter->hw; 4766 struct sockaddr *addr = p; 4767 4768 if (!is_valid_ether_addr(addr->sa_data)) 4769 return -EADDRNOTAVAIL; 4770 4771 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4772 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4773 4774 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4775 4776 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4777 /* activate the work around */ 4778 e1000e_set_laa_state_82571(&adapter->hw, 1); 4779 4780 /* Hold a copy of the LAA in RAR[14] This is done so that 4781 * between the time RAR[0] gets clobbered and the time it 4782 * gets fixed (in e1000_watchdog), the actual LAA is in one 4783 * of the RARs and no incoming packets directed to this port 4784 * are dropped. Eventually the LAA will be in RAR[0] and 4785 * RAR[14] 4786 */ 4787 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4788 adapter->hw.mac.rar_entry_count - 1); 4789 } 4790 4791 return 0; 4792 } 4793 4794 /** 4795 * e1000e_update_phy_task - work thread to update phy 4796 * @work: pointer to our work struct 4797 * 4798 * this worker thread exists because we must acquire a 4799 * semaphore to read the phy, which we could msleep while 4800 * waiting for it, and we can't msleep in a timer. 4801 **/ 4802 static void e1000e_update_phy_task(struct work_struct *work) 4803 { 4804 struct e1000_adapter *adapter = container_of(work, 4805 struct e1000_adapter, 4806 update_phy_task); 4807 struct e1000_hw *hw = &adapter->hw; 4808 4809 if (test_bit(__E1000_DOWN, &adapter->state)) 4810 return; 4811 4812 e1000_get_phy_info(hw); 4813 4814 /* Enable EEE on 82579 after link up */ 4815 if (hw->phy.type >= e1000_phy_82579) 4816 e1000_set_eee_pchlan(hw); 4817 } 4818 4819 /** 4820 * e1000_update_phy_info - timre call-back to update PHY info 4821 * @data: pointer to adapter cast into an unsigned long 4822 * 4823 * Need to wait a few seconds after link up to get diagnostic information from 4824 * the phy 4825 **/ 4826 static void e1000_update_phy_info(struct timer_list *t) 4827 { 4828 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4829 4830 if (test_bit(__E1000_DOWN, &adapter->state)) 4831 return; 4832 4833 schedule_work(&adapter->update_phy_task); 4834 } 4835 4836 /** 4837 * e1000e_update_phy_stats - Update the PHY statistics counters 4838 * @adapter: board private structure 4839 * 4840 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4841 **/ 4842 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4843 { 4844 struct e1000_hw *hw = &adapter->hw; 4845 s32 ret_val; 4846 u16 phy_data; 4847 4848 ret_val = hw->phy.ops.acquire(hw); 4849 if (ret_val) 4850 return; 4851 4852 /* A page set is expensive so check if already on desired page. 4853 * If not, set to the page with the PHY status registers. 4854 */ 4855 hw->phy.addr = 1; 4856 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4857 &phy_data); 4858 if (ret_val) 4859 goto release; 4860 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4861 ret_val = hw->phy.ops.set_page(hw, 4862 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4863 if (ret_val) 4864 goto release; 4865 } 4866 4867 /* Single Collision Count */ 4868 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4869 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4870 if (!ret_val) 4871 adapter->stats.scc += phy_data; 4872 4873 /* Excessive Collision Count */ 4874 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4875 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4876 if (!ret_val) 4877 adapter->stats.ecol += phy_data; 4878 4879 /* Multiple Collision Count */ 4880 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4881 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4882 if (!ret_val) 4883 adapter->stats.mcc += phy_data; 4884 4885 /* Late Collision Count */ 4886 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4887 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4888 if (!ret_val) 4889 adapter->stats.latecol += phy_data; 4890 4891 /* Collision Count - also used for adaptive IFS */ 4892 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4893 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4894 if (!ret_val) 4895 hw->mac.collision_delta = phy_data; 4896 4897 /* Defer Count */ 4898 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4899 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4900 if (!ret_val) 4901 adapter->stats.dc += phy_data; 4902 4903 /* Transmit with no CRS */ 4904 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4905 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4906 if (!ret_val) 4907 adapter->stats.tncrs += phy_data; 4908 4909 release: 4910 hw->phy.ops.release(hw); 4911 } 4912 4913 /** 4914 * e1000e_update_stats - Update the board statistics counters 4915 * @adapter: board private structure 4916 **/ 4917 static void e1000e_update_stats(struct e1000_adapter *adapter) 4918 { 4919 struct net_device *netdev = adapter->netdev; 4920 struct e1000_hw *hw = &adapter->hw; 4921 struct pci_dev *pdev = adapter->pdev; 4922 4923 /* Prevent stats update while adapter is being reset, or if the pci 4924 * connection is down. 4925 */ 4926 if (adapter->link_speed == 0) 4927 return; 4928 if (pci_channel_offline(pdev)) 4929 return; 4930 4931 adapter->stats.crcerrs += er32(CRCERRS); 4932 adapter->stats.gprc += er32(GPRC); 4933 adapter->stats.gorc += er32(GORCL); 4934 er32(GORCH); /* Clear gorc */ 4935 adapter->stats.bprc += er32(BPRC); 4936 adapter->stats.mprc += er32(MPRC); 4937 adapter->stats.roc += er32(ROC); 4938 4939 adapter->stats.mpc += er32(MPC); 4940 4941 /* Half-duplex statistics */ 4942 if (adapter->link_duplex == HALF_DUPLEX) { 4943 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4944 e1000e_update_phy_stats(adapter); 4945 } else { 4946 adapter->stats.scc += er32(SCC); 4947 adapter->stats.ecol += er32(ECOL); 4948 adapter->stats.mcc += er32(MCC); 4949 adapter->stats.latecol += er32(LATECOL); 4950 adapter->stats.dc += er32(DC); 4951 4952 hw->mac.collision_delta = er32(COLC); 4953 4954 if ((hw->mac.type != e1000_82574) && 4955 (hw->mac.type != e1000_82583)) 4956 adapter->stats.tncrs += er32(TNCRS); 4957 } 4958 adapter->stats.colc += hw->mac.collision_delta; 4959 } 4960 4961 adapter->stats.xonrxc += er32(XONRXC); 4962 adapter->stats.xontxc += er32(XONTXC); 4963 adapter->stats.xoffrxc += er32(XOFFRXC); 4964 adapter->stats.xofftxc += er32(XOFFTXC); 4965 adapter->stats.gptc += er32(GPTC); 4966 adapter->stats.gotc += er32(GOTCL); 4967 er32(GOTCH); /* Clear gotc */ 4968 adapter->stats.rnbc += er32(RNBC); 4969 adapter->stats.ruc += er32(RUC); 4970 4971 adapter->stats.mptc += er32(MPTC); 4972 adapter->stats.bptc += er32(BPTC); 4973 4974 /* used for adaptive IFS */ 4975 4976 hw->mac.tx_packet_delta = er32(TPT); 4977 adapter->stats.tpt += hw->mac.tx_packet_delta; 4978 4979 adapter->stats.algnerrc += er32(ALGNERRC); 4980 adapter->stats.rxerrc += er32(RXERRC); 4981 adapter->stats.cexterr += er32(CEXTERR); 4982 adapter->stats.tsctc += er32(TSCTC); 4983 adapter->stats.tsctfc += er32(TSCTFC); 4984 4985 /* Fill out the OS statistics structure */ 4986 netdev->stats.multicast = adapter->stats.mprc; 4987 netdev->stats.collisions = adapter->stats.colc; 4988 4989 /* Rx Errors */ 4990 4991 /* RLEC on some newer hardware can be incorrect so build 4992 * our own version based on RUC and ROC 4993 */ 4994 netdev->stats.rx_errors = adapter->stats.rxerrc + 4995 adapter->stats.crcerrs + adapter->stats.algnerrc + 4996 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 4997 netdev->stats.rx_length_errors = adapter->stats.ruc + 4998 adapter->stats.roc; 4999 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5000 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5001 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5002 5003 /* Tx Errors */ 5004 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5005 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5006 netdev->stats.tx_window_errors = adapter->stats.latecol; 5007 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5008 5009 /* Tx Dropped needs to be maintained elsewhere */ 5010 5011 /* Management Stats */ 5012 adapter->stats.mgptc += er32(MGTPTC); 5013 adapter->stats.mgprc += er32(MGTPRC); 5014 adapter->stats.mgpdc += er32(MGTPDC); 5015 5016 /* Correctable ECC Errors */ 5017 if (hw->mac.type >= e1000_pch_lpt) { 5018 u32 pbeccsts = er32(PBECCSTS); 5019 5020 adapter->corr_errors += 5021 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5022 adapter->uncorr_errors += 5023 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5024 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5025 } 5026 } 5027 5028 /** 5029 * e1000_phy_read_status - Update the PHY register status snapshot 5030 * @adapter: board private structure 5031 **/ 5032 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5033 { 5034 struct e1000_hw *hw = &adapter->hw; 5035 struct e1000_phy_regs *phy = &adapter->phy_regs; 5036 5037 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5038 (er32(STATUS) & E1000_STATUS_LU) && 5039 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5040 int ret_val; 5041 5042 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5043 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5044 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5045 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5046 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5047 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5048 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5049 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5050 if (ret_val) 5051 e_warn("Error reading PHY register\n"); 5052 } else { 5053 /* Do not read PHY registers if link is not up 5054 * Set values to typical power-on defaults 5055 */ 5056 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5057 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5058 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5059 BMSR_ERCAP); 5060 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5061 ADVERTISE_ALL | ADVERTISE_CSMA); 5062 phy->lpa = 0; 5063 phy->expansion = EXPANSION_ENABLENPAGE; 5064 phy->ctrl1000 = ADVERTISE_1000FULL; 5065 phy->stat1000 = 0; 5066 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5067 } 5068 } 5069 5070 static void e1000_print_link_info(struct e1000_adapter *adapter) 5071 { 5072 struct e1000_hw *hw = &adapter->hw; 5073 u32 ctrl = er32(CTRL); 5074 5075 /* Link status message must follow this format for user tools */ 5076 netdev_info(adapter->netdev, 5077 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5078 adapter->link_speed, 5079 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5080 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5081 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5082 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5083 } 5084 5085 static bool e1000e_has_link(struct e1000_adapter *adapter) 5086 { 5087 struct e1000_hw *hw = &adapter->hw; 5088 bool link_active = false; 5089 s32 ret_val = 0; 5090 5091 /* get_link_status is set on LSC (link status) interrupt or 5092 * Rx sequence error interrupt. get_link_status will stay 5093 * true until the check_for_link establishes link 5094 * for copper adapters ONLY 5095 */ 5096 switch (hw->phy.media_type) { 5097 case e1000_media_type_copper: 5098 if (hw->mac.get_link_status) { 5099 ret_val = hw->mac.ops.check_for_link(hw); 5100 link_active = !hw->mac.get_link_status; 5101 } else { 5102 link_active = true; 5103 } 5104 break; 5105 case e1000_media_type_fiber: 5106 ret_val = hw->mac.ops.check_for_link(hw); 5107 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5108 break; 5109 case e1000_media_type_internal_serdes: 5110 ret_val = hw->mac.ops.check_for_link(hw); 5111 link_active = hw->mac.serdes_has_link; 5112 break; 5113 default: 5114 case e1000_media_type_unknown: 5115 break; 5116 } 5117 5118 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5119 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5120 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5121 e_info("Gigabit has been disabled, downgrading speed\n"); 5122 } 5123 5124 return link_active; 5125 } 5126 5127 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5128 { 5129 /* make sure the receive unit is started */ 5130 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5131 (adapter->flags & FLAG_RESTART_NOW)) { 5132 struct e1000_hw *hw = &adapter->hw; 5133 u32 rctl = er32(RCTL); 5134 5135 ew32(RCTL, rctl | E1000_RCTL_EN); 5136 adapter->flags &= ~FLAG_RESTART_NOW; 5137 } 5138 } 5139 5140 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5141 { 5142 struct e1000_hw *hw = &adapter->hw; 5143 5144 /* With 82574 controllers, PHY needs to be checked periodically 5145 * for hung state and reset, if two calls return true 5146 */ 5147 if (e1000_check_phy_82574(hw)) 5148 adapter->phy_hang_count++; 5149 else 5150 adapter->phy_hang_count = 0; 5151 5152 if (adapter->phy_hang_count > 1) { 5153 adapter->phy_hang_count = 0; 5154 e_dbg("PHY appears hung - resetting\n"); 5155 schedule_work(&adapter->reset_task); 5156 } 5157 } 5158 5159 static void e1000_watchdog_task(struct work_struct *work) 5160 { 5161 struct e1000_adapter *adapter = container_of(work, 5162 struct e1000_adapter, 5163 watchdog_task.work); 5164 struct net_device *netdev = adapter->netdev; 5165 struct e1000_mac_info *mac = &adapter->hw.mac; 5166 struct e1000_phy_info *phy = &adapter->hw.phy; 5167 struct e1000_ring *tx_ring = adapter->tx_ring; 5168 u32 dmoff_exit_timeout = 100, tries = 0; 5169 struct e1000_hw *hw = &adapter->hw; 5170 u32 link, tctl, pcim_state; 5171 5172 if (test_bit(__E1000_DOWN, &adapter->state)) 5173 return; 5174 5175 link = e1000e_has_link(adapter); 5176 if ((netif_carrier_ok(netdev)) && link) { 5177 /* Cancel scheduled suspend requests. */ 5178 pm_runtime_resume(netdev->dev.parent); 5179 5180 e1000e_enable_receives(adapter); 5181 goto link_up; 5182 } 5183 5184 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5185 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5186 e1000_update_mng_vlan(adapter); 5187 5188 if (link) { 5189 if (!netif_carrier_ok(netdev)) { 5190 bool txb2b = true; 5191 5192 /* Cancel scheduled suspend requests. */ 5193 pm_runtime_resume(netdev->dev.parent); 5194 5195 /* Checking if MAC is in DMoff state*/ 5196 pcim_state = er32(STATUS); 5197 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5198 if (tries++ == dmoff_exit_timeout) { 5199 e_dbg("Error in exiting dmoff\n"); 5200 break; 5201 } 5202 usleep_range(10000, 20000); 5203 pcim_state = er32(STATUS); 5204 5205 /* Checking if MAC exited DMoff state */ 5206 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5207 e1000_phy_hw_reset(&adapter->hw); 5208 } 5209 5210 /* update snapshot of PHY registers on LSC */ 5211 e1000_phy_read_status(adapter); 5212 mac->ops.get_link_up_info(&adapter->hw, 5213 &adapter->link_speed, 5214 &adapter->link_duplex); 5215 e1000_print_link_info(adapter); 5216 5217 /* check if SmartSpeed worked */ 5218 e1000e_check_downshift(hw); 5219 if (phy->speed_downgraded) 5220 netdev_warn(netdev, 5221 "Link Speed was downgraded by SmartSpeed\n"); 5222 5223 /* On supported PHYs, check for duplex mismatch only 5224 * if link has autonegotiated at 10/100 half 5225 */ 5226 if ((hw->phy.type == e1000_phy_igp_3 || 5227 hw->phy.type == e1000_phy_bm) && 5228 hw->mac.autoneg && 5229 (adapter->link_speed == SPEED_10 || 5230 adapter->link_speed == SPEED_100) && 5231 (adapter->link_duplex == HALF_DUPLEX)) { 5232 u16 autoneg_exp; 5233 5234 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5235 5236 if (!(autoneg_exp & EXPANSION_NWAY)) 5237 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5238 } 5239 5240 /* adjust timeout factor according to speed/duplex */ 5241 adapter->tx_timeout_factor = 1; 5242 switch (adapter->link_speed) { 5243 case SPEED_10: 5244 txb2b = false; 5245 adapter->tx_timeout_factor = 16; 5246 break; 5247 case SPEED_100: 5248 txb2b = false; 5249 adapter->tx_timeout_factor = 10; 5250 break; 5251 } 5252 5253 /* workaround: re-program speed mode bit after 5254 * link-up event 5255 */ 5256 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5257 !txb2b) { 5258 u32 tarc0; 5259 5260 tarc0 = er32(TARC(0)); 5261 tarc0 &= ~SPEED_MODE_BIT; 5262 ew32(TARC(0), tarc0); 5263 } 5264 5265 /* disable TSO for pcie and 10/100 speeds, to avoid 5266 * some hardware issues 5267 */ 5268 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5269 switch (adapter->link_speed) { 5270 case SPEED_10: 5271 case SPEED_100: 5272 e_info("10/100 speed: disabling TSO\n"); 5273 netdev->features &= ~NETIF_F_TSO; 5274 netdev->features &= ~NETIF_F_TSO6; 5275 break; 5276 case SPEED_1000: 5277 netdev->features |= NETIF_F_TSO; 5278 netdev->features |= NETIF_F_TSO6; 5279 break; 5280 default: 5281 /* oops */ 5282 break; 5283 } 5284 } 5285 5286 /* enable transmits in the hardware, need to do this 5287 * after setting TARC(0) 5288 */ 5289 tctl = er32(TCTL); 5290 tctl |= E1000_TCTL_EN; 5291 ew32(TCTL, tctl); 5292 5293 /* Perform any post-link-up configuration before 5294 * reporting link up. 5295 */ 5296 if (phy->ops.cfg_on_link_up) 5297 phy->ops.cfg_on_link_up(hw); 5298 5299 netif_wake_queue(netdev); 5300 netif_carrier_on(netdev); 5301 5302 if (!test_bit(__E1000_DOWN, &adapter->state)) 5303 mod_timer(&adapter->phy_info_timer, 5304 round_jiffies(jiffies + 2 * HZ)); 5305 } 5306 } else { 5307 if (netif_carrier_ok(netdev)) { 5308 adapter->link_speed = 0; 5309 adapter->link_duplex = 0; 5310 /* Link status message must follow this format */ 5311 netdev_info(netdev, "NIC Link is Down\n"); 5312 netif_carrier_off(netdev); 5313 netif_stop_queue(netdev); 5314 if (!test_bit(__E1000_DOWN, &adapter->state)) 5315 mod_timer(&adapter->phy_info_timer, 5316 round_jiffies(jiffies + 2 * HZ)); 5317 5318 /* 8000ES2LAN requires a Rx packet buffer work-around 5319 * on link down event; reset the controller to flush 5320 * the Rx packet buffer. 5321 */ 5322 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5323 adapter->flags |= FLAG_RESTART_NOW; 5324 else 5325 pm_schedule_suspend(netdev->dev.parent, 5326 LINK_TIMEOUT); 5327 } 5328 } 5329 5330 link_up: 5331 spin_lock(&adapter->stats64_lock); 5332 e1000e_update_stats(adapter); 5333 5334 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5335 adapter->tpt_old = adapter->stats.tpt; 5336 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5337 adapter->colc_old = adapter->stats.colc; 5338 5339 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5340 adapter->gorc_old = adapter->stats.gorc; 5341 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5342 adapter->gotc_old = adapter->stats.gotc; 5343 spin_unlock(&adapter->stats64_lock); 5344 5345 /* If the link is lost the controller stops DMA, but 5346 * if there is queued Tx work it cannot be done. So 5347 * reset the controller to flush the Tx packet buffers. 5348 */ 5349 if (!netif_carrier_ok(netdev) && 5350 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5351 adapter->flags |= FLAG_RESTART_NOW; 5352 5353 /* If reset is necessary, do it outside of interrupt context. */ 5354 if (adapter->flags & FLAG_RESTART_NOW) { 5355 schedule_work(&adapter->reset_task); 5356 /* return immediately since reset is imminent */ 5357 return; 5358 } 5359 5360 e1000e_update_adaptive(&adapter->hw); 5361 5362 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5363 if (adapter->itr_setting == 4) { 5364 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5365 * Total asymmetrical Tx or Rx gets ITR=8000; 5366 * everyone else is between 2000-8000. 5367 */ 5368 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5369 u32 dif = (adapter->gotc > adapter->gorc ? 5370 adapter->gotc - adapter->gorc : 5371 adapter->gorc - adapter->gotc) / 10000; 5372 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5373 5374 e1000e_write_itr(adapter, itr); 5375 } 5376 5377 /* Cause software interrupt to ensure Rx ring is cleaned */ 5378 if (adapter->msix_entries) 5379 ew32(ICS, adapter->rx_ring->ims_val); 5380 else 5381 ew32(ICS, E1000_ICS_RXDMT0); 5382 5383 /* flush pending descriptors to memory before detecting Tx hang */ 5384 e1000e_flush_descriptors(adapter); 5385 5386 /* Force detection of hung controller every watchdog period */ 5387 adapter->detect_tx_hung = true; 5388 5389 /* With 82571 controllers, LAA may be overwritten due to controller 5390 * reset from the other port. Set the appropriate LAA in RAR[0] 5391 */ 5392 if (e1000e_get_laa_state_82571(hw)) 5393 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5394 5395 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5396 e1000e_check_82574_phy_workaround(adapter); 5397 5398 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5399 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5400 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5401 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5402 er32(RXSTMPH); 5403 adapter->rx_hwtstamp_cleared++; 5404 } else { 5405 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5406 } 5407 } 5408 5409 /* Reset the timer */ 5410 if (!test_bit(__E1000_DOWN, &adapter->state)) 5411 queue_delayed_work(adapter->e1000_workqueue, 5412 &adapter->watchdog_task, 5413 round_jiffies(2 * HZ)); 5414 } 5415 5416 #define E1000_TX_FLAGS_CSUM 0x00000001 5417 #define E1000_TX_FLAGS_VLAN 0x00000002 5418 #define E1000_TX_FLAGS_TSO 0x00000004 5419 #define E1000_TX_FLAGS_IPV4 0x00000008 5420 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5421 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5422 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5423 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5424 5425 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5426 __be16 protocol) 5427 { 5428 struct e1000_context_desc *context_desc; 5429 struct e1000_buffer *buffer_info; 5430 unsigned int i; 5431 u32 cmd_length = 0; 5432 u16 ipcse = 0, mss; 5433 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5434 int err; 5435 5436 if (!skb_is_gso(skb)) 5437 return 0; 5438 5439 err = skb_cow_head(skb, 0); 5440 if (err < 0) 5441 return err; 5442 5443 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5444 mss = skb_shinfo(skb)->gso_size; 5445 if (protocol == htons(ETH_P_IP)) { 5446 struct iphdr *iph = ip_hdr(skb); 5447 iph->tot_len = 0; 5448 iph->check = 0; 5449 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5450 0, IPPROTO_TCP, 0); 5451 cmd_length = E1000_TXD_CMD_IP; 5452 ipcse = skb_transport_offset(skb) - 1; 5453 } else if (skb_is_gso_v6(skb)) { 5454 ipv6_hdr(skb)->payload_len = 0; 5455 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 5456 &ipv6_hdr(skb)->daddr, 5457 0, IPPROTO_TCP, 0); 5458 ipcse = 0; 5459 } 5460 ipcss = skb_network_offset(skb); 5461 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5462 tucss = skb_transport_offset(skb); 5463 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5464 5465 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5466 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5467 5468 i = tx_ring->next_to_use; 5469 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5470 buffer_info = &tx_ring->buffer_info[i]; 5471 5472 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5473 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5474 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5475 context_desc->upper_setup.tcp_fields.tucss = tucss; 5476 context_desc->upper_setup.tcp_fields.tucso = tucso; 5477 context_desc->upper_setup.tcp_fields.tucse = 0; 5478 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5479 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5480 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5481 5482 buffer_info->time_stamp = jiffies; 5483 buffer_info->next_to_watch = i; 5484 5485 i++; 5486 if (i == tx_ring->count) 5487 i = 0; 5488 tx_ring->next_to_use = i; 5489 5490 return 1; 5491 } 5492 5493 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5494 __be16 protocol) 5495 { 5496 struct e1000_adapter *adapter = tx_ring->adapter; 5497 struct e1000_context_desc *context_desc; 5498 struct e1000_buffer *buffer_info; 5499 unsigned int i; 5500 u8 css; 5501 u32 cmd_len = E1000_TXD_CMD_DEXT; 5502 5503 if (skb->ip_summed != CHECKSUM_PARTIAL) 5504 return false; 5505 5506 switch (protocol) { 5507 case cpu_to_be16(ETH_P_IP): 5508 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5509 cmd_len |= E1000_TXD_CMD_TCP; 5510 break; 5511 case cpu_to_be16(ETH_P_IPV6): 5512 /* XXX not handling all IPV6 headers */ 5513 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5514 cmd_len |= E1000_TXD_CMD_TCP; 5515 break; 5516 default: 5517 if (unlikely(net_ratelimit())) 5518 e_warn("checksum_partial proto=%x!\n", 5519 be16_to_cpu(protocol)); 5520 break; 5521 } 5522 5523 css = skb_checksum_start_offset(skb); 5524 5525 i = tx_ring->next_to_use; 5526 buffer_info = &tx_ring->buffer_info[i]; 5527 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5528 5529 context_desc->lower_setup.ip_config = 0; 5530 context_desc->upper_setup.tcp_fields.tucss = css; 5531 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5532 context_desc->upper_setup.tcp_fields.tucse = 0; 5533 context_desc->tcp_seg_setup.data = 0; 5534 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5535 5536 buffer_info->time_stamp = jiffies; 5537 buffer_info->next_to_watch = i; 5538 5539 i++; 5540 if (i == tx_ring->count) 5541 i = 0; 5542 tx_ring->next_to_use = i; 5543 5544 return true; 5545 } 5546 5547 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5548 unsigned int first, unsigned int max_per_txd, 5549 unsigned int nr_frags) 5550 { 5551 struct e1000_adapter *adapter = tx_ring->adapter; 5552 struct pci_dev *pdev = adapter->pdev; 5553 struct e1000_buffer *buffer_info; 5554 unsigned int len = skb_headlen(skb); 5555 unsigned int offset = 0, size, count = 0, i; 5556 unsigned int f, bytecount, segs; 5557 5558 i = tx_ring->next_to_use; 5559 5560 while (len) { 5561 buffer_info = &tx_ring->buffer_info[i]; 5562 size = min(len, max_per_txd); 5563 5564 buffer_info->length = size; 5565 buffer_info->time_stamp = jiffies; 5566 buffer_info->next_to_watch = i; 5567 buffer_info->dma = dma_map_single(&pdev->dev, 5568 skb->data + offset, 5569 size, DMA_TO_DEVICE); 5570 buffer_info->mapped_as_page = false; 5571 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5572 goto dma_error; 5573 5574 len -= size; 5575 offset += size; 5576 count++; 5577 5578 if (len) { 5579 i++; 5580 if (i == tx_ring->count) 5581 i = 0; 5582 } 5583 } 5584 5585 for (f = 0; f < nr_frags; f++) { 5586 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5587 5588 len = skb_frag_size(frag); 5589 offset = 0; 5590 5591 while (len) { 5592 i++; 5593 if (i == tx_ring->count) 5594 i = 0; 5595 5596 buffer_info = &tx_ring->buffer_info[i]; 5597 size = min(len, max_per_txd); 5598 5599 buffer_info->length = size; 5600 buffer_info->time_stamp = jiffies; 5601 buffer_info->next_to_watch = i; 5602 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5603 offset, size, 5604 DMA_TO_DEVICE); 5605 buffer_info->mapped_as_page = true; 5606 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5607 goto dma_error; 5608 5609 len -= size; 5610 offset += size; 5611 count++; 5612 } 5613 } 5614 5615 segs = skb_shinfo(skb)->gso_segs ? : 1; 5616 /* multiply data chunks by size of headers */ 5617 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5618 5619 tx_ring->buffer_info[i].skb = skb; 5620 tx_ring->buffer_info[i].segs = segs; 5621 tx_ring->buffer_info[i].bytecount = bytecount; 5622 tx_ring->buffer_info[first].next_to_watch = i; 5623 5624 return count; 5625 5626 dma_error: 5627 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5628 buffer_info->dma = 0; 5629 if (count) 5630 count--; 5631 5632 while (count--) { 5633 if (i == 0) 5634 i += tx_ring->count; 5635 i--; 5636 buffer_info = &tx_ring->buffer_info[i]; 5637 e1000_put_txbuf(tx_ring, buffer_info, true); 5638 } 5639 5640 return 0; 5641 } 5642 5643 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5644 { 5645 struct e1000_adapter *adapter = tx_ring->adapter; 5646 struct e1000_tx_desc *tx_desc = NULL; 5647 struct e1000_buffer *buffer_info; 5648 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5649 unsigned int i; 5650 5651 if (tx_flags & E1000_TX_FLAGS_TSO) { 5652 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5653 E1000_TXD_CMD_TSE; 5654 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5655 5656 if (tx_flags & E1000_TX_FLAGS_IPV4) 5657 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5658 } 5659 5660 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5661 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5662 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5663 } 5664 5665 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5666 txd_lower |= E1000_TXD_CMD_VLE; 5667 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5668 } 5669 5670 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5671 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5672 5673 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5674 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5675 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5676 } 5677 5678 i = tx_ring->next_to_use; 5679 5680 do { 5681 buffer_info = &tx_ring->buffer_info[i]; 5682 tx_desc = E1000_TX_DESC(*tx_ring, i); 5683 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5684 tx_desc->lower.data = cpu_to_le32(txd_lower | 5685 buffer_info->length); 5686 tx_desc->upper.data = cpu_to_le32(txd_upper); 5687 5688 i++; 5689 if (i == tx_ring->count) 5690 i = 0; 5691 } while (--count > 0); 5692 5693 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5694 5695 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5696 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5697 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5698 5699 /* Force memory writes to complete before letting h/w 5700 * know there are new descriptors to fetch. (Only 5701 * applicable for weak-ordered memory model archs, 5702 * such as IA-64). 5703 */ 5704 wmb(); 5705 5706 tx_ring->next_to_use = i; 5707 } 5708 5709 #define MINIMUM_DHCP_PACKET_SIZE 282 5710 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5711 struct sk_buff *skb) 5712 { 5713 struct e1000_hw *hw = &adapter->hw; 5714 u16 length, offset; 5715 5716 if (skb_vlan_tag_present(skb) && 5717 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5718 (adapter->hw.mng_cookie.status & 5719 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5720 return 0; 5721 5722 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5723 return 0; 5724 5725 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5726 return 0; 5727 5728 { 5729 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5730 struct udphdr *udp; 5731 5732 if (ip->protocol != IPPROTO_UDP) 5733 return 0; 5734 5735 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5736 if (ntohs(udp->dest) != 67) 5737 return 0; 5738 5739 offset = (u8 *)udp + 8 - skb->data; 5740 length = skb->len - offset; 5741 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5742 } 5743 5744 return 0; 5745 } 5746 5747 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5748 { 5749 struct e1000_adapter *adapter = tx_ring->adapter; 5750 5751 netif_stop_queue(adapter->netdev); 5752 /* Herbert's original patch had: 5753 * smp_mb__after_netif_stop_queue(); 5754 * but since that doesn't exist yet, just open code it. 5755 */ 5756 smp_mb(); 5757 5758 /* We need to check again in a case another CPU has just 5759 * made room available. 5760 */ 5761 if (e1000_desc_unused(tx_ring) < size) 5762 return -EBUSY; 5763 5764 /* A reprieve! */ 5765 netif_start_queue(adapter->netdev); 5766 ++adapter->restart_queue; 5767 return 0; 5768 } 5769 5770 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5771 { 5772 BUG_ON(size > tx_ring->count); 5773 5774 if (e1000_desc_unused(tx_ring) >= size) 5775 return 0; 5776 return __e1000_maybe_stop_tx(tx_ring, size); 5777 } 5778 5779 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5780 struct net_device *netdev) 5781 { 5782 struct e1000_adapter *adapter = netdev_priv(netdev); 5783 struct e1000_ring *tx_ring = adapter->tx_ring; 5784 unsigned int first; 5785 unsigned int tx_flags = 0; 5786 unsigned int len = skb_headlen(skb); 5787 unsigned int nr_frags; 5788 unsigned int mss; 5789 int count = 0; 5790 int tso; 5791 unsigned int f; 5792 __be16 protocol = vlan_get_protocol(skb); 5793 5794 if (test_bit(__E1000_DOWN, &adapter->state)) { 5795 dev_kfree_skb_any(skb); 5796 return NETDEV_TX_OK; 5797 } 5798 5799 if (skb->len <= 0) { 5800 dev_kfree_skb_any(skb); 5801 return NETDEV_TX_OK; 5802 } 5803 5804 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5805 * pad skb in order to meet this minimum size requirement 5806 */ 5807 if (skb_put_padto(skb, 17)) 5808 return NETDEV_TX_OK; 5809 5810 mss = skb_shinfo(skb)->gso_size; 5811 if (mss) { 5812 u8 hdr_len; 5813 5814 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5815 * points to just header, pull a few bytes of payload from 5816 * frags into skb->data 5817 */ 5818 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5819 /* we do this workaround for ES2LAN, but it is un-necessary, 5820 * avoiding it could save a lot of cycles 5821 */ 5822 if (skb->data_len && (hdr_len == len)) { 5823 unsigned int pull_size; 5824 5825 pull_size = min_t(unsigned int, 4, skb->data_len); 5826 if (!__pskb_pull_tail(skb, pull_size)) { 5827 e_err("__pskb_pull_tail failed.\n"); 5828 dev_kfree_skb_any(skb); 5829 return NETDEV_TX_OK; 5830 } 5831 len = skb_headlen(skb); 5832 } 5833 } 5834 5835 /* reserve a descriptor for the offload context */ 5836 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5837 count++; 5838 count++; 5839 5840 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5841 5842 nr_frags = skb_shinfo(skb)->nr_frags; 5843 for (f = 0; f < nr_frags; f++) 5844 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5845 adapter->tx_fifo_limit); 5846 5847 if (adapter->hw.mac.tx_pkt_filtering) 5848 e1000_transfer_dhcp_info(adapter, skb); 5849 5850 /* need: count + 2 desc gap to keep tail from touching 5851 * head, otherwise try next time 5852 */ 5853 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5854 return NETDEV_TX_BUSY; 5855 5856 if (skb_vlan_tag_present(skb)) { 5857 tx_flags |= E1000_TX_FLAGS_VLAN; 5858 tx_flags |= (skb_vlan_tag_get(skb) << 5859 E1000_TX_FLAGS_VLAN_SHIFT); 5860 } 5861 5862 first = tx_ring->next_to_use; 5863 5864 tso = e1000_tso(tx_ring, skb, protocol); 5865 if (tso < 0) { 5866 dev_kfree_skb_any(skb); 5867 return NETDEV_TX_OK; 5868 } 5869 5870 if (tso) 5871 tx_flags |= E1000_TX_FLAGS_TSO; 5872 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5873 tx_flags |= E1000_TX_FLAGS_CSUM; 5874 5875 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5876 * 82571 hardware supports TSO capabilities for IPv6 as well... 5877 * no longer assume, we must. 5878 */ 5879 if (protocol == htons(ETH_P_IP)) 5880 tx_flags |= E1000_TX_FLAGS_IPV4; 5881 5882 if (unlikely(skb->no_fcs)) 5883 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5884 5885 /* if count is 0 then mapping error has occurred */ 5886 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5887 nr_frags); 5888 if (count) { 5889 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5890 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5891 if (!adapter->tx_hwtstamp_skb) { 5892 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5893 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5894 adapter->tx_hwtstamp_skb = skb_get(skb); 5895 adapter->tx_hwtstamp_start = jiffies; 5896 schedule_work(&adapter->tx_hwtstamp_work); 5897 } else { 5898 adapter->tx_hwtstamp_skipped++; 5899 } 5900 } 5901 5902 skb_tx_timestamp(skb); 5903 5904 netdev_sent_queue(netdev, skb->len); 5905 e1000_tx_queue(tx_ring, tx_flags, count); 5906 /* Make sure there is space in the ring for the next send. */ 5907 e1000_maybe_stop_tx(tx_ring, 5908 (MAX_SKB_FRAGS * 5909 DIV_ROUND_UP(PAGE_SIZE, 5910 adapter->tx_fifo_limit) + 2)); 5911 5912 if (!netdev_xmit_more() || 5913 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5914 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5915 e1000e_update_tdt_wa(tx_ring, 5916 tx_ring->next_to_use); 5917 else 5918 writel(tx_ring->next_to_use, tx_ring->tail); 5919 } 5920 } else { 5921 dev_kfree_skb_any(skb); 5922 tx_ring->buffer_info[first].time_stamp = 0; 5923 tx_ring->next_to_use = first; 5924 } 5925 5926 return NETDEV_TX_OK; 5927 } 5928 5929 /** 5930 * e1000_tx_timeout - Respond to a Tx Hang 5931 * @netdev: network interface device structure 5932 **/ 5933 static void e1000_tx_timeout(struct net_device *netdev, unsigned int txqueue) 5934 { 5935 struct e1000_adapter *adapter = netdev_priv(netdev); 5936 5937 /* Do the reset outside of interrupt context */ 5938 adapter->tx_timeout_count++; 5939 schedule_work(&adapter->reset_task); 5940 } 5941 5942 static void e1000_reset_task(struct work_struct *work) 5943 { 5944 struct e1000_adapter *adapter; 5945 adapter = container_of(work, struct e1000_adapter, reset_task); 5946 5947 /* don't run the task if already down */ 5948 if (test_bit(__E1000_DOWN, &adapter->state)) 5949 return; 5950 5951 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5952 e1000e_dump(adapter); 5953 e_err("Reset adapter unexpectedly\n"); 5954 } 5955 e1000e_reinit_locked(adapter); 5956 } 5957 5958 /** 5959 * e1000_get_stats64 - Get System Network Statistics 5960 * @netdev: network interface device structure 5961 * @stats: rtnl_link_stats64 pointer 5962 * 5963 * Returns the address of the device statistics structure. 5964 **/ 5965 void e1000e_get_stats64(struct net_device *netdev, 5966 struct rtnl_link_stats64 *stats) 5967 { 5968 struct e1000_adapter *adapter = netdev_priv(netdev); 5969 5970 spin_lock(&adapter->stats64_lock); 5971 e1000e_update_stats(adapter); 5972 /* Fill out the OS statistics structure */ 5973 stats->rx_bytes = adapter->stats.gorc; 5974 stats->rx_packets = adapter->stats.gprc; 5975 stats->tx_bytes = adapter->stats.gotc; 5976 stats->tx_packets = adapter->stats.gptc; 5977 stats->multicast = adapter->stats.mprc; 5978 stats->collisions = adapter->stats.colc; 5979 5980 /* Rx Errors */ 5981 5982 /* RLEC on some newer hardware can be incorrect so build 5983 * our own version based on RUC and ROC 5984 */ 5985 stats->rx_errors = adapter->stats.rxerrc + 5986 adapter->stats.crcerrs + adapter->stats.algnerrc + 5987 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5988 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 5989 stats->rx_crc_errors = adapter->stats.crcerrs; 5990 stats->rx_frame_errors = adapter->stats.algnerrc; 5991 stats->rx_missed_errors = adapter->stats.mpc; 5992 5993 /* Tx Errors */ 5994 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5995 stats->tx_aborted_errors = adapter->stats.ecol; 5996 stats->tx_window_errors = adapter->stats.latecol; 5997 stats->tx_carrier_errors = adapter->stats.tncrs; 5998 5999 /* Tx Dropped needs to be maintained elsewhere */ 6000 6001 spin_unlock(&adapter->stats64_lock); 6002 } 6003 6004 /** 6005 * e1000_change_mtu - Change the Maximum Transfer Unit 6006 * @netdev: network interface device structure 6007 * @new_mtu: new value for maximum frame size 6008 * 6009 * Returns 0 on success, negative on failure 6010 **/ 6011 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6012 { 6013 struct e1000_adapter *adapter = netdev_priv(netdev); 6014 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6015 6016 /* Jumbo frame support */ 6017 if ((new_mtu > ETH_DATA_LEN) && 6018 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6019 e_err("Jumbo Frames not supported.\n"); 6020 return -EINVAL; 6021 } 6022 6023 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6024 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6025 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6026 (new_mtu > ETH_DATA_LEN)) { 6027 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6028 return -EINVAL; 6029 } 6030 6031 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6032 usleep_range(1000, 1100); 6033 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6034 adapter->max_frame_size = max_frame; 6035 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6036 netdev->mtu, new_mtu); 6037 netdev->mtu = new_mtu; 6038 6039 pm_runtime_get_sync(netdev->dev.parent); 6040 6041 if (netif_running(netdev)) 6042 e1000e_down(adapter, true); 6043 6044 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6045 * means we reserve 2 more, this pushes us to allocate from the next 6046 * larger slab size. 6047 * i.e. RXBUFFER_2048 --> size-4096 slab 6048 * However with the new *_jumbo_rx* routines, jumbo receives will use 6049 * fragmented skbs 6050 */ 6051 6052 if (max_frame <= 2048) 6053 adapter->rx_buffer_len = 2048; 6054 else 6055 adapter->rx_buffer_len = 4096; 6056 6057 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6058 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6059 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6060 6061 if (netif_running(netdev)) 6062 e1000e_up(adapter); 6063 else 6064 e1000e_reset(adapter); 6065 6066 pm_runtime_put_sync(netdev->dev.parent); 6067 6068 clear_bit(__E1000_RESETTING, &adapter->state); 6069 6070 return 0; 6071 } 6072 6073 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6074 int cmd) 6075 { 6076 struct e1000_adapter *adapter = netdev_priv(netdev); 6077 struct mii_ioctl_data *data = if_mii(ifr); 6078 6079 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6080 return -EOPNOTSUPP; 6081 6082 switch (cmd) { 6083 case SIOCGMIIPHY: 6084 data->phy_id = adapter->hw.phy.addr; 6085 break; 6086 case SIOCGMIIREG: 6087 e1000_phy_read_status(adapter); 6088 6089 switch (data->reg_num & 0x1F) { 6090 case MII_BMCR: 6091 data->val_out = adapter->phy_regs.bmcr; 6092 break; 6093 case MII_BMSR: 6094 data->val_out = adapter->phy_regs.bmsr; 6095 break; 6096 case MII_PHYSID1: 6097 data->val_out = (adapter->hw.phy.id >> 16); 6098 break; 6099 case MII_PHYSID2: 6100 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6101 break; 6102 case MII_ADVERTISE: 6103 data->val_out = adapter->phy_regs.advertise; 6104 break; 6105 case MII_LPA: 6106 data->val_out = adapter->phy_regs.lpa; 6107 break; 6108 case MII_EXPANSION: 6109 data->val_out = adapter->phy_regs.expansion; 6110 break; 6111 case MII_CTRL1000: 6112 data->val_out = adapter->phy_regs.ctrl1000; 6113 break; 6114 case MII_STAT1000: 6115 data->val_out = adapter->phy_regs.stat1000; 6116 break; 6117 case MII_ESTATUS: 6118 data->val_out = adapter->phy_regs.estatus; 6119 break; 6120 default: 6121 return -EIO; 6122 } 6123 break; 6124 case SIOCSMIIREG: 6125 default: 6126 return -EOPNOTSUPP; 6127 } 6128 return 0; 6129 } 6130 6131 /** 6132 * e1000e_hwtstamp_ioctl - control hardware time stamping 6133 * @netdev: network interface device structure 6134 * @ifreq: interface request 6135 * 6136 * Outgoing time stamping can be enabled and disabled. Play nice and 6137 * disable it when requested, although it shouldn't cause any overhead 6138 * when no packet needs it. At most one packet in the queue may be 6139 * marked for time stamping, otherwise it would be impossible to tell 6140 * for sure to which packet the hardware time stamp belongs. 6141 * 6142 * Incoming time stamping has to be configured via the hardware filters. 6143 * Not all combinations are supported, in particular event type has to be 6144 * specified. Matching the kind of event packet is not supported, with the 6145 * exception of "all V2 events regardless of level 2 or 4". 6146 **/ 6147 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6148 { 6149 struct e1000_adapter *adapter = netdev_priv(netdev); 6150 struct hwtstamp_config config; 6151 int ret_val; 6152 6153 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6154 return -EFAULT; 6155 6156 ret_val = e1000e_config_hwtstamp(adapter, &config); 6157 if (ret_val) 6158 return ret_val; 6159 6160 switch (config.rx_filter) { 6161 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6162 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6163 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6164 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6165 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6166 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6167 /* With V2 type filters which specify a Sync or Delay Request, 6168 * Path Delay Request/Response messages are also time stamped 6169 * by hardware so notify the caller the requested packets plus 6170 * some others are time stamped. 6171 */ 6172 config.rx_filter = HWTSTAMP_FILTER_SOME; 6173 break; 6174 default: 6175 break; 6176 } 6177 6178 return copy_to_user(ifr->ifr_data, &config, 6179 sizeof(config)) ? -EFAULT : 0; 6180 } 6181 6182 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6183 { 6184 struct e1000_adapter *adapter = netdev_priv(netdev); 6185 6186 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6187 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6188 } 6189 6190 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6191 { 6192 switch (cmd) { 6193 case SIOCGMIIPHY: 6194 case SIOCGMIIREG: 6195 case SIOCSMIIREG: 6196 return e1000_mii_ioctl(netdev, ifr, cmd); 6197 case SIOCSHWTSTAMP: 6198 return e1000e_hwtstamp_set(netdev, ifr); 6199 case SIOCGHWTSTAMP: 6200 return e1000e_hwtstamp_get(netdev, ifr); 6201 default: 6202 return -EOPNOTSUPP; 6203 } 6204 } 6205 6206 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6207 { 6208 struct e1000_hw *hw = &adapter->hw; 6209 u32 i, mac_reg, wuc; 6210 u16 phy_reg, wuc_enable; 6211 int retval; 6212 6213 /* copy MAC RARs to PHY RARs */ 6214 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6215 6216 retval = hw->phy.ops.acquire(hw); 6217 if (retval) { 6218 e_err("Could not acquire PHY\n"); 6219 return retval; 6220 } 6221 6222 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6223 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6224 if (retval) 6225 goto release; 6226 6227 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6228 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6229 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6230 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6231 (u16)(mac_reg & 0xFFFF)); 6232 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6233 (u16)((mac_reg >> 16) & 0xFFFF)); 6234 } 6235 6236 /* configure PHY Rx Control register */ 6237 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6238 mac_reg = er32(RCTL); 6239 if (mac_reg & E1000_RCTL_UPE) 6240 phy_reg |= BM_RCTL_UPE; 6241 if (mac_reg & E1000_RCTL_MPE) 6242 phy_reg |= BM_RCTL_MPE; 6243 phy_reg &= ~(BM_RCTL_MO_MASK); 6244 if (mac_reg & E1000_RCTL_MO_3) 6245 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6246 << BM_RCTL_MO_SHIFT); 6247 if (mac_reg & E1000_RCTL_BAM) 6248 phy_reg |= BM_RCTL_BAM; 6249 if (mac_reg & E1000_RCTL_PMCF) 6250 phy_reg |= BM_RCTL_PMCF; 6251 mac_reg = er32(CTRL); 6252 if (mac_reg & E1000_CTRL_RFCE) 6253 phy_reg |= BM_RCTL_RFCE; 6254 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6255 6256 wuc = E1000_WUC_PME_EN; 6257 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6258 wuc |= E1000_WUC_APME; 6259 6260 /* enable PHY wakeup in MAC register */ 6261 ew32(WUFC, wufc); 6262 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6263 E1000_WUC_PME_STATUS | wuc)); 6264 6265 /* configure and enable PHY wakeup in PHY registers */ 6266 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6267 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6268 6269 /* activate PHY wakeup */ 6270 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6271 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6272 if (retval) 6273 e_err("Could not set PHY Host Wakeup bit\n"); 6274 release: 6275 hw->phy.ops.release(hw); 6276 6277 return retval; 6278 } 6279 6280 static void e1000e_flush_lpic(struct pci_dev *pdev) 6281 { 6282 struct net_device *netdev = pci_get_drvdata(pdev); 6283 struct e1000_adapter *adapter = netdev_priv(netdev); 6284 struct e1000_hw *hw = &adapter->hw; 6285 u32 ret_val; 6286 6287 pm_runtime_get_sync(netdev->dev.parent); 6288 6289 ret_val = hw->phy.ops.acquire(hw); 6290 if (ret_val) 6291 goto fl_out; 6292 6293 pr_info("EEE TX LPI TIMER: %08X\n", 6294 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6295 6296 hw->phy.ops.release(hw); 6297 6298 fl_out: 6299 pm_runtime_put_sync(netdev->dev.parent); 6300 } 6301 6302 #ifdef CONFIG_PM_SLEEP 6303 /* S0ix implementation */ 6304 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6305 { 6306 struct e1000_hw *hw = &adapter->hw; 6307 u32 mac_data; 6308 u16 phy_data; 6309 6310 /* Disable the periodic inband message, 6311 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6312 */ 6313 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6314 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6315 phy_data |= BIT(10); 6316 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6317 6318 /* Make sure we don't exit K1 every time a new packet arrives 6319 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6320 */ 6321 e1e_rphy(hw, I217_CGFREG, &phy_data); 6322 phy_data |= BIT(5); 6323 e1e_wphy(hw, I217_CGFREG, phy_data); 6324 6325 /* Change the MAC/PHY interface to SMBus 6326 * Force the SMBus in PHY page769_23[0] = 1 6327 * Force the SMBus in MAC CTRL_EXT[11] = 1 6328 */ 6329 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6330 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6331 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6332 mac_data = er32(CTRL_EXT); 6333 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6334 ew32(CTRL_EXT, mac_data); 6335 6336 /* DFT control: PHY bit: page769_20[0] = 1 6337 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6338 */ 6339 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6340 phy_data |= BIT(0); 6341 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6342 6343 mac_data = er32(EXTCNF_CTRL); 6344 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6345 ew32(EXTCNF_CTRL, mac_data); 6346 6347 /* Check MAC Tx/Rx packet buffer pointers. 6348 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6349 * pending traffic indication that would prevent power gating. 6350 */ 6351 mac_data = er32(TDFH); 6352 if (mac_data) 6353 ew32(TDFH, 0); 6354 mac_data = er32(TDFT); 6355 if (mac_data) 6356 ew32(TDFT, 0); 6357 mac_data = er32(TDFHS); 6358 if (mac_data) 6359 ew32(TDFHS, 0); 6360 mac_data = er32(TDFTS); 6361 if (mac_data) 6362 ew32(TDFTS, 0); 6363 mac_data = er32(TDFPC); 6364 if (mac_data) 6365 ew32(TDFPC, 0); 6366 mac_data = er32(RDFH); 6367 if (mac_data) 6368 ew32(RDFH, 0); 6369 mac_data = er32(RDFT); 6370 if (mac_data) 6371 ew32(RDFT, 0); 6372 mac_data = er32(RDFHS); 6373 if (mac_data) 6374 ew32(RDFHS, 0); 6375 mac_data = er32(RDFTS); 6376 if (mac_data) 6377 ew32(RDFTS, 0); 6378 mac_data = er32(RDFPC); 6379 if (mac_data) 6380 ew32(RDFPC, 0); 6381 6382 /* Enable the Dynamic Power Gating in the MAC */ 6383 mac_data = er32(FEXTNVM7); 6384 mac_data |= BIT(22); 6385 ew32(FEXTNVM7, mac_data); 6386 6387 /* Disable the time synchronization clock */ 6388 mac_data = er32(FEXTNVM7); 6389 mac_data |= BIT(31); 6390 mac_data &= ~BIT(0); 6391 ew32(FEXTNVM7, mac_data); 6392 6393 /* Dynamic Power Gating Enable */ 6394 mac_data = er32(CTRL_EXT); 6395 mac_data |= BIT(3); 6396 ew32(CTRL_EXT, mac_data); 6397 6398 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6399 mac_data = er32(CTRL_EXT); 6400 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6401 ew32(CTRL_EXT, mac_data); 6402 6403 /* No MAC DPG gating SLP_S0 in modern standby 6404 * Switch the logic of the lanphypc to use PMC counter 6405 */ 6406 mac_data = er32(FEXTNVM5); 6407 mac_data |= BIT(7); 6408 ew32(FEXTNVM5, mac_data); 6409 } 6410 6411 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6412 { 6413 struct e1000_hw *hw = &adapter->hw; 6414 u32 mac_data; 6415 u16 phy_data; 6416 6417 /* Disable the Dynamic Power Gating in the MAC */ 6418 mac_data = er32(FEXTNVM7); 6419 mac_data &= 0xFFBFFFFF; 6420 ew32(FEXTNVM7, mac_data); 6421 6422 /* Enable the time synchronization clock */ 6423 mac_data = er32(FEXTNVM7); 6424 mac_data |= BIT(0); 6425 ew32(FEXTNVM7, mac_data); 6426 6427 /* Disable Dynamic Power Gating */ 6428 mac_data = er32(CTRL_EXT); 6429 mac_data &= 0xFFFFFFF7; 6430 ew32(CTRL_EXT, mac_data); 6431 6432 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6433 mac_data = er32(CTRL_EXT); 6434 mac_data &= 0xFFF7FFFF; 6435 ew32(CTRL_EXT, mac_data); 6436 6437 /* Revert the lanphypc logic to use the internal Gbe counter 6438 * and not the PMC counter 6439 */ 6440 mac_data = er32(FEXTNVM5); 6441 mac_data &= 0xFFFFFF7F; 6442 ew32(FEXTNVM5, mac_data); 6443 6444 /* Enable the periodic inband message, 6445 * Request PCIe clock in K1 page770_17[10:9] =01b 6446 */ 6447 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6448 phy_data &= 0xFBFF; 6449 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6450 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6451 6452 /* Return back configuration 6453 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6454 */ 6455 e1e_rphy(hw, I217_CGFREG, &phy_data); 6456 phy_data &= 0xFFDF; 6457 e1e_wphy(hw, I217_CGFREG, phy_data); 6458 6459 /* Change the MAC/PHY interface to Kumeran 6460 * Unforce the SMBus in PHY page769_23[0] = 0 6461 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6462 */ 6463 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6464 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6465 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6466 mac_data = er32(CTRL_EXT); 6467 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6468 ew32(CTRL_EXT, mac_data); 6469 } 6470 #endif /* CONFIG_PM_SLEEP */ 6471 6472 static int e1000e_pm_freeze(struct device *dev) 6473 { 6474 struct net_device *netdev = dev_get_drvdata(dev); 6475 struct e1000_adapter *adapter = netdev_priv(netdev); 6476 bool present; 6477 6478 rtnl_lock(); 6479 6480 present = netif_device_present(netdev); 6481 netif_device_detach(netdev); 6482 6483 if (present && netif_running(netdev)) { 6484 int count = E1000_CHECK_RESET_COUNT; 6485 6486 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6487 usleep_range(10000, 11000); 6488 6489 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6490 6491 /* Quiesce the device without resetting the hardware */ 6492 e1000e_down(adapter, false); 6493 e1000_free_irq(adapter); 6494 } 6495 rtnl_unlock(); 6496 6497 e1000e_reset_interrupt_capability(adapter); 6498 6499 /* Allow time for pending master requests to run */ 6500 e1000e_disable_pcie_master(&adapter->hw); 6501 6502 return 0; 6503 } 6504 6505 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6506 { 6507 struct net_device *netdev = pci_get_drvdata(pdev); 6508 struct e1000_adapter *adapter = netdev_priv(netdev); 6509 struct e1000_hw *hw = &adapter->hw; 6510 u32 ctrl, ctrl_ext, rctl, status; 6511 /* Runtime suspend should only enable wakeup for link changes */ 6512 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6513 int retval = 0; 6514 6515 status = er32(STATUS); 6516 if (status & E1000_STATUS_LU) 6517 wufc &= ~E1000_WUFC_LNKC; 6518 6519 if (wufc) { 6520 e1000_setup_rctl(adapter); 6521 e1000e_set_rx_mode(netdev); 6522 6523 /* turn on all-multi mode if wake on multicast is enabled */ 6524 if (wufc & E1000_WUFC_MC) { 6525 rctl = er32(RCTL); 6526 rctl |= E1000_RCTL_MPE; 6527 ew32(RCTL, rctl); 6528 } 6529 6530 ctrl = er32(CTRL); 6531 ctrl |= E1000_CTRL_ADVD3WUC; 6532 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6533 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6534 ew32(CTRL, ctrl); 6535 6536 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6537 adapter->hw.phy.media_type == 6538 e1000_media_type_internal_serdes) { 6539 /* keep the laser running in D3 */ 6540 ctrl_ext = er32(CTRL_EXT); 6541 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6542 ew32(CTRL_EXT, ctrl_ext); 6543 } 6544 6545 if (!runtime) 6546 e1000e_power_up_phy(adapter); 6547 6548 if (adapter->flags & FLAG_IS_ICH) 6549 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6550 6551 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6552 /* enable wakeup by the PHY */ 6553 retval = e1000_init_phy_wakeup(adapter, wufc); 6554 if (retval) 6555 return retval; 6556 } else { 6557 /* enable wakeup by the MAC */ 6558 ew32(WUFC, wufc); 6559 ew32(WUC, E1000_WUC_PME_EN); 6560 } 6561 } else { 6562 ew32(WUC, 0); 6563 ew32(WUFC, 0); 6564 6565 e1000_power_down_phy(adapter); 6566 } 6567 6568 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6569 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6570 } else if (hw->mac.type >= e1000_pch_lpt) { 6571 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6572 /* ULP does not support wake from unicast, multicast 6573 * or broadcast. 6574 */ 6575 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6576 6577 if (retval) 6578 return retval; 6579 } 6580 6581 /* Ensure that the appropriate bits are set in LPI_CTRL 6582 * for EEE in Sx 6583 */ 6584 if ((hw->phy.type >= e1000_phy_i217) && 6585 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6586 u16 lpi_ctrl = 0; 6587 6588 retval = hw->phy.ops.acquire(hw); 6589 if (!retval) { 6590 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6591 &lpi_ctrl); 6592 if (!retval) { 6593 if (adapter->eee_advert & 6594 hw->dev_spec.ich8lan.eee_lp_ability & 6595 I82579_EEE_100_SUPPORTED) 6596 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6597 if (adapter->eee_advert & 6598 hw->dev_spec.ich8lan.eee_lp_ability & 6599 I82579_EEE_1000_SUPPORTED) 6600 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6601 6602 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6603 lpi_ctrl); 6604 } 6605 } 6606 hw->phy.ops.release(hw); 6607 } 6608 6609 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6610 * would have already happened in close and is redundant. 6611 */ 6612 e1000e_release_hw_control(adapter); 6613 6614 pci_clear_master(pdev); 6615 6616 /* The pci-e switch on some quad port adapters will report a 6617 * correctable error when the MAC transitions from D0 to D3. To 6618 * prevent this we need to mask off the correctable errors on the 6619 * downstream port of the pci-e switch. 6620 * 6621 * We don't have the associated upstream bridge while assigning 6622 * the PCI device into guest. For example, the KVM on power is 6623 * one of the cases. 6624 */ 6625 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6626 struct pci_dev *us_dev = pdev->bus->self; 6627 u16 devctl; 6628 6629 if (!us_dev) 6630 return 0; 6631 6632 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6633 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6634 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6635 6636 pci_save_state(pdev); 6637 pci_prepare_to_sleep(pdev); 6638 6639 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6640 } 6641 6642 return 0; 6643 } 6644 6645 /** 6646 * __e1000e_disable_aspm - Disable ASPM states 6647 * @pdev: pointer to PCI device struct 6648 * @state: bit-mask of ASPM states to disable 6649 * @locked: indication if this context holds pci_bus_sem locked. 6650 * 6651 * Some devices *must* have certain ASPM states disabled per hardware errata. 6652 **/ 6653 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6654 { 6655 struct pci_dev *parent = pdev->bus->self; 6656 u16 aspm_dis_mask = 0; 6657 u16 pdev_aspmc, parent_aspmc; 6658 6659 switch (state) { 6660 case PCIE_LINK_STATE_L0S: 6661 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6662 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6663 /* fall-through - can't have L1 without L0s */ 6664 case PCIE_LINK_STATE_L1: 6665 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6666 break; 6667 default: 6668 return; 6669 } 6670 6671 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6672 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6673 6674 if (parent) { 6675 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6676 &parent_aspmc); 6677 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6678 } 6679 6680 /* Nothing to do if the ASPM states to be disabled already are */ 6681 if (!(pdev_aspmc & aspm_dis_mask) && 6682 (!parent || !(parent_aspmc & aspm_dis_mask))) 6683 return; 6684 6685 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6686 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6687 "L0s" : "", 6688 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6689 "L1" : ""); 6690 6691 #ifdef CONFIG_PCIEASPM 6692 if (locked) 6693 pci_disable_link_state_locked(pdev, state); 6694 else 6695 pci_disable_link_state(pdev, state); 6696 6697 /* Double-check ASPM control. If not disabled by the above, the 6698 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6699 * not enabled); override by writing PCI config space directly. 6700 */ 6701 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6702 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6703 6704 if (!(aspm_dis_mask & pdev_aspmc)) 6705 return; 6706 #endif 6707 6708 /* Both device and parent should have the same ASPM setting. 6709 * Disable ASPM in downstream component first and then upstream. 6710 */ 6711 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6712 6713 if (parent) 6714 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6715 aspm_dis_mask); 6716 } 6717 6718 /** 6719 * e1000e_disable_aspm - Disable ASPM states. 6720 * @pdev: pointer to PCI device struct 6721 * @state: bit-mask of ASPM states to disable 6722 * 6723 * This function acquires the pci_bus_sem! 6724 * Some devices *must* have certain ASPM states disabled per hardware errata. 6725 **/ 6726 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6727 { 6728 __e1000e_disable_aspm(pdev, state, 0); 6729 } 6730 6731 /** 6732 * e1000e_disable_aspm_locked Disable ASPM states. 6733 * @pdev: pointer to PCI device struct 6734 * @state: bit-mask of ASPM states to disable 6735 * 6736 * This function must be called with pci_bus_sem acquired! 6737 * Some devices *must* have certain ASPM states disabled per hardware errata. 6738 **/ 6739 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6740 { 6741 __e1000e_disable_aspm(pdev, state, 1); 6742 } 6743 6744 static int e1000e_pm_thaw(struct device *dev) 6745 { 6746 struct net_device *netdev = dev_get_drvdata(dev); 6747 struct e1000_adapter *adapter = netdev_priv(netdev); 6748 int rc = 0; 6749 6750 e1000e_set_interrupt_capability(adapter); 6751 6752 rtnl_lock(); 6753 if (netif_running(netdev)) { 6754 rc = e1000_request_irq(adapter); 6755 if (rc) 6756 goto err_irq; 6757 6758 e1000e_up(adapter); 6759 } 6760 6761 netif_device_attach(netdev); 6762 err_irq: 6763 rtnl_unlock(); 6764 6765 return rc; 6766 } 6767 6768 #ifdef CONFIG_PM 6769 static int __e1000_resume(struct pci_dev *pdev) 6770 { 6771 struct net_device *netdev = pci_get_drvdata(pdev); 6772 struct e1000_adapter *adapter = netdev_priv(netdev); 6773 struct e1000_hw *hw = &adapter->hw; 6774 u16 aspm_disable_flag = 0; 6775 6776 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6777 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6778 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6779 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6780 if (aspm_disable_flag) 6781 e1000e_disable_aspm(pdev, aspm_disable_flag); 6782 6783 pci_set_master(pdev); 6784 6785 if (hw->mac.type >= e1000_pch2lan) 6786 e1000_resume_workarounds_pchlan(&adapter->hw); 6787 6788 e1000e_power_up_phy(adapter); 6789 6790 /* report the system wakeup cause from S3/S4 */ 6791 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6792 u16 phy_data; 6793 6794 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6795 if (phy_data) { 6796 e_info("PHY Wakeup cause - %s\n", 6797 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6798 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6799 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6800 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6801 phy_data & E1000_WUS_LNKC ? 6802 "Link Status Change" : "other"); 6803 } 6804 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6805 } else { 6806 u32 wus = er32(WUS); 6807 6808 if (wus) { 6809 e_info("MAC Wakeup cause - %s\n", 6810 wus & E1000_WUS_EX ? "Unicast Packet" : 6811 wus & E1000_WUS_MC ? "Multicast Packet" : 6812 wus & E1000_WUS_BC ? "Broadcast Packet" : 6813 wus & E1000_WUS_MAG ? "Magic Packet" : 6814 wus & E1000_WUS_LNKC ? "Link Status Change" : 6815 "other"); 6816 } 6817 ew32(WUS, ~0); 6818 } 6819 6820 e1000e_reset(adapter); 6821 6822 e1000_init_manageability_pt(adapter); 6823 6824 /* If the controller has AMT, do not set DRV_LOAD until the interface 6825 * is up. For all other cases, let the f/w know that the h/w is now 6826 * under the control of the driver. 6827 */ 6828 if (!(adapter->flags & FLAG_HAS_AMT)) 6829 e1000e_get_hw_control(adapter); 6830 6831 return 0; 6832 } 6833 6834 #ifdef CONFIG_PM_SLEEP 6835 static int e1000e_pm_suspend(struct device *dev) 6836 { 6837 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6838 struct e1000_adapter *adapter = netdev_priv(netdev); 6839 struct pci_dev *pdev = to_pci_dev(dev); 6840 struct e1000_hw *hw = &adapter->hw; 6841 int rc; 6842 6843 e1000e_flush_lpic(pdev); 6844 6845 e1000e_pm_freeze(dev); 6846 6847 rc = __e1000_shutdown(pdev, false); 6848 if (rc) 6849 e1000e_pm_thaw(dev); 6850 6851 /* Introduce S0ix implementation */ 6852 if (hw->mac.type >= e1000_pch_cnp) 6853 e1000e_s0ix_entry_flow(adapter); 6854 6855 return rc; 6856 } 6857 6858 static int e1000e_pm_resume(struct device *dev) 6859 { 6860 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6861 struct e1000_adapter *adapter = netdev_priv(netdev); 6862 struct pci_dev *pdev = to_pci_dev(dev); 6863 struct e1000_hw *hw = &adapter->hw; 6864 int rc; 6865 6866 /* Introduce S0ix implementation */ 6867 if (hw->mac.type >= e1000_pch_cnp) 6868 e1000e_s0ix_exit_flow(adapter); 6869 6870 rc = __e1000_resume(pdev); 6871 if (rc) 6872 return rc; 6873 6874 return e1000e_pm_thaw(dev); 6875 } 6876 #endif /* CONFIG_PM_SLEEP */ 6877 6878 static int e1000e_pm_runtime_idle(struct device *dev) 6879 { 6880 struct net_device *netdev = dev_get_drvdata(dev); 6881 struct e1000_adapter *adapter = netdev_priv(netdev); 6882 u16 eee_lp; 6883 6884 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 6885 6886 if (!e1000e_has_link(adapter)) { 6887 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 6888 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 6889 } 6890 6891 return -EBUSY; 6892 } 6893 6894 static int e1000e_pm_runtime_resume(struct device *dev) 6895 { 6896 struct pci_dev *pdev = to_pci_dev(dev); 6897 struct net_device *netdev = pci_get_drvdata(pdev); 6898 struct e1000_adapter *adapter = netdev_priv(netdev); 6899 int rc; 6900 6901 rc = __e1000_resume(pdev); 6902 if (rc) 6903 return rc; 6904 6905 if (netdev->flags & IFF_UP) 6906 e1000e_up(adapter); 6907 6908 return rc; 6909 } 6910 6911 static int e1000e_pm_runtime_suspend(struct device *dev) 6912 { 6913 struct pci_dev *pdev = to_pci_dev(dev); 6914 struct net_device *netdev = pci_get_drvdata(pdev); 6915 struct e1000_adapter *adapter = netdev_priv(netdev); 6916 6917 if (netdev->flags & IFF_UP) { 6918 int count = E1000_CHECK_RESET_COUNT; 6919 6920 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6921 usleep_range(10000, 11000); 6922 6923 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6924 6925 /* Down the device without resetting the hardware */ 6926 e1000e_down(adapter, false); 6927 } 6928 6929 if (__e1000_shutdown(pdev, true)) { 6930 e1000e_pm_runtime_resume(dev); 6931 return -EBUSY; 6932 } 6933 6934 return 0; 6935 } 6936 #endif /* CONFIG_PM */ 6937 6938 static void e1000_shutdown(struct pci_dev *pdev) 6939 { 6940 e1000e_flush_lpic(pdev); 6941 6942 e1000e_pm_freeze(&pdev->dev); 6943 6944 __e1000_shutdown(pdev, false); 6945 } 6946 6947 #ifdef CONFIG_NET_POLL_CONTROLLER 6948 6949 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 6950 { 6951 struct net_device *netdev = data; 6952 struct e1000_adapter *adapter = netdev_priv(netdev); 6953 6954 if (adapter->msix_entries) { 6955 int vector, msix_irq; 6956 6957 vector = 0; 6958 msix_irq = adapter->msix_entries[vector].vector; 6959 if (disable_hardirq(msix_irq)) 6960 e1000_intr_msix_rx(msix_irq, netdev); 6961 enable_irq(msix_irq); 6962 6963 vector++; 6964 msix_irq = adapter->msix_entries[vector].vector; 6965 if (disable_hardirq(msix_irq)) 6966 e1000_intr_msix_tx(msix_irq, netdev); 6967 enable_irq(msix_irq); 6968 6969 vector++; 6970 msix_irq = adapter->msix_entries[vector].vector; 6971 if (disable_hardirq(msix_irq)) 6972 e1000_msix_other(msix_irq, netdev); 6973 enable_irq(msix_irq); 6974 } 6975 6976 return IRQ_HANDLED; 6977 } 6978 6979 /** 6980 * e1000_netpoll 6981 * @netdev: network interface device structure 6982 * 6983 * Polling 'interrupt' - used by things like netconsole to send skbs 6984 * without having to re-enable interrupts. It's not called while 6985 * the interrupt routine is executing. 6986 */ 6987 static void e1000_netpoll(struct net_device *netdev) 6988 { 6989 struct e1000_adapter *adapter = netdev_priv(netdev); 6990 6991 switch (adapter->int_mode) { 6992 case E1000E_INT_MODE_MSIX: 6993 e1000_intr_msix(adapter->pdev->irq, netdev); 6994 break; 6995 case E1000E_INT_MODE_MSI: 6996 if (disable_hardirq(adapter->pdev->irq)) 6997 e1000_intr_msi(adapter->pdev->irq, netdev); 6998 enable_irq(adapter->pdev->irq); 6999 break; 7000 default: /* E1000E_INT_MODE_LEGACY */ 7001 if (disable_hardirq(adapter->pdev->irq)) 7002 e1000_intr(adapter->pdev->irq, netdev); 7003 enable_irq(adapter->pdev->irq); 7004 break; 7005 } 7006 } 7007 #endif 7008 7009 /** 7010 * e1000_io_error_detected - called when PCI error is detected 7011 * @pdev: Pointer to PCI device 7012 * @state: The current pci connection state 7013 * 7014 * This function is called after a PCI bus error affecting 7015 * this device has been detected. 7016 */ 7017 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7018 pci_channel_state_t state) 7019 { 7020 e1000e_pm_freeze(&pdev->dev); 7021 7022 if (state == pci_channel_io_perm_failure) 7023 return PCI_ERS_RESULT_DISCONNECT; 7024 7025 pci_disable_device(pdev); 7026 7027 /* Request a slot slot reset. */ 7028 return PCI_ERS_RESULT_NEED_RESET; 7029 } 7030 7031 /** 7032 * e1000_io_slot_reset - called after the pci bus has been reset. 7033 * @pdev: Pointer to PCI device 7034 * 7035 * Restart the card from scratch, as if from a cold-boot. Implementation 7036 * resembles the first-half of the e1000e_pm_resume routine. 7037 */ 7038 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7039 { 7040 struct net_device *netdev = pci_get_drvdata(pdev); 7041 struct e1000_adapter *adapter = netdev_priv(netdev); 7042 struct e1000_hw *hw = &adapter->hw; 7043 u16 aspm_disable_flag = 0; 7044 int err; 7045 pci_ers_result_t result; 7046 7047 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7048 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7049 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7050 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7051 if (aspm_disable_flag) 7052 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7053 7054 err = pci_enable_device_mem(pdev); 7055 if (err) { 7056 dev_err(&pdev->dev, 7057 "Cannot re-enable PCI device after reset.\n"); 7058 result = PCI_ERS_RESULT_DISCONNECT; 7059 } else { 7060 pdev->state_saved = true; 7061 pci_restore_state(pdev); 7062 pci_set_master(pdev); 7063 7064 pci_enable_wake(pdev, PCI_D3hot, 0); 7065 pci_enable_wake(pdev, PCI_D3cold, 0); 7066 7067 e1000e_reset(adapter); 7068 ew32(WUS, ~0); 7069 result = PCI_ERS_RESULT_RECOVERED; 7070 } 7071 7072 return result; 7073 } 7074 7075 /** 7076 * e1000_io_resume - called when traffic can start flowing again. 7077 * @pdev: Pointer to PCI device 7078 * 7079 * This callback is called when the error recovery driver tells us that 7080 * its OK to resume normal operation. Implementation resembles the 7081 * second-half of the e1000e_pm_resume routine. 7082 */ 7083 static void e1000_io_resume(struct pci_dev *pdev) 7084 { 7085 struct net_device *netdev = pci_get_drvdata(pdev); 7086 struct e1000_adapter *adapter = netdev_priv(netdev); 7087 7088 e1000_init_manageability_pt(adapter); 7089 7090 e1000e_pm_thaw(&pdev->dev); 7091 7092 /* If the controller has AMT, do not set DRV_LOAD until the interface 7093 * is up. For all other cases, let the f/w know that the h/w is now 7094 * under the control of the driver. 7095 */ 7096 if (!(adapter->flags & FLAG_HAS_AMT)) 7097 e1000e_get_hw_control(adapter); 7098 } 7099 7100 static void e1000_print_device_info(struct e1000_adapter *adapter) 7101 { 7102 struct e1000_hw *hw = &adapter->hw; 7103 struct net_device *netdev = adapter->netdev; 7104 u32 ret_val; 7105 u8 pba_str[E1000_PBANUM_LENGTH]; 7106 7107 /* print bus type/speed/width info */ 7108 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7109 /* bus width */ 7110 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7111 "Width x1"), 7112 /* MAC address */ 7113 netdev->dev_addr); 7114 e_info("Intel(R) PRO/%s Network Connection\n", 7115 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7116 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7117 E1000_PBANUM_LENGTH); 7118 if (ret_val) 7119 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7120 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7121 hw->mac.type, hw->phy.type, pba_str); 7122 } 7123 7124 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7125 { 7126 struct e1000_hw *hw = &adapter->hw; 7127 int ret_val; 7128 u16 buf = 0; 7129 7130 if (hw->mac.type != e1000_82573) 7131 return; 7132 7133 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7134 le16_to_cpus(&buf); 7135 if (!ret_val && (!(buf & BIT(0)))) { 7136 /* Deep Smart Power Down (DSPD) */ 7137 dev_warn(&adapter->pdev->dev, 7138 "Warning: detected DSPD enabled in EEPROM\n"); 7139 } 7140 } 7141 7142 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7143 netdev_features_t features) 7144 { 7145 struct e1000_adapter *adapter = netdev_priv(netdev); 7146 struct e1000_hw *hw = &adapter->hw; 7147 7148 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7149 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7150 features &= ~NETIF_F_RXFCS; 7151 7152 /* Since there is no support for separate Rx/Tx vlan accel 7153 * enable/disable make sure Tx flag is always in same state as Rx. 7154 */ 7155 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7156 features |= NETIF_F_HW_VLAN_CTAG_TX; 7157 else 7158 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7159 7160 return features; 7161 } 7162 7163 static int e1000_set_features(struct net_device *netdev, 7164 netdev_features_t features) 7165 { 7166 struct e1000_adapter *adapter = netdev_priv(netdev); 7167 netdev_features_t changed = features ^ netdev->features; 7168 7169 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7170 adapter->flags |= FLAG_TSO_FORCE; 7171 7172 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7173 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7174 NETIF_F_RXALL))) 7175 return 0; 7176 7177 if (changed & NETIF_F_RXFCS) { 7178 if (features & NETIF_F_RXFCS) { 7179 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7180 } else { 7181 /* We need to take it back to defaults, which might mean 7182 * stripping is still disabled at the adapter level. 7183 */ 7184 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7185 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7186 else 7187 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7188 } 7189 } 7190 7191 netdev->features = features; 7192 7193 if (netif_running(netdev)) 7194 e1000e_reinit_locked(adapter); 7195 else 7196 e1000e_reset(adapter); 7197 7198 return 1; 7199 } 7200 7201 static const struct net_device_ops e1000e_netdev_ops = { 7202 .ndo_open = e1000e_open, 7203 .ndo_stop = e1000e_close, 7204 .ndo_start_xmit = e1000_xmit_frame, 7205 .ndo_get_stats64 = e1000e_get_stats64, 7206 .ndo_set_rx_mode = e1000e_set_rx_mode, 7207 .ndo_set_mac_address = e1000_set_mac, 7208 .ndo_change_mtu = e1000_change_mtu, 7209 .ndo_do_ioctl = e1000_ioctl, 7210 .ndo_tx_timeout = e1000_tx_timeout, 7211 .ndo_validate_addr = eth_validate_addr, 7212 7213 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7214 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7215 #ifdef CONFIG_NET_POLL_CONTROLLER 7216 .ndo_poll_controller = e1000_netpoll, 7217 #endif 7218 .ndo_set_features = e1000_set_features, 7219 .ndo_fix_features = e1000_fix_features, 7220 .ndo_features_check = passthru_features_check, 7221 }; 7222 7223 /** 7224 * e1000_probe - Device Initialization Routine 7225 * @pdev: PCI device information struct 7226 * @ent: entry in e1000_pci_tbl 7227 * 7228 * Returns 0 on success, negative on failure 7229 * 7230 * e1000_probe initializes an adapter identified by a pci_dev structure. 7231 * The OS initialization, configuring of the adapter private structure, 7232 * and a hardware reset occur. 7233 **/ 7234 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7235 { 7236 struct net_device *netdev; 7237 struct e1000_adapter *adapter; 7238 struct e1000_hw *hw; 7239 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7240 resource_size_t mmio_start, mmio_len; 7241 resource_size_t flash_start, flash_len; 7242 static int cards_found; 7243 u16 aspm_disable_flag = 0; 7244 int bars, i, err, pci_using_dac; 7245 u16 eeprom_data = 0; 7246 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7247 s32 ret_val = 0; 7248 7249 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7250 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7251 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7252 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7253 if (aspm_disable_flag) 7254 e1000e_disable_aspm(pdev, aspm_disable_flag); 7255 7256 err = pci_enable_device_mem(pdev); 7257 if (err) 7258 return err; 7259 7260 pci_using_dac = 0; 7261 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7262 if (!err) { 7263 pci_using_dac = 1; 7264 } else { 7265 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 7266 if (err) { 7267 dev_err(&pdev->dev, 7268 "No usable DMA configuration, aborting\n"); 7269 goto err_dma; 7270 } 7271 } 7272 7273 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7274 err = pci_request_selected_regions_exclusive(pdev, bars, 7275 e1000e_driver_name); 7276 if (err) 7277 goto err_pci_reg; 7278 7279 /* AER (Advanced Error Reporting) hooks */ 7280 pci_enable_pcie_error_reporting(pdev); 7281 7282 pci_set_master(pdev); 7283 /* PCI config space info */ 7284 err = pci_save_state(pdev); 7285 if (err) 7286 goto err_alloc_etherdev; 7287 7288 err = -ENOMEM; 7289 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7290 if (!netdev) 7291 goto err_alloc_etherdev; 7292 7293 SET_NETDEV_DEV(netdev, &pdev->dev); 7294 7295 netdev->irq = pdev->irq; 7296 7297 pci_set_drvdata(pdev, netdev); 7298 adapter = netdev_priv(netdev); 7299 hw = &adapter->hw; 7300 adapter->netdev = netdev; 7301 adapter->pdev = pdev; 7302 adapter->ei = ei; 7303 adapter->pba = ei->pba; 7304 adapter->flags = ei->flags; 7305 adapter->flags2 = ei->flags2; 7306 adapter->hw.adapter = adapter; 7307 adapter->hw.mac.type = ei->mac; 7308 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7309 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7310 7311 mmio_start = pci_resource_start(pdev, 0); 7312 mmio_len = pci_resource_len(pdev, 0); 7313 7314 err = -EIO; 7315 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7316 if (!adapter->hw.hw_addr) 7317 goto err_ioremap; 7318 7319 if ((adapter->flags & FLAG_HAS_FLASH) && 7320 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7321 (hw->mac.type < e1000_pch_spt)) { 7322 flash_start = pci_resource_start(pdev, 1); 7323 flash_len = pci_resource_len(pdev, 1); 7324 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7325 if (!adapter->hw.flash_address) 7326 goto err_flashmap; 7327 } 7328 7329 /* Set default EEE advertisement */ 7330 if (adapter->flags2 & FLAG2_HAS_EEE) 7331 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7332 7333 /* construct the net_device struct */ 7334 netdev->netdev_ops = &e1000e_netdev_ops; 7335 e1000e_set_ethtool_ops(netdev); 7336 netdev->watchdog_timeo = 5 * HZ; 7337 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 7338 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7339 7340 netdev->mem_start = mmio_start; 7341 netdev->mem_end = mmio_start + mmio_len; 7342 7343 adapter->bd_number = cards_found++; 7344 7345 e1000e_check_options(adapter); 7346 7347 /* setup adapter struct */ 7348 err = e1000_sw_init(adapter); 7349 if (err) 7350 goto err_sw_init; 7351 7352 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7353 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7354 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7355 7356 err = ei->get_variants(adapter); 7357 if (err) 7358 goto err_hw_init; 7359 7360 if ((adapter->flags & FLAG_IS_ICH) && 7361 (adapter->flags & FLAG_READ_ONLY_NVM) && 7362 (hw->mac.type < e1000_pch_spt)) 7363 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7364 7365 hw->mac.ops.get_bus_info(&adapter->hw); 7366 7367 adapter->hw.phy.autoneg_wait_to_complete = 0; 7368 7369 /* Copper options */ 7370 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7371 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7372 adapter->hw.phy.disable_polarity_correction = 0; 7373 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7374 } 7375 7376 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7377 dev_info(&pdev->dev, 7378 "PHY reset is blocked due to SOL/IDER session.\n"); 7379 7380 /* Set initial default active device features */ 7381 netdev->features = (NETIF_F_SG | 7382 NETIF_F_HW_VLAN_CTAG_RX | 7383 NETIF_F_HW_VLAN_CTAG_TX | 7384 NETIF_F_TSO | 7385 NETIF_F_TSO6 | 7386 NETIF_F_RXHASH | 7387 NETIF_F_RXCSUM | 7388 NETIF_F_HW_CSUM); 7389 7390 /* Set user-changeable features (subset of all device features) */ 7391 netdev->hw_features = netdev->features; 7392 netdev->hw_features |= NETIF_F_RXFCS; 7393 netdev->priv_flags |= IFF_SUPP_NOFCS; 7394 netdev->hw_features |= NETIF_F_RXALL; 7395 7396 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7397 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7398 7399 netdev->vlan_features |= (NETIF_F_SG | 7400 NETIF_F_TSO | 7401 NETIF_F_TSO6 | 7402 NETIF_F_HW_CSUM); 7403 7404 netdev->priv_flags |= IFF_UNICAST_FLT; 7405 7406 if (pci_using_dac) { 7407 netdev->features |= NETIF_F_HIGHDMA; 7408 netdev->vlan_features |= NETIF_F_HIGHDMA; 7409 } 7410 7411 /* MTU range: 68 - max_hw_frame_size */ 7412 netdev->min_mtu = ETH_MIN_MTU; 7413 netdev->max_mtu = adapter->max_hw_frame_size - 7414 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7415 7416 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7417 adapter->flags |= FLAG_MNG_PT_ENABLED; 7418 7419 /* before reading the NVM, reset the controller to 7420 * put the device in a known good starting state 7421 */ 7422 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7423 7424 /* systems with ASPM and others may see the checksum fail on the first 7425 * attempt. Let's give it a few tries 7426 */ 7427 for (i = 0;; i++) { 7428 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7429 break; 7430 if (i == 2) { 7431 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7432 err = -EIO; 7433 goto err_eeprom; 7434 } 7435 } 7436 7437 e1000_eeprom_checks(adapter); 7438 7439 /* copy the MAC address */ 7440 if (e1000e_read_mac_addr(&adapter->hw)) 7441 dev_err(&pdev->dev, 7442 "NVM Read Error while reading MAC address\n"); 7443 7444 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 7445 7446 if (!is_valid_ether_addr(netdev->dev_addr)) { 7447 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7448 netdev->dev_addr); 7449 err = -EIO; 7450 goto err_eeprom; 7451 } 7452 7453 adapter->e1000_workqueue = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, 7454 e1000e_driver_name); 7455 7456 if (!adapter->e1000_workqueue) { 7457 err = -ENOMEM; 7458 goto err_workqueue; 7459 } 7460 7461 INIT_DELAYED_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7462 queue_delayed_work(adapter->e1000_workqueue, &adapter->watchdog_task, 7463 0); 7464 7465 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7466 7467 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7468 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7469 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7470 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7471 7472 /* Initialize link parameters. User can change them with ethtool */ 7473 adapter->hw.mac.autoneg = 1; 7474 adapter->fc_autoneg = true; 7475 adapter->hw.fc.requested_mode = e1000_fc_default; 7476 adapter->hw.fc.current_mode = e1000_fc_default; 7477 adapter->hw.phy.autoneg_advertised = 0x2f; 7478 7479 /* Initial Wake on LAN setting - If APM wake is enabled in 7480 * the EEPROM, enable the ACPI Magic Packet filter 7481 */ 7482 if (adapter->flags & FLAG_APME_IN_WUC) { 7483 /* APME bit in EEPROM is mapped to WUC.APME */ 7484 eeprom_data = er32(WUC); 7485 eeprom_apme_mask = E1000_WUC_APME; 7486 if ((hw->mac.type > e1000_ich10lan) && 7487 (eeprom_data & E1000_WUC_PHY_WAKE)) 7488 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7489 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7490 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7491 (adapter->hw.bus.func == 1)) 7492 ret_val = e1000_read_nvm(&adapter->hw, 7493 NVM_INIT_CONTROL3_PORT_B, 7494 1, &eeprom_data); 7495 else 7496 ret_val = e1000_read_nvm(&adapter->hw, 7497 NVM_INIT_CONTROL3_PORT_A, 7498 1, &eeprom_data); 7499 } 7500 7501 /* fetch WoL from EEPROM */ 7502 if (ret_val) 7503 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7504 else if (eeprom_data & eeprom_apme_mask) 7505 adapter->eeprom_wol |= E1000_WUFC_MAG; 7506 7507 /* now that we have the eeprom settings, apply the special cases 7508 * where the eeprom may be wrong or the board simply won't support 7509 * wake on lan on a particular port 7510 */ 7511 if (!(adapter->flags & FLAG_HAS_WOL)) 7512 adapter->eeprom_wol = 0; 7513 7514 /* initialize the wol settings based on the eeprom settings */ 7515 adapter->wol = adapter->eeprom_wol; 7516 7517 /* make sure adapter isn't asleep if manageability is enabled */ 7518 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7519 (hw->mac.ops.check_mng_mode(hw))) 7520 device_wakeup_enable(&pdev->dev); 7521 7522 /* save off EEPROM version number */ 7523 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7524 7525 if (ret_val) { 7526 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7527 adapter->eeprom_vers = 0; 7528 } 7529 7530 /* init PTP hardware clock */ 7531 e1000e_ptp_init(adapter); 7532 7533 /* reset the hardware with the new settings */ 7534 e1000e_reset(adapter); 7535 7536 /* If the controller has AMT, do not set DRV_LOAD until the interface 7537 * is up. For all other cases, let the f/w know that the h/w is now 7538 * under the control of the driver. 7539 */ 7540 if (!(adapter->flags & FLAG_HAS_AMT)) 7541 e1000e_get_hw_control(adapter); 7542 7543 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7544 err = register_netdev(netdev); 7545 if (err) 7546 goto err_register; 7547 7548 /* carrier off reporting is important to ethtool even BEFORE open */ 7549 netif_carrier_off(netdev); 7550 7551 e1000_print_device_info(adapter); 7552 7553 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); 7554 7555 if (pci_dev_run_wake(pdev) && hw->mac.type < e1000_pch_cnp) 7556 pm_runtime_put_noidle(&pdev->dev); 7557 7558 return 0; 7559 7560 err_register: 7561 flush_workqueue(adapter->e1000_workqueue); 7562 destroy_workqueue(adapter->e1000_workqueue); 7563 err_workqueue: 7564 if (!(adapter->flags & FLAG_HAS_AMT)) 7565 e1000e_release_hw_control(adapter); 7566 err_eeprom: 7567 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7568 e1000_phy_hw_reset(&adapter->hw); 7569 err_hw_init: 7570 kfree(adapter->tx_ring); 7571 kfree(adapter->rx_ring); 7572 err_sw_init: 7573 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7574 iounmap(adapter->hw.flash_address); 7575 e1000e_reset_interrupt_capability(adapter); 7576 err_flashmap: 7577 iounmap(adapter->hw.hw_addr); 7578 err_ioremap: 7579 free_netdev(netdev); 7580 err_alloc_etherdev: 7581 pci_release_mem_regions(pdev); 7582 err_pci_reg: 7583 err_dma: 7584 pci_disable_device(pdev); 7585 return err; 7586 } 7587 7588 /** 7589 * e1000_remove - Device Removal Routine 7590 * @pdev: PCI device information struct 7591 * 7592 * e1000_remove is called by the PCI subsystem to alert the driver 7593 * that it should release a PCI device. The could be caused by a 7594 * Hot-Plug event, or because the driver is going to be removed from 7595 * memory. 7596 **/ 7597 static void e1000_remove(struct pci_dev *pdev) 7598 { 7599 struct net_device *netdev = pci_get_drvdata(pdev); 7600 struct e1000_adapter *adapter = netdev_priv(netdev); 7601 7602 e1000e_ptp_remove(adapter); 7603 7604 /* The timers may be rescheduled, so explicitly disable them 7605 * from being rescheduled. 7606 */ 7607 set_bit(__E1000_DOWN, &adapter->state); 7608 del_timer_sync(&adapter->phy_info_timer); 7609 7610 cancel_work_sync(&adapter->reset_task); 7611 cancel_work_sync(&adapter->downshift_task); 7612 cancel_work_sync(&adapter->update_phy_task); 7613 cancel_work_sync(&adapter->print_hang_task); 7614 7615 cancel_delayed_work(&adapter->watchdog_task); 7616 flush_workqueue(adapter->e1000_workqueue); 7617 destroy_workqueue(adapter->e1000_workqueue); 7618 7619 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7620 cancel_work_sync(&adapter->tx_hwtstamp_work); 7621 if (adapter->tx_hwtstamp_skb) { 7622 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7623 adapter->tx_hwtstamp_skb = NULL; 7624 } 7625 } 7626 7627 unregister_netdev(netdev); 7628 7629 if (pci_dev_run_wake(pdev)) 7630 pm_runtime_get_noresume(&pdev->dev); 7631 7632 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7633 * would have already happened in close and is redundant. 7634 */ 7635 e1000e_release_hw_control(adapter); 7636 7637 e1000e_reset_interrupt_capability(adapter); 7638 kfree(adapter->tx_ring); 7639 kfree(adapter->rx_ring); 7640 7641 iounmap(adapter->hw.hw_addr); 7642 if ((adapter->hw.flash_address) && 7643 (adapter->hw.mac.type < e1000_pch_spt)) 7644 iounmap(adapter->hw.flash_address); 7645 pci_release_mem_regions(pdev); 7646 7647 free_netdev(netdev); 7648 7649 /* AER disable */ 7650 pci_disable_pcie_error_reporting(pdev); 7651 7652 pci_disable_device(pdev); 7653 } 7654 7655 /* PCI Error Recovery (ERS) */ 7656 static const struct pci_error_handlers e1000_err_handler = { 7657 .error_detected = e1000_io_error_detected, 7658 .slot_reset = e1000_io_slot_reset, 7659 .resume = e1000_io_resume, 7660 }; 7661 7662 static const struct pci_device_id e1000_pci_tbl[] = { 7663 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7664 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7665 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7666 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7667 board_82571 }, 7668 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7669 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7670 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7671 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7672 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7673 7674 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7675 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7676 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7677 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7678 7679 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7680 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7681 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7682 7683 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7684 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7685 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7686 7687 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7688 board_80003es2lan }, 7689 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7690 board_80003es2lan }, 7691 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7692 board_80003es2lan }, 7693 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7694 board_80003es2lan }, 7695 7696 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7697 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7698 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7699 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7700 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7701 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7702 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7703 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7704 7705 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7706 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7707 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7708 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7709 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7710 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7711 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7712 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7713 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7714 7715 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7716 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7717 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7718 7719 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7720 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7721 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7722 7723 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7724 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7725 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7726 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7727 7728 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7729 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7730 7731 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7732 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7733 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7734 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7735 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7736 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7737 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7738 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7739 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7740 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7741 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7742 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7743 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7744 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7745 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7746 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7747 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7748 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7749 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7750 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7751 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7752 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7753 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7754 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7755 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7756 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp }, 7757 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp }, 7758 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp }, 7759 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, 7760 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, 7761 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, 7762 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_cnp }, 7763 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_cnp }, 7764 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_cnp }, 7765 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp }, 7766 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp }, 7767 7768 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7769 }; 7770 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7771 7772 static const struct dev_pm_ops e1000_pm_ops = { 7773 #ifdef CONFIG_PM_SLEEP 7774 .suspend = e1000e_pm_suspend, 7775 .resume = e1000e_pm_resume, 7776 .freeze = e1000e_pm_freeze, 7777 .thaw = e1000e_pm_thaw, 7778 .poweroff = e1000e_pm_suspend, 7779 .restore = e1000e_pm_resume, 7780 #endif 7781 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7782 e1000e_pm_runtime_idle) 7783 }; 7784 7785 /* PCI Device API Driver */ 7786 static struct pci_driver e1000_driver = { 7787 .name = e1000e_driver_name, 7788 .id_table = e1000_pci_tbl, 7789 .probe = e1000_probe, 7790 .remove = e1000_remove, 7791 .driver = { 7792 .pm = &e1000_pm_ops, 7793 }, 7794 .shutdown = e1000_shutdown, 7795 .err_handler = &e1000_err_handler 7796 }; 7797 7798 /** 7799 * e1000_init_module - Driver Registration Routine 7800 * 7801 * e1000_init_module is the first routine called when the driver is 7802 * loaded. All it does is register with the PCI subsystem. 7803 **/ 7804 static int __init e1000_init_module(void) 7805 { 7806 pr_info("Intel(R) PRO/1000 Network Driver - %s\n", 7807 e1000e_driver_version); 7808 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7809 7810 return pci_register_driver(&e1000_driver); 7811 } 7812 module_init(e1000_init_module); 7813 7814 /** 7815 * e1000_exit_module - Driver Exit Cleanup Routine 7816 * 7817 * e1000_exit_module is called just before the driver is removed 7818 * from memory. 7819 **/ 7820 static void __exit e1000_exit_module(void) 7821 { 7822 pci_unregister_driver(&e1000_driver); 7823 } 7824 module_exit(e1000_exit_module); 7825 7826 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7827 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7828 MODULE_LICENSE("GPL v2"); 7829 MODULE_VERSION(DRV_VERSION); 7830 7831 /* netdev.c */ 7832