1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/prefetch.h> 27 #include <linux/suspend.h> 28 #include <linux/dmi.h> 29 30 #include "e1000.h" 31 #define CREATE_TRACE_POINTS 32 #include "e1000e_trace.h" 33 34 char e1000e_driver_name[] = "e1000e"; 35 36 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 37 static int debug = -1; 38 module_param(debug, int, 0); 39 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 40 41 static const struct e1000_info *e1000_info_tbl[] = { 42 [board_82571] = &e1000_82571_info, 43 [board_82572] = &e1000_82572_info, 44 [board_82573] = &e1000_82573_info, 45 [board_82574] = &e1000_82574_info, 46 [board_82583] = &e1000_82583_info, 47 [board_80003es2lan] = &e1000_es2_info, 48 [board_ich8lan] = &e1000_ich8_info, 49 [board_ich9lan] = &e1000_ich9_info, 50 [board_ich10lan] = &e1000_ich10_info, 51 [board_pchlan] = &e1000_pch_info, 52 [board_pch2lan] = &e1000_pch2_info, 53 [board_pch_lpt] = &e1000_pch_lpt_info, 54 [board_pch_spt] = &e1000_pch_spt_info, 55 [board_pch_cnp] = &e1000_pch_cnp_info, 56 [board_pch_tgp] = &e1000_pch_tgp_info, 57 [board_pch_adp] = &e1000_pch_adp_info, 58 [board_pch_mtp] = &e1000_pch_mtp_info, 59 [board_pch_ptp] = &e1000_pch_ptp_info, 60 }; 61 62 static const struct dmi_system_id disable_k1_list[] = { 63 { 64 .ident = "Dell Pro 16 Plus PB16250", 65 .matches = { 66 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 67 DMI_MATCH(DMI_PRODUCT_NAME, "Dell Pro 16 Plus PB16250"), 68 }, 69 }, 70 {} 71 }; 72 73 struct e1000_reg_info { 74 u32 ofs; 75 char *name; 76 }; 77 78 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 79 /* General Registers */ 80 {E1000_CTRL, "CTRL"}, 81 {E1000_STATUS, "STATUS"}, 82 {E1000_CTRL_EXT, "CTRL_EXT"}, 83 84 /* Interrupt Registers */ 85 {E1000_ICR, "ICR"}, 86 87 /* Rx Registers */ 88 {E1000_RCTL, "RCTL"}, 89 {E1000_RDLEN(0), "RDLEN"}, 90 {E1000_RDH(0), "RDH"}, 91 {E1000_RDT(0), "RDT"}, 92 {E1000_RDTR, "RDTR"}, 93 {E1000_RXDCTL(0), "RXDCTL"}, 94 {E1000_ERT, "ERT"}, 95 {E1000_RDBAL(0), "RDBAL"}, 96 {E1000_RDBAH(0), "RDBAH"}, 97 {E1000_RDFH, "RDFH"}, 98 {E1000_RDFT, "RDFT"}, 99 {E1000_RDFHS, "RDFHS"}, 100 {E1000_RDFTS, "RDFTS"}, 101 {E1000_RDFPC, "RDFPC"}, 102 103 /* Tx Registers */ 104 {E1000_TCTL, "TCTL"}, 105 {E1000_TDBAL(0), "TDBAL"}, 106 {E1000_TDBAH(0), "TDBAH"}, 107 {E1000_TDLEN(0), "TDLEN"}, 108 {E1000_TDH(0), "TDH"}, 109 {E1000_TDT(0), "TDT"}, 110 {E1000_TIDV, "TIDV"}, 111 {E1000_TXDCTL(0), "TXDCTL"}, 112 {E1000_TADV, "TADV"}, 113 {E1000_TARC(0), "TARC"}, 114 {E1000_TDFH, "TDFH"}, 115 {E1000_TDFT, "TDFT"}, 116 {E1000_TDFHS, "TDFHS"}, 117 {E1000_TDFTS, "TDFTS"}, 118 {E1000_TDFPC, "TDFPC"}, 119 120 /* List Terminator */ 121 {0, NULL} 122 }; 123 124 /** 125 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 126 * @hw: pointer to the HW structure 127 * 128 * When updating the MAC CSR registers, the Manageability Engine (ME) could 129 * be accessing the registers at the same time. Normally, this is handled in 130 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 131 * accesses later than it should which could result in the register to have 132 * an incorrect value. Workaround this by checking the FWSM register which 133 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 134 * and try again a number of times. 135 **/ 136 static void __ew32_prepare(struct e1000_hw *hw) 137 { 138 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 139 140 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 141 udelay(50); 142 } 143 144 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 145 { 146 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 147 __ew32_prepare(hw); 148 149 writel(val, hw->hw_addr + reg); 150 } 151 152 /** 153 * e1000_regdump - register printout routine 154 * @hw: pointer to the HW structure 155 * @reginfo: pointer to the register info table 156 **/ 157 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 158 { 159 int n = 0; 160 char rname[16]; 161 u32 regs[8]; 162 163 switch (reginfo->ofs) { 164 case E1000_RXDCTL(0): 165 for (n = 0; n < 2; n++) 166 regs[n] = __er32(hw, E1000_RXDCTL(n)); 167 break; 168 case E1000_TXDCTL(0): 169 for (n = 0; n < 2; n++) 170 regs[n] = __er32(hw, E1000_TXDCTL(n)); 171 break; 172 case E1000_TARC(0): 173 for (n = 0; n < 2; n++) 174 regs[n] = __er32(hw, E1000_TARC(n)); 175 break; 176 default: 177 pr_info("%-15s %08x\n", 178 reginfo->name, __er32(hw, reginfo->ofs)); 179 return; 180 } 181 182 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 183 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 184 } 185 186 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 187 struct e1000_buffer *bi) 188 { 189 int i; 190 struct e1000_ps_page *ps_page; 191 192 for (i = 0; i < adapter->rx_ps_pages; i++) { 193 ps_page = &bi->ps_pages[i]; 194 195 if (ps_page->page) { 196 pr_info("packet dump for ps_page %d:\n", i); 197 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 198 16, 1, page_address(ps_page->page), 199 PAGE_SIZE, true); 200 } 201 } 202 } 203 204 /** 205 * e1000e_dump - Print registers, Tx-ring and Rx-ring 206 * @adapter: board private structure 207 **/ 208 static void e1000e_dump(struct e1000_adapter *adapter) 209 { 210 struct net_device *netdev = adapter->netdev; 211 struct e1000_hw *hw = &adapter->hw; 212 struct e1000_reg_info *reginfo; 213 struct e1000_ring *tx_ring = adapter->tx_ring; 214 struct e1000_tx_desc *tx_desc; 215 struct my_u0 { 216 __le64 a; 217 __le64 b; 218 } *u0; 219 struct e1000_buffer *buffer_info; 220 struct e1000_ring *rx_ring = adapter->rx_ring; 221 union e1000_rx_desc_packet_split *rx_desc_ps; 222 union e1000_rx_desc_extended *rx_desc; 223 struct my_u1 { 224 __le64 a; 225 __le64 b; 226 __le64 c; 227 __le64 d; 228 } *u1; 229 u32 staterr; 230 int i = 0; 231 232 if (!netif_msg_hw(adapter)) 233 return; 234 235 /* Print netdevice Info */ 236 if (netdev) { 237 dev_info(&adapter->pdev->dev, "Net device Info\n"); 238 pr_info("Device Name state trans_start\n"); 239 pr_info("%-15s %016lX %016lX\n", netdev->name, 240 netdev->state, dev_trans_start(netdev)); 241 } 242 243 /* Print Registers */ 244 dev_info(&adapter->pdev->dev, "Register Dump\n"); 245 pr_info(" Register Name Value\n"); 246 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 247 reginfo->name; reginfo++) { 248 e1000_regdump(hw, reginfo); 249 } 250 251 /* Print Tx Ring Summary */ 252 if (!netdev || !netif_running(netdev)) 253 return; 254 255 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 256 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 257 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 258 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 259 0, tx_ring->next_to_use, tx_ring->next_to_clean, 260 (unsigned long long)buffer_info->dma, 261 buffer_info->length, 262 buffer_info->next_to_watch, 263 (unsigned long long)buffer_info->time_stamp); 264 265 /* Print Tx Ring */ 266 if (!netif_msg_tx_done(adapter)) 267 goto rx_ring_summary; 268 269 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 270 271 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 272 * 273 * Legacy Transmit Descriptor 274 * +--------------------------------------------------------------+ 275 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 276 * +--------------------------------------------------------------+ 277 * 8 | Special | CSS | Status | CMD | CSO | Length | 278 * +--------------------------------------------------------------+ 279 * 63 48 47 36 35 32 31 24 23 16 15 0 280 * 281 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 282 * 63 48 47 40 39 32 31 16 15 8 7 0 283 * +----------------------------------------------------------------+ 284 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 285 * +----------------------------------------------------------------+ 286 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 287 * +----------------------------------------------------------------+ 288 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 289 * 290 * Extended Data Descriptor (DTYP=0x1) 291 * +----------------------------------------------------------------+ 292 * 0 | Buffer Address [63:0] | 293 * +----------------------------------------------------------------+ 294 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 295 * +----------------------------------------------------------------+ 296 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 297 */ 298 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 299 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 300 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 301 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 302 const char *next_desc; 303 tx_desc = E1000_TX_DESC(*tx_ring, i); 304 buffer_info = &tx_ring->buffer_info[i]; 305 u0 = (struct my_u0 *)tx_desc; 306 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 307 next_desc = " NTC/U"; 308 else if (i == tx_ring->next_to_use) 309 next_desc = " NTU"; 310 else if (i == tx_ring->next_to_clean) 311 next_desc = " NTC"; 312 else 313 next_desc = ""; 314 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 315 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 316 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 317 i, 318 (unsigned long long)le64_to_cpu(u0->a), 319 (unsigned long long)le64_to_cpu(u0->b), 320 (unsigned long long)buffer_info->dma, 321 buffer_info->length, buffer_info->next_to_watch, 322 (unsigned long long)buffer_info->time_stamp, 323 buffer_info->skb, next_desc); 324 325 if (netif_msg_pktdata(adapter) && buffer_info->skb) 326 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 327 16, 1, buffer_info->skb->data, 328 buffer_info->skb->len, true); 329 } 330 331 /* Print Rx Ring Summary */ 332 rx_ring_summary: 333 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 334 pr_info("Queue [NTU] [NTC]\n"); 335 pr_info(" %5d %5X %5X\n", 336 0, rx_ring->next_to_use, rx_ring->next_to_clean); 337 338 /* Print Rx Ring */ 339 if (!netif_msg_rx_status(adapter)) 340 return; 341 342 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 343 switch (adapter->rx_ps_pages) { 344 case 1: 345 case 2: 346 case 3: 347 /* [Extended] Packet Split Receive Descriptor Format 348 * 349 * +-----------------------------------------------------+ 350 * 0 | Buffer Address 0 [63:0] | 351 * +-----------------------------------------------------+ 352 * 8 | Buffer Address 1 [63:0] | 353 * +-----------------------------------------------------+ 354 * 16 | Buffer Address 2 [63:0] | 355 * +-----------------------------------------------------+ 356 * 24 | Buffer Address 3 [63:0] | 357 * +-----------------------------------------------------+ 358 */ 359 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 360 /* [Extended] Receive Descriptor (Write-Back) Format 361 * 362 * 63 48 47 32 31 13 12 8 7 4 3 0 363 * +------------------------------------------------------+ 364 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 365 * | Checksum | Ident | | Queue | | Type | 366 * +------------------------------------------------------+ 367 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 368 * +------------------------------------------------------+ 369 * 63 48 47 32 31 20 19 0 370 */ 371 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 372 for (i = 0; i < rx_ring->count; i++) { 373 const char *next_desc; 374 buffer_info = &rx_ring->buffer_info[i]; 375 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 376 u1 = (struct my_u1 *)rx_desc_ps; 377 staterr = 378 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 379 380 if (i == rx_ring->next_to_use) 381 next_desc = " NTU"; 382 else if (i == rx_ring->next_to_clean) 383 next_desc = " NTC"; 384 else 385 next_desc = ""; 386 387 if (staterr & E1000_RXD_STAT_DD) { 388 /* Descriptor Done */ 389 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 390 "RWB", i, 391 (unsigned long long)le64_to_cpu(u1->a), 392 (unsigned long long)le64_to_cpu(u1->b), 393 (unsigned long long)le64_to_cpu(u1->c), 394 (unsigned long long)le64_to_cpu(u1->d), 395 buffer_info->skb, next_desc); 396 } else { 397 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 398 "R ", i, 399 (unsigned long long)le64_to_cpu(u1->a), 400 (unsigned long long)le64_to_cpu(u1->b), 401 (unsigned long long)le64_to_cpu(u1->c), 402 (unsigned long long)le64_to_cpu(u1->d), 403 (unsigned long long)buffer_info->dma, 404 buffer_info->skb, next_desc); 405 406 if (netif_msg_pktdata(adapter)) 407 e1000e_dump_ps_pages(adapter, 408 buffer_info); 409 } 410 } 411 break; 412 default: 413 case 0: 414 /* Extended Receive Descriptor (Read) Format 415 * 416 * +-----------------------------------------------------+ 417 * 0 | Buffer Address [63:0] | 418 * +-----------------------------------------------------+ 419 * 8 | Reserved | 420 * +-----------------------------------------------------+ 421 */ 422 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 423 /* Extended Receive Descriptor (Write-Back) Format 424 * 425 * 63 48 47 32 31 24 23 4 3 0 426 * +------------------------------------------------------+ 427 * | RSS Hash | | | | 428 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 429 * | Packet | IP | | | Type | 430 * | Checksum | Ident | | | | 431 * +------------------------------------------------------+ 432 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 433 * +------------------------------------------------------+ 434 * 63 48 47 32 31 20 19 0 435 */ 436 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 437 438 for (i = 0; i < rx_ring->count; i++) { 439 const char *next_desc; 440 441 buffer_info = &rx_ring->buffer_info[i]; 442 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 443 u1 = (struct my_u1 *)rx_desc; 444 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 445 446 if (i == rx_ring->next_to_use) 447 next_desc = " NTU"; 448 else if (i == rx_ring->next_to_clean) 449 next_desc = " NTC"; 450 else 451 next_desc = ""; 452 453 if (staterr & E1000_RXD_STAT_DD) { 454 /* Descriptor Done */ 455 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 456 "RWB", i, 457 (unsigned long long)le64_to_cpu(u1->a), 458 (unsigned long long)le64_to_cpu(u1->b), 459 buffer_info->skb, next_desc); 460 } else { 461 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 462 "R ", i, 463 (unsigned long long)le64_to_cpu(u1->a), 464 (unsigned long long)le64_to_cpu(u1->b), 465 (unsigned long long)buffer_info->dma, 466 buffer_info->skb, next_desc); 467 468 if (netif_msg_pktdata(adapter) && 469 buffer_info->skb) 470 print_hex_dump(KERN_INFO, "", 471 DUMP_PREFIX_ADDRESS, 16, 472 1, 473 buffer_info->skb->data, 474 adapter->rx_buffer_len, 475 true); 476 } 477 } 478 } 479 } 480 481 /** 482 * e1000_desc_unused - calculate if we have unused descriptors 483 * @ring: pointer to ring struct to perform calculation on 484 **/ 485 static int e1000_desc_unused(struct e1000_ring *ring) 486 { 487 if (ring->next_to_clean > ring->next_to_use) 488 return ring->next_to_clean - ring->next_to_use - 1; 489 490 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 491 } 492 493 /** 494 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 495 * @adapter: board private structure 496 * @hwtstamps: time stamp structure to update 497 * @systim: unsigned 64bit system time value. 498 * 499 * Convert the system time value stored in the RX/TXSTMP registers into a 500 * hwtstamp which can be used by the upper level time stamping functions. 501 * 502 * The 'systim_lock' spinlock is used to protect the consistency of the 503 * system time value. This is needed because reading the 64 bit time 504 * value involves reading two 32 bit registers. The first read latches the 505 * value. 506 **/ 507 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 508 struct skb_shared_hwtstamps *hwtstamps, 509 u64 systim) 510 { 511 u64 ns; 512 unsigned long flags; 513 514 spin_lock_irqsave(&adapter->systim_lock, flags); 515 ns = timecounter_cyc2time(&adapter->tc, systim); 516 spin_unlock_irqrestore(&adapter->systim_lock, flags); 517 518 memset(hwtstamps, 0, sizeof(*hwtstamps)); 519 hwtstamps->hwtstamp = ns_to_ktime(ns); 520 } 521 522 /** 523 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 524 * @adapter: board private structure 525 * @status: descriptor extended error and status field 526 * @skb: particular skb to include time stamp 527 * 528 * If the time stamp is valid, convert it into the timecounter ns value 529 * and store that result into the shhwtstamps structure which is passed 530 * up the network stack. 531 **/ 532 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 533 struct sk_buff *skb) 534 { 535 struct e1000_hw *hw = &adapter->hw; 536 u64 rxstmp; 537 538 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 539 !(status & E1000_RXDEXT_STATERR_TST) || 540 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 541 return; 542 543 /* The Rx time stamp registers contain the time stamp. No other 544 * received packet will be time stamped until the Rx time stamp 545 * registers are read. Because only one packet can be time stamped 546 * at a time, the register values must belong to this packet and 547 * therefore none of the other additional attributes need to be 548 * compared. 549 */ 550 rxstmp = (u64)er32(RXSTMPL); 551 rxstmp |= (u64)er32(RXSTMPH) << 32; 552 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 553 554 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 555 } 556 557 /** 558 * e1000_receive_skb - helper function to handle Rx indications 559 * @adapter: board private structure 560 * @netdev: pointer to netdev struct 561 * @staterr: descriptor extended error and status field as written by hardware 562 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 563 * @skb: pointer to sk_buff to be indicated to stack 564 **/ 565 static void e1000_receive_skb(struct e1000_adapter *adapter, 566 struct net_device *netdev, struct sk_buff *skb, 567 u32 staterr, __le16 vlan) 568 { 569 u16 tag = le16_to_cpu(vlan); 570 571 e1000e_rx_hwtstamp(adapter, staterr, skb); 572 573 skb->protocol = eth_type_trans(skb, netdev); 574 575 if (staterr & E1000_RXD_STAT_VP) 576 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 577 578 napi_gro_receive(&adapter->napi, skb); 579 } 580 581 /** 582 * e1000_rx_checksum - Receive Checksum Offload 583 * @adapter: board private structure 584 * @status_err: receive descriptor status and error fields 585 * @skb: socket buffer with received data 586 **/ 587 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 588 struct sk_buff *skb) 589 { 590 u16 status = (u16)status_err; 591 u8 errors = (u8)(status_err >> 24); 592 593 skb_checksum_none_assert(skb); 594 595 /* Rx checksum disabled */ 596 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 597 return; 598 599 /* Ignore Checksum bit is set */ 600 if (status & E1000_RXD_STAT_IXSM) 601 return; 602 603 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 604 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 605 /* let the stack verify checksum errors */ 606 adapter->hw_csum_err++; 607 return; 608 } 609 610 /* TCP/UDP Checksum has not been calculated */ 611 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 612 return; 613 614 /* It must be a TCP or UDP packet with a valid checksum */ 615 skb->ip_summed = CHECKSUM_UNNECESSARY; 616 adapter->hw_csum_good++; 617 } 618 619 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 620 { 621 struct e1000_adapter *adapter = rx_ring->adapter; 622 struct e1000_hw *hw = &adapter->hw; 623 624 __ew32_prepare(hw); 625 writel(i, rx_ring->tail); 626 627 if (unlikely(i != readl(rx_ring->tail))) { 628 u32 rctl = er32(RCTL); 629 630 ew32(RCTL, rctl & ~E1000_RCTL_EN); 631 e_err("ME firmware caused invalid RDT - resetting\n"); 632 schedule_work(&adapter->reset_task); 633 } 634 } 635 636 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 637 { 638 struct e1000_adapter *adapter = tx_ring->adapter; 639 struct e1000_hw *hw = &adapter->hw; 640 641 __ew32_prepare(hw); 642 writel(i, tx_ring->tail); 643 644 if (unlikely(i != readl(tx_ring->tail))) { 645 u32 tctl = er32(TCTL); 646 647 ew32(TCTL, tctl & ~E1000_TCTL_EN); 648 e_err("ME firmware caused invalid TDT - resetting\n"); 649 schedule_work(&adapter->reset_task); 650 } 651 } 652 653 /** 654 * e1000_alloc_rx_buffers - Replace used receive buffers 655 * @rx_ring: Rx descriptor ring 656 * @cleaned_count: number to reallocate 657 * @gfp: flags for allocation 658 **/ 659 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 660 int cleaned_count, gfp_t gfp) 661 { 662 struct e1000_adapter *adapter = rx_ring->adapter; 663 struct net_device *netdev = adapter->netdev; 664 struct pci_dev *pdev = adapter->pdev; 665 union e1000_rx_desc_extended *rx_desc; 666 struct e1000_buffer *buffer_info; 667 struct sk_buff *skb; 668 unsigned int i; 669 unsigned int bufsz = adapter->rx_buffer_len; 670 671 i = rx_ring->next_to_use; 672 buffer_info = &rx_ring->buffer_info[i]; 673 674 while (cleaned_count--) { 675 skb = buffer_info->skb; 676 if (skb) { 677 skb_trim(skb, 0); 678 goto map_skb; 679 } 680 681 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 682 if (!skb) { 683 /* Better luck next round */ 684 adapter->alloc_rx_buff_failed++; 685 break; 686 } 687 688 buffer_info->skb = skb; 689 map_skb: 690 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 691 adapter->rx_buffer_len, 692 DMA_FROM_DEVICE); 693 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 694 dev_err(&pdev->dev, "Rx DMA map failed\n"); 695 adapter->rx_dma_failed++; 696 break; 697 } 698 699 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 700 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 701 702 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 703 /* Force memory writes to complete before letting h/w 704 * know there are new descriptors to fetch. (Only 705 * applicable for weak-ordered memory model archs, 706 * such as IA-64). 707 */ 708 wmb(); 709 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 710 e1000e_update_rdt_wa(rx_ring, i); 711 else 712 writel(i, rx_ring->tail); 713 } 714 i++; 715 if (i == rx_ring->count) 716 i = 0; 717 buffer_info = &rx_ring->buffer_info[i]; 718 } 719 720 rx_ring->next_to_use = i; 721 } 722 723 /** 724 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 725 * @rx_ring: Rx descriptor ring 726 * @cleaned_count: number to reallocate 727 * @gfp: flags for allocation 728 **/ 729 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 730 int cleaned_count, gfp_t gfp) 731 { 732 struct e1000_adapter *adapter = rx_ring->adapter; 733 struct net_device *netdev = adapter->netdev; 734 struct pci_dev *pdev = adapter->pdev; 735 union e1000_rx_desc_packet_split *rx_desc; 736 struct e1000_buffer *buffer_info; 737 struct e1000_ps_page *ps_page; 738 struct sk_buff *skb; 739 unsigned int i, j; 740 741 i = rx_ring->next_to_use; 742 buffer_info = &rx_ring->buffer_info[i]; 743 744 while (cleaned_count--) { 745 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 746 747 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 748 ps_page = &buffer_info->ps_pages[j]; 749 if (j >= adapter->rx_ps_pages) { 750 /* all unused desc entries get hw null ptr */ 751 rx_desc->read.buffer_addr[j + 1] = 752 ~cpu_to_le64(0); 753 continue; 754 } 755 if (!ps_page->page) { 756 ps_page->page = alloc_page(gfp); 757 if (!ps_page->page) { 758 adapter->alloc_rx_buff_failed++; 759 goto no_buffers; 760 } 761 ps_page->dma = dma_map_page(&pdev->dev, 762 ps_page->page, 763 0, PAGE_SIZE, 764 DMA_FROM_DEVICE); 765 if (dma_mapping_error(&pdev->dev, 766 ps_page->dma)) { 767 dev_err(&adapter->pdev->dev, 768 "Rx DMA page map failed\n"); 769 adapter->rx_dma_failed++; 770 goto no_buffers; 771 } 772 } 773 /* Refresh the desc even if buffer_addrs 774 * didn't change because each write-back 775 * erases this info. 776 */ 777 rx_desc->read.buffer_addr[j + 1] = 778 cpu_to_le64(ps_page->dma); 779 } 780 781 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 782 gfp); 783 784 if (!skb) { 785 adapter->alloc_rx_buff_failed++; 786 break; 787 } 788 789 buffer_info->skb = skb; 790 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 791 adapter->rx_ps_bsize0, 792 DMA_FROM_DEVICE); 793 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 794 dev_err(&pdev->dev, "Rx DMA map failed\n"); 795 adapter->rx_dma_failed++; 796 /* cleanup skb */ 797 dev_kfree_skb_any(skb); 798 buffer_info->skb = NULL; 799 break; 800 } 801 802 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 803 804 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 805 /* Force memory writes to complete before letting h/w 806 * know there are new descriptors to fetch. (Only 807 * applicable for weak-ordered memory model archs, 808 * such as IA-64). 809 */ 810 wmb(); 811 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 812 e1000e_update_rdt_wa(rx_ring, i << 1); 813 else 814 writel(i << 1, rx_ring->tail); 815 } 816 817 i++; 818 if (i == rx_ring->count) 819 i = 0; 820 buffer_info = &rx_ring->buffer_info[i]; 821 } 822 823 no_buffers: 824 rx_ring->next_to_use = i; 825 } 826 827 /** 828 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 829 * @rx_ring: Rx descriptor ring 830 * @cleaned_count: number of buffers to allocate this pass 831 * @gfp: flags for allocation 832 **/ 833 834 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 835 int cleaned_count, gfp_t gfp) 836 { 837 struct e1000_adapter *adapter = rx_ring->adapter; 838 struct net_device *netdev = adapter->netdev; 839 struct pci_dev *pdev = adapter->pdev; 840 union e1000_rx_desc_extended *rx_desc; 841 struct e1000_buffer *buffer_info; 842 struct sk_buff *skb; 843 unsigned int i; 844 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 845 846 i = rx_ring->next_to_use; 847 buffer_info = &rx_ring->buffer_info[i]; 848 849 while (cleaned_count--) { 850 skb = buffer_info->skb; 851 if (skb) { 852 skb_trim(skb, 0); 853 goto check_page; 854 } 855 856 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 857 if (unlikely(!skb)) { 858 /* Better luck next round */ 859 adapter->alloc_rx_buff_failed++; 860 break; 861 } 862 863 buffer_info->skb = skb; 864 check_page: 865 /* allocate a new page if necessary */ 866 if (!buffer_info->page) { 867 buffer_info->page = alloc_page(gfp); 868 if (unlikely(!buffer_info->page)) { 869 adapter->alloc_rx_buff_failed++; 870 break; 871 } 872 } 873 874 if (!buffer_info->dma) { 875 buffer_info->dma = dma_map_page(&pdev->dev, 876 buffer_info->page, 0, 877 PAGE_SIZE, 878 DMA_FROM_DEVICE); 879 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 880 adapter->alloc_rx_buff_failed++; 881 break; 882 } 883 } 884 885 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 886 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 887 888 if (unlikely(++i == rx_ring->count)) 889 i = 0; 890 buffer_info = &rx_ring->buffer_info[i]; 891 } 892 893 if (likely(rx_ring->next_to_use != i)) { 894 rx_ring->next_to_use = i; 895 if (unlikely(i-- == 0)) 896 i = (rx_ring->count - 1); 897 898 /* Force memory writes to complete before letting h/w 899 * know there are new descriptors to fetch. (Only 900 * applicable for weak-ordered memory model archs, 901 * such as IA-64). 902 */ 903 wmb(); 904 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 905 e1000e_update_rdt_wa(rx_ring, i); 906 else 907 writel(i, rx_ring->tail); 908 } 909 } 910 911 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 912 struct sk_buff *skb) 913 { 914 if (netdev->features & NETIF_F_RXHASH) 915 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 916 } 917 918 /** 919 * e1000_clean_rx_irq - Send received data up the network stack 920 * @rx_ring: Rx descriptor ring 921 * @work_done: output parameter for indicating completed work 922 * @work_to_do: how many packets we can clean 923 * 924 * the return value indicates whether actual cleaning was done, there 925 * is no guarantee that everything was cleaned 926 **/ 927 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 928 int work_to_do) 929 { 930 struct e1000_adapter *adapter = rx_ring->adapter; 931 struct net_device *netdev = adapter->netdev; 932 struct pci_dev *pdev = adapter->pdev; 933 struct e1000_hw *hw = &adapter->hw; 934 union e1000_rx_desc_extended *rx_desc, *next_rxd; 935 struct e1000_buffer *buffer_info, *next_buffer; 936 u32 length, staterr; 937 unsigned int i; 938 int cleaned_count = 0; 939 bool cleaned = false; 940 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 941 942 i = rx_ring->next_to_clean; 943 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 944 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 945 buffer_info = &rx_ring->buffer_info[i]; 946 947 while (staterr & E1000_RXD_STAT_DD) { 948 struct sk_buff *skb; 949 950 if (*work_done >= work_to_do) 951 break; 952 (*work_done)++; 953 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 954 955 skb = buffer_info->skb; 956 buffer_info->skb = NULL; 957 958 prefetch(skb->data - NET_IP_ALIGN); 959 960 i++; 961 if (i == rx_ring->count) 962 i = 0; 963 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 964 prefetch(next_rxd); 965 966 next_buffer = &rx_ring->buffer_info[i]; 967 968 cleaned = true; 969 cleaned_count++; 970 dma_unmap_single(&pdev->dev, buffer_info->dma, 971 adapter->rx_buffer_len, DMA_FROM_DEVICE); 972 buffer_info->dma = 0; 973 974 length = le16_to_cpu(rx_desc->wb.upper.length); 975 976 /* !EOP means multiple descriptors were used to store a single 977 * packet, if that's the case we need to toss it. In fact, we 978 * need to toss every packet with the EOP bit clear and the 979 * next frame that _does_ have the EOP bit set, as it is by 980 * definition only a frame fragment 981 */ 982 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 983 adapter->flags2 |= FLAG2_IS_DISCARDING; 984 985 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 986 /* All receives must fit into a single buffer */ 987 e_dbg("Receive packet consumed multiple buffers\n"); 988 /* recycle */ 989 buffer_info->skb = skb; 990 if (staterr & E1000_RXD_STAT_EOP) 991 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 992 goto next_desc; 993 } 994 995 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 996 !(netdev->features & NETIF_F_RXALL))) { 997 /* recycle */ 998 buffer_info->skb = skb; 999 goto next_desc; 1000 } 1001 1002 /* adjust length to remove Ethernet CRC */ 1003 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1004 /* If configured to store CRC, don't subtract FCS, 1005 * but keep the FCS bytes out of the total_rx_bytes 1006 * counter 1007 */ 1008 if (netdev->features & NETIF_F_RXFCS) 1009 total_rx_bytes -= 4; 1010 else 1011 length -= 4; 1012 } 1013 1014 total_rx_bytes += length; 1015 total_rx_packets++; 1016 1017 /* code added for copybreak, this should improve 1018 * performance for small packets with large amounts 1019 * of reassembly being done in the stack 1020 */ 1021 if (length < copybreak) { 1022 struct sk_buff *new_skb = 1023 napi_alloc_skb(&adapter->napi, length); 1024 if (new_skb) { 1025 skb_copy_to_linear_data_offset(new_skb, 1026 -NET_IP_ALIGN, 1027 (skb->data - 1028 NET_IP_ALIGN), 1029 (length + 1030 NET_IP_ALIGN)); 1031 /* save the skb in buffer_info as good */ 1032 buffer_info->skb = skb; 1033 skb = new_skb; 1034 } 1035 /* else just continue with the old one */ 1036 } 1037 /* end copybreak code */ 1038 skb_put(skb, length); 1039 1040 /* Receive Checksum Offload */ 1041 e1000_rx_checksum(adapter, staterr, skb); 1042 1043 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1044 1045 e1000_receive_skb(adapter, netdev, skb, staterr, 1046 rx_desc->wb.upper.vlan); 1047 1048 next_desc: 1049 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1050 1051 /* return some buffers to hardware, one at a time is too slow */ 1052 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1053 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1054 GFP_ATOMIC); 1055 cleaned_count = 0; 1056 } 1057 1058 /* use prefetched values */ 1059 rx_desc = next_rxd; 1060 buffer_info = next_buffer; 1061 1062 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1063 } 1064 rx_ring->next_to_clean = i; 1065 1066 cleaned_count = e1000_desc_unused(rx_ring); 1067 if (cleaned_count) 1068 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1069 1070 adapter->total_rx_bytes += total_rx_bytes; 1071 adapter->total_rx_packets += total_rx_packets; 1072 return cleaned; 1073 } 1074 1075 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1076 struct e1000_buffer *buffer_info, 1077 bool drop) 1078 { 1079 struct e1000_adapter *adapter = tx_ring->adapter; 1080 1081 if (buffer_info->dma) { 1082 if (buffer_info->mapped_as_page) 1083 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1084 buffer_info->length, DMA_TO_DEVICE); 1085 else 1086 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1087 buffer_info->length, DMA_TO_DEVICE); 1088 buffer_info->dma = 0; 1089 } 1090 if (buffer_info->skb) { 1091 if (drop) 1092 dev_kfree_skb_any(buffer_info->skb); 1093 else 1094 dev_consume_skb_any(buffer_info->skb); 1095 buffer_info->skb = NULL; 1096 } 1097 buffer_info->time_stamp = 0; 1098 } 1099 1100 static void e1000_print_hw_hang(struct work_struct *work) 1101 { 1102 struct e1000_adapter *adapter = container_of(work, 1103 struct e1000_adapter, 1104 print_hang_task); 1105 struct net_device *netdev = adapter->netdev; 1106 struct e1000_ring *tx_ring = adapter->tx_ring; 1107 unsigned int i = tx_ring->next_to_clean; 1108 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1109 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1110 struct e1000_hw *hw = &adapter->hw; 1111 u16 phy_status, phy_1000t_status, phy_ext_status; 1112 u16 pci_status; 1113 1114 if (test_bit(__E1000_DOWN, &adapter->state)) 1115 return; 1116 1117 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1118 /* May be block on write-back, flush and detect again 1119 * flush pending descriptor writebacks to memory 1120 */ 1121 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1122 /* execute the writes immediately */ 1123 e1e_flush(); 1124 /* Due to rare timing issues, write to TIDV again to ensure 1125 * the write is successful 1126 */ 1127 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1128 /* execute the writes immediately */ 1129 e1e_flush(); 1130 adapter->tx_hang_recheck = true; 1131 return; 1132 } 1133 adapter->tx_hang_recheck = false; 1134 1135 if (er32(TDH(0)) == er32(TDT(0))) { 1136 e_dbg("false hang detected, ignoring\n"); 1137 return; 1138 } 1139 1140 /* Real hang detected */ 1141 netif_stop_queue(netdev); 1142 1143 e1e_rphy(hw, MII_BMSR, &phy_status); 1144 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1145 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1146 1147 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1148 1149 /* detected Hardware unit hang */ 1150 e_err("Detected Hardware Unit Hang:\n" 1151 " TDH <%x>\n" 1152 " TDT <%x>\n" 1153 " next_to_use <%x>\n" 1154 " next_to_clean <%x>\n" 1155 "buffer_info[next_to_clean]:\n" 1156 " time_stamp <%lx>\n" 1157 " next_to_watch <%x>\n" 1158 " jiffies <%lx>\n" 1159 " next_to_watch.status <%x>\n" 1160 "MAC Status <%x>\n" 1161 "PHY Status <%x>\n" 1162 "PHY 1000BASE-T Status <%x>\n" 1163 "PHY Extended Status <%x>\n" 1164 "PCI Status <%x>\n", 1165 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1166 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1167 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1168 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1169 1170 e1000e_dump(adapter); 1171 1172 /* Suggest workaround for known h/w issue */ 1173 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1174 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1175 } 1176 1177 /** 1178 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1179 * @work: pointer to work struct 1180 * 1181 * This work function polls the TSYNCTXCTL valid bit to determine when a 1182 * timestamp has been taken for the current stored skb. The timestamp must 1183 * be for this skb because only one such packet is allowed in the queue. 1184 */ 1185 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1186 { 1187 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1188 tx_hwtstamp_work); 1189 struct e1000_hw *hw = &adapter->hw; 1190 1191 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1192 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1193 struct skb_shared_hwtstamps shhwtstamps; 1194 u64 txstmp; 1195 1196 txstmp = er32(TXSTMPL); 1197 txstmp |= (u64)er32(TXSTMPH) << 32; 1198 1199 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1200 1201 /* Clear the global tx_hwtstamp_skb pointer and force writes 1202 * prior to notifying the stack of a Tx timestamp. 1203 */ 1204 adapter->tx_hwtstamp_skb = NULL; 1205 wmb(); /* force write prior to skb_tstamp_tx */ 1206 1207 skb_tstamp_tx(skb, &shhwtstamps); 1208 dev_consume_skb_any(skb); 1209 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1210 + adapter->tx_timeout_factor * HZ)) { 1211 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1212 adapter->tx_hwtstamp_skb = NULL; 1213 adapter->tx_hwtstamp_timeouts++; 1214 e_warn("clearing Tx timestamp hang\n"); 1215 } else { 1216 /* reschedule to check later */ 1217 schedule_work(&adapter->tx_hwtstamp_work); 1218 } 1219 } 1220 1221 /** 1222 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1223 * @tx_ring: Tx descriptor ring 1224 * 1225 * the return value indicates whether actual cleaning was done, there 1226 * is no guarantee that everything was cleaned 1227 **/ 1228 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1229 { 1230 struct e1000_adapter *adapter = tx_ring->adapter; 1231 struct net_device *netdev = adapter->netdev; 1232 struct e1000_hw *hw = &adapter->hw; 1233 struct e1000_tx_desc *tx_desc, *eop_desc; 1234 struct e1000_buffer *buffer_info; 1235 unsigned int i, eop; 1236 unsigned int count = 0; 1237 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1238 unsigned int bytes_compl = 0, pkts_compl = 0; 1239 1240 i = tx_ring->next_to_clean; 1241 eop = tx_ring->buffer_info[i].next_to_watch; 1242 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1243 1244 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1245 (count < tx_ring->count)) { 1246 bool cleaned = false; 1247 1248 dma_rmb(); /* read buffer_info after eop_desc */ 1249 for (; !cleaned; count++) { 1250 tx_desc = E1000_TX_DESC(*tx_ring, i); 1251 buffer_info = &tx_ring->buffer_info[i]; 1252 cleaned = (i == eop); 1253 1254 if (cleaned) { 1255 total_tx_packets += buffer_info->segs; 1256 total_tx_bytes += buffer_info->bytecount; 1257 if (buffer_info->skb) { 1258 bytes_compl += buffer_info->skb->len; 1259 pkts_compl++; 1260 } 1261 } 1262 1263 e1000_put_txbuf(tx_ring, buffer_info, false); 1264 tx_desc->upper.data = 0; 1265 1266 i++; 1267 if (i == tx_ring->count) 1268 i = 0; 1269 } 1270 1271 if (i == tx_ring->next_to_use) 1272 break; 1273 eop = tx_ring->buffer_info[i].next_to_watch; 1274 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1275 } 1276 1277 tx_ring->next_to_clean = i; 1278 1279 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1280 1281 #define TX_WAKE_THRESHOLD 32 1282 if (count && netif_carrier_ok(netdev) && 1283 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1284 /* Make sure that anybody stopping the queue after this 1285 * sees the new next_to_clean. 1286 */ 1287 smp_mb(); 1288 1289 if (netif_queue_stopped(netdev) && 1290 !(test_bit(__E1000_DOWN, &adapter->state))) { 1291 netif_wake_queue(netdev); 1292 ++adapter->restart_queue; 1293 } 1294 } 1295 1296 if (adapter->detect_tx_hung) { 1297 /* Detect a transmit hang in hardware, this serializes the 1298 * check with the clearing of time_stamp and movement of i 1299 */ 1300 adapter->detect_tx_hung = false; 1301 if (tx_ring->buffer_info[i].time_stamp && 1302 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1303 + (adapter->tx_timeout_factor * HZ)) && 1304 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1305 schedule_work(&adapter->print_hang_task); 1306 else 1307 adapter->tx_hang_recheck = false; 1308 } 1309 adapter->total_tx_bytes += total_tx_bytes; 1310 adapter->total_tx_packets += total_tx_packets; 1311 return count < tx_ring->count; 1312 } 1313 1314 /** 1315 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1316 * @rx_ring: Rx descriptor ring 1317 * @work_done: output parameter for indicating completed work 1318 * @work_to_do: how many packets we can clean 1319 * 1320 * the return value indicates whether actual cleaning was done, there 1321 * is no guarantee that everything was cleaned 1322 **/ 1323 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1324 int work_to_do) 1325 { 1326 struct e1000_adapter *adapter = rx_ring->adapter; 1327 struct e1000_hw *hw = &adapter->hw; 1328 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1329 struct net_device *netdev = adapter->netdev; 1330 struct pci_dev *pdev = adapter->pdev; 1331 struct e1000_buffer *buffer_info, *next_buffer; 1332 struct e1000_ps_page *ps_page; 1333 struct sk_buff *skb; 1334 unsigned int i, j; 1335 u32 length, staterr; 1336 int cleaned_count = 0; 1337 bool cleaned = false; 1338 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1339 1340 i = rx_ring->next_to_clean; 1341 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1342 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1343 buffer_info = &rx_ring->buffer_info[i]; 1344 1345 while (staterr & E1000_RXD_STAT_DD) { 1346 if (*work_done >= work_to_do) 1347 break; 1348 (*work_done)++; 1349 skb = buffer_info->skb; 1350 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1351 1352 /* in the packet split case this is header only */ 1353 prefetch(skb->data - NET_IP_ALIGN); 1354 1355 i++; 1356 if (i == rx_ring->count) 1357 i = 0; 1358 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1359 prefetch(next_rxd); 1360 1361 next_buffer = &rx_ring->buffer_info[i]; 1362 1363 cleaned = true; 1364 cleaned_count++; 1365 dma_unmap_single(&pdev->dev, buffer_info->dma, 1366 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1367 buffer_info->dma = 0; 1368 1369 /* see !EOP comment in other Rx routine */ 1370 if (!(staterr & E1000_RXD_STAT_EOP)) 1371 adapter->flags2 |= FLAG2_IS_DISCARDING; 1372 1373 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1374 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1375 dev_kfree_skb_irq(skb); 1376 if (staterr & E1000_RXD_STAT_EOP) 1377 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1378 goto next_desc; 1379 } 1380 1381 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1382 !(netdev->features & NETIF_F_RXALL))) { 1383 dev_kfree_skb_irq(skb); 1384 goto next_desc; 1385 } 1386 1387 length = le16_to_cpu(rx_desc->wb.middle.length0); 1388 1389 if (!length) { 1390 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1391 dev_kfree_skb_irq(skb); 1392 goto next_desc; 1393 } 1394 1395 /* Good Receive */ 1396 skb_put(skb, length); 1397 1398 { 1399 /* this looks ugly, but it seems compiler issues make 1400 * it more efficient than reusing j 1401 */ 1402 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1403 1404 /* page alloc/put takes too long and effects small 1405 * packet throughput, so unsplit small packets and 1406 * save the alloc/put 1407 */ 1408 if (l1 && (l1 <= copybreak) && 1409 ((length + l1) <= adapter->rx_ps_bsize0)) { 1410 ps_page = &buffer_info->ps_pages[0]; 1411 1412 dma_sync_single_for_cpu(&pdev->dev, 1413 ps_page->dma, 1414 PAGE_SIZE, 1415 DMA_FROM_DEVICE); 1416 memcpy(skb_tail_pointer(skb), 1417 page_address(ps_page->page), l1); 1418 dma_sync_single_for_device(&pdev->dev, 1419 ps_page->dma, 1420 PAGE_SIZE, 1421 DMA_FROM_DEVICE); 1422 1423 /* remove the CRC */ 1424 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1425 if (!(netdev->features & NETIF_F_RXFCS)) 1426 l1 -= 4; 1427 } 1428 1429 skb_put(skb, l1); 1430 goto copydone; 1431 } /* if */ 1432 } 1433 1434 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1435 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1436 if (!length) 1437 break; 1438 1439 ps_page = &buffer_info->ps_pages[j]; 1440 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1441 DMA_FROM_DEVICE); 1442 ps_page->dma = 0; 1443 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1444 ps_page->page = NULL; 1445 skb->len += length; 1446 skb->data_len += length; 1447 skb->truesize += PAGE_SIZE; 1448 } 1449 1450 /* strip the ethernet crc, problem is we're using pages now so 1451 * this whole operation can get a little cpu intensive 1452 */ 1453 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1454 if (!(netdev->features & NETIF_F_RXFCS)) 1455 pskb_trim(skb, skb->len - 4); 1456 } 1457 1458 copydone: 1459 total_rx_bytes += skb->len; 1460 total_rx_packets++; 1461 1462 e1000_rx_checksum(adapter, staterr, skb); 1463 1464 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1465 1466 if (rx_desc->wb.upper.header_status & 1467 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1468 adapter->rx_hdr_split++; 1469 1470 e1000_receive_skb(adapter, netdev, skb, staterr, 1471 rx_desc->wb.middle.vlan); 1472 1473 next_desc: 1474 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1475 buffer_info->skb = NULL; 1476 1477 /* return some buffers to hardware, one at a time is too slow */ 1478 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1479 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1480 GFP_ATOMIC); 1481 cleaned_count = 0; 1482 } 1483 1484 /* use prefetched values */ 1485 rx_desc = next_rxd; 1486 buffer_info = next_buffer; 1487 1488 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1489 } 1490 rx_ring->next_to_clean = i; 1491 1492 cleaned_count = e1000_desc_unused(rx_ring); 1493 if (cleaned_count) 1494 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1495 1496 adapter->total_rx_bytes += total_rx_bytes; 1497 adapter->total_rx_packets += total_rx_packets; 1498 return cleaned; 1499 } 1500 1501 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1502 u16 length) 1503 { 1504 bi->page = NULL; 1505 skb->len += length; 1506 skb->data_len += length; 1507 skb->truesize += PAGE_SIZE; 1508 } 1509 1510 /** 1511 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1512 * @rx_ring: Rx descriptor ring 1513 * @work_done: output parameter for indicating completed work 1514 * @work_to_do: how many packets we can clean 1515 * 1516 * the return value indicates whether actual cleaning was done, there 1517 * is no guarantee that everything was cleaned 1518 **/ 1519 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1520 int work_to_do) 1521 { 1522 struct e1000_adapter *adapter = rx_ring->adapter; 1523 struct net_device *netdev = adapter->netdev; 1524 struct pci_dev *pdev = adapter->pdev; 1525 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1526 struct e1000_buffer *buffer_info, *next_buffer; 1527 u32 length, staterr; 1528 unsigned int i; 1529 int cleaned_count = 0; 1530 bool cleaned = false; 1531 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1532 struct skb_shared_info *shinfo; 1533 1534 i = rx_ring->next_to_clean; 1535 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1536 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1537 buffer_info = &rx_ring->buffer_info[i]; 1538 1539 while (staterr & E1000_RXD_STAT_DD) { 1540 struct sk_buff *skb; 1541 1542 if (*work_done >= work_to_do) 1543 break; 1544 (*work_done)++; 1545 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1546 1547 skb = buffer_info->skb; 1548 buffer_info->skb = NULL; 1549 1550 ++i; 1551 if (i == rx_ring->count) 1552 i = 0; 1553 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1554 prefetch(next_rxd); 1555 1556 next_buffer = &rx_ring->buffer_info[i]; 1557 1558 cleaned = true; 1559 cleaned_count++; 1560 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1561 DMA_FROM_DEVICE); 1562 buffer_info->dma = 0; 1563 1564 length = le16_to_cpu(rx_desc->wb.upper.length); 1565 1566 /* errors is only valid for DD + EOP descriptors */ 1567 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1568 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1569 !(netdev->features & NETIF_F_RXALL)))) { 1570 /* recycle both page and skb */ 1571 buffer_info->skb = skb; 1572 /* an error means any chain goes out the window too */ 1573 if (rx_ring->rx_skb_top) 1574 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1575 rx_ring->rx_skb_top = NULL; 1576 goto next_desc; 1577 } 1578 #define rxtop (rx_ring->rx_skb_top) 1579 if (!(staterr & E1000_RXD_STAT_EOP)) { 1580 /* this descriptor is only the beginning (or middle) */ 1581 if (!rxtop) { 1582 /* this is the beginning of a chain */ 1583 rxtop = skb; 1584 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1585 0, length); 1586 } else { 1587 /* this is the middle of a chain */ 1588 shinfo = skb_shinfo(rxtop); 1589 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1590 buffer_info->page, 0, 1591 length); 1592 /* re-use the skb, only consumed the page */ 1593 buffer_info->skb = skb; 1594 } 1595 e1000_consume_page(buffer_info, rxtop, length); 1596 goto next_desc; 1597 } else { 1598 if (rxtop) { 1599 /* end of the chain */ 1600 shinfo = skb_shinfo(rxtop); 1601 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1602 buffer_info->page, 0, 1603 length); 1604 /* re-use the current skb, we only consumed the 1605 * page 1606 */ 1607 buffer_info->skb = skb; 1608 skb = rxtop; 1609 rxtop = NULL; 1610 e1000_consume_page(buffer_info, skb, length); 1611 } else { 1612 /* no chain, got EOP, this buf is the packet 1613 * copybreak to save the put_page/alloc_page 1614 */ 1615 if (length <= copybreak && 1616 skb_tailroom(skb) >= length) { 1617 memcpy(skb_tail_pointer(skb), 1618 page_address(buffer_info->page), 1619 length); 1620 /* re-use the page, so don't erase 1621 * buffer_info->page 1622 */ 1623 skb_put(skb, length); 1624 } else { 1625 skb_fill_page_desc(skb, 0, 1626 buffer_info->page, 0, 1627 length); 1628 e1000_consume_page(buffer_info, skb, 1629 length); 1630 } 1631 } 1632 } 1633 1634 /* Receive Checksum Offload */ 1635 e1000_rx_checksum(adapter, staterr, skb); 1636 1637 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1638 1639 /* probably a little skewed due to removing CRC */ 1640 total_rx_bytes += skb->len; 1641 total_rx_packets++; 1642 1643 /* eth type trans needs skb->data to point to something */ 1644 if (!pskb_may_pull(skb, ETH_HLEN)) { 1645 e_err("pskb_may_pull failed.\n"); 1646 dev_kfree_skb_irq(skb); 1647 goto next_desc; 1648 } 1649 1650 e1000_receive_skb(adapter, netdev, skb, staterr, 1651 rx_desc->wb.upper.vlan); 1652 1653 next_desc: 1654 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1655 1656 /* return some buffers to hardware, one at a time is too slow */ 1657 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1658 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1659 GFP_ATOMIC); 1660 cleaned_count = 0; 1661 } 1662 1663 /* use prefetched values */ 1664 rx_desc = next_rxd; 1665 buffer_info = next_buffer; 1666 1667 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1668 } 1669 rx_ring->next_to_clean = i; 1670 1671 cleaned_count = e1000_desc_unused(rx_ring); 1672 if (cleaned_count) 1673 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1674 1675 adapter->total_rx_bytes += total_rx_bytes; 1676 adapter->total_rx_packets += total_rx_packets; 1677 return cleaned; 1678 } 1679 1680 /** 1681 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1682 * @rx_ring: Rx descriptor ring 1683 **/ 1684 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1685 { 1686 struct e1000_adapter *adapter = rx_ring->adapter; 1687 struct e1000_buffer *buffer_info; 1688 struct e1000_ps_page *ps_page; 1689 struct pci_dev *pdev = adapter->pdev; 1690 unsigned int i, j; 1691 1692 /* Free all the Rx ring sk_buffs */ 1693 for (i = 0; i < rx_ring->count; i++) { 1694 buffer_info = &rx_ring->buffer_info[i]; 1695 if (buffer_info->dma) { 1696 if (adapter->clean_rx == e1000_clean_rx_irq) 1697 dma_unmap_single(&pdev->dev, buffer_info->dma, 1698 adapter->rx_buffer_len, 1699 DMA_FROM_DEVICE); 1700 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1701 dma_unmap_page(&pdev->dev, buffer_info->dma, 1702 PAGE_SIZE, DMA_FROM_DEVICE); 1703 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1704 dma_unmap_single(&pdev->dev, buffer_info->dma, 1705 adapter->rx_ps_bsize0, 1706 DMA_FROM_DEVICE); 1707 buffer_info->dma = 0; 1708 } 1709 1710 if (buffer_info->page) { 1711 put_page(buffer_info->page); 1712 buffer_info->page = NULL; 1713 } 1714 1715 if (buffer_info->skb) { 1716 dev_kfree_skb(buffer_info->skb); 1717 buffer_info->skb = NULL; 1718 } 1719 1720 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1721 ps_page = &buffer_info->ps_pages[j]; 1722 if (!ps_page->page) 1723 break; 1724 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1725 DMA_FROM_DEVICE); 1726 ps_page->dma = 0; 1727 put_page(ps_page->page); 1728 ps_page->page = NULL; 1729 } 1730 } 1731 1732 /* there also may be some cached data from a chained receive */ 1733 if (rx_ring->rx_skb_top) { 1734 dev_kfree_skb(rx_ring->rx_skb_top); 1735 rx_ring->rx_skb_top = NULL; 1736 } 1737 1738 /* Zero out the descriptor ring */ 1739 memset(rx_ring->desc, 0, rx_ring->size); 1740 1741 rx_ring->next_to_clean = 0; 1742 rx_ring->next_to_use = 0; 1743 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1744 } 1745 1746 static void e1000e_downshift_workaround(struct work_struct *work) 1747 { 1748 struct e1000_adapter *adapter = container_of(work, 1749 struct e1000_adapter, 1750 downshift_task); 1751 1752 if (test_bit(__E1000_DOWN, &adapter->state)) 1753 return; 1754 1755 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1756 } 1757 1758 /** 1759 * e1000_intr_msi - Interrupt Handler 1760 * @irq: interrupt number 1761 * @data: pointer to a network interface device structure 1762 **/ 1763 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1764 { 1765 struct net_device *netdev = data; 1766 struct e1000_adapter *adapter = netdev_priv(netdev); 1767 struct e1000_hw *hw = &adapter->hw; 1768 u32 icr = er32(ICR); 1769 1770 /* read ICR disables interrupts using IAM */ 1771 if (icr & E1000_ICR_LSC) { 1772 hw->mac.get_link_status = true; 1773 /* ICH8 workaround-- Call gig speed drop workaround on cable 1774 * disconnect (LSC) before accessing any PHY registers 1775 */ 1776 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1777 (!(er32(STATUS) & E1000_STATUS_LU))) 1778 schedule_work(&adapter->downshift_task); 1779 1780 /* 80003ES2LAN workaround-- For packet buffer work-around on 1781 * link down event; disable receives here in the ISR and reset 1782 * adapter in watchdog 1783 */ 1784 if (netif_carrier_ok(netdev) && 1785 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1786 /* disable receives */ 1787 u32 rctl = er32(RCTL); 1788 1789 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1790 adapter->flags |= FLAG_RESTART_NOW; 1791 } 1792 /* guard against interrupt when we're going down */ 1793 if (!test_bit(__E1000_DOWN, &adapter->state)) 1794 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1795 } 1796 1797 /* Reset on uncorrectable ECC error */ 1798 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1799 u32 pbeccsts = er32(PBECCSTS); 1800 1801 adapter->corr_errors += 1802 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1803 adapter->uncorr_errors += 1804 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 1805 1806 /* Do the reset outside of interrupt context */ 1807 schedule_work(&adapter->reset_task); 1808 1809 /* return immediately since reset is imminent */ 1810 return IRQ_HANDLED; 1811 } 1812 1813 if (napi_schedule_prep(&adapter->napi)) { 1814 adapter->total_tx_bytes = 0; 1815 adapter->total_tx_packets = 0; 1816 adapter->total_rx_bytes = 0; 1817 adapter->total_rx_packets = 0; 1818 __napi_schedule_irqoff(&adapter->napi); 1819 } 1820 1821 return IRQ_HANDLED; 1822 } 1823 1824 /** 1825 * e1000_intr - Interrupt Handler 1826 * @irq: interrupt number 1827 * @data: pointer to a network interface device structure 1828 **/ 1829 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1830 { 1831 struct net_device *netdev = data; 1832 struct e1000_adapter *adapter = netdev_priv(netdev); 1833 struct e1000_hw *hw = &adapter->hw; 1834 u32 rctl, icr = er32(ICR); 1835 1836 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1837 return IRQ_NONE; /* Not our interrupt */ 1838 1839 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1840 * not set, then the adapter didn't send an interrupt 1841 */ 1842 if (!(icr & E1000_ICR_INT_ASSERTED)) 1843 return IRQ_NONE; 1844 1845 /* Interrupt Auto-Mask...upon reading ICR, 1846 * interrupts are masked. No need for the 1847 * IMC write 1848 */ 1849 1850 if (icr & E1000_ICR_LSC) { 1851 hw->mac.get_link_status = true; 1852 /* ICH8 workaround-- Call gig speed drop workaround on cable 1853 * disconnect (LSC) before accessing any PHY registers 1854 */ 1855 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1856 (!(er32(STATUS) & E1000_STATUS_LU))) 1857 schedule_work(&adapter->downshift_task); 1858 1859 /* 80003ES2LAN workaround-- 1860 * For packet buffer work-around on link down event; 1861 * disable receives here in the ISR and 1862 * reset adapter in watchdog 1863 */ 1864 if (netif_carrier_ok(netdev) && 1865 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1866 /* disable receives */ 1867 rctl = er32(RCTL); 1868 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1869 adapter->flags |= FLAG_RESTART_NOW; 1870 } 1871 /* guard against interrupt when we're going down */ 1872 if (!test_bit(__E1000_DOWN, &adapter->state)) 1873 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1874 } 1875 1876 /* Reset on uncorrectable ECC error */ 1877 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1878 u32 pbeccsts = er32(PBECCSTS); 1879 1880 adapter->corr_errors += 1881 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1882 adapter->uncorr_errors += 1883 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 1884 1885 /* Do the reset outside of interrupt context */ 1886 schedule_work(&adapter->reset_task); 1887 1888 /* return immediately since reset is imminent */ 1889 return IRQ_HANDLED; 1890 } 1891 1892 if (napi_schedule_prep(&adapter->napi)) { 1893 adapter->total_tx_bytes = 0; 1894 adapter->total_tx_packets = 0; 1895 adapter->total_rx_bytes = 0; 1896 adapter->total_rx_packets = 0; 1897 __napi_schedule_irqoff(&adapter->napi); 1898 } 1899 1900 return IRQ_HANDLED; 1901 } 1902 1903 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1904 { 1905 struct net_device *netdev = data; 1906 struct e1000_adapter *adapter = netdev_priv(netdev); 1907 struct e1000_hw *hw = &adapter->hw; 1908 u32 icr = er32(ICR); 1909 1910 if (icr & adapter->eiac_mask) 1911 ew32(ICS, (icr & adapter->eiac_mask)); 1912 1913 if (icr & E1000_ICR_LSC) { 1914 hw->mac.get_link_status = true; 1915 /* guard against interrupt when we're going down */ 1916 if (!test_bit(__E1000_DOWN, &adapter->state)) 1917 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1918 } 1919 1920 if (!test_bit(__E1000_DOWN, &adapter->state)) 1921 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1922 1923 return IRQ_HANDLED; 1924 } 1925 1926 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1927 { 1928 struct net_device *netdev = data; 1929 struct e1000_adapter *adapter = netdev_priv(netdev); 1930 struct e1000_hw *hw = &adapter->hw; 1931 struct e1000_ring *tx_ring = adapter->tx_ring; 1932 1933 adapter->total_tx_bytes = 0; 1934 adapter->total_tx_packets = 0; 1935 1936 if (!e1000_clean_tx_irq(tx_ring)) 1937 /* Ring was not completely cleaned, so fire another interrupt */ 1938 ew32(ICS, tx_ring->ims_val); 1939 1940 if (!test_bit(__E1000_DOWN, &adapter->state)) 1941 ew32(IMS, adapter->tx_ring->ims_val); 1942 1943 return IRQ_HANDLED; 1944 } 1945 1946 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1947 { 1948 struct net_device *netdev = data; 1949 struct e1000_adapter *adapter = netdev_priv(netdev); 1950 struct e1000_ring *rx_ring = adapter->rx_ring; 1951 1952 /* Write the ITR value calculated at the end of the 1953 * previous interrupt. 1954 */ 1955 if (rx_ring->set_itr) { 1956 u32 itr = rx_ring->itr_val ? 1957 1000000000 / (rx_ring->itr_val * 256) : 0; 1958 1959 writel(itr, rx_ring->itr_register); 1960 rx_ring->set_itr = 0; 1961 } 1962 1963 if (napi_schedule_prep(&adapter->napi)) { 1964 adapter->total_rx_bytes = 0; 1965 adapter->total_rx_packets = 0; 1966 __napi_schedule_irqoff(&adapter->napi); 1967 } 1968 return IRQ_HANDLED; 1969 } 1970 1971 /** 1972 * e1000_configure_msix - Configure MSI-X hardware 1973 * @adapter: board private structure 1974 * 1975 * e1000_configure_msix sets up the hardware to properly 1976 * generate MSI-X interrupts. 1977 **/ 1978 static void e1000_configure_msix(struct e1000_adapter *adapter) 1979 { 1980 struct e1000_hw *hw = &adapter->hw; 1981 struct e1000_ring *rx_ring = adapter->rx_ring; 1982 struct e1000_ring *tx_ring = adapter->tx_ring; 1983 int vector = 0; 1984 u32 ctrl_ext, ivar = 0; 1985 1986 adapter->eiac_mask = 0; 1987 1988 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1989 if (hw->mac.type == e1000_82574) { 1990 u32 rfctl = er32(RFCTL); 1991 1992 rfctl |= E1000_RFCTL_ACK_DIS; 1993 ew32(RFCTL, rfctl); 1994 } 1995 1996 /* Configure Rx vector */ 1997 rx_ring->ims_val = E1000_IMS_RXQ0; 1998 adapter->eiac_mask |= rx_ring->ims_val; 1999 if (rx_ring->itr_val) 2000 writel(1000000000 / (rx_ring->itr_val * 256), 2001 rx_ring->itr_register); 2002 else 2003 writel(1, rx_ring->itr_register); 2004 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 2005 2006 /* Configure Tx vector */ 2007 tx_ring->ims_val = E1000_IMS_TXQ0; 2008 vector++; 2009 if (tx_ring->itr_val) 2010 writel(1000000000 / (tx_ring->itr_val * 256), 2011 tx_ring->itr_register); 2012 else 2013 writel(1, tx_ring->itr_register); 2014 adapter->eiac_mask |= tx_ring->ims_val; 2015 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2016 2017 /* set vector for Other Causes, e.g. link changes */ 2018 vector++; 2019 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2020 if (rx_ring->itr_val) 2021 writel(1000000000 / (rx_ring->itr_val * 256), 2022 hw->hw_addr + E1000_EITR_82574(vector)); 2023 else 2024 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2025 2026 /* Cause Tx interrupts on every write back */ 2027 ivar |= BIT(31); 2028 2029 ew32(IVAR, ivar); 2030 2031 /* enable MSI-X PBA support */ 2032 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2033 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2034 ew32(CTRL_EXT, ctrl_ext); 2035 e1e_flush(); 2036 } 2037 2038 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2039 { 2040 if (adapter->msix_entries) { 2041 pci_disable_msix(adapter->pdev); 2042 kfree(adapter->msix_entries); 2043 adapter->msix_entries = NULL; 2044 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2045 pci_disable_msi(adapter->pdev); 2046 adapter->flags &= ~FLAG_MSI_ENABLED; 2047 } 2048 } 2049 2050 /** 2051 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2052 * @adapter: board private structure 2053 * 2054 * Attempt to configure interrupts using the best available 2055 * capabilities of the hardware and kernel. 2056 **/ 2057 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2058 { 2059 int err; 2060 int i; 2061 2062 switch (adapter->int_mode) { 2063 case E1000E_INT_MODE_MSIX: 2064 if (adapter->flags & FLAG_HAS_MSIX) { 2065 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2066 adapter->msix_entries = kzalloc_objs(struct msix_entry, 2067 adapter->num_vectors); 2068 if (adapter->msix_entries) { 2069 struct e1000_adapter *a = adapter; 2070 2071 for (i = 0; i < adapter->num_vectors; i++) 2072 adapter->msix_entries[i].entry = i; 2073 2074 err = pci_enable_msix_range(a->pdev, 2075 a->msix_entries, 2076 a->num_vectors, 2077 a->num_vectors); 2078 if (err > 0) 2079 return; 2080 } 2081 /* MSI-X failed, so fall through and try MSI */ 2082 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2083 e1000e_reset_interrupt_capability(adapter); 2084 } 2085 adapter->int_mode = E1000E_INT_MODE_MSI; 2086 fallthrough; 2087 case E1000E_INT_MODE_MSI: 2088 if (!pci_enable_msi(adapter->pdev)) { 2089 adapter->flags |= FLAG_MSI_ENABLED; 2090 } else { 2091 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2092 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2093 } 2094 fallthrough; 2095 case E1000E_INT_MODE_LEGACY: 2096 /* Don't do anything; this is the system default */ 2097 break; 2098 } 2099 2100 /* store the number of vectors being used */ 2101 adapter->num_vectors = 1; 2102 } 2103 2104 /** 2105 * e1000_request_msix - Initialize MSI-X interrupts 2106 * @adapter: board private structure 2107 * 2108 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2109 * kernel. 2110 **/ 2111 static int e1000_request_msix(struct e1000_adapter *adapter) 2112 { 2113 struct net_device *netdev = adapter->netdev; 2114 int err = 0, vector = 0, i; 2115 2116 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2117 snprintf(adapter->rx_ring->name, 2118 sizeof(adapter->rx_ring->name) - 1, 2119 "%.14s-rx-0", netdev->name); 2120 else 2121 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2122 err = request_irq(adapter->msix_entries[vector].vector, 2123 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2124 netdev); 2125 if (err) 2126 goto err_free; 2127 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2128 E1000_EITR_82574(vector); 2129 adapter->rx_ring->itr_val = adapter->itr; 2130 vector++; 2131 2132 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2133 snprintf(adapter->tx_ring->name, 2134 sizeof(adapter->tx_ring->name) - 1, 2135 "%.14s-tx-0", netdev->name); 2136 else 2137 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2138 err = request_irq(adapter->msix_entries[vector].vector, 2139 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2140 netdev); 2141 if (err) 2142 goto err_free; 2143 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2144 E1000_EITR_82574(vector); 2145 adapter->tx_ring->itr_val = adapter->itr; 2146 vector++; 2147 2148 err = request_irq(adapter->msix_entries[vector].vector, 2149 e1000_msix_other, 0, netdev->name, netdev); 2150 if (err) 2151 goto err_free; 2152 2153 e1000_configure_msix(adapter); 2154 2155 return 0; 2156 2157 err_free: 2158 for (i = vector - 1; i >= 0; i--) 2159 free_irq(adapter->msix_entries[i].vector, netdev); 2160 return err; 2161 } 2162 2163 /** 2164 * e1000_request_irq - initialize interrupts 2165 * @adapter: board private structure 2166 * 2167 * Attempts to configure interrupts using the best available 2168 * capabilities of the hardware and kernel. 2169 **/ 2170 static int e1000_request_irq(struct e1000_adapter *adapter) 2171 { 2172 struct net_device *netdev = adapter->netdev; 2173 int err; 2174 2175 if (adapter->msix_entries) { 2176 err = e1000_request_msix(adapter); 2177 if (!err) 2178 return err; 2179 /* fall back to MSI */ 2180 e1000e_reset_interrupt_capability(adapter); 2181 adapter->int_mode = E1000E_INT_MODE_MSI; 2182 e1000e_set_interrupt_capability(adapter); 2183 } 2184 if (adapter->flags & FLAG_MSI_ENABLED) { 2185 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2186 netdev->name, netdev); 2187 if (!err) 2188 return err; 2189 2190 /* fall back to legacy interrupt */ 2191 e1000e_reset_interrupt_capability(adapter); 2192 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2193 } 2194 2195 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2196 netdev->name, netdev); 2197 if (err) 2198 e_err("Unable to allocate interrupt, Error: %d\n", err); 2199 2200 return err; 2201 } 2202 2203 static void e1000_free_irq(struct e1000_adapter *adapter) 2204 { 2205 struct net_device *netdev = adapter->netdev; 2206 2207 if (adapter->msix_entries) { 2208 int vector = 0; 2209 2210 free_irq(adapter->msix_entries[vector].vector, netdev); 2211 vector++; 2212 2213 free_irq(adapter->msix_entries[vector].vector, netdev); 2214 vector++; 2215 2216 /* Other Causes interrupt vector */ 2217 free_irq(adapter->msix_entries[vector].vector, netdev); 2218 return; 2219 } 2220 2221 free_irq(adapter->pdev->irq, netdev); 2222 } 2223 2224 /** 2225 * e1000_irq_disable - Mask off interrupt generation on the NIC 2226 * @adapter: board private structure 2227 **/ 2228 static void e1000_irq_disable(struct e1000_adapter *adapter) 2229 { 2230 struct e1000_hw *hw = &adapter->hw; 2231 2232 ew32(IMC, ~0); 2233 if (adapter->msix_entries) 2234 ew32(EIAC_82574, 0); 2235 e1e_flush(); 2236 2237 if (adapter->msix_entries) { 2238 int i; 2239 2240 for (i = 0; i < adapter->num_vectors; i++) 2241 synchronize_irq(adapter->msix_entries[i].vector); 2242 } else { 2243 synchronize_irq(adapter->pdev->irq); 2244 } 2245 } 2246 2247 /** 2248 * e1000_irq_enable - Enable default interrupt generation settings 2249 * @adapter: board private structure 2250 **/ 2251 static void e1000_irq_enable(struct e1000_adapter *adapter) 2252 { 2253 struct e1000_hw *hw = &adapter->hw; 2254 2255 if (adapter->msix_entries) { 2256 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2257 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2258 IMS_OTHER_MASK); 2259 } else if (hw->mac.type >= e1000_pch_lpt) { 2260 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2261 } else { 2262 ew32(IMS, IMS_ENABLE_MASK); 2263 } 2264 e1e_flush(); 2265 } 2266 2267 /** 2268 * e1000e_get_hw_control - get control of the h/w from f/w 2269 * @adapter: address of board private structure 2270 * 2271 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2272 * For ASF and Pass Through versions of f/w this means that 2273 * the driver is loaded. For AMT version (only with 82573) 2274 * of the f/w this means that the network i/f is open. 2275 **/ 2276 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2277 { 2278 struct e1000_hw *hw = &adapter->hw; 2279 u32 ctrl_ext; 2280 u32 swsm; 2281 2282 /* Let firmware know the driver has taken over */ 2283 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2284 swsm = er32(SWSM); 2285 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2286 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2287 ctrl_ext = er32(CTRL_EXT); 2288 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2289 } 2290 } 2291 2292 /** 2293 * e1000e_release_hw_control - release control of the h/w to f/w 2294 * @adapter: address of board private structure 2295 * 2296 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2297 * For ASF and Pass Through versions of f/w this means that the 2298 * driver is no longer loaded. For AMT version (only with 82573) i 2299 * of the f/w this means that the network i/f is closed. 2300 * 2301 **/ 2302 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2303 { 2304 struct e1000_hw *hw = &adapter->hw; 2305 u32 ctrl_ext; 2306 u32 swsm; 2307 2308 /* Let firmware taken over control of h/w */ 2309 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2310 swsm = er32(SWSM); 2311 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2312 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2313 ctrl_ext = er32(CTRL_EXT); 2314 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2315 } 2316 } 2317 2318 /** 2319 * e1000_alloc_ring_dma - allocate memory for a ring structure 2320 * @adapter: board private structure 2321 * @ring: ring struct for which to allocate dma 2322 **/ 2323 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2324 struct e1000_ring *ring) 2325 { 2326 struct pci_dev *pdev = adapter->pdev; 2327 2328 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2329 GFP_KERNEL); 2330 if (!ring->desc) 2331 return -ENOMEM; 2332 2333 return 0; 2334 } 2335 2336 /** 2337 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2338 * @tx_ring: Tx descriptor ring 2339 * 2340 * Return 0 on success, negative on failure 2341 **/ 2342 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2343 { 2344 struct e1000_adapter *adapter = tx_ring->adapter; 2345 int err = -ENOMEM, size; 2346 2347 size = sizeof(struct e1000_buffer) * tx_ring->count; 2348 tx_ring->buffer_info = vzalloc(size); 2349 if (!tx_ring->buffer_info) 2350 goto err; 2351 2352 /* round up to nearest 4K */ 2353 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2354 tx_ring->size = ALIGN(tx_ring->size, 4096); 2355 2356 err = e1000_alloc_ring_dma(adapter, tx_ring); 2357 if (err) 2358 goto err; 2359 2360 tx_ring->next_to_use = 0; 2361 tx_ring->next_to_clean = 0; 2362 2363 return 0; 2364 err: 2365 vfree(tx_ring->buffer_info); 2366 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2367 return err; 2368 } 2369 2370 /** 2371 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2372 * @rx_ring: Rx descriptor ring 2373 * 2374 * Returns 0 on success, negative on failure 2375 **/ 2376 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2377 { 2378 struct e1000_adapter *adapter = rx_ring->adapter; 2379 struct e1000_buffer *buffer_info; 2380 int i, size, desc_len, err = -ENOMEM; 2381 2382 size = sizeof(struct e1000_buffer) * rx_ring->count; 2383 rx_ring->buffer_info = vzalloc(size); 2384 if (!rx_ring->buffer_info) 2385 goto err; 2386 2387 for (i = 0; i < rx_ring->count; i++) { 2388 buffer_info = &rx_ring->buffer_info[i]; 2389 buffer_info->ps_pages = kzalloc_objs(struct e1000_ps_page, 2390 PS_PAGE_BUFFERS); 2391 if (!buffer_info->ps_pages) 2392 goto err_pages; 2393 } 2394 2395 desc_len = sizeof(union e1000_rx_desc_packet_split); 2396 2397 /* Round up to nearest 4K */ 2398 rx_ring->size = rx_ring->count * desc_len; 2399 rx_ring->size = ALIGN(rx_ring->size, 4096); 2400 2401 err = e1000_alloc_ring_dma(adapter, rx_ring); 2402 if (err) 2403 goto err_pages; 2404 2405 rx_ring->next_to_clean = 0; 2406 rx_ring->next_to_use = 0; 2407 rx_ring->rx_skb_top = NULL; 2408 2409 return 0; 2410 2411 err_pages: 2412 for (i = 0; i < rx_ring->count; i++) { 2413 buffer_info = &rx_ring->buffer_info[i]; 2414 kfree(buffer_info->ps_pages); 2415 } 2416 err: 2417 vfree(rx_ring->buffer_info); 2418 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2419 return err; 2420 } 2421 2422 /** 2423 * e1000_clean_tx_ring - Free Tx Buffers 2424 * @tx_ring: Tx descriptor ring 2425 **/ 2426 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2427 { 2428 struct e1000_adapter *adapter = tx_ring->adapter; 2429 struct e1000_buffer *buffer_info; 2430 unsigned long size; 2431 unsigned int i; 2432 2433 for (i = 0; i < tx_ring->count; i++) { 2434 buffer_info = &tx_ring->buffer_info[i]; 2435 e1000_put_txbuf(tx_ring, buffer_info, false); 2436 } 2437 2438 netdev_reset_queue(adapter->netdev); 2439 size = sizeof(struct e1000_buffer) * tx_ring->count; 2440 memset(tx_ring->buffer_info, 0, size); 2441 2442 memset(tx_ring->desc, 0, tx_ring->size); 2443 2444 tx_ring->next_to_use = 0; 2445 tx_ring->next_to_clean = 0; 2446 } 2447 2448 /** 2449 * e1000e_free_tx_resources - Free Tx Resources per Queue 2450 * @tx_ring: Tx descriptor ring 2451 * 2452 * Free all transmit software resources 2453 **/ 2454 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2455 { 2456 struct e1000_adapter *adapter = tx_ring->adapter; 2457 struct pci_dev *pdev = adapter->pdev; 2458 2459 e1000_clean_tx_ring(tx_ring); 2460 2461 vfree(tx_ring->buffer_info); 2462 tx_ring->buffer_info = NULL; 2463 2464 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2465 tx_ring->dma); 2466 tx_ring->desc = NULL; 2467 } 2468 2469 /** 2470 * e1000e_free_rx_resources - Free Rx Resources 2471 * @rx_ring: Rx descriptor ring 2472 * 2473 * Free all receive software resources 2474 **/ 2475 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2476 { 2477 struct e1000_adapter *adapter = rx_ring->adapter; 2478 struct pci_dev *pdev = adapter->pdev; 2479 int i; 2480 2481 e1000_clean_rx_ring(rx_ring); 2482 2483 for (i = 0; i < rx_ring->count; i++) 2484 kfree(rx_ring->buffer_info[i].ps_pages); 2485 2486 vfree(rx_ring->buffer_info); 2487 rx_ring->buffer_info = NULL; 2488 2489 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2490 rx_ring->dma); 2491 rx_ring->desc = NULL; 2492 } 2493 2494 /** 2495 * e1000_update_itr - update the dynamic ITR value based on statistics 2496 * @itr_setting: current adapter->itr 2497 * @packets: the number of packets during this measurement interval 2498 * @bytes: the number of bytes during this measurement interval 2499 * 2500 * Stores a new ITR value based on packets and byte 2501 * counts during the last interrupt. The advantage of per interrupt 2502 * computation is faster updates and more accurate ITR for the current 2503 * traffic pattern. Constants in this function were computed 2504 * based on theoretical maximum wire speed and thresholds were set based 2505 * on testing data as well as attempting to minimize response time 2506 * while increasing bulk throughput. This functionality is controlled 2507 * by the InterruptThrottleRate module parameter. 2508 **/ 2509 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2510 { 2511 unsigned int retval = itr_setting; 2512 2513 if (packets == 0) 2514 return itr_setting; 2515 2516 switch (itr_setting) { 2517 case lowest_latency: 2518 /* handle TSO and jumbo frames */ 2519 if (bytes / packets > 8000) 2520 retval = bulk_latency; 2521 else if ((packets < 5) && (bytes > 512)) 2522 retval = low_latency; 2523 break; 2524 case low_latency: /* 50 usec aka 20000 ints/s */ 2525 if (bytes > 10000) { 2526 /* this if handles the TSO accounting */ 2527 if (bytes / packets > 8000) 2528 retval = bulk_latency; 2529 else if ((packets < 10) || ((bytes / packets) > 1200)) 2530 retval = bulk_latency; 2531 else if ((packets > 35)) 2532 retval = lowest_latency; 2533 } else if (bytes / packets > 2000) { 2534 retval = bulk_latency; 2535 } else if (packets <= 2 && bytes < 512) { 2536 retval = lowest_latency; 2537 } 2538 break; 2539 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2540 if (bytes > 25000) { 2541 if (packets > 35) 2542 retval = low_latency; 2543 } else if (bytes < 6000) { 2544 retval = low_latency; 2545 } 2546 break; 2547 } 2548 2549 return retval; 2550 } 2551 2552 static void e1000_set_itr(struct e1000_adapter *adapter) 2553 { 2554 u16 current_itr; 2555 u32 new_itr = adapter->itr; 2556 2557 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2558 if (adapter->link_speed != SPEED_1000) { 2559 new_itr = 4000; 2560 goto set_itr_now; 2561 } 2562 2563 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2564 new_itr = 0; 2565 goto set_itr_now; 2566 } 2567 2568 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2569 adapter->total_tx_packets, 2570 adapter->total_tx_bytes); 2571 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2572 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2573 adapter->tx_itr = low_latency; 2574 2575 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2576 adapter->total_rx_packets, 2577 adapter->total_rx_bytes); 2578 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2579 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2580 adapter->rx_itr = low_latency; 2581 2582 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2583 2584 /* counts and packets in update_itr are dependent on these numbers */ 2585 switch (current_itr) { 2586 case lowest_latency: 2587 new_itr = 70000; 2588 break; 2589 case low_latency: 2590 new_itr = 20000; /* aka hwitr = ~200 */ 2591 break; 2592 case bulk_latency: 2593 new_itr = 4000; 2594 break; 2595 default: 2596 break; 2597 } 2598 2599 set_itr_now: 2600 if (new_itr != adapter->itr) { 2601 /* this attempts to bias the interrupt rate towards Bulk 2602 * by adding intermediate steps when interrupt rate is 2603 * increasing 2604 */ 2605 new_itr = new_itr > adapter->itr ? 2606 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2607 adapter->itr = new_itr; 2608 adapter->rx_ring->itr_val = new_itr; 2609 if (adapter->msix_entries) 2610 adapter->rx_ring->set_itr = 1; 2611 else 2612 e1000e_write_itr(adapter, new_itr); 2613 } 2614 } 2615 2616 /** 2617 * e1000e_write_itr - write the ITR value to the appropriate registers 2618 * @adapter: address of board private structure 2619 * @itr: new ITR value to program 2620 * 2621 * e1000e_write_itr determines if the adapter is in MSI-X mode 2622 * and, if so, writes the EITR registers with the ITR value. 2623 * Otherwise, it writes the ITR value into the ITR register. 2624 **/ 2625 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2626 { 2627 struct e1000_hw *hw = &adapter->hw; 2628 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2629 2630 if (adapter->msix_entries) { 2631 int vector; 2632 2633 for (vector = 0; vector < adapter->num_vectors; vector++) 2634 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2635 } else { 2636 ew32(ITR, new_itr); 2637 } 2638 } 2639 2640 /** 2641 * e1000_alloc_queues - Allocate memory for all rings 2642 * @adapter: board private structure to initialize 2643 **/ 2644 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2645 { 2646 int size = sizeof(struct e1000_ring); 2647 2648 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2649 if (!adapter->tx_ring) 2650 goto err; 2651 adapter->tx_ring->count = adapter->tx_ring_count; 2652 adapter->tx_ring->adapter = adapter; 2653 2654 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2655 if (!adapter->rx_ring) 2656 goto err; 2657 adapter->rx_ring->count = adapter->rx_ring_count; 2658 adapter->rx_ring->adapter = adapter; 2659 2660 return 0; 2661 err: 2662 e_err("Unable to allocate memory for queues\n"); 2663 kfree(adapter->rx_ring); 2664 kfree(adapter->tx_ring); 2665 return -ENOMEM; 2666 } 2667 2668 /** 2669 * e1000e_poll - NAPI Rx polling callback 2670 * @napi: struct associated with this polling callback 2671 * @budget: number of packets driver is allowed to process this poll 2672 **/ 2673 static int e1000e_poll(struct napi_struct *napi, int budget) 2674 { 2675 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2676 napi); 2677 struct e1000_hw *hw = &adapter->hw; 2678 struct net_device *poll_dev = adapter->netdev; 2679 int tx_cleaned = 1, work_done = 0; 2680 2681 adapter = netdev_priv(poll_dev); 2682 2683 if (!adapter->msix_entries || 2684 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2685 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2686 2687 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2688 2689 if (!tx_cleaned || work_done == budget) 2690 return budget; 2691 2692 /* Exit the polling mode, but don't re-enable interrupts if stack might 2693 * poll us due to busy-polling 2694 */ 2695 if (likely(napi_complete_done(napi, work_done))) { 2696 if (adapter->itr_setting & 3) 2697 e1000_set_itr(adapter); 2698 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2699 if (adapter->msix_entries) 2700 ew32(IMS, adapter->rx_ring->ims_val); 2701 else 2702 e1000_irq_enable(adapter); 2703 } 2704 } 2705 2706 return work_done; 2707 } 2708 2709 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2710 __always_unused __be16 proto, u16 vid) 2711 { 2712 struct e1000_adapter *adapter = netdev_priv(netdev); 2713 struct e1000_hw *hw = &adapter->hw; 2714 u32 vfta, index; 2715 2716 /* don't update vlan cookie if already programmed */ 2717 if ((adapter->hw.mng_cookie.status & 2718 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2719 (vid == adapter->mng_vlan_id)) 2720 return 0; 2721 2722 /* add VID to filter table */ 2723 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2724 index = (vid >> 5) & 0x7F; 2725 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2726 vfta |= BIT((vid & 0x1F)); 2727 hw->mac.ops.write_vfta(hw, index, vfta); 2728 } 2729 2730 set_bit(vid, adapter->active_vlans); 2731 2732 return 0; 2733 } 2734 2735 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2736 __always_unused __be16 proto, u16 vid) 2737 { 2738 struct e1000_adapter *adapter = netdev_priv(netdev); 2739 struct e1000_hw *hw = &adapter->hw; 2740 u32 vfta, index; 2741 2742 if ((adapter->hw.mng_cookie.status & 2743 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2744 (vid == adapter->mng_vlan_id)) { 2745 /* release control to f/w */ 2746 e1000e_release_hw_control(adapter); 2747 return 0; 2748 } 2749 2750 /* remove VID from filter table */ 2751 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2752 index = (vid >> 5) & 0x7F; 2753 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2754 vfta &= ~BIT((vid & 0x1F)); 2755 hw->mac.ops.write_vfta(hw, index, vfta); 2756 } 2757 2758 clear_bit(vid, adapter->active_vlans); 2759 2760 return 0; 2761 } 2762 2763 /** 2764 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2765 * @adapter: board private structure to initialize 2766 **/ 2767 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2768 { 2769 struct net_device *netdev = adapter->netdev; 2770 struct e1000_hw *hw = &adapter->hw; 2771 u32 rctl; 2772 2773 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2774 /* disable VLAN receive filtering */ 2775 rctl = er32(RCTL); 2776 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2777 ew32(RCTL, rctl); 2778 2779 if (adapter->mng_vlan_id != E1000_MNG_VLAN_NONE) { 2780 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2781 adapter->mng_vlan_id); 2782 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2783 } 2784 } 2785 } 2786 2787 /** 2788 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2789 * @adapter: board private structure to initialize 2790 **/ 2791 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2792 { 2793 struct e1000_hw *hw = &adapter->hw; 2794 u32 rctl; 2795 2796 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2797 /* enable VLAN receive filtering */ 2798 rctl = er32(RCTL); 2799 rctl |= E1000_RCTL_VFE; 2800 rctl &= ~E1000_RCTL_CFIEN; 2801 ew32(RCTL, rctl); 2802 } 2803 } 2804 2805 /** 2806 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2807 * @adapter: board private structure to initialize 2808 **/ 2809 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2810 { 2811 struct e1000_hw *hw = &adapter->hw; 2812 u32 ctrl; 2813 2814 /* disable VLAN tag insert/strip */ 2815 ctrl = er32(CTRL); 2816 ctrl &= ~E1000_CTRL_VME; 2817 ew32(CTRL, ctrl); 2818 } 2819 2820 /** 2821 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2822 * @adapter: board private structure to initialize 2823 **/ 2824 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2825 { 2826 struct e1000_hw *hw = &adapter->hw; 2827 u32 ctrl; 2828 2829 /* enable VLAN tag insert/strip */ 2830 ctrl = er32(CTRL); 2831 ctrl |= E1000_CTRL_VME; 2832 ew32(CTRL, ctrl); 2833 } 2834 2835 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2836 { 2837 struct net_device *netdev = adapter->netdev; 2838 u16 vid = adapter->hw.mng_cookie.vlan_id; 2839 u16 old_vid = adapter->mng_vlan_id; 2840 2841 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2842 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2843 adapter->mng_vlan_id = vid; 2844 } 2845 2846 if (old_vid != E1000_MNG_VLAN_NONE && vid != old_vid) 2847 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2848 } 2849 2850 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2851 { 2852 u16 vid; 2853 2854 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2855 2856 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2857 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2858 } 2859 2860 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2861 { 2862 struct e1000_hw *hw = &adapter->hw; 2863 u32 manc, manc2h, mdef, i, j; 2864 2865 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2866 return; 2867 2868 manc = er32(MANC); 2869 2870 /* enable receiving management packets to the host. this will probably 2871 * generate destination unreachable messages from the host OS, but 2872 * the packets will be handled on SMBUS 2873 */ 2874 manc |= E1000_MANC_EN_MNG2HOST; 2875 manc2h = er32(MANC2H); 2876 2877 switch (hw->mac.type) { 2878 default: 2879 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2880 break; 2881 case e1000_82574: 2882 case e1000_82583: 2883 /* Check if IPMI pass-through decision filter already exists; 2884 * if so, enable it. 2885 */ 2886 for (i = 0, j = 0; i < 8; i++) { 2887 mdef = er32(MDEF(i)); 2888 2889 /* Ignore filters with anything other than IPMI ports */ 2890 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2891 continue; 2892 2893 /* Enable this decision filter in MANC2H */ 2894 if (mdef) 2895 manc2h |= BIT(i); 2896 2897 j |= mdef; 2898 } 2899 2900 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2901 break; 2902 2903 /* Create new decision filter in an empty filter */ 2904 for (i = 0, j = 0; i < 8; i++) 2905 if (er32(MDEF(i)) == 0) { 2906 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2907 E1000_MDEF_PORT_664)); 2908 manc2h |= BIT(1); 2909 j++; 2910 break; 2911 } 2912 2913 if (!j) 2914 e_warn("Unable to create IPMI pass-through filter\n"); 2915 break; 2916 } 2917 2918 ew32(MANC2H, manc2h); 2919 ew32(MANC, manc); 2920 } 2921 2922 /** 2923 * e1000_configure_tx - Configure Transmit Unit after Reset 2924 * @adapter: board private structure 2925 * 2926 * Configure the Tx unit of the MAC after a reset. 2927 **/ 2928 static void e1000_configure_tx(struct e1000_adapter *adapter) 2929 { 2930 struct e1000_hw *hw = &adapter->hw; 2931 struct e1000_ring *tx_ring = adapter->tx_ring; 2932 u64 tdba; 2933 u32 tdlen, tctl, tarc; 2934 2935 /* Setup the HW Tx Head and Tail descriptor pointers */ 2936 tdba = tx_ring->dma; 2937 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2938 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2939 ew32(TDBAH(0), (tdba >> 32)); 2940 ew32(TDLEN(0), tdlen); 2941 ew32(TDH(0), 0); 2942 ew32(TDT(0), 0); 2943 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2944 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2945 2946 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2947 e1000e_update_tdt_wa(tx_ring, 0); 2948 2949 /* Set the Tx Interrupt Delay register */ 2950 ew32(TIDV, adapter->tx_int_delay); 2951 /* Tx irq moderation */ 2952 ew32(TADV, adapter->tx_abs_int_delay); 2953 2954 if (adapter->flags2 & FLAG2_DMA_BURST) { 2955 u32 txdctl = er32(TXDCTL(0)); 2956 2957 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2958 E1000_TXDCTL_WTHRESH); 2959 /* set up some performance related parameters to encourage the 2960 * hardware to use the bus more efficiently in bursts, depends 2961 * on the tx_int_delay to be enabled, 2962 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2963 * hthresh = 1 ==> prefetch when one or more available 2964 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2965 * BEWARE: this seems to work but should be considered first if 2966 * there are Tx hangs or other Tx related bugs 2967 */ 2968 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2969 ew32(TXDCTL(0), txdctl); 2970 } 2971 /* erratum work around: set txdctl the same for both queues */ 2972 ew32(TXDCTL(1), er32(TXDCTL(0))); 2973 2974 /* Program the Transmit Control Register */ 2975 tctl = er32(TCTL); 2976 tctl &= ~E1000_TCTL_CT; 2977 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2978 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2979 2980 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2981 tarc = er32(TARC(0)); 2982 /* set the speed mode bit, we'll clear it if we're not at 2983 * gigabit link later 2984 */ 2985 #define SPEED_MODE_BIT BIT(21) 2986 tarc |= SPEED_MODE_BIT; 2987 ew32(TARC(0), tarc); 2988 } 2989 2990 /* errata: program both queues to unweighted RR */ 2991 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2992 tarc = er32(TARC(0)); 2993 tarc |= 1; 2994 ew32(TARC(0), tarc); 2995 tarc = er32(TARC(1)); 2996 tarc |= 1; 2997 ew32(TARC(1), tarc); 2998 } 2999 3000 /* Setup Transmit Descriptor Settings for eop descriptor */ 3001 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 3002 3003 /* only set IDE if we are delaying interrupts using the timers */ 3004 if (adapter->tx_int_delay) 3005 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3006 3007 /* enable Report Status bit */ 3008 adapter->txd_cmd |= E1000_TXD_CMD_RS; 3009 3010 ew32(TCTL, tctl); 3011 3012 hw->mac.ops.config_collision_dist(hw); 3013 3014 /* SPT and KBL Si errata workaround to avoid data corruption */ 3015 if (hw->mac.type == e1000_pch_spt) { 3016 u32 reg_val; 3017 3018 reg_val = er32(IOSFPC); 3019 reg_val |= E1000_RCTL_RDMTS_HEX; 3020 ew32(IOSFPC, reg_val); 3021 3022 reg_val = er32(TARC(0)); 3023 /* SPT and KBL Si errata workaround to avoid Tx hang. 3024 * Dropping the number of outstanding requests from 3025 * 3 to 2 in order to avoid a buffer overrun. 3026 */ 3027 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3028 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3029 ew32(TARC(0), reg_val); 3030 } 3031 } 3032 3033 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3034 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3035 3036 /** 3037 * e1000_setup_rctl - configure the receive control registers 3038 * @adapter: Board private structure 3039 **/ 3040 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3041 { 3042 struct e1000_hw *hw = &adapter->hw; 3043 u32 rctl, rfctl; 3044 u32 pages = 0; 3045 3046 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3047 * If jumbo frames not set, program related MAC/PHY registers 3048 * to h/w defaults 3049 */ 3050 if (hw->mac.type >= e1000_pch2lan) { 3051 s32 ret_val; 3052 3053 if (adapter->netdev->mtu > ETH_DATA_LEN) 3054 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3055 else 3056 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3057 3058 if (ret_val) 3059 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3060 } 3061 3062 /* Program MC offset vector base */ 3063 rctl = er32(RCTL); 3064 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3065 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3066 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3067 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3068 3069 /* Do not Store bad packets */ 3070 rctl &= ~E1000_RCTL_SBP; 3071 3072 /* Enable Long Packet receive */ 3073 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3074 rctl &= ~E1000_RCTL_LPE; 3075 else 3076 rctl |= E1000_RCTL_LPE; 3077 3078 /* Some systems expect that the CRC is included in SMBUS traffic. The 3079 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3080 * host memory when this is enabled 3081 */ 3082 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3083 rctl |= E1000_RCTL_SECRC; 3084 3085 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3086 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3087 u16 phy_data; 3088 3089 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3090 phy_data &= 0xfff8; 3091 phy_data |= BIT(2); 3092 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3093 3094 e1e_rphy(hw, 22, &phy_data); 3095 phy_data &= 0x0fff; 3096 phy_data |= BIT(14); 3097 e1e_wphy(hw, 0x10, 0x2823); 3098 e1e_wphy(hw, 0x11, 0x0003); 3099 e1e_wphy(hw, 22, phy_data); 3100 } 3101 3102 /* Setup buffer sizes */ 3103 rctl &= ~E1000_RCTL_SZ_4096; 3104 rctl |= E1000_RCTL_BSEX; 3105 switch (adapter->rx_buffer_len) { 3106 case 2048: 3107 default: 3108 rctl |= E1000_RCTL_SZ_2048; 3109 rctl &= ~E1000_RCTL_BSEX; 3110 break; 3111 case 4096: 3112 rctl |= E1000_RCTL_SZ_4096; 3113 break; 3114 case 8192: 3115 rctl |= E1000_RCTL_SZ_8192; 3116 break; 3117 case 16384: 3118 rctl |= E1000_RCTL_SZ_16384; 3119 break; 3120 } 3121 3122 /* Enable Extended Status in all Receive Descriptors */ 3123 rfctl = er32(RFCTL); 3124 rfctl |= E1000_RFCTL_EXTEN; 3125 ew32(RFCTL, rfctl); 3126 3127 /* 82571 and greater support packet-split where the protocol 3128 * header is placed in skb->data and the packet data is 3129 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3130 * In the case of a non-split, skb->data is linearly filled, 3131 * followed by the page buffers. Therefore, skb->data is 3132 * sized to hold the largest protocol header. 3133 * 3134 * allocations using alloc_page take too long for regular MTU 3135 * so only enable packet split for jumbo frames 3136 * 3137 * Using pages when the page size is greater than 16k wastes 3138 * a lot of memory, since we allocate 3 pages at all times 3139 * per packet. 3140 */ 3141 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3142 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3143 adapter->rx_ps_pages = pages; 3144 else 3145 adapter->rx_ps_pages = 0; 3146 3147 if (adapter->rx_ps_pages) { 3148 u32 psrctl = 0; 3149 3150 /* Enable Packet split descriptors */ 3151 rctl |= E1000_RCTL_DTYP_PS; 3152 3153 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3154 3155 switch (adapter->rx_ps_pages) { 3156 case 3: 3157 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3158 fallthrough; 3159 case 2: 3160 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3161 fallthrough; 3162 case 1: 3163 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3164 break; 3165 } 3166 3167 ew32(PSRCTL, psrctl); 3168 } 3169 3170 /* This is useful for sniffing bad packets. */ 3171 if (adapter->netdev->features & NETIF_F_RXALL) { 3172 /* UPE and MPE will be handled by normal PROMISC logic 3173 * in e1000e_set_rx_mode 3174 */ 3175 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3176 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3177 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3178 3179 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3180 E1000_RCTL_DPF | /* Allow filtered pause */ 3181 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3182 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3183 * and that breaks VLANs. 3184 */ 3185 } 3186 3187 ew32(RCTL, rctl); 3188 /* just started the receive unit, no need to restart */ 3189 adapter->flags &= ~FLAG_RESTART_NOW; 3190 } 3191 3192 /** 3193 * e1000_configure_rx - Configure Receive Unit after Reset 3194 * @adapter: board private structure 3195 * 3196 * Configure the Rx unit of the MAC after a reset. 3197 **/ 3198 static void e1000_configure_rx(struct e1000_adapter *adapter) 3199 { 3200 struct e1000_hw *hw = &adapter->hw; 3201 struct e1000_ring *rx_ring = adapter->rx_ring; 3202 u64 rdba; 3203 u32 rdlen, rctl, rxcsum, ctrl_ext; 3204 3205 if (adapter->rx_ps_pages) { 3206 /* this is a 32 byte descriptor */ 3207 rdlen = rx_ring->count * 3208 sizeof(union e1000_rx_desc_packet_split); 3209 adapter->clean_rx = e1000_clean_rx_irq_ps; 3210 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3211 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3212 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3213 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3214 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3215 } else { 3216 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3217 adapter->clean_rx = e1000_clean_rx_irq; 3218 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3219 } 3220 3221 /* disable receives while setting up the descriptors */ 3222 rctl = er32(RCTL); 3223 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3224 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3225 e1e_flush(); 3226 usleep_range(10000, 11000); 3227 3228 if (adapter->flags2 & FLAG2_DMA_BURST) { 3229 /* set the writeback threshold (only takes effect if the RDTR 3230 * is set). set GRAN=1 and write back up to 0x4 worth, and 3231 * enable prefetching of 0x20 Rx descriptors 3232 * granularity = 01 3233 * wthresh = 04, 3234 * hthresh = 04, 3235 * pthresh = 0x20 3236 */ 3237 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3238 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3239 } 3240 3241 /* set the Receive Delay Timer Register */ 3242 ew32(RDTR, adapter->rx_int_delay); 3243 3244 /* irq moderation */ 3245 ew32(RADV, adapter->rx_abs_int_delay); 3246 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3247 e1000e_write_itr(adapter, adapter->itr); 3248 3249 ctrl_ext = er32(CTRL_EXT); 3250 /* Auto-Mask interrupts upon ICR access */ 3251 ctrl_ext |= E1000_CTRL_EXT_IAME; 3252 ew32(IAM, 0xffffffff); 3253 ew32(CTRL_EXT, ctrl_ext); 3254 e1e_flush(); 3255 3256 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3257 * the Base and Length of the Rx Descriptor Ring 3258 */ 3259 rdba = rx_ring->dma; 3260 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3261 ew32(RDBAH(0), (rdba >> 32)); 3262 ew32(RDLEN(0), rdlen); 3263 ew32(RDH(0), 0); 3264 ew32(RDT(0), 0); 3265 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3266 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3267 3268 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3269 e1000e_update_rdt_wa(rx_ring, 0); 3270 3271 /* Enable Receive Checksum Offload for TCP and UDP */ 3272 rxcsum = er32(RXCSUM); 3273 if (adapter->netdev->features & NETIF_F_RXCSUM) 3274 rxcsum |= E1000_RXCSUM_TUOFL; 3275 else 3276 rxcsum &= ~E1000_RXCSUM_TUOFL; 3277 ew32(RXCSUM, rxcsum); 3278 3279 /* With jumbo frames, excessive C-state transition latencies result 3280 * in dropped transactions. 3281 */ 3282 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3283 u32 lat = 3284 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3285 adapter->max_frame_size) * 8 / 1000; 3286 3287 if (adapter->flags & FLAG_IS_ICH) { 3288 u32 rxdctl = er32(RXDCTL(0)); 3289 3290 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3291 } 3292 3293 dev_info(&adapter->pdev->dev, 3294 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3295 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat); 3296 } else { 3297 cpu_latency_qos_update_request(&adapter->pm_qos_req, 3298 PM_QOS_DEFAULT_VALUE); 3299 } 3300 3301 /* Enable Receives */ 3302 ew32(RCTL, rctl); 3303 } 3304 3305 /** 3306 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3307 * @netdev: network interface device structure 3308 * 3309 * Writes multicast address list to the MTA hash table. 3310 * Returns: -ENOMEM on failure 3311 * 0 on no addresses written 3312 * X on writing X addresses to MTA 3313 */ 3314 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3315 { 3316 struct e1000_adapter *adapter = netdev_priv(netdev); 3317 struct e1000_hw *hw = &adapter->hw; 3318 struct netdev_hw_addr *ha; 3319 u8 *mta_list; 3320 int i; 3321 3322 if (netdev_mc_empty(netdev)) { 3323 /* nothing to program, so clear mc list */ 3324 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3325 return 0; 3326 } 3327 3328 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3329 if (!mta_list) 3330 return -ENOMEM; 3331 3332 /* update_mc_addr_list expects a packed array of only addresses. */ 3333 i = 0; 3334 netdev_for_each_mc_addr(ha, netdev) 3335 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3336 3337 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3338 kfree(mta_list); 3339 3340 return netdev_mc_count(netdev); 3341 } 3342 3343 /** 3344 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3345 * @netdev: network interface device structure 3346 * 3347 * Writes unicast address list to the RAR table. 3348 * Returns: -ENOMEM on failure/insufficient address space 3349 * 0 on no addresses written 3350 * X on writing X addresses to the RAR table 3351 **/ 3352 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3353 { 3354 struct e1000_adapter *adapter = netdev_priv(netdev); 3355 struct e1000_hw *hw = &adapter->hw; 3356 unsigned int rar_entries; 3357 int count = 0; 3358 3359 rar_entries = hw->mac.ops.rar_get_count(hw); 3360 3361 /* save a rar entry for our hardware address */ 3362 rar_entries--; 3363 3364 /* save a rar entry for the LAA workaround */ 3365 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3366 rar_entries--; 3367 3368 /* return ENOMEM indicating insufficient memory for addresses */ 3369 if (netdev_uc_count(netdev) > rar_entries) 3370 return -ENOMEM; 3371 3372 if (!netdev_uc_empty(netdev) && rar_entries) { 3373 struct netdev_hw_addr *ha; 3374 3375 /* write the addresses in reverse order to avoid write 3376 * combining 3377 */ 3378 netdev_for_each_uc_addr(ha, netdev) { 3379 int ret_val; 3380 3381 if (!rar_entries) 3382 break; 3383 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3384 if (ret_val < 0) 3385 return -ENOMEM; 3386 count++; 3387 } 3388 } 3389 3390 /* zero out the remaining RAR entries not used above */ 3391 for (; rar_entries > 0; rar_entries--) { 3392 ew32(RAH(rar_entries), 0); 3393 ew32(RAL(rar_entries), 0); 3394 } 3395 e1e_flush(); 3396 3397 return count; 3398 } 3399 3400 /** 3401 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3402 * @netdev: network interface device structure 3403 * 3404 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3405 * address list or the network interface flags are updated. This routine is 3406 * responsible for configuring the hardware for proper unicast, multicast, 3407 * promiscuous mode, and all-multi behavior. 3408 **/ 3409 static void e1000e_set_rx_mode(struct net_device *netdev) 3410 { 3411 struct e1000_adapter *adapter = netdev_priv(netdev); 3412 struct e1000_hw *hw = &adapter->hw; 3413 u32 rctl; 3414 3415 if (pm_runtime_suspended(netdev->dev.parent)) 3416 return; 3417 3418 /* Check for Promiscuous and All Multicast modes */ 3419 rctl = er32(RCTL); 3420 3421 /* clear the affected bits */ 3422 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3423 3424 if (netdev->flags & IFF_PROMISC) { 3425 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3426 /* Do not hardware filter VLANs in promisc mode */ 3427 e1000e_vlan_filter_disable(adapter); 3428 } else { 3429 int count; 3430 3431 if (netdev->flags & IFF_ALLMULTI) { 3432 rctl |= E1000_RCTL_MPE; 3433 } else { 3434 /* Write addresses to the MTA, if the attempt fails 3435 * then we should just turn on promiscuous mode so 3436 * that we can at least receive multicast traffic 3437 */ 3438 count = e1000e_write_mc_addr_list(netdev); 3439 if (count < 0) 3440 rctl |= E1000_RCTL_MPE; 3441 } 3442 e1000e_vlan_filter_enable(adapter); 3443 /* Write addresses to available RAR registers, if there is not 3444 * sufficient space to store all the addresses then enable 3445 * unicast promiscuous mode 3446 */ 3447 count = e1000e_write_uc_addr_list(netdev); 3448 if (count < 0) 3449 rctl |= E1000_RCTL_UPE; 3450 } 3451 3452 ew32(RCTL, rctl); 3453 3454 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3455 e1000e_vlan_strip_enable(adapter); 3456 else 3457 e1000e_vlan_strip_disable(adapter); 3458 } 3459 3460 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3461 { 3462 struct e1000_hw *hw = &adapter->hw; 3463 u32 mrqc, rxcsum; 3464 u32 rss_key[10]; 3465 int i; 3466 3467 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3468 for (i = 0; i < 10; i++) 3469 ew32(RSSRK(i), rss_key[i]); 3470 3471 /* Direct all traffic to queue 0 */ 3472 for (i = 0; i < 32; i++) 3473 ew32(RETA(i), 0); 3474 3475 /* Disable raw packet checksumming so that RSS hash is placed in 3476 * descriptor on writeback. 3477 */ 3478 rxcsum = er32(RXCSUM); 3479 rxcsum |= E1000_RXCSUM_PCSD; 3480 3481 ew32(RXCSUM, rxcsum); 3482 3483 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3484 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3485 E1000_MRQC_RSS_FIELD_IPV6 | 3486 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3487 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3488 3489 ew32(MRQC, mrqc); 3490 } 3491 3492 /** 3493 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3494 * @adapter: board private structure 3495 * @timinca: pointer to returned time increment attributes 3496 * 3497 * Get attributes for incrementing the System Time Register SYSTIML/H at 3498 * the default base frequency, and set the cyclecounter shift value. 3499 **/ 3500 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3501 { 3502 struct e1000_hw *hw = &adapter->hw; 3503 u32 incvalue, incperiod, shift; 3504 3505 /* Make sure clock is enabled on I217/I218/I219 before checking 3506 * the frequency 3507 */ 3508 if ((hw->mac.type >= e1000_pch_lpt) && 3509 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3510 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3511 u32 fextnvm7 = er32(FEXTNVM7); 3512 3513 if (!(fextnvm7 & BIT(0))) { 3514 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3515 e1e_flush(); 3516 } 3517 } 3518 3519 switch (hw->mac.type) { 3520 case e1000_pch2lan: 3521 /* Stable 96MHz frequency */ 3522 incperiod = INCPERIOD_96MHZ; 3523 incvalue = INCVALUE_96MHZ; 3524 shift = INCVALUE_SHIFT_96MHZ; 3525 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3526 break; 3527 case e1000_pch_lpt: 3528 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3529 /* Stable 96MHz frequency */ 3530 incperiod = INCPERIOD_96MHZ; 3531 incvalue = INCVALUE_96MHZ; 3532 shift = INCVALUE_SHIFT_96MHZ; 3533 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3534 } else { 3535 /* Stable 25MHz frequency */ 3536 incperiod = INCPERIOD_25MHZ; 3537 incvalue = INCVALUE_25MHZ; 3538 shift = INCVALUE_SHIFT_25MHZ; 3539 adapter->cc.shift = shift; 3540 } 3541 break; 3542 case e1000_pch_spt: 3543 /* Stable 24MHz frequency */ 3544 incperiod = INCPERIOD_24MHZ; 3545 incvalue = INCVALUE_24MHZ; 3546 shift = INCVALUE_SHIFT_24MHZ; 3547 adapter->cc.shift = shift; 3548 break; 3549 case e1000_pch_cnp: 3550 case e1000_pch_tgp: 3551 case e1000_pch_adp: 3552 case e1000_pch_nvp: 3553 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3554 /* Stable 24MHz frequency */ 3555 incperiod = INCPERIOD_24MHZ; 3556 incvalue = INCVALUE_24MHZ; 3557 shift = INCVALUE_SHIFT_24MHZ; 3558 adapter->cc.shift = shift; 3559 } else { 3560 /* Stable 38400KHz frequency */ 3561 incperiod = INCPERIOD_38400KHZ; 3562 incvalue = INCVALUE_38400KHZ; 3563 shift = INCVALUE_SHIFT_38400KHZ; 3564 adapter->cc.shift = shift; 3565 } 3566 break; 3567 case e1000_pch_mtp: 3568 case e1000_pch_lnp: 3569 case e1000_pch_ptp: 3570 /* System firmware can misreport this value, so set it to a 3571 * stable 38400KHz frequency. 3572 */ 3573 incperiod = INCPERIOD_38400KHZ; 3574 incvalue = INCVALUE_38400KHZ; 3575 shift = INCVALUE_SHIFT_38400KHZ; 3576 adapter->cc.shift = shift; 3577 break; 3578 case e1000_82574: 3579 case e1000_82583: 3580 /* Stable 25MHz frequency */ 3581 incperiod = INCPERIOD_25MHZ; 3582 incvalue = INCVALUE_25MHZ; 3583 shift = INCVALUE_SHIFT_25MHZ; 3584 adapter->cc.shift = shift; 3585 break; 3586 default: 3587 return -EINVAL; 3588 } 3589 3590 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3591 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3592 3593 return 0; 3594 } 3595 3596 /** 3597 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3598 * @adapter: board private structure 3599 * @config: timestamp configuration 3600 * @extack: netlink extended ACK for error report 3601 * 3602 * Outgoing time stamping can be enabled and disabled. Play nice and 3603 * disable it when requested, although it shouldn't cause any overhead 3604 * when no packet needs it. At most one packet in the queue may be 3605 * marked for time stamping, otherwise it would be impossible to tell 3606 * for sure to which packet the hardware time stamp belongs. 3607 * 3608 * Incoming time stamping has to be configured via the hardware filters. 3609 * Not all combinations are supported, in particular event type has to be 3610 * specified. Matching the kind of event packet is not supported, with the 3611 * exception of "all V2 events regardless of level 2 or 4". 3612 **/ 3613 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3614 struct kernel_hwtstamp_config *config, 3615 struct netlink_ext_ack *extack) 3616 { 3617 struct e1000_hw *hw = &adapter->hw; 3618 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3619 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3620 u32 rxmtrl = 0; 3621 u16 rxudp = 0; 3622 bool is_l4 = false; 3623 bool is_l2 = false; 3624 u32 regval; 3625 3626 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 3627 NL_SET_ERR_MSG(extack, "No HW timestamp support"); 3628 return -EINVAL; 3629 } 3630 3631 switch (config->tx_type) { 3632 case HWTSTAMP_TX_OFF: 3633 tsync_tx_ctl = 0; 3634 break; 3635 case HWTSTAMP_TX_ON: 3636 break; 3637 default: 3638 NL_SET_ERR_MSG(extack, "Unsupported TX HW timestamp type"); 3639 return -ERANGE; 3640 } 3641 3642 switch (config->rx_filter) { 3643 case HWTSTAMP_FILTER_NONE: 3644 tsync_rx_ctl = 0; 3645 break; 3646 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3647 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3648 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3649 is_l4 = true; 3650 break; 3651 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3652 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3653 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3654 is_l4 = true; 3655 break; 3656 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3657 /* Also time stamps V2 L2 Path Delay Request/Response */ 3658 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3659 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3660 is_l2 = true; 3661 break; 3662 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3663 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3664 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3665 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3666 is_l2 = true; 3667 break; 3668 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3669 /* Hardware cannot filter just V2 L4 Sync messages */ 3670 fallthrough; 3671 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3672 /* Also time stamps V2 Path Delay Request/Response. */ 3673 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3674 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3675 is_l2 = true; 3676 is_l4 = true; 3677 break; 3678 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3679 /* Hardware cannot filter just V2 L4 Delay Request messages */ 3680 fallthrough; 3681 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3682 /* Also time stamps V2 Path Delay Request/Response. */ 3683 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3684 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3685 is_l2 = true; 3686 is_l4 = true; 3687 break; 3688 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3689 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3690 /* Hardware cannot filter just V2 L4 or L2 Event messages */ 3691 fallthrough; 3692 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3693 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3694 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3695 is_l2 = true; 3696 is_l4 = true; 3697 break; 3698 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3699 /* For V1, the hardware can only filter Sync messages or 3700 * Delay Request messages but not both so fall-through to 3701 * time stamp all packets. 3702 */ 3703 fallthrough; 3704 case HWTSTAMP_FILTER_NTP_ALL: 3705 case HWTSTAMP_FILTER_ALL: 3706 is_l2 = true; 3707 is_l4 = true; 3708 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3709 config->rx_filter = HWTSTAMP_FILTER_ALL; 3710 break; 3711 default: 3712 NL_SET_ERR_MSG(extack, "Unsupported RX HW timestamp filter"); 3713 return -ERANGE; 3714 } 3715 3716 adapter->hwtstamp_config = *config; 3717 3718 /* enable/disable Tx h/w time stamping */ 3719 regval = er32(TSYNCTXCTL); 3720 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3721 regval |= tsync_tx_ctl; 3722 ew32(TSYNCTXCTL, regval); 3723 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3724 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3725 NL_SET_ERR_MSG(extack, 3726 "Timesync Tx Control register not set as expected"); 3727 return -EAGAIN; 3728 } 3729 3730 /* enable/disable Rx h/w time stamping */ 3731 regval = er32(TSYNCRXCTL); 3732 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3733 regval |= tsync_rx_ctl; 3734 ew32(TSYNCRXCTL, regval); 3735 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3736 E1000_TSYNCRXCTL_TYPE_MASK)) != 3737 (regval & (E1000_TSYNCRXCTL_ENABLED | 3738 E1000_TSYNCRXCTL_TYPE_MASK))) { 3739 NL_SET_ERR_MSG(extack, 3740 "Timesync Rx Control register not set as expected"); 3741 return -EAGAIN; 3742 } 3743 3744 /* L2: define ethertype filter for time stamped packets */ 3745 if (is_l2) 3746 rxmtrl |= ETH_P_1588; 3747 3748 /* define which PTP packets get time stamped */ 3749 ew32(RXMTRL, rxmtrl); 3750 3751 /* Filter by destination port */ 3752 if (is_l4) { 3753 rxudp = PTP_EV_PORT; 3754 cpu_to_be16s(&rxudp); 3755 } 3756 ew32(RXUDP, rxudp); 3757 3758 e1e_flush(); 3759 3760 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3761 er32(RXSTMPH); 3762 er32(TXSTMPH); 3763 3764 return 0; 3765 } 3766 3767 /** 3768 * e1000_configure - configure the hardware for Rx and Tx 3769 * @adapter: private board structure 3770 **/ 3771 static void e1000_configure(struct e1000_adapter *adapter) 3772 { 3773 struct e1000_ring *rx_ring = adapter->rx_ring; 3774 3775 e1000e_set_rx_mode(adapter->netdev); 3776 3777 e1000_restore_vlan(adapter); 3778 e1000_init_manageability_pt(adapter); 3779 3780 e1000_configure_tx(adapter); 3781 3782 if (adapter->netdev->features & NETIF_F_RXHASH) 3783 e1000e_setup_rss_hash(adapter); 3784 e1000_setup_rctl(adapter); 3785 e1000_configure_rx(adapter); 3786 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3787 } 3788 3789 /** 3790 * e1000e_power_up_phy - restore link in case the phy was powered down 3791 * @adapter: address of board private structure 3792 * 3793 * The phy may be powered down to save power and turn off link when the 3794 * driver is unloaded and wake on lan is not enabled (among others) 3795 * *** this routine MUST be followed by a call to e1000e_reset *** 3796 **/ 3797 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3798 { 3799 if (adapter->hw.phy.ops.power_up) 3800 adapter->hw.phy.ops.power_up(&adapter->hw); 3801 3802 adapter->hw.mac.ops.setup_link(&adapter->hw); 3803 } 3804 3805 /** 3806 * e1000_power_down_phy - Power down the PHY 3807 * @adapter: board private structure 3808 * 3809 * Power down the PHY so no link is implied when interface is down. 3810 * The PHY cannot be powered down if management or WoL is active. 3811 */ 3812 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3813 { 3814 if (adapter->hw.phy.ops.power_down) 3815 adapter->hw.phy.ops.power_down(&adapter->hw); 3816 } 3817 3818 /** 3819 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3820 * @adapter: board private structure 3821 * 3822 * We want to clear all pending descriptors from the TX ring. 3823 * zeroing happens when the HW reads the regs. We assign the ring itself as 3824 * the data of the next descriptor. We don't care about the data we are about 3825 * to reset the HW. 3826 */ 3827 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3828 { 3829 struct e1000_hw *hw = &adapter->hw; 3830 struct e1000_ring *tx_ring = adapter->tx_ring; 3831 struct e1000_tx_desc *tx_desc = NULL; 3832 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3833 u16 size = 512; 3834 3835 tctl = er32(TCTL); 3836 ew32(TCTL, tctl | E1000_TCTL_EN); 3837 tdt = er32(TDT(0)); 3838 BUG_ON(tdt != tx_ring->next_to_use); 3839 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3840 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma); 3841 3842 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3843 tx_desc->upper.data = 0; 3844 /* flush descriptors to memory before notifying the HW */ 3845 wmb(); 3846 tx_ring->next_to_use++; 3847 if (tx_ring->next_to_use == tx_ring->count) 3848 tx_ring->next_to_use = 0; 3849 ew32(TDT(0), tx_ring->next_to_use); 3850 usleep_range(200, 250); 3851 } 3852 3853 /** 3854 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3855 * @adapter: board private structure 3856 * 3857 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3858 */ 3859 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3860 { 3861 u32 rctl, rxdctl; 3862 struct e1000_hw *hw = &adapter->hw; 3863 3864 rctl = er32(RCTL); 3865 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3866 e1e_flush(); 3867 usleep_range(100, 150); 3868 3869 rxdctl = er32(RXDCTL(0)); 3870 /* zero the lower 14 bits (prefetch and host thresholds) */ 3871 rxdctl &= 0xffffc000; 3872 3873 /* update thresholds: prefetch threshold to 31, host threshold to 1 3874 * and make sure the granularity is "descriptors" and not "cache lines" 3875 */ 3876 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3877 3878 ew32(RXDCTL(0), rxdctl); 3879 /* momentarily enable the RX ring for the changes to take effect */ 3880 ew32(RCTL, rctl | E1000_RCTL_EN); 3881 e1e_flush(); 3882 usleep_range(100, 150); 3883 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3884 } 3885 3886 /** 3887 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3888 * @adapter: board private structure 3889 * 3890 * In i219, the descriptor rings must be emptied before resetting the HW 3891 * or before changing the device state to D3 during runtime (runtime PM). 3892 * 3893 * Failure to do this will cause the HW to enter a unit hang state which can 3894 * only be released by PCI reset on the device 3895 * 3896 */ 3897 3898 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3899 { 3900 u16 hang_state; 3901 u32 fext_nvm11, tdlen; 3902 struct e1000_hw *hw = &adapter->hw; 3903 3904 /* First, disable MULR fix in FEXTNVM11 */ 3905 fext_nvm11 = er32(FEXTNVM11); 3906 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3907 ew32(FEXTNVM11, fext_nvm11); 3908 /* do nothing if we're not in faulty state, or if the queue is empty */ 3909 tdlen = er32(TDLEN(0)); 3910 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3911 &hang_state); 3912 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3913 return; 3914 e1000_flush_tx_ring(adapter); 3915 /* recheck, maybe the fault is caused by the rx ring */ 3916 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3917 &hang_state); 3918 if (hang_state & FLUSH_DESC_REQUIRED) 3919 e1000_flush_rx_ring(adapter); 3920 } 3921 3922 /** 3923 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3924 * @adapter: board private structure 3925 * 3926 * When the MAC is reset, all hardware bits for timesync will be reset to the 3927 * default values. This function will restore the settings last in place. 3928 * Since the clock SYSTIME registers are reset, we will simply restore the 3929 * cyclecounter to the kernel real clock time. 3930 **/ 3931 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3932 { 3933 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3934 struct e1000_hw *hw = &adapter->hw; 3935 struct netlink_ext_ack extack = {}; 3936 unsigned long flags; 3937 u32 timinca; 3938 s32 ret_val; 3939 3940 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3941 return; 3942 3943 if (info->adjfine) { 3944 /* restore the previous ptp frequency delta */ 3945 ret_val = info->adjfine(info, adapter->ptp_delta); 3946 } else { 3947 /* set the default base frequency if no adjustment possible */ 3948 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3949 if (!ret_val) 3950 ew32(TIMINCA, timinca); 3951 } 3952 3953 if (ret_val) { 3954 dev_warn(&adapter->pdev->dev, 3955 "Failed to restore TIMINCA clock rate delta: %d\n", 3956 ret_val); 3957 return; 3958 } 3959 3960 /* reset the systim ns time counter */ 3961 spin_lock_irqsave(&adapter->systim_lock, flags); 3962 timecounter_init(&adapter->tc, &adapter->cc, 3963 ktime_get_real_ns()); 3964 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3965 3966 /* restore the previous hwtstamp configuration settings */ 3967 ret_val = e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config, 3968 &extack); 3969 if (ret_val) { 3970 if (extack._msg) 3971 e_err("%s\n", extack._msg); 3972 } 3973 } 3974 3975 /** 3976 * e1000e_reset - bring the hardware into a known good state 3977 * @adapter: board private structure 3978 * 3979 * This function boots the hardware and enables some settings that 3980 * require a configuration cycle of the hardware - those cannot be 3981 * set/changed during runtime. After reset the device needs to be 3982 * properly configured for Rx, Tx etc. 3983 */ 3984 void e1000e_reset(struct e1000_adapter *adapter) 3985 { 3986 struct e1000_mac_info *mac = &adapter->hw.mac; 3987 struct e1000_fc_info *fc = &adapter->hw.fc; 3988 struct e1000_hw *hw = &adapter->hw; 3989 u32 tx_space, min_tx_space, min_rx_space; 3990 u32 pba = adapter->pba; 3991 u16 hwm; 3992 3993 /* reset Packet Buffer Allocation to default */ 3994 ew32(PBA, pba); 3995 3996 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3997 /* To maintain wire speed transmits, the Tx FIFO should be 3998 * large enough to accommodate two full transmit packets, 3999 * rounded up to the next 1KB and expressed in KB. Likewise, 4000 * the Rx FIFO should be large enough to accommodate at least 4001 * one full receive packet and is similarly rounded up and 4002 * expressed in KB. 4003 */ 4004 pba = er32(PBA); 4005 /* upper 16 bits has Tx packet buffer allocation size in KB */ 4006 tx_space = pba >> 16; 4007 /* lower 16 bits has Rx packet buffer allocation size in KB */ 4008 pba &= 0xffff; 4009 /* the Tx fifo also stores 16 bytes of information about the Tx 4010 * but don't include ethernet FCS because hardware appends it 4011 */ 4012 min_tx_space = (adapter->max_frame_size + 4013 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 4014 min_tx_space = ALIGN(min_tx_space, 1024); 4015 min_tx_space >>= 10; 4016 /* software strips receive CRC, so leave room for it */ 4017 min_rx_space = adapter->max_frame_size; 4018 min_rx_space = ALIGN(min_rx_space, 1024); 4019 min_rx_space >>= 10; 4020 4021 /* If current Tx allocation is less than the min Tx FIFO size, 4022 * and the min Tx FIFO size is less than the current Rx FIFO 4023 * allocation, take space away from current Rx allocation 4024 */ 4025 if ((tx_space < min_tx_space) && 4026 ((min_tx_space - tx_space) < pba)) { 4027 pba -= min_tx_space - tx_space; 4028 4029 /* if short on Rx space, Rx wins and must trump Tx 4030 * adjustment 4031 */ 4032 if (pba < min_rx_space) 4033 pba = min_rx_space; 4034 } 4035 4036 ew32(PBA, pba); 4037 } 4038 4039 /* flow control settings 4040 * 4041 * The high water mark must be low enough to fit one full frame 4042 * (or the size used for early receive) above it in the Rx FIFO. 4043 * Set it to the lower of: 4044 * - 90% of the Rx FIFO size, and 4045 * - the full Rx FIFO size minus one full frame 4046 */ 4047 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4048 fc->pause_time = 0xFFFF; 4049 else 4050 fc->pause_time = E1000_FC_PAUSE_TIME; 4051 fc->send_xon = true; 4052 fc->current_mode = fc->requested_mode; 4053 4054 switch (hw->mac.type) { 4055 case e1000_ich9lan: 4056 case e1000_ich10lan: 4057 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4058 pba = 14; 4059 ew32(PBA, pba); 4060 fc->high_water = 0x2800; 4061 fc->low_water = fc->high_water - 8; 4062 break; 4063 } 4064 fallthrough; 4065 default: 4066 hwm = min(((pba << 10) * 9 / 10), 4067 ((pba << 10) - adapter->max_frame_size)); 4068 4069 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4070 fc->low_water = fc->high_water - 8; 4071 break; 4072 case e1000_pchlan: 4073 /* Workaround PCH LOM adapter hangs with certain network 4074 * loads. If hangs persist, try disabling Tx flow control. 4075 */ 4076 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4077 fc->high_water = 0x3500; 4078 fc->low_water = 0x1500; 4079 } else { 4080 fc->high_water = 0x5000; 4081 fc->low_water = 0x3000; 4082 } 4083 fc->refresh_time = 0x1000; 4084 break; 4085 case e1000_pch2lan: 4086 case e1000_pch_lpt: 4087 case e1000_pch_spt: 4088 case e1000_pch_cnp: 4089 case e1000_pch_tgp: 4090 case e1000_pch_adp: 4091 case e1000_pch_mtp: 4092 case e1000_pch_lnp: 4093 case e1000_pch_ptp: 4094 case e1000_pch_nvp: 4095 fc->refresh_time = 0xFFFF; 4096 fc->pause_time = 0xFFFF; 4097 4098 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4099 fc->high_water = 0x05C20; 4100 fc->low_water = 0x05048; 4101 break; 4102 } 4103 4104 pba = 14; 4105 ew32(PBA, pba); 4106 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4107 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4108 break; 4109 } 4110 4111 /* Alignment of Tx data is on an arbitrary byte boundary with the 4112 * maximum size per Tx descriptor limited only to the transmit 4113 * allocation of the packet buffer minus 96 bytes with an upper 4114 * limit of 24KB due to receive synchronization limitations. 4115 */ 4116 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4117 24 << 10); 4118 4119 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4120 * fit in receive buffer. 4121 */ 4122 if (adapter->itr_setting & 0x3) { 4123 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4124 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4125 dev_info(&adapter->pdev->dev, 4126 "Interrupt Throttle Rate off\n"); 4127 adapter->flags2 |= FLAG2_DISABLE_AIM; 4128 e1000e_write_itr(adapter, 0); 4129 } 4130 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4131 dev_info(&adapter->pdev->dev, 4132 "Interrupt Throttle Rate on\n"); 4133 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4134 adapter->itr = 20000; 4135 e1000e_write_itr(adapter, adapter->itr); 4136 } 4137 } 4138 4139 if (hw->mac.type >= e1000_pch_spt) 4140 e1000_flush_desc_rings(adapter); 4141 /* Allow time for pending master requests to run */ 4142 mac->ops.reset_hw(hw); 4143 4144 /* For parts with AMT enabled, let the firmware know 4145 * that the network interface is in control 4146 */ 4147 if (adapter->flags & FLAG_HAS_AMT) 4148 e1000e_get_hw_control(adapter); 4149 4150 ew32(WUC, 0); 4151 4152 if (mac->ops.init_hw(hw)) 4153 e_err("Hardware Error\n"); 4154 4155 e1000_update_mng_vlan(adapter); 4156 4157 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4158 ew32(VET, ETH_P_8021Q); 4159 4160 e1000e_reset_adaptive(hw); 4161 4162 /* restore systim and hwtstamp settings */ 4163 e1000e_systim_reset(adapter); 4164 4165 /* Set EEE advertisement as appropriate */ 4166 if (adapter->flags2 & FLAG2_HAS_EEE) { 4167 s32 ret_val; 4168 u16 adv_addr; 4169 4170 switch (hw->phy.type) { 4171 case e1000_phy_82579: 4172 adv_addr = I82579_EEE_ADVERTISEMENT; 4173 break; 4174 case e1000_phy_i217: 4175 adv_addr = I217_EEE_ADVERTISEMENT; 4176 break; 4177 default: 4178 dev_err(&adapter->pdev->dev, 4179 "Invalid PHY type setting EEE advertisement\n"); 4180 return; 4181 } 4182 4183 ret_val = hw->phy.ops.acquire(hw); 4184 if (ret_val) { 4185 dev_err(&adapter->pdev->dev, 4186 "EEE advertisement - unable to acquire PHY\n"); 4187 return; 4188 } 4189 4190 e1000_write_emi_reg_locked(hw, adv_addr, 4191 hw->dev_spec.ich8lan.eee_disable ? 4192 0 : adapter->eee_advert); 4193 4194 hw->phy.ops.release(hw); 4195 } 4196 4197 if (!netif_running(adapter->netdev) && 4198 !test_bit(__E1000_TESTING, &adapter->state)) 4199 e1000_power_down_phy(adapter); 4200 4201 e1000_get_phy_info(hw); 4202 4203 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4204 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4205 u16 phy_data = 0; 4206 /* speed up time to link by disabling smart power down, ignore 4207 * the return value of this function because there is nothing 4208 * different we would do if it failed 4209 */ 4210 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4211 phy_data &= ~IGP02E1000_PM_SPD; 4212 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4213 } 4214 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4215 u32 reg; 4216 4217 /* Fextnvm7 @ 0xe4[2] = 1 */ 4218 reg = er32(FEXTNVM7); 4219 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4220 ew32(FEXTNVM7, reg); 4221 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4222 reg = er32(FEXTNVM9); 4223 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4224 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4225 ew32(FEXTNVM9, reg); 4226 } 4227 4228 } 4229 4230 /** 4231 * e1000e_trigger_lsc - trigger an LSC interrupt 4232 * @adapter: board private structure 4233 * 4234 * Fire a link status change interrupt to start the watchdog. 4235 **/ 4236 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4237 { 4238 struct e1000_hw *hw = &adapter->hw; 4239 4240 if (adapter->msix_entries) 4241 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4242 else 4243 ew32(ICS, E1000_ICS_LSC); 4244 } 4245 4246 void e1000e_up(struct e1000_adapter *adapter) 4247 { 4248 /* hardware has been reset, we need to reload some things */ 4249 e1000_configure(adapter); 4250 4251 clear_bit(__E1000_DOWN, &adapter->state); 4252 4253 if (adapter->msix_entries) 4254 e1000_configure_msix(adapter); 4255 e1000_irq_enable(adapter); 4256 4257 /* Tx queue started by watchdog timer when link is up */ 4258 4259 e1000e_trigger_lsc(adapter); 4260 } 4261 4262 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4263 { 4264 struct e1000_hw *hw = &adapter->hw; 4265 4266 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4267 return; 4268 4269 /* flush pending descriptor writebacks to memory */ 4270 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4271 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4272 4273 /* execute the writes immediately */ 4274 e1e_flush(); 4275 4276 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4277 * write is successful 4278 */ 4279 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4280 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4281 4282 /* execute the writes immediately */ 4283 e1e_flush(); 4284 } 4285 4286 static void e1000e_update_stats(struct e1000_adapter *adapter); 4287 4288 /** 4289 * e1000e_down - quiesce the device and optionally reset the hardware 4290 * @adapter: board private structure 4291 * @reset: boolean flag to reset the hardware or not 4292 */ 4293 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4294 { 4295 struct net_device *netdev = adapter->netdev; 4296 struct e1000_hw *hw = &adapter->hw; 4297 u32 tctl, rctl; 4298 4299 /* signal that we're down so the interrupt handler does not 4300 * reschedule our watchdog timer 4301 */ 4302 set_bit(__E1000_DOWN, &adapter->state); 4303 4304 netif_carrier_off(netdev); 4305 4306 /* disable receives in the hardware */ 4307 rctl = er32(RCTL); 4308 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4309 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4310 /* flush and sleep below */ 4311 4312 netif_stop_queue(netdev); 4313 4314 /* disable transmits in the hardware */ 4315 tctl = er32(TCTL); 4316 tctl &= ~E1000_TCTL_EN; 4317 ew32(TCTL, tctl); 4318 4319 /* flush both disables and wait for them to finish */ 4320 e1e_flush(); 4321 usleep_range(10000, 11000); 4322 4323 e1000_irq_disable(adapter); 4324 4325 napi_synchronize(&adapter->napi); 4326 4327 timer_delete_sync(&adapter->watchdog_timer); 4328 timer_delete_sync(&adapter->phy_info_timer); 4329 4330 spin_lock(&adapter->stats64_lock); 4331 e1000e_update_stats(adapter); 4332 spin_unlock(&adapter->stats64_lock); 4333 4334 e1000e_flush_descriptors(adapter); 4335 4336 adapter->link_speed = 0; 4337 adapter->link_duplex = 0; 4338 4339 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4340 if ((hw->mac.type >= e1000_pch2lan) && 4341 (adapter->netdev->mtu > ETH_DATA_LEN) && 4342 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4343 e_dbg("failed to disable jumbo frame workaround mode\n"); 4344 4345 if (!pci_channel_offline(adapter->pdev)) { 4346 if (reset) 4347 e1000e_reset(adapter); 4348 else if (hw->mac.type >= e1000_pch_spt) 4349 e1000_flush_desc_rings(adapter); 4350 } 4351 e1000_clean_tx_ring(adapter->tx_ring); 4352 e1000_clean_rx_ring(adapter->rx_ring); 4353 } 4354 4355 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4356 { 4357 might_sleep(); 4358 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4359 usleep_range(1000, 1100); 4360 e1000e_down(adapter, true); 4361 e1000e_up(adapter); 4362 clear_bit(__E1000_RESETTING, &adapter->state); 4363 } 4364 4365 /** 4366 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4367 * @hw: pointer to the HW structure 4368 * @systim: PHC time value read, sanitized and returned 4369 * @sts: structure to hold system time before and after reading SYSTIML, 4370 * may be NULL 4371 * 4372 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4373 * check to see that the time is incrementing at a reasonable 4374 * rate and is a multiple of incvalue. 4375 **/ 4376 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4377 struct ptp_system_timestamp *sts) 4378 { 4379 u64 time_delta, rem, temp; 4380 u64 systim_next; 4381 u32 incvalue; 4382 int i; 4383 4384 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4385 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4386 /* latch SYSTIMH on read of SYSTIML */ 4387 ptp_read_system_prets(sts); 4388 systim_next = (u64)er32(SYSTIML); 4389 ptp_read_system_postts(sts); 4390 systim_next |= (u64)er32(SYSTIMH) << 32; 4391 4392 time_delta = systim_next - systim; 4393 temp = time_delta; 4394 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4395 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4396 4397 systim = systim_next; 4398 4399 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4400 break; 4401 } 4402 4403 return systim; 4404 } 4405 4406 /** 4407 * e1000e_read_systim - read SYSTIM register 4408 * @adapter: board private structure 4409 * @sts: structure which will contain system time before and after reading 4410 * SYSTIML, may be NULL 4411 **/ 4412 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4413 struct ptp_system_timestamp *sts) 4414 { 4415 struct e1000_hw *hw = &adapter->hw; 4416 u32 systimel, systimel_2, systimeh; 4417 u64 systim; 4418 /* SYSTIMH latching upon SYSTIML read does not work well. 4419 * This means that if SYSTIML overflows after we read it but before 4420 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4421 * will experience a huge non linear increment in the systime value 4422 * to fix that we test for overflow and if true, we re-read systime. 4423 */ 4424 ptp_read_system_prets(sts); 4425 systimel = er32(SYSTIML); 4426 ptp_read_system_postts(sts); 4427 systimeh = er32(SYSTIMH); 4428 /* Is systimel is so large that overflow is possible? */ 4429 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4430 ptp_read_system_prets(sts); 4431 systimel_2 = er32(SYSTIML); 4432 ptp_read_system_postts(sts); 4433 if (systimel > systimel_2) { 4434 /* There was an overflow, read again SYSTIMH, and use 4435 * systimel_2 4436 */ 4437 systimeh = er32(SYSTIMH); 4438 systimel = systimel_2; 4439 } 4440 } 4441 systim = (u64)systimel; 4442 systim |= (u64)systimeh << 32; 4443 4444 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4445 systim = e1000e_sanitize_systim(hw, systim, sts); 4446 4447 return systim; 4448 } 4449 4450 /** 4451 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4452 * @cc: cyclecounter structure 4453 **/ 4454 static u64 e1000e_cyclecounter_read(struct cyclecounter *cc) 4455 { 4456 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4457 cc); 4458 4459 return e1000e_read_systim(adapter, NULL); 4460 } 4461 4462 /** 4463 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4464 * @adapter: board private structure to initialize 4465 * 4466 * e1000_sw_init initializes the Adapter private data structure. 4467 * Fields are initialized based on PCI device information and 4468 * OS network device settings (MTU size). 4469 **/ 4470 static int e1000_sw_init(struct e1000_adapter *adapter) 4471 { 4472 struct net_device *netdev = adapter->netdev; 4473 4474 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4475 adapter->rx_ps_bsize0 = 128; 4476 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4477 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4478 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4479 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4480 4481 spin_lock_init(&adapter->stats64_lock); 4482 4483 e1000e_set_interrupt_capability(adapter); 4484 4485 if (e1000_alloc_queues(adapter)) 4486 return -ENOMEM; 4487 4488 /* Setup hardware time stamping cyclecounter */ 4489 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4490 adapter->cc.read = e1000e_cyclecounter_read; 4491 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4492 adapter->cc.mult = 1; 4493 /* cc.shift set in e1000e_get_base_tininca() */ 4494 4495 spin_lock_init(&adapter->systim_lock); 4496 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4497 } 4498 4499 /* Explicitly disable IRQ since the NIC can be in any state. */ 4500 e1000_irq_disable(adapter); 4501 4502 set_bit(__E1000_DOWN, &adapter->state); 4503 return 0; 4504 } 4505 4506 /** 4507 * e1000_intr_msi_test - Interrupt Handler 4508 * @irq: interrupt number 4509 * @data: pointer to a network interface device structure 4510 **/ 4511 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4512 { 4513 struct net_device *netdev = data; 4514 struct e1000_adapter *adapter = netdev_priv(netdev); 4515 struct e1000_hw *hw = &adapter->hw; 4516 u32 icr = er32(ICR); 4517 4518 e_dbg("icr is %08X\n", icr); 4519 if (icr & E1000_ICR_RXSEQ) { 4520 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4521 /* Force memory writes to complete before acknowledging the 4522 * interrupt is handled. 4523 */ 4524 wmb(); 4525 } 4526 4527 return IRQ_HANDLED; 4528 } 4529 4530 /** 4531 * e1000_test_msi_interrupt - Returns 0 for successful test 4532 * @adapter: board private struct 4533 * 4534 * code flow taken from tg3.c 4535 **/ 4536 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4537 { 4538 struct net_device *netdev = adapter->netdev; 4539 struct e1000_hw *hw = &adapter->hw; 4540 int err; 4541 4542 /* poll_enable hasn't been called yet, so don't need disable */ 4543 /* clear any pending events */ 4544 er32(ICR); 4545 4546 /* free the real vector and request a test handler */ 4547 e1000_free_irq(adapter); 4548 e1000e_reset_interrupt_capability(adapter); 4549 4550 /* Assume that the test fails, if it succeeds then the test 4551 * MSI irq handler will unset this flag 4552 */ 4553 adapter->flags |= FLAG_MSI_TEST_FAILED; 4554 4555 err = pci_enable_msi(adapter->pdev); 4556 if (err) 4557 goto msi_test_failed; 4558 4559 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4560 netdev->name, netdev); 4561 if (err) { 4562 pci_disable_msi(adapter->pdev); 4563 goto msi_test_failed; 4564 } 4565 4566 /* Force memory writes to complete before enabling and firing an 4567 * interrupt. 4568 */ 4569 wmb(); 4570 4571 e1000_irq_enable(adapter); 4572 4573 /* fire an unusual interrupt on the test handler */ 4574 ew32(ICS, E1000_ICS_RXSEQ); 4575 e1e_flush(); 4576 msleep(100); 4577 4578 e1000_irq_disable(adapter); 4579 4580 rmb(); /* read flags after interrupt has been fired */ 4581 4582 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4583 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4584 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4585 } else { 4586 e_dbg("MSI interrupt test succeeded!\n"); 4587 } 4588 4589 free_irq(adapter->pdev->irq, netdev); 4590 pci_disable_msi(adapter->pdev); 4591 4592 msi_test_failed: 4593 e1000e_set_interrupt_capability(adapter); 4594 return e1000_request_irq(adapter); 4595 } 4596 4597 /** 4598 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4599 * @adapter: board private struct 4600 * 4601 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4602 **/ 4603 static int e1000_test_msi(struct e1000_adapter *adapter) 4604 { 4605 int err; 4606 u16 pci_cmd; 4607 4608 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4609 return 0; 4610 4611 /* disable SERR in case the MSI write causes a master abort */ 4612 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4613 if (pci_cmd & PCI_COMMAND_SERR) 4614 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4615 pci_cmd & ~PCI_COMMAND_SERR); 4616 4617 err = e1000_test_msi_interrupt(adapter); 4618 4619 /* re-enable SERR */ 4620 if (pci_cmd & PCI_COMMAND_SERR) { 4621 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4622 pci_cmd |= PCI_COMMAND_SERR; 4623 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4624 } 4625 4626 return err; 4627 } 4628 4629 /** 4630 * e1000e_open - Called when a network interface is made active 4631 * @netdev: network interface device structure 4632 * 4633 * Returns 0 on success, negative value on failure 4634 * 4635 * The open entry point is called when a network interface is made 4636 * active by the system (IFF_UP). At this point all resources needed 4637 * for transmit and receive operations are allocated, the interrupt 4638 * handler is registered with the OS, the watchdog timer is started, 4639 * and the stack is notified that the interface is ready. 4640 **/ 4641 int e1000e_open(struct net_device *netdev) 4642 { 4643 struct e1000_adapter *adapter = netdev_priv(netdev); 4644 struct e1000_hw *hw = &adapter->hw; 4645 struct pci_dev *pdev = adapter->pdev; 4646 int err; 4647 int irq; 4648 4649 /* disallow open during test */ 4650 if (test_bit(__E1000_TESTING, &adapter->state)) 4651 return -EBUSY; 4652 4653 pm_runtime_get_sync(&pdev->dev); 4654 4655 netif_carrier_off(netdev); 4656 netif_stop_queue(netdev); 4657 4658 /* allocate transmit descriptors */ 4659 err = e1000e_setup_tx_resources(adapter->tx_ring); 4660 if (err) 4661 goto err_setup_tx; 4662 4663 /* allocate receive descriptors */ 4664 err = e1000e_setup_rx_resources(adapter->rx_ring); 4665 if (err) 4666 goto err_setup_rx; 4667 4668 /* If AMT is enabled, let the firmware know that the network 4669 * interface is now open and reset the part to a known state. 4670 */ 4671 if (adapter->flags & FLAG_HAS_AMT) { 4672 e1000e_get_hw_control(adapter); 4673 e1000e_reset(adapter); 4674 } 4675 4676 e1000e_power_up_phy(adapter); 4677 4678 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4679 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4680 e1000_update_mng_vlan(adapter); 4681 4682 /* DMA latency requirement to workaround jumbo issue */ 4683 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE); 4684 4685 /* before we allocate an interrupt, we must be ready to handle it. 4686 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4687 * as soon as we call pci_request_irq, so we have to setup our 4688 * clean_rx handler before we do so. 4689 */ 4690 e1000_configure(adapter); 4691 4692 err = e1000_request_irq(adapter); 4693 if (err) 4694 goto err_req_irq; 4695 4696 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4697 * ignore e1000e MSI messages, which means we need to test our MSI 4698 * interrupt now 4699 */ 4700 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4701 err = e1000_test_msi(adapter); 4702 if (err) { 4703 e_err("Interrupt allocation failed\n"); 4704 goto err_req_irq; 4705 } 4706 } 4707 4708 /* From here on the code is the same as e1000e_up() */ 4709 clear_bit(__E1000_DOWN, &adapter->state); 4710 4711 if (adapter->int_mode == E1000E_INT_MODE_MSIX) 4712 irq = adapter->msix_entries[0].vector; 4713 else 4714 irq = adapter->pdev->irq; 4715 4716 netif_napi_set_irq(&adapter->napi, irq); 4717 napi_enable(&adapter->napi); 4718 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, &adapter->napi); 4719 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, &adapter->napi); 4720 4721 e1000_irq_enable(adapter); 4722 4723 adapter->tx_hang_recheck = false; 4724 4725 hw->mac.get_link_status = true; 4726 pm_runtime_put(&pdev->dev); 4727 4728 e1000e_trigger_lsc(adapter); 4729 4730 return 0; 4731 4732 err_req_irq: 4733 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4734 e1000e_release_hw_control(adapter); 4735 e1000_power_down_phy(adapter); 4736 e1000e_free_rx_resources(adapter->rx_ring); 4737 err_setup_rx: 4738 e1000e_free_tx_resources(adapter->tx_ring); 4739 err_setup_tx: 4740 e1000e_reset(adapter); 4741 pm_runtime_put_sync(&pdev->dev); 4742 4743 return err; 4744 } 4745 4746 /** 4747 * e1000e_close - Disables a network interface 4748 * @netdev: network interface device structure 4749 * 4750 * Returns 0, this is not allowed to fail 4751 * 4752 * The close entry point is called when an interface is de-activated 4753 * by the OS. The hardware is still under the drivers control, but 4754 * needs to be disabled. A global MAC reset is issued to stop the 4755 * hardware, and all transmit and receive resources are freed. 4756 **/ 4757 int e1000e_close(struct net_device *netdev) 4758 { 4759 struct e1000_adapter *adapter = netdev_priv(netdev); 4760 struct pci_dev *pdev = adapter->pdev; 4761 int count = E1000_CHECK_RESET_COUNT; 4762 4763 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4764 usleep_range(10000, 11000); 4765 4766 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4767 4768 pm_runtime_get_sync(&pdev->dev); 4769 4770 if (netif_device_present(netdev)) { 4771 e1000e_down(adapter, true); 4772 e1000_free_irq(adapter); 4773 4774 /* Link status message must follow this format */ 4775 netdev_info(netdev, "NIC Link is Down\n"); 4776 } 4777 4778 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, NULL); 4779 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, NULL); 4780 napi_disable(&adapter->napi); 4781 4782 e1000e_free_tx_resources(adapter->tx_ring); 4783 e1000e_free_rx_resources(adapter->rx_ring); 4784 4785 /* kill manageability vlan ID if supported, but not if a vlan with 4786 * the same ID is registered on the host OS (let 8021q kill it) 4787 */ 4788 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4789 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4790 adapter->mng_vlan_id); 4791 4792 /* If AMT is enabled, let the firmware know that the network 4793 * interface is now closed 4794 */ 4795 if ((adapter->flags & FLAG_HAS_AMT) && 4796 !test_bit(__E1000_TESTING, &adapter->state)) 4797 e1000e_release_hw_control(adapter); 4798 4799 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4800 4801 pm_runtime_put_sync(&pdev->dev); 4802 4803 return 0; 4804 } 4805 4806 /** 4807 * e1000_set_mac - Change the Ethernet Address of the NIC 4808 * @netdev: network interface device structure 4809 * @p: pointer to an address structure 4810 * 4811 * Returns 0 on success, negative on failure 4812 **/ 4813 static int e1000_set_mac(struct net_device *netdev, void *p) 4814 { 4815 struct e1000_adapter *adapter = netdev_priv(netdev); 4816 struct e1000_hw *hw = &adapter->hw; 4817 struct sockaddr *addr = p; 4818 4819 if (!is_valid_ether_addr(addr->sa_data)) 4820 return -EADDRNOTAVAIL; 4821 4822 eth_hw_addr_set(netdev, addr->sa_data); 4823 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4824 4825 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4826 4827 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4828 /* activate the work around */ 4829 e1000e_set_laa_state_82571(&adapter->hw, 1); 4830 4831 /* Hold a copy of the LAA in RAR[14] This is done so that 4832 * between the time RAR[0] gets clobbered and the time it 4833 * gets fixed (in e1000_watchdog), the actual LAA is in one 4834 * of the RARs and no incoming packets directed to this port 4835 * are dropped. Eventually the LAA will be in RAR[0] and 4836 * RAR[14] 4837 */ 4838 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4839 adapter->hw.mac.rar_entry_count - 1); 4840 } 4841 4842 return 0; 4843 } 4844 4845 /** 4846 * e1000e_update_phy_task - work thread to update phy 4847 * @work: pointer to our work struct 4848 * 4849 * this worker thread exists because we must acquire a 4850 * semaphore to read the phy, which we could msleep while 4851 * waiting for it, and we can't msleep in a timer. 4852 **/ 4853 static void e1000e_update_phy_task(struct work_struct *work) 4854 { 4855 struct e1000_adapter *adapter = container_of(work, 4856 struct e1000_adapter, 4857 update_phy_task); 4858 struct e1000_hw *hw = &adapter->hw; 4859 4860 if (test_bit(__E1000_DOWN, &adapter->state)) 4861 return; 4862 4863 e1000_get_phy_info(hw); 4864 4865 /* Enable EEE on 82579 after link up */ 4866 if (hw->phy.type >= e1000_phy_82579) 4867 e1000_set_eee_pchlan(hw); 4868 } 4869 4870 /** 4871 * e1000_update_phy_info - timre call-back to update PHY info 4872 * @t: pointer to timer_list containing private info adapter 4873 * 4874 * Need to wait a few seconds after link up to get diagnostic information from 4875 * the phy 4876 **/ 4877 static void e1000_update_phy_info(struct timer_list *t) 4878 { 4879 struct e1000_adapter *adapter = timer_container_of(adapter, t, 4880 phy_info_timer); 4881 4882 if (test_bit(__E1000_DOWN, &adapter->state)) 4883 return; 4884 4885 schedule_work(&adapter->update_phy_task); 4886 } 4887 4888 /** 4889 * e1000e_update_phy_stats - Update the PHY statistics counters 4890 * @adapter: board private structure 4891 * 4892 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4893 **/ 4894 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4895 { 4896 struct e1000_hw *hw = &adapter->hw; 4897 s32 ret_val; 4898 u16 phy_data; 4899 4900 ret_val = hw->phy.ops.acquire(hw); 4901 if (ret_val) 4902 return; 4903 4904 /* A page set is expensive so check if already on desired page. 4905 * If not, set to the page with the PHY status registers. 4906 */ 4907 hw->phy.addr = 1; 4908 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4909 &phy_data); 4910 if (ret_val) 4911 goto release; 4912 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4913 ret_val = hw->phy.ops.set_page(hw, 4914 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4915 if (ret_val) 4916 goto release; 4917 } 4918 4919 /* Single Collision Count */ 4920 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4921 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4922 if (!ret_val) 4923 adapter->stats.scc += phy_data; 4924 4925 /* Excessive Collision Count */ 4926 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4927 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4928 if (!ret_val) 4929 adapter->stats.ecol += phy_data; 4930 4931 /* Multiple Collision Count */ 4932 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4933 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4934 if (!ret_val) 4935 adapter->stats.mcc += phy_data; 4936 4937 /* Late Collision Count */ 4938 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4939 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4940 if (!ret_val) 4941 adapter->stats.latecol += phy_data; 4942 4943 /* Collision Count - also used for adaptive IFS */ 4944 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4945 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4946 if (!ret_val) 4947 hw->mac.collision_delta = phy_data; 4948 4949 /* Defer Count */ 4950 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4951 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4952 if (!ret_val) 4953 adapter->stats.dc += phy_data; 4954 4955 /* Transmit with no CRS */ 4956 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4957 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4958 if (!ret_val) 4959 adapter->stats.tncrs += phy_data; 4960 4961 release: 4962 hw->phy.ops.release(hw); 4963 } 4964 4965 /** 4966 * e1000e_update_stats - Update the board statistics counters 4967 * @adapter: board private structure 4968 **/ 4969 static void e1000e_update_stats(struct e1000_adapter *adapter) 4970 { 4971 struct net_device *netdev = adapter->netdev; 4972 struct e1000_hw *hw = &adapter->hw; 4973 struct pci_dev *pdev = adapter->pdev; 4974 4975 /* Prevent stats update while adapter is being reset, or if the pci 4976 * connection is down. 4977 */ 4978 if (adapter->link_speed == 0) 4979 return; 4980 if (pci_channel_offline(pdev)) 4981 return; 4982 4983 adapter->stats.crcerrs += er32(CRCERRS); 4984 adapter->stats.gprc += er32(GPRC); 4985 adapter->stats.gorc += er32(GORCL); 4986 er32(GORCH); /* Clear gorc */ 4987 adapter->stats.bprc += er32(BPRC); 4988 adapter->stats.mprc += er32(MPRC); 4989 adapter->stats.roc += er32(ROC); 4990 4991 adapter->stats.mpc += er32(MPC); 4992 4993 /* Half-duplex statistics */ 4994 if (adapter->link_duplex == HALF_DUPLEX) { 4995 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4996 e1000e_update_phy_stats(adapter); 4997 } else { 4998 adapter->stats.scc += er32(SCC); 4999 adapter->stats.ecol += er32(ECOL); 5000 adapter->stats.mcc += er32(MCC); 5001 adapter->stats.latecol += er32(LATECOL); 5002 adapter->stats.dc += er32(DC); 5003 5004 hw->mac.collision_delta = er32(COLC); 5005 5006 if ((hw->mac.type != e1000_82574) && 5007 (hw->mac.type != e1000_82583)) 5008 adapter->stats.tncrs += er32(TNCRS); 5009 } 5010 adapter->stats.colc += hw->mac.collision_delta; 5011 } 5012 5013 adapter->stats.xonrxc += er32(XONRXC); 5014 adapter->stats.xontxc += er32(XONTXC); 5015 adapter->stats.xoffrxc += er32(XOFFRXC); 5016 adapter->stats.xofftxc += er32(XOFFTXC); 5017 adapter->stats.gptc += er32(GPTC); 5018 adapter->stats.gotc += er32(GOTCL); 5019 er32(GOTCH); /* Clear gotc */ 5020 adapter->stats.rnbc += er32(RNBC); 5021 adapter->stats.ruc += er32(RUC); 5022 5023 adapter->stats.mptc += er32(MPTC); 5024 adapter->stats.bptc += er32(BPTC); 5025 5026 /* used for adaptive IFS */ 5027 5028 hw->mac.tx_packet_delta = er32(TPT); 5029 adapter->stats.tpt += hw->mac.tx_packet_delta; 5030 5031 adapter->stats.algnerrc += er32(ALGNERRC); 5032 adapter->stats.rxerrc += er32(RXERRC); 5033 adapter->stats.cexterr += er32(CEXTERR); 5034 adapter->stats.tsctc += er32(TSCTC); 5035 adapter->stats.tsctfc += er32(TSCTFC); 5036 5037 /* Fill out the OS statistics structure */ 5038 netdev->stats.multicast = adapter->stats.mprc; 5039 netdev->stats.collisions = adapter->stats.colc; 5040 5041 /* Rx Errors */ 5042 5043 /* RLEC on some newer hardware can be incorrect so build 5044 * our own version based on RUC and ROC 5045 */ 5046 netdev->stats.rx_errors = adapter->stats.rxerrc + 5047 adapter->stats.crcerrs + adapter->stats.algnerrc + 5048 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5049 netdev->stats.rx_length_errors = adapter->stats.ruc + 5050 adapter->stats.roc; 5051 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5052 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5053 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5054 5055 /* Tx Errors */ 5056 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5057 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5058 netdev->stats.tx_window_errors = adapter->stats.latecol; 5059 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5060 5061 /* Tx Dropped needs to be maintained elsewhere */ 5062 5063 /* Management Stats */ 5064 adapter->stats.mgptc += er32(MGTPTC); 5065 adapter->stats.mgprc += er32(MGTPRC); 5066 adapter->stats.mgpdc += er32(MGTPDC); 5067 5068 /* Correctable ECC Errors */ 5069 if (hw->mac.type >= e1000_pch_lpt) { 5070 u32 pbeccsts = er32(PBECCSTS); 5071 5072 adapter->corr_errors += 5073 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5074 adapter->uncorr_errors += 5075 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 5076 } 5077 } 5078 5079 /** 5080 * e1000_phy_read_status - Update the PHY register status snapshot 5081 * @adapter: board private structure 5082 **/ 5083 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5084 { 5085 struct e1000_hw *hw = &adapter->hw; 5086 struct e1000_phy_regs *phy = &adapter->phy_regs; 5087 5088 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5089 (er32(STATUS) & E1000_STATUS_LU) && 5090 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5091 int ret_val; 5092 5093 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5094 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5095 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5096 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5097 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5098 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5099 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5100 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5101 if (ret_val) 5102 e_warn("Error reading PHY register\n"); 5103 } else { 5104 /* Do not read PHY registers if link is not up 5105 * Set values to typical power-on defaults 5106 */ 5107 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5108 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5109 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5110 BMSR_ERCAP); 5111 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5112 ADVERTISE_ALL | ADVERTISE_CSMA); 5113 phy->lpa = 0; 5114 phy->expansion = EXPANSION_ENABLENPAGE; 5115 phy->ctrl1000 = ADVERTISE_1000FULL; 5116 phy->stat1000 = 0; 5117 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5118 } 5119 } 5120 5121 static void e1000_print_link_info(struct e1000_adapter *adapter) 5122 { 5123 struct e1000_hw *hw = &adapter->hw; 5124 u32 ctrl = er32(CTRL); 5125 5126 /* Link status message must follow this format for user tools */ 5127 netdev_info(adapter->netdev, 5128 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5129 adapter->link_speed, 5130 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5131 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5132 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5133 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5134 } 5135 5136 static bool e1000e_has_link(struct e1000_adapter *adapter) 5137 { 5138 struct e1000_hw *hw = &adapter->hw; 5139 bool link_active = false; 5140 s32 ret_val = 0; 5141 5142 /* get_link_status is set on LSC (link status) interrupt or 5143 * Rx sequence error interrupt. get_link_status will stay 5144 * true until the check_for_link establishes link 5145 * for copper adapters ONLY 5146 */ 5147 switch (hw->phy.media_type) { 5148 case e1000_media_type_copper: 5149 if (hw->mac.get_link_status) { 5150 ret_val = hw->mac.ops.check_for_link(hw); 5151 link_active = !hw->mac.get_link_status; 5152 } else { 5153 link_active = true; 5154 } 5155 break; 5156 case e1000_media_type_fiber: 5157 ret_val = hw->mac.ops.check_for_link(hw); 5158 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5159 break; 5160 case e1000_media_type_internal_serdes: 5161 ret_val = hw->mac.ops.check_for_link(hw); 5162 link_active = hw->mac.serdes_has_link; 5163 break; 5164 default: 5165 case e1000_media_type_unknown: 5166 break; 5167 } 5168 5169 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5170 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5171 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5172 e_info("Gigabit has been disabled, downgrading speed\n"); 5173 } 5174 5175 return link_active; 5176 } 5177 5178 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5179 { 5180 /* make sure the receive unit is started */ 5181 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5182 (adapter->flags & FLAG_RESTART_NOW)) { 5183 struct e1000_hw *hw = &adapter->hw; 5184 u32 rctl = er32(RCTL); 5185 5186 ew32(RCTL, rctl | E1000_RCTL_EN); 5187 adapter->flags &= ~FLAG_RESTART_NOW; 5188 } 5189 } 5190 5191 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5192 { 5193 struct e1000_hw *hw = &adapter->hw; 5194 5195 /* With 82574 controllers, PHY needs to be checked periodically 5196 * for hung state and reset, if two calls return true 5197 */ 5198 if (e1000_check_phy_82574(hw)) 5199 adapter->phy_hang_count++; 5200 else 5201 adapter->phy_hang_count = 0; 5202 5203 if (adapter->phy_hang_count > 1) { 5204 adapter->phy_hang_count = 0; 5205 e_dbg("PHY appears hung - resetting\n"); 5206 schedule_work(&adapter->reset_task); 5207 } 5208 } 5209 5210 /** 5211 * e1000_watchdog - Timer Call-back 5212 * @t: pointer to timer_list containing private info adapter 5213 **/ 5214 static void e1000_watchdog(struct timer_list *t) 5215 { 5216 struct e1000_adapter *adapter = timer_container_of(adapter, t, 5217 watchdog_timer); 5218 5219 /* Do the rest outside of interrupt context */ 5220 schedule_work(&adapter->watchdog_task); 5221 5222 /* TODO: make this use queue_delayed_work() */ 5223 } 5224 5225 static void e1000_watchdog_task(struct work_struct *work) 5226 { 5227 struct e1000_adapter *adapter = container_of(work, 5228 struct e1000_adapter, 5229 watchdog_task); 5230 struct net_device *netdev = adapter->netdev; 5231 struct e1000_mac_info *mac = &adapter->hw.mac; 5232 struct e1000_phy_info *phy = &adapter->hw.phy; 5233 struct e1000_ring *tx_ring = adapter->tx_ring; 5234 u32 dmoff_exit_timeout = 100, tries = 0; 5235 struct e1000_hw *hw = &adapter->hw; 5236 u32 link, tctl, pcim_state; 5237 5238 if (test_bit(__E1000_DOWN, &adapter->state)) 5239 return; 5240 5241 link = e1000e_has_link(adapter); 5242 if ((netif_carrier_ok(netdev)) && link) { 5243 /* Cancel scheduled suspend requests. */ 5244 pm_runtime_resume(netdev->dev.parent); 5245 5246 e1000e_enable_receives(adapter); 5247 goto link_up; 5248 } 5249 5250 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5251 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5252 e1000_update_mng_vlan(adapter); 5253 5254 if (link) { 5255 if (!netif_carrier_ok(netdev)) { 5256 bool txb2b = true; 5257 5258 /* Cancel scheduled suspend requests. */ 5259 pm_runtime_resume(netdev->dev.parent); 5260 5261 /* Checking if MAC is in DMoff state*/ 5262 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 5263 pcim_state = er32(STATUS); 5264 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5265 if (tries++ == dmoff_exit_timeout) { 5266 e_dbg("Error in exiting dmoff\n"); 5267 break; 5268 } 5269 usleep_range(10000, 20000); 5270 pcim_state = er32(STATUS); 5271 5272 /* Checking if MAC exited DMoff state */ 5273 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5274 e1000_phy_hw_reset(&adapter->hw); 5275 } 5276 } 5277 5278 /* update snapshot of PHY registers on LSC */ 5279 e1000_phy_read_status(adapter); 5280 mac->ops.get_link_up_info(&adapter->hw, 5281 &adapter->link_speed, 5282 &adapter->link_duplex); 5283 e1000_print_link_info(adapter); 5284 5285 /* check if SmartSpeed worked */ 5286 e1000e_check_downshift(hw); 5287 if (phy->speed_downgraded) 5288 netdev_warn(netdev, 5289 "Link Speed was downgraded by SmartSpeed\n"); 5290 5291 /* On supported PHYs, check for duplex mismatch only 5292 * if link has autonegotiated at 10/100 half 5293 */ 5294 if ((hw->phy.type == e1000_phy_igp_3 || 5295 hw->phy.type == e1000_phy_bm) && 5296 hw->mac.autoneg && 5297 (adapter->link_speed == SPEED_10 || 5298 adapter->link_speed == SPEED_100) && 5299 (adapter->link_duplex == HALF_DUPLEX)) { 5300 u16 autoneg_exp; 5301 5302 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5303 5304 if (!(autoneg_exp & EXPANSION_NWAY)) 5305 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5306 } 5307 5308 /* adjust timeout factor according to speed/duplex */ 5309 adapter->tx_timeout_factor = 1; 5310 switch (adapter->link_speed) { 5311 case SPEED_10: 5312 txb2b = false; 5313 adapter->tx_timeout_factor = 16; 5314 break; 5315 case SPEED_100: 5316 txb2b = false; 5317 adapter->tx_timeout_factor = 10; 5318 break; 5319 } 5320 5321 /* workaround: re-program speed mode bit after 5322 * link-up event 5323 */ 5324 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5325 !txb2b) { 5326 u32 tarc0; 5327 5328 tarc0 = er32(TARC(0)); 5329 tarc0 &= ~SPEED_MODE_BIT; 5330 ew32(TARC(0), tarc0); 5331 } 5332 5333 /* enable transmits in the hardware, need to do this 5334 * after setting TARC(0) 5335 */ 5336 tctl = er32(TCTL); 5337 tctl |= E1000_TCTL_EN; 5338 ew32(TCTL, tctl); 5339 5340 /* Perform any post-link-up configuration before 5341 * reporting link up. 5342 */ 5343 if (phy->ops.cfg_on_link_up) 5344 phy->ops.cfg_on_link_up(hw); 5345 5346 netif_wake_queue(netdev); 5347 netif_carrier_on(netdev); 5348 5349 if (!test_bit(__E1000_DOWN, &adapter->state)) 5350 mod_timer(&adapter->phy_info_timer, 5351 round_jiffies(jiffies + 2 * HZ)); 5352 } 5353 } else { 5354 if (netif_carrier_ok(netdev)) { 5355 adapter->link_speed = 0; 5356 adapter->link_duplex = 0; 5357 /* Link status message must follow this format */ 5358 netdev_info(netdev, "NIC Link is Down\n"); 5359 netif_carrier_off(netdev); 5360 netif_stop_queue(netdev); 5361 if (!test_bit(__E1000_DOWN, &adapter->state)) 5362 mod_timer(&adapter->phy_info_timer, 5363 round_jiffies(jiffies + 2 * HZ)); 5364 5365 /* 8000ES2LAN requires a Rx packet buffer work-around 5366 * on link down event; reset the controller to flush 5367 * the Rx packet buffer. 5368 */ 5369 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5370 adapter->flags |= FLAG_RESTART_NOW; 5371 else 5372 pm_schedule_suspend(netdev->dev.parent, 5373 LINK_TIMEOUT); 5374 } 5375 } 5376 5377 link_up: 5378 spin_lock(&adapter->stats64_lock); 5379 e1000e_update_stats(adapter); 5380 5381 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5382 adapter->tpt_old = adapter->stats.tpt; 5383 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5384 adapter->colc_old = adapter->stats.colc; 5385 5386 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5387 adapter->gorc_old = adapter->stats.gorc; 5388 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5389 adapter->gotc_old = adapter->stats.gotc; 5390 spin_unlock(&adapter->stats64_lock); 5391 5392 /* If the link is lost the controller stops DMA, but 5393 * if there is queued Tx work it cannot be done. So 5394 * reset the controller to flush the Tx packet buffers. 5395 */ 5396 if (!netif_carrier_ok(netdev) && 5397 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5398 adapter->flags |= FLAG_RESTART_NOW; 5399 5400 /* If reset is necessary, do it outside of interrupt context. */ 5401 if (adapter->flags & FLAG_RESTART_NOW) { 5402 schedule_work(&adapter->reset_task); 5403 /* return immediately since reset is imminent */ 5404 return; 5405 } 5406 5407 e1000e_update_adaptive(&adapter->hw); 5408 5409 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5410 if (adapter->itr_setting == 4) { 5411 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5412 * Total asymmetrical Tx or Rx gets ITR=8000; 5413 * everyone else is between 2000-8000. 5414 */ 5415 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5416 u32 dif = (adapter->gotc > adapter->gorc ? 5417 adapter->gotc - adapter->gorc : 5418 adapter->gorc - adapter->gotc) / 10000; 5419 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5420 5421 e1000e_write_itr(adapter, itr); 5422 } 5423 5424 /* Cause software interrupt to ensure Rx ring is cleaned */ 5425 if (adapter->msix_entries) 5426 ew32(ICS, adapter->rx_ring->ims_val); 5427 else 5428 ew32(ICS, E1000_ICS_RXDMT0); 5429 5430 /* flush pending descriptors to memory before detecting Tx hang */ 5431 e1000e_flush_descriptors(adapter); 5432 5433 /* Force detection of hung controller every watchdog period */ 5434 adapter->detect_tx_hung = true; 5435 5436 /* With 82571 controllers, LAA may be overwritten due to controller 5437 * reset from the other port. Set the appropriate LAA in RAR[0] 5438 */ 5439 if (e1000e_get_laa_state_82571(hw)) 5440 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5441 5442 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5443 e1000e_check_82574_phy_workaround(adapter); 5444 5445 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5446 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5447 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5448 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5449 er32(RXSTMPH); 5450 adapter->rx_hwtstamp_cleared++; 5451 } else { 5452 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5453 } 5454 } 5455 5456 /* Reset the timer */ 5457 if (!test_bit(__E1000_DOWN, &adapter->state)) 5458 mod_timer(&adapter->watchdog_timer, 5459 round_jiffies(jiffies + 2 * HZ)); 5460 } 5461 5462 #define E1000_TX_FLAGS_CSUM 0x00000001 5463 #define E1000_TX_FLAGS_VLAN 0x00000002 5464 #define E1000_TX_FLAGS_TSO 0x00000004 5465 #define E1000_TX_FLAGS_IPV4 0x00000008 5466 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5467 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5468 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5469 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5470 5471 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5472 __be16 protocol) 5473 { 5474 struct e1000_context_desc *context_desc; 5475 struct e1000_buffer *buffer_info; 5476 unsigned int i; 5477 u32 cmd_length = 0; 5478 u16 ipcse = 0, mss; 5479 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5480 int err; 5481 5482 if (!skb_is_gso(skb)) 5483 return 0; 5484 5485 err = skb_cow_head(skb, 0); 5486 if (err < 0) 5487 return err; 5488 5489 hdr_len = skb_tcp_all_headers(skb); 5490 mss = skb_shinfo(skb)->gso_size; 5491 if (protocol == htons(ETH_P_IP)) { 5492 struct iphdr *iph = ip_hdr(skb); 5493 iph->tot_len = 0; 5494 iph->check = 0; 5495 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5496 0, IPPROTO_TCP, 0); 5497 cmd_length = E1000_TXD_CMD_IP; 5498 ipcse = skb_transport_offset(skb) - 1; 5499 } else if (skb_is_gso_v6(skb)) { 5500 tcp_v6_gso_csum_prep(skb); 5501 ipcse = 0; 5502 } 5503 ipcss = skb_network_offset(skb); 5504 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5505 tucss = skb_transport_offset(skb); 5506 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5507 5508 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5509 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5510 5511 i = tx_ring->next_to_use; 5512 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5513 buffer_info = &tx_ring->buffer_info[i]; 5514 5515 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5516 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5517 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5518 context_desc->upper_setup.tcp_fields.tucss = tucss; 5519 context_desc->upper_setup.tcp_fields.tucso = tucso; 5520 context_desc->upper_setup.tcp_fields.tucse = 0; 5521 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5522 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5523 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5524 5525 buffer_info->time_stamp = jiffies; 5526 buffer_info->next_to_watch = i; 5527 5528 i++; 5529 if (i == tx_ring->count) 5530 i = 0; 5531 tx_ring->next_to_use = i; 5532 5533 return 1; 5534 } 5535 5536 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5537 __be16 protocol) 5538 { 5539 struct e1000_adapter *adapter = tx_ring->adapter; 5540 struct e1000_context_desc *context_desc; 5541 struct e1000_buffer *buffer_info; 5542 unsigned int i; 5543 u8 css; 5544 u32 cmd_len = E1000_TXD_CMD_DEXT; 5545 5546 if (skb->ip_summed != CHECKSUM_PARTIAL) 5547 return false; 5548 5549 switch (protocol) { 5550 case cpu_to_be16(ETH_P_IP): 5551 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5552 cmd_len |= E1000_TXD_CMD_TCP; 5553 break; 5554 case cpu_to_be16(ETH_P_IPV6): 5555 /* XXX not handling all IPV6 headers */ 5556 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5557 cmd_len |= E1000_TXD_CMD_TCP; 5558 break; 5559 default: 5560 if (unlikely(net_ratelimit())) 5561 e_warn("checksum_partial proto=%x!\n", 5562 be16_to_cpu(protocol)); 5563 break; 5564 } 5565 5566 css = skb_checksum_start_offset(skb); 5567 5568 i = tx_ring->next_to_use; 5569 buffer_info = &tx_ring->buffer_info[i]; 5570 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5571 5572 context_desc->lower_setup.ip_config = 0; 5573 context_desc->upper_setup.tcp_fields.tucss = css; 5574 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5575 context_desc->upper_setup.tcp_fields.tucse = 0; 5576 context_desc->tcp_seg_setup.data = 0; 5577 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5578 5579 buffer_info->time_stamp = jiffies; 5580 buffer_info->next_to_watch = i; 5581 5582 i++; 5583 if (i == tx_ring->count) 5584 i = 0; 5585 tx_ring->next_to_use = i; 5586 5587 return true; 5588 } 5589 5590 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5591 unsigned int first, unsigned int max_per_txd, 5592 unsigned int nr_frags) 5593 { 5594 struct e1000_adapter *adapter = tx_ring->adapter; 5595 struct pci_dev *pdev = adapter->pdev; 5596 struct e1000_buffer *buffer_info; 5597 unsigned int len = skb_headlen(skb); 5598 unsigned int offset = 0, size, count = 0, i; 5599 unsigned int f, bytecount, segs; 5600 5601 i = tx_ring->next_to_use; 5602 5603 while (len) { 5604 buffer_info = &tx_ring->buffer_info[i]; 5605 size = min(len, max_per_txd); 5606 5607 buffer_info->length = size; 5608 buffer_info->time_stamp = jiffies; 5609 buffer_info->next_to_watch = i; 5610 buffer_info->dma = dma_map_single(&pdev->dev, 5611 skb->data + offset, 5612 size, DMA_TO_DEVICE); 5613 buffer_info->mapped_as_page = false; 5614 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5615 goto dma_error; 5616 5617 len -= size; 5618 offset += size; 5619 count++; 5620 5621 if (len) { 5622 i++; 5623 if (i == tx_ring->count) 5624 i = 0; 5625 } 5626 } 5627 5628 for (f = 0; f < nr_frags; f++) { 5629 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5630 5631 len = skb_frag_size(frag); 5632 offset = 0; 5633 5634 while (len) { 5635 i++; 5636 if (i == tx_ring->count) 5637 i = 0; 5638 5639 buffer_info = &tx_ring->buffer_info[i]; 5640 size = min(len, max_per_txd); 5641 5642 buffer_info->length = size; 5643 buffer_info->time_stamp = jiffies; 5644 buffer_info->next_to_watch = i; 5645 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5646 offset, size, 5647 DMA_TO_DEVICE); 5648 buffer_info->mapped_as_page = true; 5649 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5650 goto dma_error; 5651 5652 len -= size; 5653 offset += size; 5654 count++; 5655 } 5656 } 5657 5658 segs = skb_shinfo(skb)->gso_segs ? : 1; 5659 /* multiply data chunks by size of headers */ 5660 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5661 5662 tx_ring->buffer_info[i].skb = skb; 5663 tx_ring->buffer_info[i].segs = segs; 5664 tx_ring->buffer_info[i].bytecount = bytecount; 5665 tx_ring->buffer_info[first].next_to_watch = i; 5666 5667 return count; 5668 5669 dma_error: 5670 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5671 buffer_info->dma = 0; 5672 5673 while (count--) { 5674 if (i == 0) 5675 i += tx_ring->count; 5676 i--; 5677 buffer_info = &tx_ring->buffer_info[i]; 5678 e1000_put_txbuf(tx_ring, buffer_info, true); 5679 } 5680 5681 return 0; 5682 } 5683 5684 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5685 { 5686 struct e1000_adapter *adapter = tx_ring->adapter; 5687 struct e1000_tx_desc *tx_desc = NULL; 5688 struct e1000_buffer *buffer_info; 5689 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5690 unsigned int i; 5691 5692 if (tx_flags & E1000_TX_FLAGS_TSO) { 5693 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5694 E1000_TXD_CMD_TSE; 5695 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5696 5697 if (tx_flags & E1000_TX_FLAGS_IPV4) 5698 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5699 } 5700 5701 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5702 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5703 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5704 } 5705 5706 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5707 txd_lower |= E1000_TXD_CMD_VLE; 5708 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5709 } 5710 5711 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5712 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5713 5714 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5715 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5716 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5717 } 5718 5719 i = tx_ring->next_to_use; 5720 5721 do { 5722 buffer_info = &tx_ring->buffer_info[i]; 5723 tx_desc = E1000_TX_DESC(*tx_ring, i); 5724 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5725 tx_desc->lower.data = cpu_to_le32(txd_lower | 5726 buffer_info->length); 5727 tx_desc->upper.data = cpu_to_le32(txd_upper); 5728 5729 i++; 5730 if (i == tx_ring->count) 5731 i = 0; 5732 } while (--count > 0); 5733 5734 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5735 5736 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5737 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5738 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5739 5740 /* Force memory writes to complete before letting h/w 5741 * know there are new descriptors to fetch. (Only 5742 * applicable for weak-ordered memory model archs, 5743 * such as IA-64). 5744 */ 5745 wmb(); 5746 5747 tx_ring->next_to_use = i; 5748 } 5749 5750 #define MINIMUM_DHCP_PACKET_SIZE 282 5751 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5752 struct sk_buff *skb) 5753 { 5754 struct e1000_hw *hw = &adapter->hw; 5755 u16 length, offset; 5756 5757 if (skb_vlan_tag_present(skb) && 5758 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5759 (adapter->hw.mng_cookie.status & 5760 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5761 return 0; 5762 5763 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5764 return 0; 5765 5766 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5767 return 0; 5768 5769 { 5770 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5771 struct udphdr *udp; 5772 5773 if (ip->protocol != IPPROTO_UDP) 5774 return 0; 5775 5776 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5777 if (ntohs(udp->dest) != 67) 5778 return 0; 5779 5780 offset = (u8 *)udp + 8 - skb->data; 5781 length = skb->len - offset; 5782 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5783 } 5784 5785 return 0; 5786 } 5787 5788 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5789 { 5790 struct e1000_adapter *adapter = tx_ring->adapter; 5791 5792 netif_stop_queue(adapter->netdev); 5793 /* Herbert's original patch had: 5794 * smp_mb__after_netif_stop_queue(); 5795 * but since that doesn't exist yet, just open code it. 5796 */ 5797 smp_mb(); 5798 5799 /* We need to check again in a case another CPU has just 5800 * made room available. 5801 */ 5802 if (e1000_desc_unused(tx_ring) < size) 5803 return -EBUSY; 5804 5805 /* A reprieve! */ 5806 netif_start_queue(adapter->netdev); 5807 ++adapter->restart_queue; 5808 return 0; 5809 } 5810 5811 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5812 { 5813 BUG_ON(size > tx_ring->count); 5814 5815 if (e1000_desc_unused(tx_ring) >= size) 5816 return 0; 5817 return __e1000_maybe_stop_tx(tx_ring, size); 5818 } 5819 5820 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5821 struct net_device *netdev) 5822 { 5823 struct e1000_adapter *adapter = netdev_priv(netdev); 5824 struct e1000_ring *tx_ring = adapter->tx_ring; 5825 unsigned int first; 5826 unsigned int tx_flags = 0; 5827 unsigned int len = skb_headlen(skb); 5828 unsigned int nr_frags; 5829 unsigned int mss; 5830 int count = 0; 5831 int tso; 5832 unsigned int f; 5833 __be16 protocol = vlan_get_protocol(skb); 5834 5835 if (test_bit(__E1000_DOWN, &adapter->state)) { 5836 dev_kfree_skb_any(skb); 5837 return NETDEV_TX_OK; 5838 } 5839 5840 if (skb->len <= 0) { 5841 dev_kfree_skb_any(skb); 5842 return NETDEV_TX_OK; 5843 } 5844 5845 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5846 * pad skb in order to meet this minimum size requirement 5847 */ 5848 if (skb_put_padto(skb, 17)) 5849 return NETDEV_TX_OK; 5850 5851 mss = skb_shinfo(skb)->gso_size; 5852 if (mss) { 5853 u8 hdr_len; 5854 5855 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5856 * points to just header, pull a few bytes of payload from 5857 * frags into skb->data 5858 */ 5859 hdr_len = skb_tcp_all_headers(skb); 5860 /* we do this workaround for ES2LAN, but it is un-necessary, 5861 * avoiding it could save a lot of cycles 5862 */ 5863 if (skb->data_len && (hdr_len == len)) { 5864 unsigned int pull_size; 5865 5866 pull_size = min_t(unsigned int, 4, skb->data_len); 5867 if (!__pskb_pull_tail(skb, pull_size)) { 5868 e_err("__pskb_pull_tail failed.\n"); 5869 dev_kfree_skb_any(skb); 5870 return NETDEV_TX_OK; 5871 } 5872 len = skb_headlen(skb); 5873 } 5874 } 5875 5876 /* reserve a descriptor for the offload context */ 5877 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5878 count++; 5879 count++; 5880 5881 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5882 5883 nr_frags = skb_shinfo(skb)->nr_frags; 5884 for (f = 0; f < nr_frags; f++) 5885 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5886 adapter->tx_fifo_limit); 5887 5888 if (adapter->hw.mac.tx_pkt_filtering) 5889 e1000_transfer_dhcp_info(adapter, skb); 5890 5891 /* need: count + 2 desc gap to keep tail from touching 5892 * head, otherwise try next time 5893 */ 5894 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5895 return NETDEV_TX_BUSY; 5896 5897 if (skb_vlan_tag_present(skb)) { 5898 tx_flags |= E1000_TX_FLAGS_VLAN; 5899 tx_flags |= (skb_vlan_tag_get(skb) << 5900 E1000_TX_FLAGS_VLAN_SHIFT); 5901 } 5902 5903 first = tx_ring->next_to_use; 5904 5905 tso = e1000_tso(tx_ring, skb, protocol); 5906 if (tso < 0) { 5907 dev_kfree_skb_any(skb); 5908 return NETDEV_TX_OK; 5909 } 5910 5911 if (tso) 5912 tx_flags |= E1000_TX_FLAGS_TSO; 5913 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5914 tx_flags |= E1000_TX_FLAGS_CSUM; 5915 5916 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5917 * 82571 hardware supports TSO capabilities for IPv6 as well... 5918 * no longer assume, we must. 5919 */ 5920 if (protocol == htons(ETH_P_IP)) 5921 tx_flags |= E1000_TX_FLAGS_IPV4; 5922 5923 if (unlikely(skb->no_fcs)) 5924 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5925 5926 /* if count is 0 then mapping error has occurred */ 5927 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5928 nr_frags); 5929 if (count) { 5930 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5931 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5932 if (!adapter->tx_hwtstamp_skb) { 5933 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5934 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5935 adapter->tx_hwtstamp_skb = skb_get(skb); 5936 adapter->tx_hwtstamp_start = jiffies; 5937 schedule_work(&adapter->tx_hwtstamp_work); 5938 } else { 5939 adapter->tx_hwtstamp_skipped++; 5940 } 5941 } 5942 5943 skb_tx_timestamp(skb); 5944 5945 netdev_sent_queue(netdev, skb->len); 5946 e1000_tx_queue(tx_ring, tx_flags, count); 5947 /* Make sure there is space in the ring for the next send. */ 5948 e1000_maybe_stop_tx(tx_ring, 5949 ((MAX_SKB_FRAGS + 1) * 5950 DIV_ROUND_UP(PAGE_SIZE, 5951 adapter->tx_fifo_limit) + 4)); 5952 5953 if (!netdev_xmit_more() || 5954 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5955 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5956 e1000e_update_tdt_wa(tx_ring, 5957 tx_ring->next_to_use); 5958 else 5959 writel(tx_ring->next_to_use, tx_ring->tail); 5960 } 5961 } else { 5962 dev_kfree_skb_any(skb); 5963 tx_ring->buffer_info[first].time_stamp = 0; 5964 tx_ring->next_to_use = first; 5965 } 5966 5967 return NETDEV_TX_OK; 5968 } 5969 5970 /** 5971 * e1000_tx_timeout - Respond to a Tx Hang 5972 * @netdev: network interface device structure 5973 * @txqueue: index of the hung queue (unused) 5974 **/ 5975 static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 5976 { 5977 struct e1000_adapter *adapter = netdev_priv(netdev); 5978 5979 /* Do the reset outside of interrupt context */ 5980 adapter->tx_timeout_count++; 5981 schedule_work(&adapter->reset_task); 5982 } 5983 5984 static void e1000_reset_task(struct work_struct *work) 5985 { 5986 struct e1000_adapter *adapter; 5987 adapter = container_of(work, struct e1000_adapter, reset_task); 5988 5989 rtnl_lock(); 5990 /* don't run the task if already down */ 5991 if (test_bit(__E1000_DOWN, &adapter->state)) { 5992 rtnl_unlock(); 5993 return; 5994 } 5995 5996 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5997 e1000e_dump(adapter); 5998 e_err("Reset adapter unexpectedly\n"); 5999 } 6000 e1000e_reinit_locked(adapter); 6001 rtnl_unlock(); 6002 } 6003 6004 /** 6005 * e1000e_get_stats64 - Get System Network Statistics 6006 * @netdev: network interface device structure 6007 * @stats: rtnl_link_stats64 pointer 6008 * 6009 * Returns the address of the device statistics structure. 6010 **/ 6011 void e1000e_get_stats64(struct net_device *netdev, 6012 struct rtnl_link_stats64 *stats) 6013 { 6014 struct e1000_adapter *adapter = netdev_priv(netdev); 6015 6016 spin_lock(&adapter->stats64_lock); 6017 e1000e_update_stats(adapter); 6018 /* Fill out the OS statistics structure */ 6019 stats->rx_bytes = adapter->stats.gorc; 6020 stats->rx_packets = adapter->stats.gprc; 6021 stats->tx_bytes = adapter->stats.gotc; 6022 stats->tx_packets = adapter->stats.gptc; 6023 stats->multicast = adapter->stats.mprc; 6024 stats->collisions = adapter->stats.colc; 6025 6026 /* Rx Errors */ 6027 6028 /* RLEC on some newer hardware can be incorrect so build 6029 * our own version based on RUC and ROC 6030 */ 6031 stats->rx_errors = adapter->stats.rxerrc + 6032 adapter->stats.crcerrs + adapter->stats.algnerrc + 6033 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 6034 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 6035 stats->rx_crc_errors = adapter->stats.crcerrs; 6036 stats->rx_frame_errors = adapter->stats.algnerrc; 6037 stats->rx_missed_errors = adapter->stats.mpc; 6038 6039 /* Tx Errors */ 6040 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6041 stats->tx_aborted_errors = adapter->stats.ecol; 6042 stats->tx_window_errors = adapter->stats.latecol; 6043 stats->tx_carrier_errors = adapter->stats.tncrs; 6044 6045 /* Tx Dropped needs to be maintained elsewhere */ 6046 6047 spin_unlock(&adapter->stats64_lock); 6048 } 6049 6050 /** 6051 * e1000_change_mtu - Change the Maximum Transfer Unit 6052 * @netdev: network interface device structure 6053 * @new_mtu: new value for maximum frame size 6054 * 6055 * Returns 0 on success, negative on failure 6056 **/ 6057 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6058 { 6059 struct e1000_adapter *adapter = netdev_priv(netdev); 6060 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6061 6062 /* Jumbo frame support */ 6063 if ((new_mtu > ETH_DATA_LEN) && 6064 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6065 e_err("Jumbo Frames not supported.\n"); 6066 return -EINVAL; 6067 } 6068 6069 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6070 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6071 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6072 (new_mtu > ETH_DATA_LEN)) { 6073 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6074 return -EINVAL; 6075 } 6076 6077 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6078 usleep_range(1000, 1100); 6079 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6080 adapter->max_frame_size = max_frame; 6081 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6082 netdev->mtu, new_mtu); 6083 WRITE_ONCE(netdev->mtu, new_mtu); 6084 6085 pm_runtime_get_sync(netdev->dev.parent); 6086 6087 if (netif_running(netdev)) 6088 e1000e_down(adapter, true); 6089 6090 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6091 * means we reserve 2 more, this pushes us to allocate from the next 6092 * larger slab size. 6093 * i.e. RXBUFFER_2048 --> size-4096 slab 6094 * However with the new *_jumbo_rx* routines, jumbo receives will use 6095 * fragmented skbs 6096 */ 6097 6098 if (max_frame <= 2048) 6099 adapter->rx_buffer_len = 2048; 6100 else 6101 adapter->rx_buffer_len = 4096; 6102 6103 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6104 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6105 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6106 6107 if (netif_running(netdev)) 6108 e1000e_up(adapter); 6109 else 6110 e1000e_reset(adapter); 6111 6112 pm_runtime_put_sync(netdev->dev.parent); 6113 6114 clear_bit(__E1000_RESETTING, &adapter->state); 6115 6116 return 0; 6117 } 6118 6119 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6120 { 6121 struct e1000_adapter *adapter = netdev_priv(netdev); 6122 struct mii_ioctl_data *data = if_mii(ifr); 6123 6124 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6125 return -EOPNOTSUPP; 6126 6127 switch (cmd) { 6128 case SIOCGMIIPHY: 6129 data->phy_id = adapter->hw.phy.addr; 6130 break; 6131 case SIOCGMIIREG: 6132 e1000_phy_read_status(adapter); 6133 6134 switch (data->reg_num & 0x1F) { 6135 case MII_BMCR: 6136 data->val_out = adapter->phy_regs.bmcr; 6137 break; 6138 case MII_BMSR: 6139 data->val_out = adapter->phy_regs.bmsr; 6140 break; 6141 case MII_PHYSID1: 6142 data->val_out = (adapter->hw.phy.id >> 16); 6143 break; 6144 case MII_PHYSID2: 6145 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6146 break; 6147 case MII_ADVERTISE: 6148 data->val_out = adapter->phy_regs.advertise; 6149 break; 6150 case MII_LPA: 6151 data->val_out = adapter->phy_regs.lpa; 6152 break; 6153 case MII_EXPANSION: 6154 data->val_out = adapter->phy_regs.expansion; 6155 break; 6156 case MII_CTRL1000: 6157 data->val_out = adapter->phy_regs.ctrl1000; 6158 break; 6159 case MII_STAT1000: 6160 data->val_out = adapter->phy_regs.stat1000; 6161 break; 6162 case MII_ESTATUS: 6163 data->val_out = adapter->phy_regs.estatus; 6164 break; 6165 default: 6166 return -EIO; 6167 } 6168 break; 6169 case SIOCSMIIREG: 6170 default: 6171 return -EOPNOTSUPP; 6172 } 6173 return 0; 6174 } 6175 6176 /** 6177 * e1000e_hwtstamp_set - control hardware time stamping 6178 * @netdev: network interface device structure 6179 * @config: timestamp configuration 6180 * @extack: netlink extended ACK report 6181 * 6182 * Outgoing time stamping can be enabled and disabled. Play nice and 6183 * disable it when requested, although it shouldn't cause any overhead 6184 * when no packet needs it. At most one packet in the queue may be 6185 * marked for time stamping, otherwise it would be impossible to tell 6186 * for sure to which packet the hardware time stamp belongs. 6187 * 6188 * Incoming time stamping has to be configured via the hardware filters. 6189 * Not all combinations are supported, in particular event type has to be 6190 * specified. Matching the kind of event packet is not supported, with the 6191 * exception of "all V2 events regardless of level 2 or 4". 6192 **/ 6193 static int e1000e_hwtstamp_set(struct net_device *netdev, 6194 struct kernel_hwtstamp_config *config, 6195 struct netlink_ext_ack *extack) 6196 { 6197 struct e1000_adapter *adapter = netdev_priv(netdev); 6198 int ret_val; 6199 6200 ret_val = e1000e_config_hwtstamp(adapter, config, extack); 6201 if (ret_val) 6202 return ret_val; 6203 6204 switch (config->rx_filter) { 6205 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6206 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6207 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6208 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6209 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6210 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6211 /* With V2 type filters which specify a Sync or Delay Request, 6212 * Path Delay Request/Response messages are also time stamped 6213 * by hardware so notify the caller the requested packets plus 6214 * some others are time stamped. 6215 */ 6216 config->rx_filter = HWTSTAMP_FILTER_SOME; 6217 break; 6218 default: 6219 break; 6220 } 6221 6222 return 0; 6223 } 6224 6225 static int e1000e_hwtstamp_get(struct net_device *netdev, 6226 struct kernel_hwtstamp_config *kernel_config) 6227 { 6228 struct e1000_adapter *adapter = netdev_priv(netdev); 6229 6230 *kernel_config = adapter->hwtstamp_config; 6231 6232 return 0; 6233 } 6234 6235 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6236 { 6237 struct e1000_hw *hw = &adapter->hw; 6238 u32 i, mac_reg, wuc; 6239 u16 phy_reg, wuc_enable; 6240 int retval; 6241 6242 /* copy MAC RARs to PHY RARs */ 6243 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6244 6245 retval = hw->phy.ops.acquire(hw); 6246 if (retval) { 6247 e_err("Could not acquire PHY\n"); 6248 return retval; 6249 } 6250 6251 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6252 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6253 if (retval) 6254 goto release; 6255 6256 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6257 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6258 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6259 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6260 (u16)(mac_reg & 0xFFFF)); 6261 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6262 (u16)((mac_reg >> 16) & 0xFFFF)); 6263 } 6264 6265 /* configure PHY Rx Control register */ 6266 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6267 mac_reg = er32(RCTL); 6268 if (mac_reg & E1000_RCTL_UPE) 6269 phy_reg |= BM_RCTL_UPE; 6270 if (mac_reg & E1000_RCTL_MPE) 6271 phy_reg |= BM_RCTL_MPE; 6272 phy_reg &= ~(BM_RCTL_MO_MASK); 6273 if (mac_reg & E1000_RCTL_MO_3) 6274 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg) 6275 << BM_RCTL_MO_SHIFT); 6276 if (mac_reg & E1000_RCTL_BAM) 6277 phy_reg |= BM_RCTL_BAM; 6278 if (mac_reg & E1000_RCTL_PMCF) 6279 phy_reg |= BM_RCTL_PMCF; 6280 mac_reg = er32(CTRL); 6281 if (mac_reg & E1000_CTRL_RFCE) 6282 phy_reg |= BM_RCTL_RFCE; 6283 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6284 6285 wuc = E1000_WUC_PME_EN; 6286 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6287 wuc |= E1000_WUC_APME; 6288 6289 /* enable PHY wakeup in MAC register */ 6290 ew32(WUFC, wufc); 6291 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6292 E1000_WUC_PME_STATUS | wuc)); 6293 6294 /* configure and enable PHY wakeup in PHY registers */ 6295 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6296 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6297 6298 /* activate PHY wakeup */ 6299 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6300 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6301 if (retval) 6302 e_err("Could not set PHY Host Wakeup bit\n"); 6303 release: 6304 hw->phy.ops.release(hw); 6305 6306 return retval; 6307 } 6308 6309 static void e1000e_flush_lpic(struct pci_dev *pdev) 6310 { 6311 struct net_device *netdev = pci_get_drvdata(pdev); 6312 struct e1000_adapter *adapter = netdev_priv(netdev); 6313 struct e1000_hw *hw = &adapter->hw; 6314 u32 ret_val; 6315 6316 pm_runtime_get_sync(netdev->dev.parent); 6317 6318 ret_val = hw->phy.ops.acquire(hw); 6319 if (ret_val) 6320 goto fl_out; 6321 6322 pr_info("EEE TX LPI TIMER: %08X\n", 6323 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6324 6325 hw->phy.ops.release(hw); 6326 6327 fl_out: 6328 pm_runtime_put_sync(netdev->dev.parent); 6329 } 6330 6331 /* S0ix implementation */ 6332 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6333 { 6334 struct e1000_hw *hw = &adapter->hw; 6335 u32 mac_data; 6336 u16 phy_data; 6337 6338 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6339 hw->mac.type >= e1000_pch_adp) { 6340 /* Request ME configure the device for S0ix */ 6341 mac_data = er32(H2ME); 6342 mac_data |= E1000_H2ME_START_DPG; 6343 mac_data &= ~E1000_H2ME_EXIT_DPG; 6344 trace_e1000e_trace_mac_register(mac_data); 6345 ew32(H2ME, mac_data); 6346 } else { 6347 /* Request driver configure the device to S0ix */ 6348 /* Disable the periodic inband message, 6349 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6350 */ 6351 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6352 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6353 phy_data |= BIT(10); 6354 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6355 6356 /* Make sure we don't exit K1 every time a new packet arrives 6357 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6358 */ 6359 e1e_rphy(hw, I217_CGFREG, &phy_data); 6360 phy_data |= BIT(5); 6361 e1e_wphy(hw, I217_CGFREG, phy_data); 6362 6363 /* Change the MAC/PHY interface to SMBus 6364 * Force the SMBus in PHY page769_23[0] = 1 6365 * Force the SMBus in MAC CTRL_EXT[11] = 1 6366 */ 6367 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6368 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6369 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6370 mac_data = er32(CTRL_EXT); 6371 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6372 ew32(CTRL_EXT, mac_data); 6373 6374 /* DFT control: PHY bit: page769_20[0] = 1 6375 * page769_20[7] - PHY PLL stop 6376 * page769_20[8] - PHY go to the electrical idle 6377 * page769_20[9] - PHY serdes disable 6378 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6379 */ 6380 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6381 phy_data |= BIT(0); 6382 phy_data |= BIT(7); 6383 phy_data |= BIT(8); 6384 phy_data |= BIT(9); 6385 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6386 6387 mac_data = er32(EXTCNF_CTRL); 6388 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6389 ew32(EXTCNF_CTRL, mac_data); 6390 6391 /* Disable disconnected cable conditioning for Power Gating */ 6392 mac_data = er32(DPGFR); 6393 mac_data |= BIT(2); 6394 ew32(DPGFR, mac_data); 6395 6396 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6397 mac_data = er32(CTRL_EXT); 6398 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6399 ew32(CTRL_EXT, mac_data); 6400 } 6401 6402 /* Enable the Dynamic Power Gating in the MAC */ 6403 mac_data = er32(FEXTNVM7); 6404 mac_data |= BIT(22); 6405 ew32(FEXTNVM7, mac_data); 6406 6407 /* Don't wake from dynamic Power Gating with clock request */ 6408 mac_data = er32(FEXTNVM12); 6409 mac_data |= BIT(12); 6410 ew32(FEXTNVM12, mac_data); 6411 6412 /* Ungate PGCB clock */ 6413 mac_data = er32(FEXTNVM9); 6414 mac_data &= ~BIT(28); 6415 ew32(FEXTNVM9, mac_data); 6416 6417 /* Enable K1 off to enable mPHY Power Gating */ 6418 mac_data = er32(FEXTNVM6); 6419 mac_data |= BIT(31); 6420 ew32(FEXTNVM6, mac_data); 6421 6422 /* Enable mPHY power gating for any link and speed */ 6423 mac_data = er32(FEXTNVM8); 6424 mac_data |= BIT(9); 6425 ew32(FEXTNVM8, mac_data); 6426 6427 /* No MAC DPG gating SLP_S0 in modern standby 6428 * Switch the logic of the lanphypc to use PMC counter 6429 */ 6430 mac_data = er32(FEXTNVM5); 6431 mac_data |= BIT(7); 6432 ew32(FEXTNVM5, mac_data); 6433 6434 /* Disable the time synchronization clock */ 6435 mac_data = er32(FEXTNVM7); 6436 mac_data |= BIT(31); 6437 mac_data &= ~BIT(0); 6438 ew32(FEXTNVM7, mac_data); 6439 6440 /* Dynamic Power Gating Enable */ 6441 mac_data = er32(CTRL_EXT); 6442 mac_data |= BIT(3); 6443 ew32(CTRL_EXT, mac_data); 6444 6445 /* Check MAC Tx/Rx packet buffer pointers. 6446 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6447 * pending traffic indication that would prevent power gating. 6448 */ 6449 mac_data = er32(TDFH); 6450 if (mac_data) 6451 ew32(TDFH, 0); 6452 mac_data = er32(TDFT); 6453 if (mac_data) 6454 ew32(TDFT, 0); 6455 mac_data = er32(TDFHS); 6456 if (mac_data) 6457 ew32(TDFHS, 0); 6458 mac_data = er32(TDFTS); 6459 if (mac_data) 6460 ew32(TDFTS, 0); 6461 mac_data = er32(TDFPC); 6462 if (mac_data) 6463 ew32(TDFPC, 0); 6464 mac_data = er32(RDFH); 6465 if (mac_data) 6466 ew32(RDFH, 0); 6467 mac_data = er32(RDFT); 6468 if (mac_data) 6469 ew32(RDFT, 0); 6470 mac_data = er32(RDFHS); 6471 if (mac_data) 6472 ew32(RDFHS, 0); 6473 mac_data = er32(RDFTS); 6474 if (mac_data) 6475 ew32(RDFTS, 0); 6476 mac_data = er32(RDFPC); 6477 if (mac_data) 6478 ew32(RDFPC, 0); 6479 } 6480 6481 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6482 { 6483 struct e1000_hw *hw = &adapter->hw; 6484 bool firmware_bug = false; 6485 u32 mac_data; 6486 u16 phy_data; 6487 u32 i = 0; 6488 6489 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6490 hw->mac.type >= e1000_pch_adp) { 6491 /* Keep the GPT clock enabled for CSME */ 6492 mac_data = er32(FEXTNVM); 6493 mac_data |= BIT(3); 6494 ew32(FEXTNVM, mac_data); 6495 /* Request ME unconfigure the device from S0ix */ 6496 mac_data = er32(H2ME); 6497 mac_data &= ~E1000_H2ME_START_DPG; 6498 mac_data |= E1000_H2ME_EXIT_DPG; 6499 trace_e1000e_trace_mac_register(mac_data); 6500 ew32(H2ME, mac_data); 6501 6502 /* Poll up to 2.5 seconds for ME to unconfigure DPG. 6503 * If this takes more than 1 second, show a warning indicating a 6504 * firmware bug 6505 */ 6506 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) { 6507 if (i > 100 && !firmware_bug) 6508 firmware_bug = true; 6509 6510 if (i++ == 250) { 6511 e_dbg("Timeout (firmware bug): %d msec\n", 6512 i * 10); 6513 break; 6514 } 6515 6516 usleep_range(10000, 11000); 6517 } 6518 if (firmware_bug) 6519 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n", 6520 i * 10); 6521 else 6522 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10); 6523 } else { 6524 /* Request driver unconfigure the device from S0ix */ 6525 6526 /* Cancel disable disconnected cable conditioning 6527 * for Power Gating 6528 */ 6529 mac_data = er32(DPGFR); 6530 mac_data &= ~BIT(2); 6531 ew32(DPGFR, mac_data); 6532 6533 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6534 mac_data = er32(CTRL_EXT); 6535 mac_data &= 0xFFF7FFFF; 6536 ew32(CTRL_EXT, mac_data); 6537 6538 /* Enable the periodic inband message, 6539 * Request PCIe clock in K1 page770_17[10:9] =01b 6540 */ 6541 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6542 phy_data &= 0xFBFF; 6543 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6544 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6545 6546 /* Return back configuration 6547 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6548 */ 6549 e1e_rphy(hw, I217_CGFREG, &phy_data); 6550 phy_data &= 0xFFDF; 6551 e1e_wphy(hw, I217_CGFREG, phy_data); 6552 6553 /* Change the MAC/PHY interface to Kumeran 6554 * Unforce the SMBus in PHY page769_23[0] = 0 6555 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6556 */ 6557 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6558 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6559 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6560 mac_data = er32(CTRL_EXT); 6561 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6562 ew32(CTRL_EXT, mac_data); 6563 } 6564 6565 /* Disable Dynamic Power Gating */ 6566 mac_data = er32(CTRL_EXT); 6567 mac_data &= 0xFFFFFFF7; 6568 ew32(CTRL_EXT, mac_data); 6569 6570 /* Enable the time synchronization clock */ 6571 mac_data = er32(FEXTNVM7); 6572 mac_data &= ~BIT(31); 6573 mac_data |= BIT(0); 6574 ew32(FEXTNVM7, mac_data); 6575 6576 /* Disable the Dynamic Power Gating in the MAC */ 6577 mac_data = er32(FEXTNVM7); 6578 mac_data &= 0xFFBFFFFF; 6579 ew32(FEXTNVM7, mac_data); 6580 6581 /* Disable mPHY power gating for any link and speed */ 6582 mac_data = er32(FEXTNVM8); 6583 mac_data &= ~BIT(9); 6584 ew32(FEXTNVM8, mac_data); 6585 6586 /* Disable K1 off */ 6587 mac_data = er32(FEXTNVM6); 6588 mac_data &= ~BIT(31); 6589 ew32(FEXTNVM6, mac_data); 6590 6591 /* Disable Ungate PGCB clock */ 6592 mac_data = er32(FEXTNVM9); 6593 mac_data |= BIT(28); 6594 ew32(FEXTNVM9, mac_data); 6595 6596 /* Cancel not waking from dynamic 6597 * Power Gating with clock request 6598 */ 6599 mac_data = er32(FEXTNVM12); 6600 mac_data &= ~BIT(12); 6601 ew32(FEXTNVM12, mac_data); 6602 6603 /* Revert the lanphypc logic to use the internal Gbe counter 6604 * and not the PMC counter 6605 */ 6606 mac_data = er32(FEXTNVM5); 6607 mac_data &= 0xFFFFFF7F; 6608 ew32(FEXTNVM5, mac_data); 6609 } 6610 6611 static int e1000e_pm_freeze(struct device *dev) 6612 { 6613 struct net_device *netdev = dev_get_drvdata(dev); 6614 struct e1000_adapter *adapter = netdev_priv(netdev); 6615 bool present; 6616 6617 rtnl_lock(); 6618 6619 present = netif_device_present(netdev); 6620 netif_device_detach(netdev); 6621 6622 if (present && netif_running(netdev)) { 6623 int count = E1000_CHECK_RESET_COUNT; 6624 6625 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6626 usleep_range(10000, 11000); 6627 6628 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6629 6630 /* Quiesce the device without resetting the hardware */ 6631 e1000e_down(adapter, false); 6632 e1000_free_irq(adapter); 6633 } 6634 rtnl_unlock(); 6635 6636 e1000e_reset_interrupt_capability(adapter); 6637 6638 /* Allow time for pending master requests to run */ 6639 e1000e_disable_pcie_master(&adapter->hw); 6640 6641 return 0; 6642 } 6643 6644 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6645 { 6646 struct net_device *netdev = pci_get_drvdata(pdev); 6647 struct e1000_adapter *adapter = netdev_priv(netdev); 6648 struct e1000_hw *hw = &adapter->hw; 6649 u32 ctrl, ctrl_ext, rctl, status, wufc; 6650 int retval = 0; 6651 6652 /* Runtime suspend should only enable wakeup for link changes */ 6653 if (runtime) 6654 wufc = E1000_WUFC_LNKC; 6655 else if (device_may_wakeup(&pdev->dev)) 6656 wufc = adapter->wol; 6657 else 6658 wufc = 0; 6659 6660 status = er32(STATUS); 6661 if (status & E1000_STATUS_LU) 6662 wufc &= ~E1000_WUFC_LNKC; 6663 6664 if (wufc) { 6665 e1000_setup_rctl(adapter); 6666 e1000e_set_rx_mode(netdev); 6667 6668 /* turn on all-multi mode if wake on multicast is enabled */ 6669 if (wufc & E1000_WUFC_MC) { 6670 rctl = er32(RCTL); 6671 rctl |= E1000_RCTL_MPE; 6672 ew32(RCTL, rctl); 6673 } 6674 6675 ctrl = er32(CTRL); 6676 ctrl |= E1000_CTRL_ADVD3WUC; 6677 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6678 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6679 ew32(CTRL, ctrl); 6680 6681 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6682 adapter->hw.phy.media_type == 6683 e1000_media_type_internal_serdes) { 6684 /* keep the laser running in D3 */ 6685 ctrl_ext = er32(CTRL_EXT); 6686 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6687 ew32(CTRL_EXT, ctrl_ext); 6688 } 6689 6690 if (!runtime) 6691 e1000e_power_up_phy(adapter); 6692 6693 if (adapter->flags & FLAG_IS_ICH) 6694 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6695 6696 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6697 /* enable wakeup by the PHY */ 6698 retval = e1000_init_phy_wakeup(adapter, wufc); 6699 if (retval) { 6700 e_err("Failed to enable wakeup\n"); 6701 goto skip_phy_configurations; 6702 } 6703 } else { 6704 /* enable wakeup by the MAC */ 6705 ew32(WUFC, wufc); 6706 ew32(WUC, E1000_WUC_PME_EN); 6707 } 6708 } else { 6709 ew32(WUC, 0); 6710 ew32(WUFC, 0); 6711 6712 e1000_power_down_phy(adapter); 6713 } 6714 6715 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6716 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6717 } else if (hw->mac.type >= e1000_pch_lpt) { 6718 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) { 6719 /* ULP does not support wake from unicast, multicast 6720 * or broadcast. 6721 */ 6722 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6723 if (retval) { 6724 e_err("Failed to enable ULP\n"); 6725 goto skip_phy_configurations; 6726 } 6727 } 6728 } 6729 6730 /* Ensure that the appropriate bits are set in LPI_CTRL 6731 * for EEE in Sx 6732 */ 6733 if ((hw->phy.type >= e1000_phy_i217) && 6734 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6735 u16 lpi_ctrl = 0; 6736 6737 retval = hw->phy.ops.acquire(hw); 6738 if (!retval) { 6739 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6740 &lpi_ctrl); 6741 if (!retval) { 6742 if (adapter->eee_advert & 6743 hw->dev_spec.ich8lan.eee_lp_ability & 6744 I82579_EEE_100_SUPPORTED) 6745 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6746 if (adapter->eee_advert & 6747 hw->dev_spec.ich8lan.eee_lp_ability & 6748 I82579_EEE_1000_SUPPORTED) 6749 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6750 6751 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6752 lpi_ctrl); 6753 } 6754 } 6755 hw->phy.ops.release(hw); 6756 } 6757 6758 skip_phy_configurations: 6759 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6760 * would have already happened in close and is redundant. 6761 */ 6762 e1000e_release_hw_control(adapter); 6763 6764 pci_clear_master(pdev); 6765 6766 /* The pci-e switch on some quad port adapters will report a 6767 * correctable error when the MAC transitions from D0 to D3. To 6768 * prevent this we need to mask off the correctable errors on the 6769 * downstream port of the pci-e switch. 6770 * 6771 * We don't have the associated upstream bridge while assigning 6772 * the PCI device into guest. For example, the KVM on power is 6773 * one of the cases. 6774 */ 6775 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6776 struct pci_dev *us_dev = pdev->bus->self; 6777 u16 devctl; 6778 6779 if (!us_dev) 6780 return 0; 6781 6782 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6783 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6784 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6785 6786 pci_save_state(pdev); 6787 pci_prepare_to_sleep(pdev); 6788 6789 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6790 } 6791 6792 return 0; 6793 } 6794 6795 /** 6796 * __e1000e_disable_aspm - Disable ASPM states 6797 * @pdev: pointer to PCI device struct 6798 * @state: bit-mask of ASPM states to disable 6799 * @locked: indication if this context holds pci_bus_sem locked. 6800 * 6801 * Some devices *must* have certain ASPM states disabled per hardware errata. 6802 **/ 6803 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6804 { 6805 struct pci_dev *parent = pdev->bus->self; 6806 u16 aspm_dis_mask = 0; 6807 u16 pdev_aspmc, parent_aspmc; 6808 6809 switch (state) { 6810 case PCIE_LINK_STATE_L0S: 6811 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6812 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6813 fallthrough; /* can't have L1 without L0s */ 6814 case PCIE_LINK_STATE_L1: 6815 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6816 break; 6817 default: 6818 return; 6819 } 6820 6821 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6822 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6823 6824 if (parent) { 6825 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6826 &parent_aspmc); 6827 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6828 } 6829 6830 /* Nothing to do if the ASPM states to be disabled already are */ 6831 if (!(pdev_aspmc & aspm_dis_mask) && 6832 (!parent || !(parent_aspmc & aspm_dis_mask))) 6833 return; 6834 6835 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6836 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6837 "L0s" : "", 6838 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6839 "L1" : ""); 6840 6841 #ifdef CONFIG_PCIEASPM 6842 if (locked) 6843 pci_disable_link_state_locked(pdev, state); 6844 else 6845 pci_disable_link_state(pdev, state); 6846 6847 /* Double-check ASPM control. If not disabled by the above, the 6848 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6849 * not enabled); override by writing PCI config space directly. 6850 */ 6851 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6852 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6853 6854 if (!(aspm_dis_mask & pdev_aspmc)) 6855 return; 6856 #endif 6857 6858 /* Both device and parent should have the same ASPM setting. 6859 * Disable ASPM in downstream component first and then upstream. 6860 */ 6861 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6862 6863 if (parent) 6864 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6865 aspm_dis_mask); 6866 } 6867 6868 /** 6869 * e1000e_disable_aspm - Disable ASPM states. 6870 * @pdev: pointer to PCI device struct 6871 * @state: bit-mask of ASPM states to disable 6872 * 6873 * This function acquires the pci_bus_sem! 6874 * Some devices *must* have certain ASPM states disabled per hardware errata. 6875 **/ 6876 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6877 { 6878 __e1000e_disable_aspm(pdev, state, 0); 6879 } 6880 6881 /** 6882 * e1000e_disable_aspm_locked - Disable ASPM states. 6883 * @pdev: pointer to PCI device struct 6884 * @state: bit-mask of ASPM states to disable 6885 * 6886 * This function must be called with pci_bus_sem acquired! 6887 * Some devices *must* have certain ASPM states disabled per hardware errata. 6888 **/ 6889 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6890 { 6891 __e1000e_disable_aspm(pdev, state, 1); 6892 } 6893 6894 static int e1000e_pm_thaw(struct device *dev) 6895 { 6896 struct net_device *netdev = dev_get_drvdata(dev); 6897 struct e1000_adapter *adapter = netdev_priv(netdev); 6898 int rc = 0; 6899 6900 e1000e_set_interrupt_capability(adapter); 6901 6902 rtnl_lock(); 6903 if (netif_running(netdev)) { 6904 rc = e1000_request_irq(adapter); 6905 if (rc) 6906 goto err_irq; 6907 6908 e1000e_up(adapter); 6909 } 6910 6911 netif_device_attach(netdev); 6912 err_irq: 6913 rtnl_unlock(); 6914 6915 return rc; 6916 } 6917 6918 static int __e1000_resume(struct pci_dev *pdev) 6919 { 6920 struct net_device *netdev = pci_get_drvdata(pdev); 6921 struct e1000_adapter *adapter = netdev_priv(netdev); 6922 struct e1000_hw *hw = &adapter->hw; 6923 u16 aspm_disable_flag = 0; 6924 6925 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6926 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6927 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6928 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6929 if (aspm_disable_flag) 6930 e1000e_disable_aspm(pdev, aspm_disable_flag); 6931 6932 pci_set_master(pdev); 6933 6934 if (hw->mac.type >= e1000_pch2lan) 6935 e1000_resume_workarounds_pchlan(&adapter->hw); 6936 6937 e1000e_power_up_phy(adapter); 6938 6939 /* report the system wakeup cause from S3/S4 */ 6940 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6941 u16 phy_data; 6942 6943 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6944 if (phy_data) { 6945 e_info("PHY Wakeup cause - %s\n", 6946 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6947 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6948 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6949 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6950 phy_data & E1000_WUS_LNKC ? 6951 "Link Status Change" : "other"); 6952 } 6953 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6954 } else { 6955 u32 wus = er32(WUS); 6956 6957 if (wus) { 6958 e_info("MAC Wakeup cause - %s\n", 6959 wus & E1000_WUS_EX ? "Unicast Packet" : 6960 wus & E1000_WUS_MC ? "Multicast Packet" : 6961 wus & E1000_WUS_BC ? "Broadcast Packet" : 6962 wus & E1000_WUS_MAG ? "Magic Packet" : 6963 wus & E1000_WUS_LNKC ? "Link Status Change" : 6964 "other"); 6965 } 6966 ew32(WUS, ~0); 6967 } 6968 6969 e1000e_reset(adapter); 6970 6971 e1000_init_manageability_pt(adapter); 6972 6973 /* If the controller has AMT, do not set DRV_LOAD until the interface 6974 * is up. For all other cases, let the f/w know that the h/w is now 6975 * under the control of the driver. 6976 */ 6977 if (!(adapter->flags & FLAG_HAS_AMT)) 6978 e1000e_get_hw_control(adapter); 6979 6980 return 0; 6981 } 6982 6983 static int e1000e_pm_prepare(struct device *dev) 6984 { 6985 return pm_runtime_suspended(dev) && 6986 pm_suspend_via_firmware(); 6987 } 6988 6989 static int e1000e_pm_suspend(struct device *dev) 6990 { 6991 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6992 struct e1000_adapter *adapter = netdev_priv(netdev); 6993 struct pci_dev *pdev = to_pci_dev(dev); 6994 int rc; 6995 6996 e1000e_flush_lpic(pdev); 6997 6998 e1000e_pm_freeze(dev); 6999 7000 rc = __e1000_shutdown(pdev, false); 7001 if (!rc) { 7002 /* Introduce S0ix implementation */ 7003 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 7004 e1000e_s0ix_entry_flow(adapter); 7005 } 7006 7007 return 0; 7008 } 7009 7010 static int e1000e_pm_resume(struct device *dev) 7011 { 7012 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 7013 struct e1000_adapter *adapter = netdev_priv(netdev); 7014 struct pci_dev *pdev = to_pci_dev(dev); 7015 int rc; 7016 7017 /* Introduce S0ix implementation */ 7018 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 7019 e1000e_s0ix_exit_flow(adapter); 7020 7021 rc = __e1000_resume(pdev); 7022 if (rc) 7023 return rc; 7024 7025 return e1000e_pm_thaw(dev); 7026 } 7027 7028 static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev) 7029 { 7030 struct net_device *netdev = dev_get_drvdata(dev); 7031 struct e1000_adapter *adapter = netdev_priv(netdev); 7032 u16 eee_lp; 7033 7034 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 7035 7036 if (!e1000e_has_link(adapter)) { 7037 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 7038 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 7039 } 7040 7041 return -EBUSY; 7042 } 7043 7044 static int e1000e_pm_runtime_resume(struct device *dev) 7045 { 7046 struct pci_dev *pdev = to_pci_dev(dev); 7047 struct net_device *netdev = pci_get_drvdata(pdev); 7048 struct e1000_adapter *adapter = netdev_priv(netdev); 7049 int rc; 7050 7051 pdev->pme_poll = true; 7052 7053 rc = __e1000_resume(pdev); 7054 if (rc) 7055 return rc; 7056 7057 if (netdev->flags & IFF_UP) 7058 e1000e_up(adapter); 7059 7060 return rc; 7061 } 7062 7063 static int e1000e_pm_runtime_suspend(struct device *dev) 7064 { 7065 struct pci_dev *pdev = to_pci_dev(dev); 7066 struct net_device *netdev = pci_get_drvdata(pdev); 7067 struct e1000_adapter *adapter = netdev_priv(netdev); 7068 7069 if (netdev->flags & IFF_UP) { 7070 int count = E1000_CHECK_RESET_COUNT; 7071 7072 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 7073 usleep_range(10000, 11000); 7074 7075 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 7076 7077 /* Down the device without resetting the hardware */ 7078 e1000e_down(adapter, false); 7079 } 7080 7081 if (__e1000_shutdown(pdev, true)) { 7082 e1000e_pm_runtime_resume(dev); 7083 return -EBUSY; 7084 } 7085 7086 return 0; 7087 } 7088 7089 static void e1000_shutdown(struct pci_dev *pdev) 7090 { 7091 e1000e_flush_lpic(pdev); 7092 7093 e1000e_pm_freeze(&pdev->dev); 7094 7095 __e1000_shutdown(pdev, false); 7096 } 7097 7098 #ifdef CONFIG_NET_POLL_CONTROLLER 7099 7100 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 7101 { 7102 struct net_device *netdev = data; 7103 struct e1000_adapter *adapter = netdev_priv(netdev); 7104 7105 if (adapter->msix_entries) { 7106 int vector, msix_irq; 7107 7108 vector = 0; 7109 msix_irq = adapter->msix_entries[vector].vector; 7110 if (disable_hardirq(msix_irq)) 7111 e1000_intr_msix_rx(msix_irq, netdev); 7112 enable_irq(msix_irq); 7113 7114 vector++; 7115 msix_irq = adapter->msix_entries[vector].vector; 7116 if (disable_hardirq(msix_irq)) 7117 e1000_intr_msix_tx(msix_irq, netdev); 7118 enable_irq(msix_irq); 7119 7120 vector++; 7121 msix_irq = adapter->msix_entries[vector].vector; 7122 if (disable_hardirq(msix_irq)) 7123 e1000_msix_other(msix_irq, netdev); 7124 enable_irq(msix_irq); 7125 } 7126 7127 return IRQ_HANDLED; 7128 } 7129 7130 /** 7131 * e1000_netpoll 7132 * @netdev: network interface device structure 7133 * 7134 * Polling 'interrupt' - used by things like netconsole to send skbs 7135 * without having to re-enable interrupts. It's not called while 7136 * the interrupt routine is executing. 7137 */ 7138 static void e1000_netpoll(struct net_device *netdev) 7139 { 7140 struct e1000_adapter *adapter = netdev_priv(netdev); 7141 7142 switch (adapter->int_mode) { 7143 case E1000E_INT_MODE_MSIX: 7144 e1000_intr_msix(adapter->pdev->irq, netdev); 7145 break; 7146 case E1000E_INT_MODE_MSI: 7147 if (disable_hardirq(adapter->pdev->irq)) 7148 e1000_intr_msi(adapter->pdev->irq, netdev); 7149 enable_irq(adapter->pdev->irq); 7150 break; 7151 default: /* E1000E_INT_MODE_LEGACY */ 7152 if (disable_hardirq(adapter->pdev->irq)) 7153 e1000_intr(adapter->pdev->irq, netdev); 7154 enable_irq(adapter->pdev->irq); 7155 break; 7156 } 7157 } 7158 #endif 7159 7160 /** 7161 * e1000_io_error_detected - called when PCI error is detected 7162 * @pdev: Pointer to PCI device 7163 * @state: The current pci connection state 7164 * 7165 * This function is called after a PCI bus error affecting 7166 * this device has been detected. 7167 */ 7168 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7169 pci_channel_state_t state) 7170 { 7171 e1000e_pm_freeze(&pdev->dev); 7172 7173 if (state == pci_channel_io_perm_failure) 7174 return PCI_ERS_RESULT_DISCONNECT; 7175 7176 pci_disable_device(pdev); 7177 7178 /* Request a slot reset. */ 7179 return PCI_ERS_RESULT_NEED_RESET; 7180 } 7181 7182 /** 7183 * e1000_io_slot_reset - called after the pci bus has been reset. 7184 * @pdev: Pointer to PCI device 7185 * 7186 * Restart the card from scratch, as if from a cold-boot. Implementation 7187 * resembles the first-half of the e1000e_pm_resume routine. 7188 */ 7189 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7190 { 7191 struct net_device *netdev = pci_get_drvdata(pdev); 7192 struct e1000_adapter *adapter = netdev_priv(netdev); 7193 struct e1000_hw *hw = &adapter->hw; 7194 u16 aspm_disable_flag = 0; 7195 int err; 7196 pci_ers_result_t result; 7197 7198 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7199 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7200 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7201 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7202 if (aspm_disable_flag) 7203 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7204 7205 err = pci_enable_device_mem(pdev); 7206 if (err) { 7207 dev_err(&pdev->dev, 7208 "Cannot re-enable PCI device after reset.\n"); 7209 result = PCI_ERS_RESULT_DISCONNECT; 7210 } else { 7211 pci_restore_state(pdev); 7212 pci_set_master(pdev); 7213 7214 pci_enable_wake(pdev, PCI_D3hot, 0); 7215 pci_enable_wake(pdev, PCI_D3cold, 0); 7216 7217 e1000e_reset(adapter); 7218 ew32(WUS, ~0); 7219 result = PCI_ERS_RESULT_RECOVERED; 7220 } 7221 7222 return result; 7223 } 7224 7225 /** 7226 * e1000_io_resume - called when traffic can start flowing again. 7227 * @pdev: Pointer to PCI device 7228 * 7229 * This callback is called when the error recovery driver tells us that 7230 * its OK to resume normal operation. Implementation resembles the 7231 * second-half of the e1000e_pm_resume routine. 7232 */ 7233 static void e1000_io_resume(struct pci_dev *pdev) 7234 { 7235 struct net_device *netdev = pci_get_drvdata(pdev); 7236 struct e1000_adapter *adapter = netdev_priv(netdev); 7237 7238 e1000_init_manageability_pt(adapter); 7239 7240 e1000e_pm_thaw(&pdev->dev); 7241 7242 /* If the controller has AMT, do not set DRV_LOAD until the interface 7243 * is up. For all other cases, let the f/w know that the h/w is now 7244 * under the control of the driver. 7245 */ 7246 if (!(adapter->flags & FLAG_HAS_AMT)) 7247 e1000e_get_hw_control(adapter); 7248 } 7249 7250 static void e1000_print_device_info(struct e1000_adapter *adapter) 7251 { 7252 struct e1000_hw *hw = &adapter->hw; 7253 struct net_device *netdev = adapter->netdev; 7254 u32 ret_val; 7255 u8 pba_str[E1000_PBANUM_LENGTH]; 7256 7257 /* print bus type/speed/width info */ 7258 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7259 /* bus width */ 7260 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7261 "Width x1"), 7262 /* MAC address */ 7263 netdev->dev_addr); 7264 e_info("Intel(R) PRO/%s Network Connection\n", 7265 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7266 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7267 E1000_PBANUM_LENGTH); 7268 if (ret_val) 7269 strscpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7270 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7271 hw->mac.type, hw->phy.type, pba_str); 7272 } 7273 7274 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7275 { 7276 struct e1000_hw *hw = &adapter->hw; 7277 int ret_val; 7278 u16 buf = 0; 7279 7280 if (hw->mac.type != e1000_82573) 7281 return; 7282 7283 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7284 le16_to_cpus(&buf); 7285 if (!ret_val && (!(buf & BIT(0)))) { 7286 /* Deep Smart Power Down (DSPD) */ 7287 dev_warn(&adapter->pdev->dev, 7288 "Warning: detected DSPD enabled in EEPROM\n"); 7289 } 7290 } 7291 7292 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7293 netdev_features_t features) 7294 { 7295 struct e1000_adapter *adapter = netdev_priv(netdev); 7296 struct e1000_hw *hw = &adapter->hw; 7297 7298 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7299 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7300 features &= ~NETIF_F_RXFCS; 7301 7302 /* Since there is no support for separate Rx/Tx vlan accel 7303 * enable/disable make sure Tx flag is always in same state as Rx. 7304 */ 7305 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7306 features |= NETIF_F_HW_VLAN_CTAG_TX; 7307 else 7308 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7309 7310 return features; 7311 } 7312 7313 static int e1000_set_features(struct net_device *netdev, 7314 netdev_features_t features) 7315 { 7316 struct e1000_adapter *adapter = netdev_priv(netdev); 7317 netdev_features_t changed = features ^ netdev->features; 7318 7319 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7320 adapter->flags |= FLAG_TSO_FORCE; 7321 7322 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7323 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7324 NETIF_F_RXALL))) 7325 return 0; 7326 7327 if (changed & NETIF_F_RXFCS) { 7328 if (features & NETIF_F_RXFCS) { 7329 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7330 } else { 7331 /* We need to take it back to defaults, which might mean 7332 * stripping is still disabled at the adapter level. 7333 */ 7334 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7335 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7336 else 7337 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7338 } 7339 } 7340 7341 netdev->features = features; 7342 7343 if (netif_running(netdev)) 7344 e1000e_reinit_locked(adapter); 7345 else 7346 e1000e_reset(adapter); 7347 7348 return 1; 7349 } 7350 7351 static const struct net_device_ops e1000e_netdev_ops = { 7352 .ndo_open = e1000e_open, 7353 .ndo_stop = e1000e_close, 7354 .ndo_start_xmit = e1000_xmit_frame, 7355 .ndo_get_stats64 = e1000e_get_stats64, 7356 .ndo_set_rx_mode = e1000e_set_rx_mode, 7357 .ndo_set_mac_address = e1000_set_mac, 7358 .ndo_change_mtu = e1000_change_mtu, 7359 .ndo_eth_ioctl = e1000_ioctl, 7360 .ndo_tx_timeout = e1000_tx_timeout, 7361 .ndo_validate_addr = eth_validate_addr, 7362 7363 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7364 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7365 #ifdef CONFIG_NET_POLL_CONTROLLER 7366 .ndo_poll_controller = e1000_netpoll, 7367 #endif 7368 .ndo_set_features = e1000_set_features, 7369 .ndo_fix_features = e1000_fix_features, 7370 .ndo_features_check = passthru_features_check, 7371 .ndo_hwtstamp_get = e1000e_hwtstamp_get, 7372 .ndo_hwtstamp_set = e1000e_hwtstamp_set, 7373 }; 7374 7375 /** 7376 * e1000_probe - Device Initialization Routine 7377 * @pdev: PCI device information struct 7378 * @ent: entry in e1000_pci_tbl 7379 * 7380 * Returns 0 on success, negative on failure 7381 * 7382 * e1000_probe initializes an adapter identified by a pci_dev structure. 7383 * The OS initialization, configuring of the adapter private structure, 7384 * and a hardware reset occur. 7385 **/ 7386 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7387 { 7388 struct net_device *netdev; 7389 struct e1000_adapter *adapter; 7390 struct e1000_hw *hw; 7391 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7392 resource_size_t mmio_start, mmio_len; 7393 resource_size_t flash_start, flash_len; 7394 static int cards_found; 7395 u16 aspm_disable_flag = 0; 7396 u16 eeprom_data = 0; 7397 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7398 int bars, i, err; 7399 s32 ret_val = 0; 7400 7401 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7402 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7403 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7404 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7405 if (aspm_disable_flag) 7406 e1000e_disable_aspm(pdev, aspm_disable_flag); 7407 7408 err = pci_enable_device_mem(pdev); 7409 if (err) 7410 return err; 7411 7412 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7413 if (err) { 7414 dev_err(&pdev->dev, 7415 "No usable DMA configuration, aborting\n"); 7416 goto err_dma; 7417 } 7418 7419 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7420 err = pci_request_selected_regions_exclusive(pdev, bars, 7421 e1000e_driver_name); 7422 if (err) 7423 goto err_pci_reg; 7424 7425 pci_set_master(pdev); 7426 /* PCI config space info */ 7427 err = pci_save_state(pdev); 7428 if (err) 7429 goto err_alloc_etherdev; 7430 7431 err = -ENOMEM; 7432 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7433 if (!netdev) 7434 goto err_alloc_etherdev; 7435 7436 SET_NETDEV_DEV(netdev, &pdev->dev); 7437 7438 netdev->irq = pdev->irq; 7439 7440 pci_set_drvdata(pdev, netdev); 7441 adapter = netdev_priv(netdev); 7442 hw = &adapter->hw; 7443 adapter->netdev = netdev; 7444 adapter->pdev = pdev; 7445 adapter->ei = ei; 7446 adapter->pba = ei->pba; 7447 adapter->flags = ei->flags; 7448 adapter->flags2 = ei->flags2; 7449 adapter->hw.adapter = adapter; 7450 adapter->hw.mac.type = ei->mac; 7451 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7452 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7453 7454 mmio_start = pci_resource_start(pdev, 0); 7455 mmio_len = pci_resource_len(pdev, 0); 7456 7457 err = -EIO; 7458 /* Smallest BAR0 that covers every register the driver accesses */ 7459 if (mmio_len < SZ_64K) { 7460 dev_err(&pdev->dev, "MMIO len is too small\n"); 7461 goto err_ioremap; 7462 } 7463 7464 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7465 if (!adapter->hw.hw_addr) 7466 goto err_ioremap; 7467 7468 if ((adapter->flags & FLAG_HAS_FLASH) && 7469 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7470 (hw->mac.type < e1000_pch_spt)) { 7471 flash_start = pci_resource_start(pdev, 1); 7472 flash_len = pci_resource_len(pdev, 1); 7473 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7474 if (!adapter->hw.flash_address) 7475 goto err_flashmap; 7476 } 7477 7478 /* Set default EEE advertisement */ 7479 if (adapter->flags2 & FLAG2_HAS_EEE) 7480 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7481 7482 /* construct the net_device struct */ 7483 netdev->netdev_ops = &e1000e_netdev_ops; 7484 e1000e_set_ethtool_ops(netdev); 7485 netdev->watchdog_timeo = 5 * HZ; 7486 netif_napi_add(netdev, &adapter->napi, e1000e_poll); 7487 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7488 7489 netdev->mem_start = mmio_start; 7490 netdev->mem_end = mmio_start + mmio_len; 7491 7492 adapter->bd_number = cards_found++; 7493 7494 e1000e_check_options(adapter); 7495 7496 /* setup adapter struct */ 7497 err = e1000_sw_init(adapter); 7498 if (err) 7499 goto err_sw_init; 7500 7501 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7502 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7503 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7504 7505 err = ei->get_variants(adapter); 7506 if (err) 7507 goto err_hw_init; 7508 7509 if ((adapter->flags & FLAG_IS_ICH) && 7510 (adapter->flags & FLAG_READ_ONLY_NVM) && 7511 (hw->mac.type < e1000_pch_spt)) 7512 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7513 7514 hw->mac.ops.get_bus_info(&adapter->hw); 7515 7516 adapter->hw.phy.autoneg_wait_to_complete = 0; 7517 7518 /* Copper options */ 7519 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7520 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7521 adapter->hw.phy.disable_polarity_correction = 0; 7522 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7523 } 7524 7525 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7526 dev_info(&pdev->dev, 7527 "PHY reset is blocked due to SOL/IDER session.\n"); 7528 7529 /* Set initial default active device features */ 7530 netdev->features = (NETIF_F_SG | 7531 NETIF_F_HW_VLAN_CTAG_RX | 7532 NETIF_F_HW_VLAN_CTAG_TX | 7533 NETIF_F_TSO | 7534 NETIF_F_TSO6 | 7535 NETIF_F_RXHASH | 7536 NETIF_F_RXCSUM | 7537 NETIF_F_HW_CSUM); 7538 7539 /* disable TSO for pcie and 10/100 speeds to avoid 7540 * some hardware issues and for i219 to fix transfer 7541 * speed being capped at 60% 7542 */ 7543 if (!(adapter->flags & FLAG_TSO_FORCE)) { 7544 switch (adapter->link_speed) { 7545 case SPEED_10: 7546 case SPEED_100: 7547 e_info("10/100 speed: disabling TSO\n"); 7548 netdev->features &= ~NETIF_F_TSO; 7549 netdev->features &= ~NETIF_F_TSO6; 7550 break; 7551 case SPEED_1000: 7552 netdev->features |= NETIF_F_TSO; 7553 netdev->features |= NETIF_F_TSO6; 7554 break; 7555 default: 7556 /* oops */ 7557 break; 7558 } 7559 if (hw->mac.type == e1000_pch_spt) { 7560 netdev->features &= ~NETIF_F_TSO; 7561 netdev->features &= ~NETIF_F_TSO6; 7562 } 7563 } 7564 7565 /* Set user-changeable features (subset of all device features) */ 7566 netdev->hw_features = netdev->features; 7567 netdev->hw_features |= NETIF_F_RXFCS; 7568 netdev->priv_flags |= IFF_SUPP_NOFCS; 7569 netdev->hw_features |= NETIF_F_RXALL; 7570 7571 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7572 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7573 7574 netdev->vlan_features |= (NETIF_F_SG | 7575 NETIF_F_TSO | 7576 NETIF_F_TSO6 | 7577 NETIF_F_HW_CSUM); 7578 7579 netdev->priv_flags |= IFF_UNICAST_FLT; 7580 7581 netdev->features |= NETIF_F_HIGHDMA; 7582 netdev->vlan_features |= NETIF_F_HIGHDMA; 7583 7584 /* MTU range: 68 - max_hw_frame_size */ 7585 netdev->min_mtu = ETH_MIN_MTU; 7586 netdev->max_mtu = adapter->max_hw_frame_size - 7587 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7588 7589 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7590 adapter->flags |= FLAG_MNG_PT_ENABLED; 7591 7592 /* before reading the NVM, reset the controller to 7593 * put the device in a known good starting state 7594 */ 7595 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7596 7597 /* systems with ASPM and others may see the checksum fail on the first 7598 * attempt. Let's give it a few tries 7599 */ 7600 for (i = 0;; i++) { 7601 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7602 break; 7603 if (i == 2) { 7604 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7605 err = -EIO; 7606 goto err_eeprom; 7607 } 7608 } 7609 7610 e1000_eeprom_checks(adapter); 7611 7612 /* copy the MAC address */ 7613 if (e1000e_read_mac_addr(&adapter->hw)) 7614 dev_err(&pdev->dev, 7615 "NVM Read Error while reading MAC address\n"); 7616 7617 eth_hw_addr_set(netdev, adapter->hw.mac.addr); 7618 7619 if (!is_valid_ether_addr(netdev->dev_addr)) { 7620 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7621 netdev->dev_addr); 7622 err = -EIO; 7623 goto err_eeprom; 7624 } 7625 7626 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7627 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7628 7629 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7630 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7631 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7632 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7633 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7634 7635 /* Initialize link parameters. User can change them with ethtool */ 7636 adapter->hw.mac.autoneg = 1; 7637 adapter->fc_autoneg = true; 7638 adapter->hw.fc.requested_mode = e1000_fc_default; 7639 adapter->hw.fc.current_mode = e1000_fc_default; 7640 adapter->hw.phy.autoneg_advertised = 0x2f; 7641 7642 /* Initial Wake on LAN setting - If APM wake is enabled in 7643 * the EEPROM, enable the ACPI Magic Packet filter 7644 */ 7645 if (adapter->flags & FLAG_APME_IN_WUC) { 7646 /* APME bit in EEPROM is mapped to WUC.APME */ 7647 eeprom_data = er32(WUC); 7648 eeprom_apme_mask = E1000_WUC_APME; 7649 if ((hw->mac.type > e1000_ich10lan) && 7650 (eeprom_data & E1000_WUC_PHY_WAKE)) 7651 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7652 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7653 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7654 (adapter->hw.bus.func == 1)) 7655 ret_val = e1000_read_nvm(&adapter->hw, 7656 NVM_INIT_CONTROL3_PORT_B, 7657 1, &eeprom_data); 7658 else 7659 ret_val = e1000_read_nvm(&adapter->hw, 7660 NVM_INIT_CONTROL3_PORT_A, 7661 1, &eeprom_data); 7662 } 7663 7664 /* fetch WoL from EEPROM */ 7665 if (ret_val) 7666 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7667 else if (eeprom_data & eeprom_apme_mask) 7668 adapter->eeprom_wol |= E1000_WUFC_MAG; 7669 7670 /* now that we have the eeprom settings, apply the special cases 7671 * where the eeprom may be wrong or the board simply won't support 7672 * wake on lan on a particular port 7673 */ 7674 if (!(adapter->flags & FLAG_HAS_WOL)) 7675 adapter->eeprom_wol = 0; 7676 7677 /* initialize the wol settings based on the eeprom settings */ 7678 adapter->wol = adapter->eeprom_wol; 7679 7680 /* make sure adapter isn't asleep if manageability is enabled */ 7681 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7682 (hw->mac.ops.check_mng_mode(hw))) 7683 device_wakeup_enable(&pdev->dev); 7684 7685 /* save off EEPROM version number */ 7686 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7687 7688 if (ret_val) { 7689 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7690 adapter->eeprom_vers = 0; 7691 } 7692 7693 /* init PTP hardware clock */ 7694 e1000e_ptp_init(adapter); 7695 7696 /* disable K1 by default on known problematic systems */ 7697 if (hw->mac.type >= e1000_pch_mtp && dmi_check_system(disable_k1_list)) 7698 adapter->flags2 |= FLAG2_DISABLE_K1; 7699 7700 /* reset the hardware with the new settings */ 7701 e1000e_reset(adapter); 7702 7703 /* If the controller has AMT, do not set DRV_LOAD until the interface 7704 * is up. For all other cases, let the f/w know that the h/w is now 7705 * under the control of the driver. 7706 */ 7707 if (!(adapter->flags & FLAG_HAS_AMT)) 7708 e1000e_get_hw_control(adapter); 7709 7710 if (hw->mac.type >= e1000_pch_cnp) 7711 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS; 7712 7713 strscpy(netdev->name, "eth%d", sizeof(netdev->name)); 7714 err = register_netdev(netdev); 7715 if (err) 7716 goto err_register; 7717 7718 /* carrier off reporting is important to ethtool even BEFORE open */ 7719 netif_carrier_off(netdev); 7720 7721 e1000_print_device_info(adapter); 7722 7723 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE); 7724 7725 if (pci_dev_run_wake(pdev)) 7726 pm_runtime_put_noidle(&pdev->dev); 7727 7728 return 0; 7729 7730 err_register: 7731 if (!(adapter->flags & FLAG_HAS_AMT)) 7732 e1000e_release_hw_control(adapter); 7733 e1000e_ptp_remove(adapter); 7734 err_eeprom: 7735 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7736 e1000_phy_hw_reset(&adapter->hw); 7737 err_hw_init: 7738 kfree(adapter->tx_ring); 7739 kfree(adapter->rx_ring); 7740 err_sw_init: 7741 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7742 iounmap(adapter->hw.flash_address); 7743 e1000e_reset_interrupt_capability(adapter); 7744 err_flashmap: 7745 iounmap(adapter->hw.hw_addr); 7746 err_ioremap: 7747 free_netdev(netdev); 7748 err_alloc_etherdev: 7749 pci_release_mem_regions(pdev); 7750 err_pci_reg: 7751 err_dma: 7752 pci_disable_device(pdev); 7753 return err; 7754 } 7755 7756 /** 7757 * e1000_remove - Device Removal Routine 7758 * @pdev: PCI device information struct 7759 * 7760 * e1000_remove is called by the PCI subsystem to alert the driver 7761 * that it should release a PCI device. This could be caused by a 7762 * Hot-Plug event, or because the driver is going to be removed from 7763 * memory. 7764 **/ 7765 static void e1000_remove(struct pci_dev *pdev) 7766 { 7767 struct net_device *netdev = pci_get_drvdata(pdev); 7768 struct e1000_adapter *adapter = netdev_priv(netdev); 7769 7770 e1000e_ptp_remove(adapter); 7771 7772 /* The timers may be rescheduled, so explicitly disable them 7773 * from being rescheduled. 7774 */ 7775 set_bit(__E1000_DOWN, &adapter->state); 7776 timer_delete_sync(&adapter->watchdog_timer); 7777 timer_delete_sync(&adapter->phy_info_timer); 7778 7779 cancel_work_sync(&adapter->reset_task); 7780 cancel_work_sync(&adapter->watchdog_task); 7781 cancel_work_sync(&adapter->downshift_task); 7782 cancel_work_sync(&adapter->update_phy_task); 7783 cancel_work_sync(&adapter->print_hang_task); 7784 7785 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7786 cancel_work_sync(&adapter->tx_hwtstamp_work); 7787 if (adapter->tx_hwtstamp_skb) { 7788 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7789 adapter->tx_hwtstamp_skb = NULL; 7790 } 7791 } 7792 7793 unregister_netdev(netdev); 7794 7795 if (pci_dev_run_wake(pdev)) 7796 pm_runtime_get_noresume(&pdev->dev); 7797 7798 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7799 * would have already happened in close and is redundant. 7800 */ 7801 e1000e_release_hw_control(adapter); 7802 7803 e1000e_reset_interrupt_capability(adapter); 7804 kfree(adapter->tx_ring); 7805 kfree(adapter->rx_ring); 7806 7807 iounmap(adapter->hw.hw_addr); 7808 if ((adapter->hw.flash_address) && 7809 (adapter->hw.mac.type < e1000_pch_spt)) 7810 iounmap(adapter->hw.flash_address); 7811 pci_release_mem_regions(pdev); 7812 7813 free_netdev(netdev); 7814 7815 pci_disable_device(pdev); 7816 } 7817 7818 /* PCI Error Recovery (ERS) */ 7819 static const struct pci_error_handlers e1000_err_handler = { 7820 .error_detected = e1000_io_error_detected, 7821 .slot_reset = e1000_io_slot_reset, 7822 .resume = e1000_io_resume, 7823 }; 7824 7825 static const struct pci_device_id e1000_pci_tbl[] = { 7826 { 7827 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), 7828 .driver_data = board_82571, 7829 }, { 7830 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), 7831 .driver_data = board_82571, 7832 }, { 7833 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), 7834 .driver_data = board_82571, 7835 }, { 7836 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7837 .driver_data = board_82571, 7838 }, { 7839 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), 7840 .driver_data = board_82571, 7841 }, { 7842 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), 7843 .driver_data = board_82571, 7844 }, { 7845 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), 7846 .driver_data = board_82571, 7847 }, { 7848 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), 7849 .driver_data = board_82571, 7850 }, { 7851 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), 7852 .driver_data = board_82571, 7853 }, 7854 7855 { 7856 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), 7857 .driver_data = board_82572, 7858 }, { 7859 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), 7860 .driver_data = board_82572, 7861 }, { 7862 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), 7863 .driver_data = board_82572, 7864 }, { 7865 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), 7866 .driver_data = board_82572, 7867 }, 7868 7869 { 7870 PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), 7871 .driver_data = board_82573, 7872 }, { 7873 PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), 7874 .driver_data = board_82573, 7875 }, { 7876 PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), 7877 .driver_data = board_82573, 7878 }, 7879 7880 { 7881 PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), 7882 .driver_data = board_82574, 7883 }, { 7884 PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), 7885 .driver_data = board_82574, 7886 }, { 7887 PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), 7888 .driver_data = board_82583, 7889 }, 7890 7891 { 7892 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7893 .driver_data = board_80003es2lan, 7894 }, { 7895 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7896 .driver_data = board_80003es2lan, 7897 }, { 7898 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7899 .driver_data = board_80003es2lan, 7900 }, { 7901 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7902 .driver_data = board_80003es2lan, 7903 }, 7904 7905 { 7906 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), 7907 .driver_data = board_ich8lan, 7908 }, { 7909 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), 7910 .driver_data = board_ich8lan, 7911 }, { 7912 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), 7913 .driver_data = board_ich8lan, 7914 }, { 7915 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), 7916 .driver_data = board_ich8lan, 7917 }, { 7918 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), 7919 .driver_data = board_ich8lan, 7920 }, { 7921 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), 7922 .driver_data = board_ich8lan, 7923 }, { 7924 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), 7925 .driver_data = board_ich8lan, 7926 }, { 7927 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), 7928 .driver_data = board_ich8lan, 7929 }, 7930 7931 { 7932 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), 7933 .driver_data = board_ich9lan, 7934 }, { 7935 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), 7936 .driver_data = board_ich9lan, 7937 }, { 7938 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), 7939 .driver_data = board_ich9lan, 7940 }, { 7941 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), 7942 .driver_data = board_ich9lan, 7943 }, { 7944 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), 7945 .driver_data = board_ich9lan, 7946 }, { 7947 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), 7948 .driver_data = board_ich9lan, 7949 }, { 7950 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), 7951 .driver_data = board_ich9lan, 7952 }, { 7953 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), 7954 .driver_data = board_ich9lan, 7955 }, { 7956 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), 7957 .driver_data = board_ich9lan 7958 }, 7959 7960 { 7961 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), 7962 .driver_data = board_ich9lan, 7963 }, { 7964 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), 7965 .driver_data = board_ich9lan, 7966 }, { 7967 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), 7968 .driver_data = board_ich9lan, 7969 }, 7970 7971 { 7972 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), 7973 .driver_data = board_ich10lan, 7974 }, { 7975 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), 7976 .driver_data = board_ich10lan, 7977 }, { 7978 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), 7979 .driver_data = board_ich10lan, 7980 }, 7981 7982 { 7983 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), 7984 .driver_data = board_pchlan, 7985 }, { 7986 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), 7987 .driver_data = board_pchlan, 7988 }, { 7989 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), 7990 .driver_data = board_pchlan, 7991 }, { 7992 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), 7993 .driver_data = board_pchlan 7994 }, 7995 7996 { 7997 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), 7998 .driver_data = board_pch2lan, 7999 }, { 8000 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), 8001 .driver_data = board_pch2lan 8002 }, 8003 8004 { 8005 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), 8006 .driver_data = board_pch_lpt, 8007 }, { 8008 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), 8009 .driver_data = board_pch_lpt, 8010 }, { 8011 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), 8012 .driver_data = board_pch_lpt, 8013 }, { 8014 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), 8015 .driver_data = board_pch_lpt, 8016 }, { 8017 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), 8018 .driver_data = board_pch_lpt, 8019 }, { 8020 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), 8021 .driver_data = board_pch_lpt, 8022 }, { 8023 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), 8024 .driver_data = board_pch_lpt, 8025 }, { 8026 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), 8027 .driver_data = board_pch_lpt, 8028 }, { 8029 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), 8030 .driver_data = board_pch_spt, 8031 }, { 8032 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), 8033 .driver_data = board_pch_spt, 8034 }, { 8035 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), 8036 .driver_data = board_pch_spt, 8037 }, { 8038 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), 8039 .driver_data = board_pch_spt, 8040 }, { 8041 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), 8042 .driver_data = board_pch_spt, 8043 }, { 8044 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), 8045 .driver_data = board_pch_spt, 8046 }, { 8047 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), 8048 .driver_data = board_pch_spt, 8049 }, { 8050 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), 8051 .driver_data = board_pch_spt, 8052 }, { 8053 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), 8054 .driver_data = board_pch_spt, 8055 }, { 8056 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), 8057 .driver_data = board_pch_cnp, 8058 }, { 8059 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), 8060 .driver_data = board_pch_cnp, 8061 }, { 8062 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), 8063 .driver_data = board_pch_cnp, 8064 }, { 8065 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), 8066 .driver_data = board_pch_cnp, 8067 }, { 8068 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), 8069 .driver_data = board_pch_cnp, 8070 }, { 8071 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), 8072 .driver_data = board_pch_cnp, 8073 }, { 8074 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), 8075 .driver_data = board_pch_cnp, 8076 }, { 8077 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), 8078 .driver_data = board_pch_cnp, 8079 }, { 8080 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), 8081 .driver_data = board_pch_cnp, 8082 }, { 8083 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), 8084 .driver_data = board_pch_cnp, 8085 }, { 8086 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), 8087 .driver_data = board_pch_cnp, 8088 }, { 8089 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), 8090 .driver_data = board_pch_cnp, 8091 }, { 8092 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), 8093 .driver_data = board_pch_spt, 8094 }, { 8095 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), 8096 .driver_data = board_pch_spt, 8097 }, { 8098 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), 8099 .driver_data = board_pch_tgp, 8100 }, { 8101 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), 8102 .driver_data = board_pch_tgp, 8103 }, { 8104 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), 8105 .driver_data = board_pch_tgp, 8106 }, { 8107 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), 8108 .driver_data = board_pch_tgp, 8109 }, { 8110 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), 8111 .driver_data = board_pch_tgp, 8112 }, { 8113 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), 8114 .driver_data = board_pch_tgp, 8115 }, { 8116 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), 8117 .driver_data = board_pch_adp, 8118 }, { 8119 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), 8120 .driver_data = board_pch_adp, 8121 }, { 8122 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), 8123 .driver_data = board_pch_adp, 8124 }, { 8125 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), 8126 .driver_data = board_pch_adp, 8127 }, { 8128 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), 8129 .driver_data = board_pch_adp, 8130 }, { 8131 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), 8132 .driver_data = board_pch_adp, 8133 }, { 8134 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), 8135 .driver_data = board_pch_adp, 8136 }, { 8137 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), 8138 .driver_data = board_pch_adp, 8139 }, { 8140 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM19), 8141 .driver_data = board_pch_adp, 8142 }, { 8143 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V19), 8144 .driver_data = board_pch_adp, 8145 }, { 8146 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), 8147 .driver_data = board_pch_mtp, 8148 }, { 8149 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), 8150 .driver_data = board_pch_mtp, 8151 }, { 8152 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), 8153 .driver_data = board_pch_mtp, 8154 }, { 8155 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), 8156 .driver_data = board_pch_mtp, 8157 }, { 8158 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), 8159 .driver_data = board_pch_mtp, 8160 }, { 8161 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), 8162 .driver_data = board_pch_mtp, 8163 }, { 8164 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), 8165 .driver_data = board_pch_mtp, 8166 }, { 8167 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), 8168 .driver_data = board_pch_mtp, 8169 }, { 8170 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), 8171 .driver_data = board_pch_ptp, 8172 }, { 8173 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), 8174 .driver_data = board_pch_ptp, 8175 }, { 8176 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), 8177 .driver_data = board_pch_ptp, 8178 }, { 8179 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), 8180 .driver_data = board_pch_ptp, 8181 }, { 8182 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29), 8183 .driver_data = board_pch_ptp, 8184 }, { 8185 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29), 8186 .driver_data = board_pch_ptp 8187 }, 8188 8189 { } /* terminate list */ 8190 }; 8191 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 8192 8193 static const struct dev_pm_ops e1000e_pm_ops = { 8194 .prepare = e1000e_pm_prepare, 8195 .suspend = e1000e_pm_suspend, 8196 .resume = e1000e_pm_resume, 8197 .freeze = e1000e_pm_freeze, 8198 .thaw = e1000e_pm_thaw, 8199 .poweroff = e1000e_pm_suspend, 8200 .restore = e1000e_pm_resume, 8201 RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 8202 e1000e_pm_runtime_idle) 8203 }; 8204 8205 /* PCI Device API Driver */ 8206 static struct pci_driver e1000_driver = { 8207 .name = e1000e_driver_name, 8208 .id_table = e1000_pci_tbl, 8209 .probe = e1000_probe, 8210 .remove = e1000_remove, 8211 .driver.pm = pm_ptr(&e1000e_pm_ops), 8212 .shutdown = e1000_shutdown, 8213 .err_handler = &e1000_err_handler 8214 }; 8215 8216 /** 8217 * e1000_init_module - Driver Registration Routine 8218 * 8219 * e1000_init_module is the first routine called when the driver is 8220 * loaded. All it does is register with the PCI subsystem. 8221 **/ 8222 static int __init e1000_init_module(void) 8223 { 8224 pr_info("Intel(R) PRO/1000 Network Driver\n"); 8225 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 8226 8227 return pci_register_driver(&e1000_driver); 8228 } 8229 module_init(e1000_init_module); 8230 8231 /** 8232 * e1000_exit_module - Driver Exit Cleanup Routine 8233 * 8234 * e1000_exit_module is called just before the driver is removed 8235 * from memory. 8236 **/ 8237 static void __exit e1000_exit_module(void) 8238 { 8239 pci_unregister_driver(&e1000_driver); 8240 } 8241 module_exit(e1000_exit_module); 8242 8243 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 8244 MODULE_LICENSE("GPL v2"); 8245 8246 /* netdev.c */ 8247