1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* 82562G 10/100 Network Connection 5 * 82562G-2 10/100 Network Connection 6 * 82562GT 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 8 * 82562V 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 11 * 82566DC Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 13 * 82566DM Gigabit Network Connection 14 * 82566MC Gigabit Network Connection 15 * 82566MM Gigabit Network Connection 16 * 82567LM Gigabit Network Connection 17 * 82567LF Gigabit Network Connection 18 * 82567V Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection 22 * 82567LF-3 Gigabit Network Connection 23 * 82567LM-3 Gigabit Network Connection 24 * 82567LM-4 Gigabit Network Connection 25 * 82577LM Gigabit Network Connection 26 * 82577LC Gigabit Network Connection 27 * 82578DM Gigabit Network Connection 28 * 82578DC Gigabit Network Connection 29 * 82579LM Gigabit Network Connection 30 * 82579V Gigabit Network Connection 31 * Ethernet Connection I217-LM 32 * Ethernet Connection I217-V 33 * Ethernet Connection I218-V 34 * Ethernet Connection I218-LM 35 * Ethernet Connection (2) I218-LM 36 * Ethernet Connection (2) I218-V 37 * Ethernet Connection (3) I218-LM 38 * Ethernet Connection (3) I218-V 39 */ 40 41 #include "e1000.h" 42 43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 44 /* Offset 04h HSFSTS */ 45 union ich8_hws_flash_status { 46 struct ich8_hsfsts { 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 48 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 49 u16 dael:1; /* bit 2 Direct Access error Log */ 50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 52 u16 reserved1:2; /* bit 13:6 Reserved */ 53 u16 reserved2:6; /* bit 13:6 Reserved */ 54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 56 } hsf_status; 57 u16 regval; 58 }; 59 60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 61 /* Offset 06h FLCTL */ 62 union ich8_hws_flash_ctrl { 63 struct ich8_hsflctl { 64 u16 flcgo:1; /* 0 Flash Cycle Go */ 65 u16 flcycle:2; /* 2:1 Flash Cycle */ 66 u16 reserved:5; /* 7:3 Reserved */ 67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 68 u16 flockdn:6; /* 15:10 Reserved */ 69 } hsf_ctrl; 70 u16 regval; 71 }; 72 73 /* ICH Flash Region Access Permissions */ 74 union ich8_hws_flash_regacc { 75 struct ich8_flracc { 76 u32 grra:8; /* 0:7 GbE region Read Access */ 77 u32 grwa:8; /* 8:15 GbE region Write Access */ 78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 80 } hsf_flregacc; 81 u16 regval; 82 }; 83 84 /* ICH Flash Protected Region */ 85 union ich8_flash_protected_range { 86 struct ich8_pr { 87 u32 base:13; /* 0:12 Protected Range Base */ 88 u32 reserved1:2; /* 13:14 Reserved */ 89 u32 rpe:1; /* 15 Read Protection Enable */ 90 u32 limit:13; /* 16:28 Protected Range Limit */ 91 u32 reserved2:2; /* 29:30 Reserved */ 92 u32 wpe:1; /* 31 Write Protection Enable */ 93 } range; 94 u32 regval; 95 }; 96 97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 101 u32 offset, u8 byte); 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 103 u8 *data); 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 105 u16 *data); 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 107 u8 size, u16 *data); 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 109 u32 *data); 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 111 u32 offset, u32 *data); 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 113 u32 offset, u32 data); 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 115 u32 offset, u32 dword); 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 140 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 142 { 143 return readw(hw->flash_address + reg); 144 } 145 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 147 { 148 return readl(hw->flash_address + reg); 149 } 150 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 152 { 153 writew(val, hw->flash_address + reg); 154 } 155 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 157 { 158 writel(val, hw->flash_address + reg); 159 } 160 161 #define er16flash(reg) __er16flash(hw, (reg)) 162 #define er32flash(reg) __er32flash(hw, (reg)) 163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 165 166 /** 167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 168 * @hw: pointer to the HW structure 169 * 170 * Test access to the PHY registers by reading the PHY ID registers. If 171 * the PHY ID is already known (e.g. resume path) compare it with known ID, 172 * otherwise assume the read PHY ID is correct if it is valid. 173 * 174 * Assumes the sw/fw/hw semaphore is already acquired. 175 **/ 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 177 { 178 u16 phy_reg = 0; 179 u32 phy_id = 0; 180 s32 ret_val = 0; 181 u16 retry_count; 182 u32 mac_reg = 0; 183 184 for (retry_count = 0; retry_count < 2; retry_count++) { 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 186 if (ret_val || (phy_reg == 0xFFFF)) 187 continue; 188 phy_id = (u32)(phy_reg << 16); 189 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) { 192 phy_id = 0; 193 continue; 194 } 195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 196 break; 197 } 198 199 if (hw->phy.id) { 200 if (hw->phy.id == phy_id) 201 goto out; 202 } else if (phy_id) { 203 hw->phy.id = phy_id; 204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 205 goto out; 206 } 207 208 /* In case the PHY needs to be in mdio slow mode, 209 * set slow mode and try to get the PHY id again. 210 */ 211 if (hw->mac.type < e1000_pch_lpt) { 212 hw->phy.ops.release(hw); 213 ret_val = e1000_set_mdio_slow_mode_hv(hw); 214 if (!ret_val) 215 ret_val = e1000e_get_phy_id(hw); 216 hw->phy.ops.acquire(hw); 217 } 218 219 if (ret_val) 220 return false; 221 out: 222 if (hw->mac.type >= e1000_pch_lpt) { 223 /* Only unforce SMBus if ME is not active */ 224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 225 /* Switching PHY interface always returns MDI error 226 * so disable retry mechanism to avoid wasting time 227 */ 228 e1000e_disable_phy_retry(hw); 229 230 /* Unforce SMBus mode in PHY */ 231 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 232 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 233 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 234 235 e1000e_enable_phy_retry(hw); 236 237 /* Unforce SMBus mode in MAC */ 238 mac_reg = er32(CTRL_EXT); 239 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 240 ew32(CTRL_EXT, mac_reg); 241 } 242 } 243 244 return true; 245 } 246 247 /** 248 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 249 * @hw: pointer to the HW structure 250 * 251 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 252 * used to reset the PHY to a quiescent state when necessary. 253 **/ 254 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 255 { 256 u32 mac_reg; 257 258 /* Set Phy Config Counter to 50msec */ 259 mac_reg = er32(FEXTNVM3); 260 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 261 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 262 ew32(FEXTNVM3, mac_reg); 263 264 /* Toggle LANPHYPC Value bit */ 265 mac_reg = er32(CTRL); 266 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 267 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 268 ew32(CTRL, mac_reg); 269 e1e_flush(); 270 usleep_range(10, 20); 271 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 272 ew32(CTRL, mac_reg); 273 e1e_flush(); 274 275 if (hw->mac.type < e1000_pch_lpt) { 276 msleep(50); 277 } else { 278 u16 count = 20; 279 280 do { 281 usleep_range(5000, 6000); 282 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 283 284 msleep(30); 285 } 286 } 287 288 /** 289 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 290 * @hw: pointer to the HW structure 291 * 292 * Workarounds/flow necessary for PHY initialization during driver load 293 * and resume paths. 294 **/ 295 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 296 { 297 struct e1000_adapter *adapter = hw->adapter; 298 u32 mac_reg, fwsm = er32(FWSM); 299 s32 ret_val; 300 301 /* Gate automatic PHY configuration by hardware on managed and 302 * non-managed 82579 and newer adapters. 303 */ 304 e1000_gate_hw_phy_config_ich8lan(hw, true); 305 306 /* It is not possible to be certain of the current state of ULP 307 * so forcibly disable it. 308 */ 309 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 310 ret_val = e1000_disable_ulp_lpt_lp(hw, true); 311 if (ret_val) 312 e_warn("Failed to disable ULP\n"); 313 314 ret_val = hw->phy.ops.acquire(hw); 315 if (ret_val) { 316 e_dbg("Failed to initialize PHY flow\n"); 317 goto out; 318 } 319 320 /* There is no guarantee that the PHY is accessible at this time 321 * so disable retry mechanism to avoid wasting time 322 */ 323 e1000e_disable_phy_retry(hw); 324 325 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 326 * inaccessible and resetting the PHY is not blocked, toggle the 327 * LANPHYPC Value bit to force the interconnect to PCIe mode. 328 */ 329 switch (hw->mac.type) { 330 case e1000_pch_lpt: 331 case e1000_pch_spt: 332 case e1000_pch_cnp: 333 case e1000_pch_tgp: 334 case e1000_pch_adp: 335 case e1000_pch_mtp: 336 case e1000_pch_lnp: 337 case e1000_pch_ptp: 338 case e1000_pch_nvp: 339 if (e1000_phy_is_accessible_pchlan(hw)) 340 break; 341 342 /* Before toggling LANPHYPC, see if PHY is accessible by 343 * forcing MAC to SMBus mode first. 344 */ 345 mac_reg = er32(CTRL_EXT); 346 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 347 ew32(CTRL_EXT, mac_reg); 348 349 /* Wait 50 milliseconds for MAC to finish any retries 350 * that it might be trying to perform from previous 351 * attempts to acknowledge any phy read requests. 352 */ 353 msleep(50); 354 355 fallthrough; 356 case e1000_pch2lan: 357 if (e1000_phy_is_accessible_pchlan(hw)) 358 break; 359 360 fallthrough; 361 case e1000_pchlan: 362 if ((hw->mac.type == e1000_pchlan) && 363 (fwsm & E1000_ICH_FWSM_FW_VALID)) 364 break; 365 366 if (hw->phy.ops.check_reset_block(hw)) { 367 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 368 ret_val = -E1000_ERR_PHY; 369 break; 370 } 371 372 /* Toggle LANPHYPC Value bit */ 373 e1000_toggle_lanphypc_pch_lpt(hw); 374 if (hw->mac.type >= e1000_pch_lpt) { 375 if (e1000_phy_is_accessible_pchlan(hw)) 376 break; 377 378 /* Toggling LANPHYPC brings the PHY out of SMBus mode 379 * so ensure that the MAC is also out of SMBus mode 380 */ 381 mac_reg = er32(CTRL_EXT); 382 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 383 ew32(CTRL_EXT, mac_reg); 384 385 if (e1000_phy_is_accessible_pchlan(hw)) 386 break; 387 388 ret_val = -E1000_ERR_PHY; 389 } 390 break; 391 default: 392 break; 393 } 394 395 e1000e_enable_phy_retry(hw); 396 397 hw->phy.ops.release(hw); 398 if (!ret_val) { 399 400 /* Check to see if able to reset PHY. Print error if not */ 401 if (hw->phy.ops.check_reset_block(hw)) { 402 e_err("Reset blocked by ME\n"); 403 goto out; 404 } 405 406 /* Reset the PHY before any access to it. Doing so, ensures 407 * that the PHY is in a known good state before we read/write 408 * PHY registers. The generic reset is sufficient here, 409 * because we haven't determined the PHY type yet. 410 */ 411 ret_val = e1000e_phy_hw_reset_generic(hw); 412 if (ret_val) 413 goto out; 414 415 /* On a successful reset, possibly need to wait for the PHY 416 * to quiesce to an accessible state before returning control 417 * to the calling function. If the PHY does not quiesce, then 418 * return E1000E_BLK_PHY_RESET, as this is the condition that 419 * the PHY is in. 420 */ 421 ret_val = hw->phy.ops.check_reset_block(hw); 422 if (ret_val) 423 e_err("ME blocked access to PHY after reset\n"); 424 } 425 426 out: 427 /* Ungate automatic PHY configuration on non-managed 82579 */ 428 if ((hw->mac.type == e1000_pch2lan) && 429 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 430 usleep_range(10000, 11000); 431 e1000_gate_hw_phy_config_ich8lan(hw, false); 432 } 433 434 return ret_val; 435 } 436 437 /** 438 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 439 * @hw: pointer to the HW structure 440 * 441 * Initialize family-specific PHY parameters and function pointers. 442 **/ 443 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 444 { 445 struct e1000_phy_info *phy = &hw->phy; 446 s32 ret_val; 447 448 phy->addr = 1; 449 phy->reset_delay_us = 100; 450 451 phy->ops.set_page = e1000_set_page_igp; 452 phy->ops.read_reg = e1000_read_phy_reg_hv; 453 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 454 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 455 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 456 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 457 phy->ops.write_reg = e1000_write_phy_reg_hv; 458 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 459 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 460 phy->ops.power_up = e1000_power_up_phy_copper; 461 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 462 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 463 464 phy->id = e1000_phy_unknown; 465 466 if (hw->mac.type == e1000_pch_mtp) { 467 phy->retry_count = 2; 468 e1000e_enable_phy_retry(hw); 469 } 470 471 ret_val = e1000_init_phy_workarounds_pchlan(hw); 472 if (ret_val) 473 return ret_val; 474 475 if (phy->id == e1000_phy_unknown) 476 switch (hw->mac.type) { 477 default: 478 ret_val = e1000e_get_phy_id(hw); 479 if (ret_val) 480 return ret_val; 481 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 482 break; 483 fallthrough; 484 case e1000_pch2lan: 485 case e1000_pch_lpt: 486 case e1000_pch_spt: 487 case e1000_pch_cnp: 488 case e1000_pch_tgp: 489 case e1000_pch_adp: 490 case e1000_pch_mtp: 491 case e1000_pch_lnp: 492 case e1000_pch_ptp: 493 case e1000_pch_nvp: 494 /* In case the PHY needs to be in mdio slow mode, 495 * set slow mode and try to get the PHY id again. 496 */ 497 ret_val = e1000_set_mdio_slow_mode_hv(hw); 498 if (ret_val) 499 return ret_val; 500 ret_val = e1000e_get_phy_id(hw); 501 if (ret_val) 502 return ret_val; 503 break; 504 } 505 phy->type = e1000e_get_phy_type_from_id(phy->id); 506 507 switch (phy->type) { 508 case e1000_phy_82577: 509 case e1000_phy_82579: 510 case e1000_phy_i217: 511 phy->ops.check_polarity = e1000_check_polarity_82577; 512 phy->ops.force_speed_duplex = 513 e1000_phy_force_speed_duplex_82577; 514 phy->ops.get_cable_length = e1000_get_cable_length_82577; 515 phy->ops.get_info = e1000_get_phy_info_82577; 516 phy->ops.commit = e1000e_phy_sw_reset; 517 break; 518 case e1000_phy_82578: 519 phy->ops.check_polarity = e1000_check_polarity_m88; 520 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 521 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 522 phy->ops.get_info = e1000e_get_phy_info_m88; 523 break; 524 default: 525 ret_val = -E1000_ERR_PHY; 526 break; 527 } 528 529 return ret_val; 530 } 531 532 /** 533 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 534 * @hw: pointer to the HW structure 535 * 536 * Initialize family-specific PHY parameters and function pointers. 537 **/ 538 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 539 { 540 struct e1000_phy_info *phy = &hw->phy; 541 s32 ret_val; 542 u16 i = 0; 543 544 phy->addr = 1; 545 phy->reset_delay_us = 100; 546 547 phy->ops.power_up = e1000_power_up_phy_copper; 548 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 549 550 /* We may need to do this twice - once for IGP and if that fails, 551 * we'll set BM func pointers and try again 552 */ 553 ret_val = e1000e_determine_phy_address(hw); 554 if (ret_val) { 555 phy->ops.write_reg = e1000e_write_phy_reg_bm; 556 phy->ops.read_reg = e1000e_read_phy_reg_bm; 557 ret_val = e1000e_determine_phy_address(hw); 558 if (ret_val) { 559 e_dbg("Cannot determine PHY addr. Erroring out\n"); 560 return ret_val; 561 } 562 } 563 564 phy->id = 0; 565 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 566 (i++ < 100)) { 567 usleep_range(1000, 1100); 568 ret_val = e1000e_get_phy_id(hw); 569 if (ret_val) 570 return ret_val; 571 } 572 573 /* Verify phy id */ 574 switch (phy->id) { 575 case IGP03E1000_E_PHY_ID: 576 phy->type = e1000_phy_igp_3; 577 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 578 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 579 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 580 phy->ops.get_info = e1000e_get_phy_info_igp; 581 phy->ops.check_polarity = e1000_check_polarity_igp; 582 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 583 break; 584 case IFE_E_PHY_ID: 585 case IFE_PLUS_E_PHY_ID: 586 case IFE_C_E_PHY_ID: 587 phy->type = e1000_phy_ife; 588 phy->autoneg_mask = E1000_ALL_NOT_GIG; 589 phy->ops.get_info = e1000_get_phy_info_ife; 590 phy->ops.check_polarity = e1000_check_polarity_ife; 591 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 592 break; 593 case BME1000_E_PHY_ID: 594 phy->type = e1000_phy_bm; 595 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 596 phy->ops.read_reg = e1000e_read_phy_reg_bm; 597 phy->ops.write_reg = e1000e_write_phy_reg_bm; 598 phy->ops.commit = e1000e_phy_sw_reset; 599 phy->ops.get_info = e1000e_get_phy_info_m88; 600 phy->ops.check_polarity = e1000_check_polarity_m88; 601 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 602 break; 603 default: 604 return -E1000_ERR_PHY; 605 } 606 607 return 0; 608 } 609 610 /** 611 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 612 * @hw: pointer to the HW structure 613 * 614 * Initialize family-specific NVM parameters and function 615 * pointers. 616 **/ 617 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 618 { 619 struct e1000_nvm_info *nvm = &hw->nvm; 620 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 621 u32 gfpreg, sector_base_addr, sector_end_addr; 622 u16 i; 623 u32 nvm_size; 624 625 nvm->type = e1000_nvm_flash_sw; 626 627 if (hw->mac.type >= e1000_pch_spt) { 628 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 629 * STRAP register. This is because in SPT the GbE Flash region 630 * is no longer accessed through the flash registers. Instead, 631 * the mechanism has changed, and the Flash region access 632 * registers are now implemented in GbE memory space. 633 */ 634 nvm->flash_base_addr = 0; 635 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 636 * NVM_SIZE_MULTIPLIER; 637 nvm->flash_bank_size = nvm_size / 2; 638 /* Adjust to word count */ 639 nvm->flash_bank_size /= sizeof(u16); 640 /* Set the base address for flash register access */ 641 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 642 } else { 643 /* Can't read flash registers if register set isn't mapped. */ 644 if (!hw->flash_address) { 645 e_dbg("ERROR: Flash registers not mapped\n"); 646 return -E1000_ERR_CONFIG; 647 } 648 649 gfpreg = er32flash(ICH_FLASH_GFPREG); 650 651 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 652 * Add 1 to sector_end_addr since this sector is included in 653 * the overall size. 654 */ 655 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 656 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 657 658 /* flash_base_addr is byte-aligned */ 659 nvm->flash_base_addr = sector_base_addr 660 << FLASH_SECTOR_ADDR_SHIFT; 661 662 /* find total size of the NVM, then cut in half since the total 663 * size represents two separate NVM banks. 664 */ 665 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 666 << FLASH_SECTOR_ADDR_SHIFT); 667 nvm->flash_bank_size /= 2; 668 /* Adjust to word count */ 669 nvm->flash_bank_size /= sizeof(u16); 670 } 671 672 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 673 674 /* Clear shadow ram */ 675 for (i = 0; i < nvm->word_size; i++) { 676 dev_spec->shadow_ram[i].modified = false; 677 dev_spec->shadow_ram[i].value = 0xFFFF; 678 } 679 680 return 0; 681 } 682 683 /** 684 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 685 * @hw: pointer to the HW structure 686 * 687 * Initialize family-specific MAC parameters and function 688 * pointers. 689 **/ 690 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 691 { 692 struct e1000_mac_info *mac = &hw->mac; 693 694 /* Set media type function pointer */ 695 hw->phy.media_type = e1000_media_type_copper; 696 697 /* Set mta register count */ 698 mac->mta_reg_count = 32; 699 /* Set rar entry count */ 700 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 701 if (mac->type == e1000_ich8lan) 702 mac->rar_entry_count--; 703 /* FWSM register */ 704 mac->has_fwsm = true; 705 /* ARC subsystem not supported */ 706 mac->arc_subsystem_valid = false; 707 /* Adaptive IFS supported */ 708 mac->adaptive_ifs = true; 709 710 /* LED and other operations */ 711 switch (mac->type) { 712 case e1000_ich8lan: 713 case e1000_ich9lan: 714 case e1000_ich10lan: 715 /* check management mode */ 716 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 717 /* ID LED init */ 718 mac->ops.id_led_init = e1000e_id_led_init_generic; 719 /* blink LED */ 720 mac->ops.blink_led = e1000e_blink_led_generic; 721 /* setup LED */ 722 mac->ops.setup_led = e1000e_setup_led_generic; 723 /* cleanup LED */ 724 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 725 /* turn on/off LED */ 726 mac->ops.led_on = e1000_led_on_ich8lan; 727 mac->ops.led_off = e1000_led_off_ich8lan; 728 break; 729 case e1000_pch2lan: 730 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 731 mac->ops.rar_set = e1000_rar_set_pch2lan; 732 fallthrough; 733 case e1000_pch_lpt: 734 case e1000_pch_spt: 735 case e1000_pch_cnp: 736 case e1000_pch_tgp: 737 case e1000_pch_adp: 738 case e1000_pch_mtp: 739 case e1000_pch_lnp: 740 case e1000_pch_ptp: 741 case e1000_pch_nvp: 742 case e1000_pchlan: 743 /* check management mode */ 744 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 745 /* ID LED init */ 746 mac->ops.id_led_init = e1000_id_led_init_pchlan; 747 /* setup LED */ 748 mac->ops.setup_led = e1000_setup_led_pchlan; 749 /* cleanup LED */ 750 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 751 /* turn on/off LED */ 752 mac->ops.led_on = e1000_led_on_pchlan; 753 mac->ops.led_off = e1000_led_off_pchlan; 754 break; 755 default: 756 break; 757 } 758 759 if (mac->type >= e1000_pch_lpt) { 760 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 761 mac->ops.rar_set = e1000_rar_set_pch_lpt; 762 mac->ops.setup_physical_interface = 763 e1000_setup_copper_link_pch_lpt; 764 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 765 } 766 767 /* Enable PCS Lock-loss workaround for ICH8 */ 768 if (mac->type == e1000_ich8lan) 769 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 770 771 return 0; 772 } 773 774 /** 775 * __e1000_access_emi_reg_locked - Read/write EMI register 776 * @hw: pointer to the HW structure 777 * @address: EMI address to program 778 * @data: pointer to value to read/write from/to the EMI address 779 * @read: boolean flag to indicate read or write 780 * 781 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 782 **/ 783 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 784 u16 *data, bool read) 785 { 786 s32 ret_val; 787 788 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 789 if (ret_val) 790 return ret_val; 791 792 if (read) 793 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 794 else 795 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 796 797 return ret_val; 798 } 799 800 /** 801 * e1000_read_emi_reg_locked - Read Extended Management Interface register 802 * @hw: pointer to the HW structure 803 * @addr: EMI address to program 804 * @data: value to be read from the EMI address 805 * 806 * Assumes the SW/FW/HW Semaphore is already acquired. 807 **/ 808 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 809 { 810 return __e1000_access_emi_reg_locked(hw, addr, data, true); 811 } 812 813 /** 814 * e1000_write_emi_reg_locked - Write Extended Management Interface register 815 * @hw: pointer to the HW structure 816 * @addr: EMI address to program 817 * @data: value to be written to the EMI address 818 * 819 * Assumes the SW/FW/HW Semaphore is already acquired. 820 **/ 821 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 822 { 823 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 824 } 825 826 /** 827 * e1000_set_eee_pchlan - Enable/disable EEE support 828 * @hw: pointer to the HW structure 829 * 830 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 831 * the link and the EEE capabilities of the link partner. The LPI Control 832 * register bits will remain set only if/when link is up. 833 * 834 * EEE LPI must not be asserted earlier than one second after link is up. 835 * On 82579, EEE LPI should not be enabled until such time otherwise there 836 * can be link issues with some switches. Other devices can have EEE LPI 837 * enabled immediately upon link up since they have a timer in hardware which 838 * prevents LPI from being asserted too early. 839 **/ 840 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 841 { 842 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 843 s32 ret_val; 844 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 845 846 switch (hw->phy.type) { 847 case e1000_phy_82579: 848 lpa = I82579_EEE_LP_ABILITY; 849 pcs_status = I82579_EEE_PCS_STATUS; 850 adv_addr = I82579_EEE_ADVERTISEMENT; 851 break; 852 case e1000_phy_i217: 853 lpa = I217_EEE_LP_ABILITY; 854 pcs_status = I217_EEE_PCS_STATUS; 855 adv_addr = I217_EEE_ADVERTISEMENT; 856 break; 857 default: 858 return 0; 859 } 860 861 ret_val = hw->phy.ops.acquire(hw); 862 if (ret_val) 863 return ret_val; 864 865 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 866 if (ret_val) 867 goto release; 868 869 /* Clear bits that enable EEE in various speeds */ 870 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 871 872 /* Enable EEE if not disabled by user */ 873 if (!dev_spec->eee_disable) { 874 /* Save off link partner's EEE ability */ 875 ret_val = e1000_read_emi_reg_locked(hw, lpa, 876 &dev_spec->eee_lp_ability); 877 if (ret_val) 878 goto release; 879 880 /* Read EEE advertisement */ 881 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 882 if (ret_val) 883 goto release; 884 885 /* Enable EEE only for speeds in which the link partner is 886 * EEE capable and for which we advertise EEE. 887 */ 888 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 889 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 890 891 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 892 e1e_rphy_locked(hw, MII_LPA, &data); 893 if (data & LPA_100FULL) 894 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 895 else 896 /* EEE is not supported in 100Half, so ignore 897 * partner's EEE in 100 ability if full-duplex 898 * is not advertised. 899 */ 900 dev_spec->eee_lp_ability &= 901 ~I82579_EEE_100_SUPPORTED; 902 } 903 } 904 905 if (hw->phy.type == e1000_phy_82579) { 906 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 907 &data); 908 if (ret_val) 909 goto release; 910 911 data &= ~I82579_LPI_100_PLL_SHUT; 912 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 913 data); 914 } 915 916 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 917 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 918 if (ret_val) 919 goto release; 920 921 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 922 release: 923 hw->phy.ops.release(hw); 924 925 return ret_val; 926 } 927 928 /** 929 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 930 * @hw: pointer to the HW structure 931 * @link: link up bool flag 932 * 933 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 934 * preventing further DMA write requests. Workaround the issue by disabling 935 * the de-assertion of the clock request when in 1Gpbs mode. 936 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 937 * speeds in order to avoid Tx hangs. 938 **/ 939 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 940 { 941 u32 fextnvm6 = er32(FEXTNVM6); 942 u32 status = er32(STATUS); 943 s32 ret_val = 0; 944 u16 reg; 945 946 if (link && (status & E1000_STATUS_SPEED_1000)) { 947 ret_val = hw->phy.ops.acquire(hw); 948 if (ret_val) 949 return ret_val; 950 951 ret_val = 952 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 953 ®); 954 if (ret_val) 955 goto release; 956 957 ret_val = 958 e1000e_write_kmrn_reg_locked(hw, 959 E1000_KMRNCTRLSTA_K1_CONFIG, 960 reg & 961 ~E1000_KMRNCTRLSTA_K1_ENABLE); 962 if (ret_val) 963 goto release; 964 965 usleep_range(10, 20); 966 967 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 968 969 ret_val = 970 e1000e_write_kmrn_reg_locked(hw, 971 E1000_KMRNCTRLSTA_K1_CONFIG, 972 reg); 973 release: 974 hw->phy.ops.release(hw); 975 } else { 976 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 977 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 978 979 if ((hw->phy.revision > 5) || !link || 980 ((status & E1000_STATUS_SPEED_100) && 981 (status & E1000_STATUS_FD))) 982 goto update_fextnvm6; 983 984 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 985 if (ret_val) 986 return ret_val; 987 988 /* Clear link status transmit timeout */ 989 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 990 991 if (status & E1000_STATUS_SPEED_100) { 992 /* Set inband Tx timeout to 5x10us for 100Half */ 993 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 994 995 /* Do not extend the K1 entry latency for 100Half */ 996 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 997 } else { 998 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 999 reg |= 50 << 1000 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1001 1002 /* Extend the K1 entry latency for 10 Mbps */ 1003 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1004 } 1005 1006 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 1007 if (ret_val) 1008 return ret_val; 1009 1010 update_fextnvm6: 1011 ew32(FEXTNVM6, fextnvm6); 1012 } 1013 1014 return ret_val; 1015 } 1016 1017 /** 1018 * e1000_platform_pm_pch_lpt - Set platform power management values 1019 * @hw: pointer to the HW structure 1020 * @link: bool indicating link status 1021 * 1022 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1023 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1024 * when link is up (which must not exceed the maximum latency supported 1025 * by the platform), otherwise specify there is no LTR requirement. 1026 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 1027 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1028 * Capability register set, on this device LTR is set by writing the 1029 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1030 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1031 * message to the PMC. 1032 **/ 1033 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1034 { 1035 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1036 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1037 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */ 1038 u32 lat_enc_d = 0; /* latency decoded */ 1039 u16 lat_enc = 0; /* latency encoded */ 1040 1041 if (link) { 1042 u16 speed, duplex, scale = 0; 1043 u16 max_snoop, max_nosnoop; 1044 u16 max_ltr_enc; /* max LTR latency encoded */ 1045 u64 value; 1046 u32 rxa; 1047 1048 if (!hw->adapter->max_frame_size) { 1049 e_dbg("max_frame_size not set.\n"); 1050 return -E1000_ERR_CONFIG; 1051 } 1052 1053 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1054 if (!speed) { 1055 e_dbg("Speed not set.\n"); 1056 return -E1000_ERR_CONFIG; 1057 } 1058 1059 /* Rx Packet Buffer Allocation size (KB) */ 1060 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1061 1062 /* Determine the maximum latency tolerated by the device. 1063 * 1064 * Per the PCIe spec, the tolerated latencies are encoded as 1065 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1066 * a 10-bit value (0-1023) to provide a range from 1 ns to 1067 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1068 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1069 */ 1070 rxa *= 512; 1071 value = (rxa > hw->adapter->max_frame_size) ? 1072 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1073 0; 1074 1075 while (value > PCI_LTR_VALUE_MASK) { 1076 scale++; 1077 value = DIV_ROUND_UP(value, BIT(5)); 1078 } 1079 if (scale > E1000_LTRV_SCALE_MAX) { 1080 e_dbg("Invalid LTR latency scale %d\n", scale); 1081 return -E1000_ERR_CONFIG; 1082 } 1083 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1084 1085 /* Determine the maximum latency tolerated by the platform */ 1086 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1087 &max_snoop); 1088 pci_read_config_word(hw->adapter->pdev, 1089 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1090 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1091 1092 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) * 1093 (1U << (E1000_LTRV_SCALE_FACTOR * 1094 FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc))); 1095 1096 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) * 1097 (1U << (E1000_LTRV_SCALE_FACTOR * 1098 FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc))); 1099 1100 if (lat_enc_d > max_ltr_enc_d) 1101 lat_enc = max_ltr_enc; 1102 } 1103 1104 /* Set Snoop and No-Snoop latencies the same */ 1105 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1106 ew32(LTRV, reg); 1107 1108 return 0; 1109 } 1110 1111 /** 1112 * e1000e_force_smbus - Force interfaces to transition to SMBUS mode. 1113 * @hw: pointer to the HW structure 1114 * 1115 * Force the MAC and the PHY to SMBUS mode. Assumes semaphore already 1116 * acquired. 1117 * 1118 * Return: 0 on success, negative errno on failure. 1119 **/ 1120 static s32 e1000e_force_smbus(struct e1000_hw *hw) 1121 { 1122 u16 smb_ctrl = 0; 1123 u32 ctrl_ext; 1124 s32 ret_val; 1125 1126 /* Switching PHY interface always returns MDI error 1127 * so disable retry mechanism to avoid wasting time 1128 */ 1129 e1000e_disable_phy_retry(hw); 1130 1131 /* Force SMBus mode in the PHY */ 1132 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &smb_ctrl); 1133 if (ret_val) { 1134 e1000e_enable_phy_retry(hw); 1135 return ret_val; 1136 } 1137 1138 smb_ctrl |= CV_SMB_CTRL_FORCE_SMBUS; 1139 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, smb_ctrl); 1140 1141 e1000e_enable_phy_retry(hw); 1142 1143 /* Force SMBus mode in the MAC */ 1144 ctrl_ext = er32(CTRL_EXT); 1145 ctrl_ext |= E1000_CTRL_EXT_FORCE_SMBUS; 1146 ew32(CTRL_EXT, ctrl_ext); 1147 1148 return 0; 1149 } 1150 1151 /** 1152 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1153 * @hw: pointer to the HW structure 1154 * @to_sx: boolean indicating a system power state transition to Sx 1155 * 1156 * When link is down, configure ULP mode to significantly reduce the power 1157 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1158 * ME firmware to start the ULP configuration. If not on an ME enabled 1159 * system, configure the ULP mode by software. 1160 */ 1161 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1162 { 1163 u32 mac_reg; 1164 s32 ret_val = 0; 1165 u16 phy_reg; 1166 u16 oem_reg = 0; 1167 1168 if ((hw->mac.type < e1000_pch_lpt) || 1169 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1170 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1171 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1172 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1173 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1174 return 0; 1175 1176 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1177 /* Request ME configure ULP mode in the PHY */ 1178 mac_reg = er32(H2ME); 1179 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1180 ew32(H2ME, mac_reg); 1181 1182 goto out; 1183 } 1184 1185 if (!to_sx) { 1186 int i = 0; 1187 1188 /* Poll up to 5 seconds for Cable Disconnected indication */ 1189 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1190 /* Bail if link is re-acquired */ 1191 if (er32(STATUS) & E1000_STATUS_LU) 1192 return -E1000_ERR_PHY; 1193 1194 if (i++ == 100) 1195 break; 1196 1197 msleep(50); 1198 } 1199 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1200 (er32(FEXT) & 1201 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1202 } 1203 1204 ret_val = hw->phy.ops.acquire(hw); 1205 if (ret_val) 1206 goto out; 1207 1208 if (hw->mac.type != e1000_pch_mtp) { 1209 ret_val = e1000e_force_smbus(hw); 1210 if (ret_val) { 1211 e_dbg("Failed to force SMBUS: %d\n", ret_val); 1212 goto release; 1213 } 1214 } 1215 1216 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1217 * LPLU and disable Gig speed when entering ULP 1218 */ 1219 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1220 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1221 &oem_reg); 1222 if (ret_val) 1223 goto release; 1224 1225 phy_reg = oem_reg; 1226 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1227 1228 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1229 phy_reg); 1230 1231 if (ret_val) 1232 goto release; 1233 } 1234 1235 /* Set Inband ULP Exit, Reset to SMBus mode and 1236 * Disable SMBus Release on PERST# in PHY 1237 */ 1238 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1239 if (ret_val) 1240 goto release; 1241 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1242 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1243 if (to_sx) { 1244 if (er32(WUFC) & E1000_WUFC_LNKC) 1245 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1246 else 1247 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1248 1249 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1250 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1251 } else { 1252 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1253 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1254 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1255 } 1256 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1257 1258 /* Set Disable SMBus Release on PERST# in MAC */ 1259 mac_reg = er32(FEXTNVM7); 1260 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1261 ew32(FEXTNVM7, mac_reg); 1262 1263 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1264 phy_reg |= I218_ULP_CONFIG1_START; 1265 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1266 1267 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1268 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1269 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1270 oem_reg); 1271 if (ret_val) 1272 goto release; 1273 } 1274 1275 release: 1276 if (hw->mac.type == e1000_pch_mtp) { 1277 ret_val = e1000e_force_smbus(hw); 1278 if (ret_val) 1279 e_dbg("Failed to force SMBUS over MTL system: %d\n", 1280 ret_val); 1281 } 1282 1283 hw->phy.ops.release(hw); 1284 out: 1285 if (ret_val) 1286 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1287 else 1288 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1289 1290 return ret_val; 1291 } 1292 1293 /** 1294 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1295 * @hw: pointer to the HW structure 1296 * @force: boolean indicating whether or not to force disabling ULP 1297 * 1298 * Un-configure ULP mode when link is up, the system is transitioned from 1299 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1300 * system, poll for an indication from ME that ULP has been un-configured. 1301 * If not on an ME enabled system, un-configure the ULP mode by software. 1302 * 1303 * During nominal operation, this function is called when link is acquired 1304 * to disable ULP mode (force=false); otherwise, for example when unloading 1305 * the driver or during Sx->S0 transitions, this is called with force=true 1306 * to forcibly disable ULP. 1307 */ 1308 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1309 { 1310 s32 ret_val = 0; 1311 u32 mac_reg; 1312 u16 phy_reg; 1313 int i = 0; 1314 1315 if ((hw->mac.type < e1000_pch_lpt) || 1316 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1317 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1318 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1319 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1320 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1321 return 0; 1322 1323 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1324 struct e1000_adapter *adapter = hw->adapter; 1325 bool firmware_bug = false; 1326 1327 if (force) { 1328 /* Request ME un-configure ULP mode in the PHY */ 1329 mac_reg = er32(H2ME); 1330 mac_reg &= ~E1000_H2ME_ULP; 1331 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1332 ew32(H2ME, mac_reg); 1333 } 1334 1335 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE. 1336 * If this takes more than 1 second, show a warning indicating a 1337 * firmware bug 1338 */ 1339 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1340 if (i++ == 250) { 1341 ret_val = -E1000_ERR_PHY; 1342 goto out; 1343 } 1344 if (i > 100 && !firmware_bug) 1345 firmware_bug = true; 1346 1347 usleep_range(10000, 11000); 1348 } 1349 if (firmware_bug) 1350 e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n", 1351 i * 10); 1352 else 1353 e_dbg("ULP_CONFIG_DONE cleared after %d msec\n", 1354 i * 10); 1355 1356 if (force) { 1357 mac_reg = er32(H2ME); 1358 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1359 ew32(H2ME, mac_reg); 1360 } else { 1361 /* Clear H2ME.ULP after ME ULP configuration */ 1362 mac_reg = er32(H2ME); 1363 mac_reg &= ~E1000_H2ME_ULP; 1364 ew32(H2ME, mac_reg); 1365 } 1366 1367 goto out; 1368 } 1369 1370 ret_val = hw->phy.ops.acquire(hw); 1371 if (ret_val) 1372 goto out; 1373 1374 if (force) 1375 /* Toggle LANPHYPC Value bit */ 1376 e1000_toggle_lanphypc_pch_lpt(hw); 1377 1378 /* Switching PHY interface always returns MDI error 1379 * so disable retry mechanism to avoid wasting time 1380 */ 1381 e1000e_disable_phy_retry(hw); 1382 1383 /* Unforce SMBus mode in PHY */ 1384 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1385 if (ret_val) { 1386 /* The MAC might be in PCIe mode, so temporarily force to 1387 * SMBus mode in order to access the PHY. 1388 */ 1389 mac_reg = er32(CTRL_EXT); 1390 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1391 ew32(CTRL_EXT, mac_reg); 1392 1393 msleep(50); 1394 1395 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1396 &phy_reg); 1397 if (ret_val) 1398 goto release; 1399 } 1400 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1401 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1402 1403 e1000e_enable_phy_retry(hw); 1404 1405 /* Unforce SMBus mode in MAC */ 1406 mac_reg = er32(CTRL_EXT); 1407 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1408 ew32(CTRL_EXT, mac_reg); 1409 1410 /* When ULP mode was previously entered, K1 was disabled by the 1411 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1412 */ 1413 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1414 if (ret_val) 1415 goto release; 1416 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1417 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1418 1419 /* Clear ULP enabled configuration */ 1420 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1421 if (ret_val) 1422 goto release; 1423 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1424 I218_ULP_CONFIG1_STICKY_ULP | 1425 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1426 I218_ULP_CONFIG1_WOL_HOST | 1427 I218_ULP_CONFIG1_INBAND_EXIT | 1428 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1429 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1430 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1431 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1432 1433 /* Commit ULP changes by starting auto ULP configuration */ 1434 phy_reg |= I218_ULP_CONFIG1_START; 1435 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1436 1437 /* Clear Disable SMBus Release on PERST# in MAC */ 1438 mac_reg = er32(FEXTNVM7); 1439 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1440 ew32(FEXTNVM7, mac_reg); 1441 1442 release: 1443 hw->phy.ops.release(hw); 1444 if (force) { 1445 e1000_phy_hw_reset(hw); 1446 msleep(50); 1447 } 1448 out: 1449 if (ret_val) 1450 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1451 else 1452 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1453 1454 return ret_val; 1455 } 1456 1457 /** 1458 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1459 * @hw: pointer to the HW structure 1460 * 1461 * Checks to see of the link status of the hardware has changed. If a 1462 * change in link status has been detected, then we read the PHY registers 1463 * to get the current speed/duplex if link exists. 1464 **/ 1465 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1466 { 1467 struct e1000_mac_info *mac = &hw->mac; 1468 s32 ret_val, tipg_reg = 0; 1469 u16 emi_addr, emi_val = 0; 1470 bool link; 1471 u16 phy_reg; 1472 1473 /* We only want to go out to the PHY registers to see if Auto-Neg 1474 * has completed and/or if our link status has changed. The 1475 * get_link_status flag is set upon receiving a Link Status 1476 * Change or Rx Sequence Error interrupt. 1477 */ 1478 if (!mac->get_link_status) 1479 return 0; 1480 mac->get_link_status = false; 1481 1482 /* First we want to see if the MII Status Register reports 1483 * link. If so, then we want to get the current speed/duplex 1484 * of the PHY. 1485 */ 1486 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1487 if (ret_val) 1488 goto out; 1489 1490 if (hw->mac.type == e1000_pchlan) { 1491 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1492 if (ret_val) 1493 goto out; 1494 } 1495 1496 /* When connected at 10Mbps half-duplex, some parts are excessively 1497 * aggressive resulting in many collisions. To avoid this, increase 1498 * the IPG and reduce Rx latency in the PHY. 1499 */ 1500 if ((hw->mac.type >= e1000_pch2lan) && link) { 1501 u16 speed, duplex; 1502 1503 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1504 tipg_reg = er32(TIPG); 1505 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1506 1507 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1508 tipg_reg |= 0xFF; 1509 /* Reduce Rx latency in analog PHY */ 1510 emi_val = 0; 1511 } else if (hw->mac.type >= e1000_pch_spt && 1512 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1513 tipg_reg |= 0xC; 1514 emi_val = 1; 1515 } else { 1516 1517 /* Roll back the default values */ 1518 tipg_reg |= 0x08; 1519 emi_val = 1; 1520 } 1521 1522 ew32(TIPG, tipg_reg); 1523 1524 ret_val = hw->phy.ops.acquire(hw); 1525 if (ret_val) 1526 goto out; 1527 1528 if (hw->mac.type == e1000_pch2lan) 1529 emi_addr = I82579_RX_CONFIG; 1530 else 1531 emi_addr = I217_RX_CONFIG; 1532 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1533 1534 if (hw->mac.type >= e1000_pch_lpt) { 1535 u16 phy_reg; 1536 1537 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1538 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1539 if (speed == SPEED_100 || speed == SPEED_10) 1540 phy_reg |= 0x3E8; 1541 else 1542 phy_reg |= 0xFA; 1543 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1544 1545 if (speed == SPEED_1000) { 1546 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1547 &phy_reg); 1548 1549 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1550 1551 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1552 phy_reg); 1553 } 1554 } 1555 hw->phy.ops.release(hw); 1556 1557 if (ret_val) 1558 goto out; 1559 1560 if (hw->mac.type >= e1000_pch_spt) { 1561 u16 data; 1562 u16 ptr_gap; 1563 1564 if (speed == SPEED_1000) { 1565 ret_val = hw->phy.ops.acquire(hw); 1566 if (ret_val) 1567 goto out; 1568 1569 ret_val = e1e_rphy_locked(hw, 1570 PHY_REG(776, 20), 1571 &data); 1572 if (ret_val) { 1573 hw->phy.ops.release(hw); 1574 goto out; 1575 } 1576 1577 ptr_gap = (data & (0x3FF << 2)) >> 2; 1578 if (ptr_gap < 0x18) { 1579 data &= ~(0x3FF << 2); 1580 data |= (0x18 << 2); 1581 ret_val = 1582 e1e_wphy_locked(hw, 1583 PHY_REG(776, 20), 1584 data); 1585 } 1586 hw->phy.ops.release(hw); 1587 if (ret_val) 1588 goto out; 1589 } else { 1590 ret_val = hw->phy.ops.acquire(hw); 1591 if (ret_val) 1592 goto out; 1593 1594 ret_val = e1e_wphy_locked(hw, 1595 PHY_REG(776, 20), 1596 0xC023); 1597 hw->phy.ops.release(hw); 1598 if (ret_val) 1599 goto out; 1600 1601 } 1602 } 1603 } 1604 1605 /* I217 Packet Loss issue: 1606 * ensure that FEXTNVM4 Beacon Duration is set correctly 1607 * on power up. 1608 * Set the Beacon Duration for I217 to 8 usec 1609 */ 1610 if (hw->mac.type >= e1000_pch_lpt) { 1611 u32 mac_reg; 1612 1613 mac_reg = er32(FEXTNVM4); 1614 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1615 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1616 ew32(FEXTNVM4, mac_reg); 1617 } 1618 1619 /* Work-around I218 hang issue */ 1620 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1621 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1622 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1623 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1624 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1625 if (ret_val) 1626 goto out; 1627 } 1628 if (hw->mac.type >= e1000_pch_lpt) { 1629 /* Set platform power management values for 1630 * Latency Tolerance Reporting (LTR) 1631 */ 1632 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1633 if (ret_val) 1634 goto out; 1635 } 1636 1637 /* Clear link partner's EEE ability */ 1638 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1639 1640 if (hw->mac.type >= e1000_pch_lpt) { 1641 u32 fextnvm6 = er32(FEXTNVM6); 1642 1643 if (hw->mac.type == e1000_pch_spt) { 1644 /* FEXTNVM6 K1-off workaround - for SPT only */ 1645 u32 pcieanacfg = er32(PCIEANACFG); 1646 1647 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1648 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1649 else 1650 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1651 } 1652 1653 ew32(FEXTNVM6, fextnvm6); 1654 } 1655 1656 if (!link) 1657 goto out; 1658 1659 switch (hw->mac.type) { 1660 case e1000_pch2lan: 1661 ret_val = e1000_k1_workaround_lv(hw); 1662 if (ret_val) 1663 return ret_val; 1664 fallthrough; 1665 case e1000_pchlan: 1666 if (hw->phy.type == e1000_phy_82578) { 1667 ret_val = e1000_link_stall_workaround_hv(hw); 1668 if (ret_val) 1669 return ret_val; 1670 } 1671 1672 /* Workaround for PCHx parts in half-duplex: 1673 * Set the number of preambles removed from the packet 1674 * when it is passed from the PHY to the MAC to prevent 1675 * the MAC from misinterpreting the packet type. 1676 */ 1677 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1678 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1679 1680 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1681 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1682 1683 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1684 break; 1685 default: 1686 break; 1687 } 1688 1689 /* Check if there was DownShift, must be checked 1690 * immediately after link-up 1691 */ 1692 e1000e_check_downshift(hw); 1693 1694 /* Enable/Disable EEE after link up */ 1695 if (hw->phy.type > e1000_phy_82579) { 1696 ret_val = e1000_set_eee_pchlan(hw); 1697 if (ret_val) 1698 return ret_val; 1699 } 1700 1701 /* If we are forcing speed/duplex, then we simply return since 1702 * we have already determined whether we have link or not. 1703 */ 1704 if (!mac->autoneg) 1705 return -E1000_ERR_CONFIG; 1706 1707 /* Auto-Neg is enabled. Auto Speed Detection takes care 1708 * of MAC speed/duplex configuration. So we only need to 1709 * configure Collision Distance in the MAC. 1710 */ 1711 mac->ops.config_collision_dist(hw); 1712 1713 /* Configure Flow Control now that Auto-Neg has completed. 1714 * First, we need to restore the desired flow control 1715 * settings because we may have had to re-autoneg with a 1716 * different link partner. 1717 */ 1718 ret_val = e1000e_config_fc_after_link_up(hw); 1719 if (ret_val) 1720 e_dbg("Error configuring flow control\n"); 1721 1722 return ret_val; 1723 1724 out: 1725 mac->get_link_status = true; 1726 return ret_val; 1727 } 1728 1729 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1730 { 1731 struct e1000_hw *hw = &adapter->hw; 1732 s32 rc; 1733 1734 rc = e1000_init_mac_params_ich8lan(hw); 1735 if (rc) 1736 return rc; 1737 1738 rc = e1000_init_nvm_params_ich8lan(hw); 1739 if (rc) 1740 return rc; 1741 1742 switch (hw->mac.type) { 1743 case e1000_ich8lan: 1744 case e1000_ich9lan: 1745 case e1000_ich10lan: 1746 rc = e1000_init_phy_params_ich8lan(hw); 1747 break; 1748 case e1000_pchlan: 1749 case e1000_pch2lan: 1750 case e1000_pch_lpt: 1751 case e1000_pch_spt: 1752 case e1000_pch_cnp: 1753 case e1000_pch_tgp: 1754 case e1000_pch_adp: 1755 case e1000_pch_mtp: 1756 case e1000_pch_lnp: 1757 case e1000_pch_ptp: 1758 case e1000_pch_nvp: 1759 rc = e1000_init_phy_params_pchlan(hw); 1760 break; 1761 default: 1762 break; 1763 } 1764 if (rc) 1765 return rc; 1766 1767 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1768 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1769 */ 1770 if ((adapter->hw.phy.type == e1000_phy_ife) || 1771 ((adapter->hw.mac.type >= e1000_pch2lan) && 1772 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1773 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1774 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1775 1776 hw->mac.ops.blink_led = NULL; 1777 } 1778 1779 if ((adapter->hw.mac.type == e1000_ich8lan) && 1780 (adapter->hw.phy.type != e1000_phy_ife)) 1781 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1782 1783 /* Enable workaround for 82579 w/ ME enabled */ 1784 if ((adapter->hw.mac.type == e1000_pch2lan) && 1785 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1786 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1787 1788 return 0; 1789 } 1790 1791 static DEFINE_MUTEX(nvm_mutex); 1792 1793 /** 1794 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1795 * @hw: pointer to the HW structure 1796 * 1797 * Acquires the mutex for performing NVM operations. 1798 **/ 1799 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1800 { 1801 mutex_lock(&nvm_mutex); 1802 1803 return 0; 1804 } 1805 1806 /** 1807 * e1000_release_nvm_ich8lan - Release NVM mutex 1808 * @hw: pointer to the HW structure 1809 * 1810 * Releases the mutex used while performing NVM operations. 1811 **/ 1812 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1813 { 1814 mutex_unlock(&nvm_mutex); 1815 } 1816 1817 /** 1818 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1819 * @hw: pointer to the HW structure 1820 * 1821 * Acquires the software control flag for performing PHY and select 1822 * MAC CSR accesses. 1823 **/ 1824 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1825 { 1826 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1827 s32 ret_val = 0; 1828 1829 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1830 &hw->adapter->state)) { 1831 e_dbg("contention for Phy access\n"); 1832 return -E1000_ERR_PHY; 1833 } 1834 1835 while (timeout) { 1836 extcnf_ctrl = er32(EXTCNF_CTRL); 1837 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1838 break; 1839 1840 mdelay(1); 1841 timeout--; 1842 } 1843 1844 if (!timeout) { 1845 e_dbg("SW has already locked the resource.\n"); 1846 ret_val = -E1000_ERR_CONFIG; 1847 goto out; 1848 } 1849 1850 timeout = SW_FLAG_TIMEOUT; 1851 1852 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1853 ew32(EXTCNF_CTRL, extcnf_ctrl); 1854 1855 while (timeout) { 1856 extcnf_ctrl = er32(EXTCNF_CTRL); 1857 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1858 break; 1859 1860 mdelay(1); 1861 timeout--; 1862 } 1863 1864 if (!timeout) { 1865 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1866 er32(FWSM), extcnf_ctrl); 1867 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1868 ew32(EXTCNF_CTRL, extcnf_ctrl); 1869 ret_val = -E1000_ERR_CONFIG; 1870 goto out; 1871 } 1872 1873 out: 1874 if (ret_val) 1875 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1876 1877 return ret_val; 1878 } 1879 1880 /** 1881 * e1000_release_swflag_ich8lan - Release software control flag 1882 * @hw: pointer to the HW structure 1883 * 1884 * Releases the software control flag for performing PHY and select 1885 * MAC CSR accesses. 1886 **/ 1887 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1888 { 1889 u32 extcnf_ctrl; 1890 1891 extcnf_ctrl = er32(EXTCNF_CTRL); 1892 1893 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1894 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1895 ew32(EXTCNF_CTRL, extcnf_ctrl); 1896 } else { 1897 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1898 } 1899 1900 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1901 } 1902 1903 /** 1904 * e1000_check_mng_mode_ich8lan - Checks management mode 1905 * @hw: pointer to the HW structure 1906 * 1907 * This checks if the adapter has any manageability enabled. 1908 * This is a function pointer entry point only called by read/write 1909 * routines for the PHY and NVM parts. 1910 **/ 1911 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1912 { 1913 u32 fwsm; 1914 1915 fwsm = er32(FWSM); 1916 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1917 ((fwsm & E1000_FWSM_MODE_MASK) == 1918 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1919 } 1920 1921 /** 1922 * e1000_check_mng_mode_pchlan - Checks management mode 1923 * @hw: pointer to the HW structure 1924 * 1925 * This checks if the adapter has iAMT enabled. 1926 * This is a function pointer entry point only called by read/write 1927 * routines for the PHY and NVM parts. 1928 **/ 1929 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1930 { 1931 u32 fwsm; 1932 1933 fwsm = er32(FWSM); 1934 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1935 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1936 } 1937 1938 /** 1939 * e1000_rar_set_pch2lan - Set receive address register 1940 * @hw: pointer to the HW structure 1941 * @addr: pointer to the receive address 1942 * @index: receive address array register 1943 * 1944 * Sets the receive address array register at index to the address passed 1945 * in by addr. For 82579, RAR[0] is the base address register that is to 1946 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1947 * Use SHRA[0-3] in place of those reserved for ME. 1948 **/ 1949 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1950 { 1951 u32 rar_low, rar_high; 1952 1953 /* HW expects these in little endian so we reverse the byte order 1954 * from network order (big endian) to little endian 1955 */ 1956 rar_low = ((u32)addr[0] | 1957 ((u32)addr[1] << 8) | 1958 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1959 1960 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1961 1962 /* If MAC address zero, no need to set the AV bit */ 1963 if (rar_low || rar_high) 1964 rar_high |= E1000_RAH_AV; 1965 1966 if (index == 0) { 1967 ew32(RAL(index), rar_low); 1968 e1e_flush(); 1969 ew32(RAH(index), rar_high); 1970 e1e_flush(); 1971 return 0; 1972 } 1973 1974 /* RAR[1-6] are owned by manageability. Skip those and program the 1975 * next address into the SHRA register array. 1976 */ 1977 if (index < (u32)(hw->mac.rar_entry_count)) { 1978 s32 ret_val; 1979 1980 ret_val = e1000_acquire_swflag_ich8lan(hw); 1981 if (ret_val) 1982 goto out; 1983 1984 ew32(SHRAL(index - 1), rar_low); 1985 e1e_flush(); 1986 ew32(SHRAH(index - 1), rar_high); 1987 e1e_flush(); 1988 1989 e1000_release_swflag_ich8lan(hw); 1990 1991 /* verify the register updates */ 1992 if ((er32(SHRAL(index - 1)) == rar_low) && 1993 (er32(SHRAH(index - 1)) == rar_high)) 1994 return 0; 1995 1996 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1997 (index - 1), er32(FWSM)); 1998 } 1999 2000 out: 2001 e_dbg("Failed to write receive address at index %d\n", index); 2002 return -E1000_ERR_CONFIG; 2003 } 2004 2005 /** 2006 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 2007 * @hw: pointer to the HW structure 2008 * 2009 * Get the number of available receive registers that the Host can 2010 * program. SHRA[0-10] are the shared receive address registers 2011 * that are shared between the Host and manageability engine (ME). 2012 * ME can reserve any number of addresses and the host needs to be 2013 * able to tell how many available registers it has access to. 2014 **/ 2015 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 2016 { 2017 u32 wlock_mac; 2018 u32 num_entries; 2019 2020 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2021 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2022 2023 switch (wlock_mac) { 2024 case 0: 2025 /* All SHRA[0..10] and RAR[0] available */ 2026 num_entries = hw->mac.rar_entry_count; 2027 break; 2028 case 1: 2029 /* Only RAR[0] available */ 2030 num_entries = 1; 2031 break; 2032 default: 2033 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 2034 num_entries = wlock_mac + 1; 2035 break; 2036 } 2037 2038 return num_entries; 2039 } 2040 2041 /** 2042 * e1000_rar_set_pch_lpt - Set receive address registers 2043 * @hw: pointer to the HW structure 2044 * @addr: pointer to the receive address 2045 * @index: receive address array register 2046 * 2047 * Sets the receive address register array at index to the address passed 2048 * in by addr. For LPT, RAR[0] is the base address register that is to 2049 * contain the MAC address. SHRA[0-10] are the shared receive address 2050 * registers that are shared between the Host and manageability engine (ME). 2051 **/ 2052 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 2053 { 2054 u32 rar_low, rar_high; 2055 u32 wlock_mac; 2056 2057 /* HW expects these in little endian so we reverse the byte order 2058 * from network order (big endian) to little endian 2059 */ 2060 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 2061 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 2062 2063 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 2064 2065 /* If MAC address zero, no need to set the AV bit */ 2066 if (rar_low || rar_high) 2067 rar_high |= E1000_RAH_AV; 2068 2069 if (index == 0) { 2070 ew32(RAL(index), rar_low); 2071 e1e_flush(); 2072 ew32(RAH(index), rar_high); 2073 e1e_flush(); 2074 return 0; 2075 } 2076 2077 /* The manageability engine (ME) can lock certain SHRAR registers that 2078 * it is using - those registers are unavailable for use. 2079 */ 2080 if (index < hw->mac.rar_entry_count) { 2081 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2082 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2083 2084 /* Check if all SHRAR registers are locked */ 2085 if (wlock_mac == 1) 2086 goto out; 2087 2088 if ((wlock_mac == 0) || (index <= wlock_mac)) { 2089 s32 ret_val; 2090 2091 ret_val = e1000_acquire_swflag_ich8lan(hw); 2092 2093 if (ret_val) 2094 goto out; 2095 2096 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 2097 e1e_flush(); 2098 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 2099 e1e_flush(); 2100 2101 e1000_release_swflag_ich8lan(hw); 2102 2103 /* verify the register updates */ 2104 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 2105 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 2106 return 0; 2107 } 2108 } 2109 2110 out: 2111 e_dbg("Failed to write receive address at index %d\n", index); 2112 return -E1000_ERR_CONFIG; 2113 } 2114 2115 /** 2116 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2117 * @hw: pointer to the HW structure 2118 * 2119 * Checks if firmware is blocking the reset of the PHY. 2120 * This is a function pointer entry point only called by 2121 * reset routines. 2122 **/ 2123 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2124 { 2125 bool blocked = false; 2126 int i = 0; 2127 2128 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2129 (i++ < 30)) 2130 usleep_range(10000, 11000); 2131 return blocked ? E1000_BLK_PHY_RESET : 0; 2132 } 2133 2134 /** 2135 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2136 * @hw: pointer to the HW structure 2137 * 2138 * Assumes semaphore already acquired. 2139 * 2140 **/ 2141 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2142 { 2143 u16 phy_data; 2144 u32 strap = er32(STRAP); 2145 u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap); 2146 s32 ret_val; 2147 2148 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2149 2150 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2151 if (ret_val) 2152 return ret_val; 2153 2154 phy_data &= ~HV_SMB_ADDR_MASK; 2155 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2156 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2157 2158 if (hw->phy.type == e1000_phy_i217) { 2159 /* Restore SMBus frequency */ 2160 if (freq--) { 2161 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2162 phy_data |= (freq & BIT(0)) << 2163 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2164 phy_data |= (freq & BIT(1)) << 2165 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2166 } else { 2167 e_dbg("Unsupported SMB frequency in PHY\n"); 2168 } 2169 } 2170 2171 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2172 } 2173 2174 /** 2175 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2176 * @hw: pointer to the HW structure 2177 * 2178 * SW should configure the LCD from the NVM extended configuration region 2179 * as a workaround for certain parts. 2180 **/ 2181 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2182 { 2183 struct e1000_phy_info *phy = &hw->phy; 2184 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2185 s32 ret_val = 0; 2186 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2187 2188 /* Initialize the PHY from the NVM on ICH platforms. This 2189 * is needed due to an issue where the NVM configuration is 2190 * not properly autoloaded after power transitions. 2191 * Therefore, after each PHY reset, we will load the 2192 * configuration data out of the NVM manually. 2193 */ 2194 switch (hw->mac.type) { 2195 case e1000_ich8lan: 2196 if (phy->type != e1000_phy_igp_3) 2197 return ret_val; 2198 2199 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2200 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2201 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2202 break; 2203 } 2204 fallthrough; 2205 case e1000_pchlan: 2206 case e1000_pch2lan: 2207 case e1000_pch_lpt: 2208 case e1000_pch_spt: 2209 case e1000_pch_cnp: 2210 case e1000_pch_tgp: 2211 case e1000_pch_adp: 2212 case e1000_pch_mtp: 2213 case e1000_pch_lnp: 2214 case e1000_pch_ptp: 2215 case e1000_pch_nvp: 2216 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2217 break; 2218 default: 2219 return ret_val; 2220 } 2221 2222 ret_val = hw->phy.ops.acquire(hw); 2223 if (ret_val) 2224 return ret_val; 2225 2226 data = er32(FEXTNVM); 2227 if (!(data & sw_cfg_mask)) 2228 goto release; 2229 2230 /* Make sure HW does not configure LCD from PHY 2231 * extended configuration before SW configuration 2232 */ 2233 data = er32(EXTCNF_CTRL); 2234 if ((hw->mac.type < e1000_pch2lan) && 2235 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2236 goto release; 2237 2238 cnf_size = er32(EXTCNF_SIZE); 2239 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2240 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2241 if (!cnf_size) 2242 goto release; 2243 2244 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2245 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2246 2247 if (((hw->mac.type == e1000_pchlan) && 2248 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2249 (hw->mac.type > e1000_pchlan)) { 2250 /* HW configures the SMBus address and LEDs when the 2251 * OEM and LCD Write Enable bits are set in the NVM. 2252 * When both NVM bits are cleared, SW will configure 2253 * them instead. 2254 */ 2255 ret_val = e1000_write_smbus_addr(hw); 2256 if (ret_val) 2257 goto release; 2258 2259 data = er32(LEDCTL); 2260 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2261 (u16)data); 2262 if (ret_val) 2263 goto release; 2264 } 2265 2266 /* Configure LCD from extended configuration region. */ 2267 2268 /* cnf_base_addr is in DWORD */ 2269 word_addr = (u16)(cnf_base_addr << 1); 2270 2271 for (i = 0; i < cnf_size; i++) { 2272 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2273 if (ret_val) 2274 goto release; 2275 2276 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2277 1, ®_addr); 2278 if (ret_val) 2279 goto release; 2280 2281 /* Save off the PHY page for future writes. */ 2282 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2283 phy_page = reg_data; 2284 continue; 2285 } 2286 2287 reg_addr &= PHY_REG_MASK; 2288 reg_addr |= phy_page; 2289 2290 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2291 if (ret_val) 2292 goto release; 2293 } 2294 2295 release: 2296 hw->phy.ops.release(hw); 2297 return ret_val; 2298 } 2299 2300 /** 2301 * e1000_k1_gig_workaround_hv - K1 Si workaround 2302 * @hw: pointer to the HW structure 2303 * @link: link up bool flag 2304 * 2305 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2306 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2307 * If link is down, the function will restore the default K1 setting located 2308 * in the NVM. 2309 **/ 2310 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2311 { 2312 s32 ret_val = 0; 2313 u16 status_reg = 0; 2314 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2315 2316 if (hw->mac.type != e1000_pchlan) 2317 return 0; 2318 2319 /* Wrap the whole flow with the sw flag */ 2320 ret_val = hw->phy.ops.acquire(hw); 2321 if (ret_val) 2322 return ret_val; 2323 2324 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2325 if (link) { 2326 if (hw->phy.type == e1000_phy_82578) { 2327 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2328 &status_reg); 2329 if (ret_val) 2330 goto release; 2331 2332 status_reg &= (BM_CS_STATUS_LINK_UP | 2333 BM_CS_STATUS_RESOLVED | 2334 BM_CS_STATUS_SPEED_MASK); 2335 2336 if (status_reg == (BM_CS_STATUS_LINK_UP | 2337 BM_CS_STATUS_RESOLVED | 2338 BM_CS_STATUS_SPEED_1000)) 2339 k1_enable = false; 2340 } 2341 2342 if (hw->phy.type == e1000_phy_82577) { 2343 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2344 if (ret_val) 2345 goto release; 2346 2347 status_reg &= (HV_M_STATUS_LINK_UP | 2348 HV_M_STATUS_AUTONEG_COMPLETE | 2349 HV_M_STATUS_SPEED_MASK); 2350 2351 if (status_reg == (HV_M_STATUS_LINK_UP | 2352 HV_M_STATUS_AUTONEG_COMPLETE | 2353 HV_M_STATUS_SPEED_1000)) 2354 k1_enable = false; 2355 } 2356 2357 /* Link stall fix for link up */ 2358 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2359 if (ret_val) 2360 goto release; 2361 2362 } else { 2363 /* Link stall fix for link down */ 2364 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2365 if (ret_val) 2366 goto release; 2367 } 2368 2369 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2370 2371 release: 2372 hw->phy.ops.release(hw); 2373 2374 return ret_val; 2375 } 2376 2377 /** 2378 * e1000_configure_k1_ich8lan - Configure K1 power state 2379 * @hw: pointer to the HW structure 2380 * @k1_enable: K1 state to configure 2381 * 2382 * Configure the K1 power state based on the provided parameter. 2383 * Assumes semaphore already acquired. 2384 * 2385 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2386 **/ 2387 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2388 { 2389 s32 ret_val; 2390 u32 ctrl_reg = 0; 2391 u32 ctrl_ext = 0; 2392 u32 reg = 0; 2393 u16 kmrn_reg = 0; 2394 2395 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2396 &kmrn_reg); 2397 if (ret_val) 2398 return ret_val; 2399 2400 if (k1_enable) 2401 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2402 else 2403 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2404 2405 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2406 kmrn_reg); 2407 if (ret_val) 2408 return ret_val; 2409 2410 usleep_range(20, 40); 2411 ctrl_ext = er32(CTRL_EXT); 2412 ctrl_reg = er32(CTRL); 2413 2414 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2415 reg |= E1000_CTRL_FRCSPD; 2416 ew32(CTRL, reg); 2417 2418 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2419 e1e_flush(); 2420 usleep_range(20, 40); 2421 ew32(CTRL, ctrl_reg); 2422 ew32(CTRL_EXT, ctrl_ext); 2423 e1e_flush(); 2424 usleep_range(20, 40); 2425 2426 return 0; 2427 } 2428 2429 /** 2430 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2431 * @hw: pointer to the HW structure 2432 * @d0_state: boolean if entering d0 or d3 device state 2433 * 2434 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2435 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2436 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2437 **/ 2438 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2439 { 2440 s32 ret_val = 0; 2441 u32 mac_reg; 2442 u16 oem_reg; 2443 2444 if (hw->mac.type < e1000_pchlan) 2445 return ret_val; 2446 2447 ret_val = hw->phy.ops.acquire(hw); 2448 if (ret_val) 2449 return ret_val; 2450 2451 if (hw->mac.type == e1000_pchlan) { 2452 mac_reg = er32(EXTCNF_CTRL); 2453 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2454 goto release; 2455 } 2456 2457 mac_reg = er32(FEXTNVM); 2458 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2459 goto release; 2460 2461 mac_reg = er32(PHY_CTRL); 2462 2463 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2464 if (ret_val) 2465 goto release; 2466 2467 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2468 2469 if (d0_state) { 2470 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2471 oem_reg |= HV_OEM_BITS_GBE_DIS; 2472 2473 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2474 oem_reg |= HV_OEM_BITS_LPLU; 2475 } else { 2476 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2477 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2478 oem_reg |= HV_OEM_BITS_GBE_DIS; 2479 2480 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2481 E1000_PHY_CTRL_NOND0A_LPLU)) 2482 oem_reg |= HV_OEM_BITS_LPLU; 2483 } 2484 2485 /* Set Restart auto-neg to activate the bits */ 2486 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2487 !hw->phy.ops.check_reset_block(hw)) 2488 oem_reg |= HV_OEM_BITS_RESTART_AN; 2489 2490 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2491 2492 release: 2493 hw->phy.ops.release(hw); 2494 2495 return ret_val; 2496 } 2497 2498 /** 2499 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2500 * @hw: pointer to the HW structure 2501 **/ 2502 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2503 { 2504 s32 ret_val; 2505 u16 data; 2506 2507 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2508 if (ret_val) 2509 return ret_val; 2510 2511 data |= HV_KMRN_MDIO_SLOW; 2512 2513 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2514 2515 return ret_val; 2516 } 2517 2518 /** 2519 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds 2520 * @hw: pointer to the HW structure 2521 * 2522 * A series of PHY workarounds to be done after every PHY reset. 2523 **/ 2524 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2525 { 2526 s32 ret_val = 0; 2527 u16 phy_data; 2528 2529 if (hw->mac.type != e1000_pchlan) 2530 return 0; 2531 2532 /* Set MDIO slow mode before any other MDIO access */ 2533 if (hw->phy.type == e1000_phy_82577) { 2534 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2535 if (ret_val) 2536 return ret_val; 2537 } 2538 2539 if (((hw->phy.type == e1000_phy_82577) && 2540 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2541 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2542 /* Disable generation of early preamble */ 2543 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2544 if (ret_val) 2545 return ret_val; 2546 2547 /* Preamble tuning for SSC */ 2548 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2549 if (ret_val) 2550 return ret_val; 2551 } 2552 2553 if (hw->phy.type == e1000_phy_82578) { 2554 /* Return registers to default by doing a soft reset then 2555 * writing 0x3140 to the control register. 2556 */ 2557 if (hw->phy.revision < 2) { 2558 e1000e_phy_sw_reset(hw); 2559 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2560 if (ret_val) 2561 return ret_val; 2562 } 2563 } 2564 2565 /* Select page 0 */ 2566 ret_val = hw->phy.ops.acquire(hw); 2567 if (ret_val) 2568 return ret_val; 2569 2570 hw->phy.addr = 1; 2571 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2572 hw->phy.ops.release(hw); 2573 if (ret_val) 2574 return ret_val; 2575 2576 /* Configure the K1 Si workaround during phy reset assuming there is 2577 * link so that it disables K1 if link is in 1Gbps. 2578 */ 2579 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2580 if (ret_val) 2581 return ret_val; 2582 2583 /* Workaround for link disconnects on a busy hub in half duplex */ 2584 ret_val = hw->phy.ops.acquire(hw); 2585 if (ret_val) 2586 return ret_val; 2587 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2588 if (ret_val) 2589 goto release; 2590 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2591 if (ret_val) 2592 goto release; 2593 2594 /* set MSE higher to enable link to stay up when noise is high */ 2595 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2596 release: 2597 hw->phy.ops.release(hw); 2598 2599 return ret_val; 2600 } 2601 2602 /** 2603 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2604 * @hw: pointer to the HW structure 2605 **/ 2606 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2607 { 2608 u32 mac_reg; 2609 u16 i, phy_reg = 0; 2610 s32 ret_val; 2611 2612 ret_val = hw->phy.ops.acquire(hw); 2613 if (ret_val) 2614 return; 2615 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2616 if (ret_val) 2617 goto release; 2618 2619 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2620 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2621 mac_reg = er32(RAL(i)); 2622 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2623 (u16)(mac_reg & 0xFFFF)); 2624 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2625 (u16)((mac_reg >> 16) & 0xFFFF)); 2626 2627 mac_reg = er32(RAH(i)); 2628 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2629 (u16)(mac_reg & 0xFFFF)); 2630 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2631 (u16)((mac_reg & E1000_RAH_AV) >> 16)); 2632 } 2633 2634 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2635 2636 release: 2637 hw->phy.ops.release(hw); 2638 } 2639 2640 /** 2641 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2642 * with 82579 PHY 2643 * @hw: pointer to the HW structure 2644 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2645 **/ 2646 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2647 { 2648 s32 ret_val = 0; 2649 u16 phy_reg, data; 2650 u32 mac_reg; 2651 u16 i; 2652 2653 if (hw->mac.type < e1000_pch2lan) 2654 return 0; 2655 2656 /* disable Rx path while enabling/disabling workaround */ 2657 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2658 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2659 if (ret_val) 2660 return ret_val; 2661 2662 if (enable) { 2663 /* Write Rx addresses (rar_entry_count for RAL/H, and 2664 * SHRAL/H) and initial CRC values to the MAC 2665 */ 2666 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2667 u8 mac_addr[ETH_ALEN] = { 0 }; 2668 u32 addr_high, addr_low; 2669 2670 addr_high = er32(RAH(i)); 2671 if (!(addr_high & E1000_RAH_AV)) 2672 continue; 2673 addr_low = er32(RAL(i)); 2674 mac_addr[0] = (addr_low & 0xFF); 2675 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2676 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2677 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2678 mac_addr[4] = (addr_high & 0xFF); 2679 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2680 2681 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2682 } 2683 2684 /* Write Rx addresses to the PHY */ 2685 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2686 2687 /* Enable jumbo frame workaround in the MAC */ 2688 mac_reg = er32(FFLT_DBG); 2689 mac_reg &= ~BIT(14); 2690 mac_reg |= (7 << 15); 2691 ew32(FFLT_DBG, mac_reg); 2692 2693 mac_reg = er32(RCTL); 2694 mac_reg |= E1000_RCTL_SECRC; 2695 ew32(RCTL, mac_reg); 2696 2697 ret_val = e1000e_read_kmrn_reg(hw, 2698 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2699 &data); 2700 if (ret_val) 2701 return ret_val; 2702 ret_val = e1000e_write_kmrn_reg(hw, 2703 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2704 data | BIT(0)); 2705 if (ret_val) 2706 return ret_val; 2707 ret_val = e1000e_read_kmrn_reg(hw, 2708 E1000_KMRNCTRLSTA_HD_CTRL, 2709 &data); 2710 if (ret_val) 2711 return ret_val; 2712 data &= ~(0xF << 8); 2713 data |= (0xB << 8); 2714 ret_val = e1000e_write_kmrn_reg(hw, 2715 E1000_KMRNCTRLSTA_HD_CTRL, 2716 data); 2717 if (ret_val) 2718 return ret_val; 2719 2720 /* Enable jumbo frame workaround in the PHY */ 2721 e1e_rphy(hw, PHY_REG(769, 23), &data); 2722 data &= ~(0x7F << 5); 2723 data |= (0x37 << 5); 2724 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2725 if (ret_val) 2726 return ret_val; 2727 e1e_rphy(hw, PHY_REG(769, 16), &data); 2728 data &= ~BIT(13); 2729 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2730 if (ret_val) 2731 return ret_val; 2732 e1e_rphy(hw, PHY_REG(776, 20), &data); 2733 data &= ~(0x3FF << 2); 2734 data |= (E1000_TX_PTR_GAP << 2); 2735 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2736 if (ret_val) 2737 return ret_val; 2738 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2739 if (ret_val) 2740 return ret_val; 2741 e1e_rphy(hw, HV_PM_CTRL, &data); 2742 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2743 if (ret_val) 2744 return ret_val; 2745 } else { 2746 /* Write MAC register values back to h/w defaults */ 2747 mac_reg = er32(FFLT_DBG); 2748 mac_reg &= ~(0xF << 14); 2749 ew32(FFLT_DBG, mac_reg); 2750 2751 mac_reg = er32(RCTL); 2752 mac_reg &= ~E1000_RCTL_SECRC; 2753 ew32(RCTL, mac_reg); 2754 2755 ret_val = e1000e_read_kmrn_reg(hw, 2756 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2757 &data); 2758 if (ret_val) 2759 return ret_val; 2760 ret_val = e1000e_write_kmrn_reg(hw, 2761 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2762 data & ~BIT(0)); 2763 if (ret_val) 2764 return ret_val; 2765 ret_val = e1000e_read_kmrn_reg(hw, 2766 E1000_KMRNCTRLSTA_HD_CTRL, 2767 &data); 2768 if (ret_val) 2769 return ret_val; 2770 data &= ~(0xF << 8); 2771 data |= (0xB << 8); 2772 ret_val = e1000e_write_kmrn_reg(hw, 2773 E1000_KMRNCTRLSTA_HD_CTRL, 2774 data); 2775 if (ret_val) 2776 return ret_val; 2777 2778 /* Write PHY register values back to h/w defaults */ 2779 e1e_rphy(hw, PHY_REG(769, 23), &data); 2780 data &= ~(0x7F << 5); 2781 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2782 if (ret_val) 2783 return ret_val; 2784 e1e_rphy(hw, PHY_REG(769, 16), &data); 2785 data |= BIT(13); 2786 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2787 if (ret_val) 2788 return ret_val; 2789 e1e_rphy(hw, PHY_REG(776, 20), &data); 2790 data &= ~(0x3FF << 2); 2791 data |= (0x8 << 2); 2792 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2793 if (ret_val) 2794 return ret_val; 2795 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2796 if (ret_val) 2797 return ret_val; 2798 e1e_rphy(hw, HV_PM_CTRL, &data); 2799 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2800 if (ret_val) 2801 return ret_val; 2802 } 2803 2804 /* re-enable Rx path after enabling/disabling workaround */ 2805 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2806 } 2807 2808 /** 2809 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds 2810 * @hw: pointer to the HW structure 2811 * 2812 * A series of PHY workarounds to be done after every PHY reset. 2813 **/ 2814 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2815 { 2816 s32 ret_val = 0; 2817 2818 if (hw->mac.type != e1000_pch2lan) 2819 return 0; 2820 2821 /* Set MDIO slow mode before any other MDIO access */ 2822 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2823 if (ret_val) 2824 return ret_val; 2825 2826 ret_val = hw->phy.ops.acquire(hw); 2827 if (ret_val) 2828 return ret_val; 2829 /* set MSE higher to enable link to stay up when noise is high */ 2830 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2831 if (ret_val) 2832 goto release; 2833 /* drop link after 5 times MSE threshold was reached */ 2834 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2835 release: 2836 hw->phy.ops.release(hw); 2837 2838 return ret_val; 2839 } 2840 2841 /** 2842 * e1000_k1_workaround_lv - K1 Si workaround 2843 * @hw: pointer to the HW structure 2844 * 2845 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2846 * Disable K1 in 1000Mbps and 100Mbps 2847 **/ 2848 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2849 { 2850 s32 ret_val = 0; 2851 u16 status_reg = 0; 2852 2853 if (hw->mac.type != e1000_pch2lan) 2854 return 0; 2855 2856 /* Set K1 beacon duration based on 10Mbs speed */ 2857 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2858 if (ret_val) 2859 return ret_val; 2860 2861 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2862 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2863 if (status_reg & 2864 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2865 u16 pm_phy_reg; 2866 2867 /* LV 1G/100 Packet drop issue wa */ 2868 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2869 if (ret_val) 2870 return ret_val; 2871 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2872 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2873 if (ret_val) 2874 return ret_val; 2875 } else { 2876 u32 mac_reg; 2877 2878 mac_reg = er32(FEXTNVM4); 2879 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2880 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2881 ew32(FEXTNVM4, mac_reg); 2882 } 2883 } 2884 2885 return ret_val; 2886 } 2887 2888 /** 2889 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2890 * @hw: pointer to the HW structure 2891 * @gate: boolean set to true to gate, false to ungate 2892 * 2893 * Gate/ungate the automatic PHY configuration via hardware; perform 2894 * the configuration via software instead. 2895 **/ 2896 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2897 { 2898 u32 extcnf_ctrl; 2899 2900 if (hw->mac.type < e1000_pch2lan) 2901 return; 2902 2903 extcnf_ctrl = er32(EXTCNF_CTRL); 2904 2905 if (gate) 2906 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2907 else 2908 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2909 2910 ew32(EXTCNF_CTRL, extcnf_ctrl); 2911 } 2912 2913 /** 2914 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2915 * @hw: pointer to the HW structure 2916 * 2917 * Check the appropriate indication the MAC has finished configuring the 2918 * PHY after a software reset. 2919 **/ 2920 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2921 { 2922 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2923 2924 /* Wait for basic configuration completes before proceeding */ 2925 do { 2926 data = er32(STATUS); 2927 data &= E1000_STATUS_LAN_INIT_DONE; 2928 usleep_range(100, 200); 2929 } while ((!data) && --loop); 2930 2931 /* If basic configuration is incomplete before the above loop 2932 * count reaches 0, loading the configuration from NVM will 2933 * leave the PHY in a bad state possibly resulting in no link. 2934 */ 2935 if (loop == 0) 2936 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2937 2938 /* Clear the Init Done bit for the next init event */ 2939 data = er32(STATUS); 2940 data &= ~E1000_STATUS_LAN_INIT_DONE; 2941 ew32(STATUS, data); 2942 } 2943 2944 /** 2945 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2946 * @hw: pointer to the HW structure 2947 **/ 2948 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2949 { 2950 s32 ret_val = 0; 2951 u16 reg; 2952 2953 if (hw->phy.ops.check_reset_block(hw)) 2954 return 0; 2955 2956 /* Allow time for h/w to get to quiescent state after reset */ 2957 usleep_range(10000, 11000); 2958 2959 /* Perform any necessary post-reset workarounds */ 2960 switch (hw->mac.type) { 2961 case e1000_pchlan: 2962 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2963 if (ret_val) 2964 return ret_val; 2965 break; 2966 case e1000_pch2lan: 2967 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2968 if (ret_val) 2969 return ret_val; 2970 break; 2971 default: 2972 break; 2973 } 2974 2975 /* Clear the host wakeup bit after lcd reset */ 2976 if (hw->mac.type >= e1000_pchlan) { 2977 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2978 reg &= ~BM_WUC_HOST_WU_BIT; 2979 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2980 } 2981 2982 /* Configure the LCD with the extended configuration region in NVM */ 2983 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2984 if (ret_val) 2985 return ret_val; 2986 2987 /* Configure the LCD with the OEM bits in NVM */ 2988 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2989 2990 if (hw->mac.type == e1000_pch2lan) { 2991 /* Ungate automatic PHY configuration on non-managed 82579 */ 2992 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2993 usleep_range(10000, 11000); 2994 e1000_gate_hw_phy_config_ich8lan(hw, false); 2995 } 2996 2997 /* Set EEE LPI Update Timer to 200usec */ 2998 ret_val = hw->phy.ops.acquire(hw); 2999 if (ret_val) 3000 return ret_val; 3001 ret_val = e1000_write_emi_reg_locked(hw, 3002 I82579_LPI_UPDATE_TIMER, 3003 0x1387); 3004 hw->phy.ops.release(hw); 3005 } 3006 3007 return ret_val; 3008 } 3009 3010 /** 3011 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 3012 * @hw: pointer to the HW structure 3013 * 3014 * Resets the PHY 3015 * This is a function pointer entry point called by drivers 3016 * or other shared routines. 3017 **/ 3018 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 3019 { 3020 s32 ret_val = 0; 3021 3022 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 3023 if ((hw->mac.type == e1000_pch2lan) && 3024 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 3025 e1000_gate_hw_phy_config_ich8lan(hw, true); 3026 3027 ret_val = e1000e_phy_hw_reset_generic(hw); 3028 if (ret_val) 3029 return ret_val; 3030 3031 return e1000_post_phy_reset_ich8lan(hw); 3032 } 3033 3034 /** 3035 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 3036 * @hw: pointer to the HW structure 3037 * @active: true to enable LPLU, false to disable 3038 * 3039 * Sets the LPLU state according to the active flag. For PCH, if OEM write 3040 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 3041 * the phy speed. This function will manually set the LPLU bit and restart 3042 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 3043 * since it configures the same bit. 3044 **/ 3045 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 3046 { 3047 s32 ret_val; 3048 u16 oem_reg; 3049 3050 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 3051 if (ret_val) 3052 return ret_val; 3053 3054 if (active) 3055 oem_reg |= HV_OEM_BITS_LPLU; 3056 else 3057 oem_reg &= ~HV_OEM_BITS_LPLU; 3058 3059 if (!hw->phy.ops.check_reset_block(hw)) 3060 oem_reg |= HV_OEM_BITS_RESTART_AN; 3061 3062 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 3063 } 3064 3065 /** 3066 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 3067 * @hw: pointer to the HW structure 3068 * @active: true to enable LPLU, false to disable 3069 * 3070 * Sets the LPLU D0 state according to the active flag. When 3071 * activating LPLU this function also disables smart speed 3072 * and vice versa. LPLU will not be activated unless the 3073 * device autonegotiation advertisement meets standards of 3074 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3075 * This is a function pointer entry point only called by 3076 * PHY setup routines. 3077 **/ 3078 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3079 { 3080 struct e1000_phy_info *phy = &hw->phy; 3081 u32 phy_ctrl; 3082 s32 ret_val = 0; 3083 u16 data; 3084 3085 if (phy->type == e1000_phy_ife) 3086 return 0; 3087 3088 phy_ctrl = er32(PHY_CTRL); 3089 3090 if (active) { 3091 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3092 ew32(PHY_CTRL, phy_ctrl); 3093 3094 if (phy->type != e1000_phy_igp_3) 3095 return 0; 3096 3097 /* Call gig speed drop workaround on LPLU before accessing 3098 * any PHY registers 3099 */ 3100 if (hw->mac.type == e1000_ich8lan) 3101 e1000e_gig_downshift_workaround_ich8lan(hw); 3102 3103 /* When LPLU is enabled, we should disable SmartSpeed */ 3104 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3105 if (ret_val) 3106 return ret_val; 3107 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3108 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3109 if (ret_val) 3110 return ret_val; 3111 } else { 3112 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3113 ew32(PHY_CTRL, phy_ctrl); 3114 3115 if (phy->type != e1000_phy_igp_3) 3116 return 0; 3117 3118 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3119 * during Dx states where the power conservation is most 3120 * important. During driver activity we should enable 3121 * SmartSpeed, so performance is maintained. 3122 */ 3123 if (phy->smart_speed == e1000_smart_speed_on) { 3124 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3125 &data); 3126 if (ret_val) 3127 return ret_val; 3128 3129 data |= IGP01E1000_PSCFR_SMART_SPEED; 3130 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3131 data); 3132 if (ret_val) 3133 return ret_val; 3134 } else if (phy->smart_speed == e1000_smart_speed_off) { 3135 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3136 &data); 3137 if (ret_val) 3138 return ret_val; 3139 3140 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3141 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3142 data); 3143 if (ret_val) 3144 return ret_val; 3145 } 3146 } 3147 3148 return 0; 3149 } 3150 3151 /** 3152 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3153 * @hw: pointer to the HW structure 3154 * @active: true to enable LPLU, false to disable 3155 * 3156 * Sets the LPLU D3 state according to the active flag. When 3157 * activating LPLU this function also disables smart speed 3158 * and vice versa. LPLU will not be activated unless the 3159 * device autonegotiation advertisement meets standards of 3160 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3161 * This is a function pointer entry point only called by 3162 * PHY setup routines. 3163 **/ 3164 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3165 { 3166 struct e1000_phy_info *phy = &hw->phy; 3167 u32 phy_ctrl; 3168 s32 ret_val = 0; 3169 u16 data; 3170 3171 phy_ctrl = er32(PHY_CTRL); 3172 3173 if (!active) { 3174 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3175 ew32(PHY_CTRL, phy_ctrl); 3176 3177 if (phy->type != e1000_phy_igp_3) 3178 return 0; 3179 3180 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3181 * during Dx states where the power conservation is most 3182 * important. During driver activity we should enable 3183 * SmartSpeed, so performance is maintained. 3184 */ 3185 if (phy->smart_speed == e1000_smart_speed_on) { 3186 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3187 &data); 3188 if (ret_val) 3189 return ret_val; 3190 3191 data |= IGP01E1000_PSCFR_SMART_SPEED; 3192 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3193 data); 3194 if (ret_val) 3195 return ret_val; 3196 } else if (phy->smart_speed == e1000_smart_speed_off) { 3197 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3198 &data); 3199 if (ret_val) 3200 return ret_val; 3201 3202 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3203 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3204 data); 3205 if (ret_val) 3206 return ret_val; 3207 } 3208 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3209 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3210 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3211 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3212 ew32(PHY_CTRL, phy_ctrl); 3213 3214 if (phy->type != e1000_phy_igp_3) 3215 return 0; 3216 3217 /* Call gig speed drop workaround on LPLU before accessing 3218 * any PHY registers 3219 */ 3220 if (hw->mac.type == e1000_ich8lan) 3221 e1000e_gig_downshift_workaround_ich8lan(hw); 3222 3223 /* When LPLU is enabled, we should disable SmartSpeed */ 3224 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3225 if (ret_val) 3226 return ret_val; 3227 3228 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3229 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3230 } 3231 3232 return ret_val; 3233 } 3234 3235 /** 3236 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3237 * @hw: pointer to the HW structure 3238 * @bank: pointer to the variable that returns the active bank 3239 * 3240 * Reads signature byte from the NVM using the flash access registers. 3241 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3242 **/ 3243 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3244 { 3245 u32 eecd; 3246 struct e1000_nvm_info *nvm = &hw->nvm; 3247 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3248 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3249 u32 nvm_dword = 0; 3250 u8 sig_byte = 0; 3251 s32 ret_val; 3252 3253 switch (hw->mac.type) { 3254 case e1000_pch_spt: 3255 case e1000_pch_cnp: 3256 case e1000_pch_tgp: 3257 case e1000_pch_adp: 3258 case e1000_pch_mtp: 3259 case e1000_pch_lnp: 3260 case e1000_pch_ptp: 3261 case e1000_pch_nvp: 3262 bank1_offset = nvm->flash_bank_size; 3263 act_offset = E1000_ICH_NVM_SIG_WORD; 3264 3265 /* set bank to 0 in case flash read fails */ 3266 *bank = 0; 3267 3268 /* Check bank 0 */ 3269 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3270 &nvm_dword); 3271 if (ret_val) 3272 return ret_val; 3273 sig_byte = FIELD_GET(0xFF00, nvm_dword); 3274 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3275 E1000_ICH_NVM_SIG_VALUE) { 3276 *bank = 0; 3277 return 0; 3278 } 3279 3280 /* Check bank 1 */ 3281 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3282 bank1_offset, 3283 &nvm_dword); 3284 if (ret_val) 3285 return ret_val; 3286 sig_byte = FIELD_GET(0xFF00, nvm_dword); 3287 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3288 E1000_ICH_NVM_SIG_VALUE) { 3289 *bank = 1; 3290 return 0; 3291 } 3292 3293 e_dbg("ERROR: No valid NVM bank present\n"); 3294 return -E1000_ERR_NVM; 3295 case e1000_ich8lan: 3296 case e1000_ich9lan: 3297 eecd = er32(EECD); 3298 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3299 E1000_EECD_SEC1VAL_VALID_MASK) { 3300 if (eecd & E1000_EECD_SEC1VAL) 3301 *bank = 1; 3302 else 3303 *bank = 0; 3304 3305 return 0; 3306 } 3307 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3308 fallthrough; 3309 default: 3310 /* set bank to 0 in case flash read fails */ 3311 *bank = 0; 3312 3313 /* Check bank 0 */ 3314 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3315 &sig_byte); 3316 if (ret_val) 3317 return ret_val; 3318 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3319 E1000_ICH_NVM_SIG_VALUE) { 3320 *bank = 0; 3321 return 0; 3322 } 3323 3324 /* Check bank 1 */ 3325 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3326 bank1_offset, 3327 &sig_byte); 3328 if (ret_val) 3329 return ret_val; 3330 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3331 E1000_ICH_NVM_SIG_VALUE) { 3332 *bank = 1; 3333 return 0; 3334 } 3335 3336 e_dbg("ERROR: No valid NVM bank present\n"); 3337 return -E1000_ERR_NVM; 3338 } 3339 } 3340 3341 /** 3342 * e1000_read_nvm_spt - NVM access for SPT 3343 * @hw: pointer to the HW structure 3344 * @offset: The offset (in bytes) of the word(s) to read. 3345 * @words: Size of data to read in words. 3346 * @data: pointer to the word(s) to read at offset. 3347 * 3348 * Reads a word(s) from the NVM 3349 **/ 3350 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3351 u16 *data) 3352 { 3353 struct e1000_nvm_info *nvm = &hw->nvm; 3354 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3355 u32 act_offset; 3356 s32 ret_val = 0; 3357 u32 bank = 0; 3358 u32 dword = 0; 3359 u16 offset_to_read; 3360 u16 i; 3361 3362 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3363 (words == 0)) { 3364 e_dbg("nvm parameter(s) out of bounds\n"); 3365 ret_val = -E1000_ERR_NVM; 3366 goto out; 3367 } 3368 3369 nvm->ops.acquire(hw); 3370 3371 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3372 if (ret_val) { 3373 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3374 bank = 0; 3375 } 3376 3377 act_offset = (bank) ? nvm->flash_bank_size : 0; 3378 act_offset += offset; 3379 3380 ret_val = 0; 3381 3382 for (i = 0; i < words; i += 2) { 3383 if (words - i == 1) { 3384 if (dev_spec->shadow_ram[offset + i].modified) { 3385 data[i] = 3386 dev_spec->shadow_ram[offset + i].value; 3387 } else { 3388 offset_to_read = act_offset + i - 3389 ((act_offset + i) % 2); 3390 ret_val = 3391 e1000_read_flash_dword_ich8lan(hw, 3392 offset_to_read, 3393 &dword); 3394 if (ret_val) 3395 break; 3396 if ((act_offset + i) % 2 == 0) 3397 data[i] = (u16)(dword & 0xFFFF); 3398 else 3399 data[i] = (u16)((dword >> 16) & 0xFFFF); 3400 } 3401 } else { 3402 offset_to_read = act_offset + i; 3403 if (!(dev_spec->shadow_ram[offset + i].modified) || 3404 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3405 ret_val = 3406 e1000_read_flash_dword_ich8lan(hw, 3407 offset_to_read, 3408 &dword); 3409 if (ret_val) 3410 break; 3411 } 3412 if (dev_spec->shadow_ram[offset + i].modified) 3413 data[i] = 3414 dev_spec->shadow_ram[offset + i].value; 3415 else 3416 data[i] = (u16)(dword & 0xFFFF); 3417 if (dev_spec->shadow_ram[offset + i].modified) 3418 data[i + 1] = 3419 dev_spec->shadow_ram[offset + i + 1].value; 3420 else 3421 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3422 } 3423 } 3424 3425 nvm->ops.release(hw); 3426 3427 out: 3428 if (ret_val) 3429 e_dbg("NVM read error: %d\n", ret_val); 3430 3431 return ret_val; 3432 } 3433 3434 /** 3435 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3436 * @hw: pointer to the HW structure 3437 * @offset: The offset (in bytes) of the word(s) to read. 3438 * @words: Size of data to read in words 3439 * @data: Pointer to the word(s) to read at offset. 3440 * 3441 * Reads a word(s) from the NVM using the flash access registers. 3442 **/ 3443 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3444 u16 *data) 3445 { 3446 struct e1000_nvm_info *nvm = &hw->nvm; 3447 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3448 u32 act_offset; 3449 s32 ret_val = 0; 3450 u32 bank = 0; 3451 u16 i, word; 3452 3453 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3454 (words == 0)) { 3455 e_dbg("nvm parameter(s) out of bounds\n"); 3456 ret_val = -E1000_ERR_NVM; 3457 goto out; 3458 } 3459 3460 nvm->ops.acquire(hw); 3461 3462 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3463 if (ret_val) { 3464 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3465 bank = 0; 3466 } 3467 3468 act_offset = (bank) ? nvm->flash_bank_size : 0; 3469 act_offset += offset; 3470 3471 ret_val = 0; 3472 for (i = 0; i < words; i++) { 3473 if (dev_spec->shadow_ram[offset + i].modified) { 3474 data[i] = dev_spec->shadow_ram[offset + i].value; 3475 } else { 3476 ret_val = e1000_read_flash_word_ich8lan(hw, 3477 act_offset + i, 3478 &word); 3479 if (ret_val) 3480 break; 3481 data[i] = word; 3482 } 3483 } 3484 3485 nvm->ops.release(hw); 3486 3487 out: 3488 if (ret_val) 3489 e_dbg("NVM read error: %d\n", ret_val); 3490 3491 return ret_val; 3492 } 3493 3494 /** 3495 * e1000_flash_cycle_init_ich8lan - Initialize flash 3496 * @hw: pointer to the HW structure 3497 * 3498 * This function does initial flash setup so that a new read/write/erase cycle 3499 * can be started. 3500 **/ 3501 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3502 { 3503 union ich8_hws_flash_status hsfsts; 3504 s32 ret_val = -E1000_ERR_NVM; 3505 3506 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3507 3508 /* Check if the flash descriptor is valid */ 3509 if (!hsfsts.hsf_status.fldesvalid) { 3510 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3511 return -E1000_ERR_NVM; 3512 } 3513 3514 /* Clear FCERR and DAEL in hw status by writing 1 */ 3515 hsfsts.hsf_status.flcerr = 1; 3516 hsfsts.hsf_status.dael = 1; 3517 if (hw->mac.type >= e1000_pch_spt) 3518 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3519 else 3520 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3521 3522 /* Either we should have a hardware SPI cycle in progress 3523 * bit to check against, in order to start a new cycle or 3524 * FDONE bit should be changed in the hardware so that it 3525 * is 1 after hardware reset, which can then be used as an 3526 * indication whether a cycle is in progress or has been 3527 * completed. 3528 */ 3529 3530 if (!hsfsts.hsf_status.flcinprog) { 3531 /* There is no cycle running at present, 3532 * so we can start a cycle. 3533 * Begin by setting Flash Cycle Done. 3534 */ 3535 hsfsts.hsf_status.flcdone = 1; 3536 if (hw->mac.type >= e1000_pch_spt) 3537 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3538 else 3539 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3540 ret_val = 0; 3541 } else { 3542 s32 i; 3543 3544 /* Otherwise poll for sometime so the current 3545 * cycle has a chance to end before giving up. 3546 */ 3547 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3548 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3549 if (!hsfsts.hsf_status.flcinprog) { 3550 ret_val = 0; 3551 break; 3552 } 3553 udelay(1); 3554 } 3555 if (!ret_val) { 3556 /* Successful in waiting for previous cycle to timeout, 3557 * now set the Flash Cycle Done. 3558 */ 3559 hsfsts.hsf_status.flcdone = 1; 3560 if (hw->mac.type >= e1000_pch_spt) 3561 ew32flash(ICH_FLASH_HSFSTS, 3562 hsfsts.regval & 0xFFFF); 3563 else 3564 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3565 } else { 3566 e_dbg("Flash controller busy, cannot get access\n"); 3567 } 3568 } 3569 3570 return ret_val; 3571 } 3572 3573 /** 3574 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3575 * @hw: pointer to the HW structure 3576 * @timeout: maximum time to wait for completion 3577 * 3578 * This function starts a flash cycle and waits for its completion. 3579 **/ 3580 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3581 { 3582 union ich8_hws_flash_ctrl hsflctl; 3583 union ich8_hws_flash_status hsfsts; 3584 u32 i = 0; 3585 3586 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3587 if (hw->mac.type >= e1000_pch_spt) 3588 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3589 else 3590 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3591 hsflctl.hsf_ctrl.flcgo = 1; 3592 3593 if (hw->mac.type >= e1000_pch_spt) 3594 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3595 else 3596 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3597 3598 /* wait till FDONE bit is set to 1 */ 3599 do { 3600 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3601 if (hsfsts.hsf_status.flcdone) 3602 break; 3603 udelay(1); 3604 } while (i++ < timeout); 3605 3606 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3607 return 0; 3608 3609 return -E1000_ERR_NVM; 3610 } 3611 3612 /** 3613 * e1000_read_flash_dword_ich8lan - Read dword from flash 3614 * @hw: pointer to the HW structure 3615 * @offset: offset to data location 3616 * @data: pointer to the location for storing the data 3617 * 3618 * Reads the flash dword at offset into data. Offset is converted 3619 * to bytes before read. 3620 **/ 3621 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3622 u32 *data) 3623 { 3624 /* Must convert word offset into bytes. */ 3625 offset <<= 1; 3626 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3627 } 3628 3629 /** 3630 * e1000_read_flash_word_ich8lan - Read word from flash 3631 * @hw: pointer to the HW structure 3632 * @offset: offset to data location 3633 * @data: pointer to the location for storing the data 3634 * 3635 * Reads the flash word at offset into data. Offset is converted 3636 * to bytes before read. 3637 **/ 3638 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3639 u16 *data) 3640 { 3641 /* Must convert offset into bytes. */ 3642 offset <<= 1; 3643 3644 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3645 } 3646 3647 /** 3648 * e1000_read_flash_byte_ich8lan - Read byte from flash 3649 * @hw: pointer to the HW structure 3650 * @offset: The offset of the byte to read. 3651 * @data: Pointer to a byte to store the value read. 3652 * 3653 * Reads a single byte from the NVM using the flash access registers. 3654 **/ 3655 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3656 u8 *data) 3657 { 3658 s32 ret_val; 3659 u16 word = 0; 3660 3661 /* In SPT, only 32 bits access is supported, 3662 * so this function should not be called. 3663 */ 3664 if (hw->mac.type >= e1000_pch_spt) 3665 return -E1000_ERR_NVM; 3666 else 3667 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3668 3669 if (ret_val) 3670 return ret_val; 3671 3672 *data = (u8)word; 3673 3674 return 0; 3675 } 3676 3677 /** 3678 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3679 * @hw: pointer to the HW structure 3680 * @offset: The offset (in bytes) of the byte or word to read. 3681 * @size: Size of data to read, 1=byte 2=word 3682 * @data: Pointer to the word to store the value read. 3683 * 3684 * Reads a byte or word from the NVM using the flash access registers. 3685 **/ 3686 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3687 u8 size, u16 *data) 3688 { 3689 union ich8_hws_flash_status hsfsts; 3690 union ich8_hws_flash_ctrl hsflctl; 3691 u32 flash_linear_addr; 3692 u32 flash_data = 0; 3693 s32 ret_val = -E1000_ERR_NVM; 3694 u8 count = 0; 3695 3696 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3697 return -E1000_ERR_NVM; 3698 3699 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3700 hw->nvm.flash_base_addr); 3701 3702 do { 3703 udelay(1); 3704 /* Steps */ 3705 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3706 if (ret_val) 3707 break; 3708 3709 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3710 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3711 hsflctl.hsf_ctrl.fldbcount = size - 1; 3712 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3713 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3714 3715 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3716 3717 ret_val = 3718 e1000_flash_cycle_ich8lan(hw, 3719 ICH_FLASH_READ_COMMAND_TIMEOUT); 3720 3721 /* Check if FCERR is set to 1, if set to 1, clear it 3722 * and try the whole sequence a few more times, else 3723 * read in (shift in) the Flash Data0, the order is 3724 * least significant byte first msb to lsb 3725 */ 3726 if (!ret_val) { 3727 flash_data = er32flash(ICH_FLASH_FDATA0); 3728 if (size == 1) 3729 *data = (u8)(flash_data & 0x000000FF); 3730 else if (size == 2) 3731 *data = (u16)(flash_data & 0x0000FFFF); 3732 break; 3733 } else { 3734 /* If we've gotten here, then things are probably 3735 * completely hosed, but if the error condition is 3736 * detected, it won't hurt to give it another try... 3737 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3738 */ 3739 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3740 if (hsfsts.hsf_status.flcerr) { 3741 /* Repeat for some time before giving up. */ 3742 continue; 3743 } else if (!hsfsts.hsf_status.flcdone) { 3744 e_dbg("Timeout error - flash cycle did not complete.\n"); 3745 break; 3746 } 3747 } 3748 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3749 3750 return ret_val; 3751 } 3752 3753 /** 3754 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3755 * @hw: pointer to the HW structure 3756 * @offset: The offset (in bytes) of the dword to read. 3757 * @data: Pointer to the dword to store the value read. 3758 * 3759 * Reads a byte or word from the NVM using the flash access registers. 3760 **/ 3761 3762 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3763 u32 *data) 3764 { 3765 union ich8_hws_flash_status hsfsts; 3766 union ich8_hws_flash_ctrl hsflctl; 3767 u32 flash_linear_addr; 3768 s32 ret_val = -E1000_ERR_NVM; 3769 u8 count = 0; 3770 3771 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3772 return -E1000_ERR_NVM; 3773 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3774 hw->nvm.flash_base_addr); 3775 3776 do { 3777 udelay(1); 3778 /* Steps */ 3779 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3780 if (ret_val) 3781 break; 3782 /* In SPT, This register is in Lan memory space, not flash. 3783 * Therefore, only 32 bit access is supported 3784 */ 3785 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3786 3787 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3788 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3789 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3790 /* In SPT, This register is in Lan memory space, not flash. 3791 * Therefore, only 32 bit access is supported 3792 */ 3793 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3794 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3795 3796 ret_val = 3797 e1000_flash_cycle_ich8lan(hw, 3798 ICH_FLASH_READ_COMMAND_TIMEOUT); 3799 3800 /* Check if FCERR is set to 1, if set to 1, clear it 3801 * and try the whole sequence a few more times, else 3802 * read in (shift in) the Flash Data0, the order is 3803 * least significant byte first msb to lsb 3804 */ 3805 if (!ret_val) { 3806 *data = er32flash(ICH_FLASH_FDATA0); 3807 break; 3808 } else { 3809 /* If we've gotten here, then things are probably 3810 * completely hosed, but if the error condition is 3811 * detected, it won't hurt to give it another try... 3812 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3813 */ 3814 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3815 if (hsfsts.hsf_status.flcerr) { 3816 /* Repeat for some time before giving up. */ 3817 continue; 3818 } else if (!hsfsts.hsf_status.flcdone) { 3819 e_dbg("Timeout error - flash cycle did not complete.\n"); 3820 break; 3821 } 3822 } 3823 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3824 3825 return ret_val; 3826 } 3827 3828 /** 3829 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3830 * @hw: pointer to the HW structure 3831 * @offset: The offset (in bytes) of the word(s) to write. 3832 * @words: Size of data to write in words 3833 * @data: Pointer to the word(s) to write at offset. 3834 * 3835 * Writes a byte or word to the NVM using the flash access registers. 3836 **/ 3837 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3838 u16 *data) 3839 { 3840 struct e1000_nvm_info *nvm = &hw->nvm; 3841 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3842 u16 i; 3843 3844 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3845 (words == 0)) { 3846 e_dbg("nvm parameter(s) out of bounds\n"); 3847 return -E1000_ERR_NVM; 3848 } 3849 3850 nvm->ops.acquire(hw); 3851 3852 for (i = 0; i < words; i++) { 3853 dev_spec->shadow_ram[offset + i].modified = true; 3854 dev_spec->shadow_ram[offset + i].value = data[i]; 3855 } 3856 3857 nvm->ops.release(hw); 3858 3859 return 0; 3860 } 3861 3862 /** 3863 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3864 * @hw: pointer to the HW structure 3865 * 3866 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3867 * which writes the checksum to the shadow ram. The changes in the shadow 3868 * ram are then committed to the EEPROM by processing each bank at a time 3869 * checking for the modified bit and writing only the pending changes. 3870 * After a successful commit, the shadow ram is cleared and is ready for 3871 * future writes. 3872 **/ 3873 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3874 { 3875 struct e1000_nvm_info *nvm = &hw->nvm; 3876 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3877 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3878 s32 ret_val; 3879 u32 dword = 0; 3880 3881 ret_val = e1000e_update_nvm_checksum_generic(hw); 3882 if (ret_val) 3883 goto out; 3884 3885 if (nvm->type != e1000_nvm_flash_sw) 3886 goto out; 3887 3888 nvm->ops.acquire(hw); 3889 3890 /* We're writing to the opposite bank so if we're on bank 1, 3891 * write to bank 0 etc. We also need to erase the segment that 3892 * is going to be written 3893 */ 3894 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3895 if (ret_val) { 3896 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3897 bank = 0; 3898 } 3899 3900 if (bank == 0) { 3901 new_bank_offset = nvm->flash_bank_size; 3902 old_bank_offset = 0; 3903 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3904 if (ret_val) 3905 goto release; 3906 } else { 3907 old_bank_offset = nvm->flash_bank_size; 3908 new_bank_offset = 0; 3909 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3910 if (ret_val) 3911 goto release; 3912 } 3913 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3914 /* Determine whether to write the value stored 3915 * in the other NVM bank or a modified value stored 3916 * in the shadow RAM 3917 */ 3918 ret_val = e1000_read_flash_dword_ich8lan(hw, 3919 i + old_bank_offset, 3920 &dword); 3921 3922 if (dev_spec->shadow_ram[i].modified) { 3923 dword &= 0xffff0000; 3924 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3925 } 3926 if (dev_spec->shadow_ram[i + 1].modified) { 3927 dword &= 0x0000ffff; 3928 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3929 << 16); 3930 } 3931 if (ret_val) 3932 break; 3933 3934 /* If the word is 0x13, then make sure the signature bits 3935 * (15:14) are 11b until the commit has completed. 3936 * This will allow us to write 10b which indicates the 3937 * signature is valid. We want to do this after the write 3938 * has completed so that we don't mark the segment valid 3939 * while the write is still in progress 3940 */ 3941 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3942 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3943 3944 /* Convert offset to bytes. */ 3945 act_offset = (i + new_bank_offset) << 1; 3946 3947 usleep_range(100, 200); 3948 3949 /* Write the data to the new bank. Offset in words */ 3950 act_offset = i + new_bank_offset; 3951 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 3952 dword); 3953 if (ret_val) 3954 break; 3955 } 3956 3957 /* Don't bother writing the segment valid bits if sector 3958 * programming failed. 3959 */ 3960 if (ret_val) { 3961 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3962 e_dbg("Flash commit failed.\n"); 3963 goto release; 3964 } 3965 3966 /* Finally validate the new segment by setting bit 15:14 3967 * to 10b in word 0x13 , this can be done without an 3968 * erase as well since these bits are 11 to start with 3969 * and we need to change bit 14 to 0b 3970 */ 3971 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3972 3973 /*offset in words but we read dword */ 3974 --act_offset; 3975 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3976 3977 if (ret_val) 3978 goto release; 3979 3980 dword &= 0xBFFFFFFF; 3981 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3982 3983 if (ret_val) 3984 goto release; 3985 3986 /* offset in words but we read dword */ 3987 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 3988 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3989 3990 if (ret_val) 3991 goto release; 3992 3993 dword &= 0x00FFFFFF; 3994 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3995 3996 if (ret_val) 3997 goto release; 3998 3999 /* Great! Everything worked, we can now clear the cached entries. */ 4000 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4001 dev_spec->shadow_ram[i].modified = false; 4002 dev_spec->shadow_ram[i].value = 0xFFFF; 4003 } 4004 4005 release: 4006 nvm->ops.release(hw); 4007 4008 /* Reload the EEPROM, or else modifications will not appear 4009 * until after the next adapter reset. 4010 */ 4011 if (!ret_val) { 4012 nvm->ops.reload(hw); 4013 usleep_range(10000, 11000); 4014 } 4015 4016 out: 4017 if (ret_val) 4018 e_dbg("NVM update error: %d\n", ret_val); 4019 4020 return ret_val; 4021 } 4022 4023 /** 4024 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 4025 * @hw: pointer to the HW structure 4026 * 4027 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4028 * which writes the checksum to the shadow ram. The changes in the shadow 4029 * ram are then committed to the EEPROM by processing each bank at a time 4030 * checking for the modified bit and writing only the pending changes. 4031 * After a successful commit, the shadow ram is cleared and is ready for 4032 * future writes. 4033 **/ 4034 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 4035 { 4036 struct e1000_nvm_info *nvm = &hw->nvm; 4037 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4038 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4039 s32 ret_val; 4040 u16 data = 0; 4041 4042 ret_val = e1000e_update_nvm_checksum_generic(hw); 4043 if (ret_val) 4044 goto out; 4045 4046 if (nvm->type != e1000_nvm_flash_sw) 4047 goto out; 4048 4049 nvm->ops.acquire(hw); 4050 4051 /* We're writing to the opposite bank so if we're on bank 1, 4052 * write to bank 0 etc. We also need to erase the segment that 4053 * is going to be written 4054 */ 4055 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4056 if (ret_val) { 4057 e_dbg("Could not detect valid bank, assuming bank 0\n"); 4058 bank = 0; 4059 } 4060 4061 if (bank == 0) { 4062 new_bank_offset = nvm->flash_bank_size; 4063 old_bank_offset = 0; 4064 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4065 if (ret_val) 4066 goto release; 4067 } else { 4068 old_bank_offset = nvm->flash_bank_size; 4069 new_bank_offset = 0; 4070 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4071 if (ret_val) 4072 goto release; 4073 } 4074 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4075 if (dev_spec->shadow_ram[i].modified) { 4076 data = dev_spec->shadow_ram[i].value; 4077 } else { 4078 ret_val = e1000_read_flash_word_ich8lan(hw, i + 4079 old_bank_offset, 4080 &data); 4081 if (ret_val) 4082 break; 4083 } 4084 4085 /* If the word is 0x13, then make sure the signature bits 4086 * (15:14) are 11b until the commit has completed. 4087 * This will allow us to write 10b which indicates the 4088 * signature is valid. We want to do this after the write 4089 * has completed so that we don't mark the segment valid 4090 * while the write is still in progress 4091 */ 4092 if (i == E1000_ICH_NVM_SIG_WORD) 4093 data |= E1000_ICH_NVM_SIG_MASK; 4094 4095 /* Convert offset to bytes. */ 4096 act_offset = (i + new_bank_offset) << 1; 4097 4098 usleep_range(100, 200); 4099 /* Write the bytes to the new bank. */ 4100 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4101 act_offset, 4102 (u8)data); 4103 if (ret_val) 4104 break; 4105 4106 usleep_range(100, 200); 4107 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4108 act_offset + 1, 4109 (u8)(data >> 8)); 4110 if (ret_val) 4111 break; 4112 } 4113 4114 /* Don't bother writing the segment valid bits if sector 4115 * programming failed. 4116 */ 4117 if (ret_val) { 4118 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4119 e_dbg("Flash commit failed.\n"); 4120 goto release; 4121 } 4122 4123 /* Finally validate the new segment by setting bit 15:14 4124 * to 10b in word 0x13 , this can be done without an 4125 * erase as well since these bits are 11 to start with 4126 * and we need to change bit 14 to 0b 4127 */ 4128 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4129 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4130 if (ret_val) 4131 goto release; 4132 4133 data &= 0xBFFF; 4134 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4135 act_offset * 2 + 1, 4136 (u8)(data >> 8)); 4137 if (ret_val) 4138 goto release; 4139 4140 /* And invalidate the previously valid segment by setting 4141 * its signature word (0x13) high_byte to 0b. This can be 4142 * done without an erase because flash erase sets all bits 4143 * to 1's. We can write 1's to 0's without an erase 4144 */ 4145 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4146 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4147 if (ret_val) 4148 goto release; 4149 4150 /* Great! Everything worked, we can now clear the cached entries. */ 4151 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4152 dev_spec->shadow_ram[i].modified = false; 4153 dev_spec->shadow_ram[i].value = 0xFFFF; 4154 } 4155 4156 release: 4157 nvm->ops.release(hw); 4158 4159 /* Reload the EEPROM, or else modifications will not appear 4160 * until after the next adapter reset. 4161 */ 4162 if (!ret_val) { 4163 nvm->ops.reload(hw); 4164 usleep_range(10000, 11000); 4165 } 4166 4167 out: 4168 if (ret_val) 4169 e_dbg("NVM update error: %d\n", ret_val); 4170 4171 return ret_val; 4172 } 4173 4174 /** 4175 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4176 * @hw: pointer to the HW structure 4177 * 4178 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4179 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4180 * calculated, in which case we need to calculate the checksum and set bit 6. 4181 **/ 4182 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4183 { 4184 s32 ret_val; 4185 u16 data; 4186 u16 word; 4187 u16 valid_csum_mask; 4188 4189 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4190 * the checksum needs to be fixed. This bit is an indication that 4191 * the NVM was prepared by OEM software and did not calculate 4192 * the checksum...a likely scenario. 4193 */ 4194 switch (hw->mac.type) { 4195 case e1000_pch_lpt: 4196 case e1000_pch_spt: 4197 case e1000_pch_cnp: 4198 case e1000_pch_tgp: 4199 case e1000_pch_adp: 4200 case e1000_pch_mtp: 4201 case e1000_pch_lnp: 4202 case e1000_pch_ptp: 4203 case e1000_pch_nvp: 4204 word = NVM_COMPAT; 4205 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4206 break; 4207 default: 4208 word = NVM_FUTURE_INIT_WORD1; 4209 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4210 break; 4211 } 4212 4213 ret_val = e1000_read_nvm(hw, word, 1, &data); 4214 if (ret_val) 4215 return ret_val; 4216 4217 if (!(data & valid_csum_mask)) { 4218 e_dbg("NVM Checksum valid bit not set\n"); 4219 4220 if (hw->mac.type < e1000_pch_tgp) { 4221 data |= valid_csum_mask; 4222 ret_val = e1000_write_nvm(hw, word, 1, &data); 4223 if (ret_val) 4224 return ret_val; 4225 ret_val = e1000e_update_nvm_checksum(hw); 4226 if (ret_val) 4227 return ret_val; 4228 } 4229 } 4230 4231 return e1000e_validate_nvm_checksum_generic(hw); 4232 } 4233 4234 /** 4235 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4236 * @hw: pointer to the HW structure 4237 * 4238 * To prevent malicious write/erase of the NVM, set it to be read-only 4239 * so that the hardware ignores all write/erase cycles of the NVM via 4240 * the flash control registers. The shadow-ram copy of the NVM will 4241 * still be updated, however any updates to this copy will not stick 4242 * across driver reloads. 4243 **/ 4244 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4245 { 4246 struct e1000_nvm_info *nvm = &hw->nvm; 4247 union ich8_flash_protected_range pr0; 4248 union ich8_hws_flash_status hsfsts; 4249 u32 gfpreg; 4250 4251 nvm->ops.acquire(hw); 4252 4253 gfpreg = er32flash(ICH_FLASH_GFPREG); 4254 4255 /* Write-protect GbE Sector of NVM */ 4256 pr0.regval = er32flash(ICH_FLASH_PR0); 4257 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4258 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4259 pr0.range.wpe = true; 4260 ew32flash(ICH_FLASH_PR0, pr0.regval); 4261 4262 /* Lock down a subset of GbE Flash Control Registers, e.g. 4263 * PR0 to prevent the write-protection from being lifted. 4264 * Once FLOCKDN is set, the registers protected by it cannot 4265 * be written until FLOCKDN is cleared by a hardware reset. 4266 */ 4267 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4268 hsfsts.hsf_status.flockdn = true; 4269 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4270 4271 nvm->ops.release(hw); 4272 } 4273 4274 /** 4275 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4276 * @hw: pointer to the HW structure 4277 * @offset: The offset (in bytes) of the byte/word to read. 4278 * @size: Size of data to read, 1=byte 2=word 4279 * @data: The byte(s) to write to the NVM. 4280 * 4281 * Writes one/two bytes to the NVM using the flash access registers. 4282 **/ 4283 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4284 u8 size, u16 data) 4285 { 4286 union ich8_hws_flash_status hsfsts; 4287 union ich8_hws_flash_ctrl hsflctl; 4288 u32 flash_linear_addr; 4289 u32 flash_data = 0; 4290 s32 ret_val; 4291 u8 count = 0; 4292 4293 if (hw->mac.type >= e1000_pch_spt) { 4294 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4295 return -E1000_ERR_NVM; 4296 } else { 4297 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4298 return -E1000_ERR_NVM; 4299 } 4300 4301 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4302 hw->nvm.flash_base_addr); 4303 4304 do { 4305 udelay(1); 4306 /* Steps */ 4307 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4308 if (ret_val) 4309 break; 4310 /* In SPT, This register is in Lan memory space, not 4311 * flash. Therefore, only 32 bit access is supported 4312 */ 4313 if (hw->mac.type >= e1000_pch_spt) 4314 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4315 else 4316 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4317 4318 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4319 hsflctl.hsf_ctrl.fldbcount = size - 1; 4320 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4321 /* In SPT, This register is in Lan memory space, 4322 * not flash. Therefore, only 32 bit access is 4323 * supported 4324 */ 4325 if (hw->mac.type >= e1000_pch_spt) 4326 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4327 else 4328 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4329 4330 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4331 4332 if (size == 1) 4333 flash_data = (u32)data & 0x00FF; 4334 else 4335 flash_data = (u32)data; 4336 4337 ew32flash(ICH_FLASH_FDATA0, flash_data); 4338 4339 /* check if FCERR is set to 1 , if set to 1, clear it 4340 * and try the whole sequence a few more times else done 4341 */ 4342 ret_val = 4343 e1000_flash_cycle_ich8lan(hw, 4344 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4345 if (!ret_val) 4346 break; 4347 4348 /* If we're here, then things are most likely 4349 * completely hosed, but if the error condition 4350 * is detected, it won't hurt to give it another 4351 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4352 */ 4353 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4354 if (hsfsts.hsf_status.flcerr) 4355 /* Repeat for some time before giving up. */ 4356 continue; 4357 if (!hsfsts.hsf_status.flcdone) { 4358 e_dbg("Timeout error - flash cycle did not complete.\n"); 4359 break; 4360 } 4361 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4362 4363 return ret_val; 4364 } 4365 4366 /** 4367 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4368 * @hw: pointer to the HW structure 4369 * @offset: The offset (in bytes) of the dwords to read. 4370 * @data: The 4 bytes to write to the NVM. 4371 * 4372 * Writes one/two/four bytes to the NVM using the flash access registers. 4373 **/ 4374 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4375 u32 data) 4376 { 4377 union ich8_hws_flash_status hsfsts; 4378 union ich8_hws_flash_ctrl hsflctl; 4379 u32 flash_linear_addr; 4380 s32 ret_val; 4381 u8 count = 0; 4382 4383 if (hw->mac.type >= e1000_pch_spt) { 4384 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4385 return -E1000_ERR_NVM; 4386 } 4387 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4388 hw->nvm.flash_base_addr); 4389 do { 4390 udelay(1); 4391 /* Steps */ 4392 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4393 if (ret_val) 4394 break; 4395 4396 /* In SPT, This register is in Lan memory space, not 4397 * flash. Therefore, only 32 bit access is supported 4398 */ 4399 if (hw->mac.type >= e1000_pch_spt) 4400 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4401 >> 16; 4402 else 4403 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4404 4405 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4406 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4407 4408 /* In SPT, This register is in Lan memory space, 4409 * not flash. Therefore, only 32 bit access is 4410 * supported 4411 */ 4412 if (hw->mac.type >= e1000_pch_spt) 4413 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4414 else 4415 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4416 4417 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4418 4419 ew32flash(ICH_FLASH_FDATA0, data); 4420 4421 /* check if FCERR is set to 1 , if set to 1, clear it 4422 * and try the whole sequence a few more times else done 4423 */ 4424 ret_val = 4425 e1000_flash_cycle_ich8lan(hw, 4426 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4427 4428 if (!ret_val) 4429 break; 4430 4431 /* If we're here, then things are most likely 4432 * completely hosed, but if the error condition 4433 * is detected, it won't hurt to give it another 4434 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4435 */ 4436 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4437 4438 if (hsfsts.hsf_status.flcerr) 4439 /* Repeat for some time before giving up. */ 4440 continue; 4441 if (!hsfsts.hsf_status.flcdone) { 4442 e_dbg("Timeout error - flash cycle did not complete.\n"); 4443 break; 4444 } 4445 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4446 4447 return ret_val; 4448 } 4449 4450 /** 4451 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4452 * @hw: pointer to the HW structure 4453 * @offset: The index of the byte to read. 4454 * @data: The byte to write to the NVM. 4455 * 4456 * Writes a single byte to the NVM using the flash access registers. 4457 **/ 4458 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4459 u8 data) 4460 { 4461 u16 word = (u16)data; 4462 4463 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4464 } 4465 4466 /** 4467 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4468 * @hw: pointer to the HW structure 4469 * @offset: The offset of the word to write. 4470 * @dword: The dword to write to the NVM. 4471 * 4472 * Writes a single dword to the NVM using the flash access registers. 4473 * Goes through a retry algorithm before giving up. 4474 **/ 4475 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4476 u32 offset, u32 dword) 4477 { 4478 s32 ret_val; 4479 u16 program_retries; 4480 4481 /* Must convert word offset into bytes. */ 4482 offset <<= 1; 4483 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4484 4485 if (!ret_val) 4486 return ret_val; 4487 for (program_retries = 0; program_retries < 100; program_retries++) { 4488 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4489 usleep_range(100, 200); 4490 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4491 if (!ret_val) 4492 break; 4493 } 4494 if (program_retries == 100) 4495 return -E1000_ERR_NVM; 4496 4497 return 0; 4498 } 4499 4500 /** 4501 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4502 * @hw: pointer to the HW structure 4503 * @offset: The offset of the byte to write. 4504 * @byte: The byte to write to the NVM. 4505 * 4506 * Writes a single byte to the NVM using the flash access registers. 4507 * Goes through a retry algorithm before giving up. 4508 **/ 4509 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4510 u32 offset, u8 byte) 4511 { 4512 s32 ret_val; 4513 u16 program_retries; 4514 4515 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4516 if (!ret_val) 4517 return ret_val; 4518 4519 for (program_retries = 0; program_retries < 100; program_retries++) { 4520 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4521 usleep_range(100, 200); 4522 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4523 if (!ret_val) 4524 break; 4525 } 4526 if (program_retries == 100) 4527 return -E1000_ERR_NVM; 4528 4529 return 0; 4530 } 4531 4532 /** 4533 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4534 * @hw: pointer to the HW structure 4535 * @bank: 0 for first bank, 1 for second bank, etc. 4536 * 4537 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4538 * bank N is 4096 * N + flash_reg_addr. 4539 **/ 4540 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4541 { 4542 struct e1000_nvm_info *nvm = &hw->nvm; 4543 union ich8_hws_flash_status hsfsts; 4544 union ich8_hws_flash_ctrl hsflctl; 4545 u32 flash_linear_addr; 4546 /* bank size is in 16bit words - adjust to bytes */ 4547 u32 flash_bank_size = nvm->flash_bank_size * 2; 4548 s32 ret_val; 4549 s32 count = 0; 4550 s32 j, iteration, sector_size; 4551 4552 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4553 4554 /* Determine HW Sector size: Read BERASE bits of hw flash status 4555 * register 4556 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4557 * consecutive sectors. The start index for the nth Hw sector 4558 * can be calculated as = bank * 4096 + n * 256 4559 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4560 * The start index for the nth Hw sector can be calculated 4561 * as = bank * 4096 4562 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4563 * (ich9 only, otherwise error condition) 4564 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4565 */ 4566 switch (hsfsts.hsf_status.berasesz) { 4567 case 0: 4568 /* Hw sector size 256 */ 4569 sector_size = ICH_FLASH_SEG_SIZE_256; 4570 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4571 break; 4572 case 1: 4573 sector_size = ICH_FLASH_SEG_SIZE_4K; 4574 iteration = 1; 4575 break; 4576 case 2: 4577 sector_size = ICH_FLASH_SEG_SIZE_8K; 4578 iteration = 1; 4579 break; 4580 case 3: 4581 sector_size = ICH_FLASH_SEG_SIZE_64K; 4582 iteration = 1; 4583 break; 4584 default: 4585 return -E1000_ERR_NVM; 4586 } 4587 4588 /* Start with the base address, then add the sector offset. */ 4589 flash_linear_addr = hw->nvm.flash_base_addr; 4590 flash_linear_addr += (bank) ? flash_bank_size : 0; 4591 4592 for (j = 0; j < iteration; j++) { 4593 do { 4594 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4595 4596 /* Steps */ 4597 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4598 if (ret_val) 4599 return ret_val; 4600 4601 /* Write a value 11 (block Erase) in Flash 4602 * Cycle field in hw flash control 4603 */ 4604 if (hw->mac.type >= e1000_pch_spt) 4605 hsflctl.regval = 4606 er32flash(ICH_FLASH_HSFSTS) >> 16; 4607 else 4608 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4609 4610 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4611 if (hw->mac.type >= e1000_pch_spt) 4612 ew32flash(ICH_FLASH_HSFSTS, 4613 hsflctl.regval << 16); 4614 else 4615 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4616 4617 /* Write the last 24 bits of an index within the 4618 * block into Flash Linear address field in Flash 4619 * Address. 4620 */ 4621 flash_linear_addr += (j * sector_size); 4622 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4623 4624 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4625 if (!ret_val) 4626 break; 4627 4628 /* Check if FCERR is set to 1. If 1, 4629 * clear it and try the whole sequence 4630 * a few more times else Done 4631 */ 4632 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4633 if (hsfsts.hsf_status.flcerr) 4634 /* repeat for some time before giving up */ 4635 continue; 4636 else if (!hsfsts.hsf_status.flcdone) 4637 return ret_val; 4638 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4639 } 4640 4641 return 0; 4642 } 4643 4644 /** 4645 * e1000_valid_led_default_ich8lan - Set the default LED settings 4646 * @hw: pointer to the HW structure 4647 * @data: Pointer to the LED settings 4648 * 4649 * Reads the LED default settings from the NVM to data. If the NVM LED 4650 * settings is all 0's or F's, set the LED default to a valid LED default 4651 * setting. 4652 **/ 4653 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4654 { 4655 s32 ret_val; 4656 4657 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4658 if (ret_val) { 4659 e_dbg("NVM Read Error\n"); 4660 return ret_val; 4661 } 4662 4663 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4664 *data = ID_LED_DEFAULT_ICH8LAN; 4665 4666 return 0; 4667 } 4668 4669 /** 4670 * e1000_id_led_init_pchlan - store LED configurations 4671 * @hw: pointer to the HW structure 4672 * 4673 * PCH does not control LEDs via the LEDCTL register, rather it uses 4674 * the PHY LED configuration register. 4675 * 4676 * PCH also does not have an "always on" or "always off" mode which 4677 * complicates the ID feature. Instead of using the "on" mode to indicate 4678 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4679 * use "link_up" mode. The LEDs will still ID on request if there is no 4680 * link based on logic in e1000_led_[on|off]_pchlan(). 4681 **/ 4682 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4683 { 4684 struct e1000_mac_info *mac = &hw->mac; 4685 s32 ret_val; 4686 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4687 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4688 u16 data, i, temp, shift; 4689 4690 /* Get default ID LED modes */ 4691 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4692 if (ret_val) 4693 return ret_val; 4694 4695 mac->ledctl_default = er32(LEDCTL); 4696 mac->ledctl_mode1 = mac->ledctl_default; 4697 mac->ledctl_mode2 = mac->ledctl_default; 4698 4699 for (i = 0; i < 4; i++) { 4700 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4701 shift = (i * 5); 4702 switch (temp) { 4703 case ID_LED_ON1_DEF2: 4704 case ID_LED_ON1_ON2: 4705 case ID_LED_ON1_OFF2: 4706 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4707 mac->ledctl_mode1 |= (ledctl_on << shift); 4708 break; 4709 case ID_LED_OFF1_DEF2: 4710 case ID_LED_OFF1_ON2: 4711 case ID_LED_OFF1_OFF2: 4712 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4713 mac->ledctl_mode1 |= (ledctl_off << shift); 4714 break; 4715 default: 4716 /* Do nothing */ 4717 break; 4718 } 4719 switch (temp) { 4720 case ID_LED_DEF1_ON2: 4721 case ID_LED_ON1_ON2: 4722 case ID_LED_OFF1_ON2: 4723 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4724 mac->ledctl_mode2 |= (ledctl_on << shift); 4725 break; 4726 case ID_LED_DEF1_OFF2: 4727 case ID_LED_ON1_OFF2: 4728 case ID_LED_OFF1_OFF2: 4729 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4730 mac->ledctl_mode2 |= (ledctl_off << shift); 4731 break; 4732 default: 4733 /* Do nothing */ 4734 break; 4735 } 4736 } 4737 4738 return 0; 4739 } 4740 4741 /** 4742 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4743 * @hw: pointer to the HW structure 4744 * 4745 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4746 * register, so the bus width is hard coded. 4747 **/ 4748 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4749 { 4750 struct e1000_bus_info *bus = &hw->bus; 4751 s32 ret_val; 4752 4753 ret_val = e1000e_get_bus_info_pcie(hw); 4754 4755 /* ICH devices are "PCI Express"-ish. They have 4756 * a configuration space, but do not contain 4757 * PCI Express Capability registers, so bus width 4758 * must be hardcoded. 4759 */ 4760 if (bus->width == e1000_bus_width_unknown) 4761 bus->width = e1000_bus_width_pcie_x1; 4762 4763 return ret_val; 4764 } 4765 4766 /** 4767 * e1000_reset_hw_ich8lan - Reset the hardware 4768 * @hw: pointer to the HW structure 4769 * 4770 * Does a full reset of the hardware which includes a reset of the PHY and 4771 * MAC. 4772 **/ 4773 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4774 { 4775 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4776 u16 kum_cfg; 4777 u32 ctrl, reg; 4778 s32 ret_val; 4779 4780 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4781 * on the last TLP read/write transaction when MAC is reset. 4782 */ 4783 ret_val = e1000e_disable_pcie_master(hw); 4784 if (ret_val) 4785 e_dbg("PCI-E Master disable polling has failed.\n"); 4786 4787 e_dbg("Masking off all interrupts\n"); 4788 ew32(IMC, 0xffffffff); 4789 4790 /* Disable the Transmit and Receive units. Then delay to allow 4791 * any pending transactions to complete before we hit the MAC 4792 * with the global reset. 4793 */ 4794 ew32(RCTL, 0); 4795 ew32(TCTL, E1000_TCTL_PSP); 4796 e1e_flush(); 4797 4798 usleep_range(10000, 11000); 4799 4800 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4801 if (hw->mac.type == e1000_ich8lan) { 4802 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4803 ew32(PBA, E1000_PBA_8K); 4804 /* Set Packet Buffer Size to 16k. */ 4805 ew32(PBS, E1000_PBS_16K); 4806 } 4807 4808 if (hw->mac.type == e1000_pchlan) { 4809 /* Save the NVM K1 bit setting */ 4810 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4811 if (ret_val) 4812 return ret_val; 4813 4814 if (kum_cfg & E1000_NVM_K1_ENABLE) 4815 dev_spec->nvm_k1_enabled = true; 4816 else 4817 dev_spec->nvm_k1_enabled = false; 4818 } 4819 4820 ctrl = er32(CTRL); 4821 4822 if (!hw->phy.ops.check_reset_block(hw)) { 4823 /* Full-chip reset requires MAC and PHY reset at the same 4824 * time to make sure the interface between MAC and the 4825 * external PHY is reset. 4826 */ 4827 ctrl |= E1000_CTRL_PHY_RST; 4828 4829 /* Gate automatic PHY configuration by hardware on 4830 * non-managed 82579 4831 */ 4832 if ((hw->mac.type == e1000_pch2lan) && 4833 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4834 e1000_gate_hw_phy_config_ich8lan(hw, true); 4835 } 4836 ret_val = e1000_acquire_swflag_ich8lan(hw); 4837 e_dbg("Issuing a global reset to ich8lan\n"); 4838 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4839 /* cannot issue a flush here because it hangs the hardware */ 4840 msleep(20); 4841 4842 /* Set Phy Config Counter to 50msec */ 4843 if (hw->mac.type == e1000_pch2lan) { 4844 reg = er32(FEXTNVM3); 4845 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4846 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4847 ew32(FEXTNVM3, reg); 4848 } 4849 4850 if (!ret_val) 4851 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4852 4853 if (ctrl & E1000_CTRL_PHY_RST) { 4854 ret_val = hw->phy.ops.get_cfg_done(hw); 4855 if (ret_val) 4856 return ret_val; 4857 4858 ret_val = e1000_post_phy_reset_ich8lan(hw); 4859 if (ret_val) 4860 return ret_val; 4861 } 4862 4863 /* For PCH, this write will make sure that any noise 4864 * will be detected as a CRC error and be dropped rather than show up 4865 * as a bad packet to the DMA engine. 4866 */ 4867 if (hw->mac.type == e1000_pchlan) 4868 ew32(CRC_OFFSET, 0x65656565); 4869 4870 ew32(IMC, 0xffffffff); 4871 er32(ICR); 4872 4873 reg = er32(KABGTXD); 4874 reg |= E1000_KABGTXD_BGSQLBIAS; 4875 ew32(KABGTXD, reg); 4876 4877 return 0; 4878 } 4879 4880 /** 4881 * e1000_init_hw_ich8lan - Initialize the hardware 4882 * @hw: pointer to the HW structure 4883 * 4884 * Prepares the hardware for transmit and receive by doing the following: 4885 * - initialize hardware bits 4886 * - initialize LED identification 4887 * - setup receive address registers 4888 * - setup flow control 4889 * - setup transmit descriptors 4890 * - clear statistics 4891 **/ 4892 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4893 { 4894 struct e1000_mac_info *mac = &hw->mac; 4895 u32 ctrl_ext, txdctl, snoop, fflt_dbg; 4896 s32 ret_val; 4897 u16 i; 4898 4899 e1000_initialize_hw_bits_ich8lan(hw); 4900 4901 /* Initialize identification LED */ 4902 ret_val = mac->ops.id_led_init(hw); 4903 /* An error is not fatal and we should not stop init due to this */ 4904 if (ret_val) 4905 e_dbg("Error initializing identification LED\n"); 4906 4907 /* Setup the receive address. */ 4908 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4909 4910 /* Zero out the Multicast HASH table */ 4911 e_dbg("Zeroing the MTA\n"); 4912 for (i = 0; i < mac->mta_reg_count; i++) 4913 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4914 4915 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4916 * the ME. Disable wakeup by clearing the host wakeup bit. 4917 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4918 */ 4919 if (hw->phy.type == e1000_phy_82578) { 4920 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4921 i &= ~BM_WUC_HOST_WU_BIT; 4922 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 4923 ret_val = e1000_phy_hw_reset_ich8lan(hw); 4924 if (ret_val) 4925 return ret_val; 4926 } 4927 4928 /* Setup link and flow control */ 4929 ret_val = mac->ops.setup_link(hw); 4930 4931 /* Set the transmit descriptor write-back policy for both queues */ 4932 txdctl = er32(TXDCTL(0)); 4933 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4934 E1000_TXDCTL_FULL_TX_DESC_WB); 4935 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4936 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4937 ew32(TXDCTL(0), txdctl); 4938 txdctl = er32(TXDCTL(1)); 4939 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4940 E1000_TXDCTL_FULL_TX_DESC_WB); 4941 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4942 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4943 ew32(TXDCTL(1), txdctl); 4944 4945 /* ICH8 has opposite polarity of no_snoop bits. 4946 * By default, we should use snoop behavior. 4947 */ 4948 if (mac->type == e1000_ich8lan) 4949 snoop = PCIE_ICH8_SNOOP_ALL; 4950 else 4951 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 4952 e1000e_set_pcie_no_snoop(hw, snoop); 4953 4954 /* Enable workaround for packet loss issue on TGP PCH 4955 * Do not gate DMA clock from the modPHY block 4956 */ 4957 if (mac->type >= e1000_pch_tgp) { 4958 fflt_dbg = er32(FFLT_DBG); 4959 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK; 4960 ew32(FFLT_DBG, fflt_dbg); 4961 } 4962 4963 ctrl_ext = er32(CTRL_EXT); 4964 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 4965 ew32(CTRL_EXT, ctrl_ext); 4966 4967 /* Clear all of the statistics registers (clear on read). It is 4968 * important that we do this after we have tried to establish link 4969 * because the symbol error count will increment wildly if there 4970 * is no link. 4971 */ 4972 e1000_clear_hw_cntrs_ich8lan(hw); 4973 4974 return ret_val; 4975 } 4976 4977 /** 4978 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 4979 * @hw: pointer to the HW structure 4980 * 4981 * Sets/Clears required hardware bits necessary for correctly setting up the 4982 * hardware for transmit and receive. 4983 **/ 4984 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 4985 { 4986 u32 reg; 4987 4988 /* Extended Device Control */ 4989 reg = er32(CTRL_EXT); 4990 reg |= BIT(22); 4991 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4992 if (hw->mac.type >= e1000_pchlan) 4993 reg |= E1000_CTRL_EXT_PHYPDEN; 4994 ew32(CTRL_EXT, reg); 4995 4996 /* Transmit Descriptor Control 0 */ 4997 reg = er32(TXDCTL(0)); 4998 reg |= BIT(22); 4999 ew32(TXDCTL(0), reg); 5000 5001 /* Transmit Descriptor Control 1 */ 5002 reg = er32(TXDCTL(1)); 5003 reg |= BIT(22); 5004 ew32(TXDCTL(1), reg); 5005 5006 /* Transmit Arbitration Control 0 */ 5007 reg = er32(TARC(0)); 5008 if (hw->mac.type == e1000_ich8lan) 5009 reg |= BIT(28) | BIT(29); 5010 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 5011 ew32(TARC(0), reg); 5012 5013 /* Transmit Arbitration Control 1 */ 5014 reg = er32(TARC(1)); 5015 if (er32(TCTL) & E1000_TCTL_MULR) 5016 reg &= ~BIT(28); 5017 else 5018 reg |= BIT(28); 5019 reg |= BIT(24) | BIT(26) | BIT(30); 5020 ew32(TARC(1), reg); 5021 5022 /* Device Status */ 5023 if (hw->mac.type == e1000_ich8lan) { 5024 reg = er32(STATUS); 5025 reg &= ~BIT(31); 5026 ew32(STATUS, reg); 5027 } 5028 5029 /* work-around descriptor data corruption issue during nfs v2 udp 5030 * traffic, just disable the nfs filtering capability 5031 */ 5032 reg = er32(RFCTL); 5033 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 5034 5035 /* Disable IPv6 extension header parsing because some malformed 5036 * IPv6 headers can hang the Rx. 5037 */ 5038 if (hw->mac.type == e1000_ich8lan) 5039 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 5040 ew32(RFCTL, reg); 5041 5042 /* Enable ECC on Lynxpoint */ 5043 if (hw->mac.type >= e1000_pch_lpt) { 5044 reg = er32(PBECCSTS); 5045 reg |= E1000_PBECCSTS_ECC_ENABLE; 5046 ew32(PBECCSTS, reg); 5047 5048 reg = er32(CTRL); 5049 reg |= E1000_CTRL_MEHE; 5050 ew32(CTRL, reg); 5051 } 5052 } 5053 5054 /** 5055 * e1000_setup_link_ich8lan - Setup flow control and link settings 5056 * @hw: pointer to the HW structure 5057 * 5058 * Determines which flow control settings to use, then configures flow 5059 * control. Calls the appropriate media-specific link configuration 5060 * function. Assuming the adapter has a valid link partner, a valid link 5061 * should be established. Assumes the hardware has previously been reset 5062 * and the transmitter and receiver are not enabled. 5063 **/ 5064 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 5065 { 5066 s32 ret_val; 5067 5068 if (hw->phy.ops.check_reset_block(hw)) 5069 return 0; 5070 5071 /* ICH parts do not have a word in the NVM to determine 5072 * the default flow control setting, so we explicitly 5073 * set it to full. 5074 */ 5075 if (hw->fc.requested_mode == e1000_fc_default) { 5076 /* Workaround h/w hang when Tx flow control enabled */ 5077 if (hw->mac.type == e1000_pchlan) 5078 hw->fc.requested_mode = e1000_fc_rx_pause; 5079 else 5080 hw->fc.requested_mode = e1000_fc_full; 5081 } 5082 5083 /* Save off the requested flow control mode for use later. Depending 5084 * on the link partner's capabilities, we may or may not use this mode. 5085 */ 5086 hw->fc.current_mode = hw->fc.requested_mode; 5087 5088 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 5089 5090 /* Continue to configure the copper link. */ 5091 ret_val = hw->mac.ops.setup_physical_interface(hw); 5092 if (ret_val) 5093 return ret_val; 5094 5095 ew32(FCTTV, hw->fc.pause_time); 5096 if ((hw->phy.type == e1000_phy_82578) || 5097 (hw->phy.type == e1000_phy_82579) || 5098 (hw->phy.type == e1000_phy_i217) || 5099 (hw->phy.type == e1000_phy_82577)) { 5100 ew32(FCRTV_PCH, hw->fc.refresh_time); 5101 5102 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 5103 hw->fc.pause_time); 5104 if (ret_val) 5105 return ret_val; 5106 } 5107 5108 return e1000e_set_fc_watermarks(hw); 5109 } 5110 5111 /** 5112 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5113 * @hw: pointer to the HW structure 5114 * 5115 * Configures the kumeran interface to the PHY to wait the appropriate time 5116 * when polling the PHY, then call the generic setup_copper_link to finish 5117 * configuring the copper link. 5118 **/ 5119 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5120 { 5121 u32 ctrl; 5122 s32 ret_val; 5123 u16 reg_data; 5124 5125 ctrl = er32(CTRL); 5126 ctrl |= E1000_CTRL_SLU; 5127 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5128 ew32(CTRL, ctrl); 5129 5130 /* Set the mac to wait the maximum time between each iteration 5131 * and increase the max iterations when polling the phy; 5132 * this fixes erroneous timeouts at 10Mbps. 5133 */ 5134 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 5135 if (ret_val) 5136 return ret_val; 5137 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5138 ®_data); 5139 if (ret_val) 5140 return ret_val; 5141 reg_data |= 0x3F; 5142 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5143 reg_data); 5144 if (ret_val) 5145 return ret_val; 5146 5147 switch (hw->phy.type) { 5148 case e1000_phy_igp_3: 5149 ret_val = e1000e_copper_link_setup_igp(hw); 5150 if (ret_val) 5151 return ret_val; 5152 break; 5153 case e1000_phy_bm: 5154 case e1000_phy_82578: 5155 ret_val = e1000e_copper_link_setup_m88(hw); 5156 if (ret_val) 5157 return ret_val; 5158 break; 5159 case e1000_phy_82577: 5160 case e1000_phy_82579: 5161 ret_val = e1000_copper_link_setup_82577(hw); 5162 if (ret_val) 5163 return ret_val; 5164 break; 5165 case e1000_phy_ife: 5166 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5167 if (ret_val) 5168 return ret_val; 5169 5170 reg_data &= ~IFE_PMC_AUTO_MDIX; 5171 5172 switch (hw->phy.mdix) { 5173 case 1: 5174 reg_data &= ~IFE_PMC_FORCE_MDIX; 5175 break; 5176 case 2: 5177 reg_data |= IFE_PMC_FORCE_MDIX; 5178 break; 5179 case 0: 5180 default: 5181 reg_data |= IFE_PMC_AUTO_MDIX; 5182 break; 5183 } 5184 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5185 if (ret_val) 5186 return ret_val; 5187 break; 5188 default: 5189 break; 5190 } 5191 5192 return e1000e_setup_copper_link(hw); 5193 } 5194 5195 /** 5196 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5197 * @hw: pointer to the HW structure 5198 * 5199 * Calls the PHY specific link setup function and then calls the 5200 * generic setup_copper_link to finish configuring the link for 5201 * Lynxpoint PCH devices 5202 **/ 5203 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5204 { 5205 u32 ctrl; 5206 s32 ret_val; 5207 5208 ctrl = er32(CTRL); 5209 ctrl |= E1000_CTRL_SLU; 5210 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5211 ew32(CTRL, ctrl); 5212 5213 ret_val = e1000_copper_link_setup_82577(hw); 5214 if (ret_val) 5215 return ret_val; 5216 5217 return e1000e_setup_copper_link(hw); 5218 } 5219 5220 /** 5221 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5222 * @hw: pointer to the HW structure 5223 * @speed: pointer to store current link speed 5224 * @duplex: pointer to store the current link duplex 5225 * 5226 * Calls the generic get_speed_and_duplex to retrieve the current link 5227 * information and then calls the Kumeran lock loss workaround for links at 5228 * gigabit speeds. 5229 **/ 5230 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5231 u16 *duplex) 5232 { 5233 s32 ret_val; 5234 5235 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5236 if (ret_val) 5237 return ret_val; 5238 5239 if ((hw->mac.type == e1000_ich8lan) && 5240 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5241 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5242 } 5243 5244 return ret_val; 5245 } 5246 5247 /** 5248 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5249 * @hw: pointer to the HW structure 5250 * 5251 * Work-around for 82566 Kumeran PCS lock loss: 5252 * On link status change (i.e. PCI reset, speed change) and link is up and 5253 * speed is gigabit- 5254 * 0) if workaround is optionally disabled do nothing 5255 * 1) wait 1ms for Kumeran link to come up 5256 * 2) check Kumeran Diagnostic register PCS lock loss bit 5257 * 3) if not set the link is locked (all is good), otherwise... 5258 * 4) reset the PHY 5259 * 5) repeat up to 10 times 5260 * Note: this is only called for IGP3 copper when speed is 1gb. 5261 **/ 5262 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5263 { 5264 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5265 u32 phy_ctrl; 5266 s32 ret_val; 5267 u16 i, data; 5268 bool link; 5269 5270 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5271 return 0; 5272 5273 /* Make sure link is up before proceeding. If not just return. 5274 * Attempting this while link is negotiating fouled up link 5275 * stability 5276 */ 5277 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5278 if (!link) 5279 return 0; 5280 5281 for (i = 0; i < 10; i++) { 5282 /* read once to clear */ 5283 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5284 if (ret_val) 5285 return ret_val; 5286 /* and again to get new status */ 5287 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5288 if (ret_val) 5289 return ret_val; 5290 5291 /* check for PCS lock */ 5292 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5293 return 0; 5294 5295 /* Issue PHY reset */ 5296 e1000_phy_hw_reset(hw); 5297 mdelay(5); 5298 } 5299 /* Disable GigE link negotiation */ 5300 phy_ctrl = er32(PHY_CTRL); 5301 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5302 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5303 ew32(PHY_CTRL, phy_ctrl); 5304 5305 /* Call gig speed drop workaround on Gig disable before accessing 5306 * any PHY registers 5307 */ 5308 e1000e_gig_downshift_workaround_ich8lan(hw); 5309 5310 /* unable to acquire PCS lock */ 5311 return -E1000_ERR_PHY; 5312 } 5313 5314 /** 5315 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5316 * @hw: pointer to the HW structure 5317 * @state: boolean value used to set the current Kumeran workaround state 5318 * 5319 * If ICH8, set the current Kumeran workaround state (enabled - true 5320 * /disabled - false). 5321 **/ 5322 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5323 bool state) 5324 { 5325 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5326 5327 if (hw->mac.type != e1000_ich8lan) { 5328 e_dbg("Workaround applies to ICH8 only.\n"); 5329 return; 5330 } 5331 5332 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5333 } 5334 5335 /** 5336 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5337 * @hw: pointer to the HW structure 5338 * 5339 * Workaround for 82566 power-down on D3 entry: 5340 * 1) disable gigabit link 5341 * 2) write VR power-down enable 5342 * 3) read it back 5343 * Continue if successful, else issue LCD reset and repeat 5344 **/ 5345 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5346 { 5347 u32 reg; 5348 u16 data; 5349 u8 retry = 0; 5350 5351 if (hw->phy.type != e1000_phy_igp_3) 5352 return; 5353 5354 /* Try the workaround twice (if needed) */ 5355 do { 5356 /* Disable link */ 5357 reg = er32(PHY_CTRL); 5358 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5359 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5360 ew32(PHY_CTRL, reg); 5361 5362 /* Call gig speed drop workaround on Gig disable before 5363 * accessing any PHY registers 5364 */ 5365 if (hw->mac.type == e1000_ich8lan) 5366 e1000e_gig_downshift_workaround_ich8lan(hw); 5367 5368 /* Write VR power-down enable */ 5369 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5370 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5371 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5372 5373 /* Read it back and test */ 5374 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5375 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5376 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5377 break; 5378 5379 /* Issue PHY reset and repeat at most one more time */ 5380 reg = er32(CTRL); 5381 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5382 retry++; 5383 } while (retry); 5384 } 5385 5386 /** 5387 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5388 * @hw: pointer to the HW structure 5389 * 5390 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5391 * LPLU, Gig disable, MDIC PHY reset): 5392 * 1) Set Kumeran Near-end loopback 5393 * 2) Clear Kumeran Near-end loopback 5394 * Should only be called for ICH8[m] devices with any 1G Phy. 5395 **/ 5396 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5397 { 5398 s32 ret_val; 5399 u16 reg_data; 5400 5401 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5402 return; 5403 5404 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5405 ®_data); 5406 if (ret_val) 5407 return; 5408 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5409 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5410 reg_data); 5411 if (ret_val) 5412 return; 5413 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5414 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5415 } 5416 5417 /** 5418 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5419 * @hw: pointer to the HW structure 5420 * 5421 * During S0 to Sx transition, it is possible the link remains at gig 5422 * instead of negotiating to a lower speed. Before going to Sx, set 5423 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5424 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5425 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5426 * needs to be written. 5427 * Parts that support (and are linked to a partner which support) EEE in 5428 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5429 * than 10Mbps w/o EEE. 5430 **/ 5431 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5432 { 5433 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5434 u32 phy_ctrl; 5435 s32 ret_val; 5436 5437 phy_ctrl = er32(PHY_CTRL); 5438 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5439 5440 if (hw->phy.type == e1000_phy_i217) { 5441 u16 phy_reg, device_id = hw->adapter->pdev->device; 5442 5443 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5444 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5445 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5446 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5447 (hw->mac.type >= e1000_pch_spt)) { 5448 u32 fextnvm6 = er32(FEXTNVM6); 5449 5450 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5451 } 5452 5453 ret_val = hw->phy.ops.acquire(hw); 5454 if (ret_val) 5455 goto out; 5456 5457 if (!dev_spec->eee_disable) { 5458 u16 eee_advert; 5459 5460 ret_val = 5461 e1000_read_emi_reg_locked(hw, 5462 I217_EEE_ADVERTISEMENT, 5463 &eee_advert); 5464 if (ret_val) 5465 goto release; 5466 5467 /* Disable LPLU if both link partners support 100BaseT 5468 * EEE and 100Full is advertised on both ends of the 5469 * link, and enable Auto Enable LPI since there will 5470 * be no driver to enable LPI while in Sx. 5471 */ 5472 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5473 (dev_spec->eee_lp_ability & 5474 I82579_EEE_100_SUPPORTED) && 5475 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5476 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5477 E1000_PHY_CTRL_NOND0A_LPLU); 5478 5479 /* Set Auto Enable LPI after link up */ 5480 e1e_rphy_locked(hw, 5481 I217_LPI_GPIO_CTRL, &phy_reg); 5482 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5483 e1e_wphy_locked(hw, 5484 I217_LPI_GPIO_CTRL, phy_reg); 5485 } 5486 } 5487 5488 /* For i217 Intel Rapid Start Technology support, 5489 * when the system is going into Sx and no manageability engine 5490 * is present, the driver must configure proxy to reset only on 5491 * power good. LPI (Low Power Idle) state must also reset only 5492 * on power good, as well as the MTA (Multicast table array). 5493 * The SMBus release must also be disabled on LCD reset. 5494 */ 5495 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5496 /* Enable proxy to reset only on power good. */ 5497 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5498 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5499 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5500 5501 /* Set bit enable LPI (EEE) to reset only on 5502 * power good. 5503 */ 5504 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5505 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5506 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5507 5508 /* Disable the SMB release on LCD reset. */ 5509 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5510 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5511 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5512 } 5513 5514 /* Enable MTA to reset for Intel Rapid Start Technology 5515 * Support 5516 */ 5517 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5518 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5519 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5520 5521 release: 5522 hw->phy.ops.release(hw); 5523 } 5524 out: 5525 ew32(PHY_CTRL, phy_ctrl); 5526 5527 if (hw->mac.type == e1000_ich8lan) 5528 e1000e_gig_downshift_workaround_ich8lan(hw); 5529 5530 if (hw->mac.type >= e1000_pchlan) { 5531 e1000_oem_bits_config_ich8lan(hw, false); 5532 5533 /* Reset PHY to activate OEM bits on 82577/8 */ 5534 if (hw->mac.type == e1000_pchlan) 5535 e1000e_phy_hw_reset_generic(hw); 5536 5537 ret_val = hw->phy.ops.acquire(hw); 5538 if (ret_val) 5539 return; 5540 e1000_write_smbus_addr(hw); 5541 hw->phy.ops.release(hw); 5542 } 5543 } 5544 5545 /** 5546 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5547 * @hw: pointer to the HW structure 5548 * 5549 * During Sx to S0 transitions on non-managed devices or managed devices 5550 * on which PHY resets are not blocked, if the PHY registers cannot be 5551 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5552 * the PHY. 5553 * On i217, setup Intel Rapid Start Technology. 5554 **/ 5555 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5556 { 5557 s32 ret_val; 5558 5559 if (hw->mac.type < e1000_pch2lan) 5560 return; 5561 5562 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5563 if (ret_val) { 5564 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5565 return; 5566 } 5567 5568 /* For i217 Intel Rapid Start Technology support when the system 5569 * is transitioning from Sx and no manageability engine is present 5570 * configure SMBus to restore on reset, disable proxy, and enable 5571 * the reset on MTA (Multicast table array). 5572 */ 5573 if (hw->phy.type == e1000_phy_i217) { 5574 u16 phy_reg; 5575 5576 ret_val = hw->phy.ops.acquire(hw); 5577 if (ret_val) { 5578 e_dbg("Failed to setup iRST\n"); 5579 return; 5580 } 5581 5582 /* Clear Auto Enable LPI after link up */ 5583 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5584 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5585 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5586 5587 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5588 /* Restore clear on SMB if no manageability engine 5589 * is present 5590 */ 5591 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5592 if (ret_val) 5593 goto release; 5594 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5595 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5596 5597 /* Disable Proxy */ 5598 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5599 } 5600 /* Enable reset on MTA */ 5601 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5602 if (ret_val) 5603 goto release; 5604 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5605 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5606 release: 5607 if (ret_val) 5608 e_dbg("Error %d in resume workarounds\n", ret_val); 5609 hw->phy.ops.release(hw); 5610 } 5611 } 5612 5613 /** 5614 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5615 * @hw: pointer to the HW structure 5616 * 5617 * Return the LED back to the default configuration. 5618 **/ 5619 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5620 { 5621 if (hw->phy.type == e1000_phy_ife) 5622 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5623 5624 ew32(LEDCTL, hw->mac.ledctl_default); 5625 return 0; 5626 } 5627 5628 /** 5629 * e1000_led_on_ich8lan - Turn LEDs on 5630 * @hw: pointer to the HW structure 5631 * 5632 * Turn on the LEDs. 5633 **/ 5634 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5635 { 5636 if (hw->phy.type == e1000_phy_ife) 5637 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5638 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5639 5640 ew32(LEDCTL, hw->mac.ledctl_mode2); 5641 return 0; 5642 } 5643 5644 /** 5645 * e1000_led_off_ich8lan - Turn LEDs off 5646 * @hw: pointer to the HW structure 5647 * 5648 * Turn off the LEDs. 5649 **/ 5650 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5651 { 5652 if (hw->phy.type == e1000_phy_ife) 5653 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5654 (IFE_PSCL_PROBE_MODE | 5655 IFE_PSCL_PROBE_LEDS_OFF)); 5656 5657 ew32(LEDCTL, hw->mac.ledctl_mode1); 5658 return 0; 5659 } 5660 5661 /** 5662 * e1000_setup_led_pchlan - Configures SW controllable LED 5663 * @hw: pointer to the HW structure 5664 * 5665 * This prepares the SW controllable LED for use. 5666 **/ 5667 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5668 { 5669 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5670 } 5671 5672 /** 5673 * e1000_cleanup_led_pchlan - Restore the default LED operation 5674 * @hw: pointer to the HW structure 5675 * 5676 * Return the LED back to the default configuration. 5677 **/ 5678 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5679 { 5680 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5681 } 5682 5683 /** 5684 * e1000_led_on_pchlan - Turn LEDs on 5685 * @hw: pointer to the HW structure 5686 * 5687 * Turn on the LEDs. 5688 **/ 5689 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5690 { 5691 u16 data = (u16)hw->mac.ledctl_mode2; 5692 u32 i, led; 5693 5694 /* If no link, then turn LED on by setting the invert bit 5695 * for each LED that's mode is "link_up" in ledctl_mode2. 5696 */ 5697 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5698 for (i = 0; i < 3; i++) { 5699 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5700 if ((led & E1000_PHY_LED0_MODE_MASK) != 5701 E1000_LEDCTL_MODE_LINK_UP) 5702 continue; 5703 if (led & E1000_PHY_LED0_IVRT) 5704 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5705 else 5706 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5707 } 5708 } 5709 5710 return e1e_wphy(hw, HV_LED_CONFIG, data); 5711 } 5712 5713 /** 5714 * e1000_led_off_pchlan - Turn LEDs off 5715 * @hw: pointer to the HW structure 5716 * 5717 * Turn off the LEDs. 5718 **/ 5719 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5720 { 5721 u16 data = (u16)hw->mac.ledctl_mode1; 5722 u32 i, led; 5723 5724 /* If no link, then turn LED off by clearing the invert bit 5725 * for each LED that's mode is "link_up" in ledctl_mode1. 5726 */ 5727 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5728 for (i = 0; i < 3; i++) { 5729 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5730 if ((led & E1000_PHY_LED0_MODE_MASK) != 5731 E1000_LEDCTL_MODE_LINK_UP) 5732 continue; 5733 if (led & E1000_PHY_LED0_IVRT) 5734 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5735 else 5736 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5737 } 5738 } 5739 5740 return e1e_wphy(hw, HV_LED_CONFIG, data); 5741 } 5742 5743 /** 5744 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5745 * @hw: pointer to the HW structure 5746 * 5747 * Read appropriate register for the config done bit for completion status 5748 * and configure the PHY through s/w for EEPROM-less parts. 5749 * 5750 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5751 * config done bit, so only an error is logged and continues. If we were 5752 * to return with error, EEPROM-less silicon would not be able to be reset 5753 * or change link. 5754 **/ 5755 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5756 { 5757 s32 ret_val = 0; 5758 u32 bank = 0; 5759 u32 status; 5760 5761 e1000e_get_cfg_done_generic(hw); 5762 5763 /* Wait for indication from h/w that it has completed basic config */ 5764 if (hw->mac.type >= e1000_ich10lan) { 5765 e1000_lan_init_done_ich8lan(hw); 5766 } else { 5767 ret_val = e1000e_get_auto_rd_done(hw); 5768 if (ret_val) { 5769 /* When auto config read does not complete, do not 5770 * return with an error. This can happen in situations 5771 * where there is no eeprom and prevents getting link. 5772 */ 5773 e_dbg("Auto Read Done did not complete\n"); 5774 ret_val = 0; 5775 } 5776 } 5777 5778 /* Clear PHY Reset Asserted bit */ 5779 status = er32(STATUS); 5780 if (status & E1000_STATUS_PHYRA) 5781 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5782 else 5783 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5784 5785 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5786 if (hw->mac.type <= e1000_ich9lan) { 5787 if (!(er32(EECD) & E1000_EECD_PRES) && 5788 (hw->phy.type == e1000_phy_igp_3)) { 5789 e1000e_phy_init_script_igp3(hw); 5790 } 5791 } else { 5792 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5793 /* Maybe we should do a basic PHY config */ 5794 e_dbg("EEPROM not present\n"); 5795 ret_val = -E1000_ERR_CONFIG; 5796 } 5797 } 5798 5799 return ret_val; 5800 } 5801 5802 /** 5803 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5804 * @hw: pointer to the HW structure 5805 * 5806 * In the case of a PHY power down to save power, or to turn off link during a 5807 * driver unload, or wake on lan is not enabled, remove the link. 5808 **/ 5809 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5810 { 5811 /* If the management interface is not enabled, then power down */ 5812 if (!(hw->mac.ops.check_mng_mode(hw) || 5813 hw->phy.ops.check_reset_block(hw))) 5814 e1000_power_down_phy_copper(hw); 5815 } 5816 5817 /** 5818 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5819 * @hw: pointer to the HW structure 5820 * 5821 * Clears hardware counters specific to the silicon family and calls 5822 * clear_hw_cntrs_generic to clear all general purpose counters. 5823 **/ 5824 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5825 { 5826 u16 phy_data; 5827 s32 ret_val; 5828 5829 e1000e_clear_hw_cntrs_base(hw); 5830 5831 er32(ALGNERRC); 5832 er32(RXERRC); 5833 er32(TNCRS); 5834 er32(CEXTERR); 5835 er32(TSCTC); 5836 er32(TSCTFC); 5837 5838 er32(MGTPRC); 5839 er32(MGTPDC); 5840 er32(MGTPTC); 5841 5842 er32(IAC); 5843 er32(ICRXOC); 5844 5845 /* Clear PHY statistics registers */ 5846 if ((hw->phy.type == e1000_phy_82578) || 5847 (hw->phy.type == e1000_phy_82579) || 5848 (hw->phy.type == e1000_phy_i217) || 5849 (hw->phy.type == e1000_phy_82577)) { 5850 ret_val = hw->phy.ops.acquire(hw); 5851 if (ret_val) 5852 return; 5853 ret_val = hw->phy.ops.set_page(hw, 5854 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5855 if (ret_val) 5856 goto release; 5857 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5858 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5859 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5860 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5861 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5862 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5863 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5864 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5865 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5866 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5867 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5868 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5869 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5870 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5871 release: 5872 hw->phy.ops.release(hw); 5873 } 5874 } 5875 5876 static const struct e1000_mac_operations ich8_mac_ops = { 5877 /* check_mng_mode dependent on mac type */ 5878 .check_for_link = e1000_check_for_copper_link_ich8lan, 5879 /* cleanup_led dependent on mac type */ 5880 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5881 .get_bus_info = e1000_get_bus_info_ich8lan, 5882 .set_lan_id = e1000_set_lan_id_single_port, 5883 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5884 /* led_on dependent on mac type */ 5885 /* led_off dependent on mac type */ 5886 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5887 .reset_hw = e1000_reset_hw_ich8lan, 5888 .init_hw = e1000_init_hw_ich8lan, 5889 .setup_link = e1000_setup_link_ich8lan, 5890 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5891 /* id_led_init dependent on mac type */ 5892 .config_collision_dist = e1000e_config_collision_dist_generic, 5893 .rar_set = e1000e_rar_set_generic, 5894 .rar_get_count = e1000e_rar_get_count_generic, 5895 }; 5896 5897 static const struct e1000_phy_operations ich8_phy_ops = { 5898 .acquire = e1000_acquire_swflag_ich8lan, 5899 .check_reset_block = e1000_check_reset_block_ich8lan, 5900 .commit = NULL, 5901 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5902 .get_cable_length = e1000e_get_cable_length_igp_2, 5903 .read_reg = e1000e_read_phy_reg_igp, 5904 .release = e1000_release_swflag_ich8lan, 5905 .reset = e1000_phy_hw_reset_ich8lan, 5906 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5907 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5908 .write_reg = e1000e_write_phy_reg_igp, 5909 }; 5910 5911 static const struct e1000_nvm_operations ich8_nvm_ops = { 5912 .acquire = e1000_acquire_nvm_ich8lan, 5913 .read = e1000_read_nvm_ich8lan, 5914 .release = e1000_release_nvm_ich8lan, 5915 .reload = e1000e_reload_nvm_generic, 5916 .update = e1000_update_nvm_checksum_ich8lan, 5917 .valid_led_default = e1000_valid_led_default_ich8lan, 5918 .validate = e1000_validate_nvm_checksum_ich8lan, 5919 .write = e1000_write_nvm_ich8lan, 5920 }; 5921 5922 static const struct e1000_nvm_operations spt_nvm_ops = { 5923 .acquire = e1000_acquire_nvm_ich8lan, 5924 .release = e1000_release_nvm_ich8lan, 5925 .read = e1000_read_nvm_spt, 5926 .update = e1000_update_nvm_checksum_spt, 5927 .reload = e1000e_reload_nvm_generic, 5928 .valid_led_default = e1000_valid_led_default_ich8lan, 5929 .validate = e1000_validate_nvm_checksum_ich8lan, 5930 .write = e1000_write_nvm_ich8lan, 5931 }; 5932 5933 const struct e1000_info e1000_ich8_info = { 5934 .mac = e1000_ich8lan, 5935 .flags = FLAG_HAS_WOL 5936 | FLAG_IS_ICH 5937 | FLAG_HAS_CTRLEXT_ON_LOAD 5938 | FLAG_HAS_AMT 5939 | FLAG_HAS_FLASH 5940 | FLAG_APME_IN_WUC, 5941 .pba = 8, 5942 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 5943 .get_variants = e1000_get_variants_ich8lan, 5944 .mac_ops = &ich8_mac_ops, 5945 .phy_ops = &ich8_phy_ops, 5946 .nvm_ops = &ich8_nvm_ops, 5947 }; 5948 5949 const struct e1000_info e1000_ich9_info = { 5950 .mac = e1000_ich9lan, 5951 .flags = FLAG_HAS_JUMBO_FRAMES 5952 | FLAG_IS_ICH 5953 | FLAG_HAS_WOL 5954 | FLAG_HAS_CTRLEXT_ON_LOAD 5955 | FLAG_HAS_AMT 5956 | FLAG_HAS_FLASH 5957 | FLAG_APME_IN_WUC, 5958 .pba = 18, 5959 .max_hw_frame_size = DEFAULT_JUMBO, 5960 .get_variants = e1000_get_variants_ich8lan, 5961 .mac_ops = &ich8_mac_ops, 5962 .phy_ops = &ich8_phy_ops, 5963 .nvm_ops = &ich8_nvm_ops, 5964 }; 5965 5966 const struct e1000_info e1000_ich10_info = { 5967 .mac = e1000_ich10lan, 5968 .flags = FLAG_HAS_JUMBO_FRAMES 5969 | FLAG_IS_ICH 5970 | FLAG_HAS_WOL 5971 | FLAG_HAS_CTRLEXT_ON_LOAD 5972 | FLAG_HAS_AMT 5973 | FLAG_HAS_FLASH 5974 | FLAG_APME_IN_WUC, 5975 .pba = 18, 5976 .max_hw_frame_size = DEFAULT_JUMBO, 5977 .get_variants = e1000_get_variants_ich8lan, 5978 .mac_ops = &ich8_mac_ops, 5979 .phy_ops = &ich8_phy_ops, 5980 .nvm_ops = &ich8_nvm_ops, 5981 }; 5982 5983 const struct e1000_info e1000_pch_info = { 5984 .mac = e1000_pchlan, 5985 .flags = FLAG_IS_ICH 5986 | FLAG_HAS_WOL 5987 | FLAG_HAS_CTRLEXT_ON_LOAD 5988 | FLAG_HAS_AMT 5989 | FLAG_HAS_FLASH 5990 | FLAG_HAS_JUMBO_FRAMES 5991 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 5992 | FLAG_APME_IN_WUC, 5993 .flags2 = FLAG2_HAS_PHY_STATS, 5994 .pba = 26, 5995 .max_hw_frame_size = 4096, 5996 .get_variants = e1000_get_variants_ich8lan, 5997 .mac_ops = &ich8_mac_ops, 5998 .phy_ops = &ich8_phy_ops, 5999 .nvm_ops = &ich8_nvm_ops, 6000 }; 6001 6002 const struct e1000_info e1000_pch2_info = { 6003 .mac = e1000_pch2lan, 6004 .flags = FLAG_IS_ICH 6005 | FLAG_HAS_WOL 6006 | FLAG_HAS_HW_TIMESTAMP 6007 | FLAG_HAS_CTRLEXT_ON_LOAD 6008 | FLAG_HAS_AMT 6009 | FLAG_HAS_FLASH 6010 | FLAG_HAS_JUMBO_FRAMES 6011 | FLAG_APME_IN_WUC, 6012 .flags2 = FLAG2_HAS_PHY_STATS 6013 | FLAG2_HAS_EEE 6014 | FLAG2_CHECK_SYSTIM_OVERFLOW, 6015 .pba = 26, 6016 .max_hw_frame_size = 9022, 6017 .get_variants = e1000_get_variants_ich8lan, 6018 .mac_ops = &ich8_mac_ops, 6019 .phy_ops = &ich8_phy_ops, 6020 .nvm_ops = &ich8_nvm_ops, 6021 }; 6022 6023 const struct e1000_info e1000_pch_lpt_info = { 6024 .mac = e1000_pch_lpt, 6025 .flags = FLAG_IS_ICH 6026 | FLAG_HAS_WOL 6027 | FLAG_HAS_HW_TIMESTAMP 6028 | FLAG_HAS_CTRLEXT_ON_LOAD 6029 | FLAG_HAS_AMT 6030 | FLAG_HAS_FLASH 6031 | FLAG_HAS_JUMBO_FRAMES 6032 | FLAG_APME_IN_WUC, 6033 .flags2 = FLAG2_HAS_PHY_STATS 6034 | FLAG2_HAS_EEE 6035 | FLAG2_CHECK_SYSTIM_OVERFLOW, 6036 .pba = 26, 6037 .max_hw_frame_size = 9022, 6038 .get_variants = e1000_get_variants_ich8lan, 6039 .mac_ops = &ich8_mac_ops, 6040 .phy_ops = &ich8_phy_ops, 6041 .nvm_ops = &ich8_nvm_ops, 6042 }; 6043 6044 const struct e1000_info e1000_pch_spt_info = { 6045 .mac = e1000_pch_spt, 6046 .flags = FLAG_IS_ICH 6047 | FLAG_HAS_WOL 6048 | FLAG_HAS_HW_TIMESTAMP 6049 | FLAG_HAS_CTRLEXT_ON_LOAD 6050 | FLAG_HAS_AMT 6051 | FLAG_HAS_FLASH 6052 | FLAG_HAS_JUMBO_FRAMES 6053 | FLAG_APME_IN_WUC, 6054 .flags2 = FLAG2_HAS_PHY_STATS 6055 | FLAG2_HAS_EEE, 6056 .pba = 26, 6057 .max_hw_frame_size = 9022, 6058 .get_variants = e1000_get_variants_ich8lan, 6059 .mac_ops = &ich8_mac_ops, 6060 .phy_ops = &ich8_phy_ops, 6061 .nvm_ops = &spt_nvm_ops, 6062 }; 6063 6064 const struct e1000_info e1000_pch_cnp_info = { 6065 .mac = e1000_pch_cnp, 6066 .flags = FLAG_IS_ICH 6067 | FLAG_HAS_WOL 6068 | FLAG_HAS_HW_TIMESTAMP 6069 | FLAG_HAS_CTRLEXT_ON_LOAD 6070 | FLAG_HAS_AMT 6071 | FLAG_HAS_FLASH 6072 | FLAG_HAS_JUMBO_FRAMES 6073 | FLAG_APME_IN_WUC, 6074 .flags2 = FLAG2_HAS_PHY_STATS 6075 | FLAG2_HAS_EEE, 6076 .pba = 26, 6077 .max_hw_frame_size = 9022, 6078 .get_variants = e1000_get_variants_ich8lan, 6079 .mac_ops = &ich8_mac_ops, 6080 .phy_ops = &ich8_phy_ops, 6081 .nvm_ops = &spt_nvm_ops, 6082 }; 6083 6084 const struct e1000_info e1000_pch_tgp_info = { 6085 .mac = e1000_pch_tgp, 6086 .flags = FLAG_IS_ICH 6087 | FLAG_HAS_WOL 6088 | FLAG_HAS_HW_TIMESTAMP 6089 | FLAG_HAS_CTRLEXT_ON_LOAD 6090 | FLAG_HAS_AMT 6091 | FLAG_HAS_FLASH 6092 | FLAG_HAS_JUMBO_FRAMES 6093 | FLAG_APME_IN_WUC, 6094 .flags2 = FLAG2_HAS_PHY_STATS 6095 | FLAG2_HAS_EEE, 6096 .pba = 26, 6097 .max_hw_frame_size = 9022, 6098 .get_variants = e1000_get_variants_ich8lan, 6099 .mac_ops = &ich8_mac_ops, 6100 .phy_ops = &ich8_phy_ops, 6101 .nvm_ops = &spt_nvm_ops, 6102 }; 6103 6104 const struct e1000_info e1000_pch_adp_info = { 6105 .mac = e1000_pch_adp, 6106 .flags = FLAG_IS_ICH 6107 | FLAG_HAS_WOL 6108 | FLAG_HAS_HW_TIMESTAMP 6109 | FLAG_HAS_CTRLEXT_ON_LOAD 6110 | FLAG_HAS_AMT 6111 | FLAG_HAS_FLASH 6112 | FLAG_HAS_JUMBO_FRAMES 6113 | FLAG_APME_IN_WUC, 6114 .flags2 = FLAG2_HAS_PHY_STATS 6115 | FLAG2_HAS_EEE, 6116 .pba = 26, 6117 .max_hw_frame_size = 9022, 6118 .get_variants = e1000_get_variants_ich8lan, 6119 .mac_ops = &ich8_mac_ops, 6120 .phy_ops = &ich8_phy_ops, 6121 .nvm_ops = &spt_nvm_ops, 6122 }; 6123 6124 const struct e1000_info e1000_pch_mtp_info = { 6125 .mac = e1000_pch_mtp, 6126 .flags = FLAG_IS_ICH 6127 | FLAG_HAS_WOL 6128 | FLAG_HAS_HW_TIMESTAMP 6129 | FLAG_HAS_CTRLEXT_ON_LOAD 6130 | FLAG_HAS_AMT 6131 | FLAG_HAS_FLASH 6132 | FLAG_HAS_JUMBO_FRAMES 6133 | FLAG_APME_IN_WUC, 6134 .flags2 = FLAG2_HAS_PHY_STATS 6135 | FLAG2_HAS_EEE, 6136 .pba = 26, 6137 .max_hw_frame_size = 9022, 6138 .get_variants = e1000_get_variants_ich8lan, 6139 .mac_ops = &ich8_mac_ops, 6140 .phy_ops = &ich8_phy_ops, 6141 .nvm_ops = &spt_nvm_ops, 6142 }; 6143