1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 /* 82562G 10/100 Network Connection 23 * 82562G-2 10/100 Network Connection 24 * 82562GT 10/100 Network Connection 25 * 82562GT-2 10/100 Network Connection 26 * 82562V 10/100 Network Connection 27 * 82562V-2 10/100 Network Connection 28 * 82566DC-2 Gigabit Network Connection 29 * 82566DC Gigabit Network Connection 30 * 82566DM-2 Gigabit Network Connection 31 * 82566DM Gigabit Network Connection 32 * 82566MC Gigabit Network Connection 33 * 82566MM Gigabit Network Connection 34 * 82567LM Gigabit Network Connection 35 * 82567LF Gigabit Network Connection 36 * 82567V Gigabit Network Connection 37 * 82567LM-2 Gigabit Network Connection 38 * 82567LF-2 Gigabit Network Connection 39 * 82567V-2 Gigabit Network Connection 40 * 82567LF-3 Gigabit Network Connection 41 * 82567LM-3 Gigabit Network Connection 42 * 82567LM-4 Gigabit Network Connection 43 * 82577LM Gigabit Network Connection 44 * 82577LC Gigabit Network Connection 45 * 82578DM Gigabit Network Connection 46 * 82578DC Gigabit Network Connection 47 * 82579LM Gigabit Network Connection 48 * 82579V Gigabit Network Connection 49 * Ethernet Connection I217-LM 50 * Ethernet Connection I217-V 51 * Ethernet Connection I218-V 52 * Ethernet Connection I218-LM 53 * Ethernet Connection (2) I218-LM 54 * Ethernet Connection (2) I218-V 55 * Ethernet Connection (3) I218-LM 56 * Ethernet Connection (3) I218-V 57 */ 58 59 #include "e1000.h" 60 61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 62 /* Offset 04h HSFSTS */ 63 union ich8_hws_flash_status { 64 struct ich8_hsfsts { 65 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 66 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 67 u16 dael:1; /* bit 2 Direct Access error Log */ 68 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 69 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 70 u16 reserved1:2; /* bit 13:6 Reserved */ 71 u16 reserved2:6; /* bit 13:6 Reserved */ 72 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 73 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 74 } hsf_status; 75 u16 regval; 76 }; 77 78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 79 /* Offset 06h FLCTL */ 80 union ich8_hws_flash_ctrl { 81 struct ich8_hsflctl { 82 u16 flcgo:1; /* 0 Flash Cycle Go */ 83 u16 flcycle:2; /* 2:1 Flash Cycle */ 84 u16 reserved:5; /* 7:3 Reserved */ 85 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 86 u16 flockdn:6; /* 15:10 Reserved */ 87 } hsf_ctrl; 88 u16 regval; 89 }; 90 91 /* ICH Flash Region Access Permissions */ 92 union ich8_hws_flash_regacc { 93 struct ich8_flracc { 94 u32 grra:8; /* 0:7 GbE region Read Access */ 95 u32 grwa:8; /* 8:15 GbE region Write Access */ 96 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 97 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 98 } hsf_flregacc; 99 u16 regval; 100 }; 101 102 /* ICH Flash Protected Region */ 103 union ich8_flash_protected_range { 104 struct ich8_pr { 105 u32 base:13; /* 0:12 Protected Range Base */ 106 u32 reserved1:2; /* 13:14 Reserved */ 107 u32 rpe:1; /* 15 Read Protection Enable */ 108 u32 limit:13; /* 16:28 Protected Range Limit */ 109 u32 reserved2:2; /* 29:30 Reserved */ 110 u32 wpe:1; /* 31 Write Protection Enable */ 111 } range; 112 u32 regval; 113 }; 114 115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 119 u32 offset, u8 byte); 120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 121 u8 *data); 122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 123 u16 *data); 124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 125 u8 size, u16 *data); 126 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 127 u32 *data); 128 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 129 u32 offset, u32 *data); 130 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 131 u32 offset, u32 data); 132 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 133 u32 offset, u32 dword); 134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 135 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 136 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 137 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 138 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 139 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 140 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 141 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 142 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 143 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 145 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 146 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 147 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 150 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 151 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 152 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 153 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 155 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 156 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 157 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 158 159 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 160 { 161 return readw(hw->flash_address + reg); 162 } 163 164 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 165 { 166 return readl(hw->flash_address + reg); 167 } 168 169 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 170 { 171 writew(val, hw->flash_address + reg); 172 } 173 174 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 175 { 176 writel(val, hw->flash_address + reg); 177 } 178 179 #define er16flash(reg) __er16flash(hw, (reg)) 180 #define er32flash(reg) __er32flash(hw, (reg)) 181 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 182 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 183 184 /** 185 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 186 * @hw: pointer to the HW structure 187 * 188 * Test access to the PHY registers by reading the PHY ID registers. If 189 * the PHY ID is already known (e.g. resume path) compare it with known ID, 190 * otherwise assume the read PHY ID is correct if it is valid. 191 * 192 * Assumes the sw/fw/hw semaphore is already acquired. 193 **/ 194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 195 { 196 u16 phy_reg = 0; 197 u32 phy_id = 0; 198 s32 ret_val = 0; 199 u16 retry_count; 200 u32 mac_reg = 0; 201 202 for (retry_count = 0; retry_count < 2; retry_count++) { 203 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 204 if (ret_val || (phy_reg == 0xFFFF)) 205 continue; 206 phy_id = (u32)(phy_reg << 16); 207 208 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 209 if (ret_val || (phy_reg == 0xFFFF)) { 210 phy_id = 0; 211 continue; 212 } 213 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 214 break; 215 } 216 217 if (hw->phy.id) { 218 if (hw->phy.id == phy_id) 219 goto out; 220 } else if (phy_id) { 221 hw->phy.id = phy_id; 222 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 223 goto out; 224 } 225 226 /* In case the PHY needs to be in mdio slow mode, 227 * set slow mode and try to get the PHY id again. 228 */ 229 if (hw->mac.type < e1000_pch_lpt) { 230 hw->phy.ops.release(hw); 231 ret_val = e1000_set_mdio_slow_mode_hv(hw); 232 if (!ret_val) 233 ret_val = e1000e_get_phy_id(hw); 234 hw->phy.ops.acquire(hw); 235 } 236 237 if (ret_val) 238 return false; 239 out: 240 if (hw->mac.type >= e1000_pch_lpt) { 241 /* Only unforce SMBus if ME is not active */ 242 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 243 /* Unforce SMBus mode in PHY */ 244 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 245 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 246 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 247 248 /* Unforce SMBus mode in MAC */ 249 mac_reg = er32(CTRL_EXT); 250 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 251 ew32(CTRL_EXT, mac_reg); 252 } 253 } 254 255 return true; 256 } 257 258 /** 259 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 260 * @hw: pointer to the HW structure 261 * 262 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 263 * used to reset the PHY to a quiescent state when necessary. 264 **/ 265 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 266 { 267 u32 mac_reg; 268 269 /* Set Phy Config Counter to 50msec */ 270 mac_reg = er32(FEXTNVM3); 271 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 272 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 273 ew32(FEXTNVM3, mac_reg); 274 275 /* Toggle LANPHYPC Value bit */ 276 mac_reg = er32(CTRL); 277 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 278 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 279 ew32(CTRL, mac_reg); 280 e1e_flush(); 281 usleep_range(10, 20); 282 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 283 ew32(CTRL, mac_reg); 284 e1e_flush(); 285 286 if (hw->mac.type < e1000_pch_lpt) { 287 msleep(50); 288 } else { 289 u16 count = 20; 290 291 do { 292 usleep_range(5000, 10000); 293 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 294 295 msleep(30); 296 } 297 } 298 299 /** 300 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 301 * @hw: pointer to the HW structure 302 * 303 * Workarounds/flow necessary for PHY initialization during driver load 304 * and resume paths. 305 **/ 306 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 307 { 308 struct e1000_adapter *adapter = hw->adapter; 309 u32 mac_reg, fwsm = er32(FWSM); 310 s32 ret_val; 311 312 /* Gate automatic PHY configuration by hardware on managed and 313 * non-managed 82579 and newer adapters. 314 */ 315 e1000_gate_hw_phy_config_ich8lan(hw, true); 316 317 /* It is not possible to be certain of the current state of ULP 318 * so forcibly disable it. 319 */ 320 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 321 e1000_disable_ulp_lpt_lp(hw, true); 322 323 ret_val = hw->phy.ops.acquire(hw); 324 if (ret_val) { 325 e_dbg("Failed to initialize PHY flow\n"); 326 goto out; 327 } 328 329 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 330 * inaccessible and resetting the PHY is not blocked, toggle the 331 * LANPHYPC Value bit to force the interconnect to PCIe mode. 332 */ 333 switch (hw->mac.type) { 334 case e1000_pch_lpt: 335 case e1000_pch_spt: 336 case e1000_pch_cnp: 337 if (e1000_phy_is_accessible_pchlan(hw)) 338 break; 339 340 /* Before toggling LANPHYPC, see if PHY is accessible by 341 * forcing MAC to SMBus mode first. 342 */ 343 mac_reg = er32(CTRL_EXT); 344 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 345 ew32(CTRL_EXT, mac_reg); 346 347 /* Wait 50 milliseconds for MAC to finish any retries 348 * that it might be trying to perform from previous 349 * attempts to acknowledge any phy read requests. 350 */ 351 msleep(50); 352 353 /* fall-through */ 354 case e1000_pch2lan: 355 if (e1000_phy_is_accessible_pchlan(hw)) 356 break; 357 358 /* fall-through */ 359 case e1000_pchlan: 360 if ((hw->mac.type == e1000_pchlan) && 361 (fwsm & E1000_ICH_FWSM_FW_VALID)) 362 break; 363 364 if (hw->phy.ops.check_reset_block(hw)) { 365 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 366 ret_val = -E1000_ERR_PHY; 367 break; 368 } 369 370 /* Toggle LANPHYPC Value bit */ 371 e1000_toggle_lanphypc_pch_lpt(hw); 372 if (hw->mac.type >= e1000_pch_lpt) { 373 if (e1000_phy_is_accessible_pchlan(hw)) 374 break; 375 376 /* Toggling LANPHYPC brings the PHY out of SMBus mode 377 * so ensure that the MAC is also out of SMBus mode 378 */ 379 mac_reg = er32(CTRL_EXT); 380 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 381 ew32(CTRL_EXT, mac_reg); 382 383 if (e1000_phy_is_accessible_pchlan(hw)) 384 break; 385 386 ret_val = -E1000_ERR_PHY; 387 } 388 break; 389 default: 390 break; 391 } 392 393 hw->phy.ops.release(hw); 394 if (!ret_val) { 395 396 /* Check to see if able to reset PHY. Print error if not */ 397 if (hw->phy.ops.check_reset_block(hw)) { 398 e_err("Reset blocked by ME\n"); 399 goto out; 400 } 401 402 /* Reset the PHY before any access to it. Doing so, ensures 403 * that the PHY is in a known good state before we read/write 404 * PHY registers. The generic reset is sufficient here, 405 * because we haven't determined the PHY type yet. 406 */ 407 ret_val = e1000e_phy_hw_reset_generic(hw); 408 if (ret_val) 409 goto out; 410 411 /* On a successful reset, possibly need to wait for the PHY 412 * to quiesce to an accessible state before returning control 413 * to the calling function. If the PHY does not quiesce, then 414 * return E1000E_BLK_PHY_RESET, as this is the condition that 415 * the PHY is in. 416 */ 417 ret_val = hw->phy.ops.check_reset_block(hw); 418 if (ret_val) 419 e_err("ME blocked access to PHY after reset\n"); 420 } 421 422 out: 423 /* Ungate automatic PHY configuration on non-managed 82579 */ 424 if ((hw->mac.type == e1000_pch2lan) && 425 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 426 usleep_range(10000, 20000); 427 e1000_gate_hw_phy_config_ich8lan(hw, false); 428 } 429 430 return ret_val; 431 } 432 433 /** 434 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 435 * @hw: pointer to the HW structure 436 * 437 * Initialize family-specific PHY parameters and function pointers. 438 **/ 439 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 440 { 441 struct e1000_phy_info *phy = &hw->phy; 442 s32 ret_val; 443 444 phy->addr = 1; 445 phy->reset_delay_us = 100; 446 447 phy->ops.set_page = e1000_set_page_igp; 448 phy->ops.read_reg = e1000_read_phy_reg_hv; 449 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 450 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 451 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 452 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 453 phy->ops.write_reg = e1000_write_phy_reg_hv; 454 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 455 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 456 phy->ops.power_up = e1000_power_up_phy_copper; 457 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 458 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 459 460 phy->id = e1000_phy_unknown; 461 462 ret_val = e1000_init_phy_workarounds_pchlan(hw); 463 if (ret_val) 464 return ret_val; 465 466 if (phy->id == e1000_phy_unknown) 467 switch (hw->mac.type) { 468 default: 469 ret_val = e1000e_get_phy_id(hw); 470 if (ret_val) 471 return ret_val; 472 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 473 break; 474 /* fall-through */ 475 case e1000_pch2lan: 476 case e1000_pch_lpt: 477 case e1000_pch_spt: 478 case e1000_pch_cnp: 479 /* In case the PHY needs to be in mdio slow mode, 480 * set slow mode and try to get the PHY id again. 481 */ 482 ret_val = e1000_set_mdio_slow_mode_hv(hw); 483 if (ret_val) 484 return ret_val; 485 ret_val = e1000e_get_phy_id(hw); 486 if (ret_val) 487 return ret_val; 488 break; 489 } 490 phy->type = e1000e_get_phy_type_from_id(phy->id); 491 492 switch (phy->type) { 493 case e1000_phy_82577: 494 case e1000_phy_82579: 495 case e1000_phy_i217: 496 phy->ops.check_polarity = e1000_check_polarity_82577; 497 phy->ops.force_speed_duplex = 498 e1000_phy_force_speed_duplex_82577; 499 phy->ops.get_cable_length = e1000_get_cable_length_82577; 500 phy->ops.get_info = e1000_get_phy_info_82577; 501 phy->ops.commit = e1000e_phy_sw_reset; 502 break; 503 case e1000_phy_82578: 504 phy->ops.check_polarity = e1000_check_polarity_m88; 505 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 506 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 507 phy->ops.get_info = e1000e_get_phy_info_m88; 508 break; 509 default: 510 ret_val = -E1000_ERR_PHY; 511 break; 512 } 513 514 return ret_val; 515 } 516 517 /** 518 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 519 * @hw: pointer to the HW structure 520 * 521 * Initialize family-specific PHY parameters and function pointers. 522 **/ 523 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 524 { 525 struct e1000_phy_info *phy = &hw->phy; 526 s32 ret_val; 527 u16 i = 0; 528 529 phy->addr = 1; 530 phy->reset_delay_us = 100; 531 532 phy->ops.power_up = e1000_power_up_phy_copper; 533 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 534 535 /* We may need to do this twice - once for IGP and if that fails, 536 * we'll set BM func pointers and try again 537 */ 538 ret_val = e1000e_determine_phy_address(hw); 539 if (ret_val) { 540 phy->ops.write_reg = e1000e_write_phy_reg_bm; 541 phy->ops.read_reg = e1000e_read_phy_reg_bm; 542 ret_val = e1000e_determine_phy_address(hw); 543 if (ret_val) { 544 e_dbg("Cannot determine PHY addr. Erroring out\n"); 545 return ret_val; 546 } 547 } 548 549 phy->id = 0; 550 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 551 (i++ < 100)) { 552 usleep_range(1000, 2000); 553 ret_val = e1000e_get_phy_id(hw); 554 if (ret_val) 555 return ret_val; 556 } 557 558 /* Verify phy id */ 559 switch (phy->id) { 560 case IGP03E1000_E_PHY_ID: 561 phy->type = e1000_phy_igp_3; 562 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 563 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 564 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 565 phy->ops.get_info = e1000e_get_phy_info_igp; 566 phy->ops.check_polarity = e1000_check_polarity_igp; 567 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 568 break; 569 case IFE_E_PHY_ID: 570 case IFE_PLUS_E_PHY_ID: 571 case IFE_C_E_PHY_ID: 572 phy->type = e1000_phy_ife; 573 phy->autoneg_mask = E1000_ALL_NOT_GIG; 574 phy->ops.get_info = e1000_get_phy_info_ife; 575 phy->ops.check_polarity = e1000_check_polarity_ife; 576 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 577 break; 578 case BME1000_E_PHY_ID: 579 phy->type = e1000_phy_bm; 580 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 581 phy->ops.read_reg = e1000e_read_phy_reg_bm; 582 phy->ops.write_reg = e1000e_write_phy_reg_bm; 583 phy->ops.commit = e1000e_phy_sw_reset; 584 phy->ops.get_info = e1000e_get_phy_info_m88; 585 phy->ops.check_polarity = e1000_check_polarity_m88; 586 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 587 break; 588 default: 589 return -E1000_ERR_PHY; 590 } 591 592 return 0; 593 } 594 595 /** 596 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 597 * @hw: pointer to the HW structure 598 * 599 * Initialize family-specific NVM parameters and function 600 * pointers. 601 **/ 602 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 603 { 604 struct e1000_nvm_info *nvm = &hw->nvm; 605 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 606 u32 gfpreg, sector_base_addr, sector_end_addr; 607 u16 i; 608 u32 nvm_size; 609 610 nvm->type = e1000_nvm_flash_sw; 611 612 if (hw->mac.type >= e1000_pch_spt) { 613 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 614 * STRAP register. This is because in SPT the GbE Flash region 615 * is no longer accessed through the flash registers. Instead, 616 * the mechanism has changed, and the Flash region access 617 * registers are now implemented in GbE memory space. 618 */ 619 nvm->flash_base_addr = 0; 620 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 621 * NVM_SIZE_MULTIPLIER; 622 nvm->flash_bank_size = nvm_size / 2; 623 /* Adjust to word count */ 624 nvm->flash_bank_size /= sizeof(u16); 625 /* Set the base address for flash register access */ 626 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 627 } else { 628 /* Can't read flash registers if register set isn't mapped. */ 629 if (!hw->flash_address) { 630 e_dbg("ERROR: Flash registers not mapped\n"); 631 return -E1000_ERR_CONFIG; 632 } 633 634 gfpreg = er32flash(ICH_FLASH_GFPREG); 635 636 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 637 * Add 1 to sector_end_addr since this sector is included in 638 * the overall size. 639 */ 640 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 641 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 642 643 /* flash_base_addr is byte-aligned */ 644 nvm->flash_base_addr = sector_base_addr 645 << FLASH_SECTOR_ADDR_SHIFT; 646 647 /* find total size of the NVM, then cut in half since the total 648 * size represents two separate NVM banks. 649 */ 650 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 651 << FLASH_SECTOR_ADDR_SHIFT); 652 nvm->flash_bank_size /= 2; 653 /* Adjust to word count */ 654 nvm->flash_bank_size /= sizeof(u16); 655 } 656 657 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 658 659 /* Clear shadow ram */ 660 for (i = 0; i < nvm->word_size; i++) { 661 dev_spec->shadow_ram[i].modified = false; 662 dev_spec->shadow_ram[i].value = 0xFFFF; 663 } 664 665 return 0; 666 } 667 668 /** 669 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 670 * @hw: pointer to the HW structure 671 * 672 * Initialize family-specific MAC parameters and function 673 * pointers. 674 **/ 675 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 676 { 677 struct e1000_mac_info *mac = &hw->mac; 678 679 /* Set media type function pointer */ 680 hw->phy.media_type = e1000_media_type_copper; 681 682 /* Set mta register count */ 683 mac->mta_reg_count = 32; 684 /* Set rar entry count */ 685 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 686 if (mac->type == e1000_ich8lan) 687 mac->rar_entry_count--; 688 /* FWSM register */ 689 mac->has_fwsm = true; 690 /* ARC subsystem not supported */ 691 mac->arc_subsystem_valid = false; 692 /* Adaptive IFS supported */ 693 mac->adaptive_ifs = true; 694 695 /* LED and other operations */ 696 switch (mac->type) { 697 case e1000_ich8lan: 698 case e1000_ich9lan: 699 case e1000_ich10lan: 700 /* check management mode */ 701 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 702 /* ID LED init */ 703 mac->ops.id_led_init = e1000e_id_led_init_generic; 704 /* blink LED */ 705 mac->ops.blink_led = e1000e_blink_led_generic; 706 /* setup LED */ 707 mac->ops.setup_led = e1000e_setup_led_generic; 708 /* cleanup LED */ 709 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 710 /* turn on/off LED */ 711 mac->ops.led_on = e1000_led_on_ich8lan; 712 mac->ops.led_off = e1000_led_off_ich8lan; 713 break; 714 case e1000_pch2lan: 715 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 716 mac->ops.rar_set = e1000_rar_set_pch2lan; 717 /* fall-through */ 718 case e1000_pch_lpt: 719 case e1000_pch_spt: 720 case e1000_pch_cnp: 721 case e1000_pchlan: 722 /* check management mode */ 723 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 724 /* ID LED init */ 725 mac->ops.id_led_init = e1000_id_led_init_pchlan; 726 /* setup LED */ 727 mac->ops.setup_led = e1000_setup_led_pchlan; 728 /* cleanup LED */ 729 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 730 /* turn on/off LED */ 731 mac->ops.led_on = e1000_led_on_pchlan; 732 mac->ops.led_off = e1000_led_off_pchlan; 733 break; 734 default: 735 break; 736 } 737 738 if (mac->type >= e1000_pch_lpt) { 739 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 740 mac->ops.rar_set = e1000_rar_set_pch_lpt; 741 mac->ops.setup_physical_interface = 742 e1000_setup_copper_link_pch_lpt; 743 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 744 } 745 746 /* Enable PCS Lock-loss workaround for ICH8 */ 747 if (mac->type == e1000_ich8lan) 748 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 749 750 return 0; 751 } 752 753 /** 754 * __e1000_access_emi_reg_locked - Read/write EMI register 755 * @hw: pointer to the HW structure 756 * @addr: EMI address to program 757 * @data: pointer to value to read/write from/to the EMI address 758 * @read: boolean flag to indicate read or write 759 * 760 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 761 **/ 762 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 763 u16 *data, bool read) 764 { 765 s32 ret_val; 766 767 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 768 if (ret_val) 769 return ret_val; 770 771 if (read) 772 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 773 else 774 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 775 776 return ret_val; 777 } 778 779 /** 780 * e1000_read_emi_reg_locked - Read Extended Management Interface register 781 * @hw: pointer to the HW structure 782 * @addr: EMI address to program 783 * @data: value to be read from the EMI address 784 * 785 * Assumes the SW/FW/HW Semaphore is already acquired. 786 **/ 787 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 788 { 789 return __e1000_access_emi_reg_locked(hw, addr, data, true); 790 } 791 792 /** 793 * e1000_write_emi_reg_locked - Write Extended Management Interface register 794 * @hw: pointer to the HW structure 795 * @addr: EMI address to program 796 * @data: value to be written to the EMI address 797 * 798 * Assumes the SW/FW/HW Semaphore is already acquired. 799 **/ 800 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 801 { 802 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 803 } 804 805 /** 806 * e1000_set_eee_pchlan - Enable/disable EEE support 807 * @hw: pointer to the HW structure 808 * 809 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 810 * the link and the EEE capabilities of the link partner. The LPI Control 811 * register bits will remain set only if/when link is up. 812 * 813 * EEE LPI must not be asserted earlier than one second after link is up. 814 * On 82579, EEE LPI should not be enabled until such time otherwise there 815 * can be link issues with some switches. Other devices can have EEE LPI 816 * enabled immediately upon link up since they have a timer in hardware which 817 * prevents LPI from being asserted too early. 818 **/ 819 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 820 { 821 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 822 s32 ret_val; 823 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 824 825 switch (hw->phy.type) { 826 case e1000_phy_82579: 827 lpa = I82579_EEE_LP_ABILITY; 828 pcs_status = I82579_EEE_PCS_STATUS; 829 adv_addr = I82579_EEE_ADVERTISEMENT; 830 break; 831 case e1000_phy_i217: 832 lpa = I217_EEE_LP_ABILITY; 833 pcs_status = I217_EEE_PCS_STATUS; 834 adv_addr = I217_EEE_ADVERTISEMENT; 835 break; 836 default: 837 return 0; 838 } 839 840 ret_val = hw->phy.ops.acquire(hw); 841 if (ret_val) 842 return ret_val; 843 844 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 845 if (ret_val) 846 goto release; 847 848 /* Clear bits that enable EEE in various speeds */ 849 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 850 851 /* Enable EEE if not disabled by user */ 852 if (!dev_spec->eee_disable) { 853 /* Save off link partner's EEE ability */ 854 ret_val = e1000_read_emi_reg_locked(hw, lpa, 855 &dev_spec->eee_lp_ability); 856 if (ret_val) 857 goto release; 858 859 /* Read EEE advertisement */ 860 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 861 if (ret_val) 862 goto release; 863 864 /* Enable EEE only for speeds in which the link partner is 865 * EEE capable and for which we advertise EEE. 866 */ 867 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 868 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 869 870 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 871 e1e_rphy_locked(hw, MII_LPA, &data); 872 if (data & LPA_100FULL) 873 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 874 else 875 /* EEE is not supported in 100Half, so ignore 876 * partner's EEE in 100 ability if full-duplex 877 * is not advertised. 878 */ 879 dev_spec->eee_lp_ability &= 880 ~I82579_EEE_100_SUPPORTED; 881 } 882 } 883 884 if (hw->phy.type == e1000_phy_82579) { 885 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 886 &data); 887 if (ret_val) 888 goto release; 889 890 data &= ~I82579_LPI_100_PLL_SHUT; 891 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 892 data); 893 } 894 895 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 896 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 897 if (ret_val) 898 goto release; 899 900 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 901 release: 902 hw->phy.ops.release(hw); 903 904 return ret_val; 905 } 906 907 /** 908 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 909 * @hw: pointer to the HW structure 910 * @link: link up bool flag 911 * 912 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 913 * preventing further DMA write requests. Workaround the issue by disabling 914 * the de-assertion of the clock request when in 1Gpbs mode. 915 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 916 * speeds in order to avoid Tx hangs. 917 **/ 918 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 919 { 920 u32 fextnvm6 = er32(FEXTNVM6); 921 u32 status = er32(STATUS); 922 s32 ret_val = 0; 923 u16 reg; 924 925 if (link && (status & E1000_STATUS_SPEED_1000)) { 926 ret_val = hw->phy.ops.acquire(hw); 927 if (ret_val) 928 return ret_val; 929 930 ret_val = 931 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 932 ®); 933 if (ret_val) 934 goto release; 935 936 ret_val = 937 e1000e_write_kmrn_reg_locked(hw, 938 E1000_KMRNCTRLSTA_K1_CONFIG, 939 reg & 940 ~E1000_KMRNCTRLSTA_K1_ENABLE); 941 if (ret_val) 942 goto release; 943 944 usleep_range(10, 20); 945 946 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 947 948 ret_val = 949 e1000e_write_kmrn_reg_locked(hw, 950 E1000_KMRNCTRLSTA_K1_CONFIG, 951 reg); 952 release: 953 hw->phy.ops.release(hw); 954 } else { 955 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 956 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 957 958 if ((hw->phy.revision > 5) || !link || 959 ((status & E1000_STATUS_SPEED_100) && 960 (status & E1000_STATUS_FD))) 961 goto update_fextnvm6; 962 963 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 964 if (ret_val) 965 return ret_val; 966 967 /* Clear link status transmit timeout */ 968 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 969 970 if (status & E1000_STATUS_SPEED_100) { 971 /* Set inband Tx timeout to 5x10us for 100Half */ 972 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 973 974 /* Do not extend the K1 entry latency for 100Half */ 975 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 976 } else { 977 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 978 reg |= 50 << 979 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 980 981 /* Extend the K1 entry latency for 10 Mbps */ 982 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 983 } 984 985 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 986 if (ret_val) 987 return ret_val; 988 989 update_fextnvm6: 990 ew32(FEXTNVM6, fextnvm6); 991 } 992 993 return ret_val; 994 } 995 996 /** 997 * e1000_platform_pm_pch_lpt - Set platform power management values 998 * @hw: pointer to the HW structure 999 * @link: bool indicating link status 1000 * 1001 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1002 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1003 * when link is up (which must not exceed the maximum latency supported 1004 * by the platform), otherwise specify there is no LTR requirement. 1005 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 1006 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1007 * Capability register set, on this device LTR is set by writing the 1008 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1009 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1010 * message to the PMC. 1011 **/ 1012 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1013 { 1014 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1015 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1016 u16 lat_enc = 0; /* latency encoded */ 1017 1018 if (link) { 1019 u16 speed, duplex, scale = 0; 1020 u16 max_snoop, max_nosnoop; 1021 u16 max_ltr_enc; /* max LTR latency encoded */ 1022 u64 value; 1023 u32 rxa; 1024 1025 if (!hw->adapter->max_frame_size) { 1026 e_dbg("max_frame_size not set.\n"); 1027 return -E1000_ERR_CONFIG; 1028 } 1029 1030 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1031 if (!speed) { 1032 e_dbg("Speed not set.\n"); 1033 return -E1000_ERR_CONFIG; 1034 } 1035 1036 /* Rx Packet Buffer Allocation size (KB) */ 1037 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1038 1039 /* Determine the maximum latency tolerated by the device. 1040 * 1041 * Per the PCIe spec, the tolerated latencies are encoded as 1042 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1043 * a 10-bit value (0-1023) to provide a range from 1 ns to 1044 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1045 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1046 */ 1047 rxa *= 512; 1048 value = (rxa > hw->adapter->max_frame_size) ? 1049 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1050 0; 1051 1052 while (value > PCI_LTR_VALUE_MASK) { 1053 scale++; 1054 value = DIV_ROUND_UP(value, BIT(5)); 1055 } 1056 if (scale > E1000_LTRV_SCALE_MAX) { 1057 e_dbg("Invalid LTR latency scale %d\n", scale); 1058 return -E1000_ERR_CONFIG; 1059 } 1060 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1061 1062 /* Determine the maximum latency tolerated by the platform */ 1063 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1064 &max_snoop); 1065 pci_read_config_word(hw->adapter->pdev, 1066 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1067 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1068 1069 if (lat_enc > max_ltr_enc) 1070 lat_enc = max_ltr_enc; 1071 } 1072 1073 /* Set Snoop and No-Snoop latencies the same */ 1074 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1075 ew32(LTRV, reg); 1076 1077 return 0; 1078 } 1079 1080 /** 1081 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1082 * @hw: pointer to the HW structure 1083 * @to_sx: boolean indicating a system power state transition to Sx 1084 * 1085 * When link is down, configure ULP mode to significantly reduce the power 1086 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1087 * ME firmware to start the ULP configuration. If not on an ME enabled 1088 * system, configure the ULP mode by software. 1089 */ 1090 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1091 { 1092 u32 mac_reg; 1093 s32 ret_val = 0; 1094 u16 phy_reg; 1095 u16 oem_reg = 0; 1096 1097 if ((hw->mac.type < e1000_pch_lpt) || 1098 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1099 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1100 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1101 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1102 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1103 return 0; 1104 1105 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1106 /* Request ME configure ULP mode in the PHY */ 1107 mac_reg = er32(H2ME); 1108 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1109 ew32(H2ME, mac_reg); 1110 1111 goto out; 1112 } 1113 1114 if (!to_sx) { 1115 int i = 0; 1116 1117 /* Poll up to 5 seconds for Cable Disconnected indication */ 1118 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1119 /* Bail if link is re-acquired */ 1120 if (er32(STATUS) & E1000_STATUS_LU) 1121 return -E1000_ERR_PHY; 1122 1123 if (i++ == 100) 1124 break; 1125 1126 msleep(50); 1127 } 1128 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1129 (er32(FEXT) & 1130 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1131 } 1132 1133 ret_val = hw->phy.ops.acquire(hw); 1134 if (ret_val) 1135 goto out; 1136 1137 /* Force SMBus mode in PHY */ 1138 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1139 if (ret_val) 1140 goto release; 1141 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1142 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1143 1144 /* Force SMBus mode in MAC */ 1145 mac_reg = er32(CTRL_EXT); 1146 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1147 ew32(CTRL_EXT, mac_reg); 1148 1149 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1150 * LPLU and disable Gig speed when entering ULP 1151 */ 1152 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1153 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1154 &oem_reg); 1155 if (ret_val) 1156 goto release; 1157 1158 phy_reg = oem_reg; 1159 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1160 1161 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1162 phy_reg); 1163 1164 if (ret_val) 1165 goto release; 1166 } 1167 1168 /* Set Inband ULP Exit, Reset to SMBus mode and 1169 * Disable SMBus Release on PERST# in PHY 1170 */ 1171 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1172 if (ret_val) 1173 goto release; 1174 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1175 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1176 if (to_sx) { 1177 if (er32(WUFC) & E1000_WUFC_LNKC) 1178 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1179 else 1180 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1181 1182 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1183 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1184 } else { 1185 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1186 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1187 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1188 } 1189 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1190 1191 /* Set Disable SMBus Release on PERST# in MAC */ 1192 mac_reg = er32(FEXTNVM7); 1193 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1194 ew32(FEXTNVM7, mac_reg); 1195 1196 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1197 phy_reg |= I218_ULP_CONFIG1_START; 1198 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1199 1200 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1201 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1202 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1203 oem_reg); 1204 if (ret_val) 1205 goto release; 1206 } 1207 1208 release: 1209 hw->phy.ops.release(hw); 1210 out: 1211 if (ret_val) 1212 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1213 else 1214 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1215 1216 return ret_val; 1217 } 1218 1219 /** 1220 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1221 * @hw: pointer to the HW structure 1222 * @force: boolean indicating whether or not to force disabling ULP 1223 * 1224 * Un-configure ULP mode when link is up, the system is transitioned from 1225 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1226 * system, poll for an indication from ME that ULP has been un-configured. 1227 * If not on an ME enabled system, un-configure the ULP mode by software. 1228 * 1229 * During nominal operation, this function is called when link is acquired 1230 * to disable ULP mode (force=false); otherwise, for example when unloading 1231 * the driver or during Sx->S0 transitions, this is called with force=true 1232 * to forcibly disable ULP. 1233 */ 1234 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1235 { 1236 s32 ret_val = 0; 1237 u32 mac_reg; 1238 u16 phy_reg; 1239 int i = 0; 1240 1241 if ((hw->mac.type < e1000_pch_lpt) || 1242 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1243 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1244 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1245 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1246 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1247 return 0; 1248 1249 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1250 if (force) { 1251 /* Request ME un-configure ULP mode in the PHY */ 1252 mac_reg = er32(H2ME); 1253 mac_reg &= ~E1000_H2ME_ULP; 1254 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1255 ew32(H2ME, mac_reg); 1256 } 1257 1258 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1259 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1260 if (i++ == 30) { 1261 ret_val = -E1000_ERR_PHY; 1262 goto out; 1263 } 1264 1265 usleep_range(10000, 20000); 1266 } 1267 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1268 1269 if (force) { 1270 mac_reg = er32(H2ME); 1271 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1272 ew32(H2ME, mac_reg); 1273 } else { 1274 /* Clear H2ME.ULP after ME ULP configuration */ 1275 mac_reg = er32(H2ME); 1276 mac_reg &= ~E1000_H2ME_ULP; 1277 ew32(H2ME, mac_reg); 1278 } 1279 1280 goto out; 1281 } 1282 1283 ret_val = hw->phy.ops.acquire(hw); 1284 if (ret_val) 1285 goto out; 1286 1287 if (force) 1288 /* Toggle LANPHYPC Value bit */ 1289 e1000_toggle_lanphypc_pch_lpt(hw); 1290 1291 /* Unforce SMBus mode in PHY */ 1292 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1293 if (ret_val) { 1294 /* The MAC might be in PCIe mode, so temporarily force to 1295 * SMBus mode in order to access the PHY. 1296 */ 1297 mac_reg = er32(CTRL_EXT); 1298 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1299 ew32(CTRL_EXT, mac_reg); 1300 1301 msleep(50); 1302 1303 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1304 &phy_reg); 1305 if (ret_val) 1306 goto release; 1307 } 1308 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1309 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1310 1311 /* Unforce SMBus mode in MAC */ 1312 mac_reg = er32(CTRL_EXT); 1313 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1314 ew32(CTRL_EXT, mac_reg); 1315 1316 /* When ULP mode was previously entered, K1 was disabled by the 1317 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1318 */ 1319 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1320 if (ret_val) 1321 goto release; 1322 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1323 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1324 1325 /* Clear ULP enabled configuration */ 1326 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1327 if (ret_val) 1328 goto release; 1329 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1330 I218_ULP_CONFIG1_STICKY_ULP | 1331 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1332 I218_ULP_CONFIG1_WOL_HOST | 1333 I218_ULP_CONFIG1_INBAND_EXIT | 1334 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1335 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1336 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1337 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1338 1339 /* Commit ULP changes by starting auto ULP configuration */ 1340 phy_reg |= I218_ULP_CONFIG1_START; 1341 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1342 1343 /* Clear Disable SMBus Release on PERST# in MAC */ 1344 mac_reg = er32(FEXTNVM7); 1345 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1346 ew32(FEXTNVM7, mac_reg); 1347 1348 release: 1349 hw->phy.ops.release(hw); 1350 if (force) { 1351 e1000_phy_hw_reset(hw); 1352 msleep(50); 1353 } 1354 out: 1355 if (ret_val) 1356 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1357 else 1358 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1359 1360 return ret_val; 1361 } 1362 1363 /** 1364 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1365 * @hw: pointer to the HW structure 1366 * 1367 * Checks to see of the link status of the hardware has changed. If a 1368 * change in link status has been detected, then we read the PHY registers 1369 * to get the current speed/duplex if link exists. 1370 **/ 1371 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1372 { 1373 struct e1000_mac_info *mac = &hw->mac; 1374 s32 ret_val, tipg_reg = 0; 1375 u16 emi_addr, emi_val = 0; 1376 bool link; 1377 u16 phy_reg; 1378 1379 /* We only want to go out to the PHY registers to see if Auto-Neg 1380 * has completed and/or if our link status has changed. The 1381 * get_link_status flag is set upon receiving a Link Status 1382 * Change or Rx Sequence Error interrupt. 1383 */ 1384 if (!mac->get_link_status) 1385 return 0; 1386 mac->get_link_status = false; 1387 1388 /* First we want to see if the MII Status Register reports 1389 * link. If so, then we want to get the current speed/duplex 1390 * of the PHY. 1391 */ 1392 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1393 if (ret_val) 1394 goto out; 1395 1396 if (hw->mac.type == e1000_pchlan) { 1397 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1398 if (ret_val) 1399 goto out; 1400 } 1401 1402 /* When connected at 10Mbps half-duplex, some parts are excessively 1403 * aggressive resulting in many collisions. To avoid this, increase 1404 * the IPG and reduce Rx latency in the PHY. 1405 */ 1406 if ((hw->mac.type >= e1000_pch2lan) && link) { 1407 u16 speed, duplex; 1408 1409 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1410 tipg_reg = er32(TIPG); 1411 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1412 1413 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1414 tipg_reg |= 0xFF; 1415 /* Reduce Rx latency in analog PHY */ 1416 emi_val = 0; 1417 } else if (hw->mac.type >= e1000_pch_spt && 1418 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1419 tipg_reg |= 0xC; 1420 emi_val = 1; 1421 } else { 1422 1423 /* Roll back the default values */ 1424 tipg_reg |= 0x08; 1425 emi_val = 1; 1426 } 1427 1428 ew32(TIPG, tipg_reg); 1429 1430 ret_val = hw->phy.ops.acquire(hw); 1431 if (ret_val) 1432 goto out; 1433 1434 if (hw->mac.type == e1000_pch2lan) 1435 emi_addr = I82579_RX_CONFIG; 1436 else 1437 emi_addr = I217_RX_CONFIG; 1438 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1439 1440 if (hw->mac.type >= e1000_pch_lpt) { 1441 u16 phy_reg; 1442 1443 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1444 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1445 if (speed == SPEED_100 || speed == SPEED_10) 1446 phy_reg |= 0x3E8; 1447 else 1448 phy_reg |= 0xFA; 1449 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1450 } 1451 hw->phy.ops.release(hw); 1452 1453 if (ret_val) 1454 goto out; 1455 1456 if (hw->mac.type >= e1000_pch_spt) { 1457 u16 data; 1458 u16 ptr_gap; 1459 1460 if (speed == SPEED_1000) { 1461 ret_val = hw->phy.ops.acquire(hw); 1462 if (ret_val) 1463 goto out; 1464 1465 ret_val = e1e_rphy_locked(hw, 1466 PHY_REG(776, 20), 1467 &data); 1468 if (ret_val) { 1469 hw->phy.ops.release(hw); 1470 goto out; 1471 } 1472 1473 ptr_gap = (data & (0x3FF << 2)) >> 2; 1474 if (ptr_gap < 0x18) { 1475 data &= ~(0x3FF << 2); 1476 data |= (0x18 << 2); 1477 ret_val = 1478 e1e_wphy_locked(hw, 1479 PHY_REG(776, 20), 1480 data); 1481 } 1482 hw->phy.ops.release(hw); 1483 if (ret_val) 1484 goto out; 1485 } else { 1486 ret_val = hw->phy.ops.acquire(hw); 1487 if (ret_val) 1488 goto out; 1489 1490 ret_val = e1e_wphy_locked(hw, 1491 PHY_REG(776, 20), 1492 0xC023); 1493 hw->phy.ops.release(hw); 1494 if (ret_val) 1495 goto out; 1496 1497 } 1498 } 1499 } 1500 1501 /* I217 Packet Loss issue: 1502 * ensure that FEXTNVM4 Beacon Duration is set correctly 1503 * on power up. 1504 * Set the Beacon Duration for I217 to 8 usec 1505 */ 1506 if (hw->mac.type >= e1000_pch_lpt) { 1507 u32 mac_reg; 1508 1509 mac_reg = er32(FEXTNVM4); 1510 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1511 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1512 ew32(FEXTNVM4, mac_reg); 1513 } 1514 1515 /* Work-around I218 hang issue */ 1516 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1517 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1518 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1519 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1520 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1521 if (ret_val) 1522 goto out; 1523 } 1524 if (hw->mac.type >= e1000_pch_lpt) { 1525 /* Set platform power management values for 1526 * Latency Tolerance Reporting (LTR) 1527 */ 1528 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1529 if (ret_val) 1530 goto out; 1531 } 1532 1533 /* Clear link partner's EEE ability */ 1534 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1535 1536 if (hw->mac.type >= e1000_pch_lpt) { 1537 u32 fextnvm6 = er32(FEXTNVM6); 1538 1539 if (hw->mac.type == e1000_pch_spt) { 1540 /* FEXTNVM6 K1-off workaround - for SPT only */ 1541 u32 pcieanacfg = er32(PCIEANACFG); 1542 1543 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1544 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1545 else 1546 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1547 } 1548 1549 ew32(FEXTNVM6, fextnvm6); 1550 } 1551 1552 if (!link) 1553 goto out; 1554 1555 switch (hw->mac.type) { 1556 case e1000_pch2lan: 1557 ret_val = e1000_k1_workaround_lv(hw); 1558 if (ret_val) 1559 return ret_val; 1560 /* fall-thru */ 1561 case e1000_pchlan: 1562 if (hw->phy.type == e1000_phy_82578) { 1563 ret_val = e1000_link_stall_workaround_hv(hw); 1564 if (ret_val) 1565 return ret_val; 1566 } 1567 1568 /* Workaround for PCHx parts in half-duplex: 1569 * Set the number of preambles removed from the packet 1570 * when it is passed from the PHY to the MAC to prevent 1571 * the MAC from misinterpreting the packet type. 1572 */ 1573 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1574 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1575 1576 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1577 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1578 1579 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1580 break; 1581 default: 1582 break; 1583 } 1584 1585 /* Check if there was DownShift, must be checked 1586 * immediately after link-up 1587 */ 1588 e1000e_check_downshift(hw); 1589 1590 /* Enable/Disable EEE after link up */ 1591 if (hw->phy.type > e1000_phy_82579) { 1592 ret_val = e1000_set_eee_pchlan(hw); 1593 if (ret_val) 1594 return ret_val; 1595 } 1596 1597 /* If we are forcing speed/duplex, then we simply return since 1598 * we have already determined whether we have link or not. 1599 */ 1600 if (!mac->autoneg) 1601 return -E1000_ERR_CONFIG; 1602 1603 /* Auto-Neg is enabled. Auto Speed Detection takes care 1604 * of MAC speed/duplex configuration. So we only need to 1605 * configure Collision Distance in the MAC. 1606 */ 1607 mac->ops.config_collision_dist(hw); 1608 1609 /* Configure Flow Control now that Auto-Neg has completed. 1610 * First, we need to restore the desired flow control 1611 * settings because we may have had to re-autoneg with a 1612 * different link partner. 1613 */ 1614 ret_val = e1000e_config_fc_after_link_up(hw); 1615 if (ret_val) 1616 e_dbg("Error configuring flow control\n"); 1617 1618 return ret_val; 1619 1620 out: 1621 mac->get_link_status = true; 1622 return ret_val; 1623 } 1624 1625 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1626 { 1627 struct e1000_hw *hw = &adapter->hw; 1628 s32 rc; 1629 1630 rc = e1000_init_mac_params_ich8lan(hw); 1631 if (rc) 1632 return rc; 1633 1634 rc = e1000_init_nvm_params_ich8lan(hw); 1635 if (rc) 1636 return rc; 1637 1638 switch (hw->mac.type) { 1639 case e1000_ich8lan: 1640 case e1000_ich9lan: 1641 case e1000_ich10lan: 1642 rc = e1000_init_phy_params_ich8lan(hw); 1643 break; 1644 case e1000_pchlan: 1645 case e1000_pch2lan: 1646 case e1000_pch_lpt: 1647 case e1000_pch_spt: 1648 case e1000_pch_cnp: 1649 rc = e1000_init_phy_params_pchlan(hw); 1650 break; 1651 default: 1652 break; 1653 } 1654 if (rc) 1655 return rc; 1656 1657 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1658 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1659 */ 1660 if ((adapter->hw.phy.type == e1000_phy_ife) || 1661 ((adapter->hw.mac.type >= e1000_pch2lan) && 1662 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1663 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1664 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1665 1666 hw->mac.ops.blink_led = NULL; 1667 } 1668 1669 if ((adapter->hw.mac.type == e1000_ich8lan) && 1670 (adapter->hw.phy.type != e1000_phy_ife)) 1671 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1672 1673 /* Enable workaround for 82579 w/ ME enabled */ 1674 if ((adapter->hw.mac.type == e1000_pch2lan) && 1675 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1676 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1677 1678 return 0; 1679 } 1680 1681 static DEFINE_MUTEX(nvm_mutex); 1682 1683 /** 1684 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1685 * @hw: pointer to the HW structure 1686 * 1687 * Acquires the mutex for performing NVM operations. 1688 **/ 1689 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1690 { 1691 mutex_lock(&nvm_mutex); 1692 1693 return 0; 1694 } 1695 1696 /** 1697 * e1000_release_nvm_ich8lan - Release NVM mutex 1698 * @hw: pointer to the HW structure 1699 * 1700 * Releases the mutex used while performing NVM operations. 1701 **/ 1702 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1703 { 1704 mutex_unlock(&nvm_mutex); 1705 } 1706 1707 /** 1708 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1709 * @hw: pointer to the HW structure 1710 * 1711 * Acquires the software control flag for performing PHY and select 1712 * MAC CSR accesses. 1713 **/ 1714 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1715 { 1716 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1717 s32 ret_val = 0; 1718 1719 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1720 &hw->adapter->state)) { 1721 e_dbg("contention for Phy access\n"); 1722 return -E1000_ERR_PHY; 1723 } 1724 1725 while (timeout) { 1726 extcnf_ctrl = er32(EXTCNF_CTRL); 1727 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1728 break; 1729 1730 mdelay(1); 1731 timeout--; 1732 } 1733 1734 if (!timeout) { 1735 e_dbg("SW has already locked the resource.\n"); 1736 ret_val = -E1000_ERR_CONFIG; 1737 goto out; 1738 } 1739 1740 timeout = SW_FLAG_TIMEOUT; 1741 1742 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1743 ew32(EXTCNF_CTRL, extcnf_ctrl); 1744 1745 while (timeout) { 1746 extcnf_ctrl = er32(EXTCNF_CTRL); 1747 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1748 break; 1749 1750 mdelay(1); 1751 timeout--; 1752 } 1753 1754 if (!timeout) { 1755 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1756 er32(FWSM), extcnf_ctrl); 1757 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1758 ew32(EXTCNF_CTRL, extcnf_ctrl); 1759 ret_val = -E1000_ERR_CONFIG; 1760 goto out; 1761 } 1762 1763 out: 1764 if (ret_val) 1765 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1766 1767 return ret_val; 1768 } 1769 1770 /** 1771 * e1000_release_swflag_ich8lan - Release software control flag 1772 * @hw: pointer to the HW structure 1773 * 1774 * Releases the software control flag for performing PHY and select 1775 * MAC CSR accesses. 1776 **/ 1777 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1778 { 1779 u32 extcnf_ctrl; 1780 1781 extcnf_ctrl = er32(EXTCNF_CTRL); 1782 1783 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1784 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1785 ew32(EXTCNF_CTRL, extcnf_ctrl); 1786 } else { 1787 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1788 } 1789 1790 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1791 } 1792 1793 /** 1794 * e1000_check_mng_mode_ich8lan - Checks management mode 1795 * @hw: pointer to the HW structure 1796 * 1797 * This checks if the adapter has any manageability enabled. 1798 * This is a function pointer entry point only called by read/write 1799 * routines for the PHY and NVM parts. 1800 **/ 1801 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1802 { 1803 u32 fwsm; 1804 1805 fwsm = er32(FWSM); 1806 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1807 ((fwsm & E1000_FWSM_MODE_MASK) == 1808 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1809 } 1810 1811 /** 1812 * e1000_check_mng_mode_pchlan - Checks management mode 1813 * @hw: pointer to the HW structure 1814 * 1815 * This checks if the adapter has iAMT enabled. 1816 * This is a function pointer entry point only called by read/write 1817 * routines for the PHY and NVM parts. 1818 **/ 1819 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1820 { 1821 u32 fwsm; 1822 1823 fwsm = er32(FWSM); 1824 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1825 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1826 } 1827 1828 /** 1829 * e1000_rar_set_pch2lan - Set receive address register 1830 * @hw: pointer to the HW structure 1831 * @addr: pointer to the receive address 1832 * @index: receive address array register 1833 * 1834 * Sets the receive address array register at index to the address passed 1835 * in by addr. For 82579, RAR[0] is the base address register that is to 1836 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1837 * Use SHRA[0-3] in place of those reserved for ME. 1838 **/ 1839 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1840 { 1841 u32 rar_low, rar_high; 1842 1843 /* HW expects these in little endian so we reverse the byte order 1844 * from network order (big endian) to little endian 1845 */ 1846 rar_low = ((u32)addr[0] | 1847 ((u32)addr[1] << 8) | 1848 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1849 1850 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1851 1852 /* If MAC address zero, no need to set the AV bit */ 1853 if (rar_low || rar_high) 1854 rar_high |= E1000_RAH_AV; 1855 1856 if (index == 0) { 1857 ew32(RAL(index), rar_low); 1858 e1e_flush(); 1859 ew32(RAH(index), rar_high); 1860 e1e_flush(); 1861 return 0; 1862 } 1863 1864 /* RAR[1-6] are owned by manageability. Skip those and program the 1865 * next address into the SHRA register array. 1866 */ 1867 if (index < (u32)(hw->mac.rar_entry_count)) { 1868 s32 ret_val; 1869 1870 ret_val = e1000_acquire_swflag_ich8lan(hw); 1871 if (ret_val) 1872 goto out; 1873 1874 ew32(SHRAL(index - 1), rar_low); 1875 e1e_flush(); 1876 ew32(SHRAH(index - 1), rar_high); 1877 e1e_flush(); 1878 1879 e1000_release_swflag_ich8lan(hw); 1880 1881 /* verify the register updates */ 1882 if ((er32(SHRAL(index - 1)) == rar_low) && 1883 (er32(SHRAH(index - 1)) == rar_high)) 1884 return 0; 1885 1886 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1887 (index - 1), er32(FWSM)); 1888 } 1889 1890 out: 1891 e_dbg("Failed to write receive address at index %d\n", index); 1892 return -E1000_ERR_CONFIG; 1893 } 1894 1895 /** 1896 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 1897 * @hw: pointer to the HW structure 1898 * 1899 * Get the number of available receive registers that the Host can 1900 * program. SHRA[0-10] are the shared receive address registers 1901 * that are shared between the Host and manageability engine (ME). 1902 * ME can reserve any number of addresses and the host needs to be 1903 * able to tell how many available registers it has access to. 1904 **/ 1905 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 1906 { 1907 u32 wlock_mac; 1908 u32 num_entries; 1909 1910 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1911 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1912 1913 switch (wlock_mac) { 1914 case 0: 1915 /* All SHRA[0..10] and RAR[0] available */ 1916 num_entries = hw->mac.rar_entry_count; 1917 break; 1918 case 1: 1919 /* Only RAR[0] available */ 1920 num_entries = 1; 1921 break; 1922 default: 1923 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 1924 num_entries = wlock_mac + 1; 1925 break; 1926 } 1927 1928 return num_entries; 1929 } 1930 1931 /** 1932 * e1000_rar_set_pch_lpt - Set receive address registers 1933 * @hw: pointer to the HW structure 1934 * @addr: pointer to the receive address 1935 * @index: receive address array register 1936 * 1937 * Sets the receive address register array at index to the address passed 1938 * in by addr. For LPT, RAR[0] is the base address register that is to 1939 * contain the MAC address. SHRA[0-10] are the shared receive address 1940 * registers that are shared between the Host and manageability engine (ME). 1941 **/ 1942 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 1943 { 1944 u32 rar_low, rar_high; 1945 u32 wlock_mac; 1946 1947 /* HW expects these in little endian so we reverse the byte order 1948 * from network order (big endian) to little endian 1949 */ 1950 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 1951 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1952 1953 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1954 1955 /* If MAC address zero, no need to set the AV bit */ 1956 if (rar_low || rar_high) 1957 rar_high |= E1000_RAH_AV; 1958 1959 if (index == 0) { 1960 ew32(RAL(index), rar_low); 1961 e1e_flush(); 1962 ew32(RAH(index), rar_high); 1963 e1e_flush(); 1964 return 0; 1965 } 1966 1967 /* The manageability engine (ME) can lock certain SHRAR registers that 1968 * it is using - those registers are unavailable for use. 1969 */ 1970 if (index < hw->mac.rar_entry_count) { 1971 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1972 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1973 1974 /* Check if all SHRAR registers are locked */ 1975 if (wlock_mac == 1) 1976 goto out; 1977 1978 if ((wlock_mac == 0) || (index <= wlock_mac)) { 1979 s32 ret_val; 1980 1981 ret_val = e1000_acquire_swflag_ich8lan(hw); 1982 1983 if (ret_val) 1984 goto out; 1985 1986 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 1987 e1e_flush(); 1988 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 1989 e1e_flush(); 1990 1991 e1000_release_swflag_ich8lan(hw); 1992 1993 /* verify the register updates */ 1994 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 1995 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 1996 return 0; 1997 } 1998 } 1999 2000 out: 2001 e_dbg("Failed to write receive address at index %d\n", index); 2002 return -E1000_ERR_CONFIG; 2003 } 2004 2005 /** 2006 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2007 * @hw: pointer to the HW structure 2008 * 2009 * Checks if firmware is blocking the reset of the PHY. 2010 * This is a function pointer entry point only called by 2011 * reset routines. 2012 **/ 2013 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2014 { 2015 bool blocked = false; 2016 int i = 0; 2017 2018 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2019 (i++ < 30)) 2020 usleep_range(10000, 20000); 2021 return blocked ? E1000_BLK_PHY_RESET : 0; 2022 } 2023 2024 /** 2025 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2026 * @hw: pointer to the HW structure 2027 * 2028 * Assumes semaphore already acquired. 2029 * 2030 **/ 2031 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2032 { 2033 u16 phy_data; 2034 u32 strap = er32(STRAP); 2035 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2036 E1000_STRAP_SMT_FREQ_SHIFT; 2037 s32 ret_val; 2038 2039 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2040 2041 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2042 if (ret_val) 2043 return ret_val; 2044 2045 phy_data &= ~HV_SMB_ADDR_MASK; 2046 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2047 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2048 2049 if (hw->phy.type == e1000_phy_i217) { 2050 /* Restore SMBus frequency */ 2051 if (freq--) { 2052 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2053 phy_data |= (freq & BIT(0)) << 2054 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2055 phy_data |= (freq & BIT(1)) << 2056 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2057 } else { 2058 e_dbg("Unsupported SMB frequency in PHY\n"); 2059 } 2060 } 2061 2062 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2063 } 2064 2065 /** 2066 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2067 * @hw: pointer to the HW structure 2068 * 2069 * SW should configure the LCD from the NVM extended configuration region 2070 * as a workaround for certain parts. 2071 **/ 2072 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2073 { 2074 struct e1000_phy_info *phy = &hw->phy; 2075 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2076 s32 ret_val = 0; 2077 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2078 2079 /* Initialize the PHY from the NVM on ICH platforms. This 2080 * is needed due to an issue where the NVM configuration is 2081 * not properly autoloaded after power transitions. 2082 * Therefore, after each PHY reset, we will load the 2083 * configuration data out of the NVM manually. 2084 */ 2085 switch (hw->mac.type) { 2086 case e1000_ich8lan: 2087 if (phy->type != e1000_phy_igp_3) 2088 return ret_val; 2089 2090 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2091 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2092 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2093 break; 2094 } 2095 /* Fall-thru */ 2096 case e1000_pchlan: 2097 case e1000_pch2lan: 2098 case e1000_pch_lpt: 2099 case e1000_pch_spt: 2100 case e1000_pch_cnp: 2101 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2102 break; 2103 default: 2104 return ret_val; 2105 } 2106 2107 ret_val = hw->phy.ops.acquire(hw); 2108 if (ret_val) 2109 return ret_val; 2110 2111 data = er32(FEXTNVM); 2112 if (!(data & sw_cfg_mask)) 2113 goto release; 2114 2115 /* Make sure HW does not configure LCD from PHY 2116 * extended configuration before SW configuration 2117 */ 2118 data = er32(EXTCNF_CTRL); 2119 if ((hw->mac.type < e1000_pch2lan) && 2120 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2121 goto release; 2122 2123 cnf_size = er32(EXTCNF_SIZE); 2124 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2125 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2126 if (!cnf_size) 2127 goto release; 2128 2129 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2130 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2131 2132 if (((hw->mac.type == e1000_pchlan) && 2133 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2134 (hw->mac.type > e1000_pchlan)) { 2135 /* HW configures the SMBus address and LEDs when the 2136 * OEM and LCD Write Enable bits are set in the NVM. 2137 * When both NVM bits are cleared, SW will configure 2138 * them instead. 2139 */ 2140 ret_val = e1000_write_smbus_addr(hw); 2141 if (ret_val) 2142 goto release; 2143 2144 data = er32(LEDCTL); 2145 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2146 (u16)data); 2147 if (ret_val) 2148 goto release; 2149 } 2150 2151 /* Configure LCD from extended configuration region. */ 2152 2153 /* cnf_base_addr is in DWORD */ 2154 word_addr = (u16)(cnf_base_addr << 1); 2155 2156 for (i = 0; i < cnf_size; i++) { 2157 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2158 if (ret_val) 2159 goto release; 2160 2161 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2162 1, ®_addr); 2163 if (ret_val) 2164 goto release; 2165 2166 /* Save off the PHY page for future writes. */ 2167 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2168 phy_page = reg_data; 2169 continue; 2170 } 2171 2172 reg_addr &= PHY_REG_MASK; 2173 reg_addr |= phy_page; 2174 2175 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2176 if (ret_val) 2177 goto release; 2178 } 2179 2180 release: 2181 hw->phy.ops.release(hw); 2182 return ret_val; 2183 } 2184 2185 /** 2186 * e1000_k1_gig_workaround_hv - K1 Si workaround 2187 * @hw: pointer to the HW structure 2188 * @link: link up bool flag 2189 * 2190 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2191 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2192 * If link is down, the function will restore the default K1 setting located 2193 * in the NVM. 2194 **/ 2195 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2196 { 2197 s32 ret_val = 0; 2198 u16 status_reg = 0; 2199 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2200 2201 if (hw->mac.type != e1000_pchlan) 2202 return 0; 2203 2204 /* Wrap the whole flow with the sw flag */ 2205 ret_val = hw->phy.ops.acquire(hw); 2206 if (ret_val) 2207 return ret_val; 2208 2209 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2210 if (link) { 2211 if (hw->phy.type == e1000_phy_82578) { 2212 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2213 &status_reg); 2214 if (ret_val) 2215 goto release; 2216 2217 status_reg &= (BM_CS_STATUS_LINK_UP | 2218 BM_CS_STATUS_RESOLVED | 2219 BM_CS_STATUS_SPEED_MASK); 2220 2221 if (status_reg == (BM_CS_STATUS_LINK_UP | 2222 BM_CS_STATUS_RESOLVED | 2223 BM_CS_STATUS_SPEED_1000)) 2224 k1_enable = false; 2225 } 2226 2227 if (hw->phy.type == e1000_phy_82577) { 2228 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2229 if (ret_val) 2230 goto release; 2231 2232 status_reg &= (HV_M_STATUS_LINK_UP | 2233 HV_M_STATUS_AUTONEG_COMPLETE | 2234 HV_M_STATUS_SPEED_MASK); 2235 2236 if (status_reg == (HV_M_STATUS_LINK_UP | 2237 HV_M_STATUS_AUTONEG_COMPLETE | 2238 HV_M_STATUS_SPEED_1000)) 2239 k1_enable = false; 2240 } 2241 2242 /* Link stall fix for link up */ 2243 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2244 if (ret_val) 2245 goto release; 2246 2247 } else { 2248 /* Link stall fix for link down */ 2249 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2250 if (ret_val) 2251 goto release; 2252 } 2253 2254 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2255 2256 release: 2257 hw->phy.ops.release(hw); 2258 2259 return ret_val; 2260 } 2261 2262 /** 2263 * e1000_configure_k1_ich8lan - Configure K1 power state 2264 * @hw: pointer to the HW structure 2265 * @enable: K1 state to configure 2266 * 2267 * Configure the K1 power state based on the provided parameter. 2268 * Assumes semaphore already acquired. 2269 * 2270 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2271 **/ 2272 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2273 { 2274 s32 ret_val; 2275 u32 ctrl_reg = 0; 2276 u32 ctrl_ext = 0; 2277 u32 reg = 0; 2278 u16 kmrn_reg = 0; 2279 2280 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2281 &kmrn_reg); 2282 if (ret_val) 2283 return ret_val; 2284 2285 if (k1_enable) 2286 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2287 else 2288 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2289 2290 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2291 kmrn_reg); 2292 if (ret_val) 2293 return ret_val; 2294 2295 usleep_range(20, 40); 2296 ctrl_ext = er32(CTRL_EXT); 2297 ctrl_reg = er32(CTRL); 2298 2299 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2300 reg |= E1000_CTRL_FRCSPD; 2301 ew32(CTRL, reg); 2302 2303 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2304 e1e_flush(); 2305 usleep_range(20, 40); 2306 ew32(CTRL, ctrl_reg); 2307 ew32(CTRL_EXT, ctrl_ext); 2308 e1e_flush(); 2309 usleep_range(20, 40); 2310 2311 return 0; 2312 } 2313 2314 /** 2315 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2316 * @hw: pointer to the HW structure 2317 * @d0_state: boolean if entering d0 or d3 device state 2318 * 2319 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2320 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2321 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2322 **/ 2323 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2324 { 2325 s32 ret_val = 0; 2326 u32 mac_reg; 2327 u16 oem_reg; 2328 2329 if (hw->mac.type < e1000_pchlan) 2330 return ret_val; 2331 2332 ret_val = hw->phy.ops.acquire(hw); 2333 if (ret_val) 2334 return ret_val; 2335 2336 if (hw->mac.type == e1000_pchlan) { 2337 mac_reg = er32(EXTCNF_CTRL); 2338 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2339 goto release; 2340 } 2341 2342 mac_reg = er32(FEXTNVM); 2343 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2344 goto release; 2345 2346 mac_reg = er32(PHY_CTRL); 2347 2348 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2349 if (ret_val) 2350 goto release; 2351 2352 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2353 2354 if (d0_state) { 2355 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2356 oem_reg |= HV_OEM_BITS_GBE_DIS; 2357 2358 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2359 oem_reg |= HV_OEM_BITS_LPLU; 2360 } else { 2361 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2362 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2363 oem_reg |= HV_OEM_BITS_GBE_DIS; 2364 2365 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2366 E1000_PHY_CTRL_NOND0A_LPLU)) 2367 oem_reg |= HV_OEM_BITS_LPLU; 2368 } 2369 2370 /* Set Restart auto-neg to activate the bits */ 2371 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2372 !hw->phy.ops.check_reset_block(hw)) 2373 oem_reg |= HV_OEM_BITS_RESTART_AN; 2374 2375 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2376 2377 release: 2378 hw->phy.ops.release(hw); 2379 2380 return ret_val; 2381 } 2382 2383 /** 2384 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2385 * @hw: pointer to the HW structure 2386 **/ 2387 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2388 { 2389 s32 ret_val; 2390 u16 data; 2391 2392 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2393 if (ret_val) 2394 return ret_val; 2395 2396 data |= HV_KMRN_MDIO_SLOW; 2397 2398 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2399 2400 return ret_val; 2401 } 2402 2403 /** 2404 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2405 * done after every PHY reset. 2406 **/ 2407 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2408 { 2409 s32 ret_val = 0; 2410 u16 phy_data; 2411 2412 if (hw->mac.type != e1000_pchlan) 2413 return 0; 2414 2415 /* Set MDIO slow mode before any other MDIO access */ 2416 if (hw->phy.type == e1000_phy_82577) { 2417 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2418 if (ret_val) 2419 return ret_val; 2420 } 2421 2422 if (((hw->phy.type == e1000_phy_82577) && 2423 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2424 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2425 /* Disable generation of early preamble */ 2426 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2427 if (ret_val) 2428 return ret_val; 2429 2430 /* Preamble tuning for SSC */ 2431 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2432 if (ret_val) 2433 return ret_val; 2434 } 2435 2436 if (hw->phy.type == e1000_phy_82578) { 2437 /* Return registers to default by doing a soft reset then 2438 * writing 0x3140 to the control register. 2439 */ 2440 if (hw->phy.revision < 2) { 2441 e1000e_phy_sw_reset(hw); 2442 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2443 if (ret_val) 2444 return ret_val; 2445 } 2446 } 2447 2448 /* Select page 0 */ 2449 ret_val = hw->phy.ops.acquire(hw); 2450 if (ret_val) 2451 return ret_val; 2452 2453 hw->phy.addr = 1; 2454 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2455 hw->phy.ops.release(hw); 2456 if (ret_val) 2457 return ret_val; 2458 2459 /* Configure the K1 Si workaround during phy reset assuming there is 2460 * link so that it disables K1 if link is in 1Gbps. 2461 */ 2462 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2463 if (ret_val) 2464 return ret_val; 2465 2466 /* Workaround for link disconnects on a busy hub in half duplex */ 2467 ret_val = hw->phy.ops.acquire(hw); 2468 if (ret_val) 2469 return ret_val; 2470 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2471 if (ret_val) 2472 goto release; 2473 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2474 if (ret_val) 2475 goto release; 2476 2477 /* set MSE higher to enable link to stay up when noise is high */ 2478 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2479 release: 2480 hw->phy.ops.release(hw); 2481 2482 return ret_val; 2483 } 2484 2485 /** 2486 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2487 * @hw: pointer to the HW structure 2488 **/ 2489 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2490 { 2491 u32 mac_reg; 2492 u16 i, phy_reg = 0; 2493 s32 ret_val; 2494 2495 ret_val = hw->phy.ops.acquire(hw); 2496 if (ret_val) 2497 return; 2498 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2499 if (ret_val) 2500 goto release; 2501 2502 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2503 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2504 mac_reg = er32(RAL(i)); 2505 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2506 (u16)(mac_reg & 0xFFFF)); 2507 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2508 (u16)((mac_reg >> 16) & 0xFFFF)); 2509 2510 mac_reg = er32(RAH(i)); 2511 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2512 (u16)(mac_reg & 0xFFFF)); 2513 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2514 (u16)((mac_reg & E1000_RAH_AV) 2515 >> 16)); 2516 } 2517 2518 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2519 2520 release: 2521 hw->phy.ops.release(hw); 2522 } 2523 2524 /** 2525 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2526 * with 82579 PHY 2527 * @hw: pointer to the HW structure 2528 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2529 **/ 2530 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2531 { 2532 s32 ret_val = 0; 2533 u16 phy_reg, data; 2534 u32 mac_reg; 2535 u16 i; 2536 2537 if (hw->mac.type < e1000_pch2lan) 2538 return 0; 2539 2540 /* disable Rx path while enabling/disabling workaround */ 2541 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2542 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2543 if (ret_val) 2544 return ret_val; 2545 2546 if (enable) { 2547 /* Write Rx addresses (rar_entry_count for RAL/H, and 2548 * SHRAL/H) and initial CRC values to the MAC 2549 */ 2550 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2551 u8 mac_addr[ETH_ALEN] = { 0 }; 2552 u32 addr_high, addr_low; 2553 2554 addr_high = er32(RAH(i)); 2555 if (!(addr_high & E1000_RAH_AV)) 2556 continue; 2557 addr_low = er32(RAL(i)); 2558 mac_addr[0] = (addr_low & 0xFF); 2559 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2560 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2561 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2562 mac_addr[4] = (addr_high & 0xFF); 2563 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2564 2565 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2566 } 2567 2568 /* Write Rx addresses to the PHY */ 2569 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2570 2571 /* Enable jumbo frame workaround in the MAC */ 2572 mac_reg = er32(FFLT_DBG); 2573 mac_reg &= ~BIT(14); 2574 mac_reg |= (7 << 15); 2575 ew32(FFLT_DBG, mac_reg); 2576 2577 mac_reg = er32(RCTL); 2578 mac_reg |= E1000_RCTL_SECRC; 2579 ew32(RCTL, mac_reg); 2580 2581 ret_val = e1000e_read_kmrn_reg(hw, 2582 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2583 &data); 2584 if (ret_val) 2585 return ret_val; 2586 ret_val = e1000e_write_kmrn_reg(hw, 2587 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2588 data | BIT(0)); 2589 if (ret_val) 2590 return ret_val; 2591 ret_val = e1000e_read_kmrn_reg(hw, 2592 E1000_KMRNCTRLSTA_HD_CTRL, 2593 &data); 2594 if (ret_val) 2595 return ret_val; 2596 data &= ~(0xF << 8); 2597 data |= (0xB << 8); 2598 ret_val = e1000e_write_kmrn_reg(hw, 2599 E1000_KMRNCTRLSTA_HD_CTRL, 2600 data); 2601 if (ret_val) 2602 return ret_val; 2603 2604 /* Enable jumbo frame workaround in the PHY */ 2605 e1e_rphy(hw, PHY_REG(769, 23), &data); 2606 data &= ~(0x7F << 5); 2607 data |= (0x37 << 5); 2608 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2609 if (ret_val) 2610 return ret_val; 2611 e1e_rphy(hw, PHY_REG(769, 16), &data); 2612 data &= ~BIT(13); 2613 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2614 if (ret_val) 2615 return ret_val; 2616 e1e_rphy(hw, PHY_REG(776, 20), &data); 2617 data &= ~(0x3FF << 2); 2618 data |= (E1000_TX_PTR_GAP << 2); 2619 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2620 if (ret_val) 2621 return ret_val; 2622 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2623 if (ret_val) 2624 return ret_val; 2625 e1e_rphy(hw, HV_PM_CTRL, &data); 2626 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2627 if (ret_val) 2628 return ret_val; 2629 } else { 2630 /* Write MAC register values back to h/w defaults */ 2631 mac_reg = er32(FFLT_DBG); 2632 mac_reg &= ~(0xF << 14); 2633 ew32(FFLT_DBG, mac_reg); 2634 2635 mac_reg = er32(RCTL); 2636 mac_reg &= ~E1000_RCTL_SECRC; 2637 ew32(RCTL, mac_reg); 2638 2639 ret_val = e1000e_read_kmrn_reg(hw, 2640 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2641 &data); 2642 if (ret_val) 2643 return ret_val; 2644 ret_val = e1000e_write_kmrn_reg(hw, 2645 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2646 data & ~BIT(0)); 2647 if (ret_val) 2648 return ret_val; 2649 ret_val = e1000e_read_kmrn_reg(hw, 2650 E1000_KMRNCTRLSTA_HD_CTRL, 2651 &data); 2652 if (ret_val) 2653 return ret_val; 2654 data &= ~(0xF << 8); 2655 data |= (0xB << 8); 2656 ret_val = e1000e_write_kmrn_reg(hw, 2657 E1000_KMRNCTRLSTA_HD_CTRL, 2658 data); 2659 if (ret_val) 2660 return ret_val; 2661 2662 /* Write PHY register values back to h/w defaults */ 2663 e1e_rphy(hw, PHY_REG(769, 23), &data); 2664 data &= ~(0x7F << 5); 2665 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2666 if (ret_val) 2667 return ret_val; 2668 e1e_rphy(hw, PHY_REG(769, 16), &data); 2669 data |= BIT(13); 2670 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2671 if (ret_val) 2672 return ret_val; 2673 e1e_rphy(hw, PHY_REG(776, 20), &data); 2674 data &= ~(0x3FF << 2); 2675 data |= (0x8 << 2); 2676 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2677 if (ret_val) 2678 return ret_val; 2679 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2680 if (ret_val) 2681 return ret_val; 2682 e1e_rphy(hw, HV_PM_CTRL, &data); 2683 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2684 if (ret_val) 2685 return ret_val; 2686 } 2687 2688 /* re-enable Rx path after enabling/disabling workaround */ 2689 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2690 } 2691 2692 /** 2693 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2694 * done after every PHY reset. 2695 **/ 2696 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2697 { 2698 s32 ret_val = 0; 2699 2700 if (hw->mac.type != e1000_pch2lan) 2701 return 0; 2702 2703 /* Set MDIO slow mode before any other MDIO access */ 2704 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2705 if (ret_val) 2706 return ret_val; 2707 2708 ret_val = hw->phy.ops.acquire(hw); 2709 if (ret_val) 2710 return ret_val; 2711 /* set MSE higher to enable link to stay up when noise is high */ 2712 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2713 if (ret_val) 2714 goto release; 2715 /* drop link after 5 times MSE threshold was reached */ 2716 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2717 release: 2718 hw->phy.ops.release(hw); 2719 2720 return ret_val; 2721 } 2722 2723 /** 2724 * e1000_k1_gig_workaround_lv - K1 Si workaround 2725 * @hw: pointer to the HW structure 2726 * 2727 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2728 * Disable K1 in 1000Mbps and 100Mbps 2729 **/ 2730 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2731 { 2732 s32 ret_val = 0; 2733 u16 status_reg = 0; 2734 2735 if (hw->mac.type != e1000_pch2lan) 2736 return 0; 2737 2738 /* Set K1 beacon duration based on 10Mbs speed */ 2739 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2740 if (ret_val) 2741 return ret_val; 2742 2743 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2744 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2745 if (status_reg & 2746 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2747 u16 pm_phy_reg; 2748 2749 /* LV 1G/100 Packet drop issue wa */ 2750 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2751 if (ret_val) 2752 return ret_val; 2753 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2754 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2755 if (ret_val) 2756 return ret_val; 2757 } else { 2758 u32 mac_reg; 2759 2760 mac_reg = er32(FEXTNVM4); 2761 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2762 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2763 ew32(FEXTNVM4, mac_reg); 2764 } 2765 } 2766 2767 return ret_val; 2768 } 2769 2770 /** 2771 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2772 * @hw: pointer to the HW structure 2773 * @gate: boolean set to true to gate, false to ungate 2774 * 2775 * Gate/ungate the automatic PHY configuration via hardware; perform 2776 * the configuration via software instead. 2777 **/ 2778 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2779 { 2780 u32 extcnf_ctrl; 2781 2782 if (hw->mac.type < e1000_pch2lan) 2783 return; 2784 2785 extcnf_ctrl = er32(EXTCNF_CTRL); 2786 2787 if (gate) 2788 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2789 else 2790 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2791 2792 ew32(EXTCNF_CTRL, extcnf_ctrl); 2793 } 2794 2795 /** 2796 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2797 * @hw: pointer to the HW structure 2798 * 2799 * Check the appropriate indication the MAC has finished configuring the 2800 * PHY after a software reset. 2801 **/ 2802 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2803 { 2804 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2805 2806 /* Wait for basic configuration completes before proceeding */ 2807 do { 2808 data = er32(STATUS); 2809 data &= E1000_STATUS_LAN_INIT_DONE; 2810 usleep_range(100, 200); 2811 } while ((!data) && --loop); 2812 2813 /* If basic configuration is incomplete before the above loop 2814 * count reaches 0, loading the configuration from NVM will 2815 * leave the PHY in a bad state possibly resulting in no link. 2816 */ 2817 if (loop == 0) 2818 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2819 2820 /* Clear the Init Done bit for the next init event */ 2821 data = er32(STATUS); 2822 data &= ~E1000_STATUS_LAN_INIT_DONE; 2823 ew32(STATUS, data); 2824 } 2825 2826 /** 2827 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2828 * @hw: pointer to the HW structure 2829 **/ 2830 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2831 { 2832 s32 ret_val = 0; 2833 u16 reg; 2834 2835 if (hw->phy.ops.check_reset_block(hw)) 2836 return 0; 2837 2838 /* Allow time for h/w to get to quiescent state after reset */ 2839 usleep_range(10000, 20000); 2840 2841 /* Perform any necessary post-reset workarounds */ 2842 switch (hw->mac.type) { 2843 case e1000_pchlan: 2844 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2845 if (ret_val) 2846 return ret_val; 2847 break; 2848 case e1000_pch2lan: 2849 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2850 if (ret_val) 2851 return ret_val; 2852 break; 2853 default: 2854 break; 2855 } 2856 2857 /* Clear the host wakeup bit after lcd reset */ 2858 if (hw->mac.type >= e1000_pchlan) { 2859 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2860 reg &= ~BM_WUC_HOST_WU_BIT; 2861 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2862 } 2863 2864 /* Configure the LCD with the extended configuration region in NVM */ 2865 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2866 if (ret_val) 2867 return ret_val; 2868 2869 /* Configure the LCD with the OEM bits in NVM */ 2870 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2871 2872 if (hw->mac.type == e1000_pch2lan) { 2873 /* Ungate automatic PHY configuration on non-managed 82579 */ 2874 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2875 usleep_range(10000, 20000); 2876 e1000_gate_hw_phy_config_ich8lan(hw, false); 2877 } 2878 2879 /* Set EEE LPI Update Timer to 200usec */ 2880 ret_val = hw->phy.ops.acquire(hw); 2881 if (ret_val) 2882 return ret_val; 2883 ret_val = e1000_write_emi_reg_locked(hw, 2884 I82579_LPI_UPDATE_TIMER, 2885 0x1387); 2886 hw->phy.ops.release(hw); 2887 } 2888 2889 return ret_val; 2890 } 2891 2892 /** 2893 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 2894 * @hw: pointer to the HW structure 2895 * 2896 * Resets the PHY 2897 * This is a function pointer entry point called by drivers 2898 * or other shared routines. 2899 **/ 2900 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 2901 { 2902 s32 ret_val = 0; 2903 2904 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 2905 if ((hw->mac.type == e1000_pch2lan) && 2906 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 2907 e1000_gate_hw_phy_config_ich8lan(hw, true); 2908 2909 ret_val = e1000e_phy_hw_reset_generic(hw); 2910 if (ret_val) 2911 return ret_val; 2912 2913 return e1000_post_phy_reset_ich8lan(hw); 2914 } 2915 2916 /** 2917 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2918 * @hw: pointer to the HW structure 2919 * @active: true to enable LPLU, false to disable 2920 * 2921 * Sets the LPLU state according to the active flag. For PCH, if OEM write 2922 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2923 * the phy speed. This function will manually set the LPLU bit and restart 2924 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2925 * since it configures the same bit. 2926 **/ 2927 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2928 { 2929 s32 ret_val; 2930 u16 oem_reg; 2931 2932 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 2933 if (ret_val) 2934 return ret_val; 2935 2936 if (active) 2937 oem_reg |= HV_OEM_BITS_LPLU; 2938 else 2939 oem_reg &= ~HV_OEM_BITS_LPLU; 2940 2941 if (!hw->phy.ops.check_reset_block(hw)) 2942 oem_reg |= HV_OEM_BITS_RESTART_AN; 2943 2944 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 2945 } 2946 2947 /** 2948 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2949 * @hw: pointer to the HW structure 2950 * @active: true to enable LPLU, false to disable 2951 * 2952 * Sets the LPLU D0 state according to the active flag. When 2953 * activating LPLU this function also disables smart speed 2954 * and vice versa. LPLU will not be activated unless the 2955 * device autonegotiation advertisement meets standards of 2956 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2957 * This is a function pointer entry point only called by 2958 * PHY setup routines. 2959 **/ 2960 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2961 { 2962 struct e1000_phy_info *phy = &hw->phy; 2963 u32 phy_ctrl; 2964 s32 ret_val = 0; 2965 u16 data; 2966 2967 if (phy->type == e1000_phy_ife) 2968 return 0; 2969 2970 phy_ctrl = er32(PHY_CTRL); 2971 2972 if (active) { 2973 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2974 ew32(PHY_CTRL, phy_ctrl); 2975 2976 if (phy->type != e1000_phy_igp_3) 2977 return 0; 2978 2979 /* Call gig speed drop workaround on LPLU before accessing 2980 * any PHY registers 2981 */ 2982 if (hw->mac.type == e1000_ich8lan) 2983 e1000e_gig_downshift_workaround_ich8lan(hw); 2984 2985 /* When LPLU is enabled, we should disable SmartSpeed */ 2986 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 2987 if (ret_val) 2988 return ret_val; 2989 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2990 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 2991 if (ret_val) 2992 return ret_val; 2993 } else { 2994 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2995 ew32(PHY_CTRL, phy_ctrl); 2996 2997 if (phy->type != e1000_phy_igp_3) 2998 return 0; 2999 3000 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3001 * during Dx states where the power conservation is most 3002 * important. During driver activity we should enable 3003 * SmartSpeed, so performance is maintained. 3004 */ 3005 if (phy->smart_speed == e1000_smart_speed_on) { 3006 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3007 &data); 3008 if (ret_val) 3009 return ret_val; 3010 3011 data |= IGP01E1000_PSCFR_SMART_SPEED; 3012 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3013 data); 3014 if (ret_val) 3015 return ret_val; 3016 } else if (phy->smart_speed == e1000_smart_speed_off) { 3017 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3018 &data); 3019 if (ret_val) 3020 return ret_val; 3021 3022 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3023 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3024 data); 3025 if (ret_val) 3026 return ret_val; 3027 } 3028 } 3029 3030 return 0; 3031 } 3032 3033 /** 3034 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3035 * @hw: pointer to the HW structure 3036 * @active: true to enable LPLU, false to disable 3037 * 3038 * Sets the LPLU D3 state according to the active flag. When 3039 * activating LPLU this function also disables smart speed 3040 * and vice versa. LPLU will not be activated unless the 3041 * device autonegotiation advertisement meets standards of 3042 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3043 * This is a function pointer entry point only called by 3044 * PHY setup routines. 3045 **/ 3046 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3047 { 3048 struct e1000_phy_info *phy = &hw->phy; 3049 u32 phy_ctrl; 3050 s32 ret_val = 0; 3051 u16 data; 3052 3053 phy_ctrl = er32(PHY_CTRL); 3054 3055 if (!active) { 3056 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3057 ew32(PHY_CTRL, phy_ctrl); 3058 3059 if (phy->type != e1000_phy_igp_3) 3060 return 0; 3061 3062 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3063 * during Dx states where the power conservation is most 3064 * important. During driver activity we should enable 3065 * SmartSpeed, so performance is maintained. 3066 */ 3067 if (phy->smart_speed == e1000_smart_speed_on) { 3068 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3069 &data); 3070 if (ret_val) 3071 return ret_val; 3072 3073 data |= IGP01E1000_PSCFR_SMART_SPEED; 3074 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3075 data); 3076 if (ret_val) 3077 return ret_val; 3078 } else if (phy->smart_speed == e1000_smart_speed_off) { 3079 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3080 &data); 3081 if (ret_val) 3082 return ret_val; 3083 3084 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3085 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3086 data); 3087 if (ret_val) 3088 return ret_val; 3089 } 3090 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3091 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3092 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3093 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3094 ew32(PHY_CTRL, phy_ctrl); 3095 3096 if (phy->type != e1000_phy_igp_3) 3097 return 0; 3098 3099 /* Call gig speed drop workaround on LPLU before accessing 3100 * any PHY registers 3101 */ 3102 if (hw->mac.type == e1000_ich8lan) 3103 e1000e_gig_downshift_workaround_ich8lan(hw); 3104 3105 /* When LPLU is enabled, we should disable SmartSpeed */ 3106 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3107 if (ret_val) 3108 return ret_val; 3109 3110 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3111 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3112 } 3113 3114 return ret_val; 3115 } 3116 3117 /** 3118 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3119 * @hw: pointer to the HW structure 3120 * @bank: pointer to the variable that returns the active bank 3121 * 3122 * Reads signature byte from the NVM using the flash access registers. 3123 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3124 **/ 3125 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3126 { 3127 u32 eecd; 3128 struct e1000_nvm_info *nvm = &hw->nvm; 3129 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3130 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3131 u32 nvm_dword = 0; 3132 u8 sig_byte = 0; 3133 s32 ret_val; 3134 3135 switch (hw->mac.type) { 3136 case e1000_pch_spt: 3137 case e1000_pch_cnp: 3138 bank1_offset = nvm->flash_bank_size; 3139 act_offset = E1000_ICH_NVM_SIG_WORD; 3140 3141 /* set bank to 0 in case flash read fails */ 3142 *bank = 0; 3143 3144 /* Check bank 0 */ 3145 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3146 &nvm_dword); 3147 if (ret_val) 3148 return ret_val; 3149 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3150 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3151 E1000_ICH_NVM_SIG_VALUE) { 3152 *bank = 0; 3153 return 0; 3154 } 3155 3156 /* Check bank 1 */ 3157 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3158 bank1_offset, 3159 &nvm_dword); 3160 if (ret_val) 3161 return ret_val; 3162 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3163 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3164 E1000_ICH_NVM_SIG_VALUE) { 3165 *bank = 1; 3166 return 0; 3167 } 3168 3169 e_dbg("ERROR: No valid NVM bank present\n"); 3170 return -E1000_ERR_NVM; 3171 case e1000_ich8lan: 3172 case e1000_ich9lan: 3173 eecd = er32(EECD); 3174 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3175 E1000_EECD_SEC1VAL_VALID_MASK) { 3176 if (eecd & E1000_EECD_SEC1VAL) 3177 *bank = 1; 3178 else 3179 *bank = 0; 3180 3181 return 0; 3182 } 3183 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3184 /* fall-thru */ 3185 default: 3186 /* set bank to 0 in case flash read fails */ 3187 *bank = 0; 3188 3189 /* Check bank 0 */ 3190 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3191 &sig_byte); 3192 if (ret_val) 3193 return ret_val; 3194 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3195 E1000_ICH_NVM_SIG_VALUE) { 3196 *bank = 0; 3197 return 0; 3198 } 3199 3200 /* Check bank 1 */ 3201 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3202 bank1_offset, 3203 &sig_byte); 3204 if (ret_val) 3205 return ret_val; 3206 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3207 E1000_ICH_NVM_SIG_VALUE) { 3208 *bank = 1; 3209 return 0; 3210 } 3211 3212 e_dbg("ERROR: No valid NVM bank present\n"); 3213 return -E1000_ERR_NVM; 3214 } 3215 } 3216 3217 /** 3218 * e1000_read_nvm_spt - NVM access for SPT 3219 * @hw: pointer to the HW structure 3220 * @offset: The offset (in bytes) of the word(s) to read. 3221 * @words: Size of data to read in words. 3222 * @data: pointer to the word(s) to read at offset. 3223 * 3224 * Reads a word(s) from the NVM 3225 **/ 3226 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3227 u16 *data) 3228 { 3229 struct e1000_nvm_info *nvm = &hw->nvm; 3230 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3231 u32 act_offset; 3232 s32 ret_val = 0; 3233 u32 bank = 0; 3234 u32 dword = 0; 3235 u16 offset_to_read; 3236 u16 i; 3237 3238 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3239 (words == 0)) { 3240 e_dbg("nvm parameter(s) out of bounds\n"); 3241 ret_val = -E1000_ERR_NVM; 3242 goto out; 3243 } 3244 3245 nvm->ops.acquire(hw); 3246 3247 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3248 if (ret_val) { 3249 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3250 bank = 0; 3251 } 3252 3253 act_offset = (bank) ? nvm->flash_bank_size : 0; 3254 act_offset += offset; 3255 3256 ret_val = 0; 3257 3258 for (i = 0; i < words; i += 2) { 3259 if (words - i == 1) { 3260 if (dev_spec->shadow_ram[offset + i].modified) { 3261 data[i] = 3262 dev_spec->shadow_ram[offset + i].value; 3263 } else { 3264 offset_to_read = act_offset + i - 3265 ((act_offset + i) % 2); 3266 ret_val = 3267 e1000_read_flash_dword_ich8lan(hw, 3268 offset_to_read, 3269 &dword); 3270 if (ret_val) 3271 break; 3272 if ((act_offset + i) % 2 == 0) 3273 data[i] = (u16)(dword & 0xFFFF); 3274 else 3275 data[i] = (u16)((dword >> 16) & 0xFFFF); 3276 } 3277 } else { 3278 offset_to_read = act_offset + i; 3279 if (!(dev_spec->shadow_ram[offset + i].modified) || 3280 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3281 ret_val = 3282 e1000_read_flash_dword_ich8lan(hw, 3283 offset_to_read, 3284 &dword); 3285 if (ret_val) 3286 break; 3287 } 3288 if (dev_spec->shadow_ram[offset + i].modified) 3289 data[i] = 3290 dev_spec->shadow_ram[offset + i].value; 3291 else 3292 data[i] = (u16)(dword & 0xFFFF); 3293 if (dev_spec->shadow_ram[offset + i].modified) 3294 data[i + 1] = 3295 dev_spec->shadow_ram[offset + i + 1].value; 3296 else 3297 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3298 } 3299 } 3300 3301 nvm->ops.release(hw); 3302 3303 out: 3304 if (ret_val) 3305 e_dbg("NVM read error: %d\n", ret_val); 3306 3307 return ret_val; 3308 } 3309 3310 /** 3311 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3312 * @hw: pointer to the HW structure 3313 * @offset: The offset (in bytes) of the word(s) to read. 3314 * @words: Size of data to read in words 3315 * @data: Pointer to the word(s) to read at offset. 3316 * 3317 * Reads a word(s) from the NVM using the flash access registers. 3318 **/ 3319 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3320 u16 *data) 3321 { 3322 struct e1000_nvm_info *nvm = &hw->nvm; 3323 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3324 u32 act_offset; 3325 s32 ret_val = 0; 3326 u32 bank = 0; 3327 u16 i, word; 3328 3329 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3330 (words == 0)) { 3331 e_dbg("nvm parameter(s) out of bounds\n"); 3332 ret_val = -E1000_ERR_NVM; 3333 goto out; 3334 } 3335 3336 nvm->ops.acquire(hw); 3337 3338 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3339 if (ret_val) { 3340 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3341 bank = 0; 3342 } 3343 3344 act_offset = (bank) ? nvm->flash_bank_size : 0; 3345 act_offset += offset; 3346 3347 ret_val = 0; 3348 for (i = 0; i < words; i++) { 3349 if (dev_spec->shadow_ram[offset + i].modified) { 3350 data[i] = dev_spec->shadow_ram[offset + i].value; 3351 } else { 3352 ret_val = e1000_read_flash_word_ich8lan(hw, 3353 act_offset + i, 3354 &word); 3355 if (ret_val) 3356 break; 3357 data[i] = word; 3358 } 3359 } 3360 3361 nvm->ops.release(hw); 3362 3363 out: 3364 if (ret_val) 3365 e_dbg("NVM read error: %d\n", ret_val); 3366 3367 return ret_val; 3368 } 3369 3370 /** 3371 * e1000_flash_cycle_init_ich8lan - Initialize flash 3372 * @hw: pointer to the HW structure 3373 * 3374 * This function does initial flash setup so that a new read/write/erase cycle 3375 * can be started. 3376 **/ 3377 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3378 { 3379 union ich8_hws_flash_status hsfsts; 3380 s32 ret_val = -E1000_ERR_NVM; 3381 3382 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3383 3384 /* Check if the flash descriptor is valid */ 3385 if (!hsfsts.hsf_status.fldesvalid) { 3386 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3387 return -E1000_ERR_NVM; 3388 } 3389 3390 /* Clear FCERR and DAEL in hw status by writing 1 */ 3391 hsfsts.hsf_status.flcerr = 1; 3392 hsfsts.hsf_status.dael = 1; 3393 if (hw->mac.type >= e1000_pch_spt) 3394 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3395 else 3396 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3397 3398 /* Either we should have a hardware SPI cycle in progress 3399 * bit to check against, in order to start a new cycle or 3400 * FDONE bit should be changed in the hardware so that it 3401 * is 1 after hardware reset, which can then be used as an 3402 * indication whether a cycle is in progress or has been 3403 * completed. 3404 */ 3405 3406 if (!hsfsts.hsf_status.flcinprog) { 3407 /* There is no cycle running at present, 3408 * so we can start a cycle. 3409 * Begin by setting Flash Cycle Done. 3410 */ 3411 hsfsts.hsf_status.flcdone = 1; 3412 if (hw->mac.type >= e1000_pch_spt) 3413 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3414 else 3415 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3416 ret_val = 0; 3417 } else { 3418 s32 i; 3419 3420 /* Otherwise poll for sometime so the current 3421 * cycle has a chance to end before giving up. 3422 */ 3423 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3424 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3425 if (!hsfsts.hsf_status.flcinprog) { 3426 ret_val = 0; 3427 break; 3428 } 3429 udelay(1); 3430 } 3431 if (!ret_val) { 3432 /* Successful in waiting for previous cycle to timeout, 3433 * now set the Flash Cycle Done. 3434 */ 3435 hsfsts.hsf_status.flcdone = 1; 3436 if (hw->mac.type >= e1000_pch_spt) 3437 ew32flash(ICH_FLASH_HSFSTS, 3438 hsfsts.regval & 0xFFFF); 3439 else 3440 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3441 } else { 3442 e_dbg("Flash controller busy, cannot get access\n"); 3443 } 3444 } 3445 3446 return ret_val; 3447 } 3448 3449 /** 3450 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3451 * @hw: pointer to the HW structure 3452 * @timeout: maximum time to wait for completion 3453 * 3454 * This function starts a flash cycle and waits for its completion. 3455 **/ 3456 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3457 { 3458 union ich8_hws_flash_ctrl hsflctl; 3459 union ich8_hws_flash_status hsfsts; 3460 u32 i = 0; 3461 3462 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3463 if (hw->mac.type >= e1000_pch_spt) 3464 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3465 else 3466 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3467 hsflctl.hsf_ctrl.flcgo = 1; 3468 3469 if (hw->mac.type >= e1000_pch_spt) 3470 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3471 else 3472 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3473 3474 /* wait till FDONE bit is set to 1 */ 3475 do { 3476 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3477 if (hsfsts.hsf_status.flcdone) 3478 break; 3479 udelay(1); 3480 } while (i++ < timeout); 3481 3482 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3483 return 0; 3484 3485 return -E1000_ERR_NVM; 3486 } 3487 3488 /** 3489 * e1000_read_flash_dword_ich8lan - Read dword from flash 3490 * @hw: pointer to the HW structure 3491 * @offset: offset to data location 3492 * @data: pointer to the location for storing the data 3493 * 3494 * Reads the flash dword at offset into data. Offset is converted 3495 * to bytes before read. 3496 **/ 3497 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3498 u32 *data) 3499 { 3500 /* Must convert word offset into bytes. */ 3501 offset <<= 1; 3502 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3503 } 3504 3505 /** 3506 * e1000_read_flash_word_ich8lan - Read word from flash 3507 * @hw: pointer to the HW structure 3508 * @offset: offset to data location 3509 * @data: pointer to the location for storing the data 3510 * 3511 * Reads the flash word at offset into data. Offset is converted 3512 * to bytes before read. 3513 **/ 3514 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3515 u16 *data) 3516 { 3517 /* Must convert offset into bytes. */ 3518 offset <<= 1; 3519 3520 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3521 } 3522 3523 /** 3524 * e1000_read_flash_byte_ich8lan - Read byte from flash 3525 * @hw: pointer to the HW structure 3526 * @offset: The offset of the byte to read. 3527 * @data: Pointer to a byte to store the value read. 3528 * 3529 * Reads a single byte from the NVM using the flash access registers. 3530 **/ 3531 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3532 u8 *data) 3533 { 3534 s32 ret_val; 3535 u16 word = 0; 3536 3537 /* In SPT, only 32 bits access is supported, 3538 * so this function should not be called. 3539 */ 3540 if (hw->mac.type >= e1000_pch_spt) 3541 return -E1000_ERR_NVM; 3542 else 3543 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3544 3545 if (ret_val) 3546 return ret_val; 3547 3548 *data = (u8)word; 3549 3550 return 0; 3551 } 3552 3553 /** 3554 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3555 * @hw: pointer to the HW structure 3556 * @offset: The offset (in bytes) of the byte or word to read. 3557 * @size: Size of data to read, 1=byte 2=word 3558 * @data: Pointer to the word to store the value read. 3559 * 3560 * Reads a byte or word from the NVM using the flash access registers. 3561 **/ 3562 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3563 u8 size, u16 *data) 3564 { 3565 union ich8_hws_flash_status hsfsts; 3566 union ich8_hws_flash_ctrl hsflctl; 3567 u32 flash_linear_addr; 3568 u32 flash_data = 0; 3569 s32 ret_val = -E1000_ERR_NVM; 3570 u8 count = 0; 3571 3572 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3573 return -E1000_ERR_NVM; 3574 3575 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3576 hw->nvm.flash_base_addr); 3577 3578 do { 3579 udelay(1); 3580 /* Steps */ 3581 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3582 if (ret_val) 3583 break; 3584 3585 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3586 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3587 hsflctl.hsf_ctrl.fldbcount = size - 1; 3588 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3589 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3590 3591 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3592 3593 ret_val = 3594 e1000_flash_cycle_ich8lan(hw, 3595 ICH_FLASH_READ_COMMAND_TIMEOUT); 3596 3597 /* Check if FCERR is set to 1, if set to 1, clear it 3598 * and try the whole sequence a few more times, else 3599 * read in (shift in) the Flash Data0, the order is 3600 * least significant byte first msb to lsb 3601 */ 3602 if (!ret_val) { 3603 flash_data = er32flash(ICH_FLASH_FDATA0); 3604 if (size == 1) 3605 *data = (u8)(flash_data & 0x000000FF); 3606 else if (size == 2) 3607 *data = (u16)(flash_data & 0x0000FFFF); 3608 break; 3609 } else { 3610 /* If we've gotten here, then things are probably 3611 * completely hosed, but if the error condition is 3612 * detected, it won't hurt to give it another try... 3613 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3614 */ 3615 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3616 if (hsfsts.hsf_status.flcerr) { 3617 /* Repeat for some time before giving up. */ 3618 continue; 3619 } else if (!hsfsts.hsf_status.flcdone) { 3620 e_dbg("Timeout error - flash cycle did not complete.\n"); 3621 break; 3622 } 3623 } 3624 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3625 3626 return ret_val; 3627 } 3628 3629 /** 3630 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3631 * @hw: pointer to the HW structure 3632 * @offset: The offset (in bytes) of the dword to read. 3633 * @data: Pointer to the dword to store the value read. 3634 * 3635 * Reads a byte or word from the NVM using the flash access registers. 3636 **/ 3637 3638 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3639 u32 *data) 3640 { 3641 union ich8_hws_flash_status hsfsts; 3642 union ich8_hws_flash_ctrl hsflctl; 3643 u32 flash_linear_addr; 3644 s32 ret_val = -E1000_ERR_NVM; 3645 u8 count = 0; 3646 3647 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3648 return -E1000_ERR_NVM; 3649 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3650 hw->nvm.flash_base_addr); 3651 3652 do { 3653 udelay(1); 3654 /* Steps */ 3655 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3656 if (ret_val) 3657 break; 3658 /* In SPT, This register is in Lan memory space, not flash. 3659 * Therefore, only 32 bit access is supported 3660 */ 3661 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3662 3663 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3664 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3665 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3666 /* In SPT, This register is in Lan memory space, not flash. 3667 * Therefore, only 32 bit access is supported 3668 */ 3669 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3670 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3671 3672 ret_val = 3673 e1000_flash_cycle_ich8lan(hw, 3674 ICH_FLASH_READ_COMMAND_TIMEOUT); 3675 3676 /* Check if FCERR is set to 1, if set to 1, clear it 3677 * and try the whole sequence a few more times, else 3678 * read in (shift in) the Flash Data0, the order is 3679 * least significant byte first msb to lsb 3680 */ 3681 if (!ret_val) { 3682 *data = er32flash(ICH_FLASH_FDATA0); 3683 break; 3684 } else { 3685 /* If we've gotten here, then things are probably 3686 * completely hosed, but if the error condition is 3687 * detected, it won't hurt to give it another try... 3688 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3689 */ 3690 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3691 if (hsfsts.hsf_status.flcerr) { 3692 /* Repeat for some time before giving up. */ 3693 continue; 3694 } else if (!hsfsts.hsf_status.flcdone) { 3695 e_dbg("Timeout error - flash cycle did not complete.\n"); 3696 break; 3697 } 3698 } 3699 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3700 3701 return ret_val; 3702 } 3703 3704 /** 3705 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3706 * @hw: pointer to the HW structure 3707 * @offset: The offset (in bytes) of the word(s) to write. 3708 * @words: Size of data to write in words 3709 * @data: Pointer to the word(s) to write at offset. 3710 * 3711 * Writes a byte or word to the NVM using the flash access registers. 3712 **/ 3713 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3714 u16 *data) 3715 { 3716 struct e1000_nvm_info *nvm = &hw->nvm; 3717 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3718 u16 i; 3719 3720 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3721 (words == 0)) { 3722 e_dbg("nvm parameter(s) out of bounds\n"); 3723 return -E1000_ERR_NVM; 3724 } 3725 3726 nvm->ops.acquire(hw); 3727 3728 for (i = 0; i < words; i++) { 3729 dev_spec->shadow_ram[offset + i].modified = true; 3730 dev_spec->shadow_ram[offset + i].value = data[i]; 3731 } 3732 3733 nvm->ops.release(hw); 3734 3735 return 0; 3736 } 3737 3738 /** 3739 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3740 * @hw: pointer to the HW structure 3741 * 3742 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3743 * which writes the checksum to the shadow ram. The changes in the shadow 3744 * ram are then committed to the EEPROM by processing each bank at a time 3745 * checking for the modified bit and writing only the pending changes. 3746 * After a successful commit, the shadow ram is cleared and is ready for 3747 * future writes. 3748 **/ 3749 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3750 { 3751 struct e1000_nvm_info *nvm = &hw->nvm; 3752 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3753 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3754 s32 ret_val; 3755 u32 dword = 0; 3756 3757 ret_val = e1000e_update_nvm_checksum_generic(hw); 3758 if (ret_val) 3759 goto out; 3760 3761 if (nvm->type != e1000_nvm_flash_sw) 3762 goto out; 3763 3764 nvm->ops.acquire(hw); 3765 3766 /* We're writing to the opposite bank so if we're on bank 1, 3767 * write to bank 0 etc. We also need to erase the segment that 3768 * is going to be written 3769 */ 3770 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3771 if (ret_val) { 3772 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3773 bank = 0; 3774 } 3775 3776 if (bank == 0) { 3777 new_bank_offset = nvm->flash_bank_size; 3778 old_bank_offset = 0; 3779 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3780 if (ret_val) 3781 goto release; 3782 } else { 3783 old_bank_offset = nvm->flash_bank_size; 3784 new_bank_offset = 0; 3785 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3786 if (ret_val) 3787 goto release; 3788 } 3789 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3790 /* Determine whether to write the value stored 3791 * in the other NVM bank or a modified value stored 3792 * in the shadow RAM 3793 */ 3794 ret_val = e1000_read_flash_dword_ich8lan(hw, 3795 i + old_bank_offset, 3796 &dword); 3797 3798 if (dev_spec->shadow_ram[i].modified) { 3799 dword &= 0xffff0000; 3800 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3801 } 3802 if (dev_spec->shadow_ram[i + 1].modified) { 3803 dword &= 0x0000ffff; 3804 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3805 << 16); 3806 } 3807 if (ret_val) 3808 break; 3809 3810 /* If the word is 0x13, then make sure the signature bits 3811 * (15:14) are 11b until the commit has completed. 3812 * This will allow us to write 10b which indicates the 3813 * signature is valid. We want to do this after the write 3814 * has completed so that we don't mark the segment valid 3815 * while the write is still in progress 3816 */ 3817 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3818 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3819 3820 /* Convert offset to bytes. */ 3821 act_offset = (i + new_bank_offset) << 1; 3822 3823 usleep_range(100, 200); 3824 3825 /* Write the data to the new bank. Offset in words */ 3826 act_offset = i + new_bank_offset; 3827 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 3828 dword); 3829 if (ret_val) 3830 break; 3831 } 3832 3833 /* Don't bother writing the segment valid bits if sector 3834 * programming failed. 3835 */ 3836 if (ret_val) { 3837 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3838 e_dbg("Flash commit failed.\n"); 3839 goto release; 3840 } 3841 3842 /* Finally validate the new segment by setting bit 15:14 3843 * to 10b in word 0x13 , this can be done without an 3844 * erase as well since these bits are 11 to start with 3845 * and we need to change bit 14 to 0b 3846 */ 3847 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3848 3849 /*offset in words but we read dword */ 3850 --act_offset; 3851 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3852 3853 if (ret_val) 3854 goto release; 3855 3856 dword &= 0xBFFFFFFF; 3857 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3858 3859 if (ret_val) 3860 goto release; 3861 3862 /* And invalidate the previously valid segment by setting 3863 * its signature word (0x13) high_byte to 0b. This can be 3864 * done without an erase because flash erase sets all bits 3865 * to 1's. We can write 1's to 0's without an erase 3866 */ 3867 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 3868 3869 /* offset in words but we read dword */ 3870 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 3871 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3872 3873 if (ret_val) 3874 goto release; 3875 3876 dword &= 0x00FFFFFF; 3877 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3878 3879 if (ret_val) 3880 goto release; 3881 3882 /* Great! Everything worked, we can now clear the cached entries. */ 3883 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3884 dev_spec->shadow_ram[i].modified = false; 3885 dev_spec->shadow_ram[i].value = 0xFFFF; 3886 } 3887 3888 release: 3889 nvm->ops.release(hw); 3890 3891 /* Reload the EEPROM, or else modifications will not appear 3892 * until after the next adapter reset. 3893 */ 3894 if (!ret_val) { 3895 nvm->ops.reload(hw); 3896 usleep_range(10000, 20000); 3897 } 3898 3899 out: 3900 if (ret_val) 3901 e_dbg("NVM update error: %d\n", ret_val); 3902 3903 return ret_val; 3904 } 3905 3906 /** 3907 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 3908 * @hw: pointer to the HW structure 3909 * 3910 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3911 * which writes the checksum to the shadow ram. The changes in the shadow 3912 * ram are then committed to the EEPROM by processing each bank at a time 3913 * checking for the modified bit and writing only the pending changes. 3914 * After a successful commit, the shadow ram is cleared and is ready for 3915 * future writes. 3916 **/ 3917 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 3918 { 3919 struct e1000_nvm_info *nvm = &hw->nvm; 3920 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3921 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3922 s32 ret_val; 3923 u16 data = 0; 3924 3925 ret_val = e1000e_update_nvm_checksum_generic(hw); 3926 if (ret_val) 3927 goto out; 3928 3929 if (nvm->type != e1000_nvm_flash_sw) 3930 goto out; 3931 3932 nvm->ops.acquire(hw); 3933 3934 /* We're writing to the opposite bank so if we're on bank 1, 3935 * write to bank 0 etc. We also need to erase the segment that 3936 * is going to be written 3937 */ 3938 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3939 if (ret_val) { 3940 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3941 bank = 0; 3942 } 3943 3944 if (bank == 0) { 3945 new_bank_offset = nvm->flash_bank_size; 3946 old_bank_offset = 0; 3947 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3948 if (ret_val) 3949 goto release; 3950 } else { 3951 old_bank_offset = nvm->flash_bank_size; 3952 new_bank_offset = 0; 3953 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3954 if (ret_val) 3955 goto release; 3956 } 3957 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3958 if (dev_spec->shadow_ram[i].modified) { 3959 data = dev_spec->shadow_ram[i].value; 3960 } else { 3961 ret_val = e1000_read_flash_word_ich8lan(hw, i + 3962 old_bank_offset, 3963 &data); 3964 if (ret_val) 3965 break; 3966 } 3967 3968 /* If the word is 0x13, then make sure the signature bits 3969 * (15:14) are 11b until the commit has completed. 3970 * This will allow us to write 10b which indicates the 3971 * signature is valid. We want to do this after the write 3972 * has completed so that we don't mark the segment valid 3973 * while the write is still in progress 3974 */ 3975 if (i == E1000_ICH_NVM_SIG_WORD) 3976 data |= E1000_ICH_NVM_SIG_MASK; 3977 3978 /* Convert offset to bytes. */ 3979 act_offset = (i + new_bank_offset) << 1; 3980 3981 usleep_range(100, 200); 3982 /* Write the bytes to the new bank. */ 3983 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3984 act_offset, 3985 (u8)data); 3986 if (ret_val) 3987 break; 3988 3989 usleep_range(100, 200); 3990 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3991 act_offset + 1, 3992 (u8)(data >> 8)); 3993 if (ret_val) 3994 break; 3995 } 3996 3997 /* Don't bother writing the segment valid bits if sector 3998 * programming failed. 3999 */ 4000 if (ret_val) { 4001 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4002 e_dbg("Flash commit failed.\n"); 4003 goto release; 4004 } 4005 4006 /* Finally validate the new segment by setting bit 15:14 4007 * to 10b in word 0x13 , this can be done without an 4008 * erase as well since these bits are 11 to start with 4009 * and we need to change bit 14 to 0b 4010 */ 4011 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4012 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4013 if (ret_val) 4014 goto release; 4015 4016 data &= 0xBFFF; 4017 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4018 act_offset * 2 + 1, 4019 (u8)(data >> 8)); 4020 if (ret_val) 4021 goto release; 4022 4023 /* And invalidate the previously valid segment by setting 4024 * its signature word (0x13) high_byte to 0b. This can be 4025 * done without an erase because flash erase sets all bits 4026 * to 1's. We can write 1's to 0's without an erase 4027 */ 4028 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4029 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4030 if (ret_val) 4031 goto release; 4032 4033 /* Great! Everything worked, we can now clear the cached entries. */ 4034 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4035 dev_spec->shadow_ram[i].modified = false; 4036 dev_spec->shadow_ram[i].value = 0xFFFF; 4037 } 4038 4039 release: 4040 nvm->ops.release(hw); 4041 4042 /* Reload the EEPROM, or else modifications will not appear 4043 * until after the next adapter reset. 4044 */ 4045 if (!ret_val) { 4046 nvm->ops.reload(hw); 4047 usleep_range(10000, 20000); 4048 } 4049 4050 out: 4051 if (ret_val) 4052 e_dbg("NVM update error: %d\n", ret_val); 4053 4054 return ret_val; 4055 } 4056 4057 /** 4058 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4059 * @hw: pointer to the HW structure 4060 * 4061 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4062 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4063 * calculated, in which case we need to calculate the checksum and set bit 6. 4064 **/ 4065 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4066 { 4067 s32 ret_val; 4068 u16 data; 4069 u16 word; 4070 u16 valid_csum_mask; 4071 4072 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4073 * the checksum needs to be fixed. This bit is an indication that 4074 * the NVM was prepared by OEM software and did not calculate 4075 * the checksum...a likely scenario. 4076 */ 4077 switch (hw->mac.type) { 4078 case e1000_pch_lpt: 4079 case e1000_pch_spt: 4080 case e1000_pch_cnp: 4081 word = NVM_COMPAT; 4082 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4083 break; 4084 default: 4085 word = NVM_FUTURE_INIT_WORD1; 4086 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4087 break; 4088 } 4089 4090 ret_val = e1000_read_nvm(hw, word, 1, &data); 4091 if (ret_val) 4092 return ret_val; 4093 4094 if (!(data & valid_csum_mask)) { 4095 data |= valid_csum_mask; 4096 ret_val = e1000_write_nvm(hw, word, 1, &data); 4097 if (ret_val) 4098 return ret_val; 4099 ret_val = e1000e_update_nvm_checksum(hw); 4100 if (ret_val) 4101 return ret_val; 4102 } 4103 4104 return e1000e_validate_nvm_checksum_generic(hw); 4105 } 4106 4107 /** 4108 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4109 * @hw: pointer to the HW structure 4110 * 4111 * To prevent malicious write/erase of the NVM, set it to be read-only 4112 * so that the hardware ignores all write/erase cycles of the NVM via 4113 * the flash control registers. The shadow-ram copy of the NVM will 4114 * still be updated, however any updates to this copy will not stick 4115 * across driver reloads. 4116 **/ 4117 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4118 { 4119 struct e1000_nvm_info *nvm = &hw->nvm; 4120 union ich8_flash_protected_range pr0; 4121 union ich8_hws_flash_status hsfsts; 4122 u32 gfpreg; 4123 4124 nvm->ops.acquire(hw); 4125 4126 gfpreg = er32flash(ICH_FLASH_GFPREG); 4127 4128 /* Write-protect GbE Sector of NVM */ 4129 pr0.regval = er32flash(ICH_FLASH_PR0); 4130 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4131 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4132 pr0.range.wpe = true; 4133 ew32flash(ICH_FLASH_PR0, pr0.regval); 4134 4135 /* Lock down a subset of GbE Flash Control Registers, e.g. 4136 * PR0 to prevent the write-protection from being lifted. 4137 * Once FLOCKDN is set, the registers protected by it cannot 4138 * be written until FLOCKDN is cleared by a hardware reset. 4139 */ 4140 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4141 hsfsts.hsf_status.flockdn = true; 4142 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4143 4144 nvm->ops.release(hw); 4145 } 4146 4147 /** 4148 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4149 * @hw: pointer to the HW structure 4150 * @offset: The offset (in bytes) of the byte/word to read. 4151 * @size: Size of data to read, 1=byte 2=word 4152 * @data: The byte(s) to write to the NVM. 4153 * 4154 * Writes one/two bytes to the NVM using the flash access registers. 4155 **/ 4156 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4157 u8 size, u16 data) 4158 { 4159 union ich8_hws_flash_status hsfsts; 4160 union ich8_hws_flash_ctrl hsflctl; 4161 u32 flash_linear_addr; 4162 u32 flash_data = 0; 4163 s32 ret_val; 4164 u8 count = 0; 4165 4166 if (hw->mac.type >= e1000_pch_spt) { 4167 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4168 return -E1000_ERR_NVM; 4169 } else { 4170 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4171 return -E1000_ERR_NVM; 4172 } 4173 4174 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4175 hw->nvm.flash_base_addr); 4176 4177 do { 4178 udelay(1); 4179 /* Steps */ 4180 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4181 if (ret_val) 4182 break; 4183 /* In SPT, This register is in Lan memory space, not 4184 * flash. Therefore, only 32 bit access is supported 4185 */ 4186 if (hw->mac.type >= e1000_pch_spt) 4187 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4188 else 4189 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4190 4191 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4192 hsflctl.hsf_ctrl.fldbcount = size - 1; 4193 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4194 /* In SPT, This register is in Lan memory space, 4195 * not flash. Therefore, only 32 bit access is 4196 * supported 4197 */ 4198 if (hw->mac.type >= e1000_pch_spt) 4199 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4200 else 4201 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4202 4203 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4204 4205 if (size == 1) 4206 flash_data = (u32)data & 0x00FF; 4207 else 4208 flash_data = (u32)data; 4209 4210 ew32flash(ICH_FLASH_FDATA0, flash_data); 4211 4212 /* check if FCERR is set to 1 , if set to 1, clear it 4213 * and try the whole sequence a few more times else done 4214 */ 4215 ret_val = 4216 e1000_flash_cycle_ich8lan(hw, 4217 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4218 if (!ret_val) 4219 break; 4220 4221 /* If we're here, then things are most likely 4222 * completely hosed, but if the error condition 4223 * is detected, it won't hurt to give it another 4224 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4225 */ 4226 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4227 if (hsfsts.hsf_status.flcerr) 4228 /* Repeat for some time before giving up. */ 4229 continue; 4230 if (!hsfsts.hsf_status.flcdone) { 4231 e_dbg("Timeout error - flash cycle did not complete.\n"); 4232 break; 4233 } 4234 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4235 4236 return ret_val; 4237 } 4238 4239 /** 4240 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4241 * @hw: pointer to the HW structure 4242 * @offset: The offset (in bytes) of the dwords to read. 4243 * @data: The 4 bytes to write to the NVM. 4244 * 4245 * Writes one/two/four bytes to the NVM using the flash access registers. 4246 **/ 4247 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4248 u32 data) 4249 { 4250 union ich8_hws_flash_status hsfsts; 4251 union ich8_hws_flash_ctrl hsflctl; 4252 u32 flash_linear_addr; 4253 s32 ret_val; 4254 u8 count = 0; 4255 4256 if (hw->mac.type >= e1000_pch_spt) { 4257 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4258 return -E1000_ERR_NVM; 4259 } 4260 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4261 hw->nvm.flash_base_addr); 4262 do { 4263 udelay(1); 4264 /* Steps */ 4265 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4266 if (ret_val) 4267 break; 4268 4269 /* In SPT, This register is in Lan memory space, not 4270 * flash. Therefore, only 32 bit access is supported 4271 */ 4272 if (hw->mac.type >= e1000_pch_spt) 4273 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4274 >> 16; 4275 else 4276 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4277 4278 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4279 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4280 4281 /* In SPT, This register is in Lan memory space, 4282 * not flash. Therefore, only 32 bit access is 4283 * supported 4284 */ 4285 if (hw->mac.type >= e1000_pch_spt) 4286 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4287 else 4288 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4289 4290 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4291 4292 ew32flash(ICH_FLASH_FDATA0, data); 4293 4294 /* check if FCERR is set to 1 , if set to 1, clear it 4295 * and try the whole sequence a few more times else done 4296 */ 4297 ret_val = 4298 e1000_flash_cycle_ich8lan(hw, 4299 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4300 4301 if (!ret_val) 4302 break; 4303 4304 /* If we're here, then things are most likely 4305 * completely hosed, but if the error condition 4306 * is detected, it won't hurt to give it another 4307 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4308 */ 4309 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4310 4311 if (hsfsts.hsf_status.flcerr) 4312 /* Repeat for some time before giving up. */ 4313 continue; 4314 if (!hsfsts.hsf_status.flcdone) { 4315 e_dbg("Timeout error - flash cycle did not complete.\n"); 4316 break; 4317 } 4318 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4319 4320 return ret_val; 4321 } 4322 4323 /** 4324 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4325 * @hw: pointer to the HW structure 4326 * @offset: The index of the byte to read. 4327 * @data: The byte to write to the NVM. 4328 * 4329 * Writes a single byte to the NVM using the flash access registers. 4330 **/ 4331 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4332 u8 data) 4333 { 4334 u16 word = (u16)data; 4335 4336 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4337 } 4338 4339 /** 4340 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4341 * @hw: pointer to the HW structure 4342 * @offset: The offset of the word to write. 4343 * @dword: The dword to write to the NVM. 4344 * 4345 * Writes a single dword to the NVM using the flash access registers. 4346 * Goes through a retry algorithm before giving up. 4347 **/ 4348 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4349 u32 offset, u32 dword) 4350 { 4351 s32 ret_val; 4352 u16 program_retries; 4353 4354 /* Must convert word offset into bytes. */ 4355 offset <<= 1; 4356 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4357 4358 if (!ret_val) 4359 return ret_val; 4360 for (program_retries = 0; program_retries < 100; program_retries++) { 4361 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4362 usleep_range(100, 200); 4363 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4364 if (!ret_val) 4365 break; 4366 } 4367 if (program_retries == 100) 4368 return -E1000_ERR_NVM; 4369 4370 return 0; 4371 } 4372 4373 /** 4374 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4375 * @hw: pointer to the HW structure 4376 * @offset: The offset of the byte to write. 4377 * @byte: The byte to write to the NVM. 4378 * 4379 * Writes a single byte to the NVM using the flash access registers. 4380 * Goes through a retry algorithm before giving up. 4381 **/ 4382 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4383 u32 offset, u8 byte) 4384 { 4385 s32 ret_val; 4386 u16 program_retries; 4387 4388 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4389 if (!ret_val) 4390 return ret_val; 4391 4392 for (program_retries = 0; program_retries < 100; program_retries++) { 4393 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4394 usleep_range(100, 200); 4395 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4396 if (!ret_val) 4397 break; 4398 } 4399 if (program_retries == 100) 4400 return -E1000_ERR_NVM; 4401 4402 return 0; 4403 } 4404 4405 /** 4406 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4407 * @hw: pointer to the HW structure 4408 * @bank: 0 for first bank, 1 for second bank, etc. 4409 * 4410 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4411 * bank N is 4096 * N + flash_reg_addr. 4412 **/ 4413 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4414 { 4415 struct e1000_nvm_info *nvm = &hw->nvm; 4416 union ich8_hws_flash_status hsfsts; 4417 union ich8_hws_flash_ctrl hsflctl; 4418 u32 flash_linear_addr; 4419 /* bank size is in 16bit words - adjust to bytes */ 4420 u32 flash_bank_size = nvm->flash_bank_size * 2; 4421 s32 ret_val; 4422 s32 count = 0; 4423 s32 j, iteration, sector_size; 4424 4425 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4426 4427 /* Determine HW Sector size: Read BERASE bits of hw flash status 4428 * register 4429 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4430 * consecutive sectors. The start index for the nth Hw sector 4431 * can be calculated as = bank * 4096 + n * 256 4432 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4433 * The start index for the nth Hw sector can be calculated 4434 * as = bank * 4096 4435 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4436 * (ich9 only, otherwise error condition) 4437 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4438 */ 4439 switch (hsfsts.hsf_status.berasesz) { 4440 case 0: 4441 /* Hw sector size 256 */ 4442 sector_size = ICH_FLASH_SEG_SIZE_256; 4443 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4444 break; 4445 case 1: 4446 sector_size = ICH_FLASH_SEG_SIZE_4K; 4447 iteration = 1; 4448 break; 4449 case 2: 4450 sector_size = ICH_FLASH_SEG_SIZE_8K; 4451 iteration = 1; 4452 break; 4453 case 3: 4454 sector_size = ICH_FLASH_SEG_SIZE_64K; 4455 iteration = 1; 4456 break; 4457 default: 4458 return -E1000_ERR_NVM; 4459 } 4460 4461 /* Start with the base address, then add the sector offset. */ 4462 flash_linear_addr = hw->nvm.flash_base_addr; 4463 flash_linear_addr += (bank) ? flash_bank_size : 0; 4464 4465 for (j = 0; j < iteration; j++) { 4466 do { 4467 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4468 4469 /* Steps */ 4470 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4471 if (ret_val) 4472 return ret_val; 4473 4474 /* Write a value 11 (block Erase) in Flash 4475 * Cycle field in hw flash control 4476 */ 4477 if (hw->mac.type >= e1000_pch_spt) 4478 hsflctl.regval = 4479 er32flash(ICH_FLASH_HSFSTS) >> 16; 4480 else 4481 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4482 4483 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4484 if (hw->mac.type >= e1000_pch_spt) 4485 ew32flash(ICH_FLASH_HSFSTS, 4486 hsflctl.regval << 16); 4487 else 4488 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4489 4490 /* Write the last 24 bits of an index within the 4491 * block into Flash Linear address field in Flash 4492 * Address. 4493 */ 4494 flash_linear_addr += (j * sector_size); 4495 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4496 4497 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4498 if (!ret_val) 4499 break; 4500 4501 /* Check if FCERR is set to 1. If 1, 4502 * clear it and try the whole sequence 4503 * a few more times else Done 4504 */ 4505 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4506 if (hsfsts.hsf_status.flcerr) 4507 /* repeat for some time before giving up */ 4508 continue; 4509 else if (!hsfsts.hsf_status.flcdone) 4510 return ret_val; 4511 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4512 } 4513 4514 return 0; 4515 } 4516 4517 /** 4518 * e1000_valid_led_default_ich8lan - Set the default LED settings 4519 * @hw: pointer to the HW structure 4520 * @data: Pointer to the LED settings 4521 * 4522 * Reads the LED default settings from the NVM to data. If the NVM LED 4523 * settings is all 0's or F's, set the LED default to a valid LED default 4524 * setting. 4525 **/ 4526 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4527 { 4528 s32 ret_val; 4529 4530 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4531 if (ret_val) { 4532 e_dbg("NVM Read Error\n"); 4533 return ret_val; 4534 } 4535 4536 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4537 *data = ID_LED_DEFAULT_ICH8LAN; 4538 4539 return 0; 4540 } 4541 4542 /** 4543 * e1000_id_led_init_pchlan - store LED configurations 4544 * @hw: pointer to the HW structure 4545 * 4546 * PCH does not control LEDs via the LEDCTL register, rather it uses 4547 * the PHY LED configuration register. 4548 * 4549 * PCH also does not have an "always on" or "always off" mode which 4550 * complicates the ID feature. Instead of using the "on" mode to indicate 4551 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4552 * use "link_up" mode. The LEDs will still ID on request if there is no 4553 * link based on logic in e1000_led_[on|off]_pchlan(). 4554 **/ 4555 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4556 { 4557 struct e1000_mac_info *mac = &hw->mac; 4558 s32 ret_val; 4559 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4560 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4561 u16 data, i, temp, shift; 4562 4563 /* Get default ID LED modes */ 4564 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4565 if (ret_val) 4566 return ret_val; 4567 4568 mac->ledctl_default = er32(LEDCTL); 4569 mac->ledctl_mode1 = mac->ledctl_default; 4570 mac->ledctl_mode2 = mac->ledctl_default; 4571 4572 for (i = 0; i < 4; i++) { 4573 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4574 shift = (i * 5); 4575 switch (temp) { 4576 case ID_LED_ON1_DEF2: 4577 case ID_LED_ON1_ON2: 4578 case ID_LED_ON1_OFF2: 4579 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4580 mac->ledctl_mode1 |= (ledctl_on << shift); 4581 break; 4582 case ID_LED_OFF1_DEF2: 4583 case ID_LED_OFF1_ON2: 4584 case ID_LED_OFF1_OFF2: 4585 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4586 mac->ledctl_mode1 |= (ledctl_off << shift); 4587 break; 4588 default: 4589 /* Do nothing */ 4590 break; 4591 } 4592 switch (temp) { 4593 case ID_LED_DEF1_ON2: 4594 case ID_LED_ON1_ON2: 4595 case ID_LED_OFF1_ON2: 4596 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4597 mac->ledctl_mode2 |= (ledctl_on << shift); 4598 break; 4599 case ID_LED_DEF1_OFF2: 4600 case ID_LED_ON1_OFF2: 4601 case ID_LED_OFF1_OFF2: 4602 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4603 mac->ledctl_mode2 |= (ledctl_off << shift); 4604 break; 4605 default: 4606 /* Do nothing */ 4607 break; 4608 } 4609 } 4610 4611 return 0; 4612 } 4613 4614 /** 4615 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4616 * @hw: pointer to the HW structure 4617 * 4618 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4619 * register, so the the bus width is hard coded. 4620 **/ 4621 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4622 { 4623 struct e1000_bus_info *bus = &hw->bus; 4624 s32 ret_val; 4625 4626 ret_val = e1000e_get_bus_info_pcie(hw); 4627 4628 /* ICH devices are "PCI Express"-ish. They have 4629 * a configuration space, but do not contain 4630 * PCI Express Capability registers, so bus width 4631 * must be hardcoded. 4632 */ 4633 if (bus->width == e1000_bus_width_unknown) 4634 bus->width = e1000_bus_width_pcie_x1; 4635 4636 return ret_val; 4637 } 4638 4639 /** 4640 * e1000_reset_hw_ich8lan - Reset the hardware 4641 * @hw: pointer to the HW structure 4642 * 4643 * Does a full reset of the hardware which includes a reset of the PHY and 4644 * MAC. 4645 **/ 4646 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4647 { 4648 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4649 u16 kum_cfg; 4650 u32 ctrl, reg; 4651 s32 ret_val; 4652 4653 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4654 * on the last TLP read/write transaction when MAC is reset. 4655 */ 4656 ret_val = e1000e_disable_pcie_master(hw); 4657 if (ret_val) 4658 e_dbg("PCI-E Master disable polling has failed.\n"); 4659 4660 e_dbg("Masking off all interrupts\n"); 4661 ew32(IMC, 0xffffffff); 4662 4663 /* Disable the Transmit and Receive units. Then delay to allow 4664 * any pending transactions to complete before we hit the MAC 4665 * with the global reset. 4666 */ 4667 ew32(RCTL, 0); 4668 ew32(TCTL, E1000_TCTL_PSP); 4669 e1e_flush(); 4670 4671 usleep_range(10000, 20000); 4672 4673 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4674 if (hw->mac.type == e1000_ich8lan) { 4675 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4676 ew32(PBA, E1000_PBA_8K); 4677 /* Set Packet Buffer Size to 16k. */ 4678 ew32(PBS, E1000_PBS_16K); 4679 } 4680 4681 if (hw->mac.type == e1000_pchlan) { 4682 /* Save the NVM K1 bit setting */ 4683 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4684 if (ret_val) 4685 return ret_val; 4686 4687 if (kum_cfg & E1000_NVM_K1_ENABLE) 4688 dev_spec->nvm_k1_enabled = true; 4689 else 4690 dev_spec->nvm_k1_enabled = false; 4691 } 4692 4693 ctrl = er32(CTRL); 4694 4695 if (!hw->phy.ops.check_reset_block(hw)) { 4696 /* Full-chip reset requires MAC and PHY reset at the same 4697 * time to make sure the interface between MAC and the 4698 * external PHY is reset. 4699 */ 4700 ctrl |= E1000_CTRL_PHY_RST; 4701 4702 /* Gate automatic PHY configuration by hardware on 4703 * non-managed 82579 4704 */ 4705 if ((hw->mac.type == e1000_pch2lan) && 4706 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4707 e1000_gate_hw_phy_config_ich8lan(hw, true); 4708 } 4709 ret_val = e1000_acquire_swflag_ich8lan(hw); 4710 e_dbg("Issuing a global reset to ich8lan\n"); 4711 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4712 /* cannot issue a flush here because it hangs the hardware */ 4713 msleep(20); 4714 4715 /* Set Phy Config Counter to 50msec */ 4716 if (hw->mac.type == e1000_pch2lan) { 4717 reg = er32(FEXTNVM3); 4718 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4719 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4720 ew32(FEXTNVM3, reg); 4721 } 4722 4723 if (!ret_val) 4724 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4725 4726 if (ctrl & E1000_CTRL_PHY_RST) { 4727 ret_val = hw->phy.ops.get_cfg_done(hw); 4728 if (ret_val) 4729 return ret_val; 4730 4731 ret_val = e1000_post_phy_reset_ich8lan(hw); 4732 if (ret_val) 4733 return ret_val; 4734 } 4735 4736 /* For PCH, this write will make sure that any noise 4737 * will be detected as a CRC error and be dropped rather than show up 4738 * as a bad packet to the DMA engine. 4739 */ 4740 if (hw->mac.type == e1000_pchlan) 4741 ew32(CRC_OFFSET, 0x65656565); 4742 4743 ew32(IMC, 0xffffffff); 4744 er32(ICR); 4745 4746 reg = er32(KABGTXD); 4747 reg |= E1000_KABGTXD_BGSQLBIAS; 4748 ew32(KABGTXD, reg); 4749 4750 return 0; 4751 } 4752 4753 /** 4754 * e1000_init_hw_ich8lan - Initialize the hardware 4755 * @hw: pointer to the HW structure 4756 * 4757 * Prepares the hardware for transmit and receive by doing the following: 4758 * - initialize hardware bits 4759 * - initialize LED identification 4760 * - setup receive address registers 4761 * - setup flow control 4762 * - setup transmit descriptors 4763 * - clear statistics 4764 **/ 4765 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4766 { 4767 struct e1000_mac_info *mac = &hw->mac; 4768 u32 ctrl_ext, txdctl, snoop; 4769 s32 ret_val; 4770 u16 i; 4771 4772 e1000_initialize_hw_bits_ich8lan(hw); 4773 4774 /* Initialize identification LED */ 4775 ret_val = mac->ops.id_led_init(hw); 4776 /* An error is not fatal and we should not stop init due to this */ 4777 if (ret_val) 4778 e_dbg("Error initializing identification LED\n"); 4779 4780 /* Setup the receive address. */ 4781 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4782 4783 /* Zero out the Multicast HASH table */ 4784 e_dbg("Zeroing the MTA\n"); 4785 for (i = 0; i < mac->mta_reg_count; i++) 4786 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4787 4788 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4789 * the ME. Disable wakeup by clearing the host wakeup bit. 4790 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4791 */ 4792 if (hw->phy.type == e1000_phy_82578) { 4793 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4794 i &= ~BM_WUC_HOST_WU_BIT; 4795 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 4796 ret_val = e1000_phy_hw_reset_ich8lan(hw); 4797 if (ret_val) 4798 return ret_val; 4799 } 4800 4801 /* Setup link and flow control */ 4802 ret_val = mac->ops.setup_link(hw); 4803 4804 /* Set the transmit descriptor write-back policy for both queues */ 4805 txdctl = er32(TXDCTL(0)); 4806 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4807 E1000_TXDCTL_FULL_TX_DESC_WB); 4808 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4809 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4810 ew32(TXDCTL(0), txdctl); 4811 txdctl = er32(TXDCTL(1)); 4812 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4813 E1000_TXDCTL_FULL_TX_DESC_WB); 4814 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4815 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4816 ew32(TXDCTL(1), txdctl); 4817 4818 /* ICH8 has opposite polarity of no_snoop bits. 4819 * By default, we should use snoop behavior. 4820 */ 4821 if (mac->type == e1000_ich8lan) 4822 snoop = PCIE_ICH8_SNOOP_ALL; 4823 else 4824 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 4825 e1000e_set_pcie_no_snoop(hw, snoop); 4826 4827 ctrl_ext = er32(CTRL_EXT); 4828 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 4829 ew32(CTRL_EXT, ctrl_ext); 4830 4831 /* Clear all of the statistics registers (clear on read). It is 4832 * important that we do this after we have tried to establish link 4833 * because the symbol error count will increment wildly if there 4834 * is no link. 4835 */ 4836 e1000_clear_hw_cntrs_ich8lan(hw); 4837 4838 return ret_val; 4839 } 4840 4841 /** 4842 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 4843 * @hw: pointer to the HW structure 4844 * 4845 * Sets/Clears required hardware bits necessary for correctly setting up the 4846 * hardware for transmit and receive. 4847 **/ 4848 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 4849 { 4850 u32 reg; 4851 4852 /* Extended Device Control */ 4853 reg = er32(CTRL_EXT); 4854 reg |= BIT(22); 4855 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4856 if (hw->mac.type >= e1000_pchlan) 4857 reg |= E1000_CTRL_EXT_PHYPDEN; 4858 ew32(CTRL_EXT, reg); 4859 4860 /* Transmit Descriptor Control 0 */ 4861 reg = er32(TXDCTL(0)); 4862 reg |= BIT(22); 4863 ew32(TXDCTL(0), reg); 4864 4865 /* Transmit Descriptor Control 1 */ 4866 reg = er32(TXDCTL(1)); 4867 reg |= BIT(22); 4868 ew32(TXDCTL(1), reg); 4869 4870 /* Transmit Arbitration Control 0 */ 4871 reg = er32(TARC(0)); 4872 if (hw->mac.type == e1000_ich8lan) 4873 reg |= BIT(28) | BIT(29); 4874 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 4875 ew32(TARC(0), reg); 4876 4877 /* Transmit Arbitration Control 1 */ 4878 reg = er32(TARC(1)); 4879 if (er32(TCTL) & E1000_TCTL_MULR) 4880 reg &= ~BIT(28); 4881 else 4882 reg |= BIT(28); 4883 reg |= BIT(24) | BIT(26) | BIT(30); 4884 ew32(TARC(1), reg); 4885 4886 /* Device Status */ 4887 if (hw->mac.type == e1000_ich8lan) { 4888 reg = er32(STATUS); 4889 reg &= ~BIT(31); 4890 ew32(STATUS, reg); 4891 } 4892 4893 /* work-around descriptor data corruption issue during nfs v2 udp 4894 * traffic, just disable the nfs filtering capability 4895 */ 4896 reg = er32(RFCTL); 4897 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 4898 4899 /* Disable IPv6 extension header parsing because some malformed 4900 * IPv6 headers can hang the Rx. 4901 */ 4902 if (hw->mac.type == e1000_ich8lan) 4903 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 4904 ew32(RFCTL, reg); 4905 4906 /* Enable ECC on Lynxpoint */ 4907 if (hw->mac.type >= e1000_pch_lpt) { 4908 reg = er32(PBECCSTS); 4909 reg |= E1000_PBECCSTS_ECC_ENABLE; 4910 ew32(PBECCSTS, reg); 4911 4912 reg = er32(CTRL); 4913 reg |= E1000_CTRL_MEHE; 4914 ew32(CTRL, reg); 4915 } 4916 } 4917 4918 /** 4919 * e1000_setup_link_ich8lan - Setup flow control and link settings 4920 * @hw: pointer to the HW structure 4921 * 4922 * Determines which flow control settings to use, then configures flow 4923 * control. Calls the appropriate media-specific link configuration 4924 * function. Assuming the adapter has a valid link partner, a valid link 4925 * should be established. Assumes the hardware has previously been reset 4926 * and the transmitter and receiver are not enabled. 4927 **/ 4928 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 4929 { 4930 s32 ret_val; 4931 4932 if (hw->phy.ops.check_reset_block(hw)) 4933 return 0; 4934 4935 /* ICH parts do not have a word in the NVM to determine 4936 * the default flow control setting, so we explicitly 4937 * set it to full. 4938 */ 4939 if (hw->fc.requested_mode == e1000_fc_default) { 4940 /* Workaround h/w hang when Tx flow control enabled */ 4941 if (hw->mac.type == e1000_pchlan) 4942 hw->fc.requested_mode = e1000_fc_rx_pause; 4943 else 4944 hw->fc.requested_mode = e1000_fc_full; 4945 } 4946 4947 /* Save off the requested flow control mode for use later. Depending 4948 * on the link partner's capabilities, we may or may not use this mode. 4949 */ 4950 hw->fc.current_mode = hw->fc.requested_mode; 4951 4952 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 4953 4954 /* Continue to configure the copper link. */ 4955 ret_val = hw->mac.ops.setup_physical_interface(hw); 4956 if (ret_val) 4957 return ret_val; 4958 4959 ew32(FCTTV, hw->fc.pause_time); 4960 if ((hw->phy.type == e1000_phy_82578) || 4961 (hw->phy.type == e1000_phy_82579) || 4962 (hw->phy.type == e1000_phy_i217) || 4963 (hw->phy.type == e1000_phy_82577)) { 4964 ew32(FCRTV_PCH, hw->fc.refresh_time); 4965 4966 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 4967 hw->fc.pause_time); 4968 if (ret_val) 4969 return ret_val; 4970 } 4971 4972 return e1000e_set_fc_watermarks(hw); 4973 } 4974 4975 /** 4976 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 4977 * @hw: pointer to the HW structure 4978 * 4979 * Configures the kumeran interface to the PHY to wait the appropriate time 4980 * when polling the PHY, then call the generic setup_copper_link to finish 4981 * configuring the copper link. 4982 **/ 4983 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 4984 { 4985 u32 ctrl; 4986 s32 ret_val; 4987 u16 reg_data; 4988 4989 ctrl = er32(CTRL); 4990 ctrl |= E1000_CTRL_SLU; 4991 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 4992 ew32(CTRL, ctrl); 4993 4994 /* Set the mac to wait the maximum time between each iteration 4995 * and increase the max iterations when polling the phy; 4996 * this fixes erroneous timeouts at 10Mbps. 4997 */ 4998 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 4999 if (ret_val) 5000 return ret_val; 5001 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5002 ®_data); 5003 if (ret_val) 5004 return ret_val; 5005 reg_data |= 0x3F; 5006 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5007 reg_data); 5008 if (ret_val) 5009 return ret_val; 5010 5011 switch (hw->phy.type) { 5012 case e1000_phy_igp_3: 5013 ret_val = e1000e_copper_link_setup_igp(hw); 5014 if (ret_val) 5015 return ret_val; 5016 break; 5017 case e1000_phy_bm: 5018 case e1000_phy_82578: 5019 ret_val = e1000e_copper_link_setup_m88(hw); 5020 if (ret_val) 5021 return ret_val; 5022 break; 5023 case e1000_phy_82577: 5024 case e1000_phy_82579: 5025 ret_val = e1000_copper_link_setup_82577(hw); 5026 if (ret_val) 5027 return ret_val; 5028 break; 5029 case e1000_phy_ife: 5030 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5031 if (ret_val) 5032 return ret_val; 5033 5034 reg_data &= ~IFE_PMC_AUTO_MDIX; 5035 5036 switch (hw->phy.mdix) { 5037 case 1: 5038 reg_data &= ~IFE_PMC_FORCE_MDIX; 5039 break; 5040 case 2: 5041 reg_data |= IFE_PMC_FORCE_MDIX; 5042 break; 5043 case 0: 5044 default: 5045 reg_data |= IFE_PMC_AUTO_MDIX; 5046 break; 5047 } 5048 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5049 if (ret_val) 5050 return ret_val; 5051 break; 5052 default: 5053 break; 5054 } 5055 5056 return e1000e_setup_copper_link(hw); 5057 } 5058 5059 /** 5060 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5061 * @hw: pointer to the HW structure 5062 * 5063 * Calls the PHY specific link setup function and then calls the 5064 * generic setup_copper_link to finish configuring the link for 5065 * Lynxpoint PCH devices 5066 **/ 5067 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5068 { 5069 u32 ctrl; 5070 s32 ret_val; 5071 5072 ctrl = er32(CTRL); 5073 ctrl |= E1000_CTRL_SLU; 5074 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5075 ew32(CTRL, ctrl); 5076 5077 ret_val = e1000_copper_link_setup_82577(hw); 5078 if (ret_val) 5079 return ret_val; 5080 5081 return e1000e_setup_copper_link(hw); 5082 } 5083 5084 /** 5085 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5086 * @hw: pointer to the HW structure 5087 * @speed: pointer to store current link speed 5088 * @duplex: pointer to store the current link duplex 5089 * 5090 * Calls the generic get_speed_and_duplex to retrieve the current link 5091 * information and then calls the Kumeran lock loss workaround for links at 5092 * gigabit speeds. 5093 **/ 5094 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5095 u16 *duplex) 5096 { 5097 s32 ret_val; 5098 5099 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5100 if (ret_val) 5101 return ret_val; 5102 5103 if ((hw->mac.type == e1000_ich8lan) && 5104 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5105 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5106 } 5107 5108 return ret_val; 5109 } 5110 5111 /** 5112 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5113 * @hw: pointer to the HW structure 5114 * 5115 * Work-around for 82566 Kumeran PCS lock loss: 5116 * On link status change (i.e. PCI reset, speed change) and link is up and 5117 * speed is gigabit- 5118 * 0) if workaround is optionally disabled do nothing 5119 * 1) wait 1ms for Kumeran link to come up 5120 * 2) check Kumeran Diagnostic register PCS lock loss bit 5121 * 3) if not set the link is locked (all is good), otherwise... 5122 * 4) reset the PHY 5123 * 5) repeat up to 10 times 5124 * Note: this is only called for IGP3 copper when speed is 1gb. 5125 **/ 5126 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5127 { 5128 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5129 u32 phy_ctrl; 5130 s32 ret_val; 5131 u16 i, data; 5132 bool link; 5133 5134 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5135 return 0; 5136 5137 /* Make sure link is up before proceeding. If not just return. 5138 * Attempting this while link is negotiating fouled up link 5139 * stability 5140 */ 5141 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5142 if (!link) 5143 return 0; 5144 5145 for (i = 0; i < 10; i++) { 5146 /* read once to clear */ 5147 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5148 if (ret_val) 5149 return ret_val; 5150 /* and again to get new status */ 5151 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5152 if (ret_val) 5153 return ret_val; 5154 5155 /* check for PCS lock */ 5156 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5157 return 0; 5158 5159 /* Issue PHY reset */ 5160 e1000_phy_hw_reset(hw); 5161 mdelay(5); 5162 } 5163 /* Disable GigE link negotiation */ 5164 phy_ctrl = er32(PHY_CTRL); 5165 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5166 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5167 ew32(PHY_CTRL, phy_ctrl); 5168 5169 /* Call gig speed drop workaround on Gig disable before accessing 5170 * any PHY registers 5171 */ 5172 e1000e_gig_downshift_workaround_ich8lan(hw); 5173 5174 /* unable to acquire PCS lock */ 5175 return -E1000_ERR_PHY; 5176 } 5177 5178 /** 5179 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5180 * @hw: pointer to the HW structure 5181 * @state: boolean value used to set the current Kumeran workaround state 5182 * 5183 * If ICH8, set the current Kumeran workaround state (enabled - true 5184 * /disabled - false). 5185 **/ 5186 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5187 bool state) 5188 { 5189 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5190 5191 if (hw->mac.type != e1000_ich8lan) { 5192 e_dbg("Workaround applies to ICH8 only.\n"); 5193 return; 5194 } 5195 5196 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5197 } 5198 5199 /** 5200 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5201 * @hw: pointer to the HW structure 5202 * 5203 * Workaround for 82566 power-down on D3 entry: 5204 * 1) disable gigabit link 5205 * 2) write VR power-down enable 5206 * 3) read it back 5207 * Continue if successful, else issue LCD reset and repeat 5208 **/ 5209 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5210 { 5211 u32 reg; 5212 u16 data; 5213 u8 retry = 0; 5214 5215 if (hw->phy.type != e1000_phy_igp_3) 5216 return; 5217 5218 /* Try the workaround twice (if needed) */ 5219 do { 5220 /* Disable link */ 5221 reg = er32(PHY_CTRL); 5222 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5223 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5224 ew32(PHY_CTRL, reg); 5225 5226 /* Call gig speed drop workaround on Gig disable before 5227 * accessing any PHY registers 5228 */ 5229 if (hw->mac.type == e1000_ich8lan) 5230 e1000e_gig_downshift_workaround_ich8lan(hw); 5231 5232 /* Write VR power-down enable */ 5233 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5234 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5235 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5236 5237 /* Read it back and test */ 5238 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5239 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5240 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5241 break; 5242 5243 /* Issue PHY reset and repeat at most one more time */ 5244 reg = er32(CTRL); 5245 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5246 retry++; 5247 } while (retry); 5248 } 5249 5250 /** 5251 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5252 * @hw: pointer to the HW structure 5253 * 5254 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5255 * LPLU, Gig disable, MDIC PHY reset): 5256 * 1) Set Kumeran Near-end loopback 5257 * 2) Clear Kumeran Near-end loopback 5258 * Should only be called for ICH8[m] devices with any 1G Phy. 5259 **/ 5260 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5261 { 5262 s32 ret_val; 5263 u16 reg_data; 5264 5265 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5266 return; 5267 5268 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5269 ®_data); 5270 if (ret_val) 5271 return; 5272 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5273 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5274 reg_data); 5275 if (ret_val) 5276 return; 5277 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5278 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5279 } 5280 5281 /** 5282 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5283 * @hw: pointer to the HW structure 5284 * 5285 * During S0 to Sx transition, it is possible the link remains at gig 5286 * instead of negotiating to a lower speed. Before going to Sx, set 5287 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5288 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5289 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5290 * needs to be written. 5291 * Parts that support (and are linked to a partner which support) EEE in 5292 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5293 * than 10Mbps w/o EEE. 5294 **/ 5295 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5296 { 5297 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5298 u32 phy_ctrl; 5299 s32 ret_val; 5300 5301 phy_ctrl = er32(PHY_CTRL); 5302 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5303 5304 if (hw->phy.type == e1000_phy_i217) { 5305 u16 phy_reg, device_id = hw->adapter->pdev->device; 5306 5307 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5308 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5309 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5310 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5311 (hw->mac.type >= e1000_pch_spt)) { 5312 u32 fextnvm6 = er32(FEXTNVM6); 5313 5314 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5315 } 5316 5317 ret_val = hw->phy.ops.acquire(hw); 5318 if (ret_val) 5319 goto out; 5320 5321 if (!dev_spec->eee_disable) { 5322 u16 eee_advert; 5323 5324 ret_val = 5325 e1000_read_emi_reg_locked(hw, 5326 I217_EEE_ADVERTISEMENT, 5327 &eee_advert); 5328 if (ret_val) 5329 goto release; 5330 5331 /* Disable LPLU if both link partners support 100BaseT 5332 * EEE and 100Full is advertised on both ends of the 5333 * link, and enable Auto Enable LPI since there will 5334 * be no driver to enable LPI while in Sx. 5335 */ 5336 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5337 (dev_spec->eee_lp_ability & 5338 I82579_EEE_100_SUPPORTED) && 5339 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5340 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5341 E1000_PHY_CTRL_NOND0A_LPLU); 5342 5343 /* Set Auto Enable LPI after link up */ 5344 e1e_rphy_locked(hw, 5345 I217_LPI_GPIO_CTRL, &phy_reg); 5346 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5347 e1e_wphy_locked(hw, 5348 I217_LPI_GPIO_CTRL, phy_reg); 5349 } 5350 } 5351 5352 /* For i217 Intel Rapid Start Technology support, 5353 * when the system is going into Sx and no manageability engine 5354 * is present, the driver must configure proxy to reset only on 5355 * power good. LPI (Low Power Idle) state must also reset only 5356 * on power good, as well as the MTA (Multicast table array). 5357 * The SMBus release must also be disabled on LCD reset. 5358 */ 5359 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5360 /* Enable proxy to reset only on power good. */ 5361 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5362 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5363 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5364 5365 /* Set bit enable LPI (EEE) to reset only on 5366 * power good. 5367 */ 5368 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5369 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5370 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5371 5372 /* Disable the SMB release on LCD reset. */ 5373 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5374 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5375 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5376 } 5377 5378 /* Enable MTA to reset for Intel Rapid Start Technology 5379 * Support 5380 */ 5381 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5382 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5383 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5384 5385 release: 5386 hw->phy.ops.release(hw); 5387 } 5388 out: 5389 ew32(PHY_CTRL, phy_ctrl); 5390 5391 if (hw->mac.type == e1000_ich8lan) 5392 e1000e_gig_downshift_workaround_ich8lan(hw); 5393 5394 if (hw->mac.type >= e1000_pchlan) { 5395 e1000_oem_bits_config_ich8lan(hw, false); 5396 5397 /* Reset PHY to activate OEM bits on 82577/8 */ 5398 if (hw->mac.type == e1000_pchlan) 5399 e1000e_phy_hw_reset_generic(hw); 5400 5401 ret_val = hw->phy.ops.acquire(hw); 5402 if (ret_val) 5403 return; 5404 e1000_write_smbus_addr(hw); 5405 hw->phy.ops.release(hw); 5406 } 5407 } 5408 5409 /** 5410 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5411 * @hw: pointer to the HW structure 5412 * 5413 * During Sx to S0 transitions on non-managed devices or managed devices 5414 * on which PHY resets are not blocked, if the PHY registers cannot be 5415 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5416 * the PHY. 5417 * On i217, setup Intel Rapid Start Technology. 5418 **/ 5419 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5420 { 5421 s32 ret_val; 5422 5423 if (hw->mac.type < e1000_pch2lan) 5424 return; 5425 5426 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5427 if (ret_val) { 5428 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5429 return; 5430 } 5431 5432 /* For i217 Intel Rapid Start Technology support when the system 5433 * is transitioning from Sx and no manageability engine is present 5434 * configure SMBus to restore on reset, disable proxy, and enable 5435 * the reset on MTA (Multicast table array). 5436 */ 5437 if (hw->phy.type == e1000_phy_i217) { 5438 u16 phy_reg; 5439 5440 ret_val = hw->phy.ops.acquire(hw); 5441 if (ret_val) { 5442 e_dbg("Failed to setup iRST\n"); 5443 return; 5444 } 5445 5446 /* Clear Auto Enable LPI after link up */ 5447 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5448 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5449 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5450 5451 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5452 /* Restore clear on SMB if no manageability engine 5453 * is present 5454 */ 5455 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5456 if (ret_val) 5457 goto release; 5458 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5459 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5460 5461 /* Disable Proxy */ 5462 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5463 } 5464 /* Enable reset on MTA */ 5465 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5466 if (ret_val) 5467 goto release; 5468 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5469 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5470 release: 5471 if (ret_val) 5472 e_dbg("Error %d in resume workarounds\n", ret_val); 5473 hw->phy.ops.release(hw); 5474 } 5475 } 5476 5477 /** 5478 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5479 * @hw: pointer to the HW structure 5480 * 5481 * Return the LED back to the default configuration. 5482 **/ 5483 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5484 { 5485 if (hw->phy.type == e1000_phy_ife) 5486 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5487 5488 ew32(LEDCTL, hw->mac.ledctl_default); 5489 return 0; 5490 } 5491 5492 /** 5493 * e1000_led_on_ich8lan - Turn LEDs on 5494 * @hw: pointer to the HW structure 5495 * 5496 * Turn on the LEDs. 5497 **/ 5498 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5499 { 5500 if (hw->phy.type == e1000_phy_ife) 5501 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5502 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5503 5504 ew32(LEDCTL, hw->mac.ledctl_mode2); 5505 return 0; 5506 } 5507 5508 /** 5509 * e1000_led_off_ich8lan - Turn LEDs off 5510 * @hw: pointer to the HW structure 5511 * 5512 * Turn off the LEDs. 5513 **/ 5514 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5515 { 5516 if (hw->phy.type == e1000_phy_ife) 5517 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5518 (IFE_PSCL_PROBE_MODE | 5519 IFE_PSCL_PROBE_LEDS_OFF)); 5520 5521 ew32(LEDCTL, hw->mac.ledctl_mode1); 5522 return 0; 5523 } 5524 5525 /** 5526 * e1000_setup_led_pchlan - Configures SW controllable LED 5527 * @hw: pointer to the HW structure 5528 * 5529 * This prepares the SW controllable LED for use. 5530 **/ 5531 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5532 { 5533 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5534 } 5535 5536 /** 5537 * e1000_cleanup_led_pchlan - Restore the default LED operation 5538 * @hw: pointer to the HW structure 5539 * 5540 * Return the LED back to the default configuration. 5541 **/ 5542 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5543 { 5544 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5545 } 5546 5547 /** 5548 * e1000_led_on_pchlan - Turn LEDs on 5549 * @hw: pointer to the HW structure 5550 * 5551 * Turn on the LEDs. 5552 **/ 5553 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5554 { 5555 u16 data = (u16)hw->mac.ledctl_mode2; 5556 u32 i, led; 5557 5558 /* If no link, then turn LED on by setting the invert bit 5559 * for each LED that's mode is "link_up" in ledctl_mode2. 5560 */ 5561 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5562 for (i = 0; i < 3; i++) { 5563 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5564 if ((led & E1000_PHY_LED0_MODE_MASK) != 5565 E1000_LEDCTL_MODE_LINK_UP) 5566 continue; 5567 if (led & E1000_PHY_LED0_IVRT) 5568 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5569 else 5570 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5571 } 5572 } 5573 5574 return e1e_wphy(hw, HV_LED_CONFIG, data); 5575 } 5576 5577 /** 5578 * e1000_led_off_pchlan - Turn LEDs off 5579 * @hw: pointer to the HW structure 5580 * 5581 * Turn off the LEDs. 5582 **/ 5583 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5584 { 5585 u16 data = (u16)hw->mac.ledctl_mode1; 5586 u32 i, led; 5587 5588 /* If no link, then turn LED off by clearing the invert bit 5589 * for each LED that's mode is "link_up" in ledctl_mode1. 5590 */ 5591 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5592 for (i = 0; i < 3; i++) { 5593 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5594 if ((led & E1000_PHY_LED0_MODE_MASK) != 5595 E1000_LEDCTL_MODE_LINK_UP) 5596 continue; 5597 if (led & E1000_PHY_LED0_IVRT) 5598 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5599 else 5600 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5601 } 5602 } 5603 5604 return e1e_wphy(hw, HV_LED_CONFIG, data); 5605 } 5606 5607 /** 5608 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5609 * @hw: pointer to the HW structure 5610 * 5611 * Read appropriate register for the config done bit for completion status 5612 * and configure the PHY through s/w for EEPROM-less parts. 5613 * 5614 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5615 * config done bit, so only an error is logged and continues. If we were 5616 * to return with error, EEPROM-less silicon would not be able to be reset 5617 * or change link. 5618 **/ 5619 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5620 { 5621 s32 ret_val = 0; 5622 u32 bank = 0; 5623 u32 status; 5624 5625 e1000e_get_cfg_done_generic(hw); 5626 5627 /* Wait for indication from h/w that it has completed basic config */ 5628 if (hw->mac.type >= e1000_ich10lan) { 5629 e1000_lan_init_done_ich8lan(hw); 5630 } else { 5631 ret_val = e1000e_get_auto_rd_done(hw); 5632 if (ret_val) { 5633 /* When auto config read does not complete, do not 5634 * return with an error. This can happen in situations 5635 * where there is no eeprom and prevents getting link. 5636 */ 5637 e_dbg("Auto Read Done did not complete\n"); 5638 ret_val = 0; 5639 } 5640 } 5641 5642 /* Clear PHY Reset Asserted bit */ 5643 status = er32(STATUS); 5644 if (status & E1000_STATUS_PHYRA) 5645 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5646 else 5647 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5648 5649 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5650 if (hw->mac.type <= e1000_ich9lan) { 5651 if (!(er32(EECD) & E1000_EECD_PRES) && 5652 (hw->phy.type == e1000_phy_igp_3)) { 5653 e1000e_phy_init_script_igp3(hw); 5654 } 5655 } else { 5656 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5657 /* Maybe we should do a basic PHY config */ 5658 e_dbg("EEPROM not present\n"); 5659 ret_val = -E1000_ERR_CONFIG; 5660 } 5661 } 5662 5663 return ret_val; 5664 } 5665 5666 /** 5667 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5668 * @hw: pointer to the HW structure 5669 * 5670 * In the case of a PHY power down to save power, or to turn off link during a 5671 * driver unload, or wake on lan is not enabled, remove the link. 5672 **/ 5673 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5674 { 5675 /* If the management interface is not enabled, then power down */ 5676 if (!(hw->mac.ops.check_mng_mode(hw) || 5677 hw->phy.ops.check_reset_block(hw))) 5678 e1000_power_down_phy_copper(hw); 5679 } 5680 5681 /** 5682 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5683 * @hw: pointer to the HW structure 5684 * 5685 * Clears hardware counters specific to the silicon family and calls 5686 * clear_hw_cntrs_generic to clear all general purpose counters. 5687 **/ 5688 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5689 { 5690 u16 phy_data; 5691 s32 ret_val; 5692 5693 e1000e_clear_hw_cntrs_base(hw); 5694 5695 er32(ALGNERRC); 5696 er32(RXERRC); 5697 er32(TNCRS); 5698 er32(CEXTERR); 5699 er32(TSCTC); 5700 er32(TSCTFC); 5701 5702 er32(MGTPRC); 5703 er32(MGTPDC); 5704 er32(MGTPTC); 5705 5706 er32(IAC); 5707 er32(ICRXOC); 5708 5709 /* Clear PHY statistics registers */ 5710 if ((hw->phy.type == e1000_phy_82578) || 5711 (hw->phy.type == e1000_phy_82579) || 5712 (hw->phy.type == e1000_phy_i217) || 5713 (hw->phy.type == e1000_phy_82577)) { 5714 ret_val = hw->phy.ops.acquire(hw); 5715 if (ret_val) 5716 return; 5717 ret_val = hw->phy.ops.set_page(hw, 5718 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5719 if (ret_val) 5720 goto release; 5721 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5722 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5723 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5724 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5725 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5726 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5727 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5728 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5729 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5730 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5731 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5732 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5733 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5734 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5735 release: 5736 hw->phy.ops.release(hw); 5737 } 5738 } 5739 5740 static const struct e1000_mac_operations ich8_mac_ops = { 5741 /* check_mng_mode dependent on mac type */ 5742 .check_for_link = e1000_check_for_copper_link_ich8lan, 5743 /* cleanup_led dependent on mac type */ 5744 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5745 .get_bus_info = e1000_get_bus_info_ich8lan, 5746 .set_lan_id = e1000_set_lan_id_single_port, 5747 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5748 /* led_on dependent on mac type */ 5749 /* led_off dependent on mac type */ 5750 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5751 .reset_hw = e1000_reset_hw_ich8lan, 5752 .init_hw = e1000_init_hw_ich8lan, 5753 .setup_link = e1000_setup_link_ich8lan, 5754 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5755 /* id_led_init dependent on mac type */ 5756 .config_collision_dist = e1000e_config_collision_dist_generic, 5757 .rar_set = e1000e_rar_set_generic, 5758 .rar_get_count = e1000e_rar_get_count_generic, 5759 }; 5760 5761 static const struct e1000_phy_operations ich8_phy_ops = { 5762 .acquire = e1000_acquire_swflag_ich8lan, 5763 .check_reset_block = e1000_check_reset_block_ich8lan, 5764 .commit = NULL, 5765 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5766 .get_cable_length = e1000e_get_cable_length_igp_2, 5767 .read_reg = e1000e_read_phy_reg_igp, 5768 .release = e1000_release_swflag_ich8lan, 5769 .reset = e1000_phy_hw_reset_ich8lan, 5770 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5771 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5772 .write_reg = e1000e_write_phy_reg_igp, 5773 }; 5774 5775 static const struct e1000_nvm_operations ich8_nvm_ops = { 5776 .acquire = e1000_acquire_nvm_ich8lan, 5777 .read = e1000_read_nvm_ich8lan, 5778 .release = e1000_release_nvm_ich8lan, 5779 .reload = e1000e_reload_nvm_generic, 5780 .update = e1000_update_nvm_checksum_ich8lan, 5781 .valid_led_default = e1000_valid_led_default_ich8lan, 5782 .validate = e1000_validate_nvm_checksum_ich8lan, 5783 .write = e1000_write_nvm_ich8lan, 5784 }; 5785 5786 static const struct e1000_nvm_operations spt_nvm_ops = { 5787 .acquire = e1000_acquire_nvm_ich8lan, 5788 .release = e1000_release_nvm_ich8lan, 5789 .read = e1000_read_nvm_spt, 5790 .update = e1000_update_nvm_checksum_spt, 5791 .reload = e1000e_reload_nvm_generic, 5792 .valid_led_default = e1000_valid_led_default_ich8lan, 5793 .validate = e1000_validate_nvm_checksum_ich8lan, 5794 .write = e1000_write_nvm_ich8lan, 5795 }; 5796 5797 const struct e1000_info e1000_ich8_info = { 5798 .mac = e1000_ich8lan, 5799 .flags = FLAG_HAS_WOL 5800 | FLAG_IS_ICH 5801 | FLAG_HAS_CTRLEXT_ON_LOAD 5802 | FLAG_HAS_AMT 5803 | FLAG_HAS_FLASH 5804 | FLAG_APME_IN_WUC, 5805 .pba = 8, 5806 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 5807 .get_variants = e1000_get_variants_ich8lan, 5808 .mac_ops = &ich8_mac_ops, 5809 .phy_ops = &ich8_phy_ops, 5810 .nvm_ops = &ich8_nvm_ops, 5811 }; 5812 5813 const struct e1000_info e1000_ich9_info = { 5814 .mac = e1000_ich9lan, 5815 .flags = FLAG_HAS_JUMBO_FRAMES 5816 | FLAG_IS_ICH 5817 | FLAG_HAS_WOL 5818 | FLAG_HAS_CTRLEXT_ON_LOAD 5819 | FLAG_HAS_AMT 5820 | FLAG_HAS_FLASH 5821 | FLAG_APME_IN_WUC, 5822 .pba = 18, 5823 .max_hw_frame_size = DEFAULT_JUMBO, 5824 .get_variants = e1000_get_variants_ich8lan, 5825 .mac_ops = &ich8_mac_ops, 5826 .phy_ops = &ich8_phy_ops, 5827 .nvm_ops = &ich8_nvm_ops, 5828 }; 5829 5830 const struct e1000_info e1000_ich10_info = { 5831 .mac = e1000_ich10lan, 5832 .flags = FLAG_HAS_JUMBO_FRAMES 5833 | FLAG_IS_ICH 5834 | FLAG_HAS_WOL 5835 | FLAG_HAS_CTRLEXT_ON_LOAD 5836 | FLAG_HAS_AMT 5837 | FLAG_HAS_FLASH 5838 | FLAG_APME_IN_WUC, 5839 .pba = 18, 5840 .max_hw_frame_size = DEFAULT_JUMBO, 5841 .get_variants = e1000_get_variants_ich8lan, 5842 .mac_ops = &ich8_mac_ops, 5843 .phy_ops = &ich8_phy_ops, 5844 .nvm_ops = &ich8_nvm_ops, 5845 }; 5846 5847 const struct e1000_info e1000_pch_info = { 5848 .mac = e1000_pchlan, 5849 .flags = FLAG_IS_ICH 5850 | FLAG_HAS_WOL 5851 | FLAG_HAS_CTRLEXT_ON_LOAD 5852 | FLAG_HAS_AMT 5853 | FLAG_HAS_FLASH 5854 | FLAG_HAS_JUMBO_FRAMES 5855 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 5856 | FLAG_APME_IN_WUC, 5857 .flags2 = FLAG2_HAS_PHY_STATS, 5858 .pba = 26, 5859 .max_hw_frame_size = 4096, 5860 .get_variants = e1000_get_variants_ich8lan, 5861 .mac_ops = &ich8_mac_ops, 5862 .phy_ops = &ich8_phy_ops, 5863 .nvm_ops = &ich8_nvm_ops, 5864 }; 5865 5866 const struct e1000_info e1000_pch2_info = { 5867 .mac = e1000_pch2lan, 5868 .flags = FLAG_IS_ICH 5869 | FLAG_HAS_WOL 5870 | FLAG_HAS_HW_TIMESTAMP 5871 | FLAG_HAS_CTRLEXT_ON_LOAD 5872 | FLAG_HAS_AMT 5873 | FLAG_HAS_FLASH 5874 | FLAG_HAS_JUMBO_FRAMES 5875 | FLAG_APME_IN_WUC, 5876 .flags2 = FLAG2_HAS_PHY_STATS 5877 | FLAG2_HAS_EEE 5878 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5879 .pba = 26, 5880 .max_hw_frame_size = 9022, 5881 .get_variants = e1000_get_variants_ich8lan, 5882 .mac_ops = &ich8_mac_ops, 5883 .phy_ops = &ich8_phy_ops, 5884 .nvm_ops = &ich8_nvm_ops, 5885 }; 5886 5887 const struct e1000_info e1000_pch_lpt_info = { 5888 .mac = e1000_pch_lpt, 5889 .flags = FLAG_IS_ICH 5890 | FLAG_HAS_WOL 5891 | FLAG_HAS_HW_TIMESTAMP 5892 | FLAG_HAS_CTRLEXT_ON_LOAD 5893 | FLAG_HAS_AMT 5894 | FLAG_HAS_FLASH 5895 | FLAG_HAS_JUMBO_FRAMES 5896 | FLAG_APME_IN_WUC, 5897 .flags2 = FLAG2_HAS_PHY_STATS 5898 | FLAG2_HAS_EEE 5899 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5900 .pba = 26, 5901 .max_hw_frame_size = 9022, 5902 .get_variants = e1000_get_variants_ich8lan, 5903 .mac_ops = &ich8_mac_ops, 5904 .phy_ops = &ich8_phy_ops, 5905 .nvm_ops = &ich8_nvm_ops, 5906 }; 5907 5908 const struct e1000_info e1000_pch_spt_info = { 5909 .mac = e1000_pch_spt, 5910 .flags = FLAG_IS_ICH 5911 | FLAG_HAS_WOL 5912 | FLAG_HAS_HW_TIMESTAMP 5913 | FLAG_HAS_CTRLEXT_ON_LOAD 5914 | FLAG_HAS_AMT 5915 | FLAG_HAS_FLASH 5916 | FLAG_HAS_JUMBO_FRAMES 5917 | FLAG_APME_IN_WUC, 5918 .flags2 = FLAG2_HAS_PHY_STATS 5919 | FLAG2_HAS_EEE, 5920 .pba = 26, 5921 .max_hw_frame_size = 9022, 5922 .get_variants = e1000_get_variants_ich8lan, 5923 .mac_ops = &ich8_mac_ops, 5924 .phy_ops = &ich8_phy_ops, 5925 .nvm_ops = &spt_nvm_ops, 5926 }; 5927 5928 const struct e1000_info e1000_pch_cnp_info = { 5929 .mac = e1000_pch_cnp, 5930 .flags = FLAG_IS_ICH 5931 | FLAG_HAS_WOL 5932 | FLAG_HAS_HW_TIMESTAMP 5933 | FLAG_HAS_CTRLEXT_ON_LOAD 5934 | FLAG_HAS_AMT 5935 | FLAG_HAS_FLASH 5936 | FLAG_HAS_JUMBO_FRAMES 5937 | FLAG_APME_IN_WUC, 5938 .flags2 = FLAG2_HAS_PHY_STATS 5939 | FLAG2_HAS_EEE, 5940 .pba = 26, 5941 .max_hw_frame_size = 9022, 5942 .get_variants = e1000_get_variants_ich8lan, 5943 .mac_ops = &ich8_mac_ops, 5944 .phy_ops = &ich8_phy_ops, 5945 .nvm_ops = &spt_nvm_ops, 5946 }; 5947