1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* 82562G 10/100 Network Connection 5 * 82562G-2 10/100 Network Connection 6 * 82562GT 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 8 * 82562V 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 11 * 82566DC Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 13 * 82566DM Gigabit Network Connection 14 * 82566MC Gigabit Network Connection 15 * 82566MM Gigabit Network Connection 16 * 82567LM Gigabit Network Connection 17 * 82567LF Gigabit Network Connection 18 * 82567V Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection 22 * 82567LF-3 Gigabit Network Connection 23 * 82567LM-3 Gigabit Network Connection 24 * 82567LM-4 Gigabit Network Connection 25 * 82577LM Gigabit Network Connection 26 * 82577LC Gigabit Network Connection 27 * 82578DM Gigabit Network Connection 28 * 82578DC Gigabit Network Connection 29 * 82579LM Gigabit Network Connection 30 * 82579V Gigabit Network Connection 31 * Ethernet Connection I217-LM 32 * Ethernet Connection I217-V 33 * Ethernet Connection I218-V 34 * Ethernet Connection I218-LM 35 * Ethernet Connection (2) I218-LM 36 * Ethernet Connection (2) I218-V 37 * Ethernet Connection (3) I218-LM 38 * Ethernet Connection (3) I218-V 39 */ 40 41 #include "e1000.h" 42 43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 44 /* Offset 04h HSFSTS */ 45 union ich8_hws_flash_status { 46 struct ich8_hsfsts { 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 48 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 49 u16 dael:1; /* bit 2 Direct Access error Log */ 50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 52 u16 reserved1:2; /* bit 13:6 Reserved */ 53 u16 reserved2:6; /* bit 13:6 Reserved */ 54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 56 } hsf_status; 57 u16 regval; 58 }; 59 60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 61 /* Offset 06h FLCTL */ 62 union ich8_hws_flash_ctrl { 63 struct ich8_hsflctl { 64 u16 flcgo:1; /* 0 Flash Cycle Go */ 65 u16 flcycle:2; /* 2:1 Flash Cycle */ 66 u16 reserved:5; /* 7:3 Reserved */ 67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 68 u16 flockdn:6; /* 15:10 Reserved */ 69 } hsf_ctrl; 70 u16 regval; 71 }; 72 73 /* ICH Flash Region Access Permissions */ 74 union ich8_hws_flash_regacc { 75 struct ich8_flracc { 76 u32 grra:8; /* 0:7 GbE region Read Access */ 77 u32 grwa:8; /* 8:15 GbE region Write Access */ 78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 80 } hsf_flregacc; 81 u16 regval; 82 }; 83 84 /* ICH Flash Protected Region */ 85 union ich8_flash_protected_range { 86 struct ich8_pr { 87 u32 base:13; /* 0:12 Protected Range Base */ 88 u32 reserved1:2; /* 13:14 Reserved */ 89 u32 rpe:1; /* 15 Read Protection Enable */ 90 u32 limit:13; /* 16:28 Protected Range Limit */ 91 u32 reserved2:2; /* 29:30 Reserved */ 92 u32 wpe:1; /* 31 Write Protection Enable */ 93 } range; 94 u32 regval; 95 }; 96 97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 101 u32 offset, u8 byte); 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 103 u8 *data); 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 105 u16 *data); 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 107 u8 size, u16 *data); 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 109 u32 *data); 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 111 u32 offset, u32 *data); 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 113 u32 offset, u32 data); 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 115 u32 offset, u32 dword); 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 140 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 142 { 143 return readw(hw->flash_address + reg); 144 } 145 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 147 { 148 return readl(hw->flash_address + reg); 149 } 150 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 152 { 153 writew(val, hw->flash_address + reg); 154 } 155 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 157 { 158 writel(val, hw->flash_address + reg); 159 } 160 161 #define er16flash(reg) __er16flash(hw, (reg)) 162 #define er32flash(reg) __er32flash(hw, (reg)) 163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 165 166 /** 167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 168 * @hw: pointer to the HW structure 169 * 170 * Test access to the PHY registers by reading the PHY ID registers. If 171 * the PHY ID is already known (e.g. resume path) compare it with known ID, 172 * otherwise assume the read PHY ID is correct if it is valid. 173 * 174 * Assumes the sw/fw/hw semaphore is already acquired. 175 **/ 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 177 { 178 u16 phy_reg = 0; 179 u32 phy_id = 0; 180 s32 ret_val = 0; 181 u16 retry_count; 182 u32 mac_reg = 0; 183 184 for (retry_count = 0; retry_count < 2; retry_count++) { 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 186 if (ret_val || (phy_reg == 0xFFFF)) 187 continue; 188 phy_id = (u32)(phy_reg << 16); 189 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) { 192 phy_id = 0; 193 continue; 194 } 195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 196 break; 197 } 198 199 if (hw->phy.id) { 200 if (hw->phy.id == phy_id) 201 goto out; 202 } else if (phy_id) { 203 hw->phy.id = phy_id; 204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 205 goto out; 206 } 207 208 /* In case the PHY needs to be in mdio slow mode, 209 * set slow mode and try to get the PHY id again. 210 */ 211 if (hw->mac.type < e1000_pch_lpt) { 212 hw->phy.ops.release(hw); 213 ret_val = e1000_set_mdio_slow_mode_hv(hw); 214 if (!ret_val) 215 ret_val = e1000e_get_phy_id(hw); 216 hw->phy.ops.acquire(hw); 217 } 218 219 if (ret_val) 220 return false; 221 out: 222 if (hw->mac.type >= e1000_pch_lpt) { 223 /* Only unforce SMBus if ME is not active */ 224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 225 /* Switching PHY interface always returns MDI error 226 * so disable retry mechanism to avoid wasting time 227 */ 228 e1000e_disable_phy_retry(hw); 229 230 /* Unforce SMBus mode in PHY */ 231 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 232 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 233 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 234 235 e1000e_enable_phy_retry(hw); 236 237 /* Unforce SMBus mode in MAC */ 238 mac_reg = er32(CTRL_EXT); 239 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 240 ew32(CTRL_EXT, mac_reg); 241 } 242 } 243 244 return true; 245 } 246 247 /** 248 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 249 * @hw: pointer to the HW structure 250 * 251 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 252 * used to reset the PHY to a quiescent state when necessary. 253 **/ 254 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 255 { 256 u32 mac_reg; 257 258 /* Set Phy Config Counter to 50msec */ 259 mac_reg = er32(FEXTNVM3); 260 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 261 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 262 ew32(FEXTNVM3, mac_reg); 263 264 /* Toggle LANPHYPC Value bit */ 265 mac_reg = er32(CTRL); 266 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 267 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 268 ew32(CTRL, mac_reg); 269 e1e_flush(); 270 usleep_range(10, 20); 271 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 272 ew32(CTRL, mac_reg); 273 e1e_flush(); 274 275 if (hw->mac.type < e1000_pch_lpt) { 276 msleep(50); 277 } else { 278 u16 count = 20; 279 280 do { 281 usleep_range(5000, 6000); 282 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 283 284 msleep(30); 285 } 286 } 287 288 /** 289 * e1000_reconfigure_k1_exit_timeout - reconfigure K1 exit timeout to 290 * align to MTP and later platform requirements. 291 * @hw: pointer to the HW structure 292 * 293 * Context: PHY semaphore must be held by caller. 294 * Return: 0 on success, negative on failure 295 */ 296 static s32 e1000_reconfigure_k1_exit_timeout(struct e1000_hw *hw) 297 { 298 u16 phy_timeout; 299 u32 fextnvm12; 300 s32 ret_val; 301 302 if (hw->mac.type < e1000_pch_mtp) 303 return 0; 304 305 /* Change Kumeran K1 power down state from P0s to P1 */ 306 fextnvm12 = er32(FEXTNVM12); 307 fextnvm12 &= ~E1000_FEXTNVM12_PHYPD_CTRL_MASK; 308 fextnvm12 |= E1000_FEXTNVM12_PHYPD_CTRL_P1; 309 ew32(FEXTNVM12, fextnvm12); 310 311 /* Wait for the interface the settle */ 312 usleep_range(1000, 1100); 313 314 /* Change K1 exit timeout */ 315 ret_val = e1e_rphy_locked(hw, I217_PHY_TIMEOUTS_REG, 316 &phy_timeout); 317 if (ret_val) 318 return ret_val; 319 320 phy_timeout &= ~I217_PHY_TIMEOUTS_K1_EXIT_TO_MASK; 321 phy_timeout |= 0xF00; 322 323 return e1e_wphy_locked(hw, I217_PHY_TIMEOUTS_REG, 324 phy_timeout); 325 } 326 327 /** 328 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 329 * @hw: pointer to the HW structure 330 * 331 * Workarounds/flow necessary for PHY initialization during driver load 332 * and resume paths. 333 **/ 334 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 335 { 336 struct e1000_adapter *adapter = hw->adapter; 337 u32 mac_reg, fwsm = er32(FWSM); 338 s32 ret_val; 339 340 /* Gate automatic PHY configuration by hardware on managed and 341 * non-managed 82579 and newer adapters. 342 */ 343 e1000_gate_hw_phy_config_ich8lan(hw, true); 344 345 /* It is not possible to be certain of the current state of ULP 346 * so forcibly disable it. 347 */ 348 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 349 ret_val = e1000_disable_ulp_lpt_lp(hw, true); 350 if (ret_val) 351 e_warn("Failed to disable ULP\n"); 352 353 ret_val = hw->phy.ops.acquire(hw); 354 if (ret_val) { 355 e_dbg("Failed to initialize PHY flow\n"); 356 goto out; 357 } 358 359 /* There is no guarantee that the PHY is accessible at this time 360 * so disable retry mechanism to avoid wasting time 361 */ 362 e1000e_disable_phy_retry(hw); 363 364 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 365 * inaccessible and resetting the PHY is not blocked, toggle the 366 * LANPHYPC Value bit to force the interconnect to PCIe mode. 367 */ 368 switch (hw->mac.type) { 369 case e1000_pch_mtp: 370 case e1000_pch_lnp: 371 case e1000_pch_ptp: 372 case e1000_pch_nvp: 373 /* At this point the PHY might be inaccessible so don't 374 * propagate the failure 375 */ 376 if (e1000_reconfigure_k1_exit_timeout(hw)) 377 e_dbg("Failed to reconfigure K1 exit timeout\n"); 378 379 fallthrough; 380 case e1000_pch_lpt: 381 case e1000_pch_spt: 382 case e1000_pch_cnp: 383 case e1000_pch_tgp: 384 case e1000_pch_adp: 385 if (e1000_phy_is_accessible_pchlan(hw)) 386 break; 387 388 /* Before toggling LANPHYPC, see if PHY is accessible by 389 * forcing MAC to SMBus mode first. 390 */ 391 mac_reg = er32(CTRL_EXT); 392 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 393 ew32(CTRL_EXT, mac_reg); 394 395 /* Wait 50 milliseconds for MAC to finish any retries 396 * that it might be trying to perform from previous 397 * attempts to acknowledge any phy read requests. 398 */ 399 msleep(50); 400 401 fallthrough; 402 case e1000_pch2lan: 403 if (e1000_phy_is_accessible_pchlan(hw)) 404 break; 405 406 fallthrough; 407 case e1000_pchlan: 408 if ((hw->mac.type == e1000_pchlan) && 409 (fwsm & E1000_ICH_FWSM_FW_VALID)) 410 break; 411 412 if (hw->phy.ops.check_reset_block(hw)) { 413 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 414 ret_val = -E1000_ERR_PHY; 415 break; 416 } 417 418 /* Toggle LANPHYPC Value bit */ 419 e1000_toggle_lanphypc_pch_lpt(hw); 420 if (hw->mac.type >= e1000_pch_lpt) { 421 if (e1000_phy_is_accessible_pchlan(hw)) 422 break; 423 424 /* Toggling LANPHYPC brings the PHY out of SMBus mode 425 * so ensure that the MAC is also out of SMBus mode 426 */ 427 mac_reg = er32(CTRL_EXT); 428 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 429 ew32(CTRL_EXT, mac_reg); 430 431 if (e1000_phy_is_accessible_pchlan(hw)) 432 break; 433 434 ret_val = -E1000_ERR_PHY; 435 } 436 break; 437 default: 438 break; 439 } 440 441 e1000e_enable_phy_retry(hw); 442 443 hw->phy.ops.release(hw); 444 if (!ret_val) { 445 446 /* Check to see if able to reset PHY. Print error if not */ 447 if (hw->phy.ops.check_reset_block(hw)) { 448 e_err("Reset blocked by ME\n"); 449 goto out; 450 } 451 452 /* Reset the PHY before any access to it. Doing so, ensures 453 * that the PHY is in a known good state before we read/write 454 * PHY registers. The generic reset is sufficient here, 455 * because we haven't determined the PHY type yet. 456 */ 457 ret_val = e1000e_phy_hw_reset_generic(hw); 458 if (ret_val) 459 goto out; 460 461 /* On a successful reset, possibly need to wait for the PHY 462 * to quiesce to an accessible state before returning control 463 * to the calling function. If the PHY does not quiesce, then 464 * return E1000E_BLK_PHY_RESET, as this is the condition that 465 * the PHY is in. 466 */ 467 ret_val = hw->phy.ops.check_reset_block(hw); 468 if (ret_val) { 469 e_err("ME blocked access to PHY after reset\n"); 470 goto out; 471 } 472 473 if (hw->mac.type >= e1000_pch_mtp) { 474 ret_val = hw->phy.ops.acquire(hw); 475 if (ret_val) { 476 e_err("Failed to reconfigure K1 exit timeout\n"); 477 goto out; 478 } 479 ret_val = e1000_reconfigure_k1_exit_timeout(hw); 480 hw->phy.ops.release(hw); 481 } 482 } 483 484 out: 485 /* Ungate automatic PHY configuration on non-managed 82579 */ 486 if ((hw->mac.type == e1000_pch2lan) && 487 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 488 usleep_range(10000, 11000); 489 e1000_gate_hw_phy_config_ich8lan(hw, false); 490 } 491 492 return ret_val; 493 } 494 495 /** 496 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 497 * @hw: pointer to the HW structure 498 * 499 * Initialize family-specific PHY parameters and function pointers. 500 **/ 501 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 502 { 503 struct e1000_phy_info *phy = &hw->phy; 504 s32 ret_val; 505 506 phy->addr = 1; 507 phy->reset_delay_us = 100; 508 509 phy->ops.set_page = e1000_set_page_igp; 510 phy->ops.read_reg = e1000_read_phy_reg_hv; 511 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 512 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 513 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 514 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 515 phy->ops.write_reg = e1000_write_phy_reg_hv; 516 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 517 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 518 phy->ops.power_up = e1000_power_up_phy_copper; 519 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 520 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 521 522 phy->id = e1000_phy_unknown; 523 524 if (hw->mac.type == e1000_pch_mtp) { 525 phy->retry_count = 2; 526 e1000e_enable_phy_retry(hw); 527 } 528 529 ret_val = e1000_init_phy_workarounds_pchlan(hw); 530 if (ret_val) 531 return ret_val; 532 533 if (phy->id == e1000_phy_unknown) 534 switch (hw->mac.type) { 535 default: 536 ret_val = e1000e_get_phy_id(hw); 537 if (ret_val) 538 return ret_val; 539 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 540 break; 541 fallthrough; 542 case e1000_pch2lan: 543 case e1000_pch_lpt: 544 case e1000_pch_spt: 545 case e1000_pch_cnp: 546 case e1000_pch_tgp: 547 case e1000_pch_adp: 548 case e1000_pch_mtp: 549 case e1000_pch_lnp: 550 case e1000_pch_ptp: 551 case e1000_pch_nvp: 552 /* In case the PHY needs to be in mdio slow mode, 553 * set slow mode and try to get the PHY id again. 554 */ 555 ret_val = e1000_set_mdio_slow_mode_hv(hw); 556 if (ret_val) 557 return ret_val; 558 ret_val = e1000e_get_phy_id(hw); 559 if (ret_val) 560 return ret_val; 561 break; 562 } 563 phy->type = e1000e_get_phy_type_from_id(phy->id); 564 565 switch (phy->type) { 566 case e1000_phy_82577: 567 case e1000_phy_82579: 568 case e1000_phy_i217: 569 phy->ops.check_polarity = e1000_check_polarity_82577; 570 phy->ops.force_speed_duplex = 571 e1000_phy_force_speed_duplex_82577; 572 phy->ops.get_cable_length = e1000_get_cable_length_82577; 573 phy->ops.get_info = e1000_get_phy_info_82577; 574 phy->ops.commit = e1000e_phy_sw_reset; 575 break; 576 case e1000_phy_82578: 577 phy->ops.check_polarity = e1000_check_polarity_m88; 578 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 579 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 580 phy->ops.get_info = e1000e_get_phy_info_m88; 581 break; 582 default: 583 ret_val = -E1000_ERR_PHY; 584 break; 585 } 586 587 return ret_val; 588 } 589 590 /** 591 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 592 * @hw: pointer to the HW structure 593 * 594 * Initialize family-specific PHY parameters and function pointers. 595 **/ 596 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 597 { 598 struct e1000_phy_info *phy = &hw->phy; 599 s32 ret_val; 600 u16 i = 0; 601 602 phy->addr = 1; 603 phy->reset_delay_us = 100; 604 605 phy->ops.power_up = e1000_power_up_phy_copper; 606 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 607 608 /* We may need to do this twice - once for IGP and if that fails, 609 * we'll set BM func pointers and try again 610 */ 611 ret_val = e1000e_determine_phy_address(hw); 612 if (ret_val) { 613 phy->ops.write_reg = e1000e_write_phy_reg_bm; 614 phy->ops.read_reg = e1000e_read_phy_reg_bm; 615 ret_val = e1000e_determine_phy_address(hw); 616 if (ret_val) { 617 e_dbg("Cannot determine PHY addr. Erroring out\n"); 618 return ret_val; 619 } 620 } 621 622 phy->id = 0; 623 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 624 (i++ < 100)) { 625 usleep_range(1000, 1100); 626 ret_val = e1000e_get_phy_id(hw); 627 if (ret_val) 628 return ret_val; 629 } 630 631 /* Verify phy id */ 632 switch (phy->id) { 633 case IGP03E1000_E_PHY_ID: 634 phy->type = e1000_phy_igp_3; 635 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 636 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 637 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 638 phy->ops.get_info = e1000e_get_phy_info_igp; 639 phy->ops.check_polarity = e1000_check_polarity_igp; 640 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 641 break; 642 case IFE_E_PHY_ID: 643 case IFE_PLUS_E_PHY_ID: 644 case IFE_C_E_PHY_ID: 645 phy->type = e1000_phy_ife; 646 phy->autoneg_mask = E1000_ALL_NOT_GIG; 647 phy->ops.get_info = e1000_get_phy_info_ife; 648 phy->ops.check_polarity = e1000_check_polarity_ife; 649 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 650 break; 651 case BME1000_E_PHY_ID: 652 phy->type = e1000_phy_bm; 653 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 654 phy->ops.read_reg = e1000e_read_phy_reg_bm; 655 phy->ops.write_reg = e1000e_write_phy_reg_bm; 656 phy->ops.commit = e1000e_phy_sw_reset; 657 phy->ops.get_info = e1000e_get_phy_info_m88; 658 phy->ops.check_polarity = e1000_check_polarity_m88; 659 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 660 break; 661 default: 662 return -E1000_ERR_PHY; 663 } 664 665 return 0; 666 } 667 668 /** 669 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 670 * @hw: pointer to the HW structure 671 * 672 * Initialize family-specific NVM parameters and function 673 * pointers. 674 **/ 675 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 676 { 677 struct e1000_nvm_info *nvm = &hw->nvm; 678 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 679 u32 gfpreg, sector_base_addr, sector_end_addr; 680 u16 i; 681 u32 nvm_size; 682 683 nvm->type = e1000_nvm_flash_sw; 684 685 if (hw->mac.type >= e1000_pch_spt) { 686 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 687 * STRAP register. This is because in SPT the GbE Flash region 688 * is no longer accessed through the flash registers. Instead, 689 * the mechanism has changed, and the Flash region access 690 * registers are now implemented in GbE memory space. 691 */ 692 nvm->flash_base_addr = 0; 693 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 694 * NVM_SIZE_MULTIPLIER; 695 nvm->flash_bank_size = nvm_size / 2; 696 /* Adjust to word count */ 697 nvm->flash_bank_size /= sizeof(u16); 698 /* Set the base address for flash register access */ 699 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 700 } else { 701 /* Can't read flash registers if register set isn't mapped. */ 702 if (!hw->flash_address) { 703 e_dbg("ERROR: Flash registers not mapped\n"); 704 return -E1000_ERR_CONFIG; 705 } 706 707 gfpreg = er32flash(ICH_FLASH_GFPREG); 708 709 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 710 * Add 1 to sector_end_addr since this sector is included in 711 * the overall size. 712 */ 713 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 714 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 715 716 /* flash_base_addr is byte-aligned */ 717 nvm->flash_base_addr = sector_base_addr 718 << FLASH_SECTOR_ADDR_SHIFT; 719 720 /* find total size of the NVM, then cut in half since the total 721 * size represents two separate NVM banks. 722 */ 723 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 724 << FLASH_SECTOR_ADDR_SHIFT); 725 nvm->flash_bank_size /= 2; 726 /* Adjust to word count */ 727 nvm->flash_bank_size /= sizeof(u16); 728 } 729 730 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 731 732 /* Clear shadow ram */ 733 for (i = 0; i < nvm->word_size; i++) { 734 dev_spec->shadow_ram[i].modified = false; 735 dev_spec->shadow_ram[i].value = 0xFFFF; 736 } 737 738 return 0; 739 } 740 741 /** 742 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 743 * @hw: pointer to the HW structure 744 * 745 * Initialize family-specific MAC parameters and function 746 * pointers. 747 **/ 748 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 749 { 750 struct e1000_mac_info *mac = &hw->mac; 751 752 /* Set media type function pointer */ 753 hw->phy.media_type = e1000_media_type_copper; 754 755 /* Set mta register count */ 756 mac->mta_reg_count = 32; 757 /* Set rar entry count */ 758 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 759 if (mac->type == e1000_ich8lan) 760 mac->rar_entry_count--; 761 /* FWSM register */ 762 mac->has_fwsm = true; 763 /* ARC subsystem not supported */ 764 mac->arc_subsystem_valid = false; 765 /* Adaptive IFS supported */ 766 mac->adaptive_ifs = true; 767 768 /* LED and other operations */ 769 switch (mac->type) { 770 case e1000_ich8lan: 771 case e1000_ich9lan: 772 case e1000_ich10lan: 773 /* check management mode */ 774 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 775 /* ID LED init */ 776 mac->ops.id_led_init = e1000e_id_led_init_generic; 777 /* blink LED */ 778 mac->ops.blink_led = e1000e_blink_led_generic; 779 /* setup LED */ 780 mac->ops.setup_led = e1000e_setup_led_generic; 781 /* cleanup LED */ 782 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 783 /* turn on/off LED */ 784 mac->ops.led_on = e1000_led_on_ich8lan; 785 mac->ops.led_off = e1000_led_off_ich8lan; 786 break; 787 case e1000_pch2lan: 788 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 789 mac->ops.rar_set = e1000_rar_set_pch2lan; 790 fallthrough; 791 case e1000_pch_lpt: 792 case e1000_pch_spt: 793 case e1000_pch_cnp: 794 case e1000_pch_tgp: 795 case e1000_pch_adp: 796 case e1000_pch_mtp: 797 case e1000_pch_lnp: 798 case e1000_pch_ptp: 799 case e1000_pch_nvp: 800 case e1000_pchlan: 801 /* check management mode */ 802 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 803 /* ID LED init */ 804 mac->ops.id_led_init = e1000_id_led_init_pchlan; 805 /* setup LED */ 806 mac->ops.setup_led = e1000_setup_led_pchlan; 807 /* cleanup LED */ 808 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 809 /* turn on/off LED */ 810 mac->ops.led_on = e1000_led_on_pchlan; 811 mac->ops.led_off = e1000_led_off_pchlan; 812 break; 813 default: 814 break; 815 } 816 817 if (mac->type >= e1000_pch_lpt) { 818 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 819 mac->ops.rar_set = e1000_rar_set_pch_lpt; 820 mac->ops.setup_physical_interface = 821 e1000_setup_copper_link_pch_lpt; 822 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 823 } 824 825 /* Enable PCS Lock-loss workaround for ICH8 */ 826 if (mac->type == e1000_ich8lan) 827 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 828 829 return 0; 830 } 831 832 /** 833 * __e1000_access_emi_reg_locked - Read/write EMI register 834 * @hw: pointer to the HW structure 835 * @address: EMI address to program 836 * @data: pointer to value to read/write from/to the EMI address 837 * @read: boolean flag to indicate read or write 838 * 839 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 840 **/ 841 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 842 u16 *data, bool read) 843 { 844 s32 ret_val; 845 846 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 847 if (ret_val) 848 return ret_val; 849 850 if (read) 851 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 852 else 853 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 854 855 return ret_val; 856 } 857 858 /** 859 * e1000_read_emi_reg_locked - Read Extended Management Interface register 860 * @hw: pointer to the HW structure 861 * @addr: EMI address to program 862 * @data: value to be read from the EMI address 863 * 864 * Assumes the SW/FW/HW Semaphore is already acquired. 865 **/ 866 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 867 { 868 return __e1000_access_emi_reg_locked(hw, addr, data, true); 869 } 870 871 /** 872 * e1000_write_emi_reg_locked - Write Extended Management Interface register 873 * @hw: pointer to the HW structure 874 * @addr: EMI address to program 875 * @data: value to be written to the EMI address 876 * 877 * Assumes the SW/FW/HW Semaphore is already acquired. 878 **/ 879 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 880 { 881 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 882 } 883 884 /** 885 * e1000_set_eee_pchlan - Enable/disable EEE support 886 * @hw: pointer to the HW structure 887 * 888 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 889 * the link and the EEE capabilities of the link partner. The LPI Control 890 * register bits will remain set only if/when link is up. 891 * 892 * EEE LPI must not be asserted earlier than one second after link is up. 893 * On 82579, EEE LPI should not be enabled until such time otherwise there 894 * can be link issues with some switches. Other devices can have EEE LPI 895 * enabled immediately upon link up since they have a timer in hardware which 896 * prevents LPI from being asserted too early. 897 **/ 898 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 899 { 900 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 901 s32 ret_val; 902 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 903 904 switch (hw->phy.type) { 905 case e1000_phy_82579: 906 lpa = I82579_EEE_LP_ABILITY; 907 pcs_status = I82579_EEE_PCS_STATUS; 908 adv_addr = I82579_EEE_ADVERTISEMENT; 909 break; 910 case e1000_phy_i217: 911 lpa = I217_EEE_LP_ABILITY; 912 pcs_status = I217_EEE_PCS_STATUS; 913 adv_addr = I217_EEE_ADVERTISEMENT; 914 break; 915 default: 916 return 0; 917 } 918 919 ret_val = hw->phy.ops.acquire(hw); 920 if (ret_val) 921 return ret_val; 922 923 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 924 if (ret_val) 925 goto release; 926 927 /* Clear bits that enable EEE in various speeds */ 928 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 929 930 /* Enable EEE if not disabled by user */ 931 if (!dev_spec->eee_disable) { 932 /* Save off link partner's EEE ability */ 933 ret_val = e1000_read_emi_reg_locked(hw, lpa, 934 &dev_spec->eee_lp_ability); 935 if (ret_val) 936 goto release; 937 938 /* Read EEE advertisement */ 939 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 940 if (ret_val) 941 goto release; 942 943 /* Enable EEE only for speeds in which the link partner is 944 * EEE capable and for which we advertise EEE. 945 */ 946 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 947 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 948 949 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 950 e1e_rphy_locked(hw, MII_LPA, &data); 951 if (data & LPA_100FULL) 952 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 953 else 954 /* EEE is not supported in 100Half, so ignore 955 * partner's EEE in 100 ability if full-duplex 956 * is not advertised. 957 */ 958 dev_spec->eee_lp_ability &= 959 ~I82579_EEE_100_SUPPORTED; 960 } 961 } 962 963 if (hw->phy.type == e1000_phy_82579) { 964 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 965 &data); 966 if (ret_val) 967 goto release; 968 969 data &= ~I82579_LPI_100_PLL_SHUT; 970 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 971 data); 972 } 973 974 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 975 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 976 if (ret_val) 977 goto release; 978 979 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 980 release: 981 hw->phy.ops.release(hw); 982 983 return ret_val; 984 } 985 986 /** 987 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 988 * @hw: pointer to the HW structure 989 * @link: link up bool flag 990 * 991 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 992 * preventing further DMA write requests. Workaround the issue by disabling 993 * the de-assertion of the clock request when in 1Gpbs mode. 994 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 995 * speeds in order to avoid Tx hangs. 996 **/ 997 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 998 { 999 u32 fextnvm6 = er32(FEXTNVM6); 1000 u32 status = er32(STATUS); 1001 s32 ret_val = 0; 1002 u16 reg; 1003 1004 if (link && (status & E1000_STATUS_SPEED_1000)) { 1005 ret_val = hw->phy.ops.acquire(hw); 1006 if (ret_val) 1007 return ret_val; 1008 1009 ret_val = 1010 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1011 ®); 1012 if (ret_val) 1013 goto release; 1014 1015 ret_val = 1016 e1000e_write_kmrn_reg_locked(hw, 1017 E1000_KMRNCTRLSTA_K1_CONFIG, 1018 reg & 1019 ~E1000_KMRNCTRLSTA_K1_ENABLE); 1020 if (ret_val) 1021 goto release; 1022 1023 usleep_range(10, 20); 1024 1025 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 1026 1027 ret_val = 1028 e1000e_write_kmrn_reg_locked(hw, 1029 E1000_KMRNCTRLSTA_K1_CONFIG, 1030 reg); 1031 release: 1032 hw->phy.ops.release(hw); 1033 } else { 1034 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 1035 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 1036 1037 if ((hw->phy.revision > 5) || !link || 1038 ((status & E1000_STATUS_SPEED_100) && 1039 (status & E1000_STATUS_FD))) 1040 goto update_fextnvm6; 1041 1042 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 1043 if (ret_val) 1044 return ret_val; 1045 1046 /* Clear link status transmit timeout */ 1047 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 1048 1049 if (status & E1000_STATUS_SPEED_100) { 1050 /* Set inband Tx timeout to 5x10us for 100Half */ 1051 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1052 1053 /* Do not extend the K1 entry latency for 100Half */ 1054 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1055 } else { 1056 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 1057 reg |= 50 << 1058 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1059 1060 /* Extend the K1 entry latency for 10 Mbps */ 1061 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1062 } 1063 1064 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 1065 if (ret_val) 1066 return ret_val; 1067 1068 update_fextnvm6: 1069 ew32(FEXTNVM6, fextnvm6); 1070 } 1071 1072 return ret_val; 1073 } 1074 1075 /** 1076 * e1000_platform_pm_pch_lpt - Set platform power management values 1077 * @hw: pointer to the HW structure 1078 * @link: bool indicating link status 1079 * 1080 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1081 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1082 * when link is up (which must not exceed the maximum latency supported 1083 * by the platform), otherwise specify there is no LTR requirement. 1084 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 1085 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1086 * Capability register set, on this device LTR is set by writing the 1087 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1088 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1089 * message to the PMC. 1090 **/ 1091 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1092 { 1093 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1094 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1095 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */ 1096 u32 lat_enc_d = 0; /* latency decoded */ 1097 u16 lat_enc = 0; /* latency encoded */ 1098 1099 if (link) { 1100 u16 speed, duplex, scale = 0; 1101 u16 max_snoop, max_nosnoop; 1102 u16 max_ltr_enc; /* max LTR latency encoded */ 1103 u64 value; 1104 u32 rxa; 1105 1106 if (!hw->adapter->max_frame_size) { 1107 e_dbg("max_frame_size not set.\n"); 1108 return -E1000_ERR_CONFIG; 1109 } 1110 1111 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1112 if (!speed) { 1113 e_dbg("Speed not set.\n"); 1114 return -E1000_ERR_CONFIG; 1115 } 1116 1117 /* Rx Packet Buffer Allocation size (KB) */ 1118 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1119 1120 /* Determine the maximum latency tolerated by the device. 1121 * 1122 * Per the PCIe spec, the tolerated latencies are encoded as 1123 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1124 * a 10-bit value (0-1023) to provide a range from 1 ns to 1125 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1126 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1127 */ 1128 rxa *= 512; 1129 value = (rxa > hw->adapter->max_frame_size) ? 1130 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1131 0; 1132 1133 while (value > PCI_LTR_VALUE_MASK) { 1134 scale++; 1135 value = DIV_ROUND_UP(value, BIT(5)); 1136 } 1137 if (scale > E1000_LTRV_SCALE_MAX) { 1138 e_dbg("Invalid LTR latency scale %d\n", scale); 1139 return -E1000_ERR_CONFIG; 1140 } 1141 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1142 1143 /* Determine the maximum latency tolerated by the platform */ 1144 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1145 &max_snoop); 1146 pci_read_config_word(hw->adapter->pdev, 1147 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1148 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1149 1150 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) * 1151 (1U << (E1000_LTRV_SCALE_FACTOR * 1152 FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc))); 1153 1154 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) * 1155 (1U << (E1000_LTRV_SCALE_FACTOR * 1156 FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc))); 1157 1158 if (lat_enc_d > max_ltr_enc_d) 1159 lat_enc = max_ltr_enc; 1160 } 1161 1162 /* Set Snoop and No-Snoop latencies the same */ 1163 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1164 ew32(LTRV, reg); 1165 1166 return 0; 1167 } 1168 1169 /** 1170 * e1000e_force_smbus - Force interfaces to transition to SMBUS mode. 1171 * @hw: pointer to the HW structure 1172 * 1173 * Force the MAC and the PHY to SMBUS mode. Assumes semaphore already 1174 * acquired. 1175 * 1176 * Return: 0 on success, negative errno on failure. 1177 **/ 1178 static s32 e1000e_force_smbus(struct e1000_hw *hw) 1179 { 1180 u16 smb_ctrl = 0; 1181 u32 ctrl_ext; 1182 s32 ret_val; 1183 1184 /* Switching PHY interface always returns MDI error 1185 * so disable retry mechanism to avoid wasting time 1186 */ 1187 e1000e_disable_phy_retry(hw); 1188 1189 /* Force SMBus mode in the PHY */ 1190 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &smb_ctrl); 1191 if (ret_val) { 1192 e1000e_enable_phy_retry(hw); 1193 return ret_val; 1194 } 1195 1196 smb_ctrl |= CV_SMB_CTRL_FORCE_SMBUS; 1197 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, smb_ctrl); 1198 1199 e1000e_enable_phy_retry(hw); 1200 1201 /* Force SMBus mode in the MAC */ 1202 ctrl_ext = er32(CTRL_EXT); 1203 ctrl_ext |= E1000_CTRL_EXT_FORCE_SMBUS; 1204 ew32(CTRL_EXT, ctrl_ext); 1205 1206 return 0; 1207 } 1208 1209 /** 1210 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1211 * @hw: pointer to the HW structure 1212 * @to_sx: boolean indicating a system power state transition to Sx 1213 * 1214 * When link is down, configure ULP mode to significantly reduce the power 1215 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1216 * ME firmware to start the ULP configuration. If not on an ME enabled 1217 * system, configure the ULP mode by software. 1218 */ 1219 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1220 { 1221 u32 mac_reg; 1222 s32 ret_val = 0; 1223 u16 phy_reg; 1224 u16 oem_reg = 0; 1225 1226 if ((hw->mac.type < e1000_pch_lpt) || 1227 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1228 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1229 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1230 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1231 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1232 return 0; 1233 1234 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1235 /* Request ME configure ULP mode in the PHY */ 1236 mac_reg = er32(H2ME); 1237 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1238 ew32(H2ME, mac_reg); 1239 1240 goto out; 1241 } 1242 1243 if (!to_sx) { 1244 int i = 0; 1245 1246 /* Poll up to 5 seconds for Cable Disconnected indication */ 1247 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1248 /* Bail if link is re-acquired */ 1249 if (er32(STATUS) & E1000_STATUS_LU) 1250 return -E1000_ERR_PHY; 1251 1252 if (i++ == 100) 1253 break; 1254 1255 msleep(50); 1256 } 1257 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1258 (er32(FEXT) & 1259 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1260 } 1261 1262 ret_val = hw->phy.ops.acquire(hw); 1263 if (ret_val) 1264 goto out; 1265 1266 ret_val = e1000e_force_smbus(hw); 1267 if (ret_val) { 1268 e_dbg("Failed to force SMBUS: %d\n", ret_val); 1269 goto release; 1270 } 1271 1272 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1273 * LPLU and disable Gig speed when entering ULP 1274 */ 1275 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1276 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1277 &oem_reg); 1278 if (ret_val) 1279 goto release; 1280 1281 phy_reg = oem_reg; 1282 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1283 1284 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1285 phy_reg); 1286 1287 if (ret_val) 1288 goto release; 1289 } 1290 1291 /* Set Inband ULP Exit, Reset to SMBus mode and 1292 * Disable SMBus Release on PERST# in PHY 1293 */ 1294 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1295 if (ret_val) 1296 goto release; 1297 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1298 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1299 if (to_sx) { 1300 if (er32(WUFC) & E1000_WUFC_LNKC) 1301 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1302 else 1303 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1304 1305 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1306 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1307 } else { 1308 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1309 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1310 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1311 } 1312 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1313 1314 /* Set Disable SMBus Release on PERST# in MAC */ 1315 mac_reg = er32(FEXTNVM7); 1316 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1317 ew32(FEXTNVM7, mac_reg); 1318 1319 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1320 phy_reg |= I218_ULP_CONFIG1_START; 1321 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1322 1323 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1324 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1325 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1326 oem_reg); 1327 if (ret_val) 1328 goto release; 1329 } 1330 1331 release: 1332 hw->phy.ops.release(hw); 1333 out: 1334 if (ret_val) 1335 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1336 else 1337 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1338 1339 return ret_val; 1340 } 1341 1342 /** 1343 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1344 * @hw: pointer to the HW structure 1345 * @force: boolean indicating whether or not to force disabling ULP 1346 * 1347 * Un-configure ULP mode when link is up, the system is transitioned from 1348 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1349 * system, poll for an indication from ME that ULP has been un-configured. 1350 * If not on an ME enabled system, un-configure the ULP mode by software. 1351 * 1352 * During nominal operation, this function is called when link is acquired 1353 * to disable ULP mode (force=false); otherwise, for example when unloading 1354 * the driver or during Sx->S0 transitions, this is called with force=true 1355 * to forcibly disable ULP. 1356 */ 1357 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1358 { 1359 s32 ret_val = 0; 1360 u32 mac_reg; 1361 u16 phy_reg; 1362 int i = 0; 1363 1364 if ((hw->mac.type < e1000_pch_lpt) || 1365 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1366 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1367 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1368 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1369 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1370 return 0; 1371 1372 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1373 struct e1000_adapter *adapter = hw->adapter; 1374 bool firmware_bug = false; 1375 1376 if (force) { 1377 /* Request ME un-configure ULP mode in the PHY */ 1378 mac_reg = er32(H2ME); 1379 mac_reg &= ~E1000_H2ME_ULP; 1380 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1381 ew32(H2ME, mac_reg); 1382 } 1383 1384 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE. 1385 * If this takes more than 1 second, show a warning indicating a 1386 * firmware bug 1387 */ 1388 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1389 if (i++ == 250) { 1390 ret_val = -E1000_ERR_PHY; 1391 goto out; 1392 } 1393 if (i > 100 && !firmware_bug) 1394 firmware_bug = true; 1395 1396 usleep_range(10000, 11000); 1397 } 1398 if (firmware_bug) 1399 e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n", 1400 i * 10); 1401 else 1402 e_dbg("ULP_CONFIG_DONE cleared after %d msec\n", 1403 i * 10); 1404 1405 if (force) { 1406 mac_reg = er32(H2ME); 1407 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1408 ew32(H2ME, mac_reg); 1409 } else { 1410 /* Clear H2ME.ULP after ME ULP configuration */ 1411 mac_reg = er32(H2ME); 1412 mac_reg &= ~E1000_H2ME_ULP; 1413 ew32(H2ME, mac_reg); 1414 } 1415 1416 goto out; 1417 } 1418 1419 ret_val = hw->phy.ops.acquire(hw); 1420 if (ret_val) 1421 goto out; 1422 1423 if (force) 1424 /* Toggle LANPHYPC Value bit */ 1425 e1000_toggle_lanphypc_pch_lpt(hw); 1426 1427 /* Switching PHY interface always returns MDI error 1428 * so disable retry mechanism to avoid wasting time 1429 */ 1430 e1000e_disable_phy_retry(hw); 1431 1432 /* Unforce SMBus mode in PHY */ 1433 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1434 if (ret_val) { 1435 /* The MAC might be in PCIe mode, so temporarily force to 1436 * SMBus mode in order to access the PHY. 1437 */ 1438 mac_reg = er32(CTRL_EXT); 1439 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1440 ew32(CTRL_EXT, mac_reg); 1441 1442 msleep(50); 1443 1444 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1445 &phy_reg); 1446 if (ret_val) 1447 goto release; 1448 } 1449 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1450 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1451 1452 e1000e_enable_phy_retry(hw); 1453 1454 /* Unforce SMBus mode in MAC */ 1455 mac_reg = er32(CTRL_EXT); 1456 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1457 ew32(CTRL_EXT, mac_reg); 1458 1459 /* When ULP mode was previously entered, K1 was disabled by the 1460 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1461 */ 1462 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1463 if (ret_val) 1464 goto release; 1465 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1466 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1467 1468 /* Clear ULP enabled configuration */ 1469 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1470 if (ret_val) 1471 goto release; 1472 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1473 I218_ULP_CONFIG1_STICKY_ULP | 1474 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1475 I218_ULP_CONFIG1_WOL_HOST | 1476 I218_ULP_CONFIG1_INBAND_EXIT | 1477 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1478 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1479 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1480 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1481 1482 /* Commit ULP changes by starting auto ULP configuration */ 1483 phy_reg |= I218_ULP_CONFIG1_START; 1484 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1485 1486 /* Clear Disable SMBus Release on PERST# in MAC */ 1487 mac_reg = er32(FEXTNVM7); 1488 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1489 ew32(FEXTNVM7, mac_reg); 1490 1491 release: 1492 hw->phy.ops.release(hw); 1493 if (force) { 1494 e1000_phy_hw_reset(hw); 1495 msleep(50); 1496 } 1497 out: 1498 if (ret_val) 1499 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1500 else 1501 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1502 1503 return ret_val; 1504 } 1505 1506 /** 1507 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1508 * @hw: pointer to the HW structure 1509 * 1510 * Checks to see of the link status of the hardware has changed. If a 1511 * change in link status has been detected, then we read the PHY registers 1512 * to get the current speed/duplex if link exists. 1513 **/ 1514 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1515 { 1516 struct e1000_mac_info *mac = &hw->mac; 1517 s32 ret_val, tipg_reg = 0; 1518 u16 emi_addr, emi_val = 0; 1519 bool link; 1520 u16 phy_reg; 1521 1522 /* We only want to go out to the PHY registers to see if Auto-Neg 1523 * has completed and/or if our link status has changed. The 1524 * get_link_status flag is set upon receiving a Link Status 1525 * Change or Rx Sequence Error interrupt. 1526 */ 1527 if (!mac->get_link_status) 1528 return 0; 1529 mac->get_link_status = false; 1530 1531 /* First we want to see if the MII Status Register reports 1532 * link. If so, then we want to get the current speed/duplex 1533 * of the PHY. 1534 */ 1535 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1536 if (ret_val) 1537 goto out; 1538 1539 if (hw->mac.type == e1000_pchlan) { 1540 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1541 if (ret_val) 1542 goto out; 1543 } 1544 1545 /* When connected at 10Mbps half-duplex, some parts are excessively 1546 * aggressive resulting in many collisions. To avoid this, increase 1547 * the IPG and reduce Rx latency in the PHY. 1548 */ 1549 if ((hw->mac.type >= e1000_pch2lan) && link) { 1550 u16 speed, duplex; 1551 1552 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1553 tipg_reg = er32(TIPG); 1554 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1555 1556 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1557 tipg_reg |= 0xFF; 1558 /* Reduce Rx latency in analog PHY */ 1559 emi_val = 0; 1560 } else if (hw->mac.type >= e1000_pch_spt && 1561 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1562 tipg_reg |= 0xC; 1563 emi_val = 1; 1564 } else { 1565 1566 /* Roll back the default values */ 1567 tipg_reg |= 0x08; 1568 emi_val = 1; 1569 } 1570 1571 ew32(TIPG, tipg_reg); 1572 1573 ret_val = hw->phy.ops.acquire(hw); 1574 if (ret_val) 1575 goto out; 1576 1577 if (hw->mac.type == e1000_pch2lan) 1578 emi_addr = I82579_RX_CONFIG; 1579 else 1580 emi_addr = I217_RX_CONFIG; 1581 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1582 1583 if (hw->mac.type >= e1000_pch_lpt) { 1584 u16 phy_reg; 1585 1586 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1587 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1588 if (speed == SPEED_100 || speed == SPEED_10) 1589 phy_reg |= 0x3E8; 1590 else 1591 phy_reg |= 0xFA; 1592 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1593 1594 if (speed == SPEED_1000) { 1595 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1596 &phy_reg); 1597 1598 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1599 1600 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1601 phy_reg); 1602 } 1603 } 1604 hw->phy.ops.release(hw); 1605 1606 if (ret_val) 1607 goto out; 1608 1609 if (hw->mac.type >= e1000_pch_spt) { 1610 u16 data; 1611 u16 ptr_gap; 1612 1613 if (speed == SPEED_1000) { 1614 ret_val = hw->phy.ops.acquire(hw); 1615 if (ret_val) 1616 goto out; 1617 1618 ret_val = e1e_rphy_locked(hw, 1619 PHY_REG(776, 20), 1620 &data); 1621 if (ret_val) { 1622 hw->phy.ops.release(hw); 1623 goto out; 1624 } 1625 1626 ptr_gap = (data & (0x3FF << 2)) >> 2; 1627 if (ptr_gap < 0x18) { 1628 data &= ~(0x3FF << 2); 1629 data |= (0x18 << 2); 1630 ret_val = 1631 e1e_wphy_locked(hw, 1632 PHY_REG(776, 20), 1633 data); 1634 } 1635 hw->phy.ops.release(hw); 1636 if (ret_val) 1637 goto out; 1638 } else { 1639 ret_val = hw->phy.ops.acquire(hw); 1640 if (ret_val) 1641 goto out; 1642 1643 ret_val = e1e_wphy_locked(hw, 1644 PHY_REG(776, 20), 1645 0xC023); 1646 hw->phy.ops.release(hw); 1647 if (ret_val) 1648 goto out; 1649 1650 } 1651 } 1652 } 1653 1654 /* I217 Packet Loss issue: 1655 * ensure that FEXTNVM4 Beacon Duration is set correctly 1656 * on power up. 1657 * Set the Beacon Duration for I217 to 8 usec 1658 */ 1659 if (hw->mac.type >= e1000_pch_lpt) { 1660 u32 mac_reg; 1661 1662 mac_reg = er32(FEXTNVM4); 1663 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1664 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1665 ew32(FEXTNVM4, mac_reg); 1666 } 1667 1668 /* Work-around I218 hang issue */ 1669 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1670 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1671 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1672 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1673 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1674 if (ret_val) 1675 goto out; 1676 } 1677 if (hw->mac.type >= e1000_pch_lpt) { 1678 /* Set platform power management values for 1679 * Latency Tolerance Reporting (LTR) 1680 */ 1681 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1682 if (ret_val) 1683 goto out; 1684 } 1685 1686 /* Clear link partner's EEE ability */ 1687 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1688 1689 if (hw->mac.type >= e1000_pch_lpt) { 1690 u32 fextnvm6 = er32(FEXTNVM6); 1691 1692 if (hw->mac.type == e1000_pch_spt) { 1693 /* FEXTNVM6 K1-off workaround - for SPT only */ 1694 u32 pcieanacfg = er32(PCIEANACFG); 1695 1696 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1697 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1698 else 1699 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1700 } 1701 1702 ew32(FEXTNVM6, fextnvm6); 1703 } 1704 1705 if (!link) 1706 goto out; 1707 1708 switch (hw->mac.type) { 1709 case e1000_pch2lan: 1710 ret_val = e1000_k1_workaround_lv(hw); 1711 if (ret_val) 1712 return ret_val; 1713 fallthrough; 1714 case e1000_pchlan: 1715 if (hw->phy.type == e1000_phy_82578) { 1716 ret_val = e1000_link_stall_workaround_hv(hw); 1717 if (ret_val) 1718 return ret_val; 1719 } 1720 1721 /* Workaround for PCHx parts in half-duplex: 1722 * Set the number of preambles removed from the packet 1723 * when it is passed from the PHY to the MAC to prevent 1724 * the MAC from misinterpreting the packet type. 1725 */ 1726 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1727 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1728 1729 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1730 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1731 1732 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1733 break; 1734 default: 1735 break; 1736 } 1737 1738 /* Check if there was DownShift, must be checked 1739 * immediately after link-up 1740 */ 1741 e1000e_check_downshift(hw); 1742 1743 /* Enable/Disable EEE after link up */ 1744 if (hw->phy.type > e1000_phy_82579) { 1745 ret_val = e1000_set_eee_pchlan(hw); 1746 if (ret_val) 1747 return ret_val; 1748 } 1749 1750 /* If we are forcing speed/duplex, then we simply return since 1751 * we have already determined whether we have link or not. 1752 */ 1753 if (!mac->autoneg) 1754 return -E1000_ERR_CONFIG; 1755 1756 /* Auto-Neg is enabled. Auto Speed Detection takes care 1757 * of MAC speed/duplex configuration. So we only need to 1758 * configure Collision Distance in the MAC. 1759 */ 1760 mac->ops.config_collision_dist(hw); 1761 1762 /* Configure Flow Control now that Auto-Neg has completed. 1763 * First, we need to restore the desired flow control 1764 * settings because we may have had to re-autoneg with a 1765 * different link partner. 1766 */ 1767 ret_val = e1000e_config_fc_after_link_up(hw); 1768 if (ret_val) 1769 e_dbg("Error configuring flow control\n"); 1770 1771 return ret_val; 1772 1773 out: 1774 mac->get_link_status = true; 1775 return ret_val; 1776 } 1777 1778 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1779 { 1780 struct e1000_hw *hw = &adapter->hw; 1781 s32 rc; 1782 1783 rc = e1000_init_mac_params_ich8lan(hw); 1784 if (rc) 1785 return rc; 1786 1787 rc = e1000_init_nvm_params_ich8lan(hw); 1788 if (rc) 1789 return rc; 1790 1791 switch (hw->mac.type) { 1792 case e1000_ich8lan: 1793 case e1000_ich9lan: 1794 case e1000_ich10lan: 1795 rc = e1000_init_phy_params_ich8lan(hw); 1796 break; 1797 case e1000_pchlan: 1798 case e1000_pch2lan: 1799 case e1000_pch_lpt: 1800 case e1000_pch_spt: 1801 case e1000_pch_cnp: 1802 case e1000_pch_tgp: 1803 case e1000_pch_adp: 1804 case e1000_pch_mtp: 1805 case e1000_pch_lnp: 1806 case e1000_pch_ptp: 1807 case e1000_pch_nvp: 1808 rc = e1000_init_phy_params_pchlan(hw); 1809 break; 1810 default: 1811 break; 1812 } 1813 if (rc) 1814 return rc; 1815 1816 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1817 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1818 */ 1819 if ((adapter->hw.phy.type == e1000_phy_ife) || 1820 ((adapter->hw.mac.type >= e1000_pch2lan) && 1821 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1822 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1823 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1824 1825 hw->mac.ops.blink_led = NULL; 1826 } 1827 1828 if ((adapter->hw.mac.type == e1000_ich8lan) && 1829 (adapter->hw.phy.type != e1000_phy_ife)) 1830 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1831 1832 /* Enable workaround for 82579 w/ ME enabled */ 1833 if ((adapter->hw.mac.type == e1000_pch2lan) && 1834 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1835 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1836 1837 return 0; 1838 } 1839 1840 static DEFINE_MUTEX(nvm_mutex); 1841 1842 /** 1843 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1844 * @hw: pointer to the HW structure 1845 * 1846 * Acquires the mutex for performing NVM operations. 1847 **/ 1848 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1849 { 1850 mutex_lock(&nvm_mutex); 1851 1852 return 0; 1853 } 1854 1855 /** 1856 * e1000_release_nvm_ich8lan - Release NVM mutex 1857 * @hw: pointer to the HW structure 1858 * 1859 * Releases the mutex used while performing NVM operations. 1860 **/ 1861 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1862 { 1863 mutex_unlock(&nvm_mutex); 1864 } 1865 1866 /** 1867 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1868 * @hw: pointer to the HW structure 1869 * 1870 * Acquires the software control flag for performing PHY and select 1871 * MAC CSR accesses. 1872 **/ 1873 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1874 { 1875 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1876 s32 ret_val = 0; 1877 1878 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1879 &hw->adapter->state)) { 1880 e_dbg("contention for Phy access\n"); 1881 return -E1000_ERR_PHY; 1882 } 1883 1884 while (timeout) { 1885 extcnf_ctrl = er32(EXTCNF_CTRL); 1886 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1887 break; 1888 1889 mdelay(1); 1890 timeout--; 1891 } 1892 1893 if (!timeout) { 1894 e_dbg("SW has already locked the resource.\n"); 1895 ret_val = -E1000_ERR_CONFIG; 1896 goto out; 1897 } 1898 1899 timeout = SW_FLAG_TIMEOUT; 1900 1901 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1902 ew32(EXTCNF_CTRL, extcnf_ctrl); 1903 1904 while (timeout) { 1905 extcnf_ctrl = er32(EXTCNF_CTRL); 1906 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1907 break; 1908 1909 mdelay(1); 1910 timeout--; 1911 } 1912 1913 if (!timeout) { 1914 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1915 er32(FWSM), extcnf_ctrl); 1916 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1917 ew32(EXTCNF_CTRL, extcnf_ctrl); 1918 ret_val = -E1000_ERR_CONFIG; 1919 goto out; 1920 } 1921 1922 out: 1923 if (ret_val) 1924 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1925 1926 return ret_val; 1927 } 1928 1929 /** 1930 * e1000_release_swflag_ich8lan - Release software control flag 1931 * @hw: pointer to the HW structure 1932 * 1933 * Releases the software control flag for performing PHY and select 1934 * MAC CSR accesses. 1935 **/ 1936 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1937 { 1938 u32 extcnf_ctrl; 1939 1940 extcnf_ctrl = er32(EXTCNF_CTRL); 1941 1942 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1943 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1944 ew32(EXTCNF_CTRL, extcnf_ctrl); 1945 } else { 1946 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1947 } 1948 1949 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1950 } 1951 1952 /** 1953 * e1000_check_mng_mode_ich8lan - Checks management mode 1954 * @hw: pointer to the HW structure 1955 * 1956 * This checks if the adapter has any manageability enabled. 1957 * This is a function pointer entry point only called by read/write 1958 * routines for the PHY and NVM parts. 1959 **/ 1960 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1961 { 1962 u32 fwsm; 1963 1964 fwsm = er32(FWSM); 1965 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1966 ((fwsm & E1000_FWSM_MODE_MASK) == 1967 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1968 } 1969 1970 /** 1971 * e1000_check_mng_mode_pchlan - Checks management mode 1972 * @hw: pointer to the HW structure 1973 * 1974 * This checks if the adapter has iAMT enabled. 1975 * This is a function pointer entry point only called by read/write 1976 * routines for the PHY and NVM parts. 1977 **/ 1978 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1979 { 1980 u32 fwsm; 1981 1982 fwsm = er32(FWSM); 1983 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1984 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1985 } 1986 1987 /** 1988 * e1000_rar_set_pch2lan - Set receive address register 1989 * @hw: pointer to the HW structure 1990 * @addr: pointer to the receive address 1991 * @index: receive address array register 1992 * 1993 * Sets the receive address array register at index to the address passed 1994 * in by addr. For 82579, RAR[0] is the base address register that is to 1995 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1996 * Use SHRA[0-3] in place of those reserved for ME. 1997 **/ 1998 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1999 { 2000 u32 rar_low, rar_high; 2001 2002 /* HW expects these in little endian so we reverse the byte order 2003 * from network order (big endian) to little endian 2004 */ 2005 rar_low = ((u32)addr[0] | 2006 ((u32)addr[1] << 8) | 2007 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 2008 2009 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 2010 2011 /* If MAC address zero, no need to set the AV bit */ 2012 if (rar_low || rar_high) 2013 rar_high |= E1000_RAH_AV; 2014 2015 if (index == 0) { 2016 ew32(RAL(index), rar_low); 2017 e1e_flush(); 2018 ew32(RAH(index), rar_high); 2019 e1e_flush(); 2020 return 0; 2021 } 2022 2023 /* RAR[1-6] are owned by manageability. Skip those and program the 2024 * next address into the SHRA register array. 2025 */ 2026 if (index < (u32)(hw->mac.rar_entry_count)) { 2027 s32 ret_val; 2028 2029 ret_val = e1000_acquire_swflag_ich8lan(hw); 2030 if (ret_val) 2031 goto out; 2032 2033 ew32(SHRAL(index - 1), rar_low); 2034 e1e_flush(); 2035 ew32(SHRAH(index - 1), rar_high); 2036 e1e_flush(); 2037 2038 e1000_release_swflag_ich8lan(hw); 2039 2040 /* verify the register updates */ 2041 if ((er32(SHRAL(index - 1)) == rar_low) && 2042 (er32(SHRAH(index - 1)) == rar_high)) 2043 return 0; 2044 2045 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 2046 (index - 1), er32(FWSM)); 2047 } 2048 2049 out: 2050 e_dbg("Failed to write receive address at index %d\n", index); 2051 return -E1000_ERR_CONFIG; 2052 } 2053 2054 /** 2055 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 2056 * @hw: pointer to the HW structure 2057 * 2058 * Get the number of available receive registers that the Host can 2059 * program. SHRA[0-10] are the shared receive address registers 2060 * that are shared between the Host and manageability engine (ME). 2061 * ME can reserve any number of addresses and the host needs to be 2062 * able to tell how many available registers it has access to. 2063 **/ 2064 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 2065 { 2066 u32 wlock_mac; 2067 u32 num_entries; 2068 2069 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2070 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2071 2072 switch (wlock_mac) { 2073 case 0: 2074 /* All SHRA[0..10] and RAR[0] available */ 2075 num_entries = hw->mac.rar_entry_count; 2076 break; 2077 case 1: 2078 /* Only RAR[0] available */ 2079 num_entries = 1; 2080 break; 2081 default: 2082 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 2083 num_entries = wlock_mac + 1; 2084 break; 2085 } 2086 2087 return num_entries; 2088 } 2089 2090 /** 2091 * e1000_rar_set_pch_lpt - Set receive address registers 2092 * @hw: pointer to the HW structure 2093 * @addr: pointer to the receive address 2094 * @index: receive address array register 2095 * 2096 * Sets the receive address register array at index to the address passed 2097 * in by addr. For LPT, RAR[0] is the base address register that is to 2098 * contain the MAC address. SHRA[0-10] are the shared receive address 2099 * registers that are shared between the Host and manageability engine (ME). 2100 **/ 2101 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 2102 { 2103 u32 rar_low, rar_high; 2104 u32 wlock_mac; 2105 2106 /* HW expects these in little endian so we reverse the byte order 2107 * from network order (big endian) to little endian 2108 */ 2109 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 2110 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 2111 2112 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 2113 2114 /* If MAC address zero, no need to set the AV bit */ 2115 if (rar_low || rar_high) 2116 rar_high |= E1000_RAH_AV; 2117 2118 if (index == 0) { 2119 ew32(RAL(index), rar_low); 2120 e1e_flush(); 2121 ew32(RAH(index), rar_high); 2122 e1e_flush(); 2123 return 0; 2124 } 2125 2126 /* The manageability engine (ME) can lock certain SHRAR registers that 2127 * it is using - those registers are unavailable for use. 2128 */ 2129 if (index < hw->mac.rar_entry_count) { 2130 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2131 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2132 2133 /* Check if all SHRAR registers are locked */ 2134 if (wlock_mac == 1) 2135 goto out; 2136 2137 if ((wlock_mac == 0) || (index <= wlock_mac)) { 2138 s32 ret_val; 2139 2140 ret_val = e1000_acquire_swflag_ich8lan(hw); 2141 2142 if (ret_val) 2143 goto out; 2144 2145 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 2146 e1e_flush(); 2147 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 2148 e1e_flush(); 2149 2150 e1000_release_swflag_ich8lan(hw); 2151 2152 /* verify the register updates */ 2153 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 2154 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 2155 return 0; 2156 } 2157 } 2158 2159 out: 2160 e_dbg("Failed to write receive address at index %d\n", index); 2161 return -E1000_ERR_CONFIG; 2162 } 2163 2164 /** 2165 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2166 * @hw: pointer to the HW structure 2167 * 2168 * Checks if firmware is blocking the reset of the PHY. 2169 * This is a function pointer entry point only called by 2170 * reset routines. 2171 **/ 2172 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2173 { 2174 bool blocked = false; 2175 int i = 0; 2176 2177 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2178 (i++ < 30)) 2179 usleep_range(10000, 11000); 2180 return blocked ? E1000_BLK_PHY_RESET : 0; 2181 } 2182 2183 /** 2184 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2185 * @hw: pointer to the HW structure 2186 * 2187 * Assumes semaphore already acquired. 2188 * 2189 **/ 2190 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2191 { 2192 u16 phy_data; 2193 u32 strap = er32(STRAP); 2194 u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap); 2195 s32 ret_val; 2196 2197 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2198 2199 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2200 if (ret_val) 2201 return ret_val; 2202 2203 phy_data &= ~HV_SMB_ADDR_MASK; 2204 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2205 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2206 2207 if (hw->phy.type == e1000_phy_i217) { 2208 /* Restore SMBus frequency */ 2209 if (freq--) { 2210 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2211 phy_data |= (freq & BIT(0)) << 2212 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2213 phy_data |= (freq & BIT(1)) << 2214 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2215 } else { 2216 e_dbg("Unsupported SMB frequency in PHY\n"); 2217 } 2218 } 2219 2220 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2221 } 2222 2223 /** 2224 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2225 * @hw: pointer to the HW structure 2226 * 2227 * SW should configure the LCD from the NVM extended configuration region 2228 * as a workaround for certain parts. 2229 **/ 2230 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2231 { 2232 struct e1000_phy_info *phy = &hw->phy; 2233 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2234 s32 ret_val = 0; 2235 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2236 2237 /* Initialize the PHY from the NVM on ICH platforms. This 2238 * is needed due to an issue where the NVM configuration is 2239 * not properly autoloaded after power transitions. 2240 * Therefore, after each PHY reset, we will load the 2241 * configuration data out of the NVM manually. 2242 */ 2243 switch (hw->mac.type) { 2244 case e1000_ich8lan: 2245 if (phy->type != e1000_phy_igp_3) 2246 return ret_val; 2247 2248 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2249 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2250 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2251 break; 2252 } 2253 fallthrough; 2254 case e1000_pchlan: 2255 case e1000_pch2lan: 2256 case e1000_pch_lpt: 2257 case e1000_pch_spt: 2258 case e1000_pch_cnp: 2259 case e1000_pch_tgp: 2260 case e1000_pch_adp: 2261 case e1000_pch_mtp: 2262 case e1000_pch_lnp: 2263 case e1000_pch_ptp: 2264 case e1000_pch_nvp: 2265 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2266 break; 2267 default: 2268 return ret_val; 2269 } 2270 2271 ret_val = hw->phy.ops.acquire(hw); 2272 if (ret_val) 2273 return ret_val; 2274 2275 data = er32(FEXTNVM); 2276 if (!(data & sw_cfg_mask)) 2277 goto release; 2278 2279 /* Make sure HW does not configure LCD from PHY 2280 * extended configuration before SW configuration 2281 */ 2282 data = er32(EXTCNF_CTRL); 2283 if ((hw->mac.type < e1000_pch2lan) && 2284 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2285 goto release; 2286 2287 cnf_size = er32(EXTCNF_SIZE); 2288 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2289 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2290 if (!cnf_size) 2291 goto release; 2292 2293 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2294 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2295 2296 if (((hw->mac.type == e1000_pchlan) && 2297 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2298 (hw->mac.type > e1000_pchlan)) { 2299 /* HW configures the SMBus address and LEDs when the 2300 * OEM and LCD Write Enable bits are set in the NVM. 2301 * When both NVM bits are cleared, SW will configure 2302 * them instead. 2303 */ 2304 ret_val = e1000_write_smbus_addr(hw); 2305 if (ret_val) 2306 goto release; 2307 2308 data = er32(LEDCTL); 2309 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2310 (u16)data); 2311 if (ret_val) 2312 goto release; 2313 } 2314 2315 /* Configure LCD from extended configuration region. */ 2316 2317 /* cnf_base_addr is in DWORD */ 2318 word_addr = (u16)(cnf_base_addr << 1); 2319 2320 for (i = 0; i < cnf_size; i++) { 2321 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2322 if (ret_val) 2323 goto release; 2324 2325 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2326 1, ®_addr); 2327 if (ret_val) 2328 goto release; 2329 2330 /* Save off the PHY page for future writes. */ 2331 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2332 phy_page = reg_data; 2333 continue; 2334 } 2335 2336 reg_addr &= PHY_REG_MASK; 2337 reg_addr |= phy_page; 2338 2339 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2340 if (ret_val) 2341 goto release; 2342 } 2343 2344 release: 2345 hw->phy.ops.release(hw); 2346 return ret_val; 2347 } 2348 2349 /** 2350 * e1000_k1_gig_workaround_hv - K1 Si workaround 2351 * @hw: pointer to the HW structure 2352 * @link: link up bool flag 2353 * 2354 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2355 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2356 * If link is down, the function will restore the default K1 setting located 2357 * in the NVM. 2358 **/ 2359 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2360 { 2361 s32 ret_val = 0; 2362 u16 status_reg = 0; 2363 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2364 2365 if (hw->mac.type != e1000_pchlan) 2366 return 0; 2367 2368 /* Wrap the whole flow with the sw flag */ 2369 ret_val = hw->phy.ops.acquire(hw); 2370 if (ret_val) 2371 return ret_val; 2372 2373 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2374 if (link) { 2375 if (hw->phy.type == e1000_phy_82578) { 2376 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2377 &status_reg); 2378 if (ret_val) 2379 goto release; 2380 2381 status_reg &= (BM_CS_STATUS_LINK_UP | 2382 BM_CS_STATUS_RESOLVED | 2383 BM_CS_STATUS_SPEED_MASK); 2384 2385 if (status_reg == (BM_CS_STATUS_LINK_UP | 2386 BM_CS_STATUS_RESOLVED | 2387 BM_CS_STATUS_SPEED_1000)) 2388 k1_enable = false; 2389 } 2390 2391 if (hw->phy.type == e1000_phy_82577) { 2392 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2393 if (ret_val) 2394 goto release; 2395 2396 status_reg &= (HV_M_STATUS_LINK_UP | 2397 HV_M_STATUS_AUTONEG_COMPLETE | 2398 HV_M_STATUS_SPEED_MASK); 2399 2400 if (status_reg == (HV_M_STATUS_LINK_UP | 2401 HV_M_STATUS_AUTONEG_COMPLETE | 2402 HV_M_STATUS_SPEED_1000)) 2403 k1_enable = false; 2404 } 2405 2406 /* Link stall fix for link up */ 2407 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2408 if (ret_val) 2409 goto release; 2410 2411 } else { 2412 /* Link stall fix for link down */ 2413 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2414 if (ret_val) 2415 goto release; 2416 } 2417 2418 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2419 2420 release: 2421 hw->phy.ops.release(hw); 2422 2423 return ret_val; 2424 } 2425 2426 /** 2427 * e1000_configure_k1_ich8lan - Configure K1 power state 2428 * @hw: pointer to the HW structure 2429 * @k1_enable: K1 state to configure 2430 * 2431 * Configure the K1 power state based on the provided parameter. 2432 * Assumes semaphore already acquired. 2433 * 2434 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2435 **/ 2436 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2437 { 2438 s32 ret_val; 2439 u32 ctrl_reg = 0; 2440 u32 ctrl_ext = 0; 2441 u32 reg = 0; 2442 u16 kmrn_reg = 0; 2443 2444 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2445 &kmrn_reg); 2446 if (ret_val) 2447 return ret_val; 2448 2449 if (k1_enable) 2450 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2451 else 2452 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2453 2454 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2455 kmrn_reg); 2456 if (ret_val) 2457 return ret_val; 2458 2459 usleep_range(20, 40); 2460 ctrl_ext = er32(CTRL_EXT); 2461 ctrl_reg = er32(CTRL); 2462 2463 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2464 reg |= E1000_CTRL_FRCSPD; 2465 ew32(CTRL, reg); 2466 2467 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2468 e1e_flush(); 2469 usleep_range(20, 40); 2470 ew32(CTRL, ctrl_reg); 2471 ew32(CTRL_EXT, ctrl_ext); 2472 e1e_flush(); 2473 usleep_range(20, 40); 2474 2475 return 0; 2476 } 2477 2478 /** 2479 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2480 * @hw: pointer to the HW structure 2481 * @d0_state: boolean if entering d0 or d3 device state 2482 * 2483 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2484 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2485 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2486 **/ 2487 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2488 { 2489 s32 ret_val = 0; 2490 u32 mac_reg; 2491 u16 oem_reg; 2492 2493 if (hw->mac.type < e1000_pchlan) 2494 return ret_val; 2495 2496 ret_val = hw->phy.ops.acquire(hw); 2497 if (ret_val) 2498 return ret_val; 2499 2500 if (hw->mac.type == e1000_pchlan) { 2501 mac_reg = er32(EXTCNF_CTRL); 2502 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2503 goto release; 2504 } 2505 2506 mac_reg = er32(FEXTNVM); 2507 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2508 goto release; 2509 2510 mac_reg = er32(PHY_CTRL); 2511 2512 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2513 if (ret_val) 2514 goto release; 2515 2516 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2517 2518 if (d0_state) { 2519 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2520 oem_reg |= HV_OEM_BITS_GBE_DIS; 2521 2522 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2523 oem_reg |= HV_OEM_BITS_LPLU; 2524 } else { 2525 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2526 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2527 oem_reg |= HV_OEM_BITS_GBE_DIS; 2528 2529 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2530 E1000_PHY_CTRL_NOND0A_LPLU)) 2531 oem_reg |= HV_OEM_BITS_LPLU; 2532 } 2533 2534 /* Set Restart auto-neg to activate the bits */ 2535 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2536 !hw->phy.ops.check_reset_block(hw)) 2537 oem_reg |= HV_OEM_BITS_RESTART_AN; 2538 2539 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2540 2541 release: 2542 hw->phy.ops.release(hw); 2543 2544 return ret_val; 2545 } 2546 2547 /** 2548 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2549 * @hw: pointer to the HW structure 2550 **/ 2551 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2552 { 2553 s32 ret_val; 2554 u16 data; 2555 2556 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2557 if (ret_val) 2558 return ret_val; 2559 2560 data |= HV_KMRN_MDIO_SLOW; 2561 2562 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2563 2564 return ret_val; 2565 } 2566 2567 /** 2568 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds 2569 * @hw: pointer to the HW structure 2570 * 2571 * A series of PHY workarounds to be done after every PHY reset. 2572 **/ 2573 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2574 { 2575 s32 ret_val = 0; 2576 u16 phy_data; 2577 2578 if (hw->mac.type != e1000_pchlan) 2579 return 0; 2580 2581 /* Set MDIO slow mode before any other MDIO access */ 2582 if (hw->phy.type == e1000_phy_82577) { 2583 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2584 if (ret_val) 2585 return ret_val; 2586 } 2587 2588 if (((hw->phy.type == e1000_phy_82577) && 2589 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2590 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2591 /* Disable generation of early preamble */ 2592 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2593 if (ret_val) 2594 return ret_val; 2595 2596 /* Preamble tuning for SSC */ 2597 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2598 if (ret_val) 2599 return ret_val; 2600 } 2601 2602 if (hw->phy.type == e1000_phy_82578) { 2603 /* Return registers to default by doing a soft reset then 2604 * writing 0x3140 to the control register. 2605 */ 2606 if (hw->phy.revision < 2) { 2607 e1000e_phy_sw_reset(hw); 2608 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2609 if (ret_val) 2610 return ret_val; 2611 } 2612 } 2613 2614 /* Select page 0 */ 2615 ret_val = hw->phy.ops.acquire(hw); 2616 if (ret_val) 2617 return ret_val; 2618 2619 hw->phy.addr = 1; 2620 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2621 hw->phy.ops.release(hw); 2622 if (ret_val) 2623 return ret_val; 2624 2625 /* Configure the K1 Si workaround during phy reset assuming there is 2626 * link so that it disables K1 if link is in 1Gbps. 2627 */ 2628 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2629 if (ret_val) 2630 return ret_val; 2631 2632 /* Workaround for link disconnects on a busy hub in half duplex */ 2633 ret_val = hw->phy.ops.acquire(hw); 2634 if (ret_val) 2635 return ret_val; 2636 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2637 if (ret_val) 2638 goto release; 2639 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2640 if (ret_val) 2641 goto release; 2642 2643 /* set MSE higher to enable link to stay up when noise is high */ 2644 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2645 release: 2646 hw->phy.ops.release(hw); 2647 2648 return ret_val; 2649 } 2650 2651 /** 2652 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2653 * @hw: pointer to the HW structure 2654 **/ 2655 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2656 { 2657 u32 mac_reg; 2658 u16 i, phy_reg = 0; 2659 s32 ret_val; 2660 2661 ret_val = hw->phy.ops.acquire(hw); 2662 if (ret_val) 2663 return; 2664 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2665 if (ret_val) 2666 goto release; 2667 2668 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2669 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2670 mac_reg = er32(RAL(i)); 2671 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2672 (u16)(mac_reg & 0xFFFF)); 2673 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2674 (u16)((mac_reg >> 16) & 0xFFFF)); 2675 2676 mac_reg = er32(RAH(i)); 2677 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2678 (u16)(mac_reg & 0xFFFF)); 2679 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2680 (u16)((mac_reg & E1000_RAH_AV) >> 16)); 2681 } 2682 2683 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2684 2685 release: 2686 hw->phy.ops.release(hw); 2687 } 2688 2689 /** 2690 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2691 * with 82579 PHY 2692 * @hw: pointer to the HW structure 2693 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2694 **/ 2695 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2696 { 2697 s32 ret_val = 0; 2698 u16 phy_reg, data; 2699 u32 mac_reg; 2700 u16 i; 2701 2702 if (hw->mac.type < e1000_pch2lan) 2703 return 0; 2704 2705 /* disable Rx path while enabling/disabling workaround */ 2706 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2707 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2708 if (ret_val) 2709 return ret_val; 2710 2711 if (enable) { 2712 /* Write Rx addresses (rar_entry_count for RAL/H, and 2713 * SHRAL/H) and initial CRC values to the MAC 2714 */ 2715 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2716 u8 mac_addr[ETH_ALEN] = { 0 }; 2717 u32 addr_high, addr_low; 2718 2719 addr_high = er32(RAH(i)); 2720 if (!(addr_high & E1000_RAH_AV)) 2721 continue; 2722 addr_low = er32(RAL(i)); 2723 mac_addr[0] = (addr_low & 0xFF); 2724 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2725 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2726 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2727 mac_addr[4] = (addr_high & 0xFF); 2728 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2729 2730 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2731 } 2732 2733 /* Write Rx addresses to the PHY */ 2734 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2735 2736 /* Enable jumbo frame workaround in the MAC */ 2737 mac_reg = er32(FFLT_DBG); 2738 mac_reg &= ~BIT(14); 2739 mac_reg |= (7 << 15); 2740 ew32(FFLT_DBG, mac_reg); 2741 2742 mac_reg = er32(RCTL); 2743 mac_reg |= E1000_RCTL_SECRC; 2744 ew32(RCTL, mac_reg); 2745 2746 ret_val = e1000e_read_kmrn_reg(hw, 2747 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2748 &data); 2749 if (ret_val) 2750 return ret_val; 2751 ret_val = e1000e_write_kmrn_reg(hw, 2752 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2753 data | BIT(0)); 2754 if (ret_val) 2755 return ret_val; 2756 ret_val = e1000e_read_kmrn_reg(hw, 2757 E1000_KMRNCTRLSTA_HD_CTRL, 2758 &data); 2759 if (ret_val) 2760 return ret_val; 2761 data &= ~(0xF << 8); 2762 data |= (0xB << 8); 2763 ret_val = e1000e_write_kmrn_reg(hw, 2764 E1000_KMRNCTRLSTA_HD_CTRL, 2765 data); 2766 if (ret_val) 2767 return ret_val; 2768 2769 /* Enable jumbo frame workaround in the PHY */ 2770 e1e_rphy(hw, PHY_REG(769, 23), &data); 2771 data &= ~(0x7F << 5); 2772 data |= (0x37 << 5); 2773 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2774 if (ret_val) 2775 return ret_val; 2776 e1e_rphy(hw, PHY_REG(769, 16), &data); 2777 data &= ~BIT(13); 2778 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2779 if (ret_val) 2780 return ret_val; 2781 e1e_rphy(hw, PHY_REG(776, 20), &data); 2782 data &= ~(0x3FF << 2); 2783 data |= (E1000_TX_PTR_GAP << 2); 2784 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2785 if (ret_val) 2786 return ret_val; 2787 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2788 if (ret_val) 2789 return ret_val; 2790 e1e_rphy(hw, HV_PM_CTRL, &data); 2791 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2792 if (ret_val) 2793 return ret_val; 2794 } else { 2795 /* Write MAC register values back to h/w defaults */ 2796 mac_reg = er32(FFLT_DBG); 2797 mac_reg &= ~(0xF << 14); 2798 ew32(FFLT_DBG, mac_reg); 2799 2800 mac_reg = er32(RCTL); 2801 mac_reg &= ~E1000_RCTL_SECRC; 2802 ew32(RCTL, mac_reg); 2803 2804 ret_val = e1000e_read_kmrn_reg(hw, 2805 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2806 &data); 2807 if (ret_val) 2808 return ret_val; 2809 ret_val = e1000e_write_kmrn_reg(hw, 2810 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2811 data & ~BIT(0)); 2812 if (ret_val) 2813 return ret_val; 2814 ret_val = e1000e_read_kmrn_reg(hw, 2815 E1000_KMRNCTRLSTA_HD_CTRL, 2816 &data); 2817 if (ret_val) 2818 return ret_val; 2819 data &= ~(0xF << 8); 2820 data |= (0xB << 8); 2821 ret_val = e1000e_write_kmrn_reg(hw, 2822 E1000_KMRNCTRLSTA_HD_CTRL, 2823 data); 2824 if (ret_val) 2825 return ret_val; 2826 2827 /* Write PHY register values back to h/w defaults */ 2828 e1e_rphy(hw, PHY_REG(769, 23), &data); 2829 data &= ~(0x7F << 5); 2830 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2831 if (ret_val) 2832 return ret_val; 2833 e1e_rphy(hw, PHY_REG(769, 16), &data); 2834 data |= BIT(13); 2835 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2836 if (ret_val) 2837 return ret_val; 2838 e1e_rphy(hw, PHY_REG(776, 20), &data); 2839 data &= ~(0x3FF << 2); 2840 data |= (0x8 << 2); 2841 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2842 if (ret_val) 2843 return ret_val; 2844 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2845 if (ret_val) 2846 return ret_val; 2847 e1e_rphy(hw, HV_PM_CTRL, &data); 2848 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2849 if (ret_val) 2850 return ret_val; 2851 } 2852 2853 /* re-enable Rx path after enabling/disabling workaround */ 2854 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2855 } 2856 2857 /** 2858 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds 2859 * @hw: pointer to the HW structure 2860 * 2861 * A series of PHY workarounds to be done after every PHY reset. 2862 **/ 2863 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2864 { 2865 s32 ret_val = 0; 2866 2867 if (hw->mac.type != e1000_pch2lan) 2868 return 0; 2869 2870 /* Set MDIO slow mode before any other MDIO access */ 2871 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2872 if (ret_val) 2873 return ret_val; 2874 2875 ret_val = hw->phy.ops.acquire(hw); 2876 if (ret_val) 2877 return ret_val; 2878 /* set MSE higher to enable link to stay up when noise is high */ 2879 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2880 if (ret_val) 2881 goto release; 2882 /* drop link after 5 times MSE threshold was reached */ 2883 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2884 release: 2885 hw->phy.ops.release(hw); 2886 2887 return ret_val; 2888 } 2889 2890 /** 2891 * e1000_k1_workaround_lv - K1 Si workaround 2892 * @hw: pointer to the HW structure 2893 * 2894 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2895 * Disable K1 in 1000Mbps and 100Mbps 2896 **/ 2897 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2898 { 2899 s32 ret_val = 0; 2900 u16 status_reg = 0; 2901 2902 if (hw->mac.type != e1000_pch2lan) 2903 return 0; 2904 2905 /* Set K1 beacon duration based on 10Mbs speed */ 2906 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2907 if (ret_val) 2908 return ret_val; 2909 2910 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2911 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2912 if (status_reg & 2913 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2914 u16 pm_phy_reg; 2915 2916 /* LV 1G/100 Packet drop issue wa */ 2917 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2918 if (ret_val) 2919 return ret_val; 2920 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2921 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2922 if (ret_val) 2923 return ret_val; 2924 } else { 2925 u32 mac_reg; 2926 2927 mac_reg = er32(FEXTNVM4); 2928 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2929 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2930 ew32(FEXTNVM4, mac_reg); 2931 } 2932 } 2933 2934 return ret_val; 2935 } 2936 2937 /** 2938 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2939 * @hw: pointer to the HW structure 2940 * @gate: boolean set to true to gate, false to ungate 2941 * 2942 * Gate/ungate the automatic PHY configuration via hardware; perform 2943 * the configuration via software instead. 2944 **/ 2945 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2946 { 2947 u32 extcnf_ctrl; 2948 2949 if (hw->mac.type < e1000_pch2lan) 2950 return; 2951 2952 extcnf_ctrl = er32(EXTCNF_CTRL); 2953 2954 if (gate) 2955 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2956 else 2957 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2958 2959 ew32(EXTCNF_CTRL, extcnf_ctrl); 2960 } 2961 2962 /** 2963 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2964 * @hw: pointer to the HW structure 2965 * 2966 * Check the appropriate indication the MAC has finished configuring the 2967 * PHY after a software reset. 2968 **/ 2969 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2970 { 2971 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2972 2973 /* Wait for basic configuration completes before proceeding */ 2974 do { 2975 data = er32(STATUS); 2976 data &= E1000_STATUS_LAN_INIT_DONE; 2977 usleep_range(100, 200); 2978 } while ((!data) && --loop); 2979 2980 /* If basic configuration is incomplete before the above loop 2981 * count reaches 0, loading the configuration from NVM will 2982 * leave the PHY in a bad state possibly resulting in no link. 2983 */ 2984 if (loop == 0) 2985 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2986 2987 /* Clear the Init Done bit for the next init event */ 2988 data = er32(STATUS); 2989 data &= ~E1000_STATUS_LAN_INIT_DONE; 2990 ew32(STATUS, data); 2991 } 2992 2993 /** 2994 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2995 * @hw: pointer to the HW structure 2996 **/ 2997 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2998 { 2999 s32 ret_val = 0; 3000 u16 reg; 3001 3002 if (hw->phy.ops.check_reset_block(hw)) 3003 return 0; 3004 3005 /* Allow time for h/w to get to quiescent state after reset */ 3006 usleep_range(10000, 11000); 3007 3008 /* Perform any necessary post-reset workarounds */ 3009 switch (hw->mac.type) { 3010 case e1000_pchlan: 3011 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 3012 if (ret_val) 3013 return ret_val; 3014 break; 3015 case e1000_pch2lan: 3016 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 3017 if (ret_val) 3018 return ret_val; 3019 break; 3020 default: 3021 break; 3022 } 3023 3024 /* Clear the host wakeup bit after lcd reset */ 3025 if (hw->mac.type >= e1000_pchlan) { 3026 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 3027 reg &= ~BM_WUC_HOST_WU_BIT; 3028 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 3029 } 3030 3031 /* Configure the LCD with the extended configuration region in NVM */ 3032 ret_val = e1000_sw_lcd_config_ich8lan(hw); 3033 if (ret_val) 3034 return ret_val; 3035 3036 /* Configure the LCD with the OEM bits in NVM */ 3037 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 3038 3039 if (hw->mac.type == e1000_pch2lan) { 3040 /* Ungate automatic PHY configuration on non-managed 82579 */ 3041 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 3042 usleep_range(10000, 11000); 3043 e1000_gate_hw_phy_config_ich8lan(hw, false); 3044 } 3045 3046 /* Set EEE LPI Update Timer to 200usec */ 3047 ret_val = hw->phy.ops.acquire(hw); 3048 if (ret_val) 3049 return ret_val; 3050 ret_val = e1000_write_emi_reg_locked(hw, 3051 I82579_LPI_UPDATE_TIMER, 3052 0x1387); 3053 hw->phy.ops.release(hw); 3054 } 3055 3056 return ret_val; 3057 } 3058 3059 /** 3060 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 3061 * @hw: pointer to the HW structure 3062 * 3063 * Resets the PHY 3064 * This is a function pointer entry point called by drivers 3065 * or other shared routines. 3066 **/ 3067 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 3068 { 3069 s32 ret_val = 0; 3070 3071 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 3072 if ((hw->mac.type == e1000_pch2lan) && 3073 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 3074 e1000_gate_hw_phy_config_ich8lan(hw, true); 3075 3076 ret_val = e1000e_phy_hw_reset_generic(hw); 3077 if (ret_val) 3078 return ret_val; 3079 3080 return e1000_post_phy_reset_ich8lan(hw); 3081 } 3082 3083 /** 3084 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 3085 * @hw: pointer to the HW structure 3086 * @active: true to enable LPLU, false to disable 3087 * 3088 * Sets the LPLU state according to the active flag. For PCH, if OEM write 3089 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 3090 * the phy speed. This function will manually set the LPLU bit and restart 3091 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 3092 * since it configures the same bit. 3093 **/ 3094 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 3095 { 3096 s32 ret_val; 3097 u16 oem_reg; 3098 3099 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 3100 if (ret_val) 3101 return ret_val; 3102 3103 if (active) 3104 oem_reg |= HV_OEM_BITS_LPLU; 3105 else 3106 oem_reg &= ~HV_OEM_BITS_LPLU; 3107 3108 if (!hw->phy.ops.check_reset_block(hw)) 3109 oem_reg |= HV_OEM_BITS_RESTART_AN; 3110 3111 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 3112 } 3113 3114 /** 3115 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 3116 * @hw: pointer to the HW structure 3117 * @active: true to enable LPLU, false to disable 3118 * 3119 * Sets the LPLU D0 state according to the active flag. When 3120 * activating LPLU this function also disables smart speed 3121 * and vice versa. LPLU will not be activated unless the 3122 * device autonegotiation advertisement meets standards of 3123 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3124 * This is a function pointer entry point only called by 3125 * PHY setup routines. 3126 **/ 3127 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3128 { 3129 struct e1000_phy_info *phy = &hw->phy; 3130 u32 phy_ctrl; 3131 s32 ret_val = 0; 3132 u16 data; 3133 3134 if (phy->type == e1000_phy_ife) 3135 return 0; 3136 3137 phy_ctrl = er32(PHY_CTRL); 3138 3139 if (active) { 3140 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3141 ew32(PHY_CTRL, phy_ctrl); 3142 3143 if (phy->type != e1000_phy_igp_3) 3144 return 0; 3145 3146 /* Call gig speed drop workaround on LPLU before accessing 3147 * any PHY registers 3148 */ 3149 if (hw->mac.type == e1000_ich8lan) 3150 e1000e_gig_downshift_workaround_ich8lan(hw); 3151 3152 /* When LPLU is enabled, we should disable SmartSpeed */ 3153 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3154 if (ret_val) 3155 return ret_val; 3156 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3157 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3158 if (ret_val) 3159 return ret_val; 3160 } else { 3161 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3162 ew32(PHY_CTRL, phy_ctrl); 3163 3164 if (phy->type != e1000_phy_igp_3) 3165 return 0; 3166 3167 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3168 * during Dx states where the power conservation is most 3169 * important. During driver activity we should enable 3170 * SmartSpeed, so performance is maintained. 3171 */ 3172 if (phy->smart_speed == e1000_smart_speed_on) { 3173 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3174 &data); 3175 if (ret_val) 3176 return ret_val; 3177 3178 data |= IGP01E1000_PSCFR_SMART_SPEED; 3179 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3180 data); 3181 if (ret_val) 3182 return ret_val; 3183 } else if (phy->smart_speed == e1000_smart_speed_off) { 3184 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3185 &data); 3186 if (ret_val) 3187 return ret_val; 3188 3189 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3190 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3191 data); 3192 if (ret_val) 3193 return ret_val; 3194 } 3195 } 3196 3197 return 0; 3198 } 3199 3200 /** 3201 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3202 * @hw: pointer to the HW structure 3203 * @active: true to enable LPLU, false to disable 3204 * 3205 * Sets the LPLU D3 state according to the active flag. When 3206 * activating LPLU this function also disables smart speed 3207 * and vice versa. LPLU will not be activated unless the 3208 * device autonegotiation advertisement meets standards of 3209 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3210 * This is a function pointer entry point only called by 3211 * PHY setup routines. 3212 **/ 3213 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3214 { 3215 struct e1000_phy_info *phy = &hw->phy; 3216 u32 phy_ctrl; 3217 s32 ret_val = 0; 3218 u16 data; 3219 3220 phy_ctrl = er32(PHY_CTRL); 3221 3222 if (!active) { 3223 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3224 ew32(PHY_CTRL, phy_ctrl); 3225 3226 if (phy->type != e1000_phy_igp_3) 3227 return 0; 3228 3229 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3230 * during Dx states where the power conservation is most 3231 * important. During driver activity we should enable 3232 * SmartSpeed, so performance is maintained. 3233 */ 3234 if (phy->smart_speed == e1000_smart_speed_on) { 3235 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3236 &data); 3237 if (ret_val) 3238 return ret_val; 3239 3240 data |= IGP01E1000_PSCFR_SMART_SPEED; 3241 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3242 data); 3243 if (ret_val) 3244 return ret_val; 3245 } else if (phy->smart_speed == e1000_smart_speed_off) { 3246 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3247 &data); 3248 if (ret_val) 3249 return ret_val; 3250 3251 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3252 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3253 data); 3254 if (ret_val) 3255 return ret_val; 3256 } 3257 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3258 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3259 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3260 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3261 ew32(PHY_CTRL, phy_ctrl); 3262 3263 if (phy->type != e1000_phy_igp_3) 3264 return 0; 3265 3266 /* Call gig speed drop workaround on LPLU before accessing 3267 * any PHY registers 3268 */ 3269 if (hw->mac.type == e1000_ich8lan) 3270 e1000e_gig_downshift_workaround_ich8lan(hw); 3271 3272 /* When LPLU is enabled, we should disable SmartSpeed */ 3273 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3274 if (ret_val) 3275 return ret_val; 3276 3277 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3278 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3279 } 3280 3281 return ret_val; 3282 } 3283 3284 /** 3285 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3286 * @hw: pointer to the HW structure 3287 * @bank: pointer to the variable that returns the active bank 3288 * 3289 * Reads signature byte from the NVM using the flash access registers. 3290 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3291 **/ 3292 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3293 { 3294 u32 eecd; 3295 struct e1000_nvm_info *nvm = &hw->nvm; 3296 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3297 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3298 u32 nvm_dword = 0; 3299 u8 sig_byte = 0; 3300 s32 ret_val; 3301 3302 switch (hw->mac.type) { 3303 case e1000_pch_spt: 3304 case e1000_pch_cnp: 3305 case e1000_pch_tgp: 3306 case e1000_pch_adp: 3307 case e1000_pch_mtp: 3308 case e1000_pch_lnp: 3309 case e1000_pch_ptp: 3310 case e1000_pch_nvp: 3311 bank1_offset = nvm->flash_bank_size; 3312 act_offset = E1000_ICH_NVM_SIG_WORD; 3313 3314 /* set bank to 0 in case flash read fails */ 3315 *bank = 0; 3316 3317 /* Check bank 0 */ 3318 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3319 &nvm_dword); 3320 if (ret_val) 3321 return ret_val; 3322 sig_byte = FIELD_GET(0xFF00, nvm_dword); 3323 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3324 E1000_ICH_NVM_SIG_VALUE) { 3325 *bank = 0; 3326 return 0; 3327 } 3328 3329 /* Check bank 1 */ 3330 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3331 bank1_offset, 3332 &nvm_dword); 3333 if (ret_val) 3334 return ret_val; 3335 sig_byte = FIELD_GET(0xFF00, nvm_dword); 3336 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3337 E1000_ICH_NVM_SIG_VALUE) { 3338 *bank = 1; 3339 return 0; 3340 } 3341 3342 e_dbg("ERROR: No valid NVM bank present\n"); 3343 return -E1000_ERR_NVM; 3344 case e1000_ich8lan: 3345 case e1000_ich9lan: 3346 eecd = er32(EECD); 3347 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3348 E1000_EECD_SEC1VAL_VALID_MASK) { 3349 if (eecd & E1000_EECD_SEC1VAL) 3350 *bank = 1; 3351 else 3352 *bank = 0; 3353 3354 return 0; 3355 } 3356 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3357 fallthrough; 3358 default: 3359 /* set bank to 0 in case flash read fails */ 3360 *bank = 0; 3361 3362 /* Check bank 0 */ 3363 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3364 &sig_byte); 3365 if (ret_val) 3366 return ret_val; 3367 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3368 E1000_ICH_NVM_SIG_VALUE) { 3369 *bank = 0; 3370 return 0; 3371 } 3372 3373 /* Check bank 1 */ 3374 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3375 bank1_offset, 3376 &sig_byte); 3377 if (ret_val) 3378 return ret_val; 3379 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3380 E1000_ICH_NVM_SIG_VALUE) { 3381 *bank = 1; 3382 return 0; 3383 } 3384 3385 e_dbg("ERROR: No valid NVM bank present\n"); 3386 return -E1000_ERR_NVM; 3387 } 3388 } 3389 3390 /** 3391 * e1000_read_nvm_spt - NVM access for SPT 3392 * @hw: pointer to the HW structure 3393 * @offset: The offset (in bytes) of the word(s) to read. 3394 * @words: Size of data to read in words. 3395 * @data: pointer to the word(s) to read at offset. 3396 * 3397 * Reads a word(s) from the NVM 3398 **/ 3399 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3400 u16 *data) 3401 { 3402 struct e1000_nvm_info *nvm = &hw->nvm; 3403 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3404 u32 act_offset; 3405 s32 ret_val = 0; 3406 u32 bank = 0; 3407 u32 dword = 0; 3408 u16 offset_to_read; 3409 u16 i; 3410 3411 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3412 (words == 0)) { 3413 e_dbg("nvm parameter(s) out of bounds\n"); 3414 ret_val = -E1000_ERR_NVM; 3415 goto out; 3416 } 3417 3418 nvm->ops.acquire(hw); 3419 3420 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3421 if (ret_val) { 3422 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3423 bank = 0; 3424 } 3425 3426 act_offset = (bank) ? nvm->flash_bank_size : 0; 3427 act_offset += offset; 3428 3429 ret_val = 0; 3430 3431 for (i = 0; i < words; i += 2) { 3432 if (words - i == 1) { 3433 if (dev_spec->shadow_ram[offset + i].modified) { 3434 data[i] = 3435 dev_spec->shadow_ram[offset + i].value; 3436 } else { 3437 offset_to_read = act_offset + i - 3438 ((act_offset + i) % 2); 3439 ret_val = 3440 e1000_read_flash_dword_ich8lan(hw, 3441 offset_to_read, 3442 &dword); 3443 if (ret_val) 3444 break; 3445 if ((act_offset + i) % 2 == 0) 3446 data[i] = (u16)(dword & 0xFFFF); 3447 else 3448 data[i] = (u16)((dword >> 16) & 0xFFFF); 3449 } 3450 } else { 3451 offset_to_read = act_offset + i; 3452 if (!(dev_spec->shadow_ram[offset + i].modified) || 3453 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3454 ret_val = 3455 e1000_read_flash_dword_ich8lan(hw, 3456 offset_to_read, 3457 &dword); 3458 if (ret_val) 3459 break; 3460 } 3461 if (dev_spec->shadow_ram[offset + i].modified) 3462 data[i] = 3463 dev_spec->shadow_ram[offset + i].value; 3464 else 3465 data[i] = (u16)(dword & 0xFFFF); 3466 if (dev_spec->shadow_ram[offset + i].modified) 3467 data[i + 1] = 3468 dev_spec->shadow_ram[offset + i + 1].value; 3469 else 3470 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3471 } 3472 } 3473 3474 nvm->ops.release(hw); 3475 3476 out: 3477 if (ret_val) 3478 e_dbg("NVM read error: %d\n", ret_val); 3479 3480 return ret_val; 3481 } 3482 3483 /** 3484 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3485 * @hw: pointer to the HW structure 3486 * @offset: The offset (in bytes) of the word(s) to read. 3487 * @words: Size of data to read in words 3488 * @data: Pointer to the word(s) to read at offset. 3489 * 3490 * Reads a word(s) from the NVM using the flash access registers. 3491 **/ 3492 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3493 u16 *data) 3494 { 3495 struct e1000_nvm_info *nvm = &hw->nvm; 3496 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3497 u32 act_offset; 3498 s32 ret_val = 0; 3499 u32 bank = 0; 3500 u16 i, word; 3501 3502 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3503 (words == 0)) { 3504 e_dbg("nvm parameter(s) out of bounds\n"); 3505 ret_val = -E1000_ERR_NVM; 3506 goto out; 3507 } 3508 3509 nvm->ops.acquire(hw); 3510 3511 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3512 if (ret_val) { 3513 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3514 bank = 0; 3515 } 3516 3517 act_offset = (bank) ? nvm->flash_bank_size : 0; 3518 act_offset += offset; 3519 3520 ret_val = 0; 3521 for (i = 0; i < words; i++) { 3522 if (dev_spec->shadow_ram[offset + i].modified) { 3523 data[i] = dev_spec->shadow_ram[offset + i].value; 3524 } else { 3525 ret_val = e1000_read_flash_word_ich8lan(hw, 3526 act_offset + i, 3527 &word); 3528 if (ret_val) 3529 break; 3530 data[i] = word; 3531 } 3532 } 3533 3534 nvm->ops.release(hw); 3535 3536 out: 3537 if (ret_val) 3538 e_dbg("NVM read error: %d\n", ret_val); 3539 3540 return ret_val; 3541 } 3542 3543 /** 3544 * e1000_flash_cycle_init_ich8lan - Initialize flash 3545 * @hw: pointer to the HW structure 3546 * 3547 * This function does initial flash setup so that a new read/write/erase cycle 3548 * can be started. 3549 **/ 3550 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3551 { 3552 union ich8_hws_flash_status hsfsts; 3553 s32 ret_val = -E1000_ERR_NVM; 3554 3555 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3556 3557 /* Check if the flash descriptor is valid */ 3558 if (!hsfsts.hsf_status.fldesvalid) { 3559 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3560 return -E1000_ERR_NVM; 3561 } 3562 3563 /* Clear FCERR and DAEL in hw status by writing 1 */ 3564 hsfsts.hsf_status.flcerr = 1; 3565 hsfsts.hsf_status.dael = 1; 3566 if (hw->mac.type >= e1000_pch_spt) 3567 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3568 else 3569 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3570 3571 /* Either we should have a hardware SPI cycle in progress 3572 * bit to check against, in order to start a new cycle or 3573 * FDONE bit should be changed in the hardware so that it 3574 * is 1 after hardware reset, which can then be used as an 3575 * indication whether a cycle is in progress or has been 3576 * completed. 3577 */ 3578 3579 if (!hsfsts.hsf_status.flcinprog) { 3580 /* There is no cycle running at present, 3581 * so we can start a cycle. 3582 * Begin by setting Flash Cycle Done. 3583 */ 3584 hsfsts.hsf_status.flcdone = 1; 3585 if (hw->mac.type >= e1000_pch_spt) 3586 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3587 else 3588 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3589 ret_val = 0; 3590 } else { 3591 s32 i; 3592 3593 /* Otherwise poll for sometime so the current 3594 * cycle has a chance to end before giving up. 3595 */ 3596 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3597 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3598 if (!hsfsts.hsf_status.flcinprog) { 3599 ret_val = 0; 3600 break; 3601 } 3602 udelay(1); 3603 } 3604 if (!ret_val) { 3605 /* Successful in waiting for previous cycle to timeout, 3606 * now set the Flash Cycle Done. 3607 */ 3608 hsfsts.hsf_status.flcdone = 1; 3609 if (hw->mac.type >= e1000_pch_spt) 3610 ew32flash(ICH_FLASH_HSFSTS, 3611 hsfsts.regval & 0xFFFF); 3612 else 3613 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3614 } else { 3615 e_dbg("Flash controller busy, cannot get access\n"); 3616 } 3617 } 3618 3619 return ret_val; 3620 } 3621 3622 /** 3623 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3624 * @hw: pointer to the HW structure 3625 * @timeout: maximum time to wait for completion 3626 * 3627 * This function starts a flash cycle and waits for its completion. 3628 **/ 3629 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3630 { 3631 union ich8_hws_flash_ctrl hsflctl; 3632 union ich8_hws_flash_status hsfsts; 3633 u32 i = 0; 3634 3635 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3636 if (hw->mac.type >= e1000_pch_spt) 3637 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3638 else 3639 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3640 hsflctl.hsf_ctrl.flcgo = 1; 3641 3642 if (hw->mac.type >= e1000_pch_spt) 3643 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3644 else 3645 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3646 3647 /* wait till FDONE bit is set to 1 */ 3648 do { 3649 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3650 if (hsfsts.hsf_status.flcdone) 3651 break; 3652 udelay(1); 3653 } while (i++ < timeout); 3654 3655 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3656 return 0; 3657 3658 return -E1000_ERR_NVM; 3659 } 3660 3661 /** 3662 * e1000_read_flash_dword_ich8lan - Read dword from flash 3663 * @hw: pointer to the HW structure 3664 * @offset: offset to data location 3665 * @data: pointer to the location for storing the data 3666 * 3667 * Reads the flash dword at offset into data. Offset is converted 3668 * to bytes before read. 3669 **/ 3670 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3671 u32 *data) 3672 { 3673 /* Must convert word offset into bytes. */ 3674 offset <<= 1; 3675 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3676 } 3677 3678 /** 3679 * e1000_read_flash_word_ich8lan - Read word from flash 3680 * @hw: pointer to the HW structure 3681 * @offset: offset to data location 3682 * @data: pointer to the location for storing the data 3683 * 3684 * Reads the flash word at offset into data. Offset is converted 3685 * to bytes before read. 3686 **/ 3687 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3688 u16 *data) 3689 { 3690 /* Must convert offset into bytes. */ 3691 offset <<= 1; 3692 3693 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3694 } 3695 3696 /** 3697 * e1000_read_flash_byte_ich8lan - Read byte from flash 3698 * @hw: pointer to the HW structure 3699 * @offset: The offset of the byte to read. 3700 * @data: Pointer to a byte to store the value read. 3701 * 3702 * Reads a single byte from the NVM using the flash access registers. 3703 **/ 3704 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3705 u8 *data) 3706 { 3707 s32 ret_val; 3708 u16 word = 0; 3709 3710 /* In SPT, only 32 bits access is supported, 3711 * so this function should not be called. 3712 */ 3713 if (hw->mac.type >= e1000_pch_spt) 3714 return -E1000_ERR_NVM; 3715 else 3716 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3717 3718 if (ret_val) 3719 return ret_val; 3720 3721 *data = (u8)word; 3722 3723 return 0; 3724 } 3725 3726 /** 3727 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3728 * @hw: pointer to the HW structure 3729 * @offset: The offset (in bytes) of the byte or word to read. 3730 * @size: Size of data to read, 1=byte 2=word 3731 * @data: Pointer to the word to store the value read. 3732 * 3733 * Reads a byte or word from the NVM using the flash access registers. 3734 **/ 3735 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3736 u8 size, u16 *data) 3737 { 3738 union ich8_hws_flash_status hsfsts; 3739 union ich8_hws_flash_ctrl hsflctl; 3740 u32 flash_linear_addr; 3741 u32 flash_data = 0; 3742 s32 ret_val = -E1000_ERR_NVM; 3743 u8 count = 0; 3744 3745 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3746 return -E1000_ERR_NVM; 3747 3748 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3749 hw->nvm.flash_base_addr); 3750 3751 do { 3752 udelay(1); 3753 /* Steps */ 3754 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3755 if (ret_val) 3756 break; 3757 3758 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3759 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3760 hsflctl.hsf_ctrl.fldbcount = size - 1; 3761 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3762 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3763 3764 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3765 3766 ret_val = 3767 e1000_flash_cycle_ich8lan(hw, 3768 ICH_FLASH_READ_COMMAND_TIMEOUT); 3769 3770 /* Check if FCERR is set to 1, if set to 1, clear it 3771 * and try the whole sequence a few more times, else 3772 * read in (shift in) the Flash Data0, the order is 3773 * least significant byte first msb to lsb 3774 */ 3775 if (!ret_val) { 3776 flash_data = er32flash(ICH_FLASH_FDATA0); 3777 if (size == 1) 3778 *data = (u8)(flash_data & 0x000000FF); 3779 else if (size == 2) 3780 *data = (u16)(flash_data & 0x0000FFFF); 3781 break; 3782 } else { 3783 /* If we've gotten here, then things are probably 3784 * completely hosed, but if the error condition is 3785 * detected, it won't hurt to give it another try... 3786 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3787 */ 3788 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3789 if (hsfsts.hsf_status.flcerr) { 3790 /* Repeat for some time before giving up. */ 3791 continue; 3792 } else if (!hsfsts.hsf_status.flcdone) { 3793 e_dbg("Timeout error - flash cycle did not complete.\n"); 3794 break; 3795 } 3796 } 3797 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3798 3799 return ret_val; 3800 } 3801 3802 /** 3803 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3804 * @hw: pointer to the HW structure 3805 * @offset: The offset (in bytes) of the dword to read. 3806 * @data: Pointer to the dword to store the value read. 3807 * 3808 * Reads a byte or word from the NVM using the flash access registers. 3809 **/ 3810 3811 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3812 u32 *data) 3813 { 3814 union ich8_hws_flash_status hsfsts; 3815 union ich8_hws_flash_ctrl hsflctl; 3816 u32 flash_linear_addr; 3817 s32 ret_val = -E1000_ERR_NVM; 3818 u8 count = 0; 3819 3820 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3821 return -E1000_ERR_NVM; 3822 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3823 hw->nvm.flash_base_addr); 3824 3825 do { 3826 udelay(1); 3827 /* Steps */ 3828 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3829 if (ret_val) 3830 break; 3831 /* In SPT, This register is in Lan memory space, not flash. 3832 * Therefore, only 32 bit access is supported 3833 */ 3834 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3835 3836 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3837 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3838 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3839 /* In SPT, This register is in Lan memory space, not flash. 3840 * Therefore, only 32 bit access is supported 3841 */ 3842 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3843 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3844 3845 ret_val = 3846 e1000_flash_cycle_ich8lan(hw, 3847 ICH_FLASH_READ_COMMAND_TIMEOUT); 3848 3849 /* Check if FCERR is set to 1, if set to 1, clear it 3850 * and try the whole sequence a few more times, else 3851 * read in (shift in) the Flash Data0, the order is 3852 * least significant byte first msb to lsb 3853 */ 3854 if (!ret_val) { 3855 *data = er32flash(ICH_FLASH_FDATA0); 3856 break; 3857 } else { 3858 /* If we've gotten here, then things are probably 3859 * completely hosed, but if the error condition is 3860 * detected, it won't hurt to give it another try... 3861 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3862 */ 3863 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3864 if (hsfsts.hsf_status.flcerr) { 3865 /* Repeat for some time before giving up. */ 3866 continue; 3867 } else if (!hsfsts.hsf_status.flcdone) { 3868 e_dbg("Timeout error - flash cycle did not complete.\n"); 3869 break; 3870 } 3871 } 3872 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3873 3874 return ret_val; 3875 } 3876 3877 /** 3878 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3879 * @hw: pointer to the HW structure 3880 * @offset: The offset (in bytes) of the word(s) to write. 3881 * @words: Size of data to write in words 3882 * @data: Pointer to the word(s) to write at offset. 3883 * 3884 * Writes a byte or word to the NVM using the flash access registers. 3885 **/ 3886 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3887 u16 *data) 3888 { 3889 struct e1000_nvm_info *nvm = &hw->nvm; 3890 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3891 u16 i; 3892 3893 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3894 (words == 0)) { 3895 e_dbg("nvm parameter(s) out of bounds\n"); 3896 return -E1000_ERR_NVM; 3897 } 3898 3899 nvm->ops.acquire(hw); 3900 3901 for (i = 0; i < words; i++) { 3902 dev_spec->shadow_ram[offset + i].modified = true; 3903 dev_spec->shadow_ram[offset + i].value = data[i]; 3904 } 3905 3906 nvm->ops.release(hw); 3907 3908 return 0; 3909 } 3910 3911 /** 3912 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3913 * @hw: pointer to the HW structure 3914 * 3915 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3916 * which writes the checksum to the shadow ram. The changes in the shadow 3917 * ram are then committed to the EEPROM by processing each bank at a time 3918 * checking for the modified bit and writing only the pending changes. 3919 * After a successful commit, the shadow ram is cleared and is ready for 3920 * future writes. 3921 **/ 3922 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3923 { 3924 struct e1000_nvm_info *nvm = &hw->nvm; 3925 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3926 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3927 s32 ret_val; 3928 u32 dword = 0; 3929 3930 ret_val = e1000e_update_nvm_checksum_generic(hw); 3931 if (ret_val) 3932 goto out; 3933 3934 if (nvm->type != e1000_nvm_flash_sw) 3935 goto out; 3936 3937 nvm->ops.acquire(hw); 3938 3939 /* We're writing to the opposite bank so if we're on bank 1, 3940 * write to bank 0 etc. We also need to erase the segment that 3941 * is going to be written 3942 */ 3943 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3944 if (ret_val) { 3945 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3946 bank = 0; 3947 } 3948 3949 if (bank == 0) { 3950 new_bank_offset = nvm->flash_bank_size; 3951 old_bank_offset = 0; 3952 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3953 if (ret_val) 3954 goto release; 3955 } else { 3956 old_bank_offset = nvm->flash_bank_size; 3957 new_bank_offset = 0; 3958 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3959 if (ret_val) 3960 goto release; 3961 } 3962 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3963 /* Determine whether to write the value stored 3964 * in the other NVM bank or a modified value stored 3965 * in the shadow RAM 3966 */ 3967 ret_val = e1000_read_flash_dword_ich8lan(hw, 3968 i + old_bank_offset, 3969 &dword); 3970 3971 if (dev_spec->shadow_ram[i].modified) { 3972 dword &= 0xffff0000; 3973 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3974 } 3975 if (dev_spec->shadow_ram[i + 1].modified) { 3976 dword &= 0x0000ffff; 3977 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3978 << 16); 3979 } 3980 if (ret_val) 3981 break; 3982 3983 /* If the word is 0x13, then make sure the signature bits 3984 * (15:14) are 11b until the commit has completed. 3985 * This will allow us to write 10b which indicates the 3986 * signature is valid. We want to do this after the write 3987 * has completed so that we don't mark the segment valid 3988 * while the write is still in progress 3989 */ 3990 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3991 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3992 3993 /* Convert offset to bytes. */ 3994 act_offset = (i + new_bank_offset) << 1; 3995 3996 usleep_range(100, 200); 3997 3998 /* Write the data to the new bank. Offset in words */ 3999 act_offset = i + new_bank_offset; 4000 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 4001 dword); 4002 if (ret_val) 4003 break; 4004 } 4005 4006 /* Don't bother writing the segment valid bits if sector 4007 * programming failed. 4008 */ 4009 if (ret_val) { 4010 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4011 e_dbg("Flash commit failed.\n"); 4012 goto release; 4013 } 4014 4015 /* Finally validate the new segment by setting bit 15:14 4016 * to 10b in word 0x13 , this can be done without an 4017 * erase as well since these bits are 11 to start with 4018 * and we need to change bit 14 to 0b 4019 */ 4020 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4021 4022 /*offset in words but we read dword */ 4023 --act_offset; 4024 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4025 4026 if (ret_val) 4027 goto release; 4028 4029 dword &= 0xBFFFFFFF; 4030 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4031 4032 if (ret_val) 4033 goto release; 4034 4035 /* offset in words but we read dword */ 4036 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 4037 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4038 4039 if (ret_val) 4040 goto release; 4041 4042 dword &= 0x00FFFFFF; 4043 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4044 4045 if (ret_val) 4046 goto release; 4047 4048 /* Great! Everything worked, we can now clear the cached entries. */ 4049 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4050 dev_spec->shadow_ram[i].modified = false; 4051 dev_spec->shadow_ram[i].value = 0xFFFF; 4052 } 4053 4054 release: 4055 nvm->ops.release(hw); 4056 4057 /* Reload the EEPROM, or else modifications will not appear 4058 * until after the next adapter reset. 4059 */ 4060 if (!ret_val) { 4061 nvm->ops.reload(hw); 4062 usleep_range(10000, 11000); 4063 } 4064 4065 out: 4066 if (ret_val) 4067 e_dbg("NVM update error: %d\n", ret_val); 4068 4069 return ret_val; 4070 } 4071 4072 /** 4073 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 4074 * @hw: pointer to the HW structure 4075 * 4076 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4077 * which writes the checksum to the shadow ram. The changes in the shadow 4078 * ram are then committed to the EEPROM by processing each bank at a time 4079 * checking for the modified bit and writing only the pending changes. 4080 * After a successful commit, the shadow ram is cleared and is ready for 4081 * future writes. 4082 **/ 4083 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 4084 { 4085 struct e1000_nvm_info *nvm = &hw->nvm; 4086 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4087 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4088 s32 ret_val; 4089 u16 data = 0; 4090 4091 ret_val = e1000e_update_nvm_checksum_generic(hw); 4092 if (ret_val) 4093 goto out; 4094 4095 if (nvm->type != e1000_nvm_flash_sw) 4096 goto out; 4097 4098 nvm->ops.acquire(hw); 4099 4100 /* We're writing to the opposite bank so if we're on bank 1, 4101 * write to bank 0 etc. We also need to erase the segment that 4102 * is going to be written 4103 */ 4104 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4105 if (ret_val) { 4106 e_dbg("Could not detect valid bank, assuming bank 0\n"); 4107 bank = 0; 4108 } 4109 4110 if (bank == 0) { 4111 new_bank_offset = nvm->flash_bank_size; 4112 old_bank_offset = 0; 4113 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4114 if (ret_val) 4115 goto release; 4116 } else { 4117 old_bank_offset = nvm->flash_bank_size; 4118 new_bank_offset = 0; 4119 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4120 if (ret_val) 4121 goto release; 4122 } 4123 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4124 if (dev_spec->shadow_ram[i].modified) { 4125 data = dev_spec->shadow_ram[i].value; 4126 } else { 4127 ret_val = e1000_read_flash_word_ich8lan(hw, i + 4128 old_bank_offset, 4129 &data); 4130 if (ret_val) 4131 break; 4132 } 4133 4134 /* If the word is 0x13, then make sure the signature bits 4135 * (15:14) are 11b until the commit has completed. 4136 * This will allow us to write 10b which indicates the 4137 * signature is valid. We want to do this after the write 4138 * has completed so that we don't mark the segment valid 4139 * while the write is still in progress 4140 */ 4141 if (i == E1000_ICH_NVM_SIG_WORD) 4142 data |= E1000_ICH_NVM_SIG_MASK; 4143 4144 /* Convert offset to bytes. */ 4145 act_offset = (i + new_bank_offset) << 1; 4146 4147 usleep_range(100, 200); 4148 /* Write the bytes to the new bank. */ 4149 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4150 act_offset, 4151 (u8)data); 4152 if (ret_val) 4153 break; 4154 4155 usleep_range(100, 200); 4156 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4157 act_offset + 1, 4158 (u8)(data >> 8)); 4159 if (ret_val) 4160 break; 4161 } 4162 4163 /* Don't bother writing the segment valid bits if sector 4164 * programming failed. 4165 */ 4166 if (ret_val) { 4167 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4168 e_dbg("Flash commit failed.\n"); 4169 goto release; 4170 } 4171 4172 /* Finally validate the new segment by setting bit 15:14 4173 * to 10b in word 0x13 , this can be done without an 4174 * erase as well since these bits are 11 to start with 4175 * and we need to change bit 14 to 0b 4176 */ 4177 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4178 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4179 if (ret_val) 4180 goto release; 4181 4182 data &= 0xBFFF; 4183 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4184 act_offset * 2 + 1, 4185 (u8)(data >> 8)); 4186 if (ret_val) 4187 goto release; 4188 4189 /* And invalidate the previously valid segment by setting 4190 * its signature word (0x13) high_byte to 0b. This can be 4191 * done without an erase because flash erase sets all bits 4192 * to 1's. We can write 1's to 0's without an erase 4193 */ 4194 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4195 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4196 if (ret_val) 4197 goto release; 4198 4199 /* Great! Everything worked, we can now clear the cached entries. */ 4200 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4201 dev_spec->shadow_ram[i].modified = false; 4202 dev_spec->shadow_ram[i].value = 0xFFFF; 4203 } 4204 4205 release: 4206 nvm->ops.release(hw); 4207 4208 /* Reload the EEPROM, or else modifications will not appear 4209 * until after the next adapter reset. 4210 */ 4211 if (!ret_val) { 4212 nvm->ops.reload(hw); 4213 usleep_range(10000, 11000); 4214 } 4215 4216 out: 4217 if (ret_val) 4218 e_dbg("NVM update error: %d\n", ret_val); 4219 4220 return ret_val; 4221 } 4222 4223 /** 4224 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4225 * @hw: pointer to the HW structure 4226 * 4227 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4228 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4229 * calculated, in which case we need to calculate the checksum and set bit 6. 4230 **/ 4231 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4232 { 4233 s32 ret_val; 4234 u16 data; 4235 u16 word; 4236 u16 valid_csum_mask; 4237 4238 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4239 * the checksum needs to be fixed. This bit is an indication that 4240 * the NVM was prepared by OEM software and did not calculate 4241 * the checksum...a likely scenario. 4242 */ 4243 switch (hw->mac.type) { 4244 case e1000_pch_lpt: 4245 case e1000_pch_spt: 4246 case e1000_pch_cnp: 4247 case e1000_pch_tgp: 4248 case e1000_pch_adp: 4249 case e1000_pch_mtp: 4250 case e1000_pch_lnp: 4251 case e1000_pch_ptp: 4252 case e1000_pch_nvp: 4253 word = NVM_COMPAT; 4254 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4255 break; 4256 default: 4257 word = NVM_FUTURE_INIT_WORD1; 4258 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4259 break; 4260 } 4261 4262 ret_val = e1000_read_nvm(hw, word, 1, &data); 4263 if (ret_val) 4264 return ret_val; 4265 4266 if (!(data & valid_csum_mask)) { 4267 e_dbg("NVM Checksum valid bit not set\n"); 4268 4269 if (hw->mac.type < e1000_pch_tgp) { 4270 data |= valid_csum_mask; 4271 ret_val = e1000_write_nvm(hw, word, 1, &data); 4272 if (ret_val) 4273 return ret_val; 4274 ret_val = e1000e_update_nvm_checksum(hw); 4275 if (ret_val) 4276 return ret_val; 4277 } 4278 } 4279 4280 return e1000e_validate_nvm_checksum_generic(hw); 4281 } 4282 4283 /** 4284 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4285 * @hw: pointer to the HW structure 4286 * 4287 * To prevent malicious write/erase of the NVM, set it to be read-only 4288 * so that the hardware ignores all write/erase cycles of the NVM via 4289 * the flash control registers. The shadow-ram copy of the NVM will 4290 * still be updated, however any updates to this copy will not stick 4291 * across driver reloads. 4292 **/ 4293 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4294 { 4295 struct e1000_nvm_info *nvm = &hw->nvm; 4296 union ich8_flash_protected_range pr0; 4297 union ich8_hws_flash_status hsfsts; 4298 u32 gfpreg; 4299 4300 nvm->ops.acquire(hw); 4301 4302 gfpreg = er32flash(ICH_FLASH_GFPREG); 4303 4304 /* Write-protect GbE Sector of NVM */ 4305 pr0.regval = er32flash(ICH_FLASH_PR0); 4306 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4307 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4308 pr0.range.wpe = true; 4309 ew32flash(ICH_FLASH_PR0, pr0.regval); 4310 4311 /* Lock down a subset of GbE Flash Control Registers, e.g. 4312 * PR0 to prevent the write-protection from being lifted. 4313 * Once FLOCKDN is set, the registers protected by it cannot 4314 * be written until FLOCKDN is cleared by a hardware reset. 4315 */ 4316 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4317 hsfsts.hsf_status.flockdn = true; 4318 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4319 4320 nvm->ops.release(hw); 4321 } 4322 4323 /** 4324 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4325 * @hw: pointer to the HW structure 4326 * @offset: The offset (in bytes) of the byte/word to read. 4327 * @size: Size of data to read, 1=byte 2=word 4328 * @data: The byte(s) to write to the NVM. 4329 * 4330 * Writes one/two bytes to the NVM using the flash access registers. 4331 **/ 4332 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4333 u8 size, u16 data) 4334 { 4335 union ich8_hws_flash_status hsfsts; 4336 union ich8_hws_flash_ctrl hsflctl; 4337 u32 flash_linear_addr; 4338 u32 flash_data = 0; 4339 s32 ret_val; 4340 u8 count = 0; 4341 4342 if (hw->mac.type >= e1000_pch_spt) { 4343 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4344 return -E1000_ERR_NVM; 4345 } else { 4346 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4347 return -E1000_ERR_NVM; 4348 } 4349 4350 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4351 hw->nvm.flash_base_addr); 4352 4353 do { 4354 udelay(1); 4355 /* Steps */ 4356 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4357 if (ret_val) 4358 break; 4359 /* In SPT, This register is in Lan memory space, not 4360 * flash. Therefore, only 32 bit access is supported 4361 */ 4362 if (hw->mac.type >= e1000_pch_spt) 4363 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4364 else 4365 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4366 4367 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4368 hsflctl.hsf_ctrl.fldbcount = size - 1; 4369 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4370 /* In SPT, This register is in Lan memory space, 4371 * not flash. Therefore, only 32 bit access is 4372 * supported 4373 */ 4374 if (hw->mac.type >= e1000_pch_spt) 4375 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4376 else 4377 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4378 4379 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4380 4381 if (size == 1) 4382 flash_data = (u32)data & 0x00FF; 4383 else 4384 flash_data = (u32)data; 4385 4386 ew32flash(ICH_FLASH_FDATA0, flash_data); 4387 4388 /* check if FCERR is set to 1 , if set to 1, clear it 4389 * and try the whole sequence a few more times else done 4390 */ 4391 ret_val = 4392 e1000_flash_cycle_ich8lan(hw, 4393 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4394 if (!ret_val) 4395 break; 4396 4397 /* If we're here, then things are most likely 4398 * completely hosed, but if the error condition 4399 * is detected, it won't hurt to give it another 4400 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4401 */ 4402 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4403 if (hsfsts.hsf_status.flcerr) 4404 /* Repeat for some time before giving up. */ 4405 continue; 4406 if (!hsfsts.hsf_status.flcdone) { 4407 e_dbg("Timeout error - flash cycle did not complete.\n"); 4408 break; 4409 } 4410 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4411 4412 return ret_val; 4413 } 4414 4415 /** 4416 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4417 * @hw: pointer to the HW structure 4418 * @offset: The offset (in bytes) of the dwords to read. 4419 * @data: The 4 bytes to write to the NVM. 4420 * 4421 * Writes one/two/four bytes to the NVM using the flash access registers. 4422 **/ 4423 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4424 u32 data) 4425 { 4426 union ich8_hws_flash_status hsfsts; 4427 union ich8_hws_flash_ctrl hsflctl; 4428 u32 flash_linear_addr; 4429 s32 ret_val; 4430 u8 count = 0; 4431 4432 if (hw->mac.type >= e1000_pch_spt) { 4433 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4434 return -E1000_ERR_NVM; 4435 } 4436 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4437 hw->nvm.flash_base_addr); 4438 do { 4439 udelay(1); 4440 /* Steps */ 4441 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4442 if (ret_val) 4443 break; 4444 4445 /* In SPT, This register is in Lan memory space, not 4446 * flash. Therefore, only 32 bit access is supported 4447 */ 4448 if (hw->mac.type >= e1000_pch_spt) 4449 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4450 >> 16; 4451 else 4452 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4453 4454 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4455 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4456 4457 /* In SPT, This register is in Lan memory space, 4458 * not flash. Therefore, only 32 bit access is 4459 * supported 4460 */ 4461 if (hw->mac.type >= e1000_pch_spt) 4462 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4463 else 4464 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4465 4466 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4467 4468 ew32flash(ICH_FLASH_FDATA0, data); 4469 4470 /* check if FCERR is set to 1 , if set to 1, clear it 4471 * and try the whole sequence a few more times else done 4472 */ 4473 ret_val = 4474 e1000_flash_cycle_ich8lan(hw, 4475 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4476 4477 if (!ret_val) 4478 break; 4479 4480 /* If we're here, then things are most likely 4481 * completely hosed, but if the error condition 4482 * is detected, it won't hurt to give it another 4483 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4484 */ 4485 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4486 4487 if (hsfsts.hsf_status.flcerr) 4488 /* Repeat for some time before giving up. */ 4489 continue; 4490 if (!hsfsts.hsf_status.flcdone) { 4491 e_dbg("Timeout error - flash cycle did not complete.\n"); 4492 break; 4493 } 4494 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4495 4496 return ret_val; 4497 } 4498 4499 /** 4500 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4501 * @hw: pointer to the HW structure 4502 * @offset: The index of the byte to read. 4503 * @data: The byte to write to the NVM. 4504 * 4505 * Writes a single byte to the NVM using the flash access registers. 4506 **/ 4507 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4508 u8 data) 4509 { 4510 u16 word = (u16)data; 4511 4512 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4513 } 4514 4515 /** 4516 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4517 * @hw: pointer to the HW structure 4518 * @offset: The offset of the word to write. 4519 * @dword: The dword to write to the NVM. 4520 * 4521 * Writes a single dword to the NVM using the flash access registers. 4522 * Goes through a retry algorithm before giving up. 4523 **/ 4524 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4525 u32 offset, u32 dword) 4526 { 4527 s32 ret_val; 4528 u16 program_retries; 4529 4530 /* Must convert word offset into bytes. */ 4531 offset <<= 1; 4532 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4533 4534 if (!ret_val) 4535 return ret_val; 4536 for (program_retries = 0; program_retries < 100; program_retries++) { 4537 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4538 usleep_range(100, 200); 4539 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4540 if (!ret_val) 4541 break; 4542 } 4543 if (program_retries == 100) 4544 return -E1000_ERR_NVM; 4545 4546 return 0; 4547 } 4548 4549 /** 4550 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4551 * @hw: pointer to the HW structure 4552 * @offset: The offset of the byte to write. 4553 * @byte: The byte to write to the NVM. 4554 * 4555 * Writes a single byte to the NVM using the flash access registers. 4556 * Goes through a retry algorithm before giving up. 4557 **/ 4558 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4559 u32 offset, u8 byte) 4560 { 4561 s32 ret_val; 4562 u16 program_retries; 4563 4564 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4565 if (!ret_val) 4566 return ret_val; 4567 4568 for (program_retries = 0; program_retries < 100; program_retries++) { 4569 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4570 usleep_range(100, 200); 4571 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4572 if (!ret_val) 4573 break; 4574 } 4575 if (program_retries == 100) 4576 return -E1000_ERR_NVM; 4577 4578 return 0; 4579 } 4580 4581 /** 4582 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4583 * @hw: pointer to the HW structure 4584 * @bank: 0 for first bank, 1 for second bank, etc. 4585 * 4586 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4587 * bank N is 4096 * N + flash_reg_addr. 4588 **/ 4589 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4590 { 4591 struct e1000_nvm_info *nvm = &hw->nvm; 4592 union ich8_hws_flash_status hsfsts; 4593 union ich8_hws_flash_ctrl hsflctl; 4594 u32 flash_linear_addr; 4595 /* bank size is in 16bit words - adjust to bytes */ 4596 u32 flash_bank_size = nvm->flash_bank_size * 2; 4597 s32 ret_val; 4598 s32 count = 0; 4599 s32 j, iteration, sector_size; 4600 4601 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4602 4603 /* Determine HW Sector size: Read BERASE bits of hw flash status 4604 * register 4605 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4606 * consecutive sectors. The start index for the nth Hw sector 4607 * can be calculated as = bank * 4096 + n * 256 4608 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4609 * The start index for the nth Hw sector can be calculated 4610 * as = bank * 4096 4611 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4612 * (ich9 only, otherwise error condition) 4613 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4614 */ 4615 switch (hsfsts.hsf_status.berasesz) { 4616 case 0: 4617 /* Hw sector size 256 */ 4618 sector_size = ICH_FLASH_SEG_SIZE_256; 4619 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4620 break; 4621 case 1: 4622 sector_size = ICH_FLASH_SEG_SIZE_4K; 4623 iteration = 1; 4624 break; 4625 case 2: 4626 sector_size = ICH_FLASH_SEG_SIZE_8K; 4627 iteration = 1; 4628 break; 4629 case 3: 4630 sector_size = ICH_FLASH_SEG_SIZE_64K; 4631 iteration = 1; 4632 break; 4633 default: 4634 return -E1000_ERR_NVM; 4635 } 4636 4637 /* Start with the base address, then add the sector offset. */ 4638 flash_linear_addr = hw->nvm.flash_base_addr; 4639 flash_linear_addr += (bank) ? flash_bank_size : 0; 4640 4641 for (j = 0; j < iteration; j++) { 4642 do { 4643 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4644 4645 /* Steps */ 4646 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4647 if (ret_val) 4648 return ret_val; 4649 4650 /* Write a value 11 (block Erase) in Flash 4651 * Cycle field in hw flash control 4652 */ 4653 if (hw->mac.type >= e1000_pch_spt) 4654 hsflctl.regval = 4655 er32flash(ICH_FLASH_HSFSTS) >> 16; 4656 else 4657 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4658 4659 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4660 if (hw->mac.type >= e1000_pch_spt) 4661 ew32flash(ICH_FLASH_HSFSTS, 4662 hsflctl.regval << 16); 4663 else 4664 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4665 4666 /* Write the last 24 bits of an index within the 4667 * block into Flash Linear address field in Flash 4668 * Address. 4669 */ 4670 flash_linear_addr += (j * sector_size); 4671 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4672 4673 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4674 if (!ret_val) 4675 break; 4676 4677 /* Check if FCERR is set to 1. If 1, 4678 * clear it and try the whole sequence 4679 * a few more times else Done 4680 */ 4681 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4682 if (hsfsts.hsf_status.flcerr) 4683 /* repeat for some time before giving up */ 4684 continue; 4685 else if (!hsfsts.hsf_status.flcdone) 4686 return ret_val; 4687 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4688 } 4689 4690 return 0; 4691 } 4692 4693 /** 4694 * e1000_valid_led_default_ich8lan - Set the default LED settings 4695 * @hw: pointer to the HW structure 4696 * @data: Pointer to the LED settings 4697 * 4698 * Reads the LED default settings from the NVM to data. If the NVM LED 4699 * settings is all 0's or F's, set the LED default to a valid LED default 4700 * setting. 4701 **/ 4702 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4703 { 4704 s32 ret_val; 4705 4706 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4707 if (ret_val) { 4708 e_dbg("NVM Read Error\n"); 4709 return ret_val; 4710 } 4711 4712 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4713 *data = ID_LED_DEFAULT_ICH8LAN; 4714 4715 return 0; 4716 } 4717 4718 /** 4719 * e1000_id_led_init_pchlan - store LED configurations 4720 * @hw: pointer to the HW structure 4721 * 4722 * PCH does not control LEDs via the LEDCTL register, rather it uses 4723 * the PHY LED configuration register. 4724 * 4725 * PCH also does not have an "always on" or "always off" mode which 4726 * complicates the ID feature. Instead of using the "on" mode to indicate 4727 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4728 * use "link_up" mode. The LEDs will still ID on request if there is no 4729 * link based on logic in e1000_led_[on|off]_pchlan(). 4730 **/ 4731 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4732 { 4733 struct e1000_mac_info *mac = &hw->mac; 4734 s32 ret_val; 4735 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4736 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4737 u16 data, i, temp, shift; 4738 4739 /* Get default ID LED modes */ 4740 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4741 if (ret_val) 4742 return ret_val; 4743 4744 mac->ledctl_default = er32(LEDCTL); 4745 mac->ledctl_mode1 = mac->ledctl_default; 4746 mac->ledctl_mode2 = mac->ledctl_default; 4747 4748 for (i = 0; i < 4; i++) { 4749 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4750 shift = (i * 5); 4751 switch (temp) { 4752 case ID_LED_ON1_DEF2: 4753 case ID_LED_ON1_ON2: 4754 case ID_LED_ON1_OFF2: 4755 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4756 mac->ledctl_mode1 |= (ledctl_on << shift); 4757 break; 4758 case ID_LED_OFF1_DEF2: 4759 case ID_LED_OFF1_ON2: 4760 case ID_LED_OFF1_OFF2: 4761 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4762 mac->ledctl_mode1 |= (ledctl_off << shift); 4763 break; 4764 default: 4765 /* Do nothing */ 4766 break; 4767 } 4768 switch (temp) { 4769 case ID_LED_DEF1_ON2: 4770 case ID_LED_ON1_ON2: 4771 case ID_LED_OFF1_ON2: 4772 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4773 mac->ledctl_mode2 |= (ledctl_on << shift); 4774 break; 4775 case ID_LED_DEF1_OFF2: 4776 case ID_LED_ON1_OFF2: 4777 case ID_LED_OFF1_OFF2: 4778 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4779 mac->ledctl_mode2 |= (ledctl_off << shift); 4780 break; 4781 default: 4782 /* Do nothing */ 4783 break; 4784 } 4785 } 4786 4787 return 0; 4788 } 4789 4790 /** 4791 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4792 * @hw: pointer to the HW structure 4793 * 4794 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4795 * register, so the bus width is hard coded. 4796 **/ 4797 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4798 { 4799 struct e1000_bus_info *bus = &hw->bus; 4800 s32 ret_val; 4801 4802 ret_val = e1000e_get_bus_info_pcie(hw); 4803 4804 /* ICH devices are "PCI Express"-ish. They have 4805 * a configuration space, but do not contain 4806 * PCI Express Capability registers, so bus width 4807 * must be hardcoded. 4808 */ 4809 if (bus->width == e1000_bus_width_unknown) 4810 bus->width = e1000_bus_width_pcie_x1; 4811 4812 return ret_val; 4813 } 4814 4815 /** 4816 * e1000_reset_hw_ich8lan - Reset the hardware 4817 * @hw: pointer to the HW structure 4818 * 4819 * Does a full reset of the hardware which includes a reset of the PHY and 4820 * MAC. 4821 **/ 4822 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4823 { 4824 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4825 u16 kum_cfg; 4826 u32 ctrl, reg; 4827 s32 ret_val; 4828 4829 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4830 * on the last TLP read/write transaction when MAC is reset. 4831 */ 4832 ret_val = e1000e_disable_pcie_master(hw); 4833 if (ret_val) 4834 e_dbg("PCI-E Master disable polling has failed.\n"); 4835 4836 e_dbg("Masking off all interrupts\n"); 4837 ew32(IMC, 0xffffffff); 4838 4839 /* Disable the Transmit and Receive units. Then delay to allow 4840 * any pending transactions to complete before we hit the MAC 4841 * with the global reset. 4842 */ 4843 ew32(RCTL, 0); 4844 ew32(TCTL, E1000_TCTL_PSP); 4845 e1e_flush(); 4846 4847 usleep_range(10000, 11000); 4848 4849 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4850 if (hw->mac.type == e1000_ich8lan) { 4851 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4852 ew32(PBA, E1000_PBA_8K); 4853 /* Set Packet Buffer Size to 16k. */ 4854 ew32(PBS, E1000_PBS_16K); 4855 } 4856 4857 if (hw->mac.type == e1000_pchlan) { 4858 /* Save the NVM K1 bit setting */ 4859 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4860 if (ret_val) 4861 return ret_val; 4862 4863 if (kum_cfg & E1000_NVM_K1_ENABLE) 4864 dev_spec->nvm_k1_enabled = true; 4865 else 4866 dev_spec->nvm_k1_enabled = false; 4867 } 4868 4869 ctrl = er32(CTRL); 4870 4871 if (!hw->phy.ops.check_reset_block(hw)) { 4872 /* Full-chip reset requires MAC and PHY reset at the same 4873 * time to make sure the interface between MAC and the 4874 * external PHY is reset. 4875 */ 4876 ctrl |= E1000_CTRL_PHY_RST; 4877 4878 /* Gate automatic PHY configuration by hardware on 4879 * non-managed 82579 4880 */ 4881 if ((hw->mac.type == e1000_pch2lan) && 4882 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4883 e1000_gate_hw_phy_config_ich8lan(hw, true); 4884 } 4885 ret_val = e1000_acquire_swflag_ich8lan(hw); 4886 e_dbg("Issuing a global reset to ich8lan\n"); 4887 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4888 /* cannot issue a flush here because it hangs the hardware */ 4889 msleep(20); 4890 4891 /* Set Phy Config Counter to 50msec */ 4892 if (hw->mac.type == e1000_pch2lan) { 4893 reg = er32(FEXTNVM3); 4894 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4895 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4896 ew32(FEXTNVM3, reg); 4897 } 4898 4899 if (!ret_val) 4900 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4901 4902 if (ctrl & E1000_CTRL_PHY_RST) { 4903 ret_val = hw->phy.ops.get_cfg_done(hw); 4904 if (ret_val) 4905 return ret_val; 4906 4907 ret_val = e1000_post_phy_reset_ich8lan(hw); 4908 if (ret_val) 4909 return ret_val; 4910 } 4911 4912 /* For PCH, this write will make sure that any noise 4913 * will be detected as a CRC error and be dropped rather than show up 4914 * as a bad packet to the DMA engine. 4915 */ 4916 if (hw->mac.type == e1000_pchlan) 4917 ew32(CRC_OFFSET, 0x65656565); 4918 4919 ew32(IMC, 0xffffffff); 4920 er32(ICR); 4921 4922 reg = er32(KABGTXD); 4923 reg |= E1000_KABGTXD_BGSQLBIAS; 4924 ew32(KABGTXD, reg); 4925 4926 return 0; 4927 } 4928 4929 /** 4930 * e1000_init_hw_ich8lan - Initialize the hardware 4931 * @hw: pointer to the HW structure 4932 * 4933 * Prepares the hardware for transmit and receive by doing the following: 4934 * - initialize hardware bits 4935 * - initialize LED identification 4936 * - setup receive address registers 4937 * - setup flow control 4938 * - setup transmit descriptors 4939 * - clear statistics 4940 **/ 4941 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4942 { 4943 struct e1000_mac_info *mac = &hw->mac; 4944 u32 ctrl_ext, txdctl, snoop, fflt_dbg; 4945 s32 ret_val; 4946 u16 i; 4947 4948 e1000_initialize_hw_bits_ich8lan(hw); 4949 if (hw->mac.type >= e1000_pch_mtp) { 4950 ret_val = hw->phy.ops.acquire(hw); 4951 if (ret_val) 4952 return ret_val; 4953 4954 ret_val = e1000_reconfigure_k1_exit_timeout(hw); 4955 hw->phy.ops.release(hw); 4956 if (ret_val) { 4957 e_dbg("Error failed to reconfigure K1 exit timeout\n"); 4958 return ret_val; 4959 } 4960 } 4961 4962 /* Initialize identification LED */ 4963 ret_val = mac->ops.id_led_init(hw); 4964 /* An error is not fatal and we should not stop init due to this */ 4965 if (ret_val) 4966 e_dbg("Error initializing identification LED\n"); 4967 4968 /* Setup the receive address. */ 4969 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4970 4971 /* Zero out the Multicast HASH table */ 4972 e_dbg("Zeroing the MTA\n"); 4973 for (i = 0; i < mac->mta_reg_count; i++) 4974 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4975 4976 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4977 * the ME. Disable wakeup by clearing the host wakeup bit. 4978 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4979 */ 4980 if (hw->phy.type == e1000_phy_82578) { 4981 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4982 i &= ~BM_WUC_HOST_WU_BIT; 4983 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 4984 ret_val = e1000_phy_hw_reset_ich8lan(hw); 4985 if (ret_val) 4986 return ret_val; 4987 } 4988 4989 /* Setup link and flow control */ 4990 ret_val = mac->ops.setup_link(hw); 4991 4992 /* Set the transmit descriptor write-back policy for both queues */ 4993 txdctl = er32(TXDCTL(0)); 4994 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4995 E1000_TXDCTL_FULL_TX_DESC_WB); 4996 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4997 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4998 ew32(TXDCTL(0), txdctl); 4999 txdctl = er32(TXDCTL(1)); 5000 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5001 E1000_TXDCTL_FULL_TX_DESC_WB); 5002 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5003 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5004 ew32(TXDCTL(1), txdctl); 5005 5006 /* ICH8 has opposite polarity of no_snoop bits. 5007 * By default, we should use snoop behavior. 5008 */ 5009 if (mac->type == e1000_ich8lan) 5010 snoop = PCIE_ICH8_SNOOP_ALL; 5011 else 5012 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 5013 e1000e_set_pcie_no_snoop(hw, snoop); 5014 5015 /* Enable workaround for packet loss issue on TGP PCH 5016 * Do not gate DMA clock from the modPHY block 5017 */ 5018 if (mac->type >= e1000_pch_tgp) { 5019 fflt_dbg = er32(FFLT_DBG); 5020 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK; 5021 ew32(FFLT_DBG, fflt_dbg); 5022 } 5023 5024 ctrl_ext = er32(CTRL_EXT); 5025 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 5026 ew32(CTRL_EXT, ctrl_ext); 5027 5028 /* Clear all of the statistics registers (clear on read). It is 5029 * important that we do this after we have tried to establish link 5030 * because the symbol error count will increment wildly if there 5031 * is no link. 5032 */ 5033 e1000_clear_hw_cntrs_ich8lan(hw); 5034 5035 return ret_val; 5036 } 5037 5038 /** 5039 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 5040 * @hw: pointer to the HW structure 5041 * 5042 * Sets/Clears required hardware bits necessary for correctly setting up the 5043 * hardware for transmit and receive. 5044 **/ 5045 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 5046 { 5047 u32 reg; 5048 5049 /* Extended Device Control */ 5050 reg = er32(CTRL_EXT); 5051 reg |= BIT(22); 5052 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 5053 if (hw->mac.type >= e1000_pchlan) 5054 reg |= E1000_CTRL_EXT_PHYPDEN; 5055 ew32(CTRL_EXT, reg); 5056 5057 /* Transmit Descriptor Control 0 */ 5058 reg = er32(TXDCTL(0)); 5059 reg |= BIT(22); 5060 ew32(TXDCTL(0), reg); 5061 5062 /* Transmit Descriptor Control 1 */ 5063 reg = er32(TXDCTL(1)); 5064 reg |= BIT(22); 5065 ew32(TXDCTL(1), reg); 5066 5067 /* Transmit Arbitration Control 0 */ 5068 reg = er32(TARC(0)); 5069 if (hw->mac.type == e1000_ich8lan) 5070 reg |= BIT(28) | BIT(29); 5071 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 5072 ew32(TARC(0), reg); 5073 5074 /* Transmit Arbitration Control 1 */ 5075 reg = er32(TARC(1)); 5076 if (er32(TCTL) & E1000_TCTL_MULR) 5077 reg &= ~BIT(28); 5078 else 5079 reg |= BIT(28); 5080 reg |= BIT(24) | BIT(26) | BIT(30); 5081 ew32(TARC(1), reg); 5082 5083 /* Device Status */ 5084 if (hw->mac.type == e1000_ich8lan) { 5085 reg = er32(STATUS); 5086 reg &= ~BIT(31); 5087 ew32(STATUS, reg); 5088 } 5089 5090 /* work-around descriptor data corruption issue during nfs v2 udp 5091 * traffic, just disable the nfs filtering capability 5092 */ 5093 reg = er32(RFCTL); 5094 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 5095 5096 /* Disable IPv6 extension header parsing because some malformed 5097 * IPv6 headers can hang the Rx. 5098 */ 5099 if (hw->mac.type == e1000_ich8lan) 5100 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 5101 ew32(RFCTL, reg); 5102 5103 /* Enable ECC on Lynxpoint */ 5104 if (hw->mac.type >= e1000_pch_lpt) { 5105 reg = er32(PBECCSTS); 5106 reg |= E1000_PBECCSTS_ECC_ENABLE; 5107 ew32(PBECCSTS, reg); 5108 5109 reg = er32(CTRL); 5110 reg |= E1000_CTRL_MEHE; 5111 ew32(CTRL, reg); 5112 } 5113 } 5114 5115 /** 5116 * e1000_setup_link_ich8lan - Setup flow control and link settings 5117 * @hw: pointer to the HW structure 5118 * 5119 * Determines which flow control settings to use, then configures flow 5120 * control. Calls the appropriate media-specific link configuration 5121 * function. Assuming the adapter has a valid link partner, a valid link 5122 * should be established. Assumes the hardware has previously been reset 5123 * and the transmitter and receiver are not enabled. 5124 **/ 5125 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 5126 { 5127 s32 ret_val; 5128 5129 if (hw->phy.ops.check_reset_block(hw)) 5130 return 0; 5131 5132 /* ICH parts do not have a word in the NVM to determine 5133 * the default flow control setting, so we explicitly 5134 * set it to full. 5135 */ 5136 if (hw->fc.requested_mode == e1000_fc_default) { 5137 /* Workaround h/w hang when Tx flow control enabled */ 5138 if (hw->mac.type == e1000_pchlan) 5139 hw->fc.requested_mode = e1000_fc_rx_pause; 5140 else 5141 hw->fc.requested_mode = e1000_fc_full; 5142 } 5143 5144 /* Save off the requested flow control mode for use later. Depending 5145 * on the link partner's capabilities, we may or may not use this mode. 5146 */ 5147 hw->fc.current_mode = hw->fc.requested_mode; 5148 5149 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 5150 5151 /* Continue to configure the copper link. */ 5152 ret_val = hw->mac.ops.setup_physical_interface(hw); 5153 if (ret_val) 5154 return ret_val; 5155 5156 ew32(FCTTV, hw->fc.pause_time); 5157 if ((hw->phy.type == e1000_phy_82578) || 5158 (hw->phy.type == e1000_phy_82579) || 5159 (hw->phy.type == e1000_phy_i217) || 5160 (hw->phy.type == e1000_phy_82577)) { 5161 ew32(FCRTV_PCH, hw->fc.refresh_time); 5162 5163 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 5164 hw->fc.pause_time); 5165 if (ret_val) 5166 return ret_val; 5167 } 5168 5169 return e1000e_set_fc_watermarks(hw); 5170 } 5171 5172 /** 5173 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5174 * @hw: pointer to the HW structure 5175 * 5176 * Configures the kumeran interface to the PHY to wait the appropriate time 5177 * when polling the PHY, then call the generic setup_copper_link to finish 5178 * configuring the copper link. 5179 **/ 5180 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5181 { 5182 u32 ctrl; 5183 s32 ret_val; 5184 u16 reg_data; 5185 5186 ctrl = er32(CTRL); 5187 ctrl |= E1000_CTRL_SLU; 5188 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5189 ew32(CTRL, ctrl); 5190 5191 /* Set the mac to wait the maximum time between each iteration 5192 * and increase the max iterations when polling the phy; 5193 * this fixes erroneous timeouts at 10Mbps. 5194 */ 5195 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 5196 if (ret_val) 5197 return ret_val; 5198 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5199 ®_data); 5200 if (ret_val) 5201 return ret_val; 5202 reg_data |= 0x3F; 5203 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5204 reg_data); 5205 if (ret_val) 5206 return ret_val; 5207 5208 switch (hw->phy.type) { 5209 case e1000_phy_igp_3: 5210 ret_val = e1000e_copper_link_setup_igp(hw); 5211 if (ret_val) 5212 return ret_val; 5213 break; 5214 case e1000_phy_bm: 5215 case e1000_phy_82578: 5216 ret_val = e1000e_copper_link_setup_m88(hw); 5217 if (ret_val) 5218 return ret_val; 5219 break; 5220 case e1000_phy_82577: 5221 case e1000_phy_82579: 5222 ret_val = e1000_copper_link_setup_82577(hw); 5223 if (ret_val) 5224 return ret_val; 5225 break; 5226 case e1000_phy_ife: 5227 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5228 if (ret_val) 5229 return ret_val; 5230 5231 reg_data &= ~IFE_PMC_AUTO_MDIX; 5232 5233 switch (hw->phy.mdix) { 5234 case 1: 5235 reg_data &= ~IFE_PMC_FORCE_MDIX; 5236 break; 5237 case 2: 5238 reg_data |= IFE_PMC_FORCE_MDIX; 5239 break; 5240 case 0: 5241 default: 5242 reg_data |= IFE_PMC_AUTO_MDIX; 5243 break; 5244 } 5245 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5246 if (ret_val) 5247 return ret_val; 5248 break; 5249 default: 5250 break; 5251 } 5252 5253 return e1000e_setup_copper_link(hw); 5254 } 5255 5256 /** 5257 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5258 * @hw: pointer to the HW structure 5259 * 5260 * Calls the PHY specific link setup function and then calls the 5261 * generic setup_copper_link to finish configuring the link for 5262 * Lynxpoint PCH devices 5263 **/ 5264 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5265 { 5266 u32 ctrl; 5267 s32 ret_val; 5268 5269 ctrl = er32(CTRL); 5270 ctrl |= E1000_CTRL_SLU; 5271 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5272 ew32(CTRL, ctrl); 5273 5274 ret_val = e1000_copper_link_setup_82577(hw); 5275 if (ret_val) 5276 return ret_val; 5277 5278 return e1000e_setup_copper_link(hw); 5279 } 5280 5281 /** 5282 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5283 * @hw: pointer to the HW structure 5284 * @speed: pointer to store current link speed 5285 * @duplex: pointer to store the current link duplex 5286 * 5287 * Calls the generic get_speed_and_duplex to retrieve the current link 5288 * information and then calls the Kumeran lock loss workaround for links at 5289 * gigabit speeds. 5290 **/ 5291 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5292 u16 *duplex) 5293 { 5294 s32 ret_val; 5295 5296 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5297 if (ret_val) 5298 return ret_val; 5299 5300 if ((hw->mac.type == e1000_ich8lan) && 5301 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5302 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5303 } 5304 5305 return ret_val; 5306 } 5307 5308 /** 5309 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5310 * @hw: pointer to the HW structure 5311 * 5312 * Work-around for 82566 Kumeran PCS lock loss: 5313 * On link status change (i.e. PCI reset, speed change) and link is up and 5314 * speed is gigabit- 5315 * 0) if workaround is optionally disabled do nothing 5316 * 1) wait 1ms for Kumeran link to come up 5317 * 2) check Kumeran Diagnostic register PCS lock loss bit 5318 * 3) if not set the link is locked (all is good), otherwise... 5319 * 4) reset the PHY 5320 * 5) repeat up to 10 times 5321 * Note: this is only called for IGP3 copper when speed is 1gb. 5322 **/ 5323 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5324 { 5325 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5326 u32 phy_ctrl; 5327 s32 ret_val; 5328 u16 i, data; 5329 bool link; 5330 5331 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5332 return 0; 5333 5334 /* Make sure link is up before proceeding. If not just return. 5335 * Attempting this while link is negotiating fouled up link 5336 * stability 5337 */ 5338 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5339 if (!link) 5340 return 0; 5341 5342 for (i = 0; i < 10; i++) { 5343 /* read once to clear */ 5344 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5345 if (ret_val) 5346 return ret_val; 5347 /* and again to get new status */ 5348 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5349 if (ret_val) 5350 return ret_val; 5351 5352 /* check for PCS lock */ 5353 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5354 return 0; 5355 5356 /* Issue PHY reset */ 5357 e1000_phy_hw_reset(hw); 5358 mdelay(5); 5359 } 5360 /* Disable GigE link negotiation */ 5361 phy_ctrl = er32(PHY_CTRL); 5362 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5363 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5364 ew32(PHY_CTRL, phy_ctrl); 5365 5366 /* Call gig speed drop workaround on Gig disable before accessing 5367 * any PHY registers 5368 */ 5369 e1000e_gig_downshift_workaround_ich8lan(hw); 5370 5371 /* unable to acquire PCS lock */ 5372 return -E1000_ERR_PHY; 5373 } 5374 5375 /** 5376 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5377 * @hw: pointer to the HW structure 5378 * @state: boolean value used to set the current Kumeran workaround state 5379 * 5380 * If ICH8, set the current Kumeran workaround state (enabled - true 5381 * /disabled - false). 5382 **/ 5383 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5384 bool state) 5385 { 5386 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5387 5388 if (hw->mac.type != e1000_ich8lan) { 5389 e_dbg("Workaround applies to ICH8 only.\n"); 5390 return; 5391 } 5392 5393 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5394 } 5395 5396 /** 5397 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5398 * @hw: pointer to the HW structure 5399 * 5400 * Workaround for 82566 power-down on D3 entry: 5401 * 1) disable gigabit link 5402 * 2) write VR power-down enable 5403 * 3) read it back 5404 * Continue if successful, else issue LCD reset and repeat 5405 **/ 5406 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5407 { 5408 u32 reg; 5409 u16 data; 5410 u8 retry = 0; 5411 5412 if (hw->phy.type != e1000_phy_igp_3) 5413 return; 5414 5415 /* Try the workaround twice (if needed) */ 5416 do { 5417 /* Disable link */ 5418 reg = er32(PHY_CTRL); 5419 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5420 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5421 ew32(PHY_CTRL, reg); 5422 5423 /* Call gig speed drop workaround on Gig disable before 5424 * accessing any PHY registers 5425 */ 5426 if (hw->mac.type == e1000_ich8lan) 5427 e1000e_gig_downshift_workaround_ich8lan(hw); 5428 5429 /* Write VR power-down enable */ 5430 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5431 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5432 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5433 5434 /* Read it back and test */ 5435 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5436 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5437 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5438 break; 5439 5440 /* Issue PHY reset and repeat at most one more time */ 5441 reg = er32(CTRL); 5442 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5443 retry++; 5444 } while (retry); 5445 } 5446 5447 /** 5448 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5449 * @hw: pointer to the HW structure 5450 * 5451 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5452 * LPLU, Gig disable, MDIC PHY reset): 5453 * 1) Set Kumeran Near-end loopback 5454 * 2) Clear Kumeran Near-end loopback 5455 * Should only be called for ICH8[m] devices with any 1G Phy. 5456 **/ 5457 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5458 { 5459 s32 ret_val; 5460 u16 reg_data; 5461 5462 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5463 return; 5464 5465 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5466 ®_data); 5467 if (ret_val) 5468 return; 5469 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5470 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5471 reg_data); 5472 if (ret_val) 5473 return; 5474 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5475 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5476 } 5477 5478 /** 5479 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5480 * @hw: pointer to the HW structure 5481 * 5482 * During S0 to Sx transition, it is possible the link remains at gig 5483 * instead of negotiating to a lower speed. Before going to Sx, set 5484 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5485 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5486 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5487 * needs to be written. 5488 * Parts that support (and are linked to a partner which support) EEE in 5489 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5490 * than 10Mbps w/o EEE. 5491 **/ 5492 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5493 { 5494 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5495 u32 phy_ctrl; 5496 s32 ret_val; 5497 5498 phy_ctrl = er32(PHY_CTRL); 5499 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5500 5501 if (hw->phy.type == e1000_phy_i217) { 5502 u16 phy_reg, device_id = hw->adapter->pdev->device; 5503 5504 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5505 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5506 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5507 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5508 (hw->mac.type >= e1000_pch_spt)) { 5509 u32 fextnvm6 = er32(FEXTNVM6); 5510 5511 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5512 } 5513 5514 ret_val = hw->phy.ops.acquire(hw); 5515 if (ret_val) 5516 goto out; 5517 5518 if (!dev_spec->eee_disable) { 5519 u16 eee_advert; 5520 5521 ret_val = 5522 e1000_read_emi_reg_locked(hw, 5523 I217_EEE_ADVERTISEMENT, 5524 &eee_advert); 5525 if (ret_val) 5526 goto release; 5527 5528 /* Disable LPLU if both link partners support 100BaseT 5529 * EEE and 100Full is advertised on both ends of the 5530 * link, and enable Auto Enable LPI since there will 5531 * be no driver to enable LPI while in Sx. 5532 */ 5533 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5534 (dev_spec->eee_lp_ability & 5535 I82579_EEE_100_SUPPORTED) && 5536 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5537 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5538 E1000_PHY_CTRL_NOND0A_LPLU); 5539 5540 /* Set Auto Enable LPI after link up */ 5541 e1e_rphy_locked(hw, 5542 I217_LPI_GPIO_CTRL, &phy_reg); 5543 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5544 e1e_wphy_locked(hw, 5545 I217_LPI_GPIO_CTRL, phy_reg); 5546 } 5547 } 5548 5549 /* For i217 Intel Rapid Start Technology support, 5550 * when the system is going into Sx and no manageability engine 5551 * is present, the driver must configure proxy to reset only on 5552 * power good. LPI (Low Power Idle) state must also reset only 5553 * on power good, as well as the MTA (Multicast table array). 5554 * The SMBus release must also be disabled on LCD reset. 5555 */ 5556 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5557 /* Enable proxy to reset only on power good. */ 5558 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5559 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5560 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5561 5562 /* Set bit enable LPI (EEE) to reset only on 5563 * power good. 5564 */ 5565 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5566 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5567 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5568 5569 /* Disable the SMB release on LCD reset. */ 5570 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5571 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5572 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5573 } 5574 5575 /* Enable MTA to reset for Intel Rapid Start Technology 5576 * Support 5577 */ 5578 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5579 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5580 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5581 5582 release: 5583 hw->phy.ops.release(hw); 5584 } 5585 out: 5586 ew32(PHY_CTRL, phy_ctrl); 5587 5588 if (hw->mac.type == e1000_ich8lan) 5589 e1000e_gig_downshift_workaround_ich8lan(hw); 5590 5591 if (hw->mac.type >= e1000_pchlan) { 5592 e1000_oem_bits_config_ich8lan(hw, false); 5593 5594 /* Reset PHY to activate OEM bits on 82577/8 */ 5595 if (hw->mac.type == e1000_pchlan) 5596 e1000e_phy_hw_reset_generic(hw); 5597 5598 ret_val = hw->phy.ops.acquire(hw); 5599 if (ret_val) 5600 return; 5601 e1000_write_smbus_addr(hw); 5602 hw->phy.ops.release(hw); 5603 } 5604 } 5605 5606 /** 5607 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5608 * @hw: pointer to the HW structure 5609 * 5610 * During Sx to S0 transitions on non-managed devices or managed devices 5611 * on which PHY resets are not blocked, if the PHY registers cannot be 5612 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5613 * the PHY. 5614 * On i217, setup Intel Rapid Start Technology. 5615 **/ 5616 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5617 { 5618 s32 ret_val; 5619 5620 if (hw->mac.type < e1000_pch2lan) 5621 return; 5622 5623 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5624 if (ret_val) { 5625 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5626 return; 5627 } 5628 5629 /* For i217 Intel Rapid Start Technology support when the system 5630 * is transitioning from Sx and no manageability engine is present 5631 * configure SMBus to restore on reset, disable proxy, and enable 5632 * the reset on MTA (Multicast table array). 5633 */ 5634 if (hw->phy.type == e1000_phy_i217) { 5635 u16 phy_reg; 5636 5637 ret_val = hw->phy.ops.acquire(hw); 5638 if (ret_val) { 5639 e_dbg("Failed to setup iRST\n"); 5640 return; 5641 } 5642 5643 /* Clear Auto Enable LPI after link up */ 5644 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5645 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5646 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5647 5648 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5649 /* Restore clear on SMB if no manageability engine 5650 * is present 5651 */ 5652 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5653 if (ret_val) 5654 goto release; 5655 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5656 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5657 5658 /* Disable Proxy */ 5659 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5660 } 5661 /* Enable reset on MTA */ 5662 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5663 if (ret_val) 5664 goto release; 5665 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5666 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5667 release: 5668 if (ret_val) 5669 e_dbg("Error %d in resume workarounds\n", ret_val); 5670 hw->phy.ops.release(hw); 5671 } 5672 } 5673 5674 /** 5675 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5676 * @hw: pointer to the HW structure 5677 * 5678 * Return the LED back to the default configuration. 5679 **/ 5680 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5681 { 5682 if (hw->phy.type == e1000_phy_ife) 5683 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5684 5685 ew32(LEDCTL, hw->mac.ledctl_default); 5686 return 0; 5687 } 5688 5689 /** 5690 * e1000_led_on_ich8lan - Turn LEDs on 5691 * @hw: pointer to the HW structure 5692 * 5693 * Turn on the LEDs. 5694 **/ 5695 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5696 { 5697 if (hw->phy.type == e1000_phy_ife) 5698 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5699 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5700 5701 ew32(LEDCTL, hw->mac.ledctl_mode2); 5702 return 0; 5703 } 5704 5705 /** 5706 * e1000_led_off_ich8lan - Turn LEDs off 5707 * @hw: pointer to the HW structure 5708 * 5709 * Turn off the LEDs. 5710 **/ 5711 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5712 { 5713 if (hw->phy.type == e1000_phy_ife) 5714 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5715 (IFE_PSCL_PROBE_MODE | 5716 IFE_PSCL_PROBE_LEDS_OFF)); 5717 5718 ew32(LEDCTL, hw->mac.ledctl_mode1); 5719 return 0; 5720 } 5721 5722 /** 5723 * e1000_setup_led_pchlan - Configures SW controllable LED 5724 * @hw: pointer to the HW structure 5725 * 5726 * This prepares the SW controllable LED for use. 5727 **/ 5728 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5729 { 5730 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5731 } 5732 5733 /** 5734 * e1000_cleanup_led_pchlan - Restore the default LED operation 5735 * @hw: pointer to the HW structure 5736 * 5737 * Return the LED back to the default configuration. 5738 **/ 5739 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5740 { 5741 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5742 } 5743 5744 /** 5745 * e1000_led_on_pchlan - Turn LEDs on 5746 * @hw: pointer to the HW structure 5747 * 5748 * Turn on the LEDs. 5749 **/ 5750 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5751 { 5752 u16 data = (u16)hw->mac.ledctl_mode2; 5753 u32 i, led; 5754 5755 /* If no link, then turn LED on by setting the invert bit 5756 * for each LED that's mode is "link_up" in ledctl_mode2. 5757 */ 5758 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5759 for (i = 0; i < 3; i++) { 5760 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5761 if ((led & E1000_PHY_LED0_MODE_MASK) != 5762 E1000_LEDCTL_MODE_LINK_UP) 5763 continue; 5764 if (led & E1000_PHY_LED0_IVRT) 5765 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5766 else 5767 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5768 } 5769 } 5770 5771 return e1e_wphy(hw, HV_LED_CONFIG, data); 5772 } 5773 5774 /** 5775 * e1000_led_off_pchlan - Turn LEDs off 5776 * @hw: pointer to the HW structure 5777 * 5778 * Turn off the LEDs. 5779 **/ 5780 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5781 { 5782 u16 data = (u16)hw->mac.ledctl_mode1; 5783 u32 i, led; 5784 5785 /* If no link, then turn LED off by clearing the invert bit 5786 * for each LED that's mode is "link_up" in ledctl_mode1. 5787 */ 5788 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5789 for (i = 0; i < 3; i++) { 5790 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5791 if ((led & E1000_PHY_LED0_MODE_MASK) != 5792 E1000_LEDCTL_MODE_LINK_UP) 5793 continue; 5794 if (led & E1000_PHY_LED0_IVRT) 5795 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5796 else 5797 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5798 } 5799 } 5800 5801 return e1e_wphy(hw, HV_LED_CONFIG, data); 5802 } 5803 5804 /** 5805 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5806 * @hw: pointer to the HW structure 5807 * 5808 * Read appropriate register for the config done bit for completion status 5809 * and configure the PHY through s/w for EEPROM-less parts. 5810 * 5811 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5812 * config done bit, so only an error is logged and continues. If we were 5813 * to return with error, EEPROM-less silicon would not be able to be reset 5814 * or change link. 5815 **/ 5816 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5817 { 5818 s32 ret_val = 0; 5819 u32 bank = 0; 5820 u32 status; 5821 5822 e1000e_get_cfg_done_generic(hw); 5823 5824 /* Wait for indication from h/w that it has completed basic config */ 5825 if (hw->mac.type >= e1000_ich10lan) { 5826 e1000_lan_init_done_ich8lan(hw); 5827 } else { 5828 ret_val = e1000e_get_auto_rd_done(hw); 5829 if (ret_val) { 5830 /* When auto config read does not complete, do not 5831 * return with an error. This can happen in situations 5832 * where there is no eeprom and prevents getting link. 5833 */ 5834 e_dbg("Auto Read Done did not complete\n"); 5835 ret_val = 0; 5836 } 5837 } 5838 5839 /* Clear PHY Reset Asserted bit */ 5840 status = er32(STATUS); 5841 if (status & E1000_STATUS_PHYRA) 5842 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5843 else 5844 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5845 5846 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5847 if (hw->mac.type <= e1000_ich9lan) { 5848 if (!(er32(EECD) & E1000_EECD_PRES) && 5849 (hw->phy.type == e1000_phy_igp_3)) { 5850 e1000e_phy_init_script_igp3(hw); 5851 } 5852 } else { 5853 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5854 /* Maybe we should do a basic PHY config */ 5855 e_dbg("EEPROM not present\n"); 5856 ret_val = -E1000_ERR_CONFIG; 5857 } 5858 } 5859 5860 return ret_val; 5861 } 5862 5863 /** 5864 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5865 * @hw: pointer to the HW structure 5866 * 5867 * In the case of a PHY power down to save power, or to turn off link during a 5868 * driver unload, or wake on lan is not enabled, remove the link. 5869 **/ 5870 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5871 { 5872 /* If the management interface is not enabled, then power down */ 5873 if (!(hw->mac.ops.check_mng_mode(hw) || 5874 hw->phy.ops.check_reset_block(hw))) 5875 e1000_power_down_phy_copper(hw); 5876 } 5877 5878 /** 5879 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5880 * @hw: pointer to the HW structure 5881 * 5882 * Clears hardware counters specific to the silicon family and calls 5883 * clear_hw_cntrs_generic to clear all general purpose counters. 5884 **/ 5885 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5886 { 5887 u16 phy_data; 5888 s32 ret_val; 5889 5890 e1000e_clear_hw_cntrs_base(hw); 5891 5892 er32(ALGNERRC); 5893 er32(RXERRC); 5894 er32(TNCRS); 5895 er32(CEXTERR); 5896 er32(TSCTC); 5897 er32(TSCTFC); 5898 5899 er32(MGTPRC); 5900 er32(MGTPDC); 5901 er32(MGTPTC); 5902 5903 er32(IAC); 5904 er32(ICRXOC); 5905 5906 /* Clear PHY statistics registers */ 5907 if ((hw->phy.type == e1000_phy_82578) || 5908 (hw->phy.type == e1000_phy_82579) || 5909 (hw->phy.type == e1000_phy_i217) || 5910 (hw->phy.type == e1000_phy_82577)) { 5911 ret_val = hw->phy.ops.acquire(hw); 5912 if (ret_val) 5913 return; 5914 ret_val = hw->phy.ops.set_page(hw, 5915 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5916 if (ret_val) 5917 goto release; 5918 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5919 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5920 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5921 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5922 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5923 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5924 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5925 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5926 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5927 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5928 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5929 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5930 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5931 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5932 release: 5933 hw->phy.ops.release(hw); 5934 } 5935 } 5936 5937 static const struct e1000_mac_operations ich8_mac_ops = { 5938 /* check_mng_mode dependent on mac type */ 5939 .check_for_link = e1000_check_for_copper_link_ich8lan, 5940 /* cleanup_led dependent on mac type */ 5941 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5942 .get_bus_info = e1000_get_bus_info_ich8lan, 5943 .set_lan_id = e1000_set_lan_id_single_port, 5944 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5945 /* led_on dependent on mac type */ 5946 /* led_off dependent on mac type */ 5947 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5948 .reset_hw = e1000_reset_hw_ich8lan, 5949 .init_hw = e1000_init_hw_ich8lan, 5950 .setup_link = e1000_setup_link_ich8lan, 5951 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5952 /* id_led_init dependent on mac type */ 5953 .config_collision_dist = e1000e_config_collision_dist_generic, 5954 .rar_set = e1000e_rar_set_generic, 5955 .rar_get_count = e1000e_rar_get_count_generic, 5956 }; 5957 5958 static const struct e1000_phy_operations ich8_phy_ops = { 5959 .acquire = e1000_acquire_swflag_ich8lan, 5960 .check_reset_block = e1000_check_reset_block_ich8lan, 5961 .commit = NULL, 5962 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5963 .get_cable_length = e1000e_get_cable_length_igp_2, 5964 .read_reg = e1000e_read_phy_reg_igp, 5965 .release = e1000_release_swflag_ich8lan, 5966 .reset = e1000_phy_hw_reset_ich8lan, 5967 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5968 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5969 .write_reg = e1000e_write_phy_reg_igp, 5970 }; 5971 5972 static const struct e1000_nvm_operations ich8_nvm_ops = { 5973 .acquire = e1000_acquire_nvm_ich8lan, 5974 .read = e1000_read_nvm_ich8lan, 5975 .release = e1000_release_nvm_ich8lan, 5976 .reload = e1000e_reload_nvm_generic, 5977 .update = e1000_update_nvm_checksum_ich8lan, 5978 .valid_led_default = e1000_valid_led_default_ich8lan, 5979 .validate = e1000_validate_nvm_checksum_ich8lan, 5980 .write = e1000_write_nvm_ich8lan, 5981 }; 5982 5983 static const struct e1000_nvm_operations spt_nvm_ops = { 5984 .acquire = e1000_acquire_nvm_ich8lan, 5985 .release = e1000_release_nvm_ich8lan, 5986 .read = e1000_read_nvm_spt, 5987 .update = e1000_update_nvm_checksum_spt, 5988 .reload = e1000e_reload_nvm_generic, 5989 .valid_led_default = e1000_valid_led_default_ich8lan, 5990 .validate = e1000_validate_nvm_checksum_ich8lan, 5991 .write = e1000_write_nvm_ich8lan, 5992 }; 5993 5994 const struct e1000_info e1000_ich8_info = { 5995 .mac = e1000_ich8lan, 5996 .flags = FLAG_HAS_WOL 5997 | FLAG_IS_ICH 5998 | FLAG_HAS_CTRLEXT_ON_LOAD 5999 | FLAG_HAS_AMT 6000 | FLAG_HAS_FLASH 6001 | FLAG_APME_IN_WUC, 6002 .pba = 8, 6003 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 6004 .get_variants = e1000_get_variants_ich8lan, 6005 .mac_ops = &ich8_mac_ops, 6006 .phy_ops = &ich8_phy_ops, 6007 .nvm_ops = &ich8_nvm_ops, 6008 }; 6009 6010 const struct e1000_info e1000_ich9_info = { 6011 .mac = e1000_ich9lan, 6012 .flags = FLAG_HAS_JUMBO_FRAMES 6013 | FLAG_IS_ICH 6014 | FLAG_HAS_WOL 6015 | FLAG_HAS_CTRLEXT_ON_LOAD 6016 | FLAG_HAS_AMT 6017 | FLAG_HAS_FLASH 6018 | FLAG_APME_IN_WUC, 6019 .pba = 18, 6020 .max_hw_frame_size = DEFAULT_JUMBO, 6021 .get_variants = e1000_get_variants_ich8lan, 6022 .mac_ops = &ich8_mac_ops, 6023 .phy_ops = &ich8_phy_ops, 6024 .nvm_ops = &ich8_nvm_ops, 6025 }; 6026 6027 const struct e1000_info e1000_ich10_info = { 6028 .mac = e1000_ich10lan, 6029 .flags = FLAG_HAS_JUMBO_FRAMES 6030 | FLAG_IS_ICH 6031 | FLAG_HAS_WOL 6032 | FLAG_HAS_CTRLEXT_ON_LOAD 6033 | FLAG_HAS_AMT 6034 | FLAG_HAS_FLASH 6035 | FLAG_APME_IN_WUC, 6036 .pba = 18, 6037 .max_hw_frame_size = DEFAULT_JUMBO, 6038 .get_variants = e1000_get_variants_ich8lan, 6039 .mac_ops = &ich8_mac_ops, 6040 .phy_ops = &ich8_phy_ops, 6041 .nvm_ops = &ich8_nvm_ops, 6042 }; 6043 6044 const struct e1000_info e1000_pch_info = { 6045 .mac = e1000_pchlan, 6046 .flags = FLAG_IS_ICH 6047 | FLAG_HAS_WOL 6048 | FLAG_HAS_CTRLEXT_ON_LOAD 6049 | FLAG_HAS_AMT 6050 | FLAG_HAS_FLASH 6051 | FLAG_HAS_JUMBO_FRAMES 6052 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 6053 | FLAG_APME_IN_WUC, 6054 .flags2 = FLAG2_HAS_PHY_STATS, 6055 .pba = 26, 6056 .max_hw_frame_size = 4096, 6057 .get_variants = e1000_get_variants_ich8lan, 6058 .mac_ops = &ich8_mac_ops, 6059 .phy_ops = &ich8_phy_ops, 6060 .nvm_ops = &ich8_nvm_ops, 6061 }; 6062 6063 const struct e1000_info e1000_pch2_info = { 6064 .mac = e1000_pch2lan, 6065 .flags = FLAG_IS_ICH 6066 | FLAG_HAS_WOL 6067 | FLAG_HAS_HW_TIMESTAMP 6068 | FLAG_HAS_CTRLEXT_ON_LOAD 6069 | FLAG_HAS_AMT 6070 | FLAG_HAS_FLASH 6071 | FLAG_HAS_JUMBO_FRAMES 6072 | FLAG_APME_IN_WUC, 6073 .flags2 = FLAG2_HAS_PHY_STATS 6074 | FLAG2_HAS_EEE 6075 | FLAG2_CHECK_SYSTIM_OVERFLOW, 6076 .pba = 26, 6077 .max_hw_frame_size = 9022, 6078 .get_variants = e1000_get_variants_ich8lan, 6079 .mac_ops = &ich8_mac_ops, 6080 .phy_ops = &ich8_phy_ops, 6081 .nvm_ops = &ich8_nvm_ops, 6082 }; 6083 6084 const struct e1000_info e1000_pch_lpt_info = { 6085 .mac = e1000_pch_lpt, 6086 .flags = FLAG_IS_ICH 6087 | FLAG_HAS_WOL 6088 | FLAG_HAS_HW_TIMESTAMP 6089 | FLAG_HAS_CTRLEXT_ON_LOAD 6090 | FLAG_HAS_AMT 6091 | FLAG_HAS_FLASH 6092 | FLAG_HAS_JUMBO_FRAMES 6093 | FLAG_APME_IN_WUC, 6094 .flags2 = FLAG2_HAS_PHY_STATS 6095 | FLAG2_HAS_EEE 6096 | FLAG2_CHECK_SYSTIM_OVERFLOW, 6097 .pba = 26, 6098 .max_hw_frame_size = 9022, 6099 .get_variants = e1000_get_variants_ich8lan, 6100 .mac_ops = &ich8_mac_ops, 6101 .phy_ops = &ich8_phy_ops, 6102 .nvm_ops = &ich8_nvm_ops, 6103 }; 6104 6105 const struct e1000_info e1000_pch_spt_info = { 6106 .mac = e1000_pch_spt, 6107 .flags = FLAG_IS_ICH 6108 | FLAG_HAS_WOL 6109 | FLAG_HAS_HW_TIMESTAMP 6110 | FLAG_HAS_CTRLEXT_ON_LOAD 6111 | FLAG_HAS_AMT 6112 | FLAG_HAS_FLASH 6113 | FLAG_HAS_JUMBO_FRAMES 6114 | FLAG_APME_IN_WUC, 6115 .flags2 = FLAG2_HAS_PHY_STATS 6116 | FLAG2_HAS_EEE, 6117 .pba = 26, 6118 .max_hw_frame_size = 9022, 6119 .get_variants = e1000_get_variants_ich8lan, 6120 .mac_ops = &ich8_mac_ops, 6121 .phy_ops = &ich8_phy_ops, 6122 .nvm_ops = &spt_nvm_ops, 6123 }; 6124 6125 const struct e1000_info e1000_pch_cnp_info = { 6126 .mac = e1000_pch_cnp, 6127 .flags = FLAG_IS_ICH 6128 | FLAG_HAS_WOL 6129 | FLAG_HAS_HW_TIMESTAMP 6130 | FLAG_HAS_CTRLEXT_ON_LOAD 6131 | FLAG_HAS_AMT 6132 | FLAG_HAS_FLASH 6133 | FLAG_HAS_JUMBO_FRAMES 6134 | FLAG_APME_IN_WUC, 6135 .flags2 = FLAG2_HAS_PHY_STATS 6136 | FLAG2_HAS_EEE, 6137 .pba = 26, 6138 .max_hw_frame_size = 9022, 6139 .get_variants = e1000_get_variants_ich8lan, 6140 .mac_ops = &ich8_mac_ops, 6141 .phy_ops = &ich8_phy_ops, 6142 .nvm_ops = &spt_nvm_ops, 6143 }; 6144 6145 const struct e1000_info e1000_pch_tgp_info = { 6146 .mac = e1000_pch_tgp, 6147 .flags = FLAG_IS_ICH 6148 | FLAG_HAS_WOL 6149 | FLAG_HAS_HW_TIMESTAMP 6150 | FLAG_HAS_CTRLEXT_ON_LOAD 6151 | FLAG_HAS_AMT 6152 | FLAG_HAS_FLASH 6153 | FLAG_HAS_JUMBO_FRAMES 6154 | FLAG_APME_IN_WUC, 6155 .flags2 = FLAG2_HAS_PHY_STATS 6156 | FLAG2_HAS_EEE, 6157 .pba = 26, 6158 .max_hw_frame_size = 9022, 6159 .get_variants = e1000_get_variants_ich8lan, 6160 .mac_ops = &ich8_mac_ops, 6161 .phy_ops = &ich8_phy_ops, 6162 .nvm_ops = &spt_nvm_ops, 6163 }; 6164 6165 const struct e1000_info e1000_pch_adp_info = { 6166 .mac = e1000_pch_adp, 6167 .flags = FLAG_IS_ICH 6168 | FLAG_HAS_WOL 6169 | FLAG_HAS_HW_TIMESTAMP 6170 | FLAG_HAS_CTRLEXT_ON_LOAD 6171 | FLAG_HAS_AMT 6172 | FLAG_HAS_FLASH 6173 | FLAG_HAS_JUMBO_FRAMES 6174 | FLAG_APME_IN_WUC, 6175 .flags2 = FLAG2_HAS_PHY_STATS 6176 | FLAG2_HAS_EEE, 6177 .pba = 26, 6178 .max_hw_frame_size = 9022, 6179 .get_variants = e1000_get_variants_ich8lan, 6180 .mac_ops = &ich8_mac_ops, 6181 .phy_ops = &ich8_phy_ops, 6182 .nvm_ops = &spt_nvm_ops, 6183 }; 6184 6185 const struct e1000_info e1000_pch_mtp_info = { 6186 .mac = e1000_pch_mtp, 6187 .flags = FLAG_IS_ICH 6188 | FLAG_HAS_WOL 6189 | FLAG_HAS_HW_TIMESTAMP 6190 | FLAG_HAS_CTRLEXT_ON_LOAD 6191 | FLAG_HAS_AMT 6192 | FLAG_HAS_FLASH 6193 | FLAG_HAS_JUMBO_FRAMES 6194 | FLAG_APME_IN_WUC, 6195 .flags2 = FLAG2_HAS_PHY_STATS 6196 | FLAG2_HAS_EEE, 6197 .pba = 26, 6198 .max_hw_frame_size = 9022, 6199 .get_variants = e1000_get_variants_ich8lan, 6200 .mac_ops = &ich8_mac_ops, 6201 .phy_ops = &ich8_phy_ops, 6202 .nvm_ops = &spt_nvm_ops, 6203 }; 6204