1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _E1000_HW_H_ 30 #define _E1000_HW_H_ 31 32 #include "regs.h" 33 #include "defines.h" 34 35 struct e1000_hw; 36 37 #define E1000_DEV_ID_82571EB_COPPER 0x105E 38 #define E1000_DEV_ID_82571EB_FIBER 0x105F 39 #define E1000_DEV_ID_82571EB_SERDES 0x1060 40 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 41 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 42 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 43 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 44 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 45 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 46 #define E1000_DEV_ID_82572EI_COPPER 0x107D 47 #define E1000_DEV_ID_82572EI_FIBER 0x107E 48 #define E1000_DEV_ID_82572EI_SERDES 0x107F 49 #define E1000_DEV_ID_82572EI 0x10B9 50 #define E1000_DEV_ID_82573E 0x108B 51 #define E1000_DEV_ID_82573E_IAMT 0x108C 52 #define E1000_DEV_ID_82573L 0x109A 53 #define E1000_DEV_ID_82574L 0x10D3 54 #define E1000_DEV_ID_82574LA 0x10F6 55 #define E1000_DEV_ID_82583V 0x150C 56 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 57 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 58 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 59 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 60 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 61 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 62 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 63 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 64 #define E1000_DEV_ID_ICH8_IFE 0x104C 65 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 66 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 67 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 68 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 69 #define E1000_DEV_ID_ICH9_BM 0x10E5 70 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 71 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 72 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 73 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 74 #define E1000_DEV_ID_ICH9_IFE 0x10C0 75 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 76 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 77 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 78 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 79 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 80 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 81 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 82 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 83 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 84 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 85 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 86 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 87 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 88 #define E1000_DEV_ID_PCH2_LV_V 0x1503 89 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 90 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 91 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 92 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 93 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 94 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 95 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 96 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 97 98 #define E1000_REVISION_4 4 99 100 #define E1000_FUNC_1 1 101 102 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 103 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 104 105 enum e1000_mac_type { 106 e1000_82571, 107 e1000_82572, 108 e1000_82573, 109 e1000_82574, 110 e1000_82583, 111 e1000_80003es2lan, 112 e1000_ich8lan, 113 e1000_ich9lan, 114 e1000_ich10lan, 115 e1000_pchlan, 116 e1000_pch2lan, 117 e1000_pch_lpt, 118 }; 119 120 enum e1000_media_type { 121 e1000_media_type_unknown = 0, 122 e1000_media_type_copper = 1, 123 e1000_media_type_fiber = 2, 124 e1000_media_type_internal_serdes = 3, 125 e1000_num_media_types 126 }; 127 128 enum e1000_nvm_type { 129 e1000_nvm_unknown = 0, 130 e1000_nvm_none, 131 e1000_nvm_eeprom_spi, 132 e1000_nvm_flash_hw, 133 e1000_nvm_flash_sw 134 }; 135 136 enum e1000_nvm_override { 137 e1000_nvm_override_none = 0, 138 e1000_nvm_override_spi_small, 139 e1000_nvm_override_spi_large 140 }; 141 142 enum e1000_phy_type { 143 e1000_phy_unknown = 0, 144 e1000_phy_none, 145 e1000_phy_m88, 146 e1000_phy_igp, 147 e1000_phy_igp_2, 148 e1000_phy_gg82563, 149 e1000_phy_igp_3, 150 e1000_phy_ife, 151 e1000_phy_bm, 152 e1000_phy_82578, 153 e1000_phy_82577, 154 e1000_phy_82579, 155 e1000_phy_i217, 156 }; 157 158 enum e1000_bus_width { 159 e1000_bus_width_unknown = 0, 160 e1000_bus_width_pcie_x1, 161 e1000_bus_width_pcie_x2, 162 e1000_bus_width_pcie_x4 = 4, 163 e1000_bus_width_32, 164 e1000_bus_width_64, 165 e1000_bus_width_reserved 166 }; 167 168 enum e1000_1000t_rx_status { 169 e1000_1000t_rx_status_not_ok = 0, 170 e1000_1000t_rx_status_ok, 171 e1000_1000t_rx_status_undefined = 0xFF 172 }; 173 174 enum e1000_rev_polarity { 175 e1000_rev_polarity_normal = 0, 176 e1000_rev_polarity_reversed, 177 e1000_rev_polarity_undefined = 0xFF 178 }; 179 180 enum e1000_fc_mode { 181 e1000_fc_none = 0, 182 e1000_fc_rx_pause, 183 e1000_fc_tx_pause, 184 e1000_fc_full, 185 e1000_fc_default = 0xFF 186 }; 187 188 enum e1000_ms_type { 189 e1000_ms_hw_default = 0, 190 e1000_ms_force_master, 191 e1000_ms_force_slave, 192 e1000_ms_auto 193 }; 194 195 enum e1000_smart_speed { 196 e1000_smart_speed_default = 0, 197 e1000_smart_speed_on, 198 e1000_smart_speed_off 199 }; 200 201 enum e1000_serdes_link_state { 202 e1000_serdes_link_down = 0, 203 e1000_serdes_link_autoneg_progress, 204 e1000_serdes_link_autoneg_complete, 205 e1000_serdes_link_forced_up 206 }; 207 208 /* Receive Descriptor - Extended */ 209 union e1000_rx_desc_extended { 210 struct { 211 __le64 buffer_addr; 212 __le64 reserved; 213 } read; 214 struct { 215 struct { 216 __le32 mrq; /* Multiple Rx Queues */ 217 union { 218 __le32 rss; /* RSS Hash */ 219 struct { 220 __le16 ip_id; /* IP id */ 221 __le16 csum; /* Packet Checksum */ 222 } csum_ip; 223 } hi_dword; 224 } lower; 225 struct { 226 __le32 status_error; /* ext status/error */ 227 __le16 length; 228 __le16 vlan; /* VLAN tag */ 229 } upper; 230 } wb; /* writeback */ 231 }; 232 233 #define MAX_PS_BUFFERS 4 234 235 /* Number of packet split data buffers (not including the header buffer) */ 236 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 237 238 /* Receive Descriptor - Packet Split */ 239 union e1000_rx_desc_packet_split { 240 struct { 241 /* one buffer for protocol header(s), three data buffers */ 242 __le64 buffer_addr[MAX_PS_BUFFERS]; 243 } read; 244 struct { 245 struct { 246 __le32 mrq; /* Multiple Rx Queues */ 247 union { 248 __le32 rss; /* RSS Hash */ 249 struct { 250 __le16 ip_id; /* IP id */ 251 __le16 csum; /* Packet Checksum */ 252 } csum_ip; 253 } hi_dword; 254 } lower; 255 struct { 256 __le32 status_error; /* ext status/error */ 257 __le16 length0; /* length of buffer 0 */ 258 __le16 vlan; /* VLAN tag */ 259 } middle; 260 struct { 261 __le16 header_status; 262 /* length of buffers 1-3 */ 263 __le16 length[PS_PAGE_BUFFERS]; 264 } upper; 265 __le64 reserved; 266 } wb; /* writeback */ 267 }; 268 269 /* Transmit Descriptor */ 270 struct e1000_tx_desc { 271 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 272 union { 273 __le32 data; 274 struct { 275 __le16 length; /* Data buffer length */ 276 u8 cso; /* Checksum offset */ 277 u8 cmd; /* Descriptor control */ 278 } flags; 279 } lower; 280 union { 281 __le32 data; 282 struct { 283 u8 status; /* Descriptor status */ 284 u8 css; /* Checksum start */ 285 __le16 special; 286 } fields; 287 } upper; 288 }; 289 290 /* Offload Context Descriptor */ 291 struct e1000_context_desc { 292 union { 293 __le32 ip_config; 294 struct { 295 u8 ipcss; /* IP checksum start */ 296 u8 ipcso; /* IP checksum offset */ 297 __le16 ipcse; /* IP checksum end */ 298 } ip_fields; 299 } lower_setup; 300 union { 301 __le32 tcp_config; 302 struct { 303 u8 tucss; /* TCP checksum start */ 304 u8 tucso; /* TCP checksum offset */ 305 __le16 tucse; /* TCP checksum end */ 306 } tcp_fields; 307 } upper_setup; 308 __le32 cmd_and_length; 309 union { 310 __le32 data; 311 struct { 312 u8 status; /* Descriptor status */ 313 u8 hdr_len; /* Header length */ 314 __le16 mss; /* Maximum segment size */ 315 } fields; 316 } tcp_seg_setup; 317 }; 318 319 /* Offload data descriptor */ 320 struct e1000_data_desc { 321 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 322 union { 323 __le32 data; 324 struct { 325 __le16 length; /* Data buffer length */ 326 u8 typ_len_ext; 327 u8 cmd; 328 } flags; 329 } lower; 330 union { 331 __le32 data; 332 struct { 333 u8 status; /* Descriptor status */ 334 u8 popts; /* Packet Options */ 335 __le16 special; 336 } fields; 337 } upper; 338 }; 339 340 /* Statistics counters collected by the MAC */ 341 struct e1000_hw_stats { 342 u64 crcerrs; 343 u64 algnerrc; 344 u64 symerrs; 345 u64 rxerrc; 346 u64 mpc; 347 u64 scc; 348 u64 ecol; 349 u64 mcc; 350 u64 latecol; 351 u64 colc; 352 u64 dc; 353 u64 tncrs; 354 u64 sec; 355 u64 cexterr; 356 u64 rlec; 357 u64 xonrxc; 358 u64 xontxc; 359 u64 xoffrxc; 360 u64 xofftxc; 361 u64 fcruc; 362 u64 prc64; 363 u64 prc127; 364 u64 prc255; 365 u64 prc511; 366 u64 prc1023; 367 u64 prc1522; 368 u64 gprc; 369 u64 bprc; 370 u64 mprc; 371 u64 gptc; 372 u64 gorc; 373 u64 gotc; 374 u64 rnbc; 375 u64 ruc; 376 u64 rfc; 377 u64 roc; 378 u64 rjc; 379 u64 mgprc; 380 u64 mgpdc; 381 u64 mgptc; 382 u64 tor; 383 u64 tot; 384 u64 tpr; 385 u64 tpt; 386 u64 ptc64; 387 u64 ptc127; 388 u64 ptc255; 389 u64 ptc511; 390 u64 ptc1023; 391 u64 ptc1522; 392 u64 mptc; 393 u64 bptc; 394 u64 tsctc; 395 u64 tsctfc; 396 u64 iac; 397 u64 icrxptc; 398 u64 icrxatc; 399 u64 ictxptc; 400 u64 ictxatc; 401 u64 ictxqec; 402 u64 ictxqmtc; 403 u64 icrxdmtc; 404 u64 icrxoc; 405 }; 406 407 struct e1000_phy_stats { 408 u32 idle_errors; 409 u32 receive_errors; 410 }; 411 412 struct e1000_host_mng_dhcp_cookie { 413 u32 signature; 414 u8 status; 415 u8 reserved0; 416 u16 vlan_id; 417 u32 reserved1; 418 u16 reserved2; 419 u8 reserved3; 420 u8 checksum; 421 }; 422 423 /* Host Interface "Rev 1" */ 424 struct e1000_host_command_header { 425 u8 command_id; 426 u8 command_length; 427 u8 command_options; 428 u8 checksum; 429 }; 430 431 #define E1000_HI_MAX_DATA_LENGTH 252 432 struct e1000_host_command_info { 433 struct e1000_host_command_header command_header; 434 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 435 }; 436 437 /* Host Interface "Rev 2" */ 438 struct e1000_host_mng_command_header { 439 u8 command_id; 440 u8 checksum; 441 u16 reserved1; 442 u16 reserved2; 443 u16 command_length; 444 }; 445 446 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 447 struct e1000_host_mng_command_info { 448 struct e1000_host_mng_command_header command_header; 449 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 450 }; 451 452 #include "mac.h" 453 #include "phy.h" 454 #include "nvm.h" 455 #include "manage.h" 456 457 /* Function pointers for the MAC. */ 458 struct e1000_mac_operations { 459 s32 (*id_led_init)(struct e1000_hw *); 460 s32 (*blink_led)(struct e1000_hw *); 461 bool (*check_mng_mode)(struct e1000_hw *); 462 s32 (*check_for_link)(struct e1000_hw *); 463 s32 (*cleanup_led)(struct e1000_hw *); 464 void (*clear_hw_cntrs)(struct e1000_hw *); 465 void (*clear_vfta)(struct e1000_hw *); 466 s32 (*get_bus_info)(struct e1000_hw *); 467 void (*set_lan_id)(struct e1000_hw *); 468 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 469 s32 (*led_on)(struct e1000_hw *); 470 s32 (*led_off)(struct e1000_hw *); 471 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 472 s32 (*reset_hw)(struct e1000_hw *); 473 s32 (*init_hw)(struct e1000_hw *); 474 s32 (*setup_link)(struct e1000_hw *); 475 s32 (*setup_physical_interface)(struct e1000_hw *); 476 s32 (*setup_led)(struct e1000_hw *); 477 void (*write_vfta)(struct e1000_hw *, u32, u32); 478 void (*config_collision_dist)(struct e1000_hw *); 479 void (*rar_set)(struct e1000_hw *, u8 *, u32); 480 s32 (*read_mac_addr)(struct e1000_hw *); 481 }; 482 483 /* When to use various PHY register access functions: 484 * 485 * Func Caller 486 * Function Does Does When to use 487 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 488 * X_reg L,P,A n/a for simple PHY reg accesses 489 * X_reg_locked P,A L for multiple accesses of different regs 490 * on different pages 491 * X_reg_page A L,P for multiple accesses of different regs 492 * on the same page 493 * 494 * Where X=[read|write], L=locking, P=sets page, A=register access 495 * 496 */ 497 struct e1000_phy_operations { 498 s32 (*acquire)(struct e1000_hw *); 499 s32 (*cfg_on_link_up)(struct e1000_hw *); 500 s32 (*check_polarity)(struct e1000_hw *); 501 s32 (*check_reset_block)(struct e1000_hw *); 502 s32 (*commit)(struct e1000_hw *); 503 s32 (*force_speed_duplex)(struct e1000_hw *); 504 s32 (*get_cfg_done)(struct e1000_hw *hw); 505 s32 (*get_cable_length)(struct e1000_hw *); 506 s32 (*get_info)(struct e1000_hw *); 507 s32 (*set_page)(struct e1000_hw *, u16); 508 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 509 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 510 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 511 void (*release)(struct e1000_hw *); 512 s32 (*reset)(struct e1000_hw *); 513 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 514 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 515 s32 (*write_reg)(struct e1000_hw *, u32, u16); 516 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 517 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 518 void (*power_up)(struct e1000_hw *); 519 void (*power_down)(struct e1000_hw *); 520 }; 521 522 /* Function pointers for the NVM. */ 523 struct e1000_nvm_operations { 524 s32 (*acquire)(struct e1000_hw *); 525 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 526 void (*release)(struct e1000_hw *); 527 void (*reload)(struct e1000_hw *); 528 s32 (*update)(struct e1000_hw *); 529 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 530 s32 (*validate)(struct e1000_hw *); 531 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 532 }; 533 534 struct e1000_mac_info { 535 struct e1000_mac_operations ops; 536 u8 addr[ETH_ALEN]; 537 u8 perm_addr[ETH_ALEN]; 538 539 enum e1000_mac_type type; 540 541 u32 collision_delta; 542 u32 ledctl_default; 543 u32 ledctl_mode1; 544 u32 ledctl_mode2; 545 u32 mc_filter_type; 546 u32 tx_packet_delta; 547 u32 txcw; 548 549 u16 current_ifs_val; 550 u16 ifs_max_val; 551 u16 ifs_min_val; 552 u16 ifs_ratio; 553 u16 ifs_step_size; 554 u16 mta_reg_count; 555 556 /* Maximum size of the MTA register table in all supported adapters */ 557 #define MAX_MTA_REG 128 558 u32 mta_shadow[MAX_MTA_REG]; 559 u16 rar_entry_count; 560 561 u8 forced_speed_duplex; 562 563 bool adaptive_ifs; 564 bool has_fwsm; 565 bool arc_subsystem_valid; 566 bool autoneg; 567 bool autoneg_failed; 568 bool get_link_status; 569 bool in_ifs_mode; 570 bool serdes_has_link; 571 bool tx_pkt_filtering; 572 enum e1000_serdes_link_state serdes_link_state; 573 }; 574 575 struct e1000_phy_info { 576 struct e1000_phy_operations ops; 577 578 enum e1000_phy_type type; 579 580 enum e1000_1000t_rx_status local_rx; 581 enum e1000_1000t_rx_status remote_rx; 582 enum e1000_ms_type ms_type; 583 enum e1000_ms_type original_ms_type; 584 enum e1000_rev_polarity cable_polarity; 585 enum e1000_smart_speed smart_speed; 586 587 u32 addr; 588 u32 id; 589 u32 reset_delay_us; /* in usec */ 590 u32 revision; 591 592 enum e1000_media_type media_type; 593 594 u16 autoneg_advertised; 595 u16 autoneg_mask; 596 u16 cable_length; 597 u16 max_cable_length; 598 u16 min_cable_length; 599 600 u8 mdix; 601 602 bool disable_polarity_correction; 603 bool is_mdix; 604 bool polarity_correction; 605 bool speed_downgraded; 606 bool autoneg_wait_to_complete; 607 }; 608 609 struct e1000_nvm_info { 610 struct e1000_nvm_operations ops; 611 612 enum e1000_nvm_type type; 613 enum e1000_nvm_override override; 614 615 u32 flash_bank_size; 616 u32 flash_base_addr; 617 618 u16 word_size; 619 u16 delay_usec; 620 u16 address_bits; 621 u16 opcode_bits; 622 u16 page_size; 623 }; 624 625 struct e1000_bus_info { 626 enum e1000_bus_width width; 627 628 u16 func; 629 }; 630 631 struct e1000_fc_info { 632 u32 high_water; /* Flow control high-water mark */ 633 u32 low_water; /* Flow control low-water mark */ 634 u16 pause_time; /* Flow control pause timer */ 635 u16 refresh_time; /* Flow control refresh timer */ 636 bool send_xon; /* Flow control send XON */ 637 bool strict_ieee; /* Strict IEEE mode */ 638 enum e1000_fc_mode current_mode; /* FC mode in effect */ 639 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 640 }; 641 642 struct e1000_dev_spec_82571 { 643 bool laa_is_present; 644 u32 smb_counter; 645 }; 646 647 struct e1000_dev_spec_80003es2lan { 648 bool mdic_wa_enable; 649 }; 650 651 struct e1000_shadow_ram { 652 u16 value; 653 bool modified; 654 }; 655 656 #define E1000_ICH8_SHADOW_RAM_WORDS 2048 657 658 struct e1000_dev_spec_ich8lan { 659 bool kmrn_lock_loss_workaround_enabled; 660 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; 661 bool nvm_k1_enabled; 662 bool eee_disable; 663 u16 eee_lp_ability; 664 }; 665 666 struct e1000_hw { 667 struct e1000_adapter *adapter; 668 669 void __iomem *hw_addr; 670 void __iomem *flash_address; 671 672 struct e1000_mac_info mac; 673 struct e1000_fc_info fc; 674 struct e1000_phy_info phy; 675 struct e1000_nvm_info nvm; 676 struct e1000_bus_info bus; 677 struct e1000_host_mng_dhcp_cookie mng_cookie; 678 679 union { 680 struct e1000_dev_spec_82571 e82571; 681 struct e1000_dev_spec_80003es2lan e80003es2lan; 682 struct e1000_dev_spec_ich8lan ich8lan; 683 } dev_spec; 684 }; 685 686 #include "82571.h" 687 #include "80003es2lan.h" 688 #include "ich8lan.h" 689 690 #endif 691