xref: /linux/drivers/net/ethernet/intel/e1000e/hw.h (revision b889fcf63cb62e7fdb7816565e28f44dbe4a76a5)
1 /*******************************************************************************
2 
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2012 Intel Corporation.
5 
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9 
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14 
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21 
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _E1000_HW_H_
30 #define _E1000_HW_H_
31 
32 #include <linux/types.h>
33 
34 struct e1000_hw;
35 struct e1000_adapter;
36 
37 #include "defines.h"
38 
39 enum e1e_registers {
40 	E1000_CTRL     = 0x00000, /* Device Control - RW */
41 	E1000_STATUS   = 0x00008, /* Device Status - RO */
42 	E1000_EECD     = 0x00010, /* EEPROM/Flash Control - RW */
43 	E1000_EERD     = 0x00014, /* EEPROM Read - RW */
44 	E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
45 	E1000_FLA      = 0x0001C, /* Flash Access - RW */
46 	E1000_MDIC     = 0x00020, /* MDI Control - RW */
47 	E1000_SCTL     = 0x00024, /* SerDes Control - RW */
48 	E1000_FCAL     = 0x00028, /* Flow Control Address Low - RW */
49 	E1000_FCAH     = 0x0002C, /* Flow Control Address High -RW */
50 	E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
51 	E1000_FEXTNVM  = 0x00028, /* Future Extended NVM - RW */
52 	E1000_FCT      = 0x00030, /* Flow Control Type - RW */
53 	E1000_VET      = 0x00038, /* VLAN Ether Type - RW */
54 	E1000_FEXTNVM3 = 0x0003C, /* Future Extended NVM 3 - RW */
55 	E1000_ICR      = 0x000C0, /* Interrupt Cause Read - R/clr */
56 	E1000_ITR      = 0x000C4, /* Interrupt Throttling Rate - RW */
57 	E1000_ICS      = 0x000C8, /* Interrupt Cause Set - WO */
58 	E1000_IMS      = 0x000D0, /* Interrupt Mask Set - RW */
59 	E1000_IMC      = 0x000D8, /* Interrupt Mask Clear - WO */
60 	E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
61 	E1000_IAM      = 0x000E0, /* Interrupt Acknowledge Auto Mask */
62 	E1000_IVAR     = 0x000E4, /* Interrupt Vector Allocation - RW */
63 	E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
64 #define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
65 	E1000_RCTL     = 0x00100, /* Rx Control - RW */
66 	E1000_FCTTV    = 0x00170, /* Flow Control Transmit Timer Value - RW */
67 	E1000_TXCW     = 0x00178, /* Tx Configuration Word - RW */
68 	E1000_RXCW     = 0x00180, /* Rx Configuration Word - RO */
69 	E1000_TCTL     = 0x00400, /* Tx Control - RW */
70 	E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
71 	E1000_TIPG     = 0x00410, /* Tx Inter-packet gap -RW */
72 	E1000_AIT      = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
73 	E1000_LEDCTL   = 0x00E00, /* LED Control - RW */
74 	E1000_EXTCNF_CTRL  = 0x00F00, /* Extended Configuration Control */
75 	E1000_EXTCNF_SIZE  = 0x00F08, /* Extended Configuration Size */
76 	E1000_PHY_CTRL     = 0x00F10, /* PHY Control Register in CSR */
77 #define E1000_POEMB	E1000_PHY_CTRL	/* PHY OEM Bits */
78 	E1000_PBA      = 0x01000, /* Packet Buffer Allocation - RW */
79 	E1000_PBS      = 0x01008, /* Packet Buffer Size */
80 	E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
81 	E1000_EEWR     = 0x0102C, /* EEPROM Write Register - RW */
82 	E1000_FLOP     = 0x0103C, /* FLASH Opcode Register */
83 	E1000_PBA_ECC  = 0x01100, /* PBA ECC Register */
84 	E1000_ERT      = 0x02008, /* Early Rx Threshold - RW */
85 	E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */
86 	E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */
87 	E1000_PSRCTL   = 0x02170, /* Packet Split Receive Control - RW */
88 /* Convenience macros
89  *
90  * Note: "_n" is the queue number of the register to be written to.
91  *
92  * Example usage:
93  * E1000_RDBAL(current_rx_queue)
94  */
95 	E1000_RDBAL_BASE = 0x02800, /* Rx Descriptor Base Address Low - RW */
96 #define E1000_RDBAL(_n)	(E1000_RDBAL_BASE + (_n << 8))
97 	E1000_RDBAH_BASE = 0x02804, /* Rx Descriptor Base Address High - RW */
98 #define E1000_RDBAH(_n)	(E1000_RDBAH_BASE + (_n << 8))
99 	E1000_RDLEN_BASE = 0x02808, /* Rx Descriptor Length - RW */
100 #define E1000_RDLEN(_n)	(E1000_RDLEN_BASE + (_n << 8))
101 	E1000_RDH_BASE = 0x02810, /* Rx Descriptor Head - RW */
102 #define E1000_RDH(_n)	(E1000_RDH_BASE + (_n << 8))
103 	E1000_RDT_BASE = 0x02818, /* Rx Descriptor Tail - RW */
104 #define E1000_RDT(_n)	(E1000_RDT_BASE + (_n << 8))
105 	E1000_RDTR     = 0x02820, /* Rx Delay Timer - RW */
106 	E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
107 #define E1000_RXDCTL(_n)   (E1000_RXDCTL_BASE + (_n << 8))
108 	E1000_RADV     = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
109 
110 	E1000_KABGTXD  = 0x03004, /* AFE Band Gap Transmit Ref Data */
111 	E1000_TDBAL_BASE = 0x03800, /* Tx Descriptor Base Address Low - RW */
112 #define E1000_TDBAL(_n)	(E1000_TDBAL_BASE + (_n << 8))
113 	E1000_TDBAH_BASE = 0x03804, /* Tx Descriptor Base Address High - RW */
114 #define E1000_TDBAH(_n)	(E1000_TDBAH_BASE + (_n << 8))
115 	E1000_TDLEN_BASE = 0x03808, /* Tx Descriptor Length - RW */
116 #define E1000_TDLEN(_n)	(E1000_TDLEN_BASE + (_n << 8))
117 	E1000_TDH_BASE = 0x03810, /* Tx Descriptor Head - RW */
118 #define E1000_TDH(_n)	(E1000_TDH_BASE + (_n << 8))
119 	E1000_TDT_BASE = 0x03818, /* Tx Descriptor Tail - RW */
120 #define E1000_TDT(_n)	(E1000_TDT_BASE + (_n << 8))
121 	E1000_TIDV     = 0x03820, /* Tx Interrupt Delay Value - RW */
122 	E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
123 #define E1000_TXDCTL(_n)   (E1000_TXDCTL_BASE + (_n << 8))
124 	E1000_TADV     = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
125 	E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
126 #define E1000_TARC(_n)   (E1000_TARC_BASE + (_n << 8))
127 	E1000_CRCERRS  = 0x04000, /* CRC Error Count - R/clr */
128 	E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
129 	E1000_SYMERRS  = 0x04008, /* Symbol Error Count - R/clr */
130 	E1000_RXERRC   = 0x0400C, /* Receive Error Count - R/clr */
131 	E1000_MPC      = 0x04010, /* Missed Packet Count - R/clr */
132 	E1000_SCC      = 0x04014, /* Single Collision Count - R/clr */
133 	E1000_ECOL     = 0x04018, /* Excessive Collision Count - R/clr */
134 	E1000_MCC      = 0x0401C, /* Multiple Collision Count - R/clr */
135 	E1000_LATECOL  = 0x04020, /* Late Collision Count - R/clr */
136 	E1000_COLC     = 0x04028, /* Collision Count - R/clr */
137 	E1000_DC       = 0x04030, /* Defer Count - R/clr */
138 	E1000_TNCRS    = 0x04034, /* Tx-No CRS - R/clr */
139 	E1000_SEC      = 0x04038, /* Sequence Error Count - R/clr */
140 	E1000_CEXTERR  = 0x0403C, /* Carrier Extension Error Count - R/clr */
141 	E1000_RLEC     = 0x04040, /* Receive Length Error Count - R/clr */
142 	E1000_XONRXC   = 0x04048, /* XON Rx Count - R/clr */
143 	E1000_XONTXC   = 0x0404C, /* XON Tx Count - R/clr */
144 	E1000_XOFFRXC  = 0x04050, /* XOFF Rx Count - R/clr */
145 	E1000_XOFFTXC  = 0x04054, /* XOFF Tx Count - R/clr */
146 	E1000_FCRUC    = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
147 	E1000_PRC64    = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
148 	E1000_PRC127   = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
149 	E1000_PRC255   = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
150 	E1000_PRC511   = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
151 	E1000_PRC1023  = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
152 	E1000_PRC1522  = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
153 	E1000_GPRC     = 0x04074, /* Good Packets Rx Count - R/clr */
154 	E1000_BPRC     = 0x04078, /* Broadcast Packets Rx Count - R/clr */
155 	E1000_MPRC     = 0x0407C, /* Multicast Packets Rx Count - R/clr */
156 	E1000_GPTC     = 0x04080, /* Good Packets Tx Count - R/clr */
157 	E1000_GORCL    = 0x04088, /* Good Octets Rx Count Low - R/clr */
158 	E1000_GORCH    = 0x0408C, /* Good Octets Rx Count High - R/clr */
159 	E1000_GOTCL    = 0x04090, /* Good Octets Tx Count Low - R/clr */
160 	E1000_GOTCH    = 0x04094, /* Good Octets Tx Count High - R/clr */
161 	E1000_RNBC     = 0x040A0, /* Rx No Buffers Count - R/clr */
162 	E1000_RUC      = 0x040A4, /* Rx Undersize Count - R/clr */
163 	E1000_RFC      = 0x040A8, /* Rx Fragment Count - R/clr */
164 	E1000_ROC      = 0x040AC, /* Rx Oversize Count - R/clr */
165 	E1000_RJC      = 0x040B0, /* Rx Jabber Count - R/clr */
166 	E1000_MGTPRC   = 0x040B4, /* Management Packets Rx Count - R/clr */
167 	E1000_MGTPDC   = 0x040B8, /* Management Packets Dropped Count - R/clr */
168 	E1000_MGTPTC   = 0x040BC, /* Management Packets Tx Count - R/clr */
169 	E1000_TORL     = 0x040C0, /* Total Octets Rx Low - R/clr */
170 	E1000_TORH     = 0x040C4, /* Total Octets Rx High - R/clr */
171 	E1000_TOTL     = 0x040C8, /* Total Octets Tx Low - R/clr */
172 	E1000_TOTH     = 0x040CC, /* Total Octets Tx High - R/clr */
173 	E1000_TPR      = 0x040D0, /* Total Packets Rx - R/clr */
174 	E1000_TPT      = 0x040D4, /* Total Packets Tx - R/clr */
175 	E1000_PTC64    = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
176 	E1000_PTC127   = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
177 	E1000_PTC255   = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
178 	E1000_PTC511   = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
179 	E1000_PTC1023  = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
180 	E1000_PTC1522  = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
181 	E1000_MPTC     = 0x040F0, /* Multicast Packets Tx Count - R/clr */
182 	E1000_BPTC     = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
183 	E1000_TSCTC    = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
184 	E1000_TSCTFC   = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
185 	E1000_IAC      = 0x04100, /* Interrupt Assertion Count */
186 	E1000_ICRXPTC  = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
187 	E1000_ICRXATC  = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
188 	E1000_ICTXPTC  = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
189 	E1000_ICTXATC  = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
190 	E1000_ICTXQEC  = 0x04118, /* Irq Cause Tx Queue Empty Count */
191 	E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
192 	E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
193 	E1000_ICRXOC   = 0x04124, /* Irq Cause Receiver Overrun Count */
194 	E1000_RXCSUM   = 0x05000, /* Rx Checksum Control - RW */
195 	E1000_RFCTL    = 0x05008, /* Receive Filter Control */
196 	E1000_MTA      = 0x05200, /* Multicast Table Array - RW Array */
197 	E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
198 #define E1000_RAL(_n)   (E1000_RAL_BASE + ((_n) * 8))
199 #define E1000_RA        (E1000_RAL(0))
200 	E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
201 #define E1000_RAH(_n)   (E1000_RAH_BASE + ((_n) * 8))
202 	E1000_SHRAL_PCH_LPT_BASE = 0x05408,
203 #define E1000_SHRAL_PCH_LPT(_n)   (E1000_SHRAL_PCH_LPT_BASE + ((_n) * 8))
204 	E1000_SHRAH_PCH_LTP_BASE = 0x0540C,
205 #define E1000_SHRAH_PCH_LPT(_n)   (E1000_SHRAH_PCH_LTP_BASE + ((_n) * 8))
206 	E1000_SHRAL_BASE = 0x05438, /* Shared Receive Address Low - RW */
207 #define E1000_SHRAL(_n)   (E1000_SHRAL_BASE + ((_n) * 8))
208 	E1000_SHRAH_BASE = 0x0543C, /* Shared Receive Address High - RW */
209 #define E1000_SHRAH(_n)   (E1000_SHRAH_BASE + ((_n) * 8))
210 	E1000_VFTA     = 0x05600, /* VLAN Filter Table Array - RW Array */
211 	E1000_WUC      = 0x05800, /* Wakeup Control - RW */
212 	E1000_WUFC     = 0x05808, /* Wakeup Filter Control - RW */
213 	E1000_WUS      = 0x05810, /* Wakeup Status - RO */
214 	E1000_MRQC     = 0x05818, /* Multiple Receive Control - RW */
215 	E1000_MANC     = 0x05820, /* Management Control - RW */
216 	E1000_FFLT     = 0x05F00, /* Flexible Filter Length Table - RW Array */
217 	E1000_HOST_IF  = 0x08800, /* Host Interface */
218 
219 	E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
220 	E1000_MANC2H    = 0x05860, /* Management Control To Host - RW */
221 	E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
222 #define E1000_MDEF(_n)   (E1000_MDEF_BASE + ((_n) * 4))
223 	E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
224 	E1000_GCR	= 0x05B00, /* PCI-Ex Control */
225 	E1000_GCR2      = 0x05B64, /* PCI-Ex Control #2 */
226 	E1000_FACTPS    = 0x05B30, /* Function Active and Power State to MNG */
227 	E1000_SWSM      = 0x05B50, /* SW Semaphore */
228 	E1000_FWSM      = 0x05B54, /* FW Semaphore */
229 	E1000_SWSM2     = 0x05B58, /* Driver-only SW semaphore */
230 	E1000_RETA_BASE = 0x05C00, /* Redirection Table - RW */
231 #define E1000_RETA(_n)	(E1000_RETA_BASE + ((_n) * 4))
232 	E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
233 #define E1000_RSSRK(_n)	(E1000_RSSRK_BASE + ((_n) * 4))
234 	E1000_FFLT_DBG  = 0x05F04, /* Debug Register */
235 	E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
236 #define E1000_PCH_RAICC(_n)	(E1000_PCH_RAICC_BASE + ((_n) * 4))
237 #define E1000_CRC_OFFSET	E1000_PCH_RAICC_BASE
238 	E1000_HICR      = 0x08F00, /* Host Interface Control */
239 };
240 
241 #define E1000_MAX_PHY_ADDR		4
242 
243 /* IGP01E1000 Specific Registers */
244 #define IGP01E1000_PHY_PORT_CONFIG	0x10 /* Port Config */
245 #define IGP01E1000_PHY_PORT_STATUS	0x11 /* Status */
246 #define IGP01E1000_PHY_PORT_CTRL	0x12 /* Control */
247 #define IGP01E1000_PHY_LINK_HEALTH	0x13 /* PHY Link Health */
248 #define IGP02E1000_PHY_POWER_MGMT	0x19 /* Power Management */
249 #define IGP01E1000_PHY_PAGE_SELECT	0x1F /* Page Select */
250 #define BM_PHY_PAGE_SELECT		22   /* Page Select for BM */
251 #define IGP_PAGE_SHIFT			5
252 #define PHY_REG_MASK			0x1F
253 
254 #define BM_WUC_PAGE			800
255 #define BM_WUC_ADDRESS_OPCODE		0x11
256 #define BM_WUC_DATA_OPCODE		0x12
257 #define BM_WUC_ENABLE_PAGE		769
258 #define BM_WUC_ENABLE_REG		17
259 #define BM_WUC_ENABLE_BIT		(1 << 2)
260 #define BM_WUC_HOST_WU_BIT		(1 << 4)
261 #define BM_WUC_ME_WU_BIT		(1 << 5)
262 
263 #define BM_WUC	PHY_REG(BM_WUC_PAGE, 1)
264 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
265 #define BM_WUS	PHY_REG(BM_WUC_PAGE, 3)
266 
267 #define IGP01E1000_PHY_PCS_INIT_REG	0x00B4
268 #define IGP01E1000_PHY_POLARITY_MASK	0x0078
269 
270 #define IGP01E1000_PSCR_AUTO_MDIX	0x1000
271 #define IGP01E1000_PSCR_FORCE_MDI_MDIX	0x2000 /* 0=MDI, 1=MDIX */
272 
273 #define IGP01E1000_PSCFR_SMART_SPEED	0x0080
274 
275 #define IGP02E1000_PM_SPD		0x0001 /* Smart Power Down */
276 #define IGP02E1000_PM_D0_LPLU		0x0002 /* For D0a states */
277 #define IGP02E1000_PM_D3_LPLU		0x0004 /* For all other states */
278 
279 #define IGP01E1000_PLHR_SS_DOWNGRADE	0x8000
280 
281 #define IGP01E1000_PSSR_POLARITY_REVERSED	0x0002
282 #define IGP01E1000_PSSR_MDIX			0x0800
283 #define IGP01E1000_PSSR_SPEED_MASK		0xC000
284 #define IGP01E1000_PSSR_SPEED_1000MBPS		0xC000
285 
286 #define IGP02E1000_PHY_CHANNEL_NUM		4
287 #define IGP02E1000_PHY_AGC_A			0x11B1
288 #define IGP02E1000_PHY_AGC_B			0x12B1
289 #define IGP02E1000_PHY_AGC_C			0x14B1
290 #define IGP02E1000_PHY_AGC_D			0x18B1
291 
292 #define IGP02E1000_AGC_LENGTH_SHIFT	9 /* Course - 15:13, Fine - 12:9 */
293 #define IGP02E1000_AGC_LENGTH_MASK	0x7F
294 #define IGP02E1000_AGC_RANGE		15
295 
296 /* manage.c */
297 #define E1000_VFTA_ENTRY_SHIFT		5
298 #define E1000_VFTA_ENTRY_MASK		0x7F
299 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK	0x1F
300 
301 #define E1000_HICR_EN			0x01  /* Enable bit - RO */
302 /* Driver sets this bit when done to put command in RAM */
303 #define E1000_HICR_C			0x02
304 #define E1000_HICR_FW_RESET_ENABLE	0x40
305 #define E1000_HICR_FW_RESET		0x80
306 
307 #define E1000_FWSM_MODE_MASK		0xE
308 #define E1000_FWSM_MODE_SHIFT		1
309 
310 #define E1000_MNG_IAMT_MODE		0x3
311 #define E1000_MNG_DHCP_COOKIE_LENGTH	0x10
312 #define E1000_MNG_DHCP_COOKIE_OFFSET	0x6F0
313 #define E1000_MNG_DHCP_COMMAND_TIMEOUT	10
314 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD	64
315 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING	0x1
316 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN	0x2
317 
318 /* nvm.c */
319 #define E1000_STM_OPCODE  0xDB00
320 
321 #define E1000_KMRNCTRLSTA_OFFSET	0x001F0000
322 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT	16
323 #define E1000_KMRNCTRLSTA_REN		0x00200000
324 #define E1000_KMRNCTRLSTA_CTRL_OFFSET	0x1    /* Kumeran Control */
325 #define E1000_KMRNCTRLSTA_DIAG_OFFSET	0x3    /* Kumeran Diagnostic */
326 #define E1000_KMRNCTRLSTA_TIMEOUTS	0x4    /* Kumeran Timeouts */
327 #define E1000_KMRNCTRLSTA_INBAND_PARAM	0x9    /* Kumeran InBand Parameters */
328 #define E1000_KMRNCTRLSTA_IBIST_DISABLE	0x0200 /* Kumeran IBIST Disable */
329 #define E1000_KMRNCTRLSTA_DIAG_NELPBK	0x1000 /* Nearend Loopback mode */
330 #define E1000_KMRNCTRLSTA_K1_CONFIG	0x7
331 #define E1000_KMRNCTRLSTA_K1_ENABLE	0x0002
332 #define E1000_KMRNCTRLSTA_HD_CTRL	0x10   /* Kumeran HD Control */
333 
334 #define IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
335 #define IFE_PHY_SPECIAL_CONTROL		0x11 /* 100BaseTx PHY Special Control */
336 #define IFE_PHY_SPECIAL_CONTROL_LED	0x1B /* PHY Special and LED Control */
337 #define IFE_PHY_MDIX_CONTROL		0x1C /* MDI/MDI-X Control */
338 
339 /* IFE PHY Extended Status Control */
340 #define IFE_PESC_POLARITY_REVERSED	0x0100
341 
342 /* IFE PHY Special Control */
343 #define IFE_PSC_AUTO_POLARITY_DISABLE		0x0010
344 #define IFE_PSC_FORCE_POLARITY			0x0020
345 
346 /* IFE PHY Special Control and LED Control */
347 #define IFE_PSCL_PROBE_MODE		0x0020
348 #define IFE_PSCL_PROBE_LEDS_OFF		0x0006 /* Force LEDs 0 and 2 off */
349 #define IFE_PSCL_PROBE_LEDS_ON		0x0007 /* Force LEDs 0 and 2 on */
350 
351 /* IFE PHY MDIX Control */
352 #define IFE_PMC_MDIX_STATUS	0x0020 /* 1=MDI-X, 0=MDI */
353 #define IFE_PMC_FORCE_MDIX	0x0040 /* 1=force MDI-X, 0=force MDI */
354 #define IFE_PMC_AUTO_MDIX	0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
355 
356 #define E1000_CABLE_LENGTH_UNDEFINED	0xFF
357 
358 #define E1000_DEV_ID_82571EB_COPPER		0x105E
359 #define E1000_DEV_ID_82571EB_FIBER		0x105F
360 #define E1000_DEV_ID_82571EB_SERDES		0x1060
361 #define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
362 #define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
363 #define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
364 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
365 #define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
366 #define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
367 #define E1000_DEV_ID_82572EI_COPPER		0x107D
368 #define E1000_DEV_ID_82572EI_FIBER		0x107E
369 #define E1000_DEV_ID_82572EI_SERDES		0x107F
370 #define E1000_DEV_ID_82572EI			0x10B9
371 #define E1000_DEV_ID_82573E			0x108B
372 #define E1000_DEV_ID_82573E_IAMT		0x108C
373 #define E1000_DEV_ID_82573L			0x109A
374 #define E1000_DEV_ID_82574L			0x10D3
375 #define E1000_DEV_ID_82574LA			0x10F6
376 #define E1000_DEV_ID_82583V                     0x150C
377 
378 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
379 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
380 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
381 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
382 
383 #define E1000_DEV_ID_ICH8_82567V_3		0x1501
384 #define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
385 #define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
386 #define E1000_DEV_ID_ICH8_IGP_C			0x104B
387 #define E1000_DEV_ID_ICH8_IFE			0x104C
388 #define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
389 #define E1000_DEV_ID_ICH8_IFE_G			0x10C5
390 #define E1000_DEV_ID_ICH8_IGP_M			0x104D
391 #define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
392 #define E1000_DEV_ID_ICH9_BM			0x10E5
393 #define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
394 #define E1000_DEV_ID_ICH9_IGP_M			0x10BF
395 #define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
396 #define E1000_DEV_ID_ICH9_IGP_C			0x294C
397 #define E1000_DEV_ID_ICH9_IFE			0x10C0
398 #define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
399 #define E1000_DEV_ID_ICH9_IFE_G			0x10C2
400 #define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
401 #define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
402 #define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
403 #define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
404 #define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
405 #define E1000_DEV_ID_ICH10_D_BM_V		0x1525
406 #define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
407 #define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
408 #define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
409 #define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
410 #define E1000_DEV_ID_PCH2_LV_LM			0x1502
411 #define E1000_DEV_ID_PCH2_LV_V			0x1503
412 #define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A
413 #define E1000_DEV_ID_PCH_LPT_I217_V		0x153B
414 #define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A
415 #define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559
416 
417 #define E1000_REVISION_4 4
418 
419 #define E1000_FUNC_1 1
420 
421 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
422 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
423 
424 enum e1000_mac_type {
425 	e1000_82571,
426 	e1000_82572,
427 	e1000_82573,
428 	e1000_82574,
429 	e1000_82583,
430 	e1000_80003es2lan,
431 	e1000_ich8lan,
432 	e1000_ich9lan,
433 	e1000_ich10lan,
434 	e1000_pchlan,
435 	e1000_pch2lan,
436 	e1000_pch_lpt,
437 };
438 
439 enum e1000_media_type {
440 	e1000_media_type_unknown = 0,
441 	e1000_media_type_copper = 1,
442 	e1000_media_type_fiber = 2,
443 	e1000_media_type_internal_serdes = 3,
444 	e1000_num_media_types
445 };
446 
447 enum e1000_nvm_type {
448 	e1000_nvm_unknown = 0,
449 	e1000_nvm_none,
450 	e1000_nvm_eeprom_spi,
451 	e1000_nvm_flash_hw,
452 	e1000_nvm_flash_sw
453 };
454 
455 enum e1000_nvm_override {
456 	e1000_nvm_override_none = 0,
457 	e1000_nvm_override_spi_small,
458 	e1000_nvm_override_spi_large
459 };
460 
461 enum e1000_phy_type {
462 	e1000_phy_unknown = 0,
463 	e1000_phy_none,
464 	e1000_phy_m88,
465 	e1000_phy_igp,
466 	e1000_phy_igp_2,
467 	e1000_phy_gg82563,
468 	e1000_phy_igp_3,
469 	e1000_phy_ife,
470 	e1000_phy_bm,
471 	e1000_phy_82578,
472 	e1000_phy_82577,
473 	e1000_phy_82579,
474 	e1000_phy_i217,
475 };
476 
477 enum e1000_bus_width {
478 	e1000_bus_width_unknown = 0,
479 	e1000_bus_width_pcie_x1,
480 	e1000_bus_width_pcie_x2,
481 	e1000_bus_width_pcie_x4 = 4,
482 	e1000_bus_width_32,
483 	e1000_bus_width_64,
484 	e1000_bus_width_reserved
485 };
486 
487 enum e1000_1000t_rx_status {
488 	e1000_1000t_rx_status_not_ok = 0,
489 	e1000_1000t_rx_status_ok,
490 	e1000_1000t_rx_status_undefined = 0xFF
491 };
492 
493 enum e1000_rev_polarity{
494 	e1000_rev_polarity_normal = 0,
495 	e1000_rev_polarity_reversed,
496 	e1000_rev_polarity_undefined = 0xFF
497 };
498 
499 enum e1000_fc_mode {
500 	e1000_fc_none = 0,
501 	e1000_fc_rx_pause,
502 	e1000_fc_tx_pause,
503 	e1000_fc_full,
504 	e1000_fc_default = 0xFF
505 };
506 
507 enum e1000_ms_type {
508 	e1000_ms_hw_default = 0,
509 	e1000_ms_force_master,
510 	e1000_ms_force_slave,
511 	e1000_ms_auto
512 };
513 
514 enum e1000_smart_speed {
515 	e1000_smart_speed_default = 0,
516 	e1000_smart_speed_on,
517 	e1000_smart_speed_off
518 };
519 
520 enum e1000_serdes_link_state {
521 	e1000_serdes_link_down = 0,
522 	e1000_serdes_link_autoneg_progress,
523 	e1000_serdes_link_autoneg_complete,
524 	e1000_serdes_link_forced_up
525 };
526 
527 /* Receive Descriptor */
528 struct e1000_rx_desc {
529 	__le64 buffer_addr; /* Address of the descriptor's data buffer */
530 	__le16 length;      /* Length of data DMAed into data buffer */
531 	__le16 csum;	/* Packet checksum */
532 	u8  status;      /* Descriptor status */
533 	u8  errors;      /* Descriptor Errors */
534 	__le16 special;
535 };
536 
537 /* Receive Descriptor - Extended */
538 union e1000_rx_desc_extended {
539 	struct {
540 		__le64 buffer_addr;
541 		__le64 reserved;
542 	} read;
543 	struct {
544 		struct {
545 			__le32 mrq;	      /* Multiple Rx Queues */
546 			union {
547 				__le32 rss;	    /* RSS Hash */
548 				struct {
549 					__le16 ip_id;  /* IP id */
550 					__le16 csum;   /* Packet Checksum */
551 				} csum_ip;
552 			} hi_dword;
553 		} lower;
554 		struct {
555 			__le32 status_error;     /* ext status/error */
556 			__le16 length;
557 			__le16 vlan;	     /* VLAN tag */
558 		} upper;
559 	} wb;  /* writeback */
560 };
561 
562 #define MAX_PS_BUFFERS 4
563 /* Receive Descriptor - Packet Split */
564 union e1000_rx_desc_packet_split {
565 	struct {
566 		/* one buffer for protocol header(s), three data buffers */
567 		__le64 buffer_addr[MAX_PS_BUFFERS];
568 	} read;
569 	struct {
570 		struct {
571 			__le32 mrq;	      /* Multiple Rx Queues */
572 			union {
573 				__le32 rss;	      /* RSS Hash */
574 				struct {
575 					__le16 ip_id;    /* IP id */
576 					__le16 csum;     /* Packet Checksum */
577 				} csum_ip;
578 			} hi_dword;
579 		} lower;
580 		struct {
581 			__le32 status_error;     /* ext status/error */
582 			__le16 length0;	  /* length of buffer 0 */
583 			__le16 vlan;	     /* VLAN tag */
584 		} middle;
585 		struct {
586 			__le16 header_status;
587 			__le16 length[3];	/* length of buffers 1-3 */
588 		} upper;
589 		__le64 reserved;
590 	} wb; /* writeback */
591 };
592 
593 /* Transmit Descriptor */
594 struct e1000_tx_desc {
595 	__le64 buffer_addr;      /* Address of the descriptor's data buffer */
596 	union {
597 		__le32 data;
598 		struct {
599 			__le16 length;    /* Data buffer length */
600 			u8 cso;	/* Checksum offset */
601 			u8 cmd;	/* Descriptor control */
602 		} flags;
603 	} lower;
604 	union {
605 		__le32 data;
606 		struct {
607 			u8 status;     /* Descriptor status */
608 			u8 css;	/* Checksum start */
609 			__le16 special;
610 		} fields;
611 	} upper;
612 };
613 
614 /* Offload Context Descriptor */
615 struct e1000_context_desc {
616 	union {
617 		__le32 ip_config;
618 		struct {
619 			u8 ipcss;      /* IP checksum start */
620 			u8 ipcso;      /* IP checksum offset */
621 			__le16 ipcse;     /* IP checksum end */
622 		} ip_fields;
623 	} lower_setup;
624 	union {
625 		__le32 tcp_config;
626 		struct {
627 			u8 tucss;      /* TCP checksum start */
628 			u8 tucso;      /* TCP checksum offset */
629 			__le16 tucse;     /* TCP checksum end */
630 		} tcp_fields;
631 	} upper_setup;
632 	__le32 cmd_and_length;
633 	union {
634 		__le32 data;
635 		struct {
636 			u8 status;     /* Descriptor status */
637 			u8 hdr_len;    /* Header length */
638 			__le16 mss;       /* Maximum segment size */
639 		} fields;
640 	} tcp_seg_setup;
641 };
642 
643 /* Offload data descriptor */
644 struct e1000_data_desc {
645 	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
646 	union {
647 		__le32 data;
648 		struct {
649 			__le16 length;    /* Data buffer length */
650 			u8 typ_len_ext;
651 			u8 cmd;
652 		} flags;
653 	} lower;
654 	union {
655 		__le32 data;
656 		struct {
657 			u8 status;     /* Descriptor status */
658 			u8 popts;      /* Packet Options */
659 			__le16 special;   /* */
660 		} fields;
661 	} upper;
662 };
663 
664 /* Statistics counters collected by the MAC */
665 struct e1000_hw_stats {
666 	u64 crcerrs;
667 	u64 algnerrc;
668 	u64 symerrs;
669 	u64 rxerrc;
670 	u64 mpc;
671 	u64 scc;
672 	u64 ecol;
673 	u64 mcc;
674 	u64 latecol;
675 	u64 colc;
676 	u64 dc;
677 	u64 tncrs;
678 	u64 sec;
679 	u64 cexterr;
680 	u64 rlec;
681 	u64 xonrxc;
682 	u64 xontxc;
683 	u64 xoffrxc;
684 	u64 xofftxc;
685 	u64 fcruc;
686 	u64 prc64;
687 	u64 prc127;
688 	u64 prc255;
689 	u64 prc511;
690 	u64 prc1023;
691 	u64 prc1522;
692 	u64 gprc;
693 	u64 bprc;
694 	u64 mprc;
695 	u64 gptc;
696 	u64 gorc;
697 	u64 gotc;
698 	u64 rnbc;
699 	u64 ruc;
700 	u64 rfc;
701 	u64 roc;
702 	u64 rjc;
703 	u64 mgprc;
704 	u64 mgpdc;
705 	u64 mgptc;
706 	u64 tor;
707 	u64 tot;
708 	u64 tpr;
709 	u64 tpt;
710 	u64 ptc64;
711 	u64 ptc127;
712 	u64 ptc255;
713 	u64 ptc511;
714 	u64 ptc1023;
715 	u64 ptc1522;
716 	u64 mptc;
717 	u64 bptc;
718 	u64 tsctc;
719 	u64 tsctfc;
720 	u64 iac;
721 	u64 icrxptc;
722 	u64 icrxatc;
723 	u64 ictxptc;
724 	u64 ictxatc;
725 	u64 ictxqec;
726 	u64 ictxqmtc;
727 	u64 icrxdmtc;
728 	u64 icrxoc;
729 };
730 
731 struct e1000_phy_stats {
732 	u32 idle_errors;
733 	u32 receive_errors;
734 };
735 
736 struct e1000_host_mng_dhcp_cookie {
737 	u32 signature;
738 	u8  status;
739 	u8  reserved0;
740 	u16 vlan_id;
741 	u32 reserved1;
742 	u16 reserved2;
743 	u8  reserved3;
744 	u8  checksum;
745 };
746 
747 /* Host Interface "Rev 1" */
748 struct e1000_host_command_header {
749 	u8 command_id;
750 	u8 command_length;
751 	u8 command_options;
752 	u8 checksum;
753 };
754 
755 #define E1000_HI_MAX_DATA_LENGTH     252
756 struct e1000_host_command_info {
757 	struct e1000_host_command_header command_header;
758 	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
759 };
760 
761 /* Host Interface "Rev 2" */
762 struct e1000_host_mng_command_header {
763 	u8  command_id;
764 	u8  checksum;
765 	u16 reserved1;
766 	u16 reserved2;
767 	u16 command_length;
768 };
769 
770 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
771 struct e1000_host_mng_command_info {
772 	struct e1000_host_mng_command_header command_header;
773 	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
774 };
775 
776 /* Function pointers and static data for the MAC. */
777 struct e1000_mac_operations {
778 	s32  (*id_led_init)(struct e1000_hw *);
779 	s32  (*blink_led)(struct e1000_hw *);
780 	bool (*check_mng_mode)(struct e1000_hw *);
781 	s32  (*check_for_link)(struct e1000_hw *);
782 	s32  (*cleanup_led)(struct e1000_hw *);
783 	void (*clear_hw_cntrs)(struct e1000_hw *);
784 	void (*clear_vfta)(struct e1000_hw *);
785 	s32  (*get_bus_info)(struct e1000_hw *);
786 	void (*set_lan_id)(struct e1000_hw *);
787 	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
788 	s32  (*led_on)(struct e1000_hw *);
789 	s32  (*led_off)(struct e1000_hw *);
790 	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
791 	s32  (*reset_hw)(struct e1000_hw *);
792 	s32  (*init_hw)(struct e1000_hw *);
793 	s32  (*setup_link)(struct e1000_hw *);
794 	s32  (*setup_physical_interface)(struct e1000_hw *);
795 	s32  (*setup_led)(struct e1000_hw *);
796 	void (*write_vfta)(struct e1000_hw *, u32, u32);
797 	void (*config_collision_dist)(struct e1000_hw *);
798 	void (*rar_set)(struct e1000_hw *, u8 *, u32);
799 	s32  (*read_mac_addr)(struct e1000_hw *);
800 };
801 
802 /* When to use various PHY register access functions:
803  *
804  *                 Func   Caller
805  *   Function      Does   Does    When to use
806  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
807  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
808  *   X_reg_locked  P,A    L       for multiple accesses of different regs
809  *                                on different pages
810  *   X_reg_page    A      L,P     for multiple accesses of different regs
811  *                                on the same page
812  *
813  * Where X=[read|write], L=locking, P=sets page, A=register access
814  *
815  */
816 struct e1000_phy_operations {
817 	s32  (*acquire)(struct e1000_hw *);
818 	s32  (*cfg_on_link_up)(struct e1000_hw *);
819 	s32  (*check_polarity)(struct e1000_hw *);
820 	s32  (*check_reset_block)(struct e1000_hw *);
821 	s32  (*commit)(struct e1000_hw *);
822 	s32  (*force_speed_duplex)(struct e1000_hw *);
823 	s32  (*get_cfg_done)(struct e1000_hw *hw);
824 	s32  (*get_cable_length)(struct e1000_hw *);
825 	s32  (*get_info)(struct e1000_hw *);
826 	s32  (*set_page)(struct e1000_hw *, u16);
827 	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
828 	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
829 	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
830 	void (*release)(struct e1000_hw *);
831 	s32  (*reset)(struct e1000_hw *);
832 	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
833 	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
834 	s32  (*write_reg)(struct e1000_hw *, u32, u16);
835 	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
836 	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
837 	void (*power_up)(struct e1000_hw *);
838 	void (*power_down)(struct e1000_hw *);
839 };
840 
841 /* Function pointers for the NVM. */
842 struct e1000_nvm_operations {
843 	s32  (*acquire)(struct e1000_hw *);
844 	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
845 	void (*release)(struct e1000_hw *);
846 	void (*reload)(struct e1000_hw *);
847 	s32  (*update)(struct e1000_hw *);
848 	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
849 	s32  (*validate)(struct e1000_hw *);
850 	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
851 };
852 
853 struct e1000_mac_info {
854 	struct e1000_mac_operations ops;
855 	u8 addr[ETH_ALEN];
856 	u8 perm_addr[ETH_ALEN];
857 
858 	enum e1000_mac_type type;
859 
860 	u32 collision_delta;
861 	u32 ledctl_default;
862 	u32 ledctl_mode1;
863 	u32 ledctl_mode2;
864 	u32 mc_filter_type;
865 	u32 tx_packet_delta;
866 	u32 txcw;
867 
868 	u16 current_ifs_val;
869 	u16 ifs_max_val;
870 	u16 ifs_min_val;
871 	u16 ifs_ratio;
872 	u16 ifs_step_size;
873 	u16 mta_reg_count;
874 
875 	/* Maximum size of the MTA register table in all supported adapters */
876 	#define MAX_MTA_REG 128
877 	u32 mta_shadow[MAX_MTA_REG];
878 	u16 rar_entry_count;
879 
880 	u8  forced_speed_duplex;
881 
882 	bool adaptive_ifs;
883 	bool has_fwsm;
884 	bool arc_subsystem_valid;
885 	bool autoneg;
886 	bool autoneg_failed;
887 	bool get_link_status;
888 	bool in_ifs_mode;
889 	bool serdes_has_link;
890 	bool tx_pkt_filtering;
891 	enum e1000_serdes_link_state serdes_link_state;
892 };
893 
894 struct e1000_phy_info {
895 	struct e1000_phy_operations ops;
896 
897 	enum e1000_phy_type type;
898 
899 	enum e1000_1000t_rx_status local_rx;
900 	enum e1000_1000t_rx_status remote_rx;
901 	enum e1000_ms_type ms_type;
902 	enum e1000_ms_type original_ms_type;
903 	enum e1000_rev_polarity cable_polarity;
904 	enum e1000_smart_speed smart_speed;
905 
906 	u32 addr;
907 	u32 id;
908 	u32 reset_delay_us; /* in usec */
909 	u32 revision;
910 
911 	enum e1000_media_type media_type;
912 
913 	u16 autoneg_advertised;
914 	u16 autoneg_mask;
915 	u16 cable_length;
916 	u16 max_cable_length;
917 	u16 min_cable_length;
918 
919 	u8 mdix;
920 
921 	bool disable_polarity_correction;
922 	bool is_mdix;
923 	bool polarity_correction;
924 	bool speed_downgraded;
925 	bool autoneg_wait_to_complete;
926 };
927 
928 struct e1000_nvm_info {
929 	struct e1000_nvm_operations ops;
930 
931 	enum e1000_nvm_type type;
932 	enum e1000_nvm_override override;
933 
934 	u32 flash_bank_size;
935 	u32 flash_base_addr;
936 
937 	u16 word_size;
938 	u16 delay_usec;
939 	u16 address_bits;
940 	u16 opcode_bits;
941 	u16 page_size;
942 };
943 
944 struct e1000_bus_info {
945 	enum e1000_bus_width width;
946 
947 	u16 func;
948 };
949 
950 struct e1000_fc_info {
951 	u32 high_water;          /* Flow control high-water mark */
952 	u32 low_water;           /* Flow control low-water mark */
953 	u16 pause_time;          /* Flow control pause timer */
954 	u16 refresh_time;        /* Flow control refresh timer */
955 	bool send_xon;           /* Flow control send XON */
956 	bool strict_ieee;        /* Strict IEEE mode */
957 	enum e1000_fc_mode current_mode; /* FC mode in effect */
958 	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
959 };
960 
961 struct e1000_dev_spec_82571 {
962 	bool laa_is_present;
963 	u32 smb_counter;
964 };
965 
966 struct e1000_dev_spec_80003es2lan {
967 	bool  mdic_wa_enable;
968 };
969 
970 struct e1000_shadow_ram {
971 	u16  value;
972 	bool modified;
973 };
974 
975 #define E1000_ICH8_SHADOW_RAM_WORDS		2048
976 
977 struct e1000_dev_spec_ich8lan {
978 	bool kmrn_lock_loss_workaround_enabled;
979 	struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
980 	bool nvm_k1_enabled;
981 	bool eee_disable;
982 	u16 eee_lp_ability;
983 };
984 
985 struct e1000_hw {
986 	struct e1000_adapter *adapter;
987 
988 	void __iomem *hw_addr;
989 	void __iomem *flash_address;
990 
991 	struct e1000_mac_info  mac;
992 	struct e1000_fc_info   fc;
993 	struct e1000_phy_info  phy;
994 	struct e1000_nvm_info  nvm;
995 	struct e1000_bus_info  bus;
996 	struct e1000_host_mng_dhcp_cookie mng_cookie;
997 
998 	union {
999 		struct e1000_dev_spec_82571	e82571;
1000 		struct e1000_dev_spec_80003es2lan e80003es2lan;
1001 		struct e1000_dev_spec_ich8lan	ich8lan;
1002 	} dev_spec;
1003 };
1004 
1005 #endif
1006