1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _E1000_HW_H_ 5 #define _E1000_HW_H_ 6 7 #include "regs.h" 8 #include "defines.h" 9 10 struct e1000_hw; 11 12 #define E1000_DEV_ID_82571EB_COPPER 0x105E 13 #define E1000_DEV_ID_82571EB_FIBER 0x105F 14 #define E1000_DEV_ID_82571EB_SERDES 0x1060 15 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 16 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 17 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 18 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 19 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 20 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 21 #define E1000_DEV_ID_82572EI_COPPER 0x107D 22 #define E1000_DEV_ID_82572EI_FIBER 0x107E 23 #define E1000_DEV_ID_82572EI_SERDES 0x107F 24 #define E1000_DEV_ID_82572EI 0x10B9 25 #define E1000_DEV_ID_82573E 0x108B 26 #define E1000_DEV_ID_82573E_IAMT 0x108C 27 #define E1000_DEV_ID_82573L 0x109A 28 #define E1000_DEV_ID_82574L 0x10D3 29 #define E1000_DEV_ID_82574LA 0x10F6 30 #define E1000_DEV_ID_82583V 0x150C 31 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 32 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 33 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 34 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 35 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 36 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 37 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 38 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 39 #define E1000_DEV_ID_ICH8_IFE 0x104C 40 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 41 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 42 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 43 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 44 #define E1000_DEV_ID_ICH9_BM 0x10E5 45 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 46 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 47 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 48 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 49 #define E1000_DEV_ID_ICH9_IFE 0x10C0 50 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 51 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 52 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 53 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 54 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 55 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 56 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 57 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 58 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 59 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 60 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 61 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 62 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 63 #define E1000_DEV_ID_PCH2_LV_V 0x1503 64 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 65 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 66 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 67 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 68 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 69 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 70 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 71 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 72 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */ 73 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */ 74 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */ 75 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */ 76 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */ 77 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 78 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 79 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 80 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 81 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 82 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 83 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 84 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 85 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 86 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 87 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 88 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 89 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 90 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 91 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 92 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 93 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 94 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 95 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 96 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 97 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 98 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 99 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 100 #define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 101 #define E1000_DEV_ID_PCH_ADP_I219_LM16 0x1A1E 102 #define E1000_DEV_ID_PCH_ADP_I219_V16 0x1A1F 103 #define E1000_DEV_ID_PCH_ADP_I219_LM17 0x1A1C 104 #define E1000_DEV_ID_PCH_ADP_I219_V17 0x1A1D 105 106 #define E1000_REVISION_4 4 107 108 #define E1000_FUNC_1 1 109 110 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 111 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 112 113 enum e1000_mac_type { 114 e1000_82571, 115 e1000_82572, 116 e1000_82573, 117 e1000_82574, 118 e1000_82583, 119 e1000_80003es2lan, 120 e1000_ich8lan, 121 e1000_ich9lan, 122 e1000_ich10lan, 123 e1000_pchlan, 124 e1000_pch2lan, 125 e1000_pch_lpt, 126 e1000_pch_spt, 127 e1000_pch_cnp, 128 e1000_pch_tgp, 129 e1000_pch_adp, 130 }; 131 132 enum e1000_media_type { 133 e1000_media_type_unknown = 0, 134 e1000_media_type_copper = 1, 135 e1000_media_type_fiber = 2, 136 e1000_media_type_internal_serdes = 3, 137 e1000_num_media_types 138 }; 139 140 enum e1000_nvm_type { 141 e1000_nvm_unknown = 0, 142 e1000_nvm_none, 143 e1000_nvm_eeprom_spi, 144 e1000_nvm_flash_hw, 145 e1000_nvm_flash_sw 146 }; 147 148 enum e1000_nvm_override { 149 e1000_nvm_override_none = 0, 150 e1000_nvm_override_spi_small, 151 e1000_nvm_override_spi_large 152 }; 153 154 enum e1000_phy_type { 155 e1000_phy_unknown = 0, 156 e1000_phy_none, 157 e1000_phy_m88, 158 e1000_phy_igp, 159 e1000_phy_igp_2, 160 e1000_phy_gg82563, 161 e1000_phy_igp_3, 162 e1000_phy_ife, 163 e1000_phy_bm, 164 e1000_phy_82578, 165 e1000_phy_82577, 166 e1000_phy_82579, 167 e1000_phy_i217, 168 }; 169 170 enum e1000_bus_width { 171 e1000_bus_width_unknown = 0, 172 e1000_bus_width_pcie_x1, 173 e1000_bus_width_pcie_x2, 174 e1000_bus_width_pcie_x4 = 4, 175 e1000_bus_width_pcie_x8 = 8, 176 e1000_bus_width_32, 177 e1000_bus_width_64, 178 e1000_bus_width_reserved 179 }; 180 181 enum e1000_1000t_rx_status { 182 e1000_1000t_rx_status_not_ok = 0, 183 e1000_1000t_rx_status_ok, 184 e1000_1000t_rx_status_undefined = 0xFF 185 }; 186 187 enum e1000_rev_polarity { 188 e1000_rev_polarity_normal = 0, 189 e1000_rev_polarity_reversed, 190 e1000_rev_polarity_undefined = 0xFF 191 }; 192 193 enum e1000_fc_mode { 194 e1000_fc_none = 0, 195 e1000_fc_rx_pause, 196 e1000_fc_tx_pause, 197 e1000_fc_full, 198 e1000_fc_default = 0xFF 199 }; 200 201 enum e1000_ms_type { 202 e1000_ms_hw_default = 0, 203 e1000_ms_force_master, 204 e1000_ms_force_slave, 205 e1000_ms_auto 206 }; 207 208 enum e1000_smart_speed { 209 e1000_smart_speed_default = 0, 210 e1000_smart_speed_on, 211 e1000_smart_speed_off 212 }; 213 214 enum e1000_serdes_link_state { 215 e1000_serdes_link_down = 0, 216 e1000_serdes_link_autoneg_progress, 217 e1000_serdes_link_autoneg_complete, 218 e1000_serdes_link_forced_up 219 }; 220 221 /* Receive Descriptor - Extended */ 222 union e1000_rx_desc_extended { 223 struct { 224 __le64 buffer_addr; 225 __le64 reserved; 226 } read; 227 struct { 228 struct { 229 __le32 mrq; /* Multiple Rx Queues */ 230 union { 231 __le32 rss; /* RSS Hash */ 232 struct { 233 __le16 ip_id; /* IP id */ 234 __le16 csum; /* Packet Checksum */ 235 } csum_ip; 236 } hi_dword; 237 } lower; 238 struct { 239 __le32 status_error; /* ext status/error */ 240 __le16 length; 241 __le16 vlan; /* VLAN tag */ 242 } upper; 243 } wb; /* writeback */ 244 }; 245 246 #define MAX_PS_BUFFERS 4 247 248 /* Number of packet split data buffers (not including the header buffer) */ 249 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 250 251 /* Receive Descriptor - Packet Split */ 252 union e1000_rx_desc_packet_split { 253 struct { 254 /* one buffer for protocol header(s), three data buffers */ 255 __le64 buffer_addr[MAX_PS_BUFFERS]; 256 } read; 257 struct { 258 struct { 259 __le32 mrq; /* Multiple Rx Queues */ 260 union { 261 __le32 rss; /* RSS Hash */ 262 struct { 263 __le16 ip_id; /* IP id */ 264 __le16 csum; /* Packet Checksum */ 265 } csum_ip; 266 } hi_dword; 267 } lower; 268 struct { 269 __le32 status_error; /* ext status/error */ 270 __le16 length0; /* length of buffer 0 */ 271 __le16 vlan; /* VLAN tag */ 272 } middle; 273 struct { 274 __le16 header_status; 275 /* length of buffers 1-3 */ 276 __le16 length[PS_PAGE_BUFFERS]; 277 } upper; 278 __le64 reserved; 279 } wb; /* writeback */ 280 }; 281 282 /* Transmit Descriptor */ 283 struct e1000_tx_desc { 284 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 285 union { 286 __le32 data; 287 struct { 288 __le16 length; /* Data buffer length */ 289 u8 cso; /* Checksum offset */ 290 u8 cmd; /* Descriptor control */ 291 } flags; 292 } lower; 293 union { 294 __le32 data; 295 struct { 296 u8 status; /* Descriptor status */ 297 u8 css; /* Checksum start */ 298 __le16 special; 299 } fields; 300 } upper; 301 }; 302 303 /* Offload Context Descriptor */ 304 struct e1000_context_desc { 305 union { 306 __le32 ip_config; 307 struct { 308 u8 ipcss; /* IP checksum start */ 309 u8 ipcso; /* IP checksum offset */ 310 __le16 ipcse; /* IP checksum end */ 311 } ip_fields; 312 } lower_setup; 313 union { 314 __le32 tcp_config; 315 struct { 316 u8 tucss; /* TCP checksum start */ 317 u8 tucso; /* TCP checksum offset */ 318 __le16 tucse; /* TCP checksum end */ 319 } tcp_fields; 320 } upper_setup; 321 __le32 cmd_and_length; 322 union { 323 __le32 data; 324 struct { 325 u8 status; /* Descriptor status */ 326 u8 hdr_len; /* Header length */ 327 __le16 mss; /* Maximum segment size */ 328 } fields; 329 } tcp_seg_setup; 330 }; 331 332 /* Offload data descriptor */ 333 struct e1000_data_desc { 334 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 335 union { 336 __le32 data; 337 struct { 338 __le16 length; /* Data buffer length */ 339 u8 typ_len_ext; 340 u8 cmd; 341 } flags; 342 } lower; 343 union { 344 __le32 data; 345 struct { 346 u8 status; /* Descriptor status */ 347 u8 popts; /* Packet Options */ 348 __le16 special; 349 } fields; 350 } upper; 351 }; 352 353 /* Statistics counters collected by the MAC */ 354 struct e1000_hw_stats { 355 u64 crcerrs; 356 u64 algnerrc; 357 u64 symerrs; 358 u64 rxerrc; 359 u64 mpc; 360 u64 scc; 361 u64 ecol; 362 u64 mcc; 363 u64 latecol; 364 u64 colc; 365 u64 dc; 366 u64 tncrs; 367 u64 sec; 368 u64 cexterr; 369 u64 rlec; 370 u64 xonrxc; 371 u64 xontxc; 372 u64 xoffrxc; 373 u64 xofftxc; 374 u64 fcruc; 375 u64 prc64; 376 u64 prc127; 377 u64 prc255; 378 u64 prc511; 379 u64 prc1023; 380 u64 prc1522; 381 u64 gprc; 382 u64 bprc; 383 u64 mprc; 384 u64 gptc; 385 u64 gorc; 386 u64 gotc; 387 u64 rnbc; 388 u64 ruc; 389 u64 rfc; 390 u64 roc; 391 u64 rjc; 392 u64 mgprc; 393 u64 mgpdc; 394 u64 mgptc; 395 u64 tor; 396 u64 tot; 397 u64 tpr; 398 u64 tpt; 399 u64 ptc64; 400 u64 ptc127; 401 u64 ptc255; 402 u64 ptc511; 403 u64 ptc1023; 404 u64 ptc1522; 405 u64 mptc; 406 u64 bptc; 407 u64 tsctc; 408 u64 tsctfc; 409 u64 iac; 410 u64 icrxptc; 411 u64 icrxatc; 412 u64 ictxptc; 413 u64 ictxatc; 414 u64 ictxqec; 415 u64 ictxqmtc; 416 u64 icrxdmtc; 417 u64 icrxoc; 418 }; 419 420 struct e1000_phy_stats { 421 u32 idle_errors; 422 u32 receive_errors; 423 }; 424 425 struct e1000_host_mng_dhcp_cookie { 426 u32 signature; 427 u8 status; 428 u8 reserved0; 429 u16 vlan_id; 430 u32 reserved1; 431 u16 reserved2; 432 u8 reserved3; 433 u8 checksum; 434 }; 435 436 /* Host Interface "Rev 1" */ 437 struct e1000_host_command_header { 438 u8 command_id; 439 u8 command_length; 440 u8 command_options; 441 u8 checksum; 442 }; 443 444 #define E1000_HI_MAX_DATA_LENGTH 252 445 struct e1000_host_command_info { 446 struct e1000_host_command_header command_header; 447 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 448 }; 449 450 /* Host Interface "Rev 2" */ 451 struct e1000_host_mng_command_header { 452 u8 command_id; 453 u8 checksum; 454 u16 reserved1; 455 u16 reserved2; 456 u16 command_length; 457 }; 458 459 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 460 struct e1000_host_mng_command_info { 461 struct e1000_host_mng_command_header command_header; 462 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 463 }; 464 465 #include "mac.h" 466 #include "phy.h" 467 #include "nvm.h" 468 #include "manage.h" 469 470 /* Function pointers for the MAC. */ 471 struct e1000_mac_operations { 472 s32 (*id_led_init)(struct e1000_hw *); 473 s32 (*blink_led)(struct e1000_hw *); 474 bool (*check_mng_mode)(struct e1000_hw *); 475 s32 (*check_for_link)(struct e1000_hw *); 476 s32 (*cleanup_led)(struct e1000_hw *); 477 void (*clear_hw_cntrs)(struct e1000_hw *); 478 void (*clear_vfta)(struct e1000_hw *); 479 s32 (*get_bus_info)(struct e1000_hw *); 480 void (*set_lan_id)(struct e1000_hw *); 481 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 482 s32 (*led_on)(struct e1000_hw *); 483 s32 (*led_off)(struct e1000_hw *); 484 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 485 s32 (*reset_hw)(struct e1000_hw *); 486 s32 (*init_hw)(struct e1000_hw *); 487 s32 (*setup_link)(struct e1000_hw *); 488 s32 (*setup_physical_interface)(struct e1000_hw *); 489 s32 (*setup_led)(struct e1000_hw *); 490 void (*write_vfta)(struct e1000_hw *, u32, u32); 491 void (*config_collision_dist)(struct e1000_hw *); 492 int (*rar_set)(struct e1000_hw *, u8 *, u32); 493 s32 (*read_mac_addr)(struct e1000_hw *); 494 u32 (*rar_get_count)(struct e1000_hw *); 495 }; 496 497 /* When to use various PHY register access functions: 498 * 499 * Func Caller 500 * Function Does Does When to use 501 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 502 * X_reg L,P,A n/a for simple PHY reg accesses 503 * X_reg_locked P,A L for multiple accesses of different regs 504 * on different pages 505 * X_reg_page A L,P for multiple accesses of different regs 506 * on the same page 507 * 508 * Where X=[read|write], L=locking, P=sets page, A=register access 509 * 510 */ 511 struct e1000_phy_operations { 512 s32 (*acquire)(struct e1000_hw *); 513 s32 (*cfg_on_link_up)(struct e1000_hw *); 514 s32 (*check_polarity)(struct e1000_hw *); 515 s32 (*check_reset_block)(struct e1000_hw *); 516 s32 (*commit)(struct e1000_hw *); 517 s32 (*force_speed_duplex)(struct e1000_hw *); 518 s32 (*get_cfg_done)(struct e1000_hw *hw); 519 s32 (*get_cable_length)(struct e1000_hw *); 520 s32 (*get_info)(struct e1000_hw *); 521 s32 (*set_page)(struct e1000_hw *, u16); 522 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 523 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 524 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 525 void (*release)(struct e1000_hw *); 526 s32 (*reset)(struct e1000_hw *); 527 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 528 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 529 s32 (*write_reg)(struct e1000_hw *, u32, u16); 530 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 531 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 532 void (*power_up)(struct e1000_hw *); 533 void (*power_down)(struct e1000_hw *); 534 }; 535 536 /* Function pointers for the NVM. */ 537 struct e1000_nvm_operations { 538 s32 (*acquire)(struct e1000_hw *); 539 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 540 void (*release)(struct e1000_hw *); 541 void (*reload)(struct e1000_hw *); 542 s32 (*update)(struct e1000_hw *); 543 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 544 s32 (*validate)(struct e1000_hw *); 545 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 546 }; 547 548 struct e1000_mac_info { 549 struct e1000_mac_operations ops; 550 u8 addr[ETH_ALEN]; 551 u8 perm_addr[ETH_ALEN]; 552 553 enum e1000_mac_type type; 554 555 u32 collision_delta; 556 u32 ledctl_default; 557 u32 ledctl_mode1; 558 u32 ledctl_mode2; 559 u32 mc_filter_type; 560 u32 tx_packet_delta; 561 u32 txcw; 562 563 u16 current_ifs_val; 564 u16 ifs_max_val; 565 u16 ifs_min_val; 566 u16 ifs_ratio; 567 u16 ifs_step_size; 568 u16 mta_reg_count; 569 570 /* Maximum size of the MTA register table in all supported adapters */ 571 #define MAX_MTA_REG 128 572 u32 mta_shadow[MAX_MTA_REG]; 573 u16 rar_entry_count; 574 575 u8 forced_speed_duplex; 576 577 bool adaptive_ifs; 578 bool has_fwsm; 579 bool arc_subsystem_valid; 580 bool autoneg; 581 bool autoneg_failed; 582 bool get_link_status; 583 bool in_ifs_mode; 584 bool serdes_has_link; 585 bool tx_pkt_filtering; 586 enum e1000_serdes_link_state serdes_link_state; 587 }; 588 589 struct e1000_phy_info { 590 struct e1000_phy_operations ops; 591 592 enum e1000_phy_type type; 593 594 enum e1000_1000t_rx_status local_rx; 595 enum e1000_1000t_rx_status remote_rx; 596 enum e1000_ms_type ms_type; 597 enum e1000_ms_type original_ms_type; 598 enum e1000_rev_polarity cable_polarity; 599 enum e1000_smart_speed smart_speed; 600 601 u32 addr; 602 u32 id; 603 u32 reset_delay_us; /* in usec */ 604 u32 revision; 605 606 enum e1000_media_type media_type; 607 608 u16 autoneg_advertised; 609 u16 autoneg_mask; 610 u16 cable_length; 611 u16 max_cable_length; 612 u16 min_cable_length; 613 614 u8 mdix; 615 616 bool disable_polarity_correction; 617 bool is_mdix; 618 bool polarity_correction; 619 bool speed_downgraded; 620 bool autoneg_wait_to_complete; 621 }; 622 623 struct e1000_nvm_info { 624 struct e1000_nvm_operations ops; 625 626 enum e1000_nvm_type type; 627 enum e1000_nvm_override override; 628 629 u32 flash_bank_size; 630 u32 flash_base_addr; 631 632 u16 word_size; 633 u16 delay_usec; 634 u16 address_bits; 635 u16 opcode_bits; 636 u16 page_size; 637 }; 638 639 struct e1000_bus_info { 640 enum e1000_bus_width width; 641 642 u16 func; 643 }; 644 645 struct e1000_fc_info { 646 u32 high_water; /* Flow control high-water mark */ 647 u32 low_water; /* Flow control low-water mark */ 648 u16 pause_time; /* Flow control pause timer */ 649 u16 refresh_time; /* Flow control refresh timer */ 650 bool send_xon; /* Flow control send XON */ 651 bool strict_ieee; /* Strict IEEE mode */ 652 enum e1000_fc_mode current_mode; /* FC mode in effect */ 653 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 654 }; 655 656 struct e1000_dev_spec_82571 { 657 bool laa_is_present; 658 u32 smb_counter; 659 }; 660 661 struct e1000_dev_spec_80003es2lan { 662 bool mdic_wa_enable; 663 }; 664 665 struct e1000_shadow_ram { 666 u16 value; 667 bool modified; 668 }; 669 670 #define E1000_ICH8_SHADOW_RAM_WORDS 2048 671 672 /* I218 PHY Ultra Low Power (ULP) states */ 673 enum e1000_ulp_state { 674 e1000_ulp_state_unknown, 675 e1000_ulp_state_off, 676 e1000_ulp_state_on, 677 }; 678 679 struct e1000_dev_spec_ich8lan { 680 bool kmrn_lock_loss_workaround_enabled; 681 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; 682 bool nvm_k1_enabled; 683 bool eee_disable; 684 u16 eee_lp_ability; 685 enum e1000_ulp_state ulp_state; 686 }; 687 688 struct e1000_hw { 689 struct e1000_adapter *adapter; 690 691 void __iomem *hw_addr; 692 void __iomem *flash_address; 693 694 struct e1000_mac_info mac; 695 struct e1000_fc_info fc; 696 struct e1000_phy_info phy; 697 struct e1000_nvm_info nvm; 698 struct e1000_bus_info bus; 699 struct e1000_host_mng_dhcp_cookie mng_cookie; 700 701 union { 702 struct e1000_dev_spec_82571 e82571; 703 struct e1000_dev_spec_80003es2lan e80003es2lan; 704 struct e1000_dev_spec_ich8lan ich8lan; 705 } dev_spec; 706 }; 707 708 #include "82571.h" 709 #include "80003es2lan.h" 710 #include "ich8lan.h" 711 712 #endif 713